39 Commits

Author SHA1 Message Date
Bejean Mosher
1d38f8e69f feat: Validate BMP headers to protect against LogoFAIL.
The SBL logo is verified as part of Stage2 verification, so untrusted
logos won't be parsed, but it's still good to prevent dereferencing BMP
header pointers that may fall outside of BMP file.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
2024-01-08 15:04:47 -07:00
Guo Dong
6570aa9037 Update FPDT Table
Update the FPDT header length to include the length
of boot records. This way we could easily get all the
boot records from dumped ACPI FPDT table.

Signed-off-by: Guo Dong <guo.dong@intel.com>
2023-10-12 08:35:13 -07:00
cshur
83e3f07c9d feat: Update # of X2Apic Processor Local APIC
Since # of PROCESSOR_LOCAL_APICs are
Madt Local Apic # is 1.
Madt X2 Local Apic # is 9.

Need to update # of structure type of X2Apic.

Signed-off-by: cshur <cs.hur@intel.com>
2023-09-05 15:48:55 -07:00
Guo Dong
2b8ca86087 feat: fix Klocwork issue (#1947)
Fix the issue - Uninitialized Variable ResetVectorTime

Signed-off-by: Guo Dong <guo.dong@intel.com>
2023-06-29 11:45:42 -07:00
Guo Dong
475ff9daca feat: Fix ACPI FPDT SBL boot performance (#1935)
In current code, BoardNotifyPhase() would update FPDT SBL performance
table in S3 path. It could cause S3 issue since PcdAcpiTablesRsdp is
not updated.
Move the FPDT related code to AcpiFpdt.c
Update FPDT SBL performance table in stage2 so that this table
could be updated for all payloads.

Signed-off-by: Guo Dong <guo.dong@intel.com>
2023-06-25 21:06:43 -07:00
Atharva Lele
1d2e75b5be fix: resolve FPDT related Klocwork issues
- Add a null check for Rsdp pointer before accessing it
- Initialize ResetVectorTime, Time to some value before using it
- Add debug print for success / failure

Signed-off-by: Atharva Lele <atharva.lele@intel.com>
2023-06-18 16:42:21 -07:00
koktong-ong
d7727bc60c fix: [Common] Fix KW issues (#1920)
Fixed Klocwork issues

Signed-off-by: Kobe <kok.tong.ong@intel.com>
2023-06-12 09:09:25 -04:00
Atharva Lele
3422681785 feat: add SBL boot performance data to FPDT (#1890)
Adds SBL boot performance data (Stage1 time, Stage 2 time, OsLoader time)
to the FPDT with type 0x3000 (Reserved for platform firmware Vendor usage)

Other fixes:
- Move logging of measure point 40F0 inside the condition for measured boot
- Add missing call to log measure point 40E0 used to log kernel setup print
  time

Signed-off-by: Atharva Lele <atharva.lele@intel.com>
2023-05-23 10:26:34 -07:00
Mike Crowe
990e3e81e6 Use LF line endings in the repository
Convert the line endings stored for all text files in the repository to
LF. The majority previously used DOS-style CRLF line endings. Add a
.gitattributes file to enforce this and treat certain extensions as
never being text files.

Update PatchCheck.py to insist on LF line endings rather than CRLF.
However, its other checks fail on this commit due to lots of
pre-existing complaints that it only notices because the line endings
have changed.

Silicon/QemuSocPkg/FspBin/Patches/0001-Build-QEMU-FSP-2.0-binaries.patch
needs to be treated as binary since it contains a mixture of line
endings.

This change has implications depending on the client platform you are
using the repository from:

* Windows

The usual configuration for Git on Windows means that text files will
be checked out to the work tree with DOS-style CRLF line endings. If
that's not the case then you can configure Git to do so for the entire
machine with:

 git config --global core.autocrlf true

or for just the repository with:

 git config core.autocrlf true

Line endings will be normalised to LF when they are committed to the
repository. If you commit a text file with only LF line endings then it
will be converted to CRLF line endings in your work tree.

* Linux, MacOS and other Unices

The usual configuration for Git on such platforms is to check files out
of the repository with LF line endings. This is probably the right thing
for you. In the unlikely even that you are using Git on Unix but editing
or compiling on Windows for some reason then you may need to tweak your
configuration to force the use of CRLF line endings as described above.

* General

For more information see
https://docs.github.com/en/get-started/getting-started-with-git/configuring-git-to-handle-line-endings .

Fixes: https://github.com/slimbootloader/slimbootloader/issues/1400
Signed-off-by: Mike Crowe <mac@mcrowe.com>
2021-11-10 12:46:42 -08:00
Maurice Ma
f67122518c SBL clean up to split core private data out
This patch moved SBL core private data strctures and definitions
into a private header file so that other packages cannot refer
to the private structures.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2021-11-04 10:49:49 -07:00
Maurice Ma
c62e24eb8c Add PCD to let platform control the ACPI processor ID base
This patch added PcdAcpiProcessorIdBase to allow platform to
customize the processor ID start base within MADT APIC entry.
Current EHL and TGL declared PR00 processor object in ACPI
with unique ID value 0, but other projects used vlaue 1
instead. This patch will help fix this issue.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2021-10-25 16:43:20 -07:00
Maurice Ma
41ccfcca7c Clean up release build debug output
Current SBL release debug output has more than what is expected.
This patch reset some of the debug message to proper level to limit
debug message for release build.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2021-04-04 07:59:03 -07:00
Maurice Ma
3b849acccf Allow platform to create ACPI table dynamically
This patch implemented a common method for platform to create ACPI
table dynamically. Platform can provide ACPI tempalte array through
PCD PcdAcpiTableTemplatePtr. If provided, ACPI core code will try to
call platform code to patch the table, and then install the table to
ACPI RSDT/XSDT.
It also added sample code implementation in QEMU to show case how to
do it from platform code.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2021-03-28 21:24:27 -07:00
Maurice Ma
bcfba7a847 Move X2APIC enabling to common function
This patch removed duplicated X2APIC enabling code. Instead, it
enables X2APIC in a common function. By doing so, the very first
waking up will be done in APIC mode. Afterwards, it will be using
X2APIC mode if enabled by PCD.
This patch also fixed an X2APIC ACPI MADT issue.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2021-02-20 06:52:08 -08:00
Maurice Ma
04b162e75e Add CPU X2APIC support
This patch added X2APIC support. It is to enable the case when
APIC ID is greater than 255. This patch only handle core wakeup
portion. Platform still needs to handle ACPI related changes for
X2APIC.

X2APIC lib is backward compatible with XAPIC lib. So there is no
need to use XAPIC lib anymore.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2021-02-12 17:20:57 -08:00
Maurice Ma
a85f327ad8 Enhance BGRT BMP support for logo display
BGRT can be used by bootloader to pass logo to OS. But BGRT can
only support 24bit or 32bit BMP format. If the bootloader uses
other bit format or indexed color format, the image has to be
converted before passing it to BGRT. This patch added support
to convert other BMP image format into 32bit format required by
BGRT.

This has been tested with Windows on Leafhill board. The SBL
logo was dispalyed properly while booting Windows.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2021-01-14 09:52:36 -08:00
Maurice Ma
6117ebaa7c Enable ACPI BGRT table support
This patch enabled ACPI BGRT support. It is used to pass splash
display information from bootloader to payload and OS.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2020-12-02 12:40:18 -08:00
Maurice Ma
bd07c6504c Add legacy EF segment memory config (#904)
Current SBL code will build pointers in E/F segment for ACPI
and SMBIOS table. On some platforms, E/F segment is not supported.
So a new configuration ENABLE_LEGACY_EF_SEG is added.  When
it is enabled, SBL will not use legacy E/F segment memory.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2020-11-22 21:06:38 -08:00
Aiden Park
eae81b7bc8 [X64] Support S3 resume on 64-bit build (#698)
This will support S3 resume path on X64 thru 16-bit waking vector.
- Port WakeUp code from EDKII
- Remove duplicated calls of FindS3Info from CpuInit
- Verified with Yocto on a WHL board
- TBD: 64-bit waking vector with supported OS

Signed-off-by: Aiden Park <aiden.park@intel.com>
2020-04-29 21:23:56 -07:00
Maurice Ma
762eee35b7 Common code change for QEMU x64 boot
This patch added additional changes for QEMU x64 boot.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2020-04-02 09:00:14 -07:00
Maurice Ma
72cb08ee7d Enable QEMU Stage1A boot in X64 mode (#621)
* [QEMU] Enable Stage1A boot in X64 mode

This patch added necessary changes to enable QEMU boot through
Stage1A in SBL X64 build.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>

* [QEMU] Enable QEMU Linux boot in X64 mode

This patch enabled SBL X64 boot for Linux. At this moment, since
FSP is still in 32 bit mode, it is required to thunk back into
32 bit mode to call FSP APIs.
It fixed #622.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2020-04-02 07:30:43 -07:00
Aiden Park
6bec45136f Make x64 buildable (#619)
* Add missing X64 MdePkg Library

This adds some missing Library from EDKII Stable201911.
- MdePkg/Library/BaseMemoryLibRepStr/X64
- MdePkg/Library/BaseSynchronizationLib/X64

Signed-off-by: Aiden Park <aiden.park@intel.com>

* Make X64 target buildable

This is just to build X64 target - Not functional.

Signed-off-by: Aiden Park <aiden.park@intel.com>
2020-04-02 07:28:14 -07:00
Aiden Park
3ec0361920 Fix pointer type cast errors from Visual Studio (#617)
Visual Studio reports more pointer type cast errors with 64-bit build.
This will cover the issue on the existing targets.

Signed-off-by: Aiden Park <aiden.park@intel.com>
2020-03-27 11:03:28 -07:00
Aiden Park
29446a1c2a Pointer type cast for both 32/64-bit operation (#615)
This patch allows both 32/64-bit addressing properly.
- Pointer type cast with UINTN
- Add missing EFIAPI for APIs

Signed-off-by: Aiden Park <aiden.park@intel.com>
2020-03-26 17:30:55 -07:00
Guo Dong
6476272fb5 Fix FPDT size issue
FPDT size should be FIRMWARE_PERFORMANCE_TABLE. And updated
this logic to correct the size and adjust next ACPI table
starting address.

Signed-off-by: Guo Dong <guo.dong@intel.com>
2020-02-05 13:55:44 -07:00