Currently SBL supports SMM REBASE based on configuration.
1) When payload doesn't support SMM, SBL need enable SMM rebase.
So SBL will rebase SMM to SMRAM and set SMRR to prevent SMRAM
access out of SMM and prevent payload SMM driver dispatch.
2) When payload support SMM, SBL need disable SMM rebase.
In this case SBL do nothing for SMM. Payload will do SMM
rebase.
In new UEFI payload (after stable branch 202311), SMM relocation
was removed CPU SMM driver. To work with new UEFI payload, SMM
relocation is expected in SBL, but SMRR should not be set so that
SMM drivers in UEFI payload could be dispatched into SMRAM.
This patch adds a new SMM rebase configuration that it rebase SMM
but it doesn't set SMRR.
Currently SBL supports rebase AUTO setting based on payload. This
patch also add auto support.
Signed-off-by: Guo Dong <guo.dong@intel.com>
IAS boot image format is deprecated; it is recommended to use container
boot image.
- Removed references,files related to IAS image.
- Replaced IAS image boot options with container type image.
Signed-off-by: Chirag Vijay Kolhe <chirag.vijay.kolhe@intel.com>
FSP 2.4 introduces the possibility of FSP built for x64 architecture.
This adds support for x64 FSP calling conventions based on the header x64
support attribute. Support for x64 FSP-T requires entering long mode
prior to FSP-T execution.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
FSP 2.4 with MultiPhase support expects FSP UPD buffer to stay accessible
after CallFspMemoryInit() returns, so FSP must be allocated from the heap
instead of stack.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Some silicon requires longer than provided for all APs to enter the wakeup
routine. This change makes this platform configurable. The default wait
time is none and can be increased for platforms with higher core count Si.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
When platform chooses BusScanTypeList for PCI enumeration, the BusLimit should be set to PCI_MAX_BUS.
The BusScanItems defines primary bus for PCie root port. If there is device attached to root port,
which will present on secondary bus, in the meantime the bus number is greater than Buslimit, this device
cannot be found from enumeration. Assign PCI_MAX_BUS to BusLimit to prevent this issue.
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
This commit adds support for PCIe resizable BARsupport.
The feature can be enabled by setting PcdResizableBarSupport
for the board build script and its disabled by default.
Signed-off-by: pastorcx <mariano-paulx.pastorcici@intel.com>
Adding new Board Config item REMAP_STAGE1B to control remapping Stage1B
into permanent memory after FSP-M. Decouple this from ENABLE_FAST_BOOT
and STAGE1B_XIP. This makes it simpler to enable this remap when the
slight performance boost may be needed, and leave it disabled by default.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
1) Some FSP 2.4 implementations are non-conforming and use FSPM_ARCH_UPD
instead of FSPM_ARCH2_UPD as indicated by the specification. Logic is
changed to check FSPM UPD header revision for structure version instead
of FSP spec revision.
2) MultiPhase FSP PhaseIndex is one-based so loop comparisons need to take
this into account. Side effect is that the last phase may be missed. No
current platform FSP is utilizing this.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
This will increase time of Board PostMemoryInit hook and TempRamExit,
but improve the performance of PostTempRamExit hook, PreSiliconInit hook
and FSP-S.
In total, the boot time can be reduced by ~20ms.
Signed-off-by: Yi Li <yi1.li@intel.com>
Registering logical root bridges with no devices can cause unexpected
behavior for platforms that use _PCI_ENUM_BUS_SCAN_TYPE = "range", since
all empty buses in the range will be compared against the resource
allocation table entries.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Not all root bridges have a physical device at dev 0 func 0 of the root
bus, and this requirement prevents some platforms from being fully scanned.
From this point, PciEnumerationLib doesn't access the root bridge
configuration space at all, so this is an unnecessary check.
Instead, root bus scanning will continue without dev 0 func 0 present. If
no devices are found on the root bus, scanning will continue to the next
root bridge.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
The SBL logo is verified as part of Stage2 verification, so untrusted
logos won't be parsed, but it's still good to prevent dereferencing BMP
header pointers that may fall outside of BMP file.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Update the FPDT header length to include the length
of boot records. This way we could easily get all the
boot records from dumped ACPI FPDT table.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Since # of PROCESSOR_LOCAL_APICs are
Madt Local Apic # is 1.
Madt X2 Local Apic # is 9.
Need to update # of structure type of X2Apic.
Signed-off-by: cshur <cs.hur@intel.com>
In current code, BoardNotifyPhase() would update FPDT SBL performance
table in S3 path. It could cause S3 issue since PcdAcpiTablesRsdp is
not updated.
Move the FPDT related code to AcpiFpdt.c
Update FPDT SBL performance table in stage2 so that this table
could be updated for all payloads.
Signed-off-by: Guo Dong <guo.dong@intel.com>
- Add a null check for Rsdp pointer before accessing it
- Initialize ResetVectorTime, Time to some value before using it
- Add debug print for success / failure
Signed-off-by: Atharva Lele <atharva.lele@intel.com>
FSP 2.4 adds a requirement for Bootloader to respond to FSP Variable
requests in a way that is similar to UEFI variable services. This
implementation adds support for using the updated SBL VariableLib so that
the FspVariableServicesLib wrapper is no longer needed.
Additionally, support for Multi-Phase mem and SI init is added. FSP 2.4
introduces the mandatory MultiPhaseMemInit call, and makes the
MultiPhaseSiInit call mandatory where it was previously optional.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
