80 Commits

Author SHA1 Message Date
Guo Dong
317c43386c Update SMM rebase support
Currently SBL supports SMM REBASE based on configuration.
1) When payload doesn't support SMM, SBL need enable SMM rebase.
   So SBL will rebase SMM to SMRAM and set SMRR to prevent SMRAM
   access out of SMM and prevent payload SMM driver dispatch.
2) When payload support SMM, SBL need disable SMM rebase.
   In this case SBL do nothing for SMM. Payload will do SMM
   rebase.

In new UEFI payload (after stable branch 202311), SMM relocation
was removed CPU SMM driver. To work with new UEFI payload, SMM
relocation is expected in SBL, but SMRR should not be set so that
SMM drivers in UEFI payload could be dispatched into SMRAM.

This patch adds a new SMM rebase configuration that it rebase SMM
but it doesn't set SMRR.
Currently SBL supports rebase AUTO setting based on payload. This
patch also add auto support.

Signed-off-by: Guo Dong <guo.dong@intel.com>
2025-04-14 21:36:08 -07:00
Guo Dong
475ff9daca feat: Fix ACPI FPDT SBL boot performance (#1935)
In current code, BoardNotifyPhase() would update FPDT SBL performance
table in S3 path. It could cause S3 issue since PcdAcpiTablesRsdp is
not updated.
Move the FPDT related code to AcpiFpdt.c
Update FPDT SBL performance table in stage2 so that this table
could be updated for all payloads.

Signed-off-by: Guo Dong <guo.dong@intel.com>
2023-06-25 21:06:43 -07:00
bejeanmo
a34e54e175 feat: [FSP2.4] Added FSP variable serivices, Multi Phase Mem and SI. (#1901)
FSP 2.4 adds a requirement for Bootloader to respond to FSP Variable
requests in a way that is similar to UEFI variable services. This
implementation adds support for using the updated SBL VariableLib so that
the FspVariableServicesLib wrapper is no longer needed.

Additionally, support for Multi-Phase mem and SI init is added. FSP 2.4
introduces the mandatory MultiPhaseMemInit call, and makes the
MultiPhaseSiInit call mandatory where it was previously optional.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
2023-05-24 14:36:35 -04:00
Atharva Lele
3422681785 feat: add SBL boot performance data to FPDT (#1890)
Adds SBL boot performance data (Stage1 time, Stage 2 time, OsLoader time)
to the FPDT with type 0x3000 (Reserved for platform firmware Vendor usage)

Other fixes:
- Move logging of measure point 40F0 inside the condition for measured boot
- Add missing call to log measure point 40E0 used to log kernel setup print
  time

Signed-off-by: Atharva Lele <atharva.lele@intel.com>
2023-05-23 10:26:34 -07:00
Sean McGinn
f9d614c09f Move MB/ACPI macros to BootloaderCommonLib
Move macros to BootloaderCommonLib as they
are now consumed by both SBL stages and payload

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-05-04 13:25:07 -07:00
koktong-ong
c7fbc86eb3 Added FspNonVolatileStorageHob2 support in FspSupportLib (#1850)
Support FSP 2.3 FSP_NON_VOLATILE_STORAGE_HOB2

Signed-off-by: Kobe <kok.tong.ong@intel.com>
2023-03-24 08:33:10 -04:00
Sean McGinn
38a3c2e799 Consider Simultaneous SG02 Corruptions in BP0 and BP1 for Resiliency
Before this change, whenever SG02 is corrupted
in both BP0 and BP1, SBL will continuously loop
trying to recover BP0 via BP1 and vice versa

This change makes it so that, if a failure is
detected on a recovery flow, the CPU halts

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2022-10-18 14:49:32 -07:00
Sean McGinn
22cfbc8803 Rename GetStateMachine to GetFwuStateMachine
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2022-09-06 09:38:52 -07:00
Sean McGinn
3a6aa45abb Create FirmwareUpdateStatus header and FirmwareResiliencyLib
library

Migrates FW resiliency APIs of Stage1B.c to
FirmwareResiliencyLib
Migrates FW update status types from FirmwareUpdateLib.h and
BootloaderCommonLib.h to FirmwareUpdateStatus.h

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2022-09-06 09:38:52 -07:00
Sean McGinn
7625d492e2 Move TcoTimerLib, TopSwapLib, and WatchDogTimerLib header files
Move files to CommonSocPkg from BootloaderCorePkg

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2022-08-07 17:21:33 -07:00
Sean McGinn
092ce7fcf8 Amend WatchDogTimerLib for SBL resiliency
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2022-08-07 17:21:33 -07:00
Sean McGinn
1da1768bc1 Create TopSwapLib for SBL resiliency
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2022-08-07 17:21:33 -07:00
Sean McGinn
5087516d68 Create TcoTimerLib for SBL resiliency
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2022-08-07 17:21:33 -07:00
Maurice Ma
6eb006beea Add MP service for payload
This patch adds a MpServiceLib for payload so that a payload
can utilize this library to run tasks on specified processor.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2022-03-02 09:04:08 -08:00
Sai T
b9422c7969 Enhance Smbios Init Lib
This patch does the following updates to SmBiosInitLib:

  1. Provide AddSmbiosType() to add a SmBios Type header.
  2. Provide AddSmbiosString() to append strings to Type header.
  3. Move Finalize() to after 'PrePayloadLoading' board init phase.
     All Smbios related calls need to be done before this.
  4. Modified TGL project to adjust to these changes.

Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
2021-11-16 12:35:12 -08:00
Mike Crowe
990e3e81e6 Use LF line endings in the repository
Convert the line endings stored for all text files in the repository to
LF. The majority previously used DOS-style CRLF line endings. Add a
.gitattributes file to enforce this and treat certain extensions as
never being text files.

Update PatchCheck.py to insist on LF line endings rather than CRLF.
However, its other checks fail on this commit due to lots of
pre-existing complaints that it only notices because the line endings
have changed.

Silicon/QemuSocPkg/FspBin/Patches/0001-Build-QEMU-FSP-2.0-binaries.patch
needs to be treated as binary since it contains a mixture of line
endings.

This change has implications depending on the client platform you are
using the repository from:

* Windows

The usual configuration for Git on Windows means that text files will
be checked out to the work tree with DOS-style CRLF line endings. If
that's not the case then you can configure Git to do so for the entire
machine with:

 git config --global core.autocrlf true

or for just the repository with:

 git config core.autocrlf true

Line endings will be normalised to LF when they are committed to the
repository. If you commit a text file with only LF line endings then it
will be converted to CRLF line endings in your work tree.

* Linux, MacOS and other Unices

The usual configuration for Git on such platforms is to check files out
of the repository with LF line endings. This is probably the right thing
for you. In the unlikely even that you are using Git on Unix but editing
or compiling on Windows for some reason then you may need to tweak your
configuration to force the use of CRLF line endings as described above.

* General

For more information see
https://docs.github.com/en/get-started/getting-started-with-git/configuring-git-to-handle-line-endings .

Fixes: https://github.com/slimbootloader/slimbootloader/issues/1400
Signed-off-by: Mike Crowe <mac@mcrowe.com>
2021-11-10 12:46:42 -08:00
Guo Dong
5d0195f962 Build SMM HOBs for universal payload
UEFI payload built from open sourced EDK2 supports SMM variable now.
So build the required HOBs to work with EDK2.
This patch just changed the common SBL code, so there is no platform
change required.
This patch also added a PCD PcdBuildSmmHobs for old SMM HOBs and new
SMM HOBs. Late old SMM HOBs might be dropped.

Signed-off-by: Guo Dong <guo.dong@intel.com>
2021-11-04 11:50:00 -07:00
Maurice Ma
f67122518c SBL clean up to split core private data out
This patch moved SBL core private data strctures and definitions
into a private header file so that other packages cannot refer
to the private structures.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2021-11-04 10:49:49 -07:00
Maurice Ma
a815fd2e72 Add GetSocSku/SetSocSku API
This patch added API to Get/SetSocSku. In current code, SBL always
read the PCI register to determine the SKU. It is not efficient.
Since it is used a lot, it is better to have software API to get
this info through a software only method.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2021-11-02 10:55:04 -07:00
Maurice Ma
4936832cde [TGL] Add SOC specific memory info
This patch updated the memory info for TGL platform using the SOC
specific memory map registers.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2021-10-26 14:32:20 -07:00
Maurice Ma
78cdcd8732 Provide API inferfaces to get/set platform memory info
In order to report memory size info in SMBIOS table, it is required
to know the full system memory. However, all info can only be passed
through FSP HOB, and it cannot easily identify the top of low/high
memory. The patch added core API GetMemoryInfo/SetMemoryInfo so that
platform can provide required memory info for core. By default, it
uses FSP hobs to guess these info. But platform can update it with
more accurate info during PostMemoryInit phase.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2021-10-26 14:32:20 -07:00
Maurice Ma
ae8a416449 Add SMBIOS type 19 - memory array mapped address
This patch reworked the previous reverted commit. The UEFI payload
debug version assertion was resolved. Checked in Windows, the SMBIOS
info looks good.

Current UEFI payload showed 0 KB RAM size in setup screen because
of missing SMBIOS memory type information. This patch added SMBIOS
type 19 to provide memory array mapped address information. With
this change, UEFI setup screen can show correct memory size.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2021-10-25 16:45:00 -07:00
Aiden Park
18d16d44ff Profile Max Used Heap size at runtime
This records the maximum usage of heap at runtime. The Stage1/2 heap
sometimes reaches OUT OF RESOURCE even if it looks there is enough
usable space in the heap. This is because AllocateTemporaryMemory()
sometime exceeds the heap boundary. ex) IppCryptoLib
This would help identify proper heap size required in each stages.

Signed-off-by: Aiden Park <aiden.park@intel.com>
2021-10-25 09:48:22 -07:00
Maurice Ma
449309ff75 Revert "Add SMBIOS type 19 - memory array mapped address"
This reverts commit b87d67c1fc.
In the testing, it caused debug UEFI payload assertion issue.
Roll it back for now.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2021-10-21 19:27:19 -07:00
Maurice Ma
b87d67c1fc Add SMBIOS type 19 - memory array mapped address
Current UEFI payload showed 0 KB RAM size in setup screen because
of missing SMBIOS memory type information. This patch added SMBIOS
type 19 to provide memory array mapped address information. With
this change, UEFI setup screen can show correct memory size.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
2021-10-21 18:09:04 -07:00