Added fips_selftest run before any crypto use in Stage1A.
updated IppCrypto to 1.0.1 version
Signed-off-by: Antara Borwankar <antara.borwankar@intel.com>
IAS boot image format is deprecated; it is recommended to use container
boot image.
- Removed references,files related to IAS image.
- Replaced IAS image boot options with container type image.
Signed-off-by: Chirag Vijay Kolhe <chirag.vijay.kolhe@intel.com>
FSP 2.4 introduces the possibility of FSP built for x64 architecture.
This adds support for x64 FSP calling conventions based on the header x64
support attribute. Support for x64 FSP-T requires entering long mode
prior to FSP-T execution.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Some silicon requires longer than provided for all APs to enter the wakeup
routine. This change makes this platform configurable. The default wait
time is none and can be increased for platforms with higher core count Si.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
This commit adds support for PCIe resizable BARsupport.
The feature can be enabled by setting PcdResizableBarSupport
for the board build script and its disabled by default.
Signed-off-by: pastorcx <mariano-paulx.pastorcici@intel.com>
Adding new Board Config item REMAP_STAGE1B to control remapping Stage1B
into permanent memory after FSP-M. Decouple this from ENABLE_FAST_BOOT
and STAGE1B_XIP. This makes it simpler to enable this remap when the
slight performance boost may be needed, and leave it disabled by default.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
The SBL logo is verified as part of Stage2 verification, so untrusted
logos won't be parsed, but it's still good to prevent dereferencing BMP
header pointers that may fall outside of BMP file.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
The FSP may request for a reboot when some features are
enable/disable. The SiliconInit FW update is one case for the
"FSP requested boot". Without the patch, SBL has no way to
get the notification from CallFspNotifyPhase.
The patch introduces a feature, PcdEnableFwuNotify,
to allow SBL to keep BoardNotifyPhase during firmware update.
On EHL, the feature can be enabled by "disable BIOS Lock".
Verify: EHL-CRB
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
EHL FSP does not send EOP (End Of Post) message at the
Ready to Boot. The patch adds support for SBL to send
the EOP during Ready to Boot.
Verified: EHL CRB
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Added Null template for FusaConfigLib. Platforms supporting FuSa should
follow this template for enabling FuSa configuration prior to FSP-M and
FSP-S.
Added ADL/RPL CfgData fields for FuSa according to SBL FuSa software
requirements, and dlt file for enabling FuSa and related configuration.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
* OsLoader: set default status to EFI_UNSUPPORTED when parsing a boot image
This was set to EFI_SUCCESS which resulted in ParseBootImages() returning
EFI_SUCCESS even if the boot image was not a container or a component.
Thus, the boot would continue and fail at a later stage due to the
LoadedImage structure not being populated correctly.
Setting it to EFI_UNSUPPORTED will result in ParseBootImages() returning
EFI_UNSUPPORTED if a non-supported boot image is provided and OsLoader
will attempt to boot the next entry in the boot options list.
Signed-off-by: Atharva Lele <atharva.lele@intel.com>
* Remove PcdContainerBootEnabled PCD
SBL requires boot images to be packaged as a container or a component
Signed-off-by: Atharva Lele <atharva.lele@intel.com>
---------
Signed-off-by: Atharva Lele <atharva.lele@intel.com>
PR #1760 mistakenly included a debug change to increase the default debug
print level. Reverting that one change.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Currently, users are able to update the uCode component
with a new binary that uses a different slot size than
the existing binary. If these slot sizes do not line up,
there is potential to trigger recovery (if enabled) or
brick the system. This change disallows updates where
these slot sizes do not line up.
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
PcdTccEnabled was declared as a FeaturePcd which evaluates to a code symbol
and can't be used in a #if. From the preprocessor perspective it is always
undefined. Changed this pcd to a FixedPcd instead.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
library
Migrates FW resiliency APIs of Stage1B.c to
FirmwareResiliencyLib
Migrates FW update status types from FirmwareUpdateLib.h and
BootloaderCommonLib.h to FirmwareUpdateStatus.h
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
This patch added support to get csme boot time performance
data and display it in perf command and also before booting
to linux.
Introduced a board config option BOOT_PERFORMANCE_MASK to control
PcdBootPerformanceMask, BIT 2 now enables printing CSME boot
performance data.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Different use case might want to have a different CPU order.
e.g. P-core first or E-core first.
This patch adds an option to help user sort CPU.
platform could add "self.CPU_SORT_METHOD = value" to
BoardConfig.py to override the default value.
Signed-off-by: Guo Dong <guo.dong@intel.com>
