diff --git a/Silicon/CommonSocPkg/Include/Library/SpiFlashLib.h b/Silicon/CommonSocPkg/Include/Library/SpiFlashLib.h
new file mode 100644
index 00000000..d3597e11
--- /dev/null
+++ b/Silicon/CommonSocPkg/Include/Library/SpiFlashLib.h
@@ -0,0 +1,202 @@
+/** @file
+ PCH SPI Common Driver implements the SPI Host Controller Compatibility Interface.
+
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __SPI_FLASH_LIB_H__
+#define __SPI_FLASH_LIB_H__
+
+#include
+
+/**
+ Read SFDP data from the flash part.
+
+ @param[in] ComponentNumber The Component Number for chip select
+ @param[in] ByteCount Number of bytes in SFDP data portion of the SPI cycle, the max number is 64
+ @param[out] SfdpData The Pointer to caller-allocated buffer containing the SFDP data received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashReadSfdp (
+ IN UINT8 ComponentNumber,
+ IN UINT32 ByteCount,
+ OUT UINT8 *SfdpData
+ );
+
+/**
+ Read Jedec Id from the flash part.
+
+ @param[in] ComponentNumber The Component Number for chip select
+ @param[in] ByteCount Number of bytes in JedecId data portion of the SPI cycle, the data size is 3 typically
+ @param[out] JedecId The Pointer to caller-allocated buffer containing JEDEC ID received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashReadJedecId (
+ IN UINT8 ComponentNumber,
+ IN UINT32 ByteCount,
+ OUT UINT8 *JedecId
+ );
+
+/**
+ Write the status register in the flash part.
+
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[in] StatusValue The Pointer to caller-allocated buffer containing the value of Status register writing
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashWriteStatus (
+ IN UINT32 ByteCount,
+ IN UINT8 *StatusValue
+ );
+
+/**
+ Read status register in the flash part.
+
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[out] StatusValue The Pointer to caller-allocated buffer containing the value of Status register received.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashReadStatus (
+ IN UINT32 ByteCount,
+ OUT UINT8 *StatusValue
+ );
+
+/**
+ Read SC Soft Strap Values
+
+ @param[in] SoftStrapAddr SC Soft Strap address offset from FPSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing SC Soft Strap Value.
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiReadPchSoftStrap (
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT UINT8 *SoftStrapValue
+ );
+
+
+/**
+ Read data from the flash part.
+
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[out] Buffer The Pointer to caller-allocated buffer containing the dada received.
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashRead (
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Erase some area on the flash part.
+
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashErase (
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount
+ );
+
+/**
+ Write data to the flash part.
+
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[in] Buffer Pointer to caller-allocated buffer containing the data sent during the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashWrite (
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ IN UINT8 *Buffer
+ );
+
+/**
+ Initialize an SPI library.
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @exception EFI_UNSUPPORTED The SC is not supported by this module
+**/
+EFI_STATUS
+SpiConstructor (
+ VOID
+ );
+
+/**
+ Get the SPI region base and size, based on the enum type
+
+ @param[in] FlashRegionType The Flash Region type for for the base address which is listed in the Descriptor.
+ @param[out] BaseAddress The Flash Linear Address for the Region 'n' Base
+ @param[out] RegionSize The size for the Region 'n'
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_INVALID_PARAMETER Invalid region type given
+ @retval EFI_DEVICE_ERROR The region is not used
+**/
+EFI_STATUS
+EFIAPI
+SpiGetRegionAddress (
+ IN FLASH_REGION_TYPE FlashRegionType,
+ OUT UINT32 *BaseAddress, OPTIONAL
+ OUT UINT32 *RegionSize OPTIONAL
+ );
+
+#endif
+
diff --git a/Silicon/CommonSocPkg/Library/SpiFlashLib/RegsSpi.h b/Silicon/CommonSocPkg/Library/SpiFlashLib/RegsSpi.h
new file mode 100644
index 00000000..a536d83d
--- /dev/null
+++ b/Silicon/CommonSocPkg/Library/SpiFlashLib/RegsSpi.h
@@ -0,0 +1,403 @@
+/** @file
+ Register names for SPI device.
+
+ Conventions:
+
+ - Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values of bits within the registers
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ - In general, SC registers are denoted by "_SC_" in register names
+ - Registers / bits that are different between SC generations are denoted by
+ "_SC__" in register/bit names.
+ - Registers / bits that are different between SKUs are denoted by "_"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a SC generation will be just named
+ as "_SC_" without inserted.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _REGS_SPI_H_
+#define _REGS_SPI_H_
+
+
+
+#define R_SPI_ID 0x00 ///< Identifiers
+#define R_SPI_COMMAND 0x04 ///< Command
+#define R_SPI_BASE 0x10 ///< 32-bit Memory Base Address Register
+#define B_SPI_BASE_BAR 0xFFFFF000 ///< MEMBAR
+#define B_SPI_BAR0_MASK 0x0FFF
+#define B_SPI_BASE_PREF BIT3 ///< Prefetchable
+#define B_SPI_BASE_MEMI BIT0 ///< Memory Space Indicator
+#define R_SPI_BDE 0xD8 ///< BIOS Decode Enable
+#define R_SPI_BCR 0xDC ///< BIOS Control Register
+#define S_SPI_BCR 4
+#define B_SPI_BC_OSFH BIT9 ///< OS Function Hide
+#define B_SPI_BC_BILD BIT7
+#define B_SPI_BC_BBS BIT6 ///< Boot BIOS strap
+#define N_SPI_BC_BBS 6
+#define V_SPI_BC_BBS_SPI 0 ///< Boot BIOS strapped to SPI
+#define V_SPI_BC_BBS_LPC 1 ///< Boot BIOS strapped to LPC
+#define B_SPI_BCR_SMM_BWP BIT5 ///< Enable InSMM.STS
+#define B_SPI_BCR_SRC (BIT3 | BIT2) ///< SPI Read Configuration (SRC)
+#define V_SPI_BCR_SRC_PREF_EN_CACHE_EN 0x08 ///< Prefetch Enable, Cache Enable
+#define V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS 0x04 ///< Prefetch Disable, Cache Disable
+#define V_SPI_BCR_SRC_PREF_DIS_CACHE_EN 0x00 ///< Prefetch Disable, Cache Enable
+#define N_SPI_BCR_SYNC_SS 8
+#define B_SPI_BCR_SYNC_SS BIT8
+#define B_SPI_BCR_BILD BIT7
+#define B_SPI_BCR_EISS BIT5 ///< Enable InSMM.STS
+#define B_SPI_BCR_BLE BIT1 ///< Lock Enable (LE)
+#define B_SPI_BCR_BIOSWE BIT0 ///< Write Protect Disable (WPD)
+#define N_SPI_BCR_BLE 1
+#define N_SPI_BCR_BIOSWE 0
+
+///
+/// SPI Host Interface Registers
+#define R_SPI_BFPR 0x00 ///< BIOS Flash Primary Region Register (32bits)
+#define B_SPI_BFPR_PRL 0x7FFF0000 ///< BIOS Flash Primary Region Limit
+#define B_SPI_BFPR_PRB 0x7FFF ///< BIOS Flash Primary Region Base
+#define R_SPI_HSFS 0x04 ///< Hardware Sequencing Flash Status and Control Register(32bits)
+#define B_SPI_HSFS_FSMIE BIT31 ///< Flash SPI SMI# Enable
+#define B_SPI_HSFS_FDBC_MASK 0x3F000000 ///< Flash Data Byte Count ( <= 64), Count = (Value in this field) + 1.
+#define N_SPI_HSFS_FDBC 24
+#define B_SPI_HSFS_CYCLE_MASK 0x001E0000 ///< Flash Cycle.
+#define N_SPI_HSFS_CYCLE 17
+#define V_SPI_HSFS_CYCLE_READ 0 ///< Flash Cycle Read
+#define V_SPI_HSFS_CYCLE_WRITE 2 ///< Flash Cycle Write
+#define V_SPI_HSFS_CYCLE_4K_ERASE 3 ///< Flash Cycle 4K Block Erase
+#define V_SPI_HSFS_CYCLE_64K_ERASE 4 ///< Flash Cycle 64K Sector Erase
+#define V_SPI_HSFS_CYCLE_READ_SFDP 5 ///< Flash Cycle Read SFDP
+#define V_SPI_HSFS_CYCLE_READ_JEDEC_ID 6 ///< Flash Cycle Read JEDEC ID
+#define V_SPI_HSFS_CYCLE_WRITE_STATUS 7 ///< Flash Cycle Write Status
+#define V_SPI_HSFS_CYCLE_READ_STATUS 8 ///< Flash Cycle Read Status
+#define B_SPI_HSFS_CYCLE_FGO BIT16 ///< Flash Cycle Go.
+#define B_SPI_HSFS_FLOCKDN BIT15 ///< Flash Configuration Lock-Down
+#define B_SPI_HSFS_FDV BIT14 ///< Flash Descriptor Valid
+#define B_SPI_HSFS_FDOPSS BIT13 ///< Flash Descriptor Override Pin-Strap Status
+#define B_SPI_HSFS_SCIP BIT5 ///< SPI Cycle in Progress
+#define B_SPI_HSFS_BERASE_MASK (BIT4 | BIT3) ///< Block/Sector Erase Size
+#define V_SPI_HSFS_BERASE_256B 0//0x00 ///< Block/Sector = 256 Bytes
+#define V_SPI_HSFS_BERASE_4K 1//0x01 ///< Block/Sector = 4K Bytes
+#define V_SPI_HSFS_BERASE_8K 2//0x10 ///< Block/Sector = 8K Bytes
+#define V_SPI_HSFS_BERASE_64K 3//0x11 ///< Block/Sector = 64K Bytes
+#define B_SPI_HSFS_AEL BIT2 ///< Access Error Log
+#define B_SPI_HSFS_FCERR BIT1 ///< Flash Cycle Error
+#define B_SPI_HSFS_FDONE BIT0 ///< Flash Cycle Done
+
+#define R_SPI_HSFC 0x06 ///< Hardware Sequencing Flash Control Register (16bits)
+#define B_SPI_HSFC_FSMIE BIT15 ///< Flash SPI SMI# Enable
+#define B_SPI_HSFC_FDBC_MASK 0x3F00 ///< Flash Data Byte Count ( <= 64), Count = (Value in this field) + 1.
+#define B_SPI_HSFC_FCYCLE_MASK 0x001E ///< Flash Cycle.
+#define V_SPI_HSFC_FCYCLE_READ 0 ///< Flash Cycle Read
+#define V_SPI_HSFC_FCYCLE_WRITE 2 ///< Flash Cycle Write
+#define V_SPI_HSFC_FCYCLE_ERASE 3 ///< Flash Cycle 4k Block Erase
+#define V_SPI_HSFC_FCYCLE_SERASE 4 ///< Flash Cycle 64k Sector Erase
+#define B_SPI_HSFC_FCYCLE_FGO BIT0 ///< Flash Cycle Go.
+
+#define R_SPI_FADDR 0x08 ///< SPI Flash Address
+#define B_SPI_FADDR_MASK 0x07FFFFFF ///< SPI Flash Address Mask (0~26bit)
+
+#define R_SPI_DLOCK 0x0C ///< Discrete Lock Bits
+#define B_SPI_DLOCK_PR0LOCKDN BIT8 ///< PR0LOCKDN
+
+#define R_SPI_FDATA00 0x10 ///< SPI Data 00 (32 bits)
+#define R_SPI_FDATA01 0x14 ///< SPI Data 01
+#define R_SPI_FDATA02 0x18 ///< SPI Data 02
+#define R_SPI_FDATA03 0x1C ///< SPI Data 03
+#define R_SPI_FDATA04 0x20 ///< SPI Data 04
+#define R_SPI_FDATA05 0x24 ///< SPI Data 05
+#define R_SPI_FDATA06 0x28 ///< SPI Data 06
+#define R_SPI_FDATA07 0x2C ///< SPI Data 07
+#define R_SPI_FDATA08 0x30 ///< SPI Data 08
+#define R_SPI_FDATA09 0x34 ///< SPI Data 09
+#define R_SPI_FDATA10 0x38 ///< SPI Data 10
+#define R_SPI_FDATA11 0x3C ///< SPI Data 11
+#define R_SPI_FDATA12 0x40 ///< SPI Data 12
+#define R_SPI_FDATA13 0x44 ///< SPI Data 13
+#define R_SPI_FDATA14 0x48 ///< SPI Data 14
+#define R_SPI_FDATA15 0x4C ///< SPI Data 15
+
+#define R_SPI_FRAP 0x50 ///< SPI Flash Regions Access Permissions Register
+#define B_SPI_FRAP_BMWAG_MASK 0xFF000000 ///< Master Write Access Grant MASK
+#define B_SPI_FRAP_BMRAG_MASK 0x00FF0000 ///< Master Read Access Grant Grant MASK
+#define B_SPI_FRAP_BRWA_MASK 0x0000FF00 ///< BIOS Region Write Access MASK
+#define B_SPI_FRAP_BRWA_PLATFORM BIT12 //< Region write access for Region4 PlatformData
+#define B_SPI_FRAP_BRWA_GBE BIT11 //< Region write access for Region3 GbE
+#define B_SPI_FRAP_BRWA_SEC BIT10 ///< Region Write Access for Region2 SEC
+#define B_SPI_FRAP_BRWA_BIOS BIT9 ///< Region Write Access for Region1 BIOS
+#define B_SPI_FRAP_BRWA_FLASHD BIT8 ///< Region Write Access for Region0 Flash Descriptor
+#define B_SPI_FRAP_BRRA_MASK 0x000000FF ///< BIOS Region Read Access MASK
+#define B_SPI_FRAP_BRRA_PLATFORM BIT4 ///< Region read access for Region4 PlatformData
+#define B_SPI_FRAP_BRRA_GBE BIT3 ///< Region read access for Region3 GbE
+#define B_SPI_FRAP_BRRA_SEC BIT2 ///< Region Read Access for Region2 SEC
+#define B_SPI_FRAP_BRRA_BIOS BIT1 ///< Region Read Access for Region1 BIOS
+#define B_SPI_FRAP_BRRA_FLASHD BIT0 ///< Region Read Access for Region0 Flash Descriptor
+
+#define V_SPI_FLREG_DISABLED 0x00007FFF ////< Region Base all 1's and Limits all 0's indicates the region is disabled.
+
+#define R_SPI_FREG0_FLASHD 0x54 ///< Flash Region 0 (Flash Descriptor) (32bits)
+#define B_SPI_FREG0_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define N_SPI_FREG0_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12]
+#define B_SPI_FREG0_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+#define N_SPI_FREG0_BASE 12 ///< Bit 14:0 identifies address bits [26:2]
+
+#define R_SPI_FREG1_BIOS 0x58 ///< Flash Region 1 (BIOS) (32bits)
+#define B_SPI_FREG1_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define N_SPI_FREG1_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12]
+#define B_SPI_FREG1_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+#define N_SPI_FREG1_BASE 12 ///< Bit 14:0 identifies address bits [26:2]
+
+#define R_SPI_FREG2_SEC 0x5C ///< Flash Region 2 (SEC) (32bits)
+#define B_SPI_FREG2_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define N_SPI_FREG2_LIMIT 4 //< Bit 30:16 identifies address bits [26:12]
+#define B_SPI_FREG2_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+#define N_SPI_FREG2_BASE 12 //< Bit 14:0 identifies address bits [26:2]
+
+#define R_SPI_FREG3_GBE 0x60 //< Flash Region 3(GbE)(32bits)
+#define B_SPI_FREG3_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define N_SPI_FREG3_LIMIT 4 //< Bit 30:16 identifies address bits [26:12]
+#define B_SPI_FREG3_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+#define N_SPI_FREG3_BASE 12 //< Bit 14:0 identifies address bits [26:2]
+
+#define R_SPI_FREG4_PLATFORM_DATA 0x64 ///< Flash Region 4 (Platform Data) (32bits)
+#define B_SPI_FREG4_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define N_SPI_FREG4_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12]
+#define B_SPI_FREG4_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+#define N_SPI_FREG4_BASE 12 ///< Bit 14:0 identifies address bits [26:2]
+
+#define R_SPI_FREG5_DEVICE_EXPANSION_1 0x68 ///< Flash Region 5 (Device Expansion) (32bits)
+#define B_SPI_FREG5_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define B_SPI_FREG5_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+
+#define R_SPI_FREG6_SECONDARY_BIOS 0x6C ///< Flash Region 6 (Secondary BIOS) (32bits)
+#define B_SPI_FREG6_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define B_SPI_FREG6_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+
+#define R_SPI_FREG7_UCODE_PATCH 0x70 ///< Flash Region 7 (uCode Patch) (32bits)
+#define B_SPI_FREG7_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define B_SPI_FREG7_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+
+#define R_SPI_FREG8_EC 0x74 ///< Flash Region 8 (Embedded Controller) (32bits)
+#define B_SPI_FREG8_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define B_SPI_FREG8_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+
+#define R_SPI_FREG9_DEVICE_EXPANSION_2 0x78 ///< Flash Region 9 (Device Expansion 2) (32bits)
+#define B_SPI_FREG9_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define B_SPI_FREG9_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+
+#define R_SPI_FREG10_IE_ENGINE 0x7c ///< Flash Region 10 (IE Innovation Engine) (32bits)
+#define B_SPI_FREG10_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define B_SPI_FREG10_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+
+#define R_SPI_FREG11_10_GBE_A 0x80 ///< Flash Region 11 (10 GBE A) (32bits)
+#define B_SPI_FREG11_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define B_SPI_FREG11_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+
+#define S_SPI_FREGX 4 ///< Size of Flash Region register
+#define B_SPI_FREGX_LIMIT_MASK 0x7FFF0000 ///< Flash Region Limit [30:16] represents [26:12], [11:0] are assumed to be FFFh
+#define N_SPI_FREGX_LIMIT 16 ///< Region limit bit position
+#define N_SPI_FREGX_LIMIT_REPR 12 ///< Region limit bit represents position
+#define B_SPI_FREGX_BASE_MASK 0x00007FFF ///< Flash Region Base, [14:0] represents [26:12]
+#define N_SPI_FREGX_BASE 0 ///< Region base bit position
+#define N_SPI_FREGX_BASE_REPR 12 ///< Region base bit represents position
+
+#define R_SPI_PR0 0x84 ///< Protected Region 0 Register
+#define B_SPI_PR0_WPE BIT31 ///< Write Protection Enable
+#define B_SPI_PR0_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask, [30:16] here represents upper limit of address [26:12]
+#define B_SPI_PR0_RPE BIT15 ///< Read Protection Enable
+#define B_SPI_PR0_PRB_MASK 0x00007FFF ///< Protected Range Base Mask, [14:0] here represents base limit of address [26:12]
+
+#define R_SPI_PR1 0x88 ///< Protected Region 1 Register
+#define B_SPI_PR1_WPE BIT31 ///< Write Protection Enable
+#define B_SPI_PR1_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask
+#define B_SPI_PR1_RPE BIT15 ///< Read Protection Enable
+#define B_SPI_PR1_PRB_MASK 0x00007FFF ///< Protected Range Base Mask
+
+#define R_SPI_PR2 0x8C ///< Protected Region 2 Register
+#define B_SPI_PR2_WPE BIT31 ///< Write Protection Enable
+#define B_SPI_PR2_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask
+#define B_SPI_PR2_RPE BIT15 ///< Read Protection Enable
+#define B_SPI_PR2_PRB_MASK 0x00007FFF ///< Protected Range Base Mask
+
+#define R_SPI_PR3 0x90 ///< Protected Region 3 Register
+#define B_SPI_PR3_WPE BIT31 ///< Write Protection Enable
+#define B_SPI_PR3_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask
+#define B_SPI_PR3_RPE BIT15 ///< Read Protection Enable
+#define B_SPI_PR3_PRB_MASK 0x00007FFF ///< Protected Range Base Mask
+
+#define R_SPI_PR4 0x94 ///< Protected Region 4 Register
+#define B_SPI_PR4_WPE BIT31 ///< Write Protection Enable
+#define B_SPI_PR4_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask
+#define B_SPI_PR4_RPE BIT15 ///< Read Protection Enable
+#define B_SPI_PR4_PRB_MASK 0x00007FFF ///< Protected Range Base Mask
+
+#define S_SPI_PRX 4 ///< Protected Region X Register size
+#define B_SPI_PRX_WPE BIT31 ///< Write Protection Enable
+#define B_SPI_PRX_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask, [30:16] here represents upper limit of address [26:12]
+#define N_SPI_PRX_PRL 16 ///< Protected Range Limit bit position
+#define B_SPI_PRX_RPE BIT15 ///< Read Protection Enable
+#define B_SPI_PRX_PRB_MASK 0x00007FFF ///< Protected Range Base Mask, [14:0] here represents base limit of address [26:12]
+#define N_SPI_PRX_PRB 0 ///< Protected Range Base bit position
+
+#define R_SPI_GPR0 0x98 ///< Global Protected Range 0 Register
+#define B_SPI_GPR0_WPE BIT31 ///< Write Protection Enable
+#define B_SPI_GPR0_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask
+#define B_SPI_GPR0_RPE BIT15 ///< Read Protection Enable
+#define B_SPI_GPR0_PRB_MASK 0x00007FFF ///< Protected Range Base Mask
+
+#define R_SPI_SSFCS 0xA0 ///< Software Sequencing Flash Control Status Register
+#define B_SPI_SSFCS_SCF_MASK (BIT26 | BIT25 | BIT24) ///< SPI Cycle Frequency
+#define V_SPI_SSFCS_SCF_48MHZ 2 ///< SPI Cycle Frequency = 48MHz
+#define V_SPI_SSFCS_SCF_30MHZ 4 ///< SPI Cycle Frequency = 30MHz
+#define V_SPI_SSFCS_SCF_17MHZ 6 ///< SPI Cycle Frequency = 17MHz
+
+#define B_SPI_SSFCS_SME BIT23 ///< SPI SMI# Enable
+#define B_SPI_SSFCS_DC BIT22 ///< SPI Data Cycle
+#define B_SPI_SSFCS_DBC_MASK 0x3F0000 ///< SPI Data Byte Count (value here + 1 = count)
+#define B_SPI_SSFCS_COP 0x7000 ///< Cycle Opcode Pointer
+#define B_SPI_SSFCS_SPOP BIT11 ///< Sequence Prefix Opcode Pointer
+#define B_SPI_SSFCS_ACS BIT10 ///< Atomic Cycle Sequence
+#define B_SPI_SSFCS_SCGO BIT9 ///< SPI Cycle Go
+#define B_SPI_SSFCS_FRS BIT7 ///< Fast Read Supported
+#define B_SPI_SSFCS_DOFRS BIT6 ///< Dual Output Fast Read Supported
+#define B_SPI_SSFCS_AEL BIT4 ///< Access Error Log
+#define B_SPI_SSFCS_FCERR BIT3 ///< Flash Cycle Error
+#define B_SPI_SSFCS_CDS BIT2 ///< Cycle Done Status
+#define B_SPI_SSFCS_SCIP BIT0 ///< SPI Cycle in Progress
+
+#define R_SPI_PREOP 0xA4 ///< Prefix Opcode Configuration Register (16 bits)
+#define B_SPI_PREOP1_MASK 0xFF00 ///< Prefix Opcode 1 Mask
+#define B_SPI_PREOP0_MASK 0x00FF ///< Prefix Opcode 0 Mask
+
+#define R_SPI_OPTYPE 0xA6 ///< Opcode Type Configuration
+#define B_SPI_OPTYPE7_MASK (BIT15 | BIT14) ///< Opcode Type 7 Mask
+#define B_SPI_OPTYPE6_MASK (BIT13 | BIT12) ///< Opcode Type 6 Mask
+#define B_SPI_OPTYPE5_MASK (BIT11 | BIT10) ///< Opcode Type 5 Mask
+#define B_SPI_OPTYPE4_MASK (BIT9 | BIT8) ///< Opcode Type 4 Mask
+#define B_SPI_OPTYPE3_MASK (BIT7 | BIT6) ///< Opcode Type 3 Mask
+#define B_SPI_OPTYPE2_MASK (BIT5 | BIT4) ///< Opcode Type 2 Mask
+#define B_SPI_OPTYPE1_MASK (BIT3 | BIT2) ///< Opcode Type 1 Mask
+#define B_SPI_OPTYPE0_MASK (BIT1 | BIT0) ///< Opcode Type 0 Mask
+#define V_SPI_OPTYPE_RDNOADDR 0x00 ///< Read cycle type without address
+#define V_SPI_OPTYPE_WRNOADDR 0x01 ///< Write cycle type without address
+#define V_SPI_OPTYPE_RDADDR 0x02 ///< Address required; Read cycle type
+#define V_SPI_OPTYPE_WRADDR 0x03 ///< Address required; Write cycle type
+
+#define R_SPI_OPMENU0 0xA8 ///< Opcode Menu Configuration 0 (32bits)
+#define R_SPI_OPMENU1 0xAC ///< Opcode Menu Configuration 1 (32bits)
+
+#define R_SPI_SFRAP 0xB0 ///< Secondary Flash Region Access Permissions (32 bits)
+
+#define R_SPI_FDOC 0xB4 ///< Flash Descriptor Observability Control Register (32 bits)
+#define B_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) ///< Flash Descriptor Section Select
+#define V_SPI_FDOC_FDSS_FSDM 0x0000 ///< Flash Signature and Descriptor Map
+#define V_SPI_FDOC_FDSS_COMP 0x1000 ///< Component
+#define V_SPI_FDOC_FDSS_REGN 0x2000 ///< Region
+#define V_SPI_FDOC_FDSS_MSTR 0x3000 ///< Master
+#define V_SPI_FDOC_FDSS_STRP 0x4000 ///< Soft Straps
+#define B_SPI_FDOC_FDSI_MASK 0x0FFC ///< Flash Descriptor Section Index
+
+#define R_SPI_FDOD 0xB8 ///< Flash Descriptor Observability Data Register (32 bits)
+
+#define R_SPI_AFC 0xC0 ///< Additional Flash Control Register
+#define B_SPI_AFC_RRWSP 0xFE ///< Reserved RW Scratch Pad bit [7:1]
+#define B_SPI_AFC_SPFP BIT0 ///< Stop Prefetch on Flush Pending
+
+#define R_SPI_LVSCC 0xC4 ///
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _SC_SPI_COMMON_LIB_H_
+#define _SC_SPI_COMMON_LIB_H_
+
+///
+/// Maximum time allowed while waiting the SPI cycle to complete
+/// Wait Time = 6 seconds = 6000000 microseconds
+/// Wait Period = 10 microseconds
+///
+#define WAIT_TIME 6000000 ///< Wait Time = 6 seconds = 6000000 microseconds
+#define WAIT_PERIOD 10 ///< Wait Period = 10 microseconds
+
+
+
+
+///
+/// Flash cycle Type
+///
+typedef enum {
+ FlashCycleRead,
+ FlashCycleWrite,
+ FlashCycleErase,
+ FlashCycleReadSfdp,
+ FlashCycleReadJedecId,
+ FlashCycleWriteStatus,
+ FlashCycleReadStatus,
+ FlashCycleMax
+} FLASH_CYCLE_TYPE;
+
+///
+/// Flash Component Number
+///
+typedef enum {
+ FlashComponent0,
+ FlashComponent1,
+ FlashComponentMax
+} FLASH_COMPONENT_NUM;
+
+///
+/// Private data structure definitions for the driver
+///
+#define SC_SPI_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('P', 'S', 'P', 'I')
+
+typedef struct {
+ UINTN Signature;
+ EFI_HANDLE Handle;
+ UINT32 AcpiTmrReg;
+ UINTN PchSpiBase;
+ UINT16 RegionPermission;
+ UINT32 SfdpVscc0Value;
+ UINT32 SfdpVscc1Value;
+ UINT32 StrapBaseAddress;
+ UINT8 NumberOfComponents;
+ UINT32 Component1StartAddr;
+} SPI_INSTANCE;
+
+///
+/// Function prototypes used by the SPI protocol.
+///
+
+/**
+ Initialize an SPI protocol instance.
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @retval EFI_UNSUPPORTED The SC is not supported by this module
+**/
+EFI_STATUS
+SpiConstructor (
+ VOID
+ );
+
+/**
+ This function is a hook for Spi to disable BIOS Write Protect
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in SMM phase
+**/
+EFI_STATUS
+EFIAPI
+DisableBiosWriteProtect (
+ VOID
+ );
+
+/**
+ This function is a hook for Spi to enable BIOS Write Protect
+**/
+VOID
+EFIAPI
+EnableBiosWriteProtect (
+ VOID
+ );
+
+/**
+ Acquire SC spi mmio address.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval UINT32 return SPI MMIO address
+**/
+UINT32
+AcquireSpiBar0 (
+ VOID
+ );
+
+/**
+ Release SC spi mmio address.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+**/
+VOID
+ReleaseSpiBar0 (
+ VOID
+ );
+
+/**
+ This function sends the programmed SPI command to the slave device.
+
+ @param[in] SpiRegionType The SPI Region type for flash cycle which is listed in the Descriptor
+ @param[in] FlashCycleType The Flash SPI cycle type list in HSFC (Hardware Sequencing Flash Control Register) register
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[in,out] Buffer Pointer to caller-allocated buffer containing the data received or sent during the SPI cycle.
+
+ @retval EFI_SUCCESS SPI command completes successfully.
+ @retval EFI_DEVICE_ERROR Device error, the command aborts abnormally.
+ @retval EFI_ACCESS_DENIED Some unrecognized command encountered in hardware sequencing mode
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+**/
+EFI_STATUS
+SendSpiCmd (
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN FLASH_CYCLE_TYPE FlashCycleType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ IN OUT UINT8 *Buffer
+ );
+
+/**
+ Wait execution cycle to complete on the SPI interface.
+
+ @param[in] PchSpiBar0 Spi MMIO base address
+ @param[in] ErrorCheck TRUE if the SpiCycle needs to do the error check
+
+ @retval TRUE SPI cycle completed on the interface.
+ @retval FALSE Time out while waiting the SPI cycle to complete.
+ It's not safe to program the next command on the SPI interface.
+**/
+BOOLEAN
+WaitForSpiCycleComplete (
+ IN UINT32 PchSpiBar0,
+ IN BOOLEAN ErrorCheck
+ );
+
+#endif
diff --git a/Silicon/CommonSocPkg/Library/SpiFlashLib/SpiFlashLib.c b/Silicon/CommonSocPkg/Library/SpiFlashLib/SpiFlashLib.c
new file mode 100644
index 00000000..3cb328f3
--- /dev/null
+++ b/Silicon/CommonSocPkg/Library/SpiFlashLib/SpiFlashLib.c
@@ -0,0 +1,997 @@
+/** @file
+ SC SPI Common Driver implements the SPI Host Controller Compatibility Interface.
+
+ Copyright (c) 2017-2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "ScSpiCommon.h"
+#include "RegsSpi.h"
+
+const SPI_FLASH_SERVICE mSpiFlashService = {
+ .Header.Signature = SPI_FLASH_SERVICE_SIGNATURE,
+ .Header.Version = SPI_FLASH_SERVICE_VERSION,
+ .SpiInit = SpiConstructor,
+ .SpiRead = SpiFlashRead,
+ .SpiWrite = SpiFlashWrite,
+ .SpiErase = SpiFlashErase,
+ .SpiGetRegion = SpiGetRegionAddress
+};
+
+/**
+ Get SPI Instance from library global data..
+
+ @retval SpiInstance Return SPI instance
+**/
+SPI_INSTANCE *
+GetSpiInstance (
+ VOID
+)
+{
+ EFI_STATUS Status;
+ SPI_INSTANCE *SpiInstance;
+
+ Status = GetLibraryData (PcdGet8(PcdSpiFlashLibId), (VOID **)&SpiInstance);
+ if (Status == EFI_NOT_FOUND) {
+ SpiInstance = AllocatePool (sizeof(SPI_INSTANCE));
+ ZeroMem (SpiInstance, sizeof(SPI_INSTANCE));
+ Status = SetLibraryData (PcdGet8(PcdSpiFlashLibId), SpiInstance, sizeof(SPI_INSTANCE));
+ }
+
+ if (EFI_ERROR(Status)) {
+ SpiInstance = NULL;
+ }
+
+ return SpiInstance;
+}
+
+
+
+/**
+ Initialize an SPI library.
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @exception EFI_UNSUPPORTED The SC is not supported by this module
+**/
+EFI_STATUS
+EFIAPI
+SpiConstructor (
+ VOID
+ )
+{
+ UINT32 ScSpiBar0;
+ UINT8 Comp0Density;
+ SPI_INSTANCE *SpiInstance;
+ EFI_STATUS Status;
+
+ //
+ // Initialize the SPI instance
+ //
+ SpiInstance = GetSpiInstance();
+ ASSERT (SpiInstance != NULL);
+ if (SpiInstance->Signature == SC_SPI_PRIVATE_DATA_SIGNATURE) {
+ Status = RegisterService ((VOID *)&mSpiFlashService);
+ return Status;
+ }
+ DEBUG ((DEBUG_INFO, "SpiInstance = %08X\n", SpiInstance));
+
+ SpiInstance->Signature = SC_SPI_PRIVATE_DATA_SIGNATURE;
+ SpiInstance->Handle = NULL;
+
+ SpiInstance->PchSpiBase = GetDeviceAddr (OsBootDeviceSpi, 0);
+ SpiInstance->PchSpiBase = TO_MM_PCI_ADDRESS (SpiInstance->PchSpiBase);
+ DEBUG ((DEBUG_INFO, "PchSpiBase at 0x%x\n", SpiInstance->PchSpiBase));
+
+ ScSpiBar0 = MmioRead32 (SpiInstance->PchSpiBase + PCI_BASE_ADDRESSREG_OFFSET) & 0xFFFFF000;
+ if (ScSpiBar0 == 0) {
+ ASSERT (FALSE);
+ }
+
+ if ((MmioRead32 (ScSpiBar0 + R_SPI_HSFS) & B_SPI_HSFS_FDV) == 0) {
+ DEBUG ((DEBUG_ERROR, "ERROR : SPI Flash descriptor invalid, cannot use Hardware Sequencing registers!\n"));
+ ASSERT (FALSE);
+ }
+ MmioOr32 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
+ SpiInstance->RegionPermission = MmioRead16 (ScSpiBar0 + R_SPI_FRAP);
+ SpiInstance->SfdpVscc0Value = MmioRead32 (ScSpiBar0 + R_SPI_LVSCC);
+ SpiInstance->SfdpVscc1Value = MmioRead32 (ScSpiBar0 + R_SPI_UVSCC);
+
+ ///
+ /// Select to Flash Map 0 Register to get the number of flash Component
+ ///
+ MmioAndThenOr32 (
+ ScSpiBar0 + R_SPI_FDOC,
+ (UINT32) (~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)),
+ (UINT32) (V_SPI_FDOC_FDSS_FSDM | R_SPI_FDBAR_FLASH_MAP0)
+ );
+
+ ///
+ /// Copy Zero based Number Of Components
+ ///
+ SpiInstance->NumberOfComponents = (UINT8) ((MmioRead16 (ScSpiBar0 + R_SPI_FDOD) & B_SPI_FDBAR_NC) >> N_SPI_FDBAR_NC);
+
+ MmioAndThenOr32 (
+ ScSpiBar0 + R_SPI_FDOC,
+ (UINT32) (~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)),
+ (UINT32) (V_SPI_FDOC_FDSS_COMP | R_SPI_FCBA_FLCOMP)
+ );
+
+ ///
+ /// Copy Component 0 Density
+ ///
+ Comp0Density = (UINT8) MmioRead32 (ScSpiBar0 + R_SPI_FDOD) & B_SPI_FLCOMP_COMP1_MASK;
+ SpiInstance->Component1StartAddr = (UINT32) (SIZE_512KB << Comp0Density);
+
+ ///
+ /// Select FLASH_MAP1 to get Flash SC Strap Base Address
+ ///
+ MmioAndThenOr32 (
+ (ScSpiBar0 + R_SPI_FDOC),
+ (UINT32) (~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)),
+ (UINT32) (V_SPI_FDOC_FDSS_FSDM | R_SPI_FDBAR_FLASH_MAP1)
+ );
+
+ SpiInstance->StrapBaseAddress = MmioRead32 (ScSpiBar0 + R_SPI_FDOD) & B_SPI_FDBAR_FPSBA;
+
+ ///
+ /// Align FPSBA with address bits for the SC Strap portion of flash descriptor
+ ///
+ SpiInstance->StrapBaseAddress &= B_SPI_FDBAR_FPSBA;
+
+ Status = RegisterService ((VOID *)&mSpiFlashService);
+
+ return Status;
+}
+
+
+/**
+ Read data from the flash part.
+
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[out] Buffer The Pointer to caller-allocated buffer containing the data received.
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashRead (
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+
+ ///
+ /// Sends the command to the SPI interface to execute.
+ ///
+ Status = SendSpiCmd (
+ FlashRegionType,
+ FlashCycleRead,
+ Address,
+ ByteCount,
+ Buffer
+ );
+ return Status;
+}
+
+/**
+ Write data to the flash part.
+
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[in] Buffer Pointer to caller-allocated buffer containing the data sent during the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashWrite (
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ IN UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+
+ ///
+ /// Sends the command to the SPI interface to execute.
+ ///
+ Status = SendSpiCmd (
+ FlashRegionType,
+ FlashCycleWrite,
+ Address,
+ ByteCount,
+ Buffer
+ );
+ return Status;
+}
+
+/**
+ Erase some area on the flash part.
+
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashErase (
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount
+ )
+{
+ EFI_STATUS Status;
+
+ ///
+ /// Sends the command to the SPI interface to execute.
+ ///
+ Status = SendSpiCmd (
+ FlashRegionType,
+ FlashCycleErase,
+ Address,
+ ByteCount,
+ NULL
+ );
+ return Status;
+}
+
+/**
+ Read SFDP data from the flash part.
+
+ @param[in] ComponentNumber The Component Number for chip select
+ @param[in] ByteCount Number of bytes in SFDP data portion of the SPI cycle, the max number is 64
+ @param[out] SfdpData The Pointer to caller-allocated buffer containing the SFDP data received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashReadSfdp (
+ IN UINT8 ComponentNumber,
+ IN UINT32 ByteCount,
+ OUT UINT8 *SfdpData
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Address;
+ SPI_INSTANCE *SpiInstance;
+
+ SpiInstance = GetSpiInstance();
+ Status = EFI_SUCCESS;
+
+ if ((ByteCount > 64) || (ComponentNumber > SpiInstance->NumberOfComponents)) {
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Address = 0;
+ if (ComponentNumber == FlashComponent1) {
+ Address = SpiInstance->Component1StartAddr;
+ }
+ ///
+ /// Sends the command to the SPI interface to execute.
+ ///
+ Status = SendSpiCmd (
+ 0,
+ FlashCycleReadSfdp,
+ Address,
+ ByteCount,
+ SfdpData
+ );
+ return Status;
+}
+
+/**
+ Read Jedec Id from the flash part.
+
+ @param[in] ComponentNumber The Component Number for chip select
+ @param[in] ByteCount Number of bytes in JedecId data portion of the SPI cycle, the data size is 3 typically
+ @param[out] JedecId The Pointer to caller-allocated buffer containing JEDEC ID received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashReadJedecId (
+ IN UINT8 ComponentNumber,
+ IN UINT32 ByteCount,
+ OUT UINT8 *JedecId
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Address;
+ SPI_INSTANCE *SpiInstance;
+
+ SpiInstance = GetSpiInstance();
+ Status = EFI_SUCCESS;
+
+ if (ComponentNumber > SpiInstance->NumberOfComponents) {
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Address = 0;
+ if (ComponentNumber == FlashComponent1) {
+ Address = SpiInstance->Component1StartAddr;
+ }
+
+ ///
+ /// Sends the command to the SPI interface to execute.
+ ///
+ Status = SendSpiCmd (
+ 0,
+ FlashCycleReadJedecId,
+ Address,
+ ByteCount,
+ JedecId
+ );
+ return Status;
+}
+
+/**
+ Write the status register in the flash part.
+
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[in] StatusValue The Pointer to caller-allocated buffer containing the value of Status register writing
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashWriteStatus (
+ IN UINT32 ByteCount,
+ IN UINT8 *StatusValue
+ )
+{
+ EFI_STATUS Status;
+
+ ///
+ /// Sends the command to the SPI interface to execute.
+ ///
+ Status = SendSpiCmd (
+ 0,
+ FlashCycleWriteStatus,
+ 0,
+ ByteCount,
+ StatusValue
+ );
+ return Status;
+}
+
+/**
+ Read status register in the flash part.
+
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[out] StatusValue The Pointer to caller-allocated buffer containing the value of Status register received.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashReadStatus (
+ IN UINT32 ByteCount,
+ OUT UINT8 *StatusValue
+ )
+{
+ EFI_STATUS Status;
+
+ ///
+ /// Sends the command to the SPI interface to execute.
+ ///
+ Status = SendSpiCmd (
+ 0,
+ FlashCycleReadStatus,
+ 0,
+ ByteCount,
+ StatusValue
+ );
+ return Status;
+}
+
+/**
+ Read SC Soft Strap Values
+
+ @param[in] SoftStrapAddr SC Soft Strap address offset from FPSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing SC Soft Strap Value.
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiReadPchSoftStrap (
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT UINT8 *SoftStrapValue
+ )
+{
+ UINT32 StrapFlashAddr;
+ EFI_STATUS Status;
+ SPI_INSTANCE *SpiInstance;
+
+ SpiInstance = GetSpiInstance();
+ ASSERT (SpiInstance->StrapBaseAddress != 0);
+ ///
+ /// SC Strap Flash Address = FPSBA + RamAddr
+ ///
+ StrapFlashAddr = SpiInstance->StrapBaseAddress + SoftStrapAddr;
+
+ ///
+ /// Read SC Soft straps from using execute command
+ ///
+ Status = SendSpiCmd (
+ FlashRegionDescriptor,
+ FlashCycleRead,
+ StrapFlashAddr,
+ ByteCount,
+ SoftStrapValue
+ );
+ return Status;
+}
+
+/**
+ This function sends the programmed SPI command to the slave device.
+
+ @param[in] SpiRegionType The SPI Region type for flash cycle which is listed in the Descriptor
+ @param[in] FlashCycleType The Flash SPI cycle type list in HSFC (Hardware Sequencing Flash Control Register) register
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[in,out] Buffer Pointer to caller-allocated buffer containing the data received or sent during the SPI cycle.
+
+ @retval EFI_SUCCESS SPI command completes successfully.
+ @retval EFI_DEVICE_ERROR Device error, the command aborts abnormally.
+ @retval EFI_ACCESS_DENIED Some unrecognized command encountered in hardware sequencing mode
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+**/
+EFI_STATUS
+SendSpiCmd (
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN FLASH_CYCLE_TYPE FlashCycleType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ IN OUT UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Index;
+ UINTN SpiBaseAddress;
+ UINT32 ScSpiBar0;
+ UINT32 LimitAddress;
+ UINT32 HardwareSpiAddr;
+ UINT16 PermissionBit;
+ UINT32 SpiDataCount;
+ UINT32 FlashCycle;
+ UINT8 BiosCtlSave;
+ SPI_INSTANCE *SpiInstance;
+
+ SpiInstance = GetSpiInstance();
+ Status = EFI_SUCCESS;
+ ScSpiBar0 = AcquireSpiBar0 ();
+ SpiBaseAddress = SpiInstance->PchSpiBase;
+ BiosCtlSave = MmioRead8 (SpiBaseAddress + R_SPI_BCR) & B_SPI_BCR_SRC;
+
+ ///
+ /// If it's write cycle, disable Prefetching, Caching and disable BIOS Write Protect
+ ///
+ if ((FlashCycleType == FlashCycleWrite) ||
+ (FlashCycleType == FlashCycleErase)) {
+ Status = DisableBiosWriteProtect ();
+ if (EFI_ERROR (Status)) {
+ goto SendSpiCmdEnd;
+ }
+ MmioAndThenOr32 (
+ SpiBaseAddress + R_SPI_BCR,
+ (UINT32) (~B_SPI_BCR_SRC),
+ (UINT32) (V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS << B_SPI_BCR_SRC)
+ );
+ }
+ ///
+ /// Make sure it's safe to program the command.
+ ///
+ if (!WaitForSpiCycleComplete (ScSpiBar0, FALSE)) {
+ Status = EFI_DEVICE_ERROR;
+ goto SendSpiCmdEnd;
+ }
+
+ HardwareSpiAddr = Address;
+ if ((FlashCycleType == FlashCycleRead) ||
+ (FlashCycleType == FlashCycleWrite) ||
+ (FlashCycleType == FlashCycleErase)) {
+ switch (FlashRegionType) {
+ case FlashRegionDescriptor:
+ if (FlashCycleType == FlashCycleRead) {
+ PermissionBit = B_SPI_FRAP_BRRA_FLASHD;
+ } else {
+ PermissionBit = B_SPI_FRAP_BRRA_FLASHD;
+ }
+ HardwareSpiAddr += (MmioRead32 (ScSpiBar0 + R_SPI_FREG0_FLASHD) &
+ B_SPI_FREG0_BASE_MASK) << N_SPI_FREG0_BASE;
+ LimitAddress = (MmioRead32 (ScSpiBar0 + R_SPI_FREG0_FLASHD) &
+ B_SPI_FREG0_LIMIT_MASK) >> N_SPI_FREG0_LIMIT;
+ break;
+ case FlashRegionBios:
+ if (FlashCycleType == FlashCycleRead) {
+ PermissionBit = B_SPI_FRAP_BRRA_BIOS;
+ } else {
+ PermissionBit = B_SPI_FRAP_BRRA_BIOS;
+ }
+ HardwareSpiAddr += (MmioRead32 (ScSpiBar0 + R_SPI_FREG1_BIOS) &
+ B_SPI_FREG1_BASE_MASK) << N_SPI_FREG1_BASE;
+ LimitAddress = (MmioRead32 (ScSpiBar0 + R_SPI_FREG1_BIOS) &
+ B_SPI_FREG1_LIMIT_MASK) >> N_SPI_FREG1_LIMIT;
+ break;
+ case FlashRegionMe:
+ if (FlashCycleType == FlashCycleRead) {
+ PermissionBit = B_SPI_FRAP_BRRA_SEC;
+ } else {
+ PermissionBit = B_SPI_FRAP_BRWA_SEC;
+ }
+ HardwareSpiAddr += (MmioRead32 (ScSpiBar0 + R_SPI_FREG2_SEC) &
+ B_SPI_FREG2_BASE_MASK) << N_SPI_FREG2_BASE;
+ LimitAddress = (MmioRead32 (ScSpiBar0 + R_SPI_FREG2_SEC) &
+ B_SPI_FREG2_LIMIT_MASK) >> N_SPI_FREG2_LIMIT;
+ break;
+ case FlashRegionGbE:
+ if (FlashCycleType == FlashCycleRead) {
+ PermissionBit = B_SPI_FRAP_BRRA_GBE;
+ } else {
+ PermissionBit = B_SPI_FRAP_BRWA_GBE;
+ }
+ HardwareSpiAddr += (MmioRead32 (ScSpiBar0 + R_SPI_FREG3_GBE) &
+ B_SPI_FREG3_BASE_MASK) << N_SPI_FREG3_BASE;
+ LimitAddress = (MmioRead32 (ScSpiBar0 + R_SPI_FREG3_GBE) &
+ B_SPI_FREG3_LIMIT_MASK) >> N_SPI_FREG3_LIMIT;
+ break;
+ case FlashRegionPlatformData:
+ if (FlashCycleType == FlashCycleRead) {
+ PermissionBit = B_SPI_FRAP_BRRA_PLATFORM;
+ } else {
+ PermissionBit = B_SPI_FRAP_BRWA_PLATFORM;
+ }
+ HardwareSpiAddr += (MmioRead32 (ScSpiBar0 + R_SPI_FREG4_PLATFORM_DATA) &
+ B_SPI_FREG4_BASE_MASK) << N_SPI_FREG4_BASE;
+ LimitAddress = (MmioRead32 (ScSpiBar0 + R_SPI_FREG4_PLATFORM_DATA) &
+ B_SPI_FREG4_LIMIT_MASK) >> N_SPI_FREG4_LIMIT;
+ break;
+ case FlashRegionAll:
+ ///
+ /// FlashRegionAll indicates address is relative to flash device (i.e., address is Flash Linear Address)
+ /// No error checking for this case
+ ///
+ LimitAddress = 0;
+ PermissionBit = 0;
+ break;
+ default:
+ Status = EFI_UNSUPPORTED;
+ goto SendSpiCmdEnd;
+ }
+ if ((LimitAddress != 0) && (Address > LimitAddress)) {
+ Status = EFI_INVALID_PARAMETER;
+ goto SendSpiCmdEnd;
+ }
+ ///
+ /// If the operation is read, but the region attribute is not read allowed, return error.
+ /// If the operation is write, but the region attribute is not write allowed, return error.
+ ///
+ if ((PermissionBit != 0) && ((SpiInstance->RegionPermission & PermissionBit) == 0)) {
+ Status = EFI_ACCESS_DENIED;
+ goto SendSpiCmdEnd;
+ }
+ }
+ ///
+ /// Check for SC SPI hardware sequencing required commands
+ ///
+ FlashCycle = 0;
+ switch (FlashCycleType) {
+ case FlashCycleRead:
+ FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_READ << N_SPI_HSFS_CYCLE);
+ break;
+ case FlashCycleWrite:
+ FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_WRITE << N_SPI_HSFS_CYCLE);
+ break;
+ case FlashCycleErase:
+ if (((ByteCount % SIZE_4KB) != 0) ||
+ ((HardwareSpiAddr % SIZE_4KB) != 0)) {
+ DEBUG ((DEBUG_ERROR, " Erase and erase size must be 4KB aligned. \n"));
+ ASSERT (FALSE);
+ Status = EFI_INVALID_PARAMETER;
+ goto SendSpiCmdEnd;
+ }
+ break;
+ case FlashCycleReadSfdp:
+ FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_READ_SFDP << N_SPI_HSFS_CYCLE);
+ break;
+ case FlashCycleReadJedecId:
+ FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_READ_JEDEC_ID << N_SPI_HSFS_CYCLE);
+ break;
+ case FlashCycleWriteStatus:
+ FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_WRITE_STATUS << N_SPI_HSFS_CYCLE);
+ break;
+ case FlashCycleReadStatus:
+ FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_READ_STATUS << N_SPI_HSFS_CYCLE);
+ break;
+ default:
+ ///
+ /// Unrecognized Operation
+ ///
+ ASSERT (FALSE);
+ Status = EFI_INVALID_PARAMETER;
+ goto SendSpiCmdEnd;
+ break;
+ }
+
+ do {
+ SpiDataCount = ByteCount;
+ if ((FlashCycleType == FlashCycleRead) || (FlashCycleType == FlashCycleWrite)) {
+ ///
+ /// Trim at 256 byte boundary per operation,
+ /// - SC SPI controller requires trimming at 4KB boundary
+ /// - Some SPI chips require trimming at 256 byte boundary for write operation
+ /// - Trimming has limited performance impact as we can read / write at most 64 byte
+ /// per operation
+ ///
+ if (HardwareSpiAddr + ByteCount > ((HardwareSpiAddr + BIT8) &~(BIT8 - 1))) {
+ SpiDataCount = (((UINT32) (HardwareSpiAddr) + BIT8) &~(BIT8 - 1)) - (UINT32) (HardwareSpiAddr);
+ }
+ ///
+ /// Calculate the number of bytes to shift in/out during the SPI data cycle.
+ /// Valid settings for the number of bytes during each data portion of the
+ /// SC SPI cycles are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32, 40, 48, 56, 64
+ ///
+ if (SpiDataCount >= 64) {
+ SpiDataCount = 64;
+ } else if ((SpiDataCount &~0x07) != 0) {
+ SpiDataCount = SpiDataCount &~0x07;
+ }
+ }
+ if (FlashCycleType == FlashCycleErase) {
+ if (((ByteCount / SIZE_64KB) != 0) &&
+ ((ByteCount % SIZE_64KB) == 0) &&
+ ((HardwareSpiAddr % SIZE_64KB) == 0)) {
+ if (HardwareSpiAddr < SpiInstance->Component1StartAddr) {
+ //
+ // Check whether Component0 support 64k Erase
+ //
+ if ((SpiInstance->SfdpVscc0Value & B_SPI_LVSCC_EO_64K) != 0) {
+ SpiDataCount = SIZE_64KB;
+ } else {
+ SpiDataCount = SIZE_4KB;
+ }
+ } else {
+ //
+ // Check whether Component1 support 64k Erase
+ //
+ if ((SpiInstance->SfdpVscc1Value & B_SPI_LVSCC_EO_64K) != 0) {
+ SpiDataCount = SIZE_64KB;
+ } else {
+ SpiDataCount = SIZE_4KB;
+ }
+ }
+ } else {
+ SpiDataCount = SIZE_4KB;
+ }
+ if (SpiDataCount == SIZE_4KB) {
+ FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_4K_ERASE << N_SPI_HSFS_CYCLE);
+ } else {
+ FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_64K_ERASE << N_SPI_HSFS_CYCLE);
+ }
+ }
+ ///
+ /// If it's write cycle, load data into the SPI data buffer.
+ ///
+ if ((FlashCycleType == FlashCycleWrite) || (FlashCycleType == FlashCycleWriteStatus)) {
+ if ((SpiDataCount & 0x07) != 0) {
+ ///
+ /// Use Byte write if Data Count is 0, 1, 2, 3, 4, 5, 6, 7
+ ///
+ for (Index = 0; Index < SpiDataCount; Index++) {
+ MmioWrite8 (ScSpiBar0 + R_SPI_FDATA00 + Index, Buffer[Index]);
+ }
+ } else {
+ ///
+ /// Use Dword write if Data Count is 8, 16, 24, 32, 40, 48, 56, 64
+ ///
+ for (Index = 0; Index < SpiDataCount; Index += sizeof (UINT32)) {
+ MmioWrite32 (ScSpiBar0 + R_SPI_FDATA00 + Index, *(UINT32 *) (Buffer + Index));
+ }
+ }
+ }
+
+ ///
+ /// Set the Flash Address
+ ///
+ MmioWrite32 (
+ (ScSpiBar0 + R_SPI_FADDR),
+ (UINT32) (HardwareSpiAddr & B_SPI_FADDR_MASK)
+ );
+
+ ///
+ /// Set Data count, Flash cycle, and Set Go bit to start a cycle
+ ///
+ MmioAndThenOr32 (
+ ScSpiBar0 + R_SPI_HSFS,
+ (UINT32) (~(B_SPI_HSFS_FDBC_MASK | B_SPI_HSFS_CYCLE_MASK)),
+ (UINT32) (((SpiDataCount - 1) << N_SPI_HSFS_FDBC) | FlashCycle | B_SPI_HSFS_CYCLE_FGO)
+ );
+
+ ///
+ /// end of command execution
+ ///
+ /// Wait the SPI cycle to complete.
+ ///
+ if (!WaitForSpiCycleComplete (ScSpiBar0, TRUE)) {
+ Status = EFI_DEVICE_ERROR;
+ goto SendSpiCmdEnd;
+ }
+ ///
+ /// If it's read cycle, load data into the caller's buffer.
+ ///
+ if ((FlashCycleType == FlashCycleRead) ||
+ (FlashCycleType == FlashCycleReadSfdp) ||
+ (FlashCycleType == FlashCycleReadJedecId) ||
+ (FlashCycleType == FlashCycleReadStatus)) {
+ if ((SpiDataCount & 0x07) != 0) {
+ ///
+ /// Use Byte read if Data Count is 0, 1, 2, 3, 4, 5, 6, 7
+ ///
+ for (Index = 0; Index < SpiDataCount; Index++) {
+ Buffer[Index] = MmioRead8 (ScSpiBar0 + R_SPI_FDATA00 + Index);
+ }
+ } else {
+ ///
+ /// Use Dword read if Data Count is 8, 16, 24, 32, 40, 48, 56, 64
+ ///
+ for (Index = 0; Index < SpiDataCount; Index += sizeof (UINT32)) {
+ *(UINT32 *) (Buffer + Index) = MmioRead32 (ScSpiBar0 + R_SPI_FDATA00 + Index);
+ }
+ }
+ }
+
+ HardwareSpiAddr += SpiDataCount;
+ Buffer += SpiDataCount;
+ ByteCount -= SpiDataCount;
+ } while (ByteCount > 0);
+
+SendSpiCmdEnd:
+ ///
+ /// Restore the settings for SPI Prefetching and Caching and enable BIOS Write Protect
+ ///
+ if ((FlashCycleType == FlashCycleWrite) ||
+ (FlashCycleType == FlashCycleErase)) {
+ EnableBiosWriteProtect ();
+ MmioAndThenOr8 (
+ SpiBaseAddress + R_SPI_BCR,
+ (UINT8) ~B_SPI_BCR_SRC,
+ BiosCtlSave
+ );
+ }
+
+ ReleaseSpiBar0 ();
+
+ return Status;
+}
+
+/**
+ Wait execution cycle to complete on the SPI interface.
+
+ @param[in] ScSpiBar0 Spi MMIO base address
+ @param[in] ErrorCheck TRUE if the SpiCycle needs to do the error check
+
+ @retval TRUE SPI cycle completed on the interface.
+ @retval FALSE Time out while waiting the SPI cycle to complete.
+ It's not safe to program the next command on the SPI interface.
+**/
+BOOLEAN
+WaitForSpiCycleComplete (
+ IN UINT32 ScSpiBar0,
+ IN BOOLEAN ErrorCheck
+ )
+{
+ UINT64 WaitTicks;
+ UINT64 WaitCount;
+ UINT32 Data32;
+
+ ///
+ /// Convert the wait period allowed into to tick count
+ ///
+ WaitCount = WAIT_TIME / WAIT_PERIOD;
+ ///
+ /// Wait for the SPI cycle to complete.
+ ///
+ for (WaitTicks = 0; WaitTicks < WaitCount; WaitTicks++) {
+ Data32 = MmioRead32 (ScSpiBar0 + R_SPI_HSFS);
+ if ((Data32 & B_SPI_HSFS_SCIP) == 0) {
+ MmioWrite32 (ScSpiBar0 + R_SPI_HSFS, B_SPI_HSFS_FCERR | B_SPI_HSFS_FDONE);
+ if ( ((Data32 & B_SPI_HSFS_FCERR) != 0) && (ErrorCheck == TRUE)) {
+ return FALSE;
+ } else {
+ return TRUE;
+ }
+ }
+ MicroSecondDelay ( WAIT_PERIOD);
+ }
+ return FALSE;
+}
+
+
+/**
+ Acquire SC spi mmio address.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval ScSpiBar0 Return SPI MMIO address
+**/
+UINT32
+AcquireSpiBar0 (
+ VOID
+ )
+{
+ SPI_INSTANCE *SpiInstance;
+
+ SpiInstance = GetSpiInstance();
+ return MmioRead32 (SpiInstance->PchSpiBase + R_SPI_BASE) & ~(B_SPI_BAR0_MASK);
+}
+
+/**
+ Release SC spi mmio address. Do nothing.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval None
+**/
+VOID
+ReleaseSpiBar0 (
+ VOID
+ )
+{
+}
+
+/**
+ This function is a hook for Spi to disable BIOS Write Protect
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in SMM phase
+
+**/
+EFI_STATUS
+EFIAPI
+DisableBiosWriteProtect (
+ VOID
+ )
+{
+ UINTN SpiBaseAddress;
+
+ SpiBaseAddress = GetSpiInstance()->PchSpiBase;
+
+ if ((MmioRead8 (SpiBaseAddress + R_SPI_BCR) & B_SPI_BCR_SMM_BWP) != 0) {
+ return EFI_ACCESS_DENIED;
+ }
+ //
+ // Enable the access to the BIOS space for both read and write cycles
+ //
+ MmioOr8 (SpiBaseAddress + R_SPI_BCR, B_SPI_BCR_BIOSWE);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function is a hook for Spi to enable BIOS Write Protect
+
+ @retval
+**/
+VOID
+EFIAPI
+EnableBiosWriteProtect (
+ VOID
+ )
+{
+ UINTN SpiBaseAddress;
+
+ SpiBaseAddress = GetSpiInstance()->PchSpiBase;
+
+ //
+ // Disable the access to the BIOS space for write cycles
+ //
+ MmioAnd8 (SpiBaseAddress + R_SPI_BCR, (UINT8) (~B_SPI_BCR_BIOSWE));
+}
+
+/**
+ Get the SPI region base and size, based on the enum type
+
+ @param[in] FlashRegionType The Flash Region type for for the base address which is listed in the Descriptor.
+ @param[out] BaseAddress The Flash Linear Address for the Region 'n' Base
+ @param[out] RegionSize The size for the Region 'n'
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_INVALID_PARAMETER Invalid region type given
+ @retval EFI_DEVICE_ERROR The region is not used
+**/
+EFI_STATUS
+EFIAPI
+SpiGetRegionAddress (
+ IN FLASH_REGION_TYPE FlashRegionType,
+ OUT UINT32 *BaseAddress, OPTIONAL
+ OUT UINT32 *RegionSize OPTIONAL
+ )
+{
+ UINT32 ScSpiBar0;
+ UINT32 ReadValue;
+ UINT32 Base;
+
+ if (FlashRegionType >= FlashRegionMax) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (FlashRegionType == FlashRegionAll) {
+ if (BaseAddress != NULL) {
+ *BaseAddress = 0;
+ }
+ if (RegionSize != NULL) {
+ *RegionSize = GetSpiInstance()->Component1StartAddr;
+ }
+ return EFI_SUCCESS;
+ }
+
+ ScSpiBar0 = AcquireSpiBar0 ();
+ ReadValue = MmioRead32 (ScSpiBar0 + R_SPI_FREG0_FLASHD + S_SPI_FREGX * (UINT32) FlashRegionType);
+ ReleaseSpiBar0 ();
+
+ //
+ // If the region is not used, the Region Base is 7FFFh and Region Limit is 0000h
+ //
+ if (ReadValue == B_SPI_FREGX_BASE_MASK) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ Base = (ReadValue & B_SPI_FREG1_BASE_MASK) << N_SPI_FREG1_BASE;
+ if (BaseAddress != NULL) {
+ *BaseAddress = Base;
+ }
+
+ if (RegionSize != NULL) {
+ *RegionSize = ((((ReadValue & B_SPI_FREGX_LIMIT_MASK) >> N_SPI_FREGX_LIMIT) + 1) <<
+ N_SPI_FREGX_LIMIT_REPR) - Base;
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/CommonSocPkg/Library/SpiFlashLib/SpiFlashLib.inf b/Silicon/CommonSocPkg/Library/SpiFlashLib/SpiFlashLib.inf
new file mode 100644
index 00000000..8063b160
--- /dev/null
+++ b/Silicon/CommonSocPkg/Library/SpiFlashLib/SpiFlashLib.inf
@@ -0,0 +1,39 @@
+## @file
+#
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SpiFlashLib
+ FILE_GUID = 6F96AFCB-DE89-4ca1-A63F-8703EE8FDE50
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SpiFlashLib
+ CONSTRUCTOR = SpiConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources]
+ SpiFlashLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ BootloaderCommonPkg/BootloaderCommonPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ IoLib
+ PciLib
+ TimerLib
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gPlatformCommonLibTokenSpaceGuid.PcdSpiFlashLibId