From d7bdca432e5593355bd40b98073ade5ccf172b29 Mon Sep 17 00:00:00 2001 From: Maurice Ma Date: Thu, 21 Nov 2019 22:37:02 -0800 Subject: [PATCH] PCIE device wake up enhancement This is a follow-up to the previous WOL commit. The previous implementation is more LeafHill specific. This patch further added configuration data to control how wake up signal is mapped into each PCIE root port. And the ASL code has been adjusted to utilize that info so that the code can be more generic for all other platforms. The current default configuration for PCIE wake signal is aligned with LeafHill CRB board. For other borads, to enable it properly, it is required to override the wake signal configuration using DLT. Test has been done on LeafHill to do WOL with yocto image. It worked as expected. Signed-off-by: Maurice Ma --- .../AcpiTables/Dsdt/GloblNvs.asl | 7 ++ .../AcpiTables/Dsdt/Gpe.asl | 83 +++++++++++++------ .../ApollolakeBoardPkg/AcpiTables/Dsdt/Sc.asl | 77 ++++++++++++----- .../AcpiTables/Dsdt/ScPcie.asl | 8 +- .../CfgData/CfgData_PcieRp.dsc | 8 +- .../CfgData/Template_PcieRp.dsc | 8 +- .../Stage2BoardInitLib/Stage2BoardInitLib.c | 18 ++++ Silicon/ApollolakePkg/Include/GlobalNvsArea.h | 2 + 8 files changed, 158 insertions(+), 53 deletions(-) diff --git a/Platform/ApollolakeBoardPkg/AcpiTables/Dsdt/GloblNvs.asl b/Platform/ApollolakeBoardPkg/AcpiTables/Dsdt/GloblNvs.asl index 65ab71ff..87c03ac6 100644 --- a/Platform/ApollolakeBoardPkg/AcpiTables/Dsdt/GloblNvs.asl +++ b/Platform/ApollolakeBoardPkg/AcpiTables/Dsdt/GloblNvs.asl @@ -56,4 +56,11 @@ M32L, 32, // PCIE MMIO resource length ADFM, 32, // HD-Audio DSP Feature Mask ADPM, 32, // Hd-Audio DSP Post-Processing Module Mask + RPW1, 8, // RP 1 wake GPE bit + RPW2, 8, // RP 2 wake GPE bit + RPW3, 8, // RP 3 wake GPE bit + RPW4, 8, // RP 4 wake GPE bit + RPW5, 8, // RP 5 wake GPE bit + RPW6, 8, // RP 6 wake GPE bit + RSV5, 16, // Reserved for alignment } diff --git a/Platform/ApollolakeBoardPkg/AcpiTables/Dsdt/Gpe.asl b/Platform/ApollolakeBoardPkg/AcpiTables/Dsdt/Gpe.asl index 6b4fca1b..8364be83 100644 --- a/Platform/ApollolakeBoardPkg/AcpiTables/Dsdt/Gpe.asl +++ b/Platform/ApollolakeBoardPkg/AcpiTables/Dsdt/Gpe.asl @@ -16,33 +16,51 @@ External(HGAS, MethodObj) Scope(\_GPE) { - Method(_L0D, 0) { - Notify(\_SB.PCI0.XHC, 0x02) - } - - Method(_L0E, 0) { - Notify(\_SB.PCI0.HDAS, 0x02) - } - - // Dummy method for the Tier 1 GPIO SCI enable bit - Method(_L0F, 0) {} - - Method(_L39){ - // Required for ACPI 5.0 native Windows support - Notify(\_SB.PCI0.SATA.PRT0, 2) // Device Wake (Windows) + Method(WKNT, 1) { + If(LEqual(Arg0, RPW1)) { + \_SB.PCI0.RP01.HPME() + Notify(\_SB.PCI0.RP01, 0x02) + } + If(LEqual(Arg0, RPW2)) { + \_SB.PCI0.RP02.HPME() + Notify(\_SB.PCI0.RP02, 0x02) + } + If(LEqual(Arg0, RPW3)) { + \_SB.PCI0.RP03.HPME() + Notify(\_SB.PCI0.RP03, 0x02) + } + If(LEqual(Arg0, RPW4)) { + \_SB.PCI0.RP04.HPME() + Notify(\_SB.PCI0.RP04, 0x02) + } + If(LEqual(Arg0, RPW5)) { + \_SB.PCI0.RP05.HPME() + Notify(\_SB.PCI0.RP05, 0x02) + } + If(LEqual(Arg0, RPW6)) { + \_SB.PCI0.RP06.HPME() + Notify(\_SB.PCI0.RP06, 0x02) } - - // Leaf Hill CRB: RP05 is LAN - // GPE enable bit is 3 - Method(_L03, 0) { - \_SB.PCI0.RP05.HPME() - Notify(\_SB.PCI0.RP05, 0x02) } - // Leaf Hill CRB: RP02 is WiFi/BT - // GPE enable bit is 8 + + Method(_L03, 0) { + Store (1, WK3S) + WKNT (3) + } + + Method(_L06, 0) { + Store (1, WK6S) + WKNT (6) + } + + Method(_L07, 0) { + Store (1, WK7S) + WKNT (7) + } + Method(_L08, 0) { - \_SB.PCI0.RP02.HPME() - Notify(\_SB.PCI0.RP02, 0x02) + Store (1, WK8S) + WKNT (8) } Method(_L09, 0) { @@ -71,5 +89,22 @@ Scope(\_GPE) Notify(\_SB.PCI0.RP06, 0x02) } } + + Method(_L0D, 0) { + Notify(\_SB.PCI0.XHC, 0x02) + } + + Method(_L0E, 0) { + Notify(\_SB.PCI0.HDAS, 0x02) + } + + // Dummy method for the Tier 1 GPIO SCI enable bit + Method(_L0F, 0) { + } + + Method(_L39) { + // Required for ACPI 5.0 native Windows support + Notify(\_SB.PCI0.SATA.PRT0, 2) // Device Wake (Windows) + } } diff --git a/Platform/ApollolakeBoardPkg/AcpiTables/Dsdt/Sc.asl b/Platform/ApollolakeBoardPkg/AcpiTables/Dsdt/Sc.asl index 5b0e20b2..5bf5a438 100644 --- a/Platform/ApollolakeBoardPkg/AcpiTables/Dsdt/Sc.asl +++ b/Platform/ApollolakeBoardPkg/AcpiTables/Dsdt/Sc.asl @@ -17,7 +17,13 @@ Scope(\) , 8, PWBS, 1, // Power Button Status Offset(0x20), - , 13, + , 3, + WK3S, 1, + , 2, + WK6S, 1, + WK7S, 1, + WK8S, 1, + , 4, PMEB, 1, // PME_B0_STS Offset(0x42), // General Purpose Control , 1, @@ -106,9 +112,15 @@ scope (\_SB.PCI0) { Return (0x00140000) } } - Name(_PRF, 0x09) - Include("ScPcie.asl") - Method(_PRW, 0) { Return(GPRW(_PRF, 4)) } // can wakeup from S4 state + + #define PCIE_WAKE_GPE_BIT RPW1 + #include "ScPcie.asl" + #undef PCIE_WAKE_GPE_BIT + + Method(_PRW, 0) { + Return(GPRW(RPW1, 4)) + } // can wakeup from S4 state + Method(_PRT, 0) { If(PICM) { Return(AR04) }// APIC mode Return (PR04) // PIC Mode @@ -126,9 +138,15 @@ scope (\_SB.PCI0) { Return (0x00140001) } } - Name(_PRF, 0x08) - Include("ScPcie.asl") - Method(_PRW, 0) { Return(GPRW(_PRF, 4)) } // Leaf Hill CRB: GPE enable bit for RP2 is 8, can wake up from S4 state + + #define PCIE_WAKE_GPE_BIT RPW2 + #include "ScPcie.asl" + #undef PCIE_WAKE_GPE_BIT + + Method(_PRW, 0) { + Return(GPRW(RPW2, 4)) + } // can wakeup from S4 state + Method(_PRT, 0) { If(PICM) { Return(AR05) }// APIC mode Return (PR05) // PIC Mode @@ -146,9 +164,15 @@ scope (\_SB.PCI0) { Return (0x00130000) } } - Include("ScPcie.asl") - Name(_PRF, 0x09) - Method(_PRW, 0) { Return(GPRW(_PRF, 4)) } // can wakeup from S4 state + + #define PCIE_WAKE_GPE_BIT RPW3 + #include "ScPcie.asl" + #undef PCIE_WAKE_GPE_BIT + + Method(_PRW, 0) { + Return(GPRW(RPW3, 4)) + } // can wakeup from S4 state + Method(_PRT, 0) { If(PICM) { Return(AR04) }// APIC mode Return (PR04) // PIC Mode @@ -166,9 +190,15 @@ scope (\_SB.PCI0) { Return (0x00130001) } } - Name(_PRF, 0x09) - Include("ScPcie.asl") - Method(_PRW, 0) { Return(GPRW(_PRF, 4)) } // can wakeup from S4 state + + #define PCIE_WAKE_GPE_BIT RPW4 + #include "ScPcie.asl" + #undef PCIE_WAKE_GPE_BIT + + Method(_PRW, 0) { + Return(GPRW(RPW4, 4)) + } // can wakeup from S4 state + Method(_PRT, 0) { If(PICM) { Return(AR05) }// APIC mode Return (PR05) // PIC Mode @@ -186,9 +216,15 @@ scope (\_SB.PCI0) { Return (0x00130002) } } - Name(_PRF, 0x03) - Include("ScPcie.asl") - Method(_PRW, 0) { Return(GPRW(_PRF, 4)) } // Leaf Hill CRB: GPE enable bit for RP5 is 3, can wakeup from S4 state + + #define PCIE_WAKE_GPE_BIT RPW5 + #include "ScPcie.asl" + #undef PCIE_WAKE_GPE_BIT + + Method(_PRW, 0) { + Return(GPRW(RPW5, 4)) + } // can wakeup from S4 state + Method(_PRT, 0) { If(PICM) { Return(AR06) }// APIC mode Return (PR06) // PIC Mode @@ -206,9 +242,12 @@ scope (\_SB.PCI0) { Return (0x00130003) } } - Name(_PRF, 0x09) - Include("ScPcie.asl") - Method(_PRW, 0) { Return(GPRW(_PRF, 4)) } // can wakeup from S4 state + + #define PCIE_WAKE_GPE_BIT RPW6 + #include "ScPcie.asl" + #undef PCIE_WAKE_GPE_BIT + + Method(_PRW, 0) { Return(GPRW(RPW6, 4)) } // can wakeup from S4 state Method(_PRT, 0) { If(PICM) { Return(AR07) }// APIC mode Return (PR07) // PIC Mode diff --git a/Platform/ApollolakeBoardPkg/AcpiTables/Dsdt/ScPcie.asl b/Platform/ApollolakeBoardPkg/AcpiTables/Dsdt/ScPcie.asl index 09adf1f2..a358a5c7 100644 --- a/Platform/ApollolakeBoardPkg/AcpiTables/Dsdt/ScPcie.asl +++ b/Platform/ApollolakeBoardPkg/AcpiTables/Dsdt/ScPcie.asl @@ -40,12 +40,10 @@ { Name(_ADR, 0x00000000) - // NOTE: Any PCIE Hot-Plug dependency for this port is - // specific to the CRB. Please modify the code based on - // your platform requirements: see the relevant section - // in Sc.asl before ScPcie.asl is included. + Method(_PRW, 0) { + Return(GPRW(PCIE_WAKE_GPE_BIT, 4)) + } // can wakeup from S4 state - Name(_PRW, Package(){_PRF,4}) } // diff --git a/Platform/ApollolakeBoardPkg/CfgData/CfgData_PcieRp.dsc b/Platform/ApollolakeBoardPkg/CfgData/CfgData_PcieRp.dsc index ce261c93..bb3908fb 100644 --- a/Platform/ApollolakeBoardPkg/CfgData/CfgData_PcieRp.dsc +++ b/Platform/ApollolakeBoardPkg/CfgData/CfgData_PcieRp.dsc @@ -27,11 +27,11 @@ # !BSF SUBT:{PCIERP_TMPL:5 : 0x8E} # Power : Reset - # !BSF SUBT:{PCIERP_CTRL_PIN_TMPL:0 : 0x0021318A : 0x0021618E} - # !BSF SUBT:{PCIERP_CTRL_PIN_TMPL:1 : 0x0021118A : 0x0020D18A} - # !BSF SUBT:{PCIERP_CTRL_PIN_TMPL:2 : 0x0000018B : 0x0020F18A} + # !BSF SUBT:{PCIERP_CTRL_PIN_TMPL:0 : 0x6021318A : 0x0021618E} + # !BSF SUBT:{PCIERP_CTRL_PIN_TMPL:1 : 0x8021118A : 0x0020D18A} + # !BSF SUBT:{PCIERP_CTRL_PIN_TMPL:2 : 0x4000018B : 0x0020F18A} # !BSF SUBT:{PCIERP_CTRL_PIN_TMPL:3 : 0x0000018B : 0x0022518A} - # !BSF SUBT:{PCIERP_CTRL_PIN_TMPL:4 : 0x0000018B : 0x0000018B} + # !BSF SUBT:{PCIERP_CTRL_PIN_TMPL:4 : 0x2000018B : 0x0000018B} # !BSF SUBT:{PCIERP_CTRL_PIN_TMPL:5 : 0x0000018B : 0x0000018B} gCfgData.Reserved | * | 0x02 | 0 diff --git a/Platform/ApollolakeBoardPkg/CfgData/Template_PcieRp.dsc b/Platform/ApollolakeBoardPkg/CfgData/Template_PcieRp.dsc index 250337be..a0a922fc 100644 --- a/Platform/ApollolakeBoardPkg/CfgData/Template_PcieRp.dsc +++ b/Platform/ApollolakeBoardPkg/CfgData/Template_PcieRp.dsc @@ -83,7 +83,13 @@ # !BSF NAME:{Power Reserved} TYPE:{Reserved} # !BSF CONDITION:{$(COND_PCIE_RP_PWR_PIN_SKIP)} - # !BSF FIELD:{Rsvd1:10b} + # !BSF FIELD:{Rsvd1:7b} + + # !BSF NAME:{Wake Signal} + # !BSF TYPE:{Combo} + # !BSF OPTION:{0x0:Disable, 0x1:PCIE_WAKE0, 0x2:PCIE_WAKE1, 0x3:PCIE_WAKE2, 0x4:PCIE_WAKE3} + # !BSF HELP:{Specify the PCIE wake signal connected to this port} + # !BSF FIELD:{Wake:3b} # !BSF PAGES:{PLT_RST_$(1):PLT_PCIE_RP_CTRL_PIN_RST:"PCIE RP $(1)"} # !BSF PAGE:{PLT_RST_$(1)} diff --git a/Platform/ApollolakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c b/Platform/ApollolakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c index 2ba05fcc..76c2f64b 100644 --- a/Platform/ApollolakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c +++ b/Platform/ApollolakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c @@ -11,6 +11,7 @@ UINT32 mOtgDualRoleCfg0 = 0; +CONST UINT8 mPcieRpWakeGpeBit[5] = {9, 3, 6, 7, 8}; /** Create NHLT (Non HDA-Link Table) @@ -1669,6 +1670,10 @@ PlatformUpdateAcpiGnvs ( SYS_CPU_INFO *SysCpuInfo; HDA_CFG_DATA *HdaCfgData; DEV_EN_CFG_DATA *DevEnCfgData; + PCIE_RP_CFG_DATA *PcieRpConfigData; + PCIE_RP_PIN_CTRL *PowerResetData; + UINT8 Idx1; + UINT8 Idx2; Gnvs = (GLOBAL_NVS_AREA *)GnvsIn; Pnvs = &Gnvs->PlatformNvs; @@ -1699,5 +1704,18 @@ PlatformUpdateAcpiGnvs ( Pnvs->HdaDspModMask = HdaCfgData->DspPpModuleMask; } + PcieRpConfigData = (PCIE_RP_CFG_DATA *)FindConfigDataByTag (CDATA_PCIE_RP_TAG); + if (PcieRpConfigData != NULL) { + PowerResetData = (PCIE_RP_PIN_CTRL *) PcieRpConfigData->PcieRpPinCtrlData0; + for (Idx1 = 0; Idx1 < PCIE_MAX_ROOT_PORTS; Idx1++) { + Idx2 = (UINT8)PowerResetData->PcieRpPower0.Wake; + if (Idx2 > sizeof(mPcieRpWakeGpeBit)) { + Idx2 = 0; + } + Pnvs->PcieRpGpeWakeBit[Idx1] = mPcieRpWakeGpeBit[Idx2]; + PowerResetData++; + } + } + SocUpdateAcpiGnvs ((VOID *)Gnvs); } diff --git a/Silicon/ApollolakePkg/Include/GlobalNvsArea.h b/Silicon/ApollolakePkg/Include/GlobalNvsArea.h index b89a6a79..7fc2e613 100644 --- a/Silicon/ApollolakePkg/Include/GlobalNvsArea.h +++ b/Silicon/ApollolakePkg/Include/GlobalNvsArea.h @@ -65,6 +65,8 @@ typedef struct { UINT32 Mmio32Length; ///< PCIE MMIO resource length UINT32 HdaDspFeatureMask; ///< HD-Audio DSP Feature Mask UINT32 HdaDspModMask; ///< Hd-Audio DSP Post-Processing Module Mask + UINT8 PcieRpGpeWakeBit[6]; ///< PCIE RP wake GPE bit offset + UINT8 Reserved5[2]; } PLATFORM_NVS_AREA; typedef struct {