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Add support for PCI expansion rom resource allocation

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Current SBL PCI enumeration does not allocate resource for PCI ROM
bar because SBL does not deal with option ROM at all. However, the
Linux kernel might expect the ROM bar resource to be allocated.
This patch introduces a static build configuration to allow support
PCI resource allocation for PCI ROM bar.

To enable this feature, please add following into the project
BoardConfig.py file:
  self._PCI_ENUM_FLAG_ALLOC_ROM_BAR = 1

By default, it will be disabled to keep the same behavior as before.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This commit is contained in:
Maurice Ma
2022-02-26 21:39:39 -08:00
parent b0269b62d0
commit c2e634c5c9
5 changed files with 41 additions and 10 deletions
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BootloaderCorePkg/Library/PciEnumerationLib/InternalPciEnumerationLib.c
+11 -3
View File
@@ -1,6 +1,6 @@
/** @file
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -32,14 +32,22 @@ BarExisted (
)
{
UINT32 OriginalValue;
UINT32 AllOne;
UINT32 Mask;
volatile UINT32 Value;
//
// Preserve the original value
//
OriginalValue = PciExpressRead32 (PciIoDevice->Address + Offset);
PciExpressWrite32 (PciIoDevice->Address + Offset, 0xFFFFFFFF);
Value = PciExpressRead32 (PciIoDevice->Address + Offset);
AllOne = 0xFFFFFFFF;
Mask = 0xFFFFFFFF;
if (Offset == PCI_EXPANSION_ROM_BASE) {
AllOne &= ~BIT0;
Mask &= ~0x7FF;
}
PciExpressWrite32 (PciIoDevice->Address + Offset, AllOne);
Value = PciExpressRead32 (PciIoDevice->Address + Offset) & Mask;
PciExpressWrite32 (PciIoDevice->Address + Offset, OriginalValue);
if (BarLengthValue != NULL) {
BootloaderCorePkg/Library/PciEnumerationLib/InternalPciEnumerationLib.h
+3 -2
View File
@@ -1,6 +1,6 @@
/** @file
Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -75,7 +75,8 @@ typedef struct {
typedef struct {
UINT16 AllocPmemFirst : 1;
UINT16 Reserved : 15;
UINT16 FlagAllocRomBar : 1;
UINT16 Reserved : 14;
} PCI_ENUM_FLAG;
typedef struct {
BootloaderCorePkg/Library/PciEnumerationLib/PciEnumerationLib.c
+21 -3
View File
@@ -1,6 +1,6 @@
/** @file
Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -216,7 +216,11 @@ PciParseBar (
} else {
Mask = 0xfffffff0;
if (Offset == PCI_EXPANSION_ROM_BASE) {
Mask = 0xfffff800;
} else {
Mask = 0xfffffff0;
}
PciIoDevice->PciBar[BarIndex].BaseAddress = OriginalValue & Mask;
@@ -486,11 +490,11 @@ GatherDeviceInfo (
//
// Inherit parent decode capability
//
EnumPolicy = (PCI_ENUM_POLICY_INFO *)PcdGetPtr (PcdPciEnumPolicyInfo);
if (PciIoDevice->Parent != NULL) {
PciIoDevice->Decodes = PciIoDevice->Parent->Decodes;
Downgrade = FALSE;
if (Bus == 0) {
EnumPolicy = (PCI_ENUM_POLICY_INFO *)PcdGetPtr (PcdPciEnumPolicyInfo);
if (EnumPolicy->Downgrade.Bus0 == 1) {
Downgrade = TRUE;
} else if (EnumPolicy->Downgrade.Bus0 == 2) {
@@ -513,6 +517,20 @@ GatherDeviceInfo (
Offset = PciParseBar (PciIoDevice, Offset, BarIndex);
}
//
// Find a available PCI bar slot for PCI expansion ROM
//
if (EnumPolicy->Flag.FlagAllocRomBar == 1) {
BarIndex = PCI_MAX_BAR - 1;
while (BarIndex > 0) {
if (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeUnknown) {
PciParseBar (PciIoDevice, PCI_EXPANSION_ROM_BASE, BarIndex);
break;
}
BarIndex--;
}
}
//
// Parse the SR-IOV VF bars
//