diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/BootSectImage b/BaseTools/Bin/CYGWIN_NT-5.1-i686/BootSectImage
deleted file mode 100644
index 0945d86d..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/BootSectImage
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/usr/bin/env bash
-
-full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a discussion of why $0 is not a good choice here
-dir=$(dirname "$full_cmd")
-cmd=${full_cmd##*/}
-
-if [ -n "$WORKSPACE" ] && [ -e "$WORKSPACE/Conf/BaseToolsCBinaries" ]
-then
- exec "$WORKSPACE/Conf/BaseToolsCBinaries/$cmd"
-elif [ -n "$WORKSPACE" ] && [ -e "$EDK_TOOLS_PATH/Source/C" ]
-then
- if [ ! -e "$EDK_TOOLS_PATH/Source/C/bin/$cmd" ]
- then
- echo "BaseTools C Tool binary was not found ($cmd)"
- echo "You may need to run:"
- echo " make -C $EDK_TOOLS_PATH/Source/C"
- else
- exec "$EDK_TOOLS_PATH/Source/C/bin/$cmd" "$@"
- fi
-elif [ -e "$dir/../../Source/C/bin/$cmd" ]
-then
- exec "$dir/../../Source/C/bin/$cmd" "$@"
-else
- echo "Unable to find the real '$cmd' to run"
- echo "This message was printed by"
- echo " $0"
- exit 127
-fi
-
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/BuildEnv b/BaseTools/Bin/CYGWIN_NT-5.1-i686/BuildEnv
deleted file mode 100644
index 2cb8b86a..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/BuildEnv
+++ /dev/null
@@ -1,5 +0,0 @@
-#!/usr/bin/env bash
-#python `dirname $0`/RunToolFromSource.py `basename $0` $*
-PYTHONPATH="`dirname $0`/../../Source/Python" \
- python "`dirname $0`/../../Source/Python"/`basename $0`/`basename $0`.py $*
-
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/Ecc b/BaseTools/Bin/CYGWIN_NT-5.1-i686/Ecc
deleted file mode 100644
index 1ba451cf..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/Ecc
+++ /dev/null
@@ -1,14 +0,0 @@
-#!/usr/bin/env bash
-#python `dirname $0`/RunToolFromSource.py `basename $0` $*
-
-# If a ${PYTHON_COMMAND} command is available, use it in preference to python
-if command -v ${PYTHON_COMMAND} >/dev/null 2>&1; then
- python_exe=${PYTHON_COMMAND}
-fi
-
-full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a discussion of why $0 is not a good choice here
-dir=$(dirname "$full_cmd")
-cmd=${full_cmd##*/}
-
-export PYTHONPATH="$dir/../../Source/Python"
-exec "${python_exe:-python}" "$dir/../../Source/Python/$cmd/$cmd.py" "$@"
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/EfiLdrImage b/BaseTools/Bin/CYGWIN_NT-5.1-i686/EfiLdrImage
deleted file mode 100644
index 0945d86d..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/EfiLdrImage
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/usr/bin/env bash
-
-full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a discussion of why $0 is not a good choice here
-dir=$(dirname "$full_cmd")
-cmd=${full_cmd##*/}
-
-if [ -n "$WORKSPACE" ] && [ -e "$WORKSPACE/Conf/BaseToolsCBinaries" ]
-then
- exec "$WORKSPACE/Conf/BaseToolsCBinaries/$cmd"
-elif [ -n "$WORKSPACE" ] && [ -e "$EDK_TOOLS_PATH/Source/C" ]
-then
- if [ ! -e "$EDK_TOOLS_PATH/Source/C/bin/$cmd" ]
- then
- echo "BaseTools C Tool binary was not found ($cmd)"
- echo "You may need to run:"
- echo " make -C $EDK_TOOLS_PATH/Source/C"
- else
- exec "$EDK_TOOLS_PATH/Source/C/bin/$cmd" "$@"
- fi
-elif [ -e "$dir/../../Source/C/bin/$cmd" ]
-then
- exec "$dir/../../Source/C/bin/$cmd" "$@"
-else
- echo "Unable to find the real '$cmd' to run"
- echo "This message was printed by"
- echo " $0"
- exit 127
-fi
-
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/EfiRom b/BaseTools/Bin/CYGWIN_NT-5.1-i686/EfiRom
deleted file mode 100644
index 0945d86d..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/EfiRom
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/usr/bin/env bash
-
-full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a discussion of why $0 is not a good choice here
-dir=$(dirname "$full_cmd")
-cmd=${full_cmd##*/}
-
-if [ -n "$WORKSPACE" ] && [ -e "$WORKSPACE/Conf/BaseToolsCBinaries" ]
-then
- exec "$WORKSPACE/Conf/BaseToolsCBinaries/$cmd"
-elif [ -n "$WORKSPACE" ] && [ -e "$EDK_TOOLS_PATH/Source/C" ]
-then
- if [ ! -e "$EDK_TOOLS_PATH/Source/C/bin/$cmd" ]
- then
- echo "BaseTools C Tool binary was not found ($cmd)"
- echo "You may need to run:"
- echo " make -C $EDK_TOOLS_PATH/Source/C"
- else
- exec "$EDK_TOOLS_PATH/Source/C/bin/$cmd" "$@"
- fi
-elif [ -e "$dir/../../Source/C/bin/$cmd" ]
-then
- exec "$dir/../../Source/C/bin/$cmd" "$@"
-else
- echo "Unable to find the real '$cmd' to run"
- echo "This message was printed by"
- echo " $0"
- exit 127
-fi
-
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenCrc32 b/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenCrc32
deleted file mode 100644
index 0945d86d..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenCrc32
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/usr/bin/env bash
-
-full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a discussion of why $0 is not a good choice here
-dir=$(dirname "$full_cmd")
-cmd=${full_cmd##*/}
-
-if [ -n "$WORKSPACE" ] && [ -e "$WORKSPACE/Conf/BaseToolsCBinaries" ]
-then
- exec "$WORKSPACE/Conf/BaseToolsCBinaries/$cmd"
-elif [ -n "$WORKSPACE" ] && [ -e "$EDK_TOOLS_PATH/Source/C" ]
-then
- if [ ! -e "$EDK_TOOLS_PATH/Source/C/bin/$cmd" ]
- then
- echo "BaseTools C Tool binary was not found ($cmd)"
- echo "You may need to run:"
- echo " make -C $EDK_TOOLS_PATH/Source/C"
- else
- exec "$EDK_TOOLS_PATH/Source/C/bin/$cmd" "$@"
- fi
-elif [ -e "$dir/../../Source/C/bin/$cmd" ]
-then
- exec "$dir/../../Source/C/bin/$cmd" "$@"
-else
- echo "Unable to find the real '$cmd' to run"
- echo "This message was printed by"
- echo " $0"
- exit 127
-fi
-
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenDepex b/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenDepex
deleted file mode 100644
index 1ba451cf..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenDepex
+++ /dev/null
@@ -1,14 +0,0 @@
-#!/usr/bin/env bash
-#python `dirname $0`/RunToolFromSource.py `basename $0` $*
-
-# If a ${PYTHON_COMMAND} command is available, use it in preference to python
-if command -v ${PYTHON_COMMAND} >/dev/null 2>&1; then
- python_exe=${PYTHON_COMMAND}
-fi
-
-full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a discussion of why $0 is not a good choice here
-dir=$(dirname "$full_cmd")
-cmd=${full_cmd##*/}
-
-export PYTHONPATH="$dir/../../Source/Python"
-exec "${python_exe:-python}" "$dir/../../Source/Python/$cmd/$cmd.py" "$@"
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenFds b/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenFds
deleted file mode 100644
index 1ba451cf..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenFds
+++ /dev/null
@@ -1,14 +0,0 @@
-#!/usr/bin/env bash
-#python `dirname $0`/RunToolFromSource.py `basename $0` $*
-
-# If a ${PYTHON_COMMAND} command is available, use it in preference to python
-if command -v ${PYTHON_COMMAND} >/dev/null 2>&1; then
- python_exe=${PYTHON_COMMAND}
-fi
-
-full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a discussion of why $0 is not a good choice here
-dir=$(dirname "$full_cmd")
-cmd=${full_cmd##*/}
-
-export PYTHONPATH="$dir/../../Source/Python"
-exec "${python_exe:-python}" "$dir/../../Source/Python/$cmd/$cmd.py" "$@"
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenFfs b/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenFfs
deleted file mode 100644
index 0945d86d..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenFfs
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/usr/bin/env bash
-
-full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a discussion of why $0 is not a good choice here
-dir=$(dirname "$full_cmd")
-cmd=${full_cmd##*/}
-
-if [ -n "$WORKSPACE" ] && [ -e "$WORKSPACE/Conf/BaseToolsCBinaries" ]
-then
- exec "$WORKSPACE/Conf/BaseToolsCBinaries/$cmd"
-elif [ -n "$WORKSPACE" ] && [ -e "$EDK_TOOLS_PATH/Source/C" ]
-then
- if [ ! -e "$EDK_TOOLS_PATH/Source/C/bin/$cmd" ]
- then
- echo "BaseTools C Tool binary was not found ($cmd)"
- echo "You may need to run:"
- echo " make -C $EDK_TOOLS_PATH/Source/C"
- else
- exec "$EDK_TOOLS_PATH/Source/C/bin/$cmd" "$@"
- fi
-elif [ -e "$dir/../../Source/C/bin/$cmd" ]
-then
- exec "$dir/../../Source/C/bin/$cmd" "$@"
-else
- echo "Unable to find the real '$cmd' to run"
- echo "This message was printed by"
- echo " $0"
- exit 127
-fi
-
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenFv b/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenFv
deleted file mode 100644
index 0945d86d..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenFv
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/usr/bin/env bash
-
-full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a discussion of why $0 is not a good choice here
-dir=$(dirname "$full_cmd")
-cmd=${full_cmd##*/}
-
-if [ -n "$WORKSPACE" ] && [ -e "$WORKSPACE/Conf/BaseToolsCBinaries" ]
-then
- exec "$WORKSPACE/Conf/BaseToolsCBinaries/$cmd"
-elif [ -n "$WORKSPACE" ] && [ -e "$EDK_TOOLS_PATH/Source/C" ]
-then
- if [ ! -e "$EDK_TOOLS_PATH/Source/C/bin/$cmd" ]
- then
- echo "BaseTools C Tool binary was not found ($cmd)"
- echo "You may need to run:"
- echo " make -C $EDK_TOOLS_PATH/Source/C"
- else
- exec "$EDK_TOOLS_PATH/Source/C/bin/$cmd" "$@"
- fi
-elif [ -e "$dir/../../Source/C/bin/$cmd" ]
-then
- exec "$dir/../../Source/C/bin/$cmd" "$@"
-else
- echo "Unable to find the real '$cmd' to run"
- echo "This message was printed by"
- echo " $0"
- exit 127
-fi
-
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenFw b/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenFw
deleted file mode 100644
index 0945d86d..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenFw
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/usr/bin/env bash
-
-full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a discussion of why $0 is not a good choice here
-dir=$(dirname "$full_cmd")
-cmd=${full_cmd##*/}
-
-if [ -n "$WORKSPACE" ] && [ -e "$WORKSPACE/Conf/BaseToolsCBinaries" ]
-then
- exec "$WORKSPACE/Conf/BaseToolsCBinaries/$cmd"
-elif [ -n "$WORKSPACE" ] && [ -e "$EDK_TOOLS_PATH/Source/C" ]
-then
- if [ ! -e "$EDK_TOOLS_PATH/Source/C/bin/$cmd" ]
- then
- echo "BaseTools C Tool binary was not found ($cmd)"
- echo "You may need to run:"
- echo " make -C $EDK_TOOLS_PATH/Source/C"
- else
- exec "$EDK_TOOLS_PATH/Source/C/bin/$cmd" "$@"
- fi
-elif [ -e "$dir/../../Source/C/bin/$cmd" ]
-then
- exec "$dir/../../Source/C/bin/$cmd" "$@"
-else
- echo "Unable to find the real '$cmd' to run"
- echo "This message was printed by"
- echo " $0"
- exit 127
-fi
-
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenPage b/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenPage
deleted file mode 100644
index 0945d86d..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenPage
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/usr/bin/env bash
-
-full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a discussion of why $0 is not a good choice here
-dir=$(dirname "$full_cmd")
-cmd=${full_cmd##*/}
-
-if [ -n "$WORKSPACE" ] && [ -e "$WORKSPACE/Conf/BaseToolsCBinaries" ]
-then
- exec "$WORKSPACE/Conf/BaseToolsCBinaries/$cmd"
-elif [ -n "$WORKSPACE" ] && [ -e "$EDK_TOOLS_PATH/Source/C" ]
-then
- if [ ! -e "$EDK_TOOLS_PATH/Source/C/bin/$cmd" ]
- then
- echo "BaseTools C Tool binary was not found ($cmd)"
- echo "You may need to run:"
- echo " make -C $EDK_TOOLS_PATH/Source/C"
- else
- exec "$EDK_TOOLS_PATH/Source/C/bin/$cmd" "$@"
- fi
-elif [ -e "$dir/../../Source/C/bin/$cmd" ]
-then
- exec "$dir/../../Source/C/bin/$cmd" "$@"
-else
- echo "Unable to find the real '$cmd' to run"
- echo "This message was printed by"
- echo " $0"
- exit 127
-fi
-
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenSec b/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenSec
deleted file mode 100644
index 0945d86d..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenSec
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/usr/bin/env bash
-
-full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a discussion of why $0 is not a good choice here
-dir=$(dirname "$full_cmd")
-cmd=${full_cmd##*/}
-
-if [ -n "$WORKSPACE" ] && [ -e "$WORKSPACE/Conf/BaseToolsCBinaries" ]
-then
- exec "$WORKSPACE/Conf/BaseToolsCBinaries/$cmd"
-elif [ -n "$WORKSPACE" ] && [ -e "$EDK_TOOLS_PATH/Source/C" ]
-then
- if [ ! -e "$EDK_TOOLS_PATH/Source/C/bin/$cmd" ]
- then
- echo "BaseTools C Tool binary was not found ($cmd)"
- echo "You may need to run:"
- echo " make -C $EDK_TOOLS_PATH/Source/C"
- else
- exec "$EDK_TOOLS_PATH/Source/C/bin/$cmd" "$@"
- fi
-elif [ -e "$dir/../../Source/C/bin/$cmd" ]
-then
- exec "$dir/../../Source/C/bin/$cmd" "$@"
-else
- echo "Unable to find the real '$cmd' to run"
- echo "This message was printed by"
- echo " $0"
- exit 127
-fi
-
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenVtf b/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenVtf
deleted file mode 100644
index 0945d86d..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/GenVtf
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/usr/bin/env bash
-
-full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a discussion of why $0 is not a good choice here
-dir=$(dirname "$full_cmd")
-cmd=${full_cmd##*/}
-
-if [ -n "$WORKSPACE" ] && [ -e "$WORKSPACE/Conf/BaseToolsCBinaries" ]
-then
- exec "$WORKSPACE/Conf/BaseToolsCBinaries/$cmd"
-elif [ -n "$WORKSPACE" ] && [ -e "$EDK_TOOLS_PATH/Source/C" ]
-then
- if [ ! -e "$EDK_TOOLS_PATH/Source/C/bin/$cmd" ]
- then
- echo "BaseTools C Tool binary was not found ($cmd)"
- echo "You may need to run:"
- echo " make -C $EDK_TOOLS_PATH/Source/C"
- else
- exec "$EDK_TOOLS_PATH/Source/C/bin/$cmd" "$@"
- fi
-elif [ -e "$dir/../../Source/C/bin/$cmd" ]
-then
- exec "$dir/../../Source/C/bin/$cmd" "$@"
-else
- echo "Unable to find the real '$cmd' to run"
- echo "This message was printed by"
- echo " $0"
- exit 127
-fi
-
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/GnuGenBootSector b/BaseTools/Bin/CYGWIN_NT-5.1-i686/GnuGenBootSector
deleted file mode 100644
index 0945d86d..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/GnuGenBootSector
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/usr/bin/env bash
-
-full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a discussion of why $0 is not a good choice here
-dir=$(dirname "$full_cmd")
-cmd=${full_cmd##*/}
-
-if [ -n "$WORKSPACE" ] && [ -e "$WORKSPACE/Conf/BaseToolsCBinaries" ]
-then
- exec "$WORKSPACE/Conf/BaseToolsCBinaries/$cmd"
-elif [ -n "$WORKSPACE" ] && [ -e "$EDK_TOOLS_PATH/Source/C" ]
-then
- if [ ! -e "$EDK_TOOLS_PATH/Source/C/bin/$cmd" ]
- then
- echo "BaseTools C Tool binary was not found ($cmd)"
- echo "You may need to run:"
- echo " make -C $EDK_TOOLS_PATH/Source/C"
- else
- exec "$EDK_TOOLS_PATH/Source/C/bin/$cmd" "$@"
- fi
-elif [ -e "$dir/../../Source/C/bin/$cmd" ]
-then
- exec "$dir/../../Source/C/bin/$cmd" "$@"
-else
- echo "Unable to find the real '$cmd' to run"
- echo "This message was printed by"
- echo " $0"
- exit 127
-fi
-
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/LzmaCompress b/BaseTools/Bin/CYGWIN_NT-5.1-i686/LzmaCompress
deleted file mode 100644
index 0945d86d..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/LzmaCompress
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/usr/bin/env bash
-
-full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a discussion of why $0 is not a good choice here
-dir=$(dirname "$full_cmd")
-cmd=${full_cmd##*/}
-
-if [ -n "$WORKSPACE" ] && [ -e "$WORKSPACE/Conf/BaseToolsCBinaries" ]
-then
- exec "$WORKSPACE/Conf/BaseToolsCBinaries/$cmd"
-elif [ -n "$WORKSPACE" ] && [ -e "$EDK_TOOLS_PATH/Source/C" ]
-then
- if [ ! -e "$EDK_TOOLS_PATH/Source/C/bin/$cmd" ]
- then
- echo "BaseTools C Tool binary was not found ($cmd)"
- echo "You may need to run:"
- echo " make -C $EDK_TOOLS_PATH/Source/C"
- else
- exec "$EDK_TOOLS_PATH/Source/C/bin/$cmd" "$@"
- fi
-elif [ -e "$dir/../../Source/C/bin/$cmd" ]
-then
- exec "$dir/../../Source/C/bin/$cmd" "$@"
-else
- echo "Unable to find the real '$cmd' to run"
- echo "This message was printed by"
- echo " $0"
- exit 127
-fi
-
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/LzmaF86Compress b/BaseTools/Bin/CYGWIN_NT-5.1-i686/LzmaF86Compress
deleted file mode 100644
index c712b131..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/LzmaF86Compress
+++ /dev/null
@@ -1,17 +0,0 @@
-#!/usr/bin/env bash
-#
-# This script will exec LzmaCompress tool with --f86 option that enables converter for x86 code.
-#
-# Copyright (c) 2012, Intel Corporation. All rights reserved.
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-
-for arg; do
- case $arg in
- -e|-d)
- set -- "$@" --f86
- break
- ;;
-esac
-
-exec LzmaCompress "$@"
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/RunBinToolFromBuildDir b/BaseTools/Bin/CYGWIN_NT-5.1-i686/RunBinToolFromBuildDir
deleted file mode 100644
index 4821d24f..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/RunBinToolFromBuildDir
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/usr/bin/env bash
-#python `dirname $0`/RunToolFromSource.py `basename $0` $*
-#exec `dirname $0`/../../../../C/bin/`basename $0` $*
-
-TOOL_BASENAME=`basename $0`
-
-if [ -n "$WORKSPACE" -a -e $WORKSPACE/Conf/BaseToolsCBinaries ]
-then
- exec $WORKSPACE/Conf/BaseToolsCBinaries/$TOOL_BASENAME
-elif [ -n "$WORKSPACE" -a -e $EDK_TOOLS_PATH/Source/C ]
-then
- if [ ! -e $EDK_TOOLS_PATH/Source/C/bin/$TOOL_BASENAME ]
- then
- echo BaseTools C Tool binary was not found \($TOOL_BASENAME\)
- echo You may need to run:
- echo " make -C $EDK_TOOLS_PATH/Source/C"
- else
- exec $EDK_TOOLS_PATH/Source/C/bin/$TOOL_BASENAME $*
- fi
-elif [ -e `dirname $0`/../../Source/C/bin/$TOOL_BASENAME ]
-then
- exec `dirname $0`/../../Source/C/bin/$TOOL_BASENAME $*
-else
- echo Unable to find the real \'$TOOL_BASENAME\' to run
- echo This message was printed by
- echo " $0"
- exit -1
-fi
-
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/RunToolFromSource b/BaseTools/Bin/CYGWIN_NT-5.1-i686/RunToolFromSource
deleted file mode 100644
index 2cb8b86a..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/RunToolFromSource
+++ /dev/null
@@ -1,5 +0,0 @@
-#!/usr/bin/env bash
-#python `dirname $0`/RunToolFromSource.py `basename $0` $*
-PYTHONPATH="`dirname $0`/../../Source/Python" \
- python "`dirname $0`/../../Source/Python"/`basename $0`/`basename $0`.py $*
-
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/Split b/BaseTools/Bin/CYGWIN_NT-5.1-i686/Split
deleted file mode 100644
index 0945d86d..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/Split
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/usr/bin/env bash
-
-full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a discussion of why $0 is not a good choice here
-dir=$(dirname "$full_cmd")
-cmd=${full_cmd##*/}
-
-if [ -n "$WORKSPACE" ] && [ -e "$WORKSPACE/Conf/BaseToolsCBinaries" ]
-then
- exec "$WORKSPACE/Conf/BaseToolsCBinaries/$cmd"
-elif [ -n "$WORKSPACE" ] && [ -e "$EDK_TOOLS_PATH/Source/C" ]
-then
- if [ ! -e "$EDK_TOOLS_PATH/Source/C/bin/$cmd" ]
- then
- echo "BaseTools C Tool binary was not found ($cmd)"
- echo "You may need to run:"
- echo " make -C $EDK_TOOLS_PATH/Source/C"
- else
- exec "$EDK_TOOLS_PATH/Source/C/bin/$cmd" "$@"
- fi
-elif [ -e "$dir/../../Source/C/bin/$cmd" ]
-then
- exec "$dir/../../Source/C/bin/$cmd" "$@"
-else
- echo "Unable to find the real '$cmd' to run"
- echo "This message was printed by"
- echo " $0"
- exit 127
-fi
-
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/TargetTool b/BaseTools/Bin/CYGWIN_NT-5.1-i686/TargetTool
deleted file mode 100644
index 1ba451cf..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/TargetTool
+++ /dev/null
@@ -1,14 +0,0 @@
-#!/usr/bin/env bash
-#python `dirname $0`/RunToolFromSource.py `basename $0` $*
-
-# If a ${PYTHON_COMMAND} command is available, use it in preference to python
-if command -v ${PYTHON_COMMAND} >/dev/null 2>&1; then
- python_exe=${PYTHON_COMMAND}
-fi
-
-full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a discussion of why $0 is not a good choice here
-dir=$(dirname "$full_cmd")
-cmd=${full_cmd##*/}
-
-export PYTHONPATH="$dir/../../Source/Python"
-exec "${python_exe:-python}" "$dir/../../Source/Python/$cmd/$cmd.py" "$@"
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/TianoCompress b/BaseTools/Bin/CYGWIN_NT-5.1-i686/TianoCompress
deleted file mode 100644
index 0945d86d..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/TianoCompress
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/usr/bin/env bash
-
-full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a discussion of why $0 is not a good choice here
-dir=$(dirname "$full_cmd")
-cmd=${full_cmd##*/}
-
-if [ -n "$WORKSPACE" ] && [ -e "$WORKSPACE/Conf/BaseToolsCBinaries" ]
-then
- exec "$WORKSPACE/Conf/BaseToolsCBinaries/$cmd"
-elif [ -n "$WORKSPACE" ] && [ -e "$EDK_TOOLS_PATH/Source/C" ]
-then
- if [ ! -e "$EDK_TOOLS_PATH/Source/C/bin/$cmd" ]
- then
- echo "BaseTools C Tool binary was not found ($cmd)"
- echo "You may need to run:"
- echo " make -C $EDK_TOOLS_PATH/Source/C"
- else
- exec "$EDK_TOOLS_PATH/Source/C/bin/$cmd" "$@"
- fi
-elif [ -e "$dir/../../Source/C/bin/$cmd" ]
-then
- exec "$dir/../../Source/C/bin/$cmd" "$@"
-else
- echo "Unable to find the real '$cmd' to run"
- echo "This message was printed by"
- echo " $0"
- exit 127
-fi
-
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/Trim b/BaseTools/Bin/CYGWIN_NT-5.1-i686/Trim
deleted file mode 100644
index b53b79bb..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/Trim
+++ /dev/null
@@ -1,14 +0,0 @@
-#!/usr/bin/env bash
-#python `dirname $0`/RunToolFromSource.py `basename $0` $*
-
-# If a ${PYTHON_COMMAND} command is available, use it in preference to python
-if command -v ${PYTHON_COMMAND} >/dev/null 2>&1; then
- python_exe=${PYTHON_COMMAND}
-fi
-
-full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a discussion of why $0 is not a good choice here
-dir=$(dirname "$full_cmd")
-exe=$(basename "$full_cmd")
-
-export PYTHONPATH="$dir/../../Source/Python"
-exec "${python_exe:-python}" "$dir/../../Source/Python/$exe/$exe.py" "$@"
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/VfrCompile b/BaseTools/Bin/CYGWIN_NT-5.1-i686/VfrCompile
deleted file mode 100644
index 0945d86d..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/VfrCompile
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/usr/bin/env bash
-
-full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a discussion of why $0 is not a good choice here
-dir=$(dirname "$full_cmd")
-cmd=${full_cmd##*/}
-
-if [ -n "$WORKSPACE" ] && [ -e "$WORKSPACE/Conf/BaseToolsCBinaries" ]
-then
- exec "$WORKSPACE/Conf/BaseToolsCBinaries/$cmd"
-elif [ -n "$WORKSPACE" ] && [ -e "$EDK_TOOLS_PATH/Source/C" ]
-then
- if [ ! -e "$EDK_TOOLS_PATH/Source/C/bin/$cmd" ]
- then
- echo "BaseTools C Tool binary was not found ($cmd)"
- echo "You may need to run:"
- echo " make -C $EDK_TOOLS_PATH/Source/C"
- else
- exec "$EDK_TOOLS_PATH/Source/C/bin/$cmd" "$@"
- fi
-elif [ -e "$dir/../../Source/C/bin/$cmd" ]
-then
- exec "$dir/../../Source/C/bin/$cmd" "$@"
-else
- echo "Unable to find the real '$cmd' to run"
- echo "This message was printed by"
- echo " $0"
- exit 127
-fi
-
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/VolInfo b/BaseTools/Bin/CYGWIN_NT-5.1-i686/VolInfo
deleted file mode 100644
index 0945d86d..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/VolInfo
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/usr/bin/env bash
-
-full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a discussion of why $0 is not a good choice here
-dir=$(dirname "$full_cmd")
-cmd=${full_cmd##*/}
-
-if [ -n "$WORKSPACE" ] && [ -e "$WORKSPACE/Conf/BaseToolsCBinaries" ]
-then
- exec "$WORKSPACE/Conf/BaseToolsCBinaries/$cmd"
-elif [ -n "$WORKSPACE" ] && [ -e "$EDK_TOOLS_PATH/Source/C" ]
-then
- if [ ! -e "$EDK_TOOLS_PATH/Source/C/bin/$cmd" ]
- then
- echo "BaseTools C Tool binary was not found ($cmd)"
- echo "You may need to run:"
- echo " make -C $EDK_TOOLS_PATH/Source/C"
- else
- exec "$EDK_TOOLS_PATH/Source/C/bin/$cmd" "$@"
- fi
-elif [ -e "$dir/../../Source/C/bin/$cmd" ]
-then
- exec "$dir/../../Source/C/bin/$cmd" "$@"
-else
- echo "Unable to find the real '$cmd' to run"
- echo "This message was printed by"
- echo " $0"
- exit 127
-fi
-
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/armcc_wrapper.py b/BaseTools/Bin/CYGWIN_NT-5.1-i686/armcc_wrapper.py
deleted file mode 100644
index 147c06bd..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/armcc_wrapper.py
+++ /dev/null
@@ -1,87 +0,0 @@
-#!/usr/bin/env python
-#
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-
-#
-# ARMCC tools do not support cygwin paths. Ths script converts cygwin paths to DOS paths
-# in any arguments.
-#
-# armcc_wrapper.py ToolToExec [command line to convert]
-#
-# anything with the / will be converted via cygpath cygwin call or manually.
-# -I/cygpath/c/example is a special case as you can not pass -I to cygpath
-#
-# ExceptionList if a tool takes an argument with a / add it to the exception list
-#
-from __future__ import print_function
-import sys
-import os
-import subprocess
-import pipes
-
-#
-# Convert using cygpath command line tool
-# Currently not used, but just in case we need it in the future
-#
-def ConvertCygPathToDosViacygpath(CygPath):
- p = subprocess.Popen("cygpath -m " + pipes.quote(CygPath), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT, close_fds=True)
- return p.stdout.read().strip()
-
-#
-#
-#
-def ConvertCygPathToDos(CygPath):
- if CygPath.find("/cygdrive/") == 0:
- # convert /cygdrive/c/Xyz to c:/Xyz
- DosPath = CygPath[10] + ':' + CygPath[11:]
- else:
- DosPath = CygPath
-
- # pipes.quote will add the extra \\ for us.
- return DosPath.replace('/', '\\')
-
-
-# we receive our options as a list, but we will be passing them to the shell as a line
-# this means we have to requote things as they will get one round of unquoting.
-# we can't set "shell=False" because we are running commands from the PATH and
-# if you don't use the shell you don't get a PATH search.
-def main(argv):
-
- # use 1st argument as name of tool to call
- Command = pipes.quote(sys.argv[1]);
-
- ExceptionList = ["/interwork"]
-
- for arg in argv:
- if arg.find('/') == -1:
- # if we don't need to convert just add to the command line
- Command = Command + ' ' + pipes.quote(arg)
- elif arg in ExceptionList:
- # if it is in the list, then don't do a cygpath
- # assembler stuff after --apcs has the /.
- Command = Command + ' ' + pipes.quote(arg)
- else:
- if ((arg[0] == '-') and (arg[1] == 'I' or arg[1] == 'i')):
- CygPath = arg[0] + arg[1] + ConvertCygPathToDos(arg[2:])
- else:
- CygPath = ConvertCygPathToDos(arg)
-
- Command = Command + ' ' + pipes.quote(CygPath)
-
- # call the real tool with the converted paths
- return subprocess.call(Command, shell=True)
-
-
-if __name__ == "__main__":
- try:
- ret = main(sys.argv[2:])
-
- except:
- print("exiting: exception from " + sys.argv[0])
- ret = 2
-
- sys.exit(ret)
-
diff --git a/BaseTools/Bin/CYGWIN_NT-5.1-i686/build b/BaseTools/Bin/CYGWIN_NT-5.1-i686/build
deleted file mode 100644
index 1ba451cf..00000000
--- a/BaseTools/Bin/CYGWIN_NT-5.1-i686/build
+++ /dev/null
@@ -1,14 +0,0 @@
-#!/usr/bin/env bash
-#python `dirname $0`/RunToolFromSource.py `basename $0` $*
-
-# If a ${PYTHON_COMMAND} command is available, use it in preference to python
-if command -v ${PYTHON_COMMAND} >/dev/null 2>&1; then
- python_exe=${PYTHON_COMMAND}
-fi
-
-full_cmd=${BASH_SOURCE:-$0} # see http://mywiki.wooledge.org/BashFAQ/028 for a discussion of why $0 is not a good choice here
-dir=$(dirname "$full_cmd")
-cmd=${full_cmd##*/}
-
-export PYTHONPATH="$dir/../../Source/Python"
-exec "${python_exe:-python}" "$dir/../../Source/Python/$cmd/$cmd.py" "$@"
diff --git a/BaseTools/BuildEnv b/BaseTools/BuildEnv
index 275f4c59..bd6235d7 100644
--- a/BaseTools/BuildEnv
+++ b/BaseTools/BuildEnv
@@ -20,7 +20,8 @@ SetWorkspace() {
#
# Set $WORKSPACE
#
- export WORKSPACE=`pwd`
+ WORKSPACE=$(pwd)
+ export WORKSPACE
return 0
@@ -35,8 +36,7 @@ RestorePreviousConfiguration() {
export CONF_PATH=$WORKSPACE/Conf
if [ ! -d $WORKSPACE/Conf ] && [ -n "$PACKAGES_PATH" ]
then
- PATH_LIST=${PACKAGES_PATH//:/ }
- for DIR in $PATH_LIST
+ for DIR in $(echo $PACKAGES_PATH | tr ':' ' ')
do
if [ -d $DIR/Conf ]
then
@@ -70,7 +70,13 @@ GenerateShellCodeToUpdatePath() {
OUTPUT_FILE=$1
echo "if [ -e $EDK_TOOLS_PATH_BIN ]" >> $OUTPUT_FILE
echo "then" >> $OUTPUT_FILE
- echo " if [ "\${PATH/$EDK_TOOLS_PATH_BIN/}" == "\$PATH" ]" >> $OUTPUT_FILE
+ echo " FOUND_TOOLS_PATH_BIN=0" >> $OUTPUT_FILE
+ echo " for DIR in \$(echo \$PATH | tr ':' ' '); do" >> $OUTPUT_FILE
+ echo " if [ \"\$DIR\" = \"$EDK_TOOLS_PATH_BIN\" ]; then" >> $OUTPUT_FILE
+ echo " FOUND_TOOLS_PATH_BIN=1" >> $OUTPUT_FILE
+ echo " fi" >> $OUTPUT_FILE
+ echo " done" >> $OUTPUT_FILE
+ echo " if [ \$FOUND_TOOLS_PATH_BIN = 0 ]" >> $OUTPUT_FILE
echo " then" >> $OUTPUT_FILE
echo " export PATH=$EDK_TOOLS_PATH_BIN:\$PATH" >> $OUTPUT_FILE
echo " fi" >> $OUTPUT_FILE
@@ -84,7 +90,7 @@ StoreCurrentConfiguration() {
#
OUTPUT_FILE=$CONF_PATH/BuildEnv.sh
#echo Storing current configuration into $OUTPUT_FILE
- echo "# Auto-generated by ${BASH_SOURCE[0]}" >| $OUTPUT_FILE
+ echo "# Auto-generated by BaseTools/BuildEnv" >| $OUTPUT_FILE
GenerateShellCodeToSetVariable WORKSPACE $OUTPUT_FILE
GenerateShellCodeToSetVariable EDK_TOOLS_PATH $OUTPUT_FILE
GenerateShellCodeToUpdatePath $OUTPUT_FILE
@@ -130,10 +136,9 @@ SetEdkToolsPath() {
#
# Try $PACKAGES_PATH
#
- if [ -n "$PACKAGES_PATH"]
+ if [ -n "$PACKAGES_PATH" ]
then
- PATH_LIST=${PACKAGES_PATH//:/ }
- for DIR in $PATH_LIST
+ for DIR in $(echo $PACKAGES_PATH | tr ':' ' ')
do
if [ -d $DIR/BaseTools ]
then
@@ -156,10 +161,7 @@ GetBaseToolsBinSubDir() {
#
# Figure out a uniq directory name from the uname command
#
- UNAME_DIRNAME=`uname -sm`
- UNAME_DIRNAME=${UNAME_DIRNAME// /-}
- UNAME_DIRNAME=${UNAME_DIRNAME//\//-}
- echo $UNAME_DIRNAME
+ echo $(uname -sm | tr ' ' '-')
}
GetEdkToolsPathBinDirectory() {
@@ -180,8 +182,6 @@ GetEdkToolsPathBinDirectory() {
AddDirToStartOfPath() {
DIRNAME=$1
- PATH=$DIRNAME:$DIRNAME:$DIRNAME:$PATH
- PATH=${PATH//$DIRNAME:/}
PATH=$DIRNAME:$PATH
export PATH
}
@@ -199,7 +199,7 @@ AddEdkToolsToPath() {
EDK_TOOLS_PATH_BIN=`GetEdkToolsPathBinDirectory`
# check if the edk2basetools pip package is available
- if $PYTHON_COMMAND -c "import edk2basetools" &> /dev/null; then
+ if $PYTHON_COMMAND -c "import edk2basetools" > /dev/null 2>&1; then
# if it is, use the pip version of the wrappers
echo "Using Pip Basetools"
AddDirToStartOfPath $EDK_TOOLS_PATH/BinPipWrappers/PosixLike
diff --git a/BaseTools/Conf/build_rule.template b/BaseTools/Conf/build_rule.template
index 6529e568..a009cb1b 100644
--- a/BaseTools/Conf/build_rule.template
+++ b/BaseTools/Conf/build_rule.template
@@ -145,7 +145,7 @@
$(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj
- "$(CC)" $(CC_FLAGS) $(CC_XIPFLAGS) -c -o ${dst} $(INC) ${src}
+ "$(CC)" $(DEPS_FLAGS) $(CC_FLAGS) $(CC_XIPFLAGS) -c -o ${dst} $(INC) ${src}
[C-Header-File]
@@ -342,7 +342,6 @@
$(OUTPUT_DIR)(+)$(MODULE_NAME).efi
- $(DEBUG_DIR)(+)$(MODULE_NAME).efi
$(OUTPUT_DIR)(+)$(MODULE_NAME).map
@@ -353,12 +352,12 @@
-$(CP) $(DEBUG_DIR)(+)*.pdb $(OUTPUT_DIR)
$(CP) ${src} $(DEBUG_DIR)(+)$(MODULE_NAME).debug
- $(OBJCOPY) $(OBJCOPY_STRIPFLAG) ${src}
+ "$(OBJCOPY)" $(OBJCOPY_STRIPFLAG) ${src}
#
#The below 2 lines are only needed for UNIXGCC tool chain, which generates PE image directly
#
- -$(OBJCOPY) $(OBJCOPY_ADDDEBUGFLAG) ${src}
+ -"$(OBJCOPY)" $(OBJCOPY_ADDDEBUGFLAG) ${src}
-$(CP) $(DEBUG_DIR)(+)$(MODULE_NAME).debug $(BIN_DIR)(+)$(MODULE_NAME_GUID).debug
"$(GENFW)" -e $(MODULE_TYPE) -o ${dst} ${src} $(GENFW_FLAGS)
@@ -647,5 +646,5 @@
"$(GENFW)" -o $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc -g $(MODULE_GUID) --hiibinpackage $(HII_BINARY_PACKAGES) $(GENFW_FLAGS)
"$(RC)" $(RC_FLAGS) $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc ${dst}
-
+
"$(GENFW)" -o $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc -g $(MODULE_GUID) --hiibinpackage $(HII_BINARY_PACKAGES) $(GENFW_FLAGS)
diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template
index b4389ad0..a96bc423 100755
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -15,48 +15,17 @@
#
# 2.00 - Initial version with changes for CI
# - Change RC path to use plugin
+# 3.00 - Update toolchains
+# - Add support for ARM and AARCH64 to CLANGDWARF
+# - Remove VS2008, VS2010, VS2012, VS2013, CLANG35, CLANG38, EBC
+# - Add GCC and GCCNOLTO
+# - Deprecate GCC48, GCC49 and GCC5.
#
-#!VERSION=2.00
+#!VERSION=3.00
IDENTIFIER = Default TOOL_CHAIN_CONF
# common path macros
-DEFINE VS2008_BIN = ENV(VS2008_PREFIX)Vc\bin
-DEFINE VS2008_DLL = ENV(VS2008_PREFIX)Common7\IDE;DEF(VS2008_BIN)
-DEFINE VS2008_BINX64 = DEF(VS2008_BIN)\x86_amd64
-DEFINE VS2008_BIN64 = DEF(VS2008_BIN)\x86_ia64
-
-DEFINE VS2008x86_BIN = ENV(VS2008_PREFIX)Vc\bin
-DEFINE VS2008x86_DLL = ENV(VS2008_PREFIX)Common7\IDE;DEF(VS2008x86_BIN)
-DEFINE VS2008x86_BINX64 = DEF(VS2008x86_BIN)\x86_amd64
-DEFINE VS2008x86_BIN64 = DEF(VS2008x86_BIN)\x86_ia64
-
-DEFINE VS2010_BIN = ENV(VS2010_PREFIX)Vc\bin
-DEFINE VS2010_DLL = ENV(VS2010_PREFIX)Common7\IDE;DEF(VS2010_BIN)
-DEFINE VS2010_BINX64 = DEF(VS2010_BIN)\x86_amd64
-DEFINE VS2010_BIN64 = DEF(VS2010_BIN)\x86_ia64
-
-DEFINE VS2010x86_BIN = ENV(VS2010_PREFIX)Vc\bin
-DEFINE VS2010x86_DLL = ENV(VS2010_PREFIX)Common7\IDE;DEF(VS2010x86_BIN)
-DEFINE VS2010x86_BINX64 = DEF(VS2010x86_BIN)\x86_amd64
-DEFINE VS2010x86_BIN64 = DEF(VS2010x86_BIN)\x86_ia64
-
-DEFINE VS2012_BIN = ENV(VS2012_PREFIX)Vc\bin
-DEFINE VS2012_DLL = ENV(VS2012_PREFIX)Common7\IDE;DEF(VS2012_BIN)
-DEFINE VS2012_BINX64 = DEF(VS2012_BIN)\x86_amd64
-
-DEFINE VS2012x86_BIN = ENV(VS2012_PREFIX)Vc\bin
-DEFINE VS2012x86_DLL = ENV(VS2012_PREFIX)Common7\IDE;DEF(VS2012x86_BIN)
-DEFINE VS2012x86_BINX64 = DEF(VS2012x86_BIN)\x86_amd64
-
-DEFINE VS2013_BIN = ENV(VS2013_PREFIX)Vc\bin
-DEFINE VS2013_DLL = ENV(VS2013_PREFIX)Common7\IDE;DEF(VS2013_BIN)
-DEFINE VS2013_BINX64 = DEF(VS2013_BIN)\x86_amd64
-
-DEFINE VS2013x86_BIN = ENV(VS2013_PREFIX)Vc\bin
-DEFINE VS2013x86_DLL = ENV(VS2013_PREFIX)Common7\IDE;DEF(VS2013x86_BIN)
-DEFINE VS2013x86_BINX64 = DEF(VS2013x86_BIN)\x86_amd64
-
DEFINE VS2015_BIN = ENV(VS2015_PREFIX)Vc\bin
DEFINE VS2015_DLL = ENV(VS2015_PREFIX)Common7\IDE;DEF(VS2015_BIN)
DEFINE VS2015_BINX64 = DEF(VS2015_BIN)\x86_amd64
@@ -89,18 +58,6 @@ DEFINE RC_PATH = ENV(WINSDK_PATH_FOR_RC_EXE)\rc.exe
DEFINE WINSDK_BIN = ENV(WINSDK_PREFIX)
DEFINE WINSDKx86_BIN = ENV(WINSDKx86_PREFIX)
-# Microsoft Visual Studio 2010
-DEFINE WINSDK7_BIN = ENV(WINSDK7_PREFIX)
-DEFINE WINSDK7x86_BIN = ENV(WINSDK7x86_PREFIX)
-
-# Microsoft Visual Studio 2012 Update 1 (required for rc.exe that was not included in the initial release)
-DEFINE WINSDK71_BIN = ENV(WINSDK71_PREFIX)
-DEFINE WINSDK71x86_BIN = ENV(WINSDK71x86_PREFIX)
-
-# Microsoft Visual Studio 2013 Professional Edition
-DEFINE WINSDK8_BIN = ENV(WINSDK8_PREFIX)x86\
-DEFINE WINSDK8x86_BIN = ENV(WINSDK8x86_PREFIX)x64
-
# Microsoft Visual Studio 2015 Professional Edition
DEFINE WINSDK81_BIN = ENV(WINSDK81_PREFIX)x86\
DEFINE WINSDK81x86_BIN = ENV(WINSDK81x86_PREFIX)x64
@@ -112,18 +69,9 @@ DEFINE WINSDK10_BIN = ENV(WINSDK10_PREFIX)DEF(VS_HOST)
# are used by other toolchains. An example is that ICC on Windows normally
# uses Microsoft's nmake.exe.
-# Some MS_VS_BIN options: DEF(VS2008_BIN), DEF(VS2008x86_BIN)
-DEFINE MS_VS_BIN = DEF(VS2008_BIN)
-# Some MS_VS_DLL options: DEF(VS2008_DLL), DEF(VS2008x86_DLL)
-DEFINE MS_VS_DLL = DEF(VS2008_DLL)
-
DEFINE WINDDK_BIN16 = ENV(WINDDK3790_PREFIX)bin16
DEFINE WINDDK_BINX64 = ENV(WINDDK3790_PREFIX)win64\x86\amd64
-DEFINE EBC_BIN = C:\Program Files\Intel\EBC\Bin
-DEFINE EBC_BINx86 = C:\Program Files (x86)\Intel\EBC\Bin
-
-
DEFINE CYGWIN_BIN = c:/cygwin/bin
DEFINE CYGWIN_BINIA32 = c:/cygwin/opt/tiano/i386-tiano-pe/i386-tiano-pe/bin/
DEFINE CYGWIN_BINX64 = c:/cygwin/opt/tiano/x86_64-pc-mingw64/x86_64-pc-mingw64/bin/
@@ -134,8 +82,13 @@ DEFINE GCC48_X64_PREFIX = ENV(GCC48_BIN)
DEFINE GCC49_IA32_PREFIX = ENV(GCC49_BIN)
DEFINE GCC49_X64_PREFIX = ENV(GCC49_BIN)
+DEFINE GCCNOLTO_IA32_PREFIX = ENV(GCCNOLTO_BIN)
+DEFINE GCCNOLTO_X64_PREFIX = ENV(GCCNOLTO_BIN)
+
DEFINE GCC5_IA32_PREFIX = ENV(GCC5_BIN)
DEFINE GCC5_X64_PREFIX = ENV(GCC5_BIN)
+DEFINE GCC_IA32_PREFIX = ENV(GCC_BIN)
+DEFINE GCC_X64_PREFIX = ENV(GCC_BIN)
DEFINE GCC_HOST_PREFIX = ENV(GCC_HOST_BIN)
DEFINE UNIX_IASL_BIN = ENV(IASL_PREFIX)iasl
@@ -155,10 +108,6 @@ DEFINE MSFT_ASLPP_FLAGS = /nologo /E /C /FIAutoGen.h
DEFINE MSFT_ASLCC_FLAGS = /nologo /c /FIAutoGen.h /TC /Dmain=ReferenceAcpiTable
DEFINE MSFT_ASLDLINK_FLAGS = /NODEFAULTLIB /ENTRY:ReferenceAcpiTable /SUBSYSTEM:CONSOLE
-DEFINE IPHONE_TOOLS = /Developer/Platforms/iPhoneOS.platform/Developer
-
-DEFINE SOURCERY_CYGWIN_TOOLS = /cygdrive/c/Program Files/CodeSourcery/Sourcery G++ Lite/bin
-
DEFINE DTCPP_BIN = ENV(DTCPP_PREFIX)cpp
DEFINE DTC_BIN = ENV(DTC_PREFIX)dtc
@@ -188,56 +137,15 @@ DEFINE DTC_BIN = ENV(DTC_PREFIX)dtc
#
# Supported Tool Chains
# =====================
-# VS2008 -win32- Requires:
-# Microsoft Visual Studio 2008 Team Suite Edition
-# Microsoft Windows Server 2003 Driver Development Kit (Microsoft WINDDK) version 3790.1830
-# Optional:
-# Required to build EBC drivers:
-# Intel(r) Compiler for Efi Byte Code (Intel(r) EBC Compiler)
-# Required to build platforms or ACPI tables:
-# Intel(r) ACPI Compiler (iasl.exe) from
-# https://acpica.org/downloads
-# VS2010 -win32- Requires:
-# Microsoft Visual Studio 2010 Premium Edition
-# Microsoft Windows Server 2003 Driver Development Kit (Microsoft WINDDK) version 3790.1830
-# Optional:
-# Required to build EBC drivers:
-# Intel(r) Compiler for Efi Byte Code (Intel(r) EBC Compiler)
-# Required to build platforms or ACPI tables:
-# Intel(r) ACPI Compiler (iasl.exe) from
-# https://acpica.org/downloads
-# VS2012 -win32- Requires:
-# Microsoft Visual Studio 2012 Professional Edition
-# Microsoft Windows Server 2003 Driver Development Kit (Microsoft WINDDK) version 3790.1830
-# Optional:
-# Required to build EBC drivers:
-# Intel(r) Compiler for Efi Byte Code (Intel(r) EBC Compiler)
-# Required to build platforms or ACPI tables:
-# Intel(r) ACPI Compiler (iasl.exe) from
-# https://acpica.org/downloads
-# VS2013 -win32- Requires:
-# Microsoft Visual Studio 2013 Professional Edition
-# Microsoft Windows Server 2003 Driver Development Kit (Microsoft WINDDK) version 3790.1830
-# Optional:
-# Required to build EBC drivers:
-# Intel(r) Compiler for Efi Byte Code (Intel(r) EBC Compiler)
-# Required to build platforms or ACPI tables:
-# Intel(r) ACPI Compiler (iasl.exe) from
-# https://acpica.org/downloads
# VS2015 -win32- Requires:
-# Microsoft Visual Studio 2015 Professional Edition
-# Microsoft Windows Server 2003 Driver Development Kit (Microsoft WINDDK) version 3790.1830
+# Microsoft Visual Studio 2015 Professional Edition, Update 3
# Optional:
-# Required to build EBC drivers:
-# Intel(r) Compiler for Efi Byte Code (Intel(r) EBC Compiler)
# Required to build platforms or ACPI tables:
# Intel(r) ACPI Compiler (iasl.exe) from
# https://acpica.org/downloads
# VS2017 -win32- Requires:
# Microsoft Visual Studio 2017 version 15.2 (15.4 for ARM64) or later
# Optional:
-# Required to build EBC drivers:
-# Intel(r) Compiler for Efi Byte Code (Intel(r) EBC Compiler)
# Required to build platforms or ACPI tables:
# Intel(r) ACPI Compiler (iasl.exe) from
# https://acpica.org/downloads
@@ -247,14 +155,46 @@ DEFINE DTC_BIN = ENV(DTC_PREFIX)dtc
# VS2019 -win32- Requires:
# Microsoft Visual Studio 2019 version 16.2 or later
# Optional:
-# Required to build EBC drivers:
-# Intel(r) Compiler for Efi Byte Code (Intel(r) EBC Compiler)
# Required to build platforms or ACPI tables:
# Intel(r) ACPI Compiler (iasl.exe) from
# https://acpica.org/downloads
# Note:
# Building of XIP firmware images for ARM/ARM64 is not currently supported (only applications).
# /FILEALIGN:4096 and other changes are needed for ARM firmware builds.
+# GCCNOLTO -Linux,Windows- Requires:
+# GCC 4.9 targeting x86_64-linux-gnu, aarch64-linux-gnu, or arm-linux-gnueabi
+# Optional:
+# Required to build platforms or ACPI tables:
+# Intel(r) ACPI Compiler from
+# https://acpica.org/downloads
+# GCC -Linux,Windows- Requires:
+# GCC 5 with LTO support, targeting x86_64-linux-gnu, aarch64-linux-gnu, arm-linux-gnueabi, riscv64-linux-gnu or loongarch64-linux-gnu
+# Optional:
+# Required to build platforms or ACPI tables:
+# Intel(r) ACPI Compiler from
+# https://acpica.org/downloads
+#
+# CLANGPDB -Linux, Windows, Mac- Requires:
+# Clang 9 or above from http://releases.llvm.org/
+# Optional:
+# Required to compile nasm source:
+# nasm compiler from
+# NASM -- http://www.nasm.us/
+# CLANGDWARF -Linux, Windows, Mac- Requires:
+# Clang 9 or above from http://releases.llvm.org/
+# Optional:
+# Required to compile nasm source:
+# nasm compiler from
+# NASM -- http://www.nasm.us/
+# VS2015x86 -win64- Requires:
+# Microsoft Visual Studio 2015 (x86) Update 3 or above
+# Optional:
+# Required to build platforms or ACPI tables:
+# Intel(r) ACPI Compiler (iasl.exe) from
+# https://acpica.org/downloads
+#
+# Deprecated Tool Chains
+# ======================
# GCC48 -Linux,Windows- Requires:
# GCC 4.8 targeting x86_64-linux-gnu, aarch64-linux-gnu, or arm-linux-gnueabi
# Optional:
@@ -274,68 +214,6 @@ DEFINE DTC_BIN = ENV(DTC_PREFIX)dtc
# Intel(r) ACPI Compiler from
# https://acpica.org/downloads
#
-# CLANG35 -Linux,Windows- Requires:
-# Clang v3.5 or later, and GNU binutils targeting aarch64-linux-gnu or arm-linux-gnueabi
-# Optional:
-# Required to build platforms or ACPI tables:
-# Intel(r) ACPI Compiler from
-# https://acpica.org/downloads
-# CLANG38 -Linux- Requires:
-# Clang v3.8, LLVMgold plugin and GNU binutils 2.26 targeting x86_64-linux-gnu, aarch64-linux-gnu or arm-linux-gnueabi
-# Clang v3.9 or later, LLVMgold plugin and GNU binutils 2.28 targeting x86_64-linux-gnu, aarch64-linux-gnu or arm-linux-gnueabi
-# Optional:
-# Required to build platforms or ACPI tables:
-# Intel(r) ACPI Compiler from
-# https://acpica.org/downloads
-# CLANGPDB -Linux, Windows, Mac- Requires:
-# Clang 9 or above from http://releases.llvm.org/
-# Optional:
-# Required to compile nasm source:
-# nasm compiler from
-# NASM -- http://www.nasm.us/
-# CLANGDWARF -Linux, Windows, Mac- Requires:
-# Clang 9 or above from http://releases.llvm.org/
-# Optional:
-# Required to compile nasm source:
-# nasm compiler from
-# NASM -- http://www.nasm.us/
-# VS2008x86 -win64- Requires:
-# Microsoft Visual Studio 2008 (x86)
-# Microsoft Windows Server 2003 Driver Development Kit (Microsoft WINDDK) version 3790.1830
-# Optional:
-# Required to build platforms or ACPI tables:
-# Intel(r) ACPI Compiler (iasl.exe) from
-# https://acpica.org/downloads
-# VS2010x86 -win64- Requires:
-# Microsoft Visual Studio 2010 (x86) Premium Edition
-# Microsoft Windows Server 2003 Driver Development Kit (Microsoft WINDDK) version 3790.1830
-# Optional:
-# Required to build platforms or ACPI tables:
-# Intel(r) ACPI Compiler (iasl.exe) from
-# https://acpica.org/downloads
-# VS2012x86 -win64- Requires:
-# Microsoft Visual Studio 2012 (x86) Professional Edition
-# Microsoft Windows Server 2003 Driver Development Kit (Microsoft WINDDK) version 3790.1830
-# Optional:
-# Required to build platforms or ACPI tables:
-# Intel(r) ACPI Compiler (iasl.exe) from
-# https://acpica.org/downloads
-# VS2013x86 -win64- Requires:
-# Microsoft Visual Studio 2013 (x86) Professional Edition
-# Microsoft Windows Server 2003 Driver Development Kit (Microsoft WINDDK) version 3790.1830
-# Optional:
-# Required to build platforms or ACPI tables:
-# Intel(r) ACPI Compiler (iasl.exe) from
-# https://acpica.org/downloads
-# VS2015x86 -win64- Requires:
-# Microsoft Visual Studio 2015 (x86) Update 2 or above
-# Microsoft Windows Server 2003 Driver Development Kit (Microsoft WINDDK) version 3790.1830
-# Optional:
-# Required to build platforms or ACPI tables:
-# Intel(r) ACPI Compiler (iasl.exe) from
-# https://acpica.org/downloads
-# * Commented out - All versions of VS2005 use the same standard install directory
-#
####################################################################################
####################################################################################
#
@@ -356,22 +234,6 @@ DEFINE DTC_BIN = ENV(DTC_PREFIX)dtc
####################################################################################
####################################################################################
#
-# Intel EFI Byte Code Compiler (Template)
-#
-####################################################################################
-# *_*_EBC_*_FAMILY = INTEL
-#
-# *_*_EBC_PP_PATH = C:\Program Files\Intel\EBC\Bin\iec.exe
-# *_*_EBC_CC_PATH = C:\Program Files\Intel\EBC\Bin\iec.exe
-# *_*_EBC_SLINK_PATH = C:\Program Files\Intel\EBC\Bin\link.exe
-#
-# *_*_EBC_SLINK_FLAGS = /lib /NOLOGO /MACHINE:EBC
-# *_*_EBC_PP_FLAGS = /nologo /E /TC /FIAutoGen.h
-# *_*_EBC_CC_FLAGS = /nologo /FAcs /c /W3 /WX /FIAutoGen.h
-# *_*_EBC_DLINK_FLAGS = "C:\Program Files\Intel\EBC\Lib\EbcLib.lib" /NOLOGO /MACHINE:EBC /OPT:REF /NODEFAULTLIB /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /ALIGN:32 /DRIVER
-#
-####################################################################################
-#
# Intel ACPI Source Language Compiler (Template)
#
####################################################################################
@@ -390,906 +252,6 @@ DEFINE DTC_BIN = ENV(DTC_PREFIX)dtc
#
####################################################################################
-####################################################################################
-#
-# Microsoft Visual Studio 2008
-#
-# VS2008 - Microsoft Visual Studio 2005 All Edition, including Standard, Professional, Express, TeamSuite
-# ASL - Intel ACPI Source Language Compiler
-####################################################################################
-# VS2008 - Microsoft Visual Studio 2008 ALL Edition, including Standard, Professional, Express, TeamSuite
-*_VS2008_*_*_FAMILY = MSFT
-
-*_VS2008_*_MAKE_PATH = DEF(VS2008_BIN)\nmake.exe
-*_VS2008_*_MAKE_FLAGS = /nologo
-*_VS2008_*_RC_PATH = DEF(WINSDK_BIN)\rc.exe
-
-*_VS2008_*_SLINK_FLAGS = /NOLOGO /LTCG
-*_VS2008_*_APP_FLAGS = /nologo /E /TC
-*_VS2008_*_PP_FLAGS = /nologo /E /TC /FIAutoGen.h
-*_VS2008_*_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h
-*_VS2008_*_DEPS_FLAGS = DEF(MSFT_DEPS_FLAGS)
-*_VS2008_*_ASM16_PATH = DEF(VS2008_BIN)\ml.exe
-
-##################
-# ASL definitions
-##################
-*_VS2008_*_ASL_PATH = DEF(DEFAULT_WIN_ASL_BIN)
-*_VS2008_*_ASL_FLAGS = DEF(DEFAULT_WIN_ASL_FLAGS)
-*_VS2008_*_ASL_OUTFLAGS = DEF(DEFAULT_WIN_ASL_OUTFLAGS)
-*_VS2008_*_ASLCC_FLAGS = DEF(MSFT_ASLCC_FLAGS)
-*_VS2008_*_ASLPP_FLAGS = DEF(MSFT_ASLPP_FLAGS)
-*_VS2008_*_ASLDLINK_FLAGS = DEF(MSFT_ASLDLINK_FLAGS)
-
-##################
-# IA32 definitions
-##################
-*_VS2008_IA32_*_DLL = DEF(VS2008_DLL)
-
-*_VS2008_IA32_CC_PATH = DEF(VS2008_BIN)\cl.exe
-*_VS2008_IA32_VFRPP_PATH = DEF(VS2008_BIN)\cl.exe
-*_VS2008_IA32_SLINK_PATH = DEF(VS2008_BIN)\lib.exe
-*_VS2008_IA32_DLINK_PATH = DEF(VS2008_BIN)\link.exe
-*_VS2008_IA32_APP_PATH = DEF(VS2008_BIN)\cl.exe
-*_VS2008_IA32_PP_PATH = DEF(VS2008_BIN)\cl.exe
-*_VS2008_IA32_ASM_PATH = DEF(VS2008_BIN)\ml.exe
-*_VS2008_IA32_ASLCC_PATH = DEF(VS2008_BIN)\cl.exe
-*_VS2008_IA32_ASLPP_PATH = DEF(VS2008_BIN)\cl.exe
-*_VS2008_IA32_ASLDLINK_PATH = DEF(VS2008_BIN)\link.exe
-
- DEBUG_VS2008_IA32_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm
-RELEASE_VS2008_IA32_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF
-NOOPT_VS2008_IA32_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /Od
-
- DEBUG_VS2008_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi
-RELEASE_VS2008_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd
-NOOPT_VS2008_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi
-
- DEBUG_VS2008_IA32_NASM_FLAGS = -Ox -f win32 -g
-RELEASE_VS2008_IA32_NASM_FLAGS = -Ox -f win32
-NOOPT_VS2008_IA32_NASM_FLAGS = -O0 -f win32 -g
-
- DEBUG_VS2008_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-RELEASE_VS2008_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data
-NOOPT_VS2008_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-
-##################
-# X64 definitions
-##################
-*_VS2008_X64_*_DLL = DEF(VS2008_DLL)
-
-*_VS2008_X64_CC_PATH = DEF(VS2008_BINX64)\cl.exe
-*_VS2008_X64_PP_PATH = DEF(VS2008_BINX64)\cl.exe
-*_VS2008_X64_APP_PATH = DEF(VS2008_BINX64)\cl.exe
-*_VS2008_X64_VFRPP_PATH = DEF(VS2008_BINX64)\cl.exe
-*_VS2008_X64_ASM_PATH = DEF(VS2008_BINX64)\ml64.exe
-*_VS2008_X64_SLINK_PATH = DEF(VS2008_BINX64)\lib.exe
-*_VS2008_X64_DLINK_PATH = DEF(VS2008_BINX64)\link.exe
-*_VS2008_X64_ASLCC_PATH = DEF(VS2008_BINX64)\cl.exe
-*_VS2008_X64_ASLPP_PATH = DEF(VS2008_BINX64)\cl.exe
-*_VS2008_X64_ASLDLINK_PATH = DEF(VS2008_BINX64)\link.exe
-
- DEBUG_VS2008_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Z7
-RELEASE_VS2008_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF
-NOOPT_VS2008_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Z7 /Od
-
- DEBUG_VS2008_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi
-RELEASE_VS2008_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd
-NOOPT_VS2008_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi
-
- DEBUG_VS2008_X64_NASM_FLAGS = -Ox -f win64 -g
-RELEASE_VS2008_X64_NASM_FLAGS = -Ox -f win64
-NOOPT_VS2008_X64_NASM_FLAGS = -O0 -f win64 -g
-
- DEBUG_VS2008_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-RELEASE_VS2008_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data
-NOOPT_VS2008_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-
-##################
-# EBC definitions
-##################
-*_VS2008_EBC_*_FAMILY = INTEL
-*_VS2008_EBC_*_DLL = DEF(VS2008_DLL)
-
-*_VS2008_EBC_PP_PATH = DEF(EBC_BIN)\iec.exe
-*_VS2008_EBC_VFRPP_PATH = DEF(EBC_BIN)\iec.exe
-*_VS2008_EBC_CC_PATH = DEF(EBC_BIN)\iec.exe
-*_VS2008_EBC_SLINK_PATH = DEF(VS2008_BIN)\link.exe
-*_VS2008_EBC_DLINK_PATH = DEF(VS2008_BIN)\link.exe
-
-*_VS2008_EBC_PP_FLAGS = /nologo /E /TC /FIAutoGen.h
-*_VS2008_EBC_CC_FLAGS = /nologo /c /WX /W3 /FIAutoGen.h /D$(MODULE_ENTRY_POINT)=$(ARCH_ENTRY_POINT)
-*_VS2008_EBC_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h
-*_VS2008_EBC_SLINK_FLAGS = /lib /NOLOGO /MACHINE:EBC
-*_VS2008_EBC_DLINK_FLAGS = "C:\Program Files\Intel\EBC\Lib\EbcLib.lib" /NOLOGO /NODEFAULTLIB /MACHINE:EBC /OPT:REF /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /MAP /ALIGN:32 /DRIVER
-
-
-####################################################################################
-# VS2008x86 - Microsoft Visual Studio 2008 (x86) with Intel ASL
-# ASL - Intel ACPI Source Language Compiler (iasl.exe)
-####################################################################################
-# VS2008x86 - Microsoft Visual Studio 2008 (x86) ALL Edition with Intel ASL
-*_VS2008x86_*_*_FAMILY = MSFT
-
-*_VS2008x86_*_MAKE_PATH = DEF(VS2008x86_BIN)\nmake.exe
-*_VS2008x86_*_MAKE_FLAGS = /nologo
-*_VS2008x86_*_RC_PATH = DEF(WINSDK_BIN)\rc.exe
-
-*_VS2008x86_*_SLINK_FLAGS = /NOLOGO /LTCG
-*_VS2008x86_*_APP_FLAGS = /nologo /E /TC
-*_VS2008x86_*_PP_FLAGS = /nologo /E /TC /FIAutoGen.h
-*_VS2008x86_*_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h
-*_VS2008x86_*_DEPS_FLAGS = DEF(MSFT_DEPS_FLAGS)
-*_VS2008x86_*_ASM16_PATH = DEF(VS2008x86_BIN)\ml.exe
-
-##################
-# ASL definitions
-##################
-*_VS2008x86_*_ASL_PATH = DEF(WIN_IASL_BIN)
-*_VS2008x86_*_ASL_FLAGS = DEF(DEFAULT_WIN_ASL_FLAGS)
-*_VS2008x86_*_ASL_OUTFLAGS = DEF(DEFAULT_WIN_ASL_OUTFLAGS)
-*_VS2008x86_*_ASLCC_FLAGS = DEF(MSFT_ASLCC_FLAGS)
-*_VS2008x86_*_ASLPP_FLAGS = DEF(MSFT_ASLPP_FLAGS)
-*_VS2008x86_*_ASLDLINK_FLAGS = DEF(MSFT_ASLDLINK_FLAGS)
-
-##################
-# IA32 definitions
-##################
-*_VS2008x86_IA32_*_DLL = DEF(VS2008x86_DLL)
-
-*_VS2008x86_IA32_CC_PATH = DEF(VS2008x86_BIN)\cl.exe
-*_VS2008x86_IA32_VFRPP_PATH = DEF(VS2008x86_BIN)\cl.exe
-*_VS2008x86_IA32_ASLCC_PATH = DEF(VS2008x86_BIN)\cl.exe
-*_VS2008x86_IA32_ASLPP_PATH = DEF(VS2008x86_BIN)\cl.exe
-*_VS2008x86_IA32_SLINK_PATH = DEF(VS2008x86_BIN)\lib.exe
-*_VS2008x86_IA32_DLINK_PATH = DEF(VS2008x86_BIN)\link.exe
-*_VS2008x86_IA32_ASLDLINK_PATH= DEF(VS2008x86_BIN)\link.exe
-*_VS2008x86_IA32_APP_PATH = DEF(VS2008x86_BIN)\cl.exe
-*_VS2008x86_IA32_PP_PATH = DEF(VS2008x86_BIN)\cl.exe
-*_VS2008x86_IA32_ASM_PATH = DEF(VS2008x86_BIN)\ml.exe
-
- DEBUG_VS2008x86_IA32_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Z7
-RELEASE_VS2008x86_IA32_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF
-NOOPT_VS2008x86_IA32_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Z7 /Od
-
- DEBUG_VS2008x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi
-RELEASE_VS2008x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd
-NOOPT_VS2008x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi
-
- DEBUG_VS2008x86_IA32_NASM_FLAGS = -Ox -f win32 -g
-RELEASE_VS2008x86_IA32_NASM_FLAGS = -Ox -f win32
-NOOPT_VS2008x86_IA32_NASM_FLAGS = -O0 -f win32 -g
-
- DEBUG_VS2008x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-RELEASE_VS2008x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data
-NOOPT_VS2008x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-
-##################
-# X64 definitions
-##################
-*_VS2008x86_X64_*_DLL = DEF(VS2008x86_DLL)
-
-*_VS2008x86_X64_CC_PATH = DEF(VS2008x86_BINX64)\cl.exe
-*_VS2008x86_X64_PP_PATH = DEF(VS2008x86_BINX64)\cl.exe
-*_VS2008x86_X64_APP_PATH = DEF(VS2008x86_BINX64)\cl.exe
-*_VS2008x86_X64_VFRPP_PATH = DEF(VS2008x86_BINX64)\cl.exe
-*_VS2008x86_X64_ASLCC_PATH = DEF(VS2008x86_BINX64)\cl.exe
-*_VS2008x86_X64_ASLPP_PATH = DEF(VS2008x86_BINX64)\cl.exe
-*_VS2008x86_X64_ASM_PATH = DEF(VS2008x86_BINX64)\ml64.exe
-*_VS2008x86_X64_SLINK_PATH = DEF(VS2008x86_BINX64)\lib.exe
-*_VS2008x86_X64_DLINK_PATH = DEF(VS2008x86_BINX64)\link.exe
-*_VS2008x86_X64_ASLDLINK_PATH = DEF(VS2008x86_BINX64)\link.exe
-
- DEBUG_VS2008x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Z7
-RELEASE_VS2008x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF
-NOOPT_VS2008x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Z7 /Od
- DEBUG_VS2008x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi
-RELEASE_VS2008x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd
-NOOPT_VS2008x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi
-
- DEBUG_VS2008x86_X64_NASM_FLAGS = -Ox -f win64 -g
-RELEASE_VS2008x86_X64_NASM_FLAGS = -Ox -f win64
-NOOPT_VS2008x86_X64_NASM_FLAGS = -O0 -f win64 -g
-
- DEBUG_VS2008x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-RELEASE_VS2008x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data
-NOOPT_VS2008x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-
-##################
-# EBC definitions
-##################
-*_VS2008x86_EBC_*_FAMILY = INTEL
-*_VS2008x86_EBC_*_DLL = DEF(VS2008x86_DLL)
-
-*_VS2008x86_EBC_PP_PATH = DEF(EBC_BINx86)\iec.exe
-*_VS2008x86_EBC_VFRPP_PATH = DEF(EBC_BINx86)\iec.exe
-*_VS2008x86_EBC_CC_PATH = DEF(EBC_BINx86)\iec.exe
-*_VS2008x86_EBC_SLINK_PATH = DEF(VS2008x86_BIN)\link.exe
-*_VS2008x86_EBC_DLINK_PATH = DEF(VS2008x86_BIN)\link.exe
-
-*_VS2008x86_EBC_PP_FLAGS = /nologo /E /TC /FIAutoGen.h
-*_VS2008x86_EBC_CC_FLAGS = /nologo /c /WX /W3 /FIAutoGen.h /D$(MODULE_ENTRY_POINT)=$(ARCH_ENTRY_POINT)
-*_VS2008x86_EBC_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h
-*_VS2008x86_EBC_SLINK_FLAGS = /lib /NOLOGO /MACHINE:EBC
-*_VS2008x86_EBC_DLINK_FLAGS = "C:\Program Files (x86)\Intel\EBC\Lib\EbcLib.lib" /NOLOGO /NODEFAULTLIB /MACHINE:EBC /OPT:REF /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /MAP /ALIGN:32 /DRIVER
-
-
-
-####################################################################################
-#
-# Microsoft Visual Studio 2010
-#
-# VS2010 - Microsoft Visual Studio 2010 Premium Edition with Intel ASL
-# ASL - Intel ACPI Source Language Compiler
-####################################################################################
-# VS2010 - Microsoft Visual Studio 2010 Premium Edition
-*_VS2010_*_*_FAMILY = MSFT
-
-*_VS2010_*_MAKE_PATH = DEF(VS2010_BIN)\nmake.exe
-*_VS2010_*_MAKE_FLAGS = /nologo
-*_VS2010_*_RC_PATH = DEF(WINSDK7_BIN)\rc.exe
-
-*_VS2010_*_SLINK_FLAGS = /NOLOGO /LTCG
-*_VS2010_*_APP_FLAGS = /nologo /E /TC
-*_VS2010_*_PP_FLAGS = /nologo /E /TC /FIAutoGen.h
-*_VS2010_*_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h
-*_VS2010_*_DEPS_FLAGS = DEF(MSFT_DEPS_FLAGS)
-*_VS2010_*_ASM16_PATH = DEF(VS2010_BIN)\ml.exe
-
-##################
-# ASL definitions
-##################
-*_VS2010_*_ASL_PATH = DEF(DEFAULT_WIN_ASL_BIN)
-*_VS2010_*_ASL_FLAGS = DEF(DEFAULT_WIN_ASL_FLAGS)
-*_VS2010_*_ASL_OUTFLAGS = DEF(DEFAULT_WIN_ASL_OUTFLAGS)
-*_VS2010_*_ASLCC_FLAGS = DEF(MSFT_ASLCC_FLAGS)
-*_VS2010_*_ASLPP_FLAGS = DEF(MSFT_ASLPP_FLAGS)
-*_VS2010_*_ASLDLINK_FLAGS = DEF(MSFT_ASLDLINK_FLAGS)
-
-##################
-# IA32 definitions
-##################
-*_VS2010_IA32_*_DLL = DEF(VS2010_DLL)
-
-*_VS2010_IA32_CC_PATH = DEF(VS2010_BIN)\cl.exe
-*_VS2010_IA32_VFRPP_PATH = DEF(VS2010_BIN)\cl.exe
-*_VS2010_IA32_SLINK_PATH = DEF(VS2010_BIN)\lib.exe
-*_VS2010_IA32_DLINK_PATH = DEF(VS2010_BIN)\link.exe
-*_VS2010_IA32_APP_PATH = DEF(VS2010_BIN)\cl.exe
-*_VS2010_IA32_PP_PATH = DEF(VS2010_BIN)\cl.exe
-*_VS2010_IA32_ASM_PATH = DEF(VS2010_BIN)\ml.exe
-*_VS2010_IA32_ASLCC_PATH = DEF(VS2010_BIN)\cl.exe
-*_VS2010_IA32_ASLPP_PATH = DEF(VS2010_BIN)\cl.exe
-*_VS2010_IA32_ASLDLINK_PATH = DEF(VS2010_BIN)\link.exe
-
- DEBUG_VS2010_IA32_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Z7
-RELEASE_VS2010_IA32_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF
-NOOPT_VS2010_IA32_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /Od
-
- DEBUG_VS2010_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi
-RELEASE_VS2010_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd
-NOOPT_VS2010_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi
-
- DEBUG_VS2010_IA32_NASM_FLAGS = -Ox -f win32 -g
-RELEASE_VS2010_IA32_NASM_FLAGS = -Ox -f win32
-NOOPT_VS2010_IA32_NASM_FLAGS = -O0 -f win32 -g
-
- DEBUG_VS2010_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-RELEASE_VS2010_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data
-NOOPT_VS2010_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-
-##################
-# X64 definitions
-##################
-*_VS2010_X64_*_DLL = DEF(VS2010_DLL)
-
-*_VS2010_X64_CC_PATH = DEF(VS2010_BINX64)\cl.exe
-*_VS2010_X64_PP_PATH = DEF(VS2010_BINX64)\cl.exe
-*_VS2010_X64_APP_PATH = DEF(VS2010_BINX64)\cl.exe
-*_VS2010_X64_VFRPP_PATH = DEF(VS2010_BINX64)\cl.exe
-*_VS2010_X64_ASM_PATH = DEF(VS2010_BINX64)\ml64.exe
-*_VS2010_X64_SLINK_PATH = DEF(VS2010_BINX64)\lib.exe
-*_VS2010_X64_DLINK_PATH = DEF(VS2010_BINX64)\link.exe
-*_VS2010_X64_ASLCC_PATH = DEF(VS2010_BINX64)\cl.exe
-*_VS2010_X64_ASLPP_PATH = DEF(VS2010_BINX64)\cl.exe
-*_VS2010_X64_ASLDLINK_PATH = DEF(VS2010_BINX64)\link.exe
-
- DEBUG_VS2010_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Z7
-RELEASE_VS2010_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF
-NOOPT_VS2010_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Z7 /Od
-
- DEBUG_VS2010_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi
-RELEASE_VS2010_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd
-NOOPT_VS2010_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi
-
- DEBUG_VS2010_X64_NASM_FLAGS = -Ox -f win64 -g
-RELEASE_VS2010_X64_NASM_FLAGS = -Ox -f win64
-NOOPT_VS2010_X64_NASM_FLAGS = -O0 -f win64 -g
-
- DEBUG_VS2010_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-RELEASE_VS2010_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data
-NOOPT_VS2010_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-
-##################
-# EBC definitions
-##################
-*_VS2010_EBC_*_FAMILY = INTEL
-*_VS2010_EBC_*_DLL = DEF(VS2010_DLL)
-
-*_VS2010_EBC_PP_PATH = DEF(EBC_BIN)\iec.exe
-*_VS2010_EBC_VFRPP_PATH = DEF(EBC_BIN)\iec.exe
-*_VS2010_EBC_CC_PATH = DEF(EBC_BIN)\iec.exe
-*_VS2010_EBC_SLINK_PATH = DEF(VS2010_BIN)\link.exe
-*_VS2010_EBC_DLINK_PATH = DEF(VS2010_BIN)\link.exe
-
-*_VS2010_EBC_PP_FLAGS = /nologo /E /TC /FIAutoGen.h
-*_VS2010_EBC_CC_FLAGS = /nologo /c /WX /W3 /FIAutoGen.h /D$(MODULE_ENTRY_POINT)=$(ARCH_ENTRY_POINT)
-*_VS2010_EBC_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h
-*_VS2010_EBC_SLINK_FLAGS = /lib /NOLOGO /MACHINE:EBC
-*_VS2010_EBC_DLINK_FLAGS = "C:\Program Files\Intel\EBC\Lib\EbcLib.lib" /NOLOGO /NODEFAULTLIB /MACHINE:EBC /OPT:REF /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /MAP /ALIGN:32 /DRIVER
-
-
-####################################################################################
-# VS2010x86 - Microsoft Visual Studio 2010 (x86) with Intel ASL
-# ASL - Intel ACPI Source Language Compiler (iasl.exe)
-####################################################################################
-# VS2010x86 - Microsoft Visual Studio 2010 (x86) ALL Edition with Intel ASL
-*_VS2010x86_*_*_FAMILY = MSFT
-
-*_VS2010x86_*_MAKE_PATH = DEF(VS2010x86_BIN)\nmake.exe
-*_VS2010x86_*_MAKE_FLAGS = /nologo
-*_VS2010x86_*_RC_PATH = DEF(WINSDK7x86_BIN)\rc.exe
-
-*_VS2010x86_*_SLINK_FLAGS = /NOLOGO /LTCG
-*_VS2010x86_*_APP_FLAGS = /nologo /E /TC
-*_VS2010x86_*_PP_FLAGS = /nologo /E /TC /FIAutoGen.h
-*_VS2010x86_*_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h
-*_VS2010x86_*_DEPS_FLAGS = DEF(MSFT_DEPS_FLAGS)
-*_VS2010x86_*_ASM16_PATH = DEF(VS2010x86_BIN)\ml.exe
-
-##################
-# ASL definitions
-##################
-*_VS2010x86_*_ASL_PATH = DEF(WIN_IASL_BIN)
-*_VS2010x86_*_ASL_FLAGS = DEF(DEFAULT_WIN_ASL_FLAGS)
-*_VS2010x86_*_ASL_OUTFLAGS = DEF(DEFAULT_WIN_ASL_OUTFLAGS)
-*_VS2010x86_*_ASLCC_FLAGS = DEF(MSFT_ASLCC_FLAGS)
-*_VS2010x86_*_ASLPP_FLAGS = DEF(MSFT_ASLPP_FLAGS)
-*_VS2010x86_*_ASLDLINK_FLAGS = DEF(MSFT_ASLDLINK_FLAGS)
-
-##################
-# IA32 definitions
-##################
-*_VS2010x86_IA32_*_DLL = DEF(VS2010x86_DLL)
-
-*_VS2010x86_IA32_CC_PATH = DEF(VS2010x86_BIN)\cl.exe
-*_VS2010x86_IA32_VFRPP_PATH = DEF(VS2010x86_BIN)\cl.exe
-*_VS2010x86_IA32_ASLCC_PATH = DEF(VS2010x86_BIN)\cl.exe
-*_VS2010x86_IA32_ASLPP_PATH = DEF(VS2010x86_BIN)\cl.exe
-*_VS2010x86_IA32_SLINK_PATH = DEF(VS2010x86_BIN)\lib.exe
-*_VS2010x86_IA32_DLINK_PATH = DEF(VS2010x86_BIN)\link.exe
-*_VS2010x86_IA32_ASLDLINK_PATH= DEF(VS2010x86_BIN)\link.exe
-*_VS2010x86_IA32_APP_PATH = DEF(VS2010x86_BIN)\cl.exe
-*_VS2010x86_IA32_PP_PATH = DEF(VS2010x86_BIN)\cl.exe
-*_VS2010x86_IA32_ASM_PATH = DEF(VS2010x86_BIN)\ml.exe
-
- DEBUG_VS2010x86_IA32_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Z7
-RELEASE_VS2010x86_IA32_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF
-NOOPT_VS2010x86_IA32_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Z7 /Od
-
- DEBUG_VS2010x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi
-RELEASE_VS2010x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd
-NOOPT_VS2010x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi
-
- DEBUG_VS2010x86_IA32_NASM_FLAGS = -Ox -f win32 -g
-RELEASE_VS2010x86_IA32_NASM_FLAGS = -Ox -f win32
-NOOPT_VS2010x86_IA32_NASM_FLAGS = -O0 -f win32 -g
-
- DEBUG_VS2010x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-RELEASE_VS2010x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data
-NOOPT_VS2010x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-
-##################
-# X64 definitions
-##################
-*_VS2010x86_X64_*_DLL = DEF(VS2010x86_DLL)
-
-*_VS2010x86_X64_CC_PATH = DEF(VS2010x86_BINX64)\cl.exe
-*_VS2010x86_X64_PP_PATH = DEF(VS2010x86_BINX64)\cl.exe
-*_VS2010x86_X64_APP_PATH = DEF(VS2010x86_BINX64)\cl.exe
-*_VS2010x86_X64_VFRPP_PATH = DEF(VS2010x86_BINX64)\cl.exe
-*_VS2010x86_X64_ASLCC_PATH = DEF(VS2010x86_BINX64)\cl.exe
-*_VS2010x86_X64_ASLPP_PATH = DEF(VS2010x86_BINX64)\cl.exe
-*_VS2010x86_X64_ASM_PATH = DEF(VS2010x86_BINX64)\ml64.exe
-*_VS2010x86_X64_SLINK_PATH = DEF(VS2010x86_BINX64)\lib.exe
-*_VS2010x86_X64_DLINK_PATH = DEF(VS2010x86_BINX64)\link.exe
-*_VS2010x86_X64_ASLDLINK_PATH = DEF(VS2010x86_BINX64)\link.exe
-
- DEBUG_VS2010x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Z7
-RELEASE_VS2010x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF
-NOOPT_VS2010x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Z7 /Od
-
- DEBUG_VS2010x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi
-RELEASE_VS2010x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd
-NOOPT_VS2010x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi
-
- DEBUG_VS2010x86_X64_NASM_FLAGS = -Ox -f win64 -g
-RELEASE_VS2010x86_X64_NASM_FLAGS = -Ox -f win64
-NOOPT_VS2010x86_X64_NASM_FLAGS = -O0 -f win64 -g
-
- DEBUG_VS2010x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-RELEASE_VS2010x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data
-NOOPT_VS2010x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-
-##################
-# EBC definitions
-##################
-*_VS2010x86_EBC_*_FAMILY = INTEL
-*_VS2010x86_EBC_*_DLL = DEF(VS2010x86_DLL)
-
-*_VS2010x86_EBC_PP_PATH = DEF(EBC_BINx86)\iec.exe
-*_VS2010x86_EBC_VFRPP_PATH = DEF(EBC_BINx86)\iec.exe
-*_VS2010x86_EBC_CC_PATH = DEF(EBC_BINx86)\iec.exe
-*_VS2010x86_EBC_SLINK_PATH = DEF(VS2010x86_BIN)\link.exe
-*_VS2010x86_EBC_DLINK_PATH = DEF(VS2010x86_BIN)\link.exe
-
-*_VS2010x86_EBC_PP_FLAGS = /nologo /E /TC /FIAutoGen.h
-*_VS2010x86_EBC_CC_FLAGS = /nologo /c /WX /W3 /FIAutoGen.h /D$(MODULE_ENTRY_POINT)=$(ARCH_ENTRY_POINT)
-*_VS2010x86_EBC_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h
-*_VS2010x86_EBC_SLINK_FLAGS = /lib /NOLOGO /MACHINE:EBC
-*_VS2010x86_EBC_DLINK_FLAGS = "C:\Program Files (x86)\Intel\EBC\Lib\EbcLib.lib" /NOLOGO /NODEFAULTLIB /MACHINE:EBC /OPT:REF /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /MAP /ALIGN:32 /DRIVER
-
-
-####################################################################################
-#
-# Microsoft Visual Studio 2012
-#
-# VS2012 - Microsoft Visual Studio 2012 Professional Edition with Intel ASL
-# ASL - Intel ACPI Source Language Compiler
-####################################################################################
-# VS2012 - Microsoft Visual Studio 2012 Professional Edition
-*_VS2012_*_*_FAMILY = MSFT
-
-*_VS2012_*_MAKE_PATH = DEF(VS2012_BIN)\nmake.exe
-*_VS2012_*_MAKE_FLAGS = /nologo
-*_VS2012_*_RC_PATH = DEF(WINSDK71_BIN)\rc.exe
-
-*_VS2012_*_SLINK_FLAGS = /NOLOGO /LTCG
-*_VS2012_*_APP_FLAGS = /nologo /E /TC
-*_VS2012_*_PP_FLAGS = /nologo /E /TC /FIAutoGen.h
-*_VS2012_*_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h
-*_VS2012_*_DEPS_FLAGS = DEF(MSFT_DEPS_FLAGS)
-*_VS2012_*_ASM16_PATH = DEF(VS2012_BIN)\ml.exe
-
-##################
-# ASL definitions
-##################
-*_VS2012_*_ASL_PATH = DEF(DEFAULT_WIN_ASL_BIN)
-*_VS2012_*_ASL_FLAGS = DEF(DEFAULT_WIN_ASL_FLAGS)
-*_VS2012_*_ASL_OUTFLAGS = DEF(DEFAULT_WIN_ASL_OUTFLAGS)
-*_VS2012_*_ASLCC_FLAGS = DEF(MSFT_ASLCC_FLAGS)
-*_VS2012_*_ASLPP_FLAGS = DEF(MSFT_ASLPP_FLAGS)
-*_VS2012_*_ASLDLINK_FLAGS = DEF(MSFT_ASLDLINK_FLAGS)
-
-##################
-# IA32 definitions
-##################
-*_VS2012_IA32_*_DLL = DEF(VS2012_DLL)
-
-*_VS2012_IA32_CC_PATH = DEF(VS2012_BIN)\cl.exe
-*_VS2012_IA32_VFRPP_PATH = DEF(VS2012_BIN)\cl.exe
-*_VS2012_IA32_SLINK_PATH = DEF(VS2012_BIN)\lib.exe
-*_VS2012_IA32_DLINK_PATH = DEF(VS2012_BIN)\link.exe
-*_VS2012_IA32_APP_PATH = DEF(VS2012_BIN)\cl.exe
-*_VS2012_IA32_PP_PATH = DEF(VS2012_BIN)\cl.exe
-*_VS2012_IA32_ASM_PATH = DEF(VS2012_BIN)\ml.exe
-*_VS2012_IA32_ASLCC_PATH = DEF(VS2012_BIN)\cl.exe
-*_VS2012_IA32_ASLPP_PATH = DEF(VS2012_BIN)\cl.exe
-*_VS2012_IA32_ASLDLINK_PATH = DEF(VS2012_BIN)\link.exe
-
- DEBUG_VS2012_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Z7
-RELEASE_VS2012_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF
-NOOPT_VS2012_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Z7 /Od
-
- DEBUG_VS2012_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi
-RELEASE_VS2012_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd
-NOOPT_VS2012_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi
-
- DEBUG_VS2012_IA32_NASM_FLAGS = -Ox -f win32 -g
-RELEASE_VS2012_IA32_NASM_FLAGS = -Ox -f win32
-NOOPT_VS2012_IA32_NASM_FLAGS = -O0 -f win32 -g
-
- DEBUG_VS2012_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-RELEASE_VS2012_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data
-NOOPT_VS2012_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-
-##################
-# X64 definitions
-##################
-*_VS2012_X64_*_DLL = DEF(VS2012_DLL)
-
-*_VS2012_X64_CC_PATH = DEF(VS2012_BINX64)\cl.exe
-*_VS2012_X64_PP_PATH = DEF(VS2012_BINX64)\cl.exe
-*_VS2012_X64_APP_PATH = DEF(VS2012_BINX64)\cl.exe
-*_VS2012_X64_VFRPP_PATH = DEF(VS2012_BINX64)\cl.exe
-*_VS2012_X64_ASM_PATH = DEF(VS2012_BINX64)\ml64.exe
-*_VS2012_X64_SLINK_PATH = DEF(VS2012_BINX64)\lib.exe
-*_VS2012_X64_DLINK_PATH = DEF(VS2012_BINX64)\link.exe
-*_VS2012_X64_ASLCC_PATH = DEF(VS2012_BINX64)\cl.exe
-*_VS2012_X64_ASLPP_PATH = DEF(VS2012_BINX64)\cl.exe
-*_VS2012_X64_ASLDLINK_PATH = DEF(VS2012_BINX64)\link.exe
-
- DEBUG_VS2012_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Z7
-RELEASE_VS2012_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF
-NOOPT_VS2012_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Z7 /Od
-
- DEBUG_VS2012_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi
-RELEASE_VS2012_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd
-NOOPT_VS2012_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi
-
- DEBUG_VS2012_X64_NASM_FLAGS = -Ox -f win64 -g
-RELEASE_VS2012_X64_NASM_FLAGS = -Ox -f win64
-NOOPT_VS2012_X64_NASM_FLAGS = -O0 -f win64 -g
-
- DEBUG_VS2012_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-RELEASE_VS2012_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data
-NOOPT_VS2012_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-
-##################
-# EBC definitions
-##################
-*_VS2012_EBC_*_FAMILY = INTEL
-*_VS2012_EBC_*_DLL = DEF(VS2012_DLL)
-
-*_VS2012_EBC_PP_PATH = DEF(EBC_BIN)\iec.exe
-*_VS2012_EBC_VFRPP_PATH = DEF(EBC_BIN)\iec.exe
-*_VS2012_EBC_CC_PATH = DEF(EBC_BIN)\iec.exe
-*_VS2012_EBC_SLINK_PATH = DEF(VS2012_BIN)\link.exe
-*_VS2012_EBC_DLINK_PATH = DEF(VS2012_BIN)\link.exe
-
-*_VS2012_EBC_PP_FLAGS = /nologo /E /TC /FIAutoGen.h
-*_VS2012_EBC_CC_FLAGS = /nologo /c /WX /W3 /FIAutoGen.h /D$(MODULE_ENTRY_POINT)=$(ARCH_ENTRY_POINT)
-*_VS2012_EBC_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h
-*_VS2012_EBC_SLINK_FLAGS = /lib /NOLOGO /MACHINE:EBC
-*_VS2012_EBC_DLINK_FLAGS = "C:\Program Files\Intel\EBC\Lib\EbcLib.lib" /NOLOGO /NODEFAULTLIB /MACHINE:EBC /OPT:REF /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /MAP /ALIGN:32 /DRIVER
-
-
-####################################################################################
-# VS2012x86 - Microsoft Visual Studio 2012 (x86) professional with Intel ASL
-# ASL - Intel ACPI Source Language Compiler (iasl.exe)
-####################################################################################
-# VS2012x86 - Microsoft Visual Studio 2012 (x86) professional Edition with Intel ASL
-*_VS2012x86_*_*_FAMILY = MSFT
-
-*_VS2012x86_*_MAKE_PATH = DEF(VS2012x86_BIN)\nmake.exe
-*_VS2012x86_*_MAKE_FLAGS = /nologo
-*_VS2012x86_*_RC_PATH = DEF(WINSDK71x86_BIN)\rc.exe
-
-*_VS2012x86_*_SLINK_FLAGS = /NOLOGO /LTCG
-*_VS2012x86_*_APP_FLAGS = /nologo /E /TC
-*_VS2012x86_*_PP_FLAGS = /nologo /E /TC /FIAutoGen.h
-*_VS2012x86_*_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h
-*_VS2012x86_*_DEPS_FLAGS = DEF(MSFT_DEPS_FLAGS)
-*_VS2012x86_*_ASM16_PATH = DEF(VS2012x86_BIN)\ml.exe
-
-##################
-# ASL definitions
-##################
-*_VS2012x86_*_ASL_PATH = DEF(WIN_IASL_BIN)
-*_VS2012x86_*_ASL_FLAGS = DEF(DEFAULT_WIN_ASL_FLAGS)
-*_VS2012x86_*_ASL_OUTFLAGS = DEF(DEFAULT_WIN_ASL_OUTFLAGS)
-*_VS2012x86_*_ASLCC_FLAGS = DEF(MSFT_ASLCC_FLAGS)
-*_VS2012x86_*_ASLPP_FLAGS = DEF(MSFT_ASLPP_FLAGS)
-*_VS2012x86_*_ASLDLINK_FLAGS = DEF(MSFT_ASLDLINK_FLAGS)
-
-##################
-# IA32 definitions
-##################
-*_VS2012x86_IA32_*_DLL = DEF(VS2012x86_DLL)
-
-*_VS2012x86_IA32_CC_PATH = DEF(VS2012x86_BIN)\cl.exe
-*_VS2012x86_IA32_VFRPP_PATH = DEF(VS2012x86_BIN)\cl.exe
-*_VS2012x86_IA32_ASLCC_PATH = DEF(VS2012x86_BIN)\cl.exe
-*_VS2012x86_IA32_ASLPP_PATH = DEF(VS2012x86_BIN)\cl.exe
-*_VS2012x86_IA32_SLINK_PATH = DEF(VS2012x86_BIN)\lib.exe
-*_VS2012x86_IA32_DLINK_PATH = DEF(VS2012x86_BIN)\link.exe
-*_VS2012x86_IA32_ASLDLINK_PATH= DEF(VS2012x86_BIN)\link.exe
-*_VS2012x86_IA32_APP_PATH = DEF(VS2012x86_BIN)\cl.exe
-*_VS2012x86_IA32_PP_PATH = DEF(VS2012x86_BIN)\cl.exe
-*_VS2012x86_IA32_ASM_PATH = DEF(VS2012x86_BIN)\ml.exe
-
- DEBUG_VS2012x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Z7
-RELEASE_VS2012x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF
-NOOPT_VS2012x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Z7 /Od
-
- DEBUG_VS2012x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi
-RELEASE_VS2012x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd
-NOOPT_VS2012x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi
-
- DEBUG_VS2012x86_IA32_NASM_FLAGS = -Ox -f win32 -g
-RELEASE_VS2012x86_IA32_NASM_FLAGS = -Ox -f win32
-NOOPT_VS2012x86_IA32_NASM_FLAGS = -O0 -f win32 -g
-
- DEBUG_VS2012x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-RELEASE_VS2012x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data
-NOOPT_VS2012x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-
-##################
-# X64 definitions
-##################
-*_VS2012x86_X64_*_DLL = DEF(VS2012x86_DLL)
-
-*_VS2012x86_X64_CC_PATH = DEF(VS2012x86_BINX64)\cl.exe
-*_VS2012x86_X64_PP_PATH = DEF(VS2012x86_BINX64)\cl.exe
-*_VS2012x86_X64_APP_PATH = DEF(VS2012x86_BINX64)\cl.exe
-*_VS2012x86_X64_VFRPP_PATH = DEF(VS2012x86_BINX64)\cl.exe
-*_VS2012x86_X64_ASLCC_PATH = DEF(VS2012x86_BINX64)\cl.exe
-*_VS2012x86_X64_ASLPP_PATH = DEF(VS2012x86_BINX64)\cl.exe
-*_VS2012x86_X64_ASM_PATH = DEF(VS2012x86_BINX64)\ml64.exe
-*_VS2012x86_X64_SLINK_PATH = DEF(VS2012x86_BINX64)\lib.exe
-*_VS2012x86_X64_DLINK_PATH = DEF(VS2012x86_BINX64)\link.exe
-*_VS2012x86_X64_ASLDLINK_PATH = DEF(VS2012x86_BINX64)\link.exe
-
- DEBUG_VS2012x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Z7
-RELEASE_VS2012x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF
-NOOPT_VS2012x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Z7 /Od
-
- DEBUG_VS2012x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi
-RELEASE_VS2012x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd
-NOOPT_VS2012x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi
-
- DEBUG_VS2012x86_X64_NASM_FLAGS = -Ox -f win64 -g
-RELEASE_VS2012x86_X64_NASM_FLAGS = -Ox -f win64
-NOOPT_VS2012x86_X64_NASM_FLAGS = -O0 -f win64 -g
-
- DEBUG_VS2012x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-RELEASE_VS2012x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data
-NOOPT_VS2012x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-
-##################
-# EBC definitions
-##################
-*_VS2012x86_EBC_*_FAMILY = INTEL
-*_VS2012x86_EBC_*_DLL = DEF(VS2012x86_DLL)
-
-*_VS2012x86_EBC_PP_PATH = DEF(EBC_BINx86)\iec.exe
-*_VS2012x86_EBC_VFRPP_PATH = DEF(EBC_BINx86)\iec.exe
-*_VS2012x86_EBC_CC_PATH = DEF(EBC_BINx86)\iec.exe
-*_VS2012x86_EBC_SLINK_PATH = DEF(VS2012x86_BIN)\link.exe
-*_VS2012x86_EBC_DLINK_PATH = DEF(VS2012x86_BIN)\link.exe
-
-*_VS2012x86_EBC_PP_FLAGS = /nologo /E /TC /FIAutoGen.h
-*_VS2012x86_EBC_CC_FLAGS = /nologo /c /WX /W3 /FIAutoGen.h /D$(MODULE_ENTRY_POINT)=$(ARCH_ENTRY_POINT)
-*_VS2012x86_EBC_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h
-*_VS2012x86_EBC_SLINK_FLAGS = /lib /NOLOGO /MACHINE:EBC
-*_VS2012x86_EBC_DLINK_FLAGS = "C:\Program Files (x86)\Intel\EBC\Lib\EbcLib.lib" /NOLOGO /NODEFAULTLIB /MACHINE:EBC /OPT:REF /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /MAP /ALIGN:32 /DRIVER
-
-
-####################################################################################
-#
-# Microsoft Visual Studio 2013
-#
-# VS2013 - Microsoft Visual Studio 2013 Professional Edition with Intel ASL
-# ASL - Intel ACPI Source Language Compiler
-####################################################################################
-# VS2013 - Microsoft Visual Studio 2013 Professional Edition
-*_VS2013_*_*_FAMILY = MSFT
-
-*_VS2013_*_MAKE_PATH = DEF(VS2013_BIN)\nmake.exe
-*_VS2013_*_MAKE_FLAGS = /nologo
-*_VS2013_*_RC_PATH = DEF(WINSDK8_BIN)\rc.exe
-
-*_VS2013_*_SLINK_FLAGS = /NOLOGO /LTCG
-*_VS2013_*_APP_FLAGS = /nologo /E /TC
-*_VS2013_*_PP_FLAGS = /nologo /E /TC /FIAutoGen.h
-*_VS2013_*_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h
-*_VS2013_*_DEPS_FLAGS = DEF(MSFT_DEPS_FLAGS)
-*_VS2013_*_ASM16_PATH = DEF(VS2013_BIN)\ml.exe
-
-##################
-# ASL definitions
-##################
-*_VS2013_*_ASL_PATH = DEF(DEFAULT_WIN_ASL_BIN)
-*_VS2013_*_ASL_FLAGS = DEF(DEFAULT_WIN_ASL_FLAGS)
-*_VS2013_*_ASL_OUTFLAGS = DEF(DEFAULT_WIN_ASL_OUTFLAGS)
-*_VS2013_*_ASLCC_FLAGS = DEF(MSFT_ASLCC_FLAGS)
-*_VS2013_*_ASLPP_FLAGS = DEF(MSFT_ASLPP_FLAGS)
-*_VS2013_*_ASLDLINK_FLAGS = DEF(MSFT_ASLDLINK_FLAGS)
-
-##################
-# IA32 definitions
-##################
-*_VS2013_IA32_*_DLL = DEF(VS2013_DLL)
-
-*_VS2013_IA32_CC_PATH = DEF(VS2013_BIN)\cl.exe
-*_VS2013_IA32_VFRPP_PATH = DEF(VS2013_BIN)\cl.exe
-*_VS2013_IA32_SLINK_PATH = DEF(VS2013_BIN)\lib.exe
-*_VS2013_IA32_DLINK_PATH = DEF(VS2013_BIN)\link.exe
-*_VS2013_IA32_APP_PATH = DEF(VS2013_BIN)\cl.exe
-*_VS2013_IA32_PP_PATH = DEF(VS2013_BIN)\cl.exe
-*_VS2013_IA32_ASM_PATH = DEF(VS2013_BIN)\ml.exe
-*_VS2013_IA32_ASLCC_PATH = DEF(VS2013_BIN)\cl.exe
-*_VS2013_IA32_ASLPP_PATH = DEF(VS2013_BIN)\cl.exe
-*_VS2013_IA32_ASLDLINK_PATH = DEF(VS2013_BIN)\link.exe
-
- DEBUG_VS2013_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Z7 /Gw
-RELEASE_VS2013_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gw
-NOOPT_VS2013_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Z7 /Od
-
- DEBUG_VS2013_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi
-RELEASE_VS2013_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd
-NOOPT_VS2013_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi
-
- DEBUG_VS2013_IA32_NASM_FLAGS = -Ox -f win32 -g
-RELEASE_VS2013_IA32_NASM_FLAGS = -Ox -f win32
-NOOPT_VS2013_IA32_NASM_FLAGS = -O0 -f win32 -g
-
- DEBUG_VS2013_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-RELEASE_VS2013_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data
-NOOPT_VS2013_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-
-##################
-# X64 definitions
-##################
-*_VS2013_X64_*_DLL = DEF(VS2013_DLL)
-
-*_VS2013_X64_CC_PATH = DEF(VS2013_BINX64)\cl.exe
-*_VS2013_X64_PP_PATH = DEF(VS2013_BINX64)\cl.exe
-*_VS2013_X64_APP_PATH = DEF(VS2013_BINX64)\cl.exe
-*_VS2013_X64_VFRPP_PATH = DEF(VS2013_BINX64)\cl.exe
-*_VS2013_X64_ASM_PATH = DEF(VS2013_BINX64)\ml64.exe
-*_VS2013_X64_SLINK_PATH = DEF(VS2013_BINX64)\lib.exe
-*_VS2013_X64_DLINK_PATH = DEF(VS2013_BINX64)\link.exe
-*_VS2013_X64_ASLCC_PATH = DEF(VS2013_BINX64)\cl.exe
-*_VS2013_X64_ASLPP_PATH = DEF(VS2013_BINX64)\cl.exe
-*_VS2013_X64_ASLDLINK_PATH = DEF(VS2013_BINX64)\link.exe
-
- DEBUG_VS2013_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Z7 /Gw
-RELEASE_VS2013_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Gw
-NOOPT_VS2013_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Z7 /Od
-
- DEBUG_VS2013_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi
-RELEASE_VS2013_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd
-NOOPT_VS2013_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi
-
- DEBUG_VS2013_X64_NASM_FLAGS = -Ox -f win64 -g
-RELEASE_VS2013_X64_NASM_FLAGS = -Ox -f win64
-NOOPT_VS2013_X64_NASM_FLAGS = -O0 -f win64 -g
-
- DEBUG_VS2013_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-RELEASE_VS2013_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data
-NOOPT_VS2013_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-
-##################
-# EBC definitions
-##################
-*_VS2013_EBC_*_FAMILY = INTEL
-*_VS2013_EBC_*_DLL = DEF(VS2013_DLL)
-
-*_VS2013_EBC_PP_PATH = DEF(EBC_BIN)\iec.exe
-*_VS2013_EBC_VFRPP_PATH = DEF(EBC_BIN)\iec.exe
-*_VS2013_EBC_CC_PATH = DEF(EBC_BIN)\iec.exe
-*_VS2013_EBC_SLINK_PATH = DEF(VS2013_BIN)\link.exe
-*_VS2013_EBC_DLINK_PATH = DEF(VS2013_BIN)\link.exe
-
-*_VS2013_EBC_PP_FLAGS = /nologo /E /TC /FIAutoGen.h
-*_VS2013_EBC_CC_FLAGS = /nologo /c /WX /W3 /FIAutoGen.h /D$(MODULE_ENTRY_POINT)=$(ARCH_ENTRY_POINT)
-*_VS2013_EBC_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h
-*_VS2013_EBC_SLINK_FLAGS = /lib /NOLOGO /MACHINE:EBC
-*_VS2013_EBC_DLINK_FLAGS = "C:\Program Files\Intel\EBC\Lib\EbcLib.lib" /NOLOGO /NODEFAULTLIB /MACHINE:EBC /OPT:REF /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /MAP /ALIGN:32 /DRIVER
-
-
-####################################################################################
-# VS2013x86 - Microsoft Visual Studio 2013 (x86) professional with Intel ASL
-# ASL - Intel ACPI Source Language Compiler (iasl.exe)
-####################################################################################
-# VS2013x86 - Microsoft Visual Studio 2013 (x86) professional Edition with Intel ASL
-*_VS2013x86_*_*_FAMILY = MSFT
-
-*_VS2013x86_*_MAKE_PATH = DEF(VS2013x86_BIN)\nmake.exe
-*_VS2013x86_*_MAKE_FLAGS = /nologo
-*_VS2013x86_*_RC_PATH = DEF(WINSDK8x86_BIN)\rc.exe
-
-*_VS2013x86_*_SLINK_FLAGS = /NOLOGO /LTCG
-*_VS2013x86_*_APP_FLAGS = /nologo /E /TC
-*_VS2013x86_*_PP_FLAGS = /nologo /E /TC /FIAutoGen.h
-*_VS2013x86_*_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h
-*_VS2013x86_*_DEPS_FLAGS = DEF(MSFT_DEPS_FLAGS)
-*_VS2013x86_*_ASM16_PATH = DEF(VS2013x86_BIN)\ml.exe
-
-##################
-# ASL definitions
-##################
-*_VS2013x86_*_ASL_PATH = DEF(WIN_IASL_BIN)
-*_VS2013x86_*_ASL_FLAGS = DEF(DEFAULT_WIN_ASL_FLAGS)
-*_VS2013x86_*_ASL_OUTFLAGS = DEF(DEFAULT_WIN_ASL_OUTFLAGS)
-*_VS2013x86_*_ASLCC_FLAGS = DEF(MSFT_ASLCC_FLAGS)
-*_VS2013x86_*_ASLPP_FLAGS = DEF(MSFT_ASLPP_FLAGS)
-*_VS2013x86_*_ASLDLINK_FLAGS = DEF(MSFT_ASLDLINK_FLAGS)
-
-##################
-# IA32 definitions
-##################
-*_VS2013x86_IA32_*_DLL = DEF(VS2013x86_DLL)
-
-*_VS2013x86_IA32_CC_PATH = DEF(VS2013x86_BIN)\cl.exe
-*_VS2013x86_IA32_VFRPP_PATH = DEF(VS2013x86_BIN)\cl.exe
-*_VS2013x86_IA32_ASLCC_PATH = DEF(VS2013x86_BIN)\cl.exe
-*_VS2013x86_IA32_ASLPP_PATH = DEF(VS2013x86_BIN)\cl.exe
-*_VS2013x86_IA32_SLINK_PATH = DEF(VS2013x86_BIN)\lib.exe
-*_VS2013x86_IA32_DLINK_PATH = DEF(VS2013x86_BIN)\link.exe
-*_VS2013x86_IA32_ASLDLINK_PATH= DEF(VS2013x86_BIN)\link.exe
-*_VS2013x86_IA32_APP_PATH = DEF(VS2013x86_BIN)\cl.exe
-*_VS2013x86_IA32_PP_PATH = DEF(VS2013x86_BIN)\cl.exe
-*_VS2013x86_IA32_ASM_PATH = DEF(VS2013x86_BIN)\ml.exe
-
- DEBUG_VS2013x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Z7 /Gw
-RELEASE_VS2013x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gw
-NOOPT_VS2013x86_IA32_CC_FLAGS = /nologo /arch:IA32 /c /WX /GS- /W4 /Gs32768 /D UNICODE /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Z7 /Od
-
- DEBUG_VS2013x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi
-RELEASE_VS2013x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd
-NOOPT_VS2013x86_IA32_ASM_FLAGS = /nologo /c /WX /W3 /Cx /coff /Zd /Zi
-
- DEBUG_VS2013x86_IA32_NASM_FLAGS = -Ox -f win32 -g
-RELEASE_VS2013x86_IA32_NASM_FLAGS = -Ox -f win32
-NOOPT_VS2013x86_IA32_NASM_FLAGS = -O0 -f win32 -g
-
- DEBUG_VS2013x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-RELEASE_VS2013x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data
-NOOPT_VS2013x86_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-
-##################
-# X64 definitions
-##################
-*_VS2013x86_X64_*_DLL = DEF(VS2013x86_DLL)
-
-*_VS2013x86_X64_CC_PATH = DEF(VS2013x86_BINX64)\cl.exe
-*_VS2013x86_X64_PP_PATH = DEF(VS2013x86_BINX64)\cl.exe
-*_VS2013x86_X64_APP_PATH = DEF(VS2013x86_BINX64)\cl.exe
-*_VS2013x86_X64_VFRPP_PATH = DEF(VS2013x86_BINX64)\cl.exe
-*_VS2013x86_X64_ASLCC_PATH = DEF(VS2013x86_BINX64)\cl.exe
-*_VS2013x86_X64_ASLPP_PATH = DEF(VS2013x86_BINX64)\cl.exe
-*_VS2013x86_X64_ASM_PATH = DEF(VS2013x86_BINX64)\ml64.exe
-*_VS2013x86_X64_SLINK_PATH = DEF(VS2013x86_BINX64)\lib.exe
-*_VS2013x86_X64_DLINK_PATH = DEF(VS2013x86_BINX64)\link.exe
-*_VS2013x86_X64_ASLDLINK_PATH = DEF(VS2013x86_BINX64)\link.exe
-
- DEBUG_VS2013x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Z7 /Gw
-RELEASE_VS2013x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Gw
-NOOPT_VS2013x86_X64_CC_FLAGS = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Z7 /Od
-
- DEBUG_VS2013x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi
-RELEASE_VS2013x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd
-NOOPT_VS2013x86_X64_ASM_FLAGS = /nologo /c /WX /W3 /Cx /Zd /Zi
-
- DEBUG_VS2013x86_X64_NASM_FLAGS = -Ox -f win64 -g
-RELEASE_VS2013x86_X64_NASM_FLAGS = -Ox -f win64
-NOOPT_VS2013x86_X64_NASM_FLAGS = -O0 -f win64 -g
-
- DEBUG_VS2013x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-RELEASE_VS2013x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data
-NOOPT_VS2013x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-
-##################
-# EBC definitions
-##################
-*_VS2013x86_EBC_*_FAMILY = INTEL
-*_VS2013x86_EBC_*_DLL = DEF(VS2013x86_DLL)
-
-*_VS2013x86_EBC_PP_PATH = DEF(EBC_BINx86)\iec.exe
-*_VS2013x86_EBC_VFRPP_PATH = DEF(EBC_BINx86)\iec.exe
-*_VS2013x86_EBC_CC_PATH = DEF(EBC_BINx86)\iec.exe
-*_VS2013x86_EBC_SLINK_PATH = DEF(VS2013x86_BIN)\link.exe
-*_VS2013x86_EBC_DLINK_PATH = DEF(VS2013x86_BIN)\link.exe
-
-*_VS2013x86_EBC_PP_FLAGS = /nologo /E /TC /FIAutoGen.h
-*_VS2013x86_EBC_CC_FLAGS = /nologo /c /WX /W3 /FIAutoGen.h /D$(MODULE_ENTRY_POINT)=$(ARCH_ENTRY_POINT)
-*_VS2013x86_EBC_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h
-*_VS2013x86_EBC_SLINK_FLAGS = /lib /NOLOGO /MACHINE:EBC
-*_VS2013x86_EBC_DLINK_FLAGS = "C:\Program Files (x86)\Intel\EBC\Lib\EbcLib.lib" /NOLOGO /NODEFAULTLIB /MACHINE:EBC /OPT:REF /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /MAP /ALIGN:32 /DRIVER
-
-
####################################################################################
#
# Microsoft Visual Studio 2015
@@ -1386,25 +348,6 @@ NOOPT_VS2015_X64_NASM_FLAGS = -O0 -f win64 -g
RELEASE_VS2015_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data
NOOPT_VS2015_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-##################
-# EBC definitions
-##################
-*_VS2015_EBC_*_FAMILY = INTEL
-*_VS2015_EBC_*_DLL = DEF(VS2015_DLL)
-
-*_VS2015_EBC_PP_PATH = DEF(EBC_BIN)\iec.exe
-*_VS2015_EBC_VFRPP_PATH = DEF(EBC_BIN)\iec.exe
-*_VS2015_EBC_CC_PATH = DEF(EBC_BIN)\iec.exe
-*_VS2015_EBC_SLINK_PATH = DEF(VS2015_BIN)\link.exe
-*_VS2015_EBC_DLINK_PATH = DEF(VS2015_BIN)\link.exe
-
-*_VS2015_EBC_PP_FLAGS = /nologo /E /TC /FIAutoGen.h
-*_VS2015_EBC_CC_FLAGS = /nologo /c /WX /W3 /FIAutoGen.h /D$(MODULE_ENTRY_POINT)=$(ARCH_ENTRY_POINT)
-*_VS2015_EBC_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h
-*_VS2015_EBC_SLINK_FLAGS = /lib /NOLOGO /MACHINE:EBC
-*_VS2015_EBC_DLINK_FLAGS = "C:\Program Files\Intel\EBC\Lib\EbcLib.lib" /NOLOGO /NODEFAULTLIB /MACHINE:EBC /OPT:REF /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /MAP /ALIGN:32 /DRIVER
-
-
####################################################################################
# VS2015x86 - Microsoft Visual Studio 2015 (x86) professional with Intel ASL
# ASL - Intel ACPI Source Language Compiler (iasl.exe)
@@ -1498,25 +441,6 @@ NOOPT_VS2015x86_X64_NASM_FLAGS = -O0 -f win64 -g
RELEASE_VS2015x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data
NOOPT_VS2015x86_X64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
-##################
-# EBC definitions
-##################
-*_VS2015x86_EBC_*_FAMILY = INTEL
-*_VS2015x86_EBC_*_DLL = DEF(VS2015x86_DLL)
-
-*_VS2015x86_EBC_PP_PATH = DEF(EBC_BINx86)\iec.exe
-*_VS2015x86_EBC_VFRPP_PATH = DEF(EBC_BINx86)\iec.exe
-*_VS2015x86_EBC_CC_PATH = DEF(EBC_BINx86)\iec.exe
-*_VS2015x86_EBC_SLINK_PATH = DEF(VS2015x86_BIN)\link.exe
-*_VS2015x86_EBC_DLINK_PATH = DEF(VS2015x86_BIN)\link.exe
-
-*_VS2015x86_EBC_PP_FLAGS = /nologo /E /TC /FIAutoGen.h
-*_VS2015x86_EBC_CC_FLAGS = /nologo /c /WX /W3 /FIAutoGen.h /D$(MODULE_ENTRY_POINT)=$(ARCH_ENTRY_POINT)
-*_VS2015x86_EBC_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h
-*_VS2015x86_EBC_SLINK_FLAGS = /lib /NOLOGO /MACHINE:EBC
-*_VS2015x86_EBC_DLINK_FLAGS = "C:\Program Files (x86)\Intel\EBC\Lib\EbcLib.lib" /NOLOGO /NODEFAULTLIB /MACHINE:EBC /OPT:REF /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /MAP /ALIGN:32 /DRIVER
-
-
####################################################################################
# VS2017 - Microsoft Visual Studio 2017 with Intel ASL
# ASL - Intel ACPI Source Language Compiler (iasl.exe)
@@ -1658,23 +582,6 @@ NOOPT_VS2017_AARCH64_ASM_FLAGS = /nologo
RELEASE_VS2017_AARCH64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:ARM64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /DRIVER /MERGE:.rdata=.data
NOOPT_VS2017_AARCH64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:ARM64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /DRIVER /DEBUG
-##################
-# EBC definitions
-##################
-*_VS2017_EBC_*_FAMILY = INTEL
-
-*_VS2017_EBC_PP_PATH = DEF(EBC_BINx86)\iec.exe
-*_VS2017_EBC_VFRPP_PATH = DEF(EBC_BINx86)\iec.exe
-*_VS2017_EBC_CC_PATH = DEF(EBC_BINx86)\iec.exe
-*_VS2017_EBC_SLINK_PATH = DEF(VS2017_BIN_IA32)\link.exe
-*_VS2017_EBC_DLINK_PATH = DEF(VS2017_BIN_IA32)\link.exe
-
-*_VS2017_EBC_PP_FLAGS = /nologo /E /TC /FIAutoGen.h
-*_VS2017_EBC_CC_FLAGS = /nologo /c /WX /W3 /FIAutoGen.h /D$(MODULE_ENTRY_POINT)=$(ARCH_ENTRY_POINT)
-*_VS2017_EBC_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h
-*_VS2017_EBC_SLINK_FLAGS = /lib /NOLOGO /MACHINE:EBC
-*_VS2017_EBC_DLINK_FLAGS = "C:\Program Files (x86)\Intel\EBC\Lib\EbcLib.lib" /NOLOGO /NODEFAULTLIB /MACHINE:EBC /OPT:REF /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /MAP /ALIGN:32 /DRIVER
-
####################################################################################
# VS2019 - Microsoft Visual Studio 2019 with Intel ASL
# ASL - Intel ACPI Source Language Compiler (iasl.exe)
@@ -1816,23 +723,6 @@ NOOPT_VS2019_AARCH64_ASM_FLAGS = /nologo
RELEASE_VS2019_AARCH64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:ARM64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /DRIVER /MERGE:.rdata=.data
NOOPT_VS2019_AARCH64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:ARM64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /DRIVER /DEBUG
-##################
-# EBC definitions
-##################
-*_VS2019_EBC_*_FAMILY = INTEL
-
-*_VS2019_EBC_PP_PATH = DEF(EBC_BINx86)\iec.exe
-*_VS2019_EBC_VFRPP_PATH = DEF(EBC_BINx86)\iec.exe
-*_VS2019_EBC_CC_PATH = DEF(EBC_BINx86)\iec.exe
-*_VS2019_EBC_SLINK_PATH = DEF(VS2019_BIN_IA32)\link.exe
-*_VS2019_EBC_DLINK_PATH = DEF(VS2019_BIN_IA32)\link.exe
-
-*_VS2019_EBC_PP_FLAGS = /nologo /E /TC /FIAutoGen.h
-*_VS2019_EBC_CC_FLAGS = /nologo /c /WX /W3 /FIAutoGen.h /D$(MODULE_ENTRY_POINT)=$(ARCH_ENTRY_POINT)
-*_VS2019_EBC_VFRPP_FLAGS = /nologo /E /TC /DVFRCOMPILE /FI$(MODULE_NAME)StrDefs.h
-*_VS2019_EBC_SLINK_FLAGS = /lib /NOLOGO /MACHINE:EBC
-*_VS2019_EBC_DLINK_FLAGS = "C:\Program Files (x86)\Intel\EBC\Lib\EbcLib.lib" /NOLOGO /NODEFAULTLIB /MACHINE:EBC /OPT:REF /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /MAP /ALIGN:32 /DRIVER
-
####################################################################################
# GCC Common
####################################################################################
@@ -1841,22 +731,21 @@ NOOPT_VS2019_AARCH64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF
*_*_*_OBJCOPY_FLAGS = objcopy not needed for
*_*_*_SYMRENAME_PATH = echo
*_*_*_SYMRENAME_FLAGS = Symbol renaming not needed for
-DEBUG_*_*_OBJCOPY_ADDDEBUGFLAG = --add-gnu-debuglink=$(DEBUG_DIR)/$(MODULE_NAME).debug
+DEBUG_*_*_OBJCOPY_ADDDEBUGFLAG = --add-gnu-debuglink="$(DEBUG_DIR)/$(MODULE_NAME).debug"
RELEASE_*_*_OBJCOPY_ADDDEBUGFLAG =
-NOOPT_*_*_OBJCOPY_ADDDEBUGFLAG = --add-gnu-debuglink=$(DEBUG_DIR)/$(MODULE_NAME).debug
+NOOPT_*_*_OBJCOPY_ADDDEBUGFLAG = --add-gnu-debuglink="$(DEBUG_DIR)/$(MODULE_NAME).debug"
*_*_*_OBJCOPY_STRIPFLAG = --strip-unneeded -R .eh_frame
*_*_*_DTC_FLAGS = -H epapr
*_*_*_DTCPP_PATH = DEF(DTCPP_BIN)
*_*_*_DTC_PATH = DEF(DTC_BIN)
DEFINE GCC_ALL_CC_FLAGS = -g -Os -fshort-wchar -fno-builtin -fno-strict-aliasing -Wall -Werror -Wno-array-bounds -include AutoGen.h -fno-common
-DEFINE GCC_IA32_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -m32 -malign-double -freorder-blocks -freorder-blocks-and-partition -O2 -mno-stack-arg-probe
-DEFINE GCC_X64_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mno-red-zone -Wno-address -mno-stack-arg-probe
-DEFINE GCC_ARM_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mlittle-endian -mabi=aapcs -fno-short-enums -funsigned-char -ffunction-sections -fdata-sections -fomit-frame-pointer -Wno-address -mthumb -mfloat-abi=soft -fno-pic -fno-pie
+DEFINE GCC_ARM_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mlittle-endian -mabi=aapcs -fno-short-enums -funsigned-char -ffunction-sections -fdata-sections -fomit-frame-pointer -Wno-address -mthumb -fno-pic -fno-pie
DEFINE GCC_LOONGARCH64_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mabi=lp64d -fno-asynchronous-unwind-tables -fno-plt -Wno-address -fno-short-enums -fsigned-char -ffunction-sections -fdata-sections
DEFINE GCC_ARM_CC_XIPFLAGS = -mno-unaligned-access
DEFINE GCC_AARCH64_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mlittle-endian -fno-short-enums -fverbose-asm -funsigned-char -ffunction-sections -fdata-sections -Wno-address -fno-asynchronous-unwind-tables -fno-unwind-tables -fno-pic -fno-pie -ffixed-x18
DEFINE GCC_AARCH64_CC_XIPFLAGS = -mstrict-align -mgeneral-regs-only
+DEFINE GCC_RISCV64_CC_XIPFLAGS = -mstrict-align -mgeneral-regs-only
DEFINE GCC_DLINK_FLAGS_COMMON = -nostdlib --pie
DEFINE GCC_DLINK2_FLAGS_COMMON = -Wl,--script=$(EDK_TOOLS_PATH)/Scripts/GccBase.lds
DEFINE GCC_IA32_X64_DLINK_COMMON = DEF(GCC_DLINK_FLAGS_COMMON) --gc-sections
@@ -1882,6 +771,7 @@ DEFINE GCC_IA32_RC_FLAGS = -I binary -O elf32-i386 -B i386
DEFINE GCC_X64_RC_FLAGS = -I binary -O elf64-x86-64 -B i386 --rename-section .data=.hii
DEFINE GCC_ARM_RC_FLAGS = -I binary -O elf32-littlearm -B arm --rename-section .data=.hii
DEFINE GCC_AARCH64_RC_FLAGS = -I binary -O elf64-littleaarch64 -B aarch64 --rename-section .data=.hii
+DEFINE GCC_AARCH64_RC_BTI_FLAGS = --add-section .note.gnu.property=$(WORKSPACE)/ArmPkg/Library/GnuNoteBti.bin --set-section-flags .note.gnu.property=alloc,readonly
DEFINE GCC_RISCV64_RC_FLAGS = -I binary -O elf64-littleriscv -B riscv --rename-section .data=.hii
DEFINE GCC_LOONGARCH64_RC_FLAGS = -I binary -O elf64-loongarch -B loongarch64 --rename-section .data=.hii
@@ -1890,19 +780,19 @@ DEFINE GCC_DEPS_FLAGS = -MMD -MF $@.deps
DEFINE GCC48_ALL_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -ffunction-sections -fdata-sections -DSTRING_ARRAY_NAME=$(BASE_NAME)Strings
DEFINE GCC48_IA32_X64_DLINK_COMMON = -nostdlib -Wl,-n,-q,--gc-sections -z common-page-size=0x20
-DEFINE GCC48_IA32_CC_FLAGS = DEF(GCC48_ALL_CC_FLAGS) -m32 -march=i586 -malign-double -fno-stack-protector -D EFI32 -fno-asynchronous-unwind-tables -Wno-address
-DEFINE GCC48_X64_CC_FLAGS = DEF(GCC48_ALL_CC_FLAGS) -m64 -fno-stack-protector "-DEFIAPI=__attribute__((ms_abi))" -maccumulate-outgoing-args -mno-red-zone -Wno-address -mcmodel=small -fpie -fno-asynchronous-unwind-tables -Wno-address
+DEFINE GCC48_IA32_CC_FLAGS = DEF(GCC48_ALL_CC_FLAGS) -m32 -march=i586 -malign-double -fno-stack-protector -D EFI32 -fno-asynchronous-unwind-tables -Wno-address -fno-omit-frame-pointer
+DEFINE GCC48_X64_CC_FLAGS = DEF(GCC48_ALL_CC_FLAGS) -m64 -fno-stack-protector "-DEFIAPI=__attribute__((ms_abi))" -maccumulate-outgoing-args -mno-red-zone -Wno-address -mcmodel=small -fpie -fno-asynchronous-unwind-tables -Wno-address -fno-omit-frame-pointer
DEFINE GCC48_IA32_X64_ASLDLINK_FLAGS = DEF(GCC48_IA32_X64_DLINK_COMMON) -Wl,--entry,ReferenceAcpiTable -u ReferenceAcpiTable
DEFINE GCC48_IA32_X64_DLINK_FLAGS = DEF(GCC48_IA32_X64_DLINK_COMMON) -Wl,--entry,$(IMAGE_ENTRY_POINT) -u $(IMAGE_ENTRY_POINT) -Wl,-Map,$(DEST_DIR_DEBUG)/$(BASE_NAME).map,--whole-archive
DEFINE GCC48_IA32_DLINK2_FLAGS = -Wl,--defsym=PECOFF_HEADER_SIZE=0x220 DEF(GCC_DLINK2_FLAGS_COMMON)
DEFINE GCC48_X64_DLINK_FLAGS = DEF(GCC48_IA32_X64_DLINK_FLAGS) -Wl,-melf_x86_64,--oformat=elf64-x86-64,-pie
DEFINE GCC48_X64_DLINK2_FLAGS = -Wl,--defsym=PECOFF_HEADER_SIZE=0x228 DEF(GCC_DLINK2_FLAGS_COMMON)
DEFINE GCC48_ASM_FLAGS = DEF(GCC_ASM_FLAGS)
-DEFINE GCC48_ARM_ASM_FLAGS = $(ARCHASM_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_ASM_FLAGS) -mlittle-endian
-DEFINE GCC48_AARCH64_ASM_FLAGS = $(ARCHASM_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_ASM_FLAGS) -mlittle-endian
-DEFINE GCC48_ARM_CC_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_ARM_CC_FLAGS) -fstack-protector -mword-relocations
+DEFINE GCC48_ARM_ASM_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_ASM_FLAGS) -mlittle-endian
+DEFINE GCC48_AARCH64_ASM_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_ASM_FLAGS) -mlittle-endian
+DEFINE GCC48_ARM_CC_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_ARM_CC_FLAGS) -fstack-protector -mword-relocations
DEFINE GCC48_ARM_CC_XIPFLAGS = DEF(GCC_ARM_CC_XIPFLAGS)
-DEFINE GCC48_AARCH64_CC_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -mcmodel=large DEF(GCC_AARCH64_CC_FLAGS)
+DEFINE GCC48_AARCH64_CC_FLAGS = $(PLATFORM_FLAGS) -mcmodel=large DEF(GCC_AARCH64_CC_FLAGS)
DEFINE GCC48_AARCH64_CC_XIPFLAGS = DEF(GCC_AARCH64_CC_XIPFLAGS)
DEFINE GCC48_ARM_DLINK_FLAGS = DEF(GCC_ARM_DLINK_FLAGS) -Wl,--oformat=elf32-littlearm
DEFINE GCC48_ARM_DLINK2_FLAGS = DEF(GCC_DLINK2_FLAGS_COMMON) -Wl,--defsym=PECOFF_HEADER_SIZE=0x220
@@ -1925,7 +815,7 @@ DEFINE GCC49_ARM_ASM_FLAGS = DEF(GCC48_ARM_ASM_FLAGS)
DEFINE GCC49_AARCH64_ASM_FLAGS = DEF(GCC48_AARCH64_ASM_FLAGS)
DEFINE GCC49_ARM_CC_FLAGS = DEF(GCC48_ARM_CC_FLAGS)
DEFINE GCC49_ARM_CC_XIPFLAGS = DEF(GCC48_ARM_CC_XIPFLAGS)
-DEFINE GCC49_AARCH64_CC_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC48_ALL_CC_FLAGS) DEF(GCC_AARCH64_CC_FLAGS) -mcmodel=small
+DEFINE GCC49_AARCH64_CC_FLAGS = $(PLATFORM_FLAGS) DEF(GCC48_ALL_CC_FLAGS) DEF(GCC_AARCH64_CC_FLAGS) -mcmodel=small
DEFINE GCC49_AARCH64_CC_XIPFLAGS = DEF(GCC48_AARCH64_CC_XIPFLAGS)
DEFINE GCC49_ARM_DLINK_FLAGS = DEF(GCC48_ARM_DLINK_FLAGS)
DEFINE GCC49_ARM_DLINK2_FLAGS = DEF(GCC48_ARM_DLINK2_FLAGS)
@@ -1967,9 +857,9 @@ DEFINE GCC5_RISCV_ALL_CC_FLAGS_WARNING_DISABLE = -Wno-tautological-compare -W
DEFINE GCC5_RISCV_OPENSBI_TYPES = -DOPENSBI_EXTERNAL_SBI_TYPES=OpensbiTypes.h
-DEFINE GCC5_RISCV64_ARCH = rv64imafdc
+DEFINE GCC5_RISCV64_ARCH = rv64gc
DEFINE GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS = DEF(GCC5_RISCV_ALL_DLINK_COMMON) -Wl,--entry,ReferenceAcpiTable -u ReferenceAcpiTable
-DEFINE GCC5_RISCV64_CC_FLAGS = DEF(GCC5_RISCV_ALL_CC_FLAGS) DEF(GCC5_RISCV_ALL_CC_FLAGS_WARNING_DISABLE) DEF(GCC5_RISCV_OPENSBI_TYPES) -march=DEF(GCC5_RISCV64_ARCH) -fno-builtin -fno-builtin-memcpy -fno-stack-protector -Wno-address -fno-asynchronous-unwind-tables -Wno-unused-but-set-variable -fpack-struct=8 -mcmodel=medany -mabi=lp64 -mno-relax
+DEFINE GCC5_RISCV64_CC_FLAGS = DEF(GCC5_RISCV_ALL_CC_FLAGS) DEF(GCC5_RISCV_ALL_CC_FLAGS_WARNING_DISABLE) DEF(GCC5_RISCV_OPENSBI_TYPES) -march=DEF(GCC5_RISCV64_ARCH) -fno-builtin -fno-builtin-memcpy -fno-stack-protector -Wno-address -fno-asynchronous-unwind-tables -fno-unwind-tables -Wno-unused-but-set-variable -fpack-struct=8 -mcmodel=medany -mabi=lp64 -mno-relax
DEFINE GCC5_RISCV64_DLINK_FLAGS = DEF(GCC5_RISCV_ALL_DLINK_FLAGS) -Wl,-melf64lriscv,--oformat=elf64-littleriscv,--no-relax
DEFINE GCC5_RISCV64_DLINK2_FLAGS = DEF(GCC5_RISCV_ALL_DLINK2_FLAGS)
DEFINE GCC5_RISCV64_ASM_FLAGS = DEF(GCC5_RISCV_ALL_ASM_FLAGS) -march=DEF(GCC5_RISCV64_ARCH) -mcmodel=medany -mabi=lp64
@@ -1981,8 +871,6 @@ DEFINE GCC5_LOONGARCH64_ASLDLINK_FLAGS = DEF(GCC_LOONGARCH64_ASLDLINK_FLAGS)
DEFINE GCC5_LOONGARCH64_ASM_FLAGS = -x assembler-with-cpp -mabi=lp64d -march=loongarch64 -fno-builtin -c -Wall -mno-explicit-relocs
DEFINE GCC5_LOONGARCH64_PP_FLAGS = -mabi=lp64d -march=loongarch64 DEF(GCC_PP_FLAGS)
-DEFINE GCC_PP_FLAGS = -E -x assembler-with-cpp -include AutoGen.h DEF(GCC5_RISCV_OPENSBI_TYPES)
-
####################################################################################
#
# GCC 4.8 - This configuration is used to compile under Linux to produce
@@ -2028,8 +916,8 @@ DEFINE GCC_PP_FLAGS = -E -x assembler-with-cpp -include A
*_GCC48_IA32_OBJCOPY_FLAGS =
*_GCC48_IA32_NASM_FLAGS = -f elf32
- DEBUG_GCC48_IA32_CC_FLAGS = DEF(GCC48_IA32_CC_FLAGS) -Os
-RELEASE_GCC48_IA32_CC_FLAGS = DEF(GCC48_IA32_CC_FLAGS) -Os -Wno-unused-but-set-variable
+ DEBUG_GCC48_IA32_CC_FLAGS = DEF(GCC48_IA32_CC_FLAGS)
+RELEASE_GCC48_IA32_CC_FLAGS = DEF(GCC48_IA32_CC_FLAGS) -Wno-unused-but-set-variable
NOOPT_GCC48_IA32_CC_FLAGS = DEF(GCC48_IA32_CC_FLAGS) -O0
##################
@@ -2056,8 +944,8 @@ RELEASE_GCC48_IA32_CC_FLAGS = DEF(GCC48_IA32_CC_FLAGS) -Os -Wno-unused-but
*_GCC48_X64_OBJCOPY_FLAGS =
*_GCC48_X64_NASM_FLAGS = -f elf64
- DEBUG_GCC48_X64_CC_FLAGS = DEF(GCC48_X64_CC_FLAGS) -Os
-RELEASE_GCC48_X64_CC_FLAGS = DEF(GCC48_X64_CC_FLAGS) -Os -Wno-unused-but-set-variable
+ DEBUG_GCC48_X64_CC_FLAGS = DEF(GCC48_X64_CC_FLAGS)
+RELEASE_GCC48_X64_CC_FLAGS = DEF(GCC48_X64_CC_FLAGS) -Wno-unused-but-set-variable
NOOPT_GCC48_X64_CC_FLAGS = DEF(GCC48_X64_CC_FLAGS) -O0
##################
@@ -2074,9 +962,6 @@ RELEASE_GCC48_X64_CC_FLAGS = DEF(GCC48_X64_CC_FLAGS) -Os -Wno-unused-but-s
*_GCC48_ARM_ASLPP_PATH = ENV(GCC48_ARM_PREFIX)gcc
*_GCC48_ARM_RC_PATH = ENV(GCC48_ARM_PREFIX)objcopy
-*_GCC48_ARM_ARCHCC_FLAGS = -mthumb
-*_GCC48_ARM_PLATFORM_FLAGS = -march=armv7-a
-
*_GCC48_ARM_ASLCC_FLAGS = DEF(GCC48_ASLCC_FLAGS)
*_GCC48_ARM_ASLDLINK_FLAGS = DEF(GCC48_ARM_ASLDLINK_FLAGS)
*_GCC48_ARM_ASM_FLAGS = DEF(GCC48_ARM_ASM_FLAGS)
@@ -2084,9 +969,9 @@ RELEASE_GCC48_X64_CC_FLAGS = DEF(GCC48_X64_CC_FLAGS) -Os -Wno-unused-but-s
*_GCC48_ARM_DLINK2_FLAGS = DEF(GCC48_ARM_DLINK2_FLAGS)
*_GCC48_ARM_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)
*_GCC48_ARM_PLATFORM_FLAGS = -march=armv7-a
-*_GCC48_ARM_PP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS)
+*_GCC48_ARM_PP_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS)
*_GCC48_ARM_RC_FLAGS = DEF(GCC_ARM_RC_FLAGS)
-*_GCC48_ARM_VFRPP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS)
+*_GCC48_ARM_VFRPP_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS)
*_GCC48_ARM_CC_XIPFLAGS = DEF(GCC48_ARM_CC_XIPFLAGS)
DEBUG_GCC48_ARM_CC_FLAGS = DEF(GCC48_ARM_CC_FLAGS) -O0
@@ -2114,9 +999,9 @@ RELEASE_GCC48_ARM_CC_FLAGS = DEF(GCC48_ARM_CC_FLAGS) -Wno-unused-but-set-v
*_GCC48_AARCH64_DLINK2_FLAGS = DEF(GCC48_AARCH64_DLINK2_FLAGS)
*_GCC48_AARCH64_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)
*_GCC48_AARCH64_PLATFORM_FLAGS =
-*_GCC48_AARCH64_PP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS)
+*_GCC48_AARCH64_PP_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS)
*_GCC48_AARCH64_RC_FLAGS = DEF(GCC_AARCH64_RC_FLAGS)
-*_GCC48_AARCH64_VFRPP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS)
+*_GCC48_AARCH64_VFRPP_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS)
*_GCC48_AARCH64_CC_XIPFLAGS = DEF(GCC48_AARCH64_CC_XIPFLAGS)
DEBUG_GCC48_AARCH64_CC_FLAGS = DEF(GCC48_AARCH64_CC_FLAGS) -O0
@@ -2168,8 +1053,8 @@ RELEASE_GCC48_AARCH64_CC_FLAGS = DEF(GCC48_AARCH64_CC_FLAGS) -Wno-unused-but-s
*_GCC49_IA32_OBJCOPY_FLAGS =
*_GCC49_IA32_NASM_FLAGS = -f elf32
- DEBUG_GCC49_IA32_CC_FLAGS = DEF(GCC49_IA32_CC_FLAGS) -Os
-RELEASE_GCC49_IA32_CC_FLAGS = DEF(GCC49_IA32_CC_FLAGS) -Os -Wno-unused-but-set-variable -Wno-unused-const-variable
+ DEBUG_GCC49_IA32_CC_FLAGS = DEF(GCC49_IA32_CC_FLAGS)
+RELEASE_GCC49_IA32_CC_FLAGS = DEF(GCC49_IA32_CC_FLAGS) -Wno-unused-but-set-variable -Wno-unused-const-variable
NOOPT_GCC49_IA32_CC_FLAGS = DEF(GCC49_IA32_CC_FLAGS) -O0
##################
@@ -2196,8 +1081,8 @@ RELEASE_GCC49_IA32_CC_FLAGS = DEF(GCC49_IA32_CC_FLAGS) -Os -Wno-unused-but
*_GCC49_X64_OBJCOPY_FLAGS =
*_GCC49_X64_NASM_FLAGS = -f elf64
- DEBUG_GCC49_X64_CC_FLAGS = DEF(GCC49_X64_CC_FLAGS) -Os
-RELEASE_GCC49_X64_CC_FLAGS = DEF(GCC49_X64_CC_FLAGS) -Os -Wno-unused-but-set-variable -Wno-unused-const-variable
+ DEBUG_GCC49_X64_CC_FLAGS = DEF(GCC49_X64_CC_FLAGS)
+RELEASE_GCC49_X64_CC_FLAGS = DEF(GCC49_X64_CC_FLAGS) -Wno-unused-but-set-variable -Wno-unused-const-variable
NOOPT_GCC49_X64_CC_FLAGS = DEF(GCC49_X64_CC_FLAGS) -O0
##################
@@ -2214,9 +1099,6 @@ RELEASE_GCC49_X64_CC_FLAGS = DEF(GCC49_X64_CC_FLAGS) -Os -Wno-unused-but-s
*_GCC49_ARM_ASLPP_PATH = ENV(GCC49_ARM_PREFIX)gcc
*_GCC49_ARM_RC_PATH = ENV(GCC49_ARM_PREFIX)objcopy
-*_GCC49_ARM_ARCHCC_FLAGS = -mthumb
-*_GCC49_ARM_PLATFORM_FLAGS = -march=armv7-a
-
*_GCC49_ARM_ASLCC_FLAGS = DEF(GCC49_ASLCC_FLAGS)
*_GCC49_ARM_ASLDLINK_FLAGS = DEF(GCC49_ARM_ASLDLINK_FLAGS)
*_GCC49_ARM_ASM_FLAGS = DEF(GCC49_ARM_ASM_FLAGS)
@@ -2224,9 +1106,9 @@ RELEASE_GCC49_X64_CC_FLAGS = DEF(GCC49_X64_CC_FLAGS) -Os -Wno-unused-but-s
*_GCC49_ARM_DLINK2_FLAGS = DEF(GCC49_ARM_DLINK2_FLAGS)
*_GCC49_ARM_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)
*_GCC49_ARM_PLATFORM_FLAGS = -march=armv7-a
-*_GCC49_ARM_PP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS)
+*_GCC49_ARM_PP_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS)
*_GCC49_ARM_RC_FLAGS = DEF(GCC_ARM_RC_FLAGS)
-*_GCC49_ARM_VFRPP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS)
+*_GCC49_ARM_VFRPP_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS)
*_GCC49_ARM_CC_XIPFLAGS = DEF(GCC49_ARM_CC_XIPFLAGS)
DEBUG_GCC49_ARM_CC_FLAGS = DEF(GCC49_ARM_CC_FLAGS) -O0
@@ -2253,9 +1135,9 @@ RELEASE_GCC49_ARM_CC_FLAGS = DEF(GCC49_ARM_CC_FLAGS) -Wno-unused-but-set-v
*_GCC49_AARCH64_DLINK2_FLAGS = DEF(GCC49_AARCH64_DLINK2_FLAGS)
*_GCC49_AARCH64_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)
*_GCC49_AARCH64_PLATFORM_FLAGS =
-*_GCC49_AARCH64_PP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS)
+*_GCC49_AARCH64_PP_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS)
*_GCC49_AARCH64_RC_FLAGS = DEF(GCC_AARCH64_RC_FLAGS)
-*_GCC49_AARCH64_VFRPP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS)
+*_GCC49_AARCH64_VFRPP_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS)
*_GCC49_AARCH64_CC_XIPFLAGS = DEF(GCC49_AARCH64_CC_XIPFLAGS)
DEBUG_GCC49_AARCH64_CC_FLAGS = DEF(GCC49_AARCH64_CC_FLAGS) -O0
@@ -2270,6 +1152,150 @@ RELEASE_GCC49_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20
NOOPT_GCC49_AARCH64_DLINK_FLAGS = DEF(GCC49_AARCH64_DLINK_FLAGS) -O0
NOOPT_GCC49_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20 -O0
+####################################################################################
+#
+# GCC NOLTO - This configuration is used to compile under Linux to produce
+# PE/COFF binaries using GCC without Link Time Optimization
+#
+####################################################################################
+*_GCCNOLTO_*_*_FAMILY = GCC
+
+*_GCCNOLTO_*_MAKE_PATH = DEF(GCC_HOST_PREFIX)make
+*_GCCNOLTO_*_*_DLL = ENV(GCCNOLTO_DLL)
+*_GCCNOLTO_*_ASL_PATH = DEF(UNIX_IASL_BIN)
+
+*_GCCNOLTO_*_PP_FLAGS = DEF(GCC_PP_FLAGS)
+*_GCCNOLTO_*_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS)
+*_GCCNOLTO_*_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
+*_GCCNOLTO_*_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS)
+*_GCCNOLTO_*_APP_FLAGS =
+*_GCCNOLTO_*_ASL_FLAGS = DEF(IASL_FLAGS)
+*_GCCNOLTO_*_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS)
+*_GCCNOLTO_*_DEPS_FLAGS = DEF(GCC_DEPS_FLAGS)
+
+##################
+# GCCNOLTO IA32 definitions
+##################
+*_GCCNOLTO_IA32_OBJCOPY_PATH = DEF(GCCNOLTO_IA32_PREFIX)objcopy
+*_GCCNOLTO_IA32_CC_PATH = DEF(GCCNOLTO_IA32_PREFIX)gcc
+*_GCCNOLTO_IA32_SLINK_PATH = DEF(GCCNOLTO_IA32_PREFIX)ar
+*_GCCNOLTO_IA32_DLINK_PATH = DEF(GCCNOLTO_IA32_PREFIX)gcc
+*_GCCNOLTO_IA32_ASLDLINK_PATH = DEF(GCCNOLTO_IA32_PREFIX)gcc
+*_GCCNOLTO_IA32_ASM_PATH = DEF(GCCNOLTO_IA32_PREFIX)gcc
+*_GCCNOLTO_IA32_PP_PATH = DEF(GCCNOLTO_IA32_PREFIX)gcc
+*_GCCNOLTO_IA32_VFRPP_PATH = DEF(GCCNOLTO_IA32_PREFIX)gcc
+*_GCCNOLTO_IA32_ASLCC_PATH = DEF(GCCNOLTO_IA32_PREFIX)gcc
+*_GCCNOLTO_IA32_ASLPP_PATH = DEF(GCCNOLTO_IA32_PREFIX)gcc
+*_GCCNOLTO_IA32_RC_PATH = DEF(GCCNOLTO_IA32_PREFIX)objcopy
+
+*_GCCNOLTO_IA32_ASLCC_FLAGS = DEF(GCC49_ASLCC_FLAGS) -m32
+*_GCCNOLTO_IA32_ASLDLINK_FLAGS = DEF(GCC49_IA32_X64_ASLDLINK_FLAGS) -Wl,-m,elf_i386
+*_GCCNOLTO_IA32_ASM_FLAGS = DEF(GCC49_ASM_FLAGS) -m32 -march=i386
+*_GCCNOLTO_IA32_DLINK_FLAGS = DEF(GCC49_IA32_X64_DLINK_FLAGS) -Wl,-m,elf_i386,--oformat=elf32-i386
+*_GCCNOLTO_IA32_DLINK2_FLAGS = DEF(GCC49_IA32_DLINK2_FLAGS)
+*_GCCNOLTO_IA32_RC_FLAGS = DEF(GCC_IA32_RC_FLAGS)
+*_GCCNOLTO_IA32_OBJCOPY_FLAGS =
+*_GCCNOLTO_IA32_NASM_FLAGS = -f elf32
+
+ DEBUG_GCCNOLTO_IA32_CC_FLAGS = DEF(GCC49_IA32_CC_FLAGS)
+RELEASE_GCCNOLTO_IA32_CC_FLAGS = DEF(GCC49_IA32_CC_FLAGS) -Wno-unused-but-set-variable -Wno-unused-const-variable
+ NOOPT_GCCNOLTO_IA32_CC_FLAGS = DEF(GCC49_IA32_CC_FLAGS) -O0
+
+##################
+# GCCNOLTO X64 definitions
+##################
+*_GCCNOLTO_X64_OBJCOPY_PATH = DEF(GCCNOLTO_X64_PREFIX)objcopy
+*_GCCNOLTO_X64_CC_PATH = DEF(GCCNOLTO_X64_PREFIX)gcc
+*_GCCNOLTO_X64_SLINK_PATH = DEF(GCCNOLTO_X64_PREFIX)ar
+*_GCCNOLTO_X64_DLINK_PATH = DEF(GCCNOLTO_X64_PREFIX)gcc
+*_GCCNOLTO_X64_ASLDLINK_PATH = DEF(GCCNOLTO_X64_PREFIX)gcc
+*_GCCNOLTO_X64_ASM_PATH = DEF(GCCNOLTO_X64_PREFIX)gcc
+*_GCCNOLTO_X64_PP_PATH = DEF(GCCNOLTO_X64_PREFIX)gcc
+*_GCCNOLTO_X64_VFRPP_PATH = DEF(GCCNOLTO_X64_PREFIX)gcc
+*_GCCNOLTO_X64_ASLCC_PATH = DEF(GCCNOLTO_X64_PREFIX)gcc
+*_GCCNOLTO_X64_ASLPP_PATH = DEF(GCCNOLTO_X64_PREFIX)gcc
+*_GCCNOLTO_X64_RC_PATH = DEF(GCCNOLTO_X64_PREFIX)objcopy
+
+*_GCCNOLTO_X64_ASLCC_FLAGS = DEF(GCC49_ASLCC_FLAGS) -m64
+*_GCCNOLTO_X64_ASLDLINK_FLAGS = DEF(GCC49_IA32_X64_ASLDLINK_FLAGS) -Wl,-m,elf_x86_64
+*_GCCNOLTO_X64_ASM_FLAGS = DEF(GCC49_ASM_FLAGS) -m64
+*_GCCNOLTO_X64_DLINK_FLAGS = DEF(GCC49_X64_DLINK_FLAGS)
+*_GCCNOLTO_X64_DLINK2_FLAGS = DEF(GCC49_X64_DLINK2_FLAGS)
+*_GCCNOLTO_X64_RC_FLAGS = DEF(GCC_X64_RC_FLAGS)
+*_GCCNOLTO_X64_OBJCOPY_FLAGS =
+*_GCCNOLTO_X64_NASM_FLAGS = -f elf64
+
+ DEBUG_GCCNOLTO_X64_CC_FLAGS = DEF(GCC49_X64_CC_FLAGS)
+RELEASE_GCCNOLTO_X64_CC_FLAGS = DEF(GCC49_X64_CC_FLAGS) -Wno-unused-but-set-variable -Wno-unused-const-variable
+ NOOPT_GCCNOLTO_X64_CC_FLAGS = DEF(GCC49_X64_CC_FLAGS) -O0
+
+##################
+# GCCNOLTO ARM definitions
+##################
+*_GCCNOLTO_ARM_CC_PATH = ENV(GCCNOLTO_ARM_PREFIX)gcc
+*_GCCNOLTO_ARM_SLINK_PATH = ENV(GCCNOLTO_ARM_PREFIX)ar
+*_GCCNOLTO_ARM_DLINK_PATH = ENV(GCCNOLTO_ARM_PREFIX)gcc
+*_GCCNOLTO_ARM_ASLDLINK_PATH = ENV(GCCNOLTO_ARM_PREFIX)gcc
+*_GCCNOLTO_ARM_ASM_PATH = ENV(GCCNOLTO_ARM_PREFIX)gcc
+*_GCCNOLTO_ARM_PP_PATH = ENV(GCCNOLTO_ARM_PREFIX)gcc
+*_GCCNOLTO_ARM_VFRPP_PATH = ENV(GCCNOLTO_ARM_PREFIX)gcc
+*_GCCNOLTO_ARM_ASLCC_PATH = ENV(GCCNOLTO_ARM_PREFIX)gcc
+*_GCCNOLTO_ARM_ASLPP_PATH = ENV(GCCNOLTO_ARM_PREFIX)gcc
+*_GCCNOLTO_ARM_RC_PATH = ENV(GCCNOLTO_ARM_PREFIX)objcopy
+
+*_GCCNOLTO_ARM_ASLCC_FLAGS = DEF(GCC49_ASLCC_FLAGS)
+*_GCCNOLTO_ARM_ASLDLINK_FLAGS = DEF(GCC49_ARM_ASLDLINK_FLAGS)
+*_GCCNOLTO_ARM_ASM_FLAGS = DEF(GCC49_ARM_ASM_FLAGS)
+*_GCCNOLTO_ARM_DLINK_FLAGS = DEF(GCC49_ARM_DLINK_FLAGS)
+*_GCCNOLTO_ARM_DLINK2_FLAGS = DEF(GCC49_ARM_DLINK2_FLAGS)
+*_GCCNOLTO_ARM_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)
+*_GCCNOLTO_ARM_PLATFORM_FLAGS = -march=armv7-a
+*_GCCNOLTO_ARM_PP_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS)
+*_GCCNOLTO_ARM_RC_FLAGS = DEF(GCC_ARM_RC_FLAGS)
+*_GCCNOLTO_ARM_VFRPP_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS)
+*_GCCNOLTO_ARM_CC_XIPFLAGS = DEF(GCC49_ARM_CC_XIPFLAGS)
+
+ DEBUG_GCCNOLTO_ARM_CC_FLAGS = DEF(GCC49_ARM_CC_FLAGS) -O0
+RELEASE_GCCNOLTO_ARM_CC_FLAGS = DEF(GCC49_ARM_CC_FLAGS) -Wno-unused-but-set-variable -Wno-unused-const-variable
+ NOOPT_GCCNOLTO_ARM_CC_FLAGS = DEF(GCC49_ARM_CC_FLAGS) -O0
+
+##################
+# GCCNOLTO AARCH64 definitions
+##################
+*_GCCNOLTO_AARCH64_CC_PATH = ENV(GCCNOLTO_AARCH64_PREFIX)gcc
+*_GCCNOLTO_AARCH64_SLINK_PATH = ENV(GCCNOLTO_AARCH64_PREFIX)ar
+*_GCCNOLTO_AARCH64_DLINK_PATH = ENV(GCCNOLTO_AARCH64_PREFIX)gcc
+*_GCCNOLTO_AARCH64_ASLDLINK_PATH = ENV(GCCNOLTO_AARCH64_PREFIX)gcc
+*_GCCNOLTO_AARCH64_ASM_PATH = ENV(GCCNOLTO_AARCH64_PREFIX)gcc
+*_GCCNOLTO_AARCH64_PP_PATH = ENV(GCCNOLTO_AARCH64_PREFIX)gcc
+*_GCCNOLTO_AARCH64_VFRPP_PATH = ENV(GCCNOLTO_AARCH64_PREFIX)gcc
+*_GCCNOLTO_AARCH64_ASLCC_PATH = ENV(GCCNOLTO_AARCH64_PREFIX)gcc
+*_GCCNOLTO_AARCH64_ASLPP_PATH = ENV(GCCNOLTO_AARCH64_PREFIX)gcc
+*_GCCNOLTO_AARCH64_RC_PATH = ENV(GCCNOLTO_AARCH64_PREFIX)objcopy
+
+*_GCCNOLTO_AARCH64_ASLCC_FLAGS = DEF(GCC49_ASLCC_FLAGS)
+*_GCCNOLTO_AARCH64_ASLDLINK_FLAGS = DEF(GCC49_AARCH64_ASLDLINK_FLAGS)
+*_GCCNOLTO_AARCH64_ASM_FLAGS = DEF(GCC49_AARCH64_ASM_FLAGS)
+*_GCCNOLTO_AARCH64_DLINK2_FLAGS = DEF(GCC49_AARCH64_DLINK2_FLAGS)
+*_GCCNOLTO_AARCH64_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)
+*_GCCNOLTO_AARCH64_PLATFORM_FLAGS =
+*_GCCNOLTO_AARCH64_PP_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS)
+*_GCCNOLTO_AARCH64_RC_FLAGS = DEF(GCC_AARCH64_RC_FLAGS)
+*_GCCNOLTO_AARCH64_VFRPP_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS)
+*_GCCNOLTO_AARCH64_CC_XIPFLAGS = DEF(GCC49_AARCH64_CC_XIPFLAGS)
+
+ DEBUG_GCCNOLTO_AARCH64_CC_FLAGS = DEF(GCC49_AARCH64_CC_FLAGS) -O0
+ DEBUG_GCCNOLTO_AARCH64_DLINK_FLAGS = DEF(GCC49_AARCH64_DLINK_FLAGS)
+ DEBUG_GCCNOLTO_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20
+
+RELEASE_GCCNOLTO_AARCH64_CC_FLAGS = DEF(GCC49_AARCH64_CC_FLAGS) -Wno-unused-but-set-variable -Wno-unused-const-variable
+RELEASE_GCCNOLTO_AARCH64_DLINK_FLAGS = DEF(GCC49_AARCH64_DLINK_FLAGS)
+RELEASE_GCCNOLTO_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20
+
+ NOOPT_GCCNOLTO_AARCH64_CC_FLAGS = DEF(GCC49_AARCH64_CC_FLAGS) -O0
+ NOOPT_GCCNOLTO_AARCH64_DLINK_FLAGS = DEF(GCC49_AARCH64_DLINK_FLAGS) -O0
+ NOOPT_GCCNOLTO_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20 -O0
+
####################################################################################
#
# GCC 5 - This configuration is used to compile under Linux to produce
@@ -2314,10 +1340,10 @@ RELEASE_GCC49_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20
*_GCC5_IA32_OBJCOPY_FLAGS =
*_GCC5_IA32_NASM_FLAGS = -f elf32
- DEBUG_GCC5_IA32_CC_FLAGS = DEF(GCC5_IA32_CC_FLAGS) -flto -Os
+ DEBUG_GCC5_IA32_CC_FLAGS = DEF(GCC5_IA32_CC_FLAGS) -flto
DEBUG_GCC5_IA32_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -flto -Os -Wl,-m,elf_i386,--oformat=elf32-i386
-RELEASE_GCC5_IA32_CC_FLAGS = DEF(GCC5_IA32_CC_FLAGS) -flto -Os -Wno-unused-but-set-variable -Wno-unused-const-variable
+RELEASE_GCC5_IA32_CC_FLAGS = DEF(GCC5_IA32_CC_FLAGS) -flto -Wno-unused-but-set-variable -Wno-unused-const-variable
RELEASE_GCC5_IA32_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -flto -Os -Wl,-m,elf_i386,--oformat=elf32-i386
NOOPT_GCC5_IA32_CC_FLAGS = DEF(GCC5_IA32_CC_FLAGS) -O0
@@ -2346,10 +1372,10 @@ RELEASE_GCC5_IA32_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -flto -Os -Wl,
*_GCC5_X64_OBJCOPY_FLAGS =
*_GCC5_X64_NASM_FLAGS = -f elf64
- DEBUG_GCC5_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -flto -DUSING_LTO -Os
+ DEBUG_GCC5_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -flto -DUSING_LTO
DEBUG_GCC5_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) -flto -Os
-RELEASE_GCC5_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -flto -DUSING_LTO -Os -Wno-unused-but-set-variable -Wno-unused-const-variable
+RELEASE_GCC5_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -flto -DUSING_LTO -Wno-unused-but-set-variable -Wno-unused-const-variable
RELEASE_GCC5_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) -flto -Os
NOOPT_GCC5_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -O0
@@ -2369,16 +1395,15 @@ RELEASE_GCC5_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) -flto -Os
*_GCC5_ARM_ASLPP_PATH = ENV(GCC5_ARM_PREFIX)gcc
*_GCC5_ARM_RC_PATH = ENV(GCC5_ARM_PREFIX)objcopy
-*_GCC5_ARM_ARCHCC_FLAGS = -mthumb
*_GCC5_ARM_ASLCC_FLAGS = DEF(GCC5_ASLCC_FLAGS)
*_GCC5_ARM_ASLDLINK_FLAGS = DEF(GCC5_ARM_ASLDLINK_FLAGS)
*_GCC5_ARM_ASM_FLAGS = DEF(GCC5_ARM_ASM_FLAGS)
*_GCC5_ARM_DLINK2_FLAGS = DEF(GCC5_ARM_DLINK2_FLAGS)
*_GCC5_ARM_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)
-*_GCC5_ARM_PLATFORM_FLAGS = -march=armv7-a
-*_GCC5_ARM_PP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS)
+*_GCC5_ARM_PLATFORM_FLAGS = -march=armv7-a -mfloat-abi=soft
+*_GCC5_ARM_PP_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS)
*_GCC5_ARM_RC_FLAGS = DEF(GCC_ARM_RC_FLAGS)
-*_GCC5_ARM_VFRPP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS)
+*_GCC5_ARM_VFRPP_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS)
*_GCC5_ARM_CC_XIPFLAGS = DEF(GCC5_ARM_CC_XIPFLAGS)
DEBUG_GCC5_ARM_CC_FLAGS = DEF(GCC5_ARM_CC_FLAGS) -flto -Wno-unused-but-set-variable -Wno-unused-const-variable
@@ -2410,9 +1435,9 @@ RELEASE_GCC5_ARM_DLINK_FLAGS = DEF(GCC5_ARM_DLINK_FLAGS) -flto -Os -L$(WORKS
*_GCC5_AARCH64_DLINK2_FLAGS = DEF(GCC5_AARCH64_DLINK2_FLAGS)
*_GCC5_AARCH64_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)
*_GCC5_AARCH64_PLATFORM_FLAGS =
-*_GCC5_AARCH64_PP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS)
-*_GCC5_AARCH64_RC_FLAGS = DEF(GCC_AARCH64_RC_FLAGS)
-*_GCC5_AARCH64_VFRPP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS)
+*_GCC5_AARCH64_PP_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS)
+*_GCC5_AARCH64_RC_FLAGS = DEF(GCC_AARCH64_RC_FLAGS) DEF(GCC_AARCH64_RC_BTI_FLAGS)
+*_GCC5_AARCH64_VFRPP_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS)
*_GCC5_AARCH64_CC_XIPFLAGS = DEF(GCC5_AARCH64_CC_XIPFLAGS)
DEBUG_GCC5_AARCH64_CC_FLAGS = DEF(GCC5_AARCH64_CC_FLAGS) -flto -Wno-unused-but-set-variable -Wno-unused-const-variable
@@ -2458,6 +1483,7 @@ RELEASE_GCC5_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20
*_GCC5_RISCV64_RC_FLAGS = DEF(GCC_RISCV64_RC_FLAGS)
*_GCC5_RISCV64_OBJCOPY_FLAGS =
*_GCC5_RISCV64_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)
+*_GCC5_RISCV64_PP_FLAGS = DEF(GCC_PP_FLAGS) DEF(GCC5_RISCV_OPENSBI_TYPES)
##################
# GCC5 LOONGARCH64 definitions
@@ -2489,273 +1515,220 @@ RELEASE_GCC5_LOONGARCH64_CC_FLAGS = DEF(GCC5_LOONGARCH64_CC_FLAGS) -Wno-un
####################################################################################
#
-# CLANG35 - This configuration is used to compile under Linux to produce
-# PE/COFF binaries using the clang compiler and assembler (v3.5 and up)
-# and GNU linker
+# GCC - This configuration is used to compile under Linux to produce
+# PE/COFF binaries using GCC 5 or newer
#
####################################################################################
-*_CLANG35_*_*_FAMILY = GCC
+*_GCC_*_*_FAMILY = GCC
-*_CLANG35_*_MAKE_PATH = make
-*_CLANG35_*_*_DLL = ENV(CLANG35_DLL)
-*_CLANG35_*_ASL_PATH = DEF(UNIX_IASL_BIN)
+*_GCC_*_MAKE_PATH = DEF(GCC_HOST_PREFIX)make
+*_GCC_*_*_DLL = ENV(GCC_DLL)
+*_GCC_*_ASL_PATH = DEF(UNIX_IASL_BIN)
-*_CLANG35_*_PP_FLAGS = DEF(GCC_PP_FLAGS)
-*_CLANG35_*_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
-*_CLANG35_*_APP_FLAGS =
-*_CLANG35_*_ASL_FLAGS = DEF(IASL_FLAGS)
-*_CLANG35_*_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS)
-*_CLANG35_*_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)
-
-*_CLANG35_*_CC_PATH = ENV(CLANG35_BIN)clang
-*_CLANG35_*_ASM_PATH = ENV(CLANG35_BIN)clang
-*_CLANG35_*_PP_PATH = ENV(CLANG35_BIN)clang
-*_CLANG35_*_VFRPP_PATH = ENV(CLANG35_BIN)clang
-*_CLANG35_*_ASLCC_PATH = ENV(CLANG35_BIN)clang
-*_CLANG35_*_ASLPP_PATH = ENV(CLANG35_BIN)clang
-*_CLANG35_*_DLINK_PATH = ENV(CLANG35_BIN)clang
-*_CLANG35_*_ASLDLINK_PATH = ENV(CLANG35_BIN)clang
-*_CLANG35_*_DEPS_FLAGS = DEF(GCC_DEPS_FLAGS)
-
-DEFINE CLANG35_ARM_TARGET = -target arm-linux-gnueabi
-DEFINE CLANG35_AARCH64_TARGET = -target aarch64-linux-gnu
-
-DEFINE CLANG35_WARNING_OVERRIDES = -Wno-parentheses-equality -Wno-tautological-compare -Wno-tautological-constant-out-of-range-compare -Wno-empty-body -Wno-unknown-warning-option -Wno-unused-but-set-variable -Wno-unused-const-variable
-DEFINE CLANG35_ARM_CC_FLAGS = DEF(GCC_ARM_CC_FLAGS) DEF(CLANG35_ARM_TARGET) DEF(CLANG35_WARNING_OVERRIDES)
-DEFINE CLANG35_AARCH64_CC_FLAGS = DEF(GCC_AARCH64_CC_FLAGS) DEF(CLANG35_AARCH64_TARGET) -mcmodel=small DEF(CLANG35_WARNING_OVERRIDES)
+*_GCC_*_PP_FLAGS = DEF(GCC_PP_FLAGS)
+*_GCC_*_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS)
+*_GCC_*_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
+*_GCC_*_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS)
+*_GCC_*_APP_FLAGS =
+*_GCC_*_ASL_FLAGS = DEF(IASL_FLAGS)
+*_GCC_*_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS)
+*_GCC_*_DEPS_FLAGS = DEF(GCC_DEPS_FLAGS)
##################
-# CLANG35 ARM definitions
+# GCC IA32 definitions
##################
-*_CLANG35_ARM_SLINK_PATH = ENV(CLANG35_ARM_PREFIX)ar
-*_CLANG35_ARM_RC_PATH = ENV(CLANG35_ARM_PREFIX)objcopy
+*_GCC_IA32_OBJCOPY_PATH = DEF(GCC_IA32_PREFIX)objcopy
+*_GCC_IA32_CC_PATH = DEF(GCC_IA32_PREFIX)gcc
+*_GCC_IA32_SLINK_PATH = DEF(GCC_IA32_PREFIX)gcc-ar
+*_GCC_IA32_DLINK_PATH = DEF(GCC_IA32_PREFIX)gcc
+*_GCC_IA32_ASLDLINK_PATH = DEF(GCC_IA32_PREFIX)gcc
+*_GCC_IA32_ASM_PATH = DEF(GCC_IA32_PREFIX)gcc
+*_GCC_IA32_PP_PATH = DEF(GCC_IA32_PREFIX)gcc
+*_GCC_IA32_VFRPP_PATH = DEF(GCC_IA32_PREFIX)gcc
+*_GCC_IA32_ASLCC_PATH = DEF(GCC_IA32_PREFIX)gcc
+*_GCC_IA32_ASLPP_PATH = DEF(GCC_IA32_PREFIX)gcc
+*_GCC_IA32_RC_PATH = DEF(GCC_IA32_PREFIX)objcopy
-*_CLANG35_ARM_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
-*_CLANG35_ARM_ASLDLINK_FLAGS = DEF(CLANG35_ARM_TARGET) DEF(GCC_ARM_ASLDLINK_FLAGS)
-*_CLANG35_ARM_ASM_FLAGS = DEF(GCC_ASM_FLAGS) DEF(CLANG35_ARM_TARGET) $(ARCHASM_FLAGS) $(PLATFORM_FLAGS) -Qunused-arguments
-*_CLANG35_ARM_DLINK_FLAGS = DEF(CLANG35_ARM_TARGET) DEF(GCC_ARM_DLINK_FLAGS)
-*_CLANG35_ARM_DLINK2_FLAGS = DEF(GCC_DLINK2_FLAGS_COMMON) -Wl,--defsym=PECOFF_HEADER_SIZE=0x220
-*_CLANG35_ARM_PLATFORM_FLAGS = -march=armv7-a -mkernel -Qunused-arguments
-*_CLANG35_ARM_PP_FLAGS = DEF(GCC_PP_FLAGS) DEF(CLANG35_ARM_TARGET) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS)
-*_CLANG35_ARM_RC_FLAGS = DEF(GCC_ARM_RC_FLAGS)
-*_CLANG35_ARM_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) DEF(CLANG35_ARM_TARGET) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS)
-*_CLANG35_ARM_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) DEF(CLANG35_ARM_TARGET)
-*_CLANG35_ARM_CC_XIPFLAGS = DEF(GCC_ARM_CC_XIPFLAGS)
+*_GCC_IA32_ASLCC_FLAGS = DEF(GCC5_ASLCC_FLAGS) -m32
+*_GCC_IA32_ASLDLINK_FLAGS = DEF(GCC5_IA32_X64_ASLDLINK_FLAGS) -Wl,-m,elf_i386 -no-pie
+*_GCC_IA32_ASM_FLAGS = DEF(GCC5_ASM_FLAGS) -m32 -march=i386
+*_GCC_IA32_DLINK2_FLAGS = DEF(GCC5_IA32_DLINK2_FLAGS) -no-pie
+*_GCC_IA32_RC_FLAGS = DEF(GCC_IA32_RC_FLAGS)
+*_GCC_IA32_OBJCOPY_FLAGS =
+*_GCC_IA32_NASM_FLAGS = -f elf32
- DEBUG_CLANG35_ARM_CC_FLAGS = DEF(CLANG35_ARM_CC_FLAGS) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -O1
-RELEASE_CLANG35_ARM_CC_FLAGS = DEF(CLANG35_ARM_CC_FLAGS) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -Oz
- NOOPT_CLANG35_ARM_CC_FLAGS = DEF(CLANG35_ARM_CC_FLAGS) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -O0
+ DEBUG_GCC_IA32_CC_FLAGS = DEF(GCC5_IA32_CC_FLAGS) -flto
+ DEBUG_GCC_IA32_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -flto -Os -Wl,-m,elf_i386,--oformat=elf32-i386
+
+RELEASE_GCC_IA32_CC_FLAGS = DEF(GCC5_IA32_CC_FLAGS) -flto -Wno-unused-but-set-variable -Wno-unused-const-variable
+RELEASE_GCC_IA32_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -flto -Os -Wl,-m,elf_i386,--oformat=elf32-i386
+
+ NOOPT_GCC_IA32_CC_FLAGS = DEF(GCC5_IA32_CC_FLAGS) -O0
+ NOOPT_GCC_IA32_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -Wl,-m,elf_i386,--oformat=elf32-i386 -O0
##################
-# CLANG35 AARCH64 definitions
+# GCC X64 definitions
##################
-*_CLANG35_AARCH64_SLINK_PATH = ENV(CLANG35_AARCH64_PREFIX)ar
-*_CLANG35_AARCH64_RC_PATH = ENV(CLANG35_AARCH64_PREFIX)objcopy
+*_GCC_X64_OBJCOPY_PATH = DEF(GCC_X64_PREFIX)objcopy
+*_GCC_X64_CC_PATH = DEF(GCC_X64_PREFIX)gcc
+*_GCC_X64_SLINK_PATH = DEF(GCC_X64_PREFIX)gcc-ar
+*_GCC_X64_DLINK_PATH = DEF(GCC_X64_PREFIX)gcc
+*_GCC_X64_ASLDLINK_PATH = DEF(GCC_X64_PREFIX)gcc
+*_GCC_X64_ASM_PATH = DEF(GCC_X64_PREFIX)gcc
+*_GCC_X64_PP_PATH = DEF(GCC_X64_PREFIX)gcc
+*_GCC_X64_VFRPP_PATH = DEF(GCC_X64_PREFIX)gcc
+*_GCC_X64_ASLCC_PATH = DEF(GCC_X64_PREFIX)gcc
+*_GCC_X64_ASLPP_PATH = DEF(GCC_X64_PREFIX)gcc
+*_GCC_X64_RC_PATH = DEF(GCC_X64_PREFIX)objcopy
-*_CLANG35_AARCH64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
-*_CLANG35_AARCH64_ASLDLINK_FLAGS = DEF(CLANG35_AARCH64_TARGET) DEF(GCC_AARCH64_ASLDLINK_FLAGS)
-*_CLANG35_AARCH64_ASM_FLAGS = DEF(GCC_ASM_FLAGS) DEF(CLANG35_AARCH64_TARGET) $(ARCHASM_FLAGS) $(PLATFORM_FLAGS) -Qunused-arguments
-*_CLANG35_AARCH64_DLINK_FLAGS = DEF(CLANG35_AARCH64_TARGET) DEF(GCC_AARCH64_DLINK_FLAGS) -z common-page-size=0x1000
-*_CLANG35_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20
-*_CLANG35_AARCH64_DLINK2_FLAGS = DEF(GCC_DLINK2_FLAGS_COMMON) -Wl,--defsym=PECOFF_HEADER_SIZE=0x228
-*_CLANG35_AARCH64_PLATFORM_FLAGS =
-*_CLANG35_AARCH64_PP_FLAGS = DEF(GCC_PP_FLAGS) DEF(CLANG35_AARCH64_TARGET) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS)
-*_CLANG35_AARCH64_RC_FLAGS = DEF(GCC_AARCH64_RC_FLAGS)
-*_CLANG35_AARCH64_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) DEF(CLANG35_AARCH64_TARGET) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS)
-*_CLANG35_AARCH64_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) DEF(CLANG35_AARCH64_TARGET)
-*_CLANG35_AARCH64_CC_XIPFLAGS = DEF(GCC_AARCH64_CC_XIPFLAGS)
+*_GCC_X64_ASLCC_FLAGS = DEF(GCC5_ASLCC_FLAGS) -m64
+*_GCC_X64_ASLDLINK_FLAGS = DEF(GCC5_IA32_X64_ASLDLINK_FLAGS) -Wl,-m,elf_x86_64
+*_GCC_X64_ASM_FLAGS = DEF(GCC5_ASM_FLAGS) -m64
+*_GCC_X64_DLINK2_FLAGS = DEF(GCC5_X64_DLINK2_FLAGS)
+*_GCC_X64_RC_FLAGS = DEF(GCC_X64_RC_FLAGS)
+*_GCC_X64_OBJCOPY_FLAGS =
+*_GCC_X64_NASM_FLAGS = -f elf64
- DEBUG_CLANG35_AARCH64_CC_FLAGS = DEF(CLANG35_AARCH64_CC_FLAGS) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -O1
-RELEASE_CLANG35_AARCH64_CC_FLAGS = DEF(CLANG35_AARCH64_CC_FLAGS) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -Oz
- NOOPT_CLANG35_AARCH64_CC_FLAGS = DEF(CLANG35_AARCH64_CC_FLAGS) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -O0
+ DEBUG_GCC_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -flto -DUSING_LTO
+ DEBUG_GCC_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) -flto -Os
+
+RELEASE_GCC_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -flto -DUSING_LTO -Wno-unused-but-set-variable -Wno-unused-const-variable
+RELEASE_GCC_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) -flto -Os
+
+ NOOPT_GCC_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -O0
+ NOOPT_GCC_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) -O0
+
+##################
+# GCC ARM definitions
+##################
+*_GCC_ARM_CC_PATH = ENV(GCC_ARM_PREFIX)gcc
+*_GCC_ARM_SLINK_PATH = ENV(GCC_ARM_PREFIX)gcc-ar
+*_GCC_ARM_DLINK_PATH = ENV(GCC_ARM_PREFIX)gcc
+*_GCC_ARM_ASLDLINK_PATH = ENV(GCC_ARM_PREFIX)gcc
+*_GCC_ARM_ASM_PATH = ENV(GCC_ARM_PREFIX)gcc
+*_GCC_ARM_PP_PATH = ENV(GCC_ARM_PREFIX)gcc
+*_GCC_ARM_VFRPP_PATH = ENV(GCC_ARM_PREFIX)gcc
+*_GCC_ARM_ASLCC_PATH = ENV(GCC_ARM_PREFIX)gcc
+*_GCC_ARM_ASLPP_PATH = ENV(GCC_ARM_PREFIX)gcc
+*_GCC_ARM_RC_PATH = ENV(GCC_ARM_PREFIX)objcopy
+
+*_GCC_ARM_ASLCC_FLAGS = DEF(GCC5_ASLCC_FLAGS)
+*_GCC_ARM_ASLDLINK_FLAGS = DEF(GCC5_ARM_ASLDLINK_FLAGS)
+*_GCC_ARM_ASM_FLAGS = DEF(GCC5_ARM_ASM_FLAGS)
+*_GCC_ARM_DLINK2_FLAGS = DEF(GCC5_ARM_DLINK2_FLAGS)
+*_GCC_ARM_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)
+*_GCC_ARM_PLATFORM_FLAGS = -march=armv7-a -mfloat-abi=soft
+*_GCC_ARM_PP_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS)
+*_GCC_ARM_RC_FLAGS = DEF(GCC_ARM_RC_FLAGS)
+*_GCC_ARM_VFRPP_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS)
+*_GCC_ARM_CC_XIPFLAGS = DEF(GCC5_ARM_CC_XIPFLAGS)
+
+ DEBUG_GCC_ARM_CC_FLAGS = DEF(GCC5_ARM_CC_FLAGS) -flto -Wno-unused-but-set-variable -Wno-unused-const-variable
+ DEBUG_GCC_ARM_DLINK_FLAGS = DEF(GCC5_ARM_DLINK_FLAGS) -flto -Os -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-arm -Wl,-plugin-opt=-pass-through=-llto-arm
+
+RELEASE_GCC_ARM_CC_FLAGS = DEF(GCC5_ARM_CC_FLAGS) -flto -Wno-unused-but-set-variable -Wno-unused-const-variable
+RELEASE_GCC_ARM_DLINK_FLAGS = DEF(GCC5_ARM_DLINK_FLAGS) -flto -Os -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-arm -Wl,-plugin-opt=-pass-through=-llto-arm
+
+ NOOPT_GCC_ARM_CC_FLAGS = DEF(GCC5_ARM_CC_FLAGS) -O0
+ NOOPT_GCC_ARM_DLINK_FLAGS = DEF(GCC5_ARM_DLINK_FLAGS) -O0
+
+##################
+# GCC AARCH64 definitions
+##################
+*_GCC_AARCH64_CC_PATH = ENV(GCC_AARCH64_PREFIX)gcc
+*_GCC_AARCH64_SLINK_PATH = ENV(GCC_AARCH64_PREFIX)gcc-ar
+*_GCC_AARCH64_DLINK_PATH = ENV(GCC_AARCH64_PREFIX)gcc
+*_GCC_AARCH64_ASLDLINK_PATH = ENV(GCC_AARCH64_PREFIX)gcc
+*_GCC_AARCH64_ASM_PATH = ENV(GCC_AARCH64_PREFIX)gcc
+*_GCC_AARCH64_PP_PATH = ENV(GCC_AARCH64_PREFIX)gcc
+*_GCC_AARCH64_VFRPP_PATH = ENV(GCC_AARCH64_PREFIX)gcc
+*_GCC_AARCH64_ASLCC_PATH = ENV(GCC_AARCH64_PREFIX)gcc
+*_GCC_AARCH64_ASLPP_PATH = ENV(GCC_AARCH64_PREFIX)gcc
+*_GCC_AARCH64_RC_PATH = ENV(GCC_AARCH64_PREFIX)objcopy
+
+*_GCC_AARCH64_ASLCC_FLAGS = DEF(GCC5_ASLCC_FLAGS)
+*_GCC_AARCH64_ASLDLINK_FLAGS = DEF(GCC5_AARCH64_ASLDLINK_FLAGS)
+*_GCC_AARCH64_ASM_FLAGS = DEF(GCC5_AARCH64_ASM_FLAGS)
+*_GCC_AARCH64_DLINK2_FLAGS = DEF(GCC5_AARCH64_DLINK2_FLAGS)
+*_GCC_AARCH64_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)
+*_GCC_AARCH64_PLATFORM_FLAGS =
+*_GCC_AARCH64_PP_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS)
+*_GCC_AARCH64_RC_FLAGS = DEF(GCC_AARCH64_RC_FLAGS) DEF(GCC_AARCH64_RC_BTI_FLAGS)
+*_GCC_AARCH64_VFRPP_FLAGS = $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS)
+*_GCC_AARCH64_CC_XIPFLAGS = DEF(GCC5_AARCH64_CC_XIPFLAGS)
+
+ DEBUG_GCC_AARCH64_CC_FLAGS = DEF(GCC5_AARCH64_CC_FLAGS) -flto -Wno-unused-but-set-variable -Wno-unused-const-variable
+ DEBUG_GCC_AARCH64_DLINK_FLAGS = DEF(GCC5_AARCH64_DLINK_FLAGS) -flto -Os -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-aarch64 -Wl,-plugin-opt=-pass-through=-llto-aarch64 -Wno-lto-type-mismatch
+ DEBUG_GCC_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20
+
+RELEASE_GCC_AARCH64_CC_FLAGS = DEF(GCC5_AARCH64_CC_FLAGS) -flto -Wno-unused-but-set-variable -Wno-unused-const-variable
+RELEASE_GCC_AARCH64_DLINK_FLAGS = DEF(GCC5_AARCH64_DLINK_FLAGS) -flto -Os -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-aarch64 -Wl,-plugin-opt=-pass-through=-llto-aarch64 -Wno-lto-type-mismatch
+RELEASE_GCC_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20
+
+ NOOPT_GCC_AARCH64_CC_FLAGS = DEF(GCC5_AARCH64_CC_FLAGS) -O0
+ NOOPT_GCC_AARCH64_DLINK_FLAGS = DEF(GCC5_AARCH64_DLINK_FLAGS) -O0
+ NOOPT_GCC_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20 -O0
####################################################################################
#
-# Clang 3.8 - This configuration is used to compile under Linux to produce
-# PE/COFF binaries using LLVM/Clang 3.8 with Link Time Optimization enabled
+# GCC RISC-V This configuration is used to compile under Linux to produce
+# PE/COFF binaries using GCC RISC-V tool chain
#
####################################################################################
-*_CLANG38_*_*_FAMILY = GCC
-*_CLANG38_*_MAKE_PATH = make
-*_CLANG38_*_*_DLL = ENV(CLANG38_DLL)
-*_CLANG38_*_ASL_PATH = DEF(UNIX_IASL_BIN)
-
-*_CLANG38_*_APP_FLAGS =
-*_CLANG38_*_ASL_FLAGS = DEF(IASL_FLAGS)
-*_CLANG38_*_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS)
-*_CLANG38_*_DEPS_FLAGS = DEF(GCC_DEPS_FLAGS)
-DEFINE CLANG38_IA32_PREFIX = ENV(CLANG38_BIN)
-DEFINE CLANG38_X64_PREFIX = ENV(CLANG38_BIN)
-
-DEFINE CLANG38_IA32_TARGET = -target i686-pc-linux-gnu
-DEFINE CLANG38_X64_TARGET = -target x86_64-pc-linux-gnu
-
-DEFINE CLANG38_WARNING_OVERRIDES = -Wno-parentheses-equality -Wno-tautological-compare -Wno-tautological-constant-out-of-range-compare -Wno-empty-body -Wno-unused-const-variable -Wno-varargs -Wno-unknown-warning-option -Wno-unused-but-set-variable -Wno-unused-const-variable
-DEFINE CLANG38_ALL_CC_FLAGS = DEF(GCC48_ALL_CC_FLAGS) DEF(CLANG38_WARNING_OVERRIDES) -fno-stack-protector -mms-bitfields -Wno-address -Wno-shift-negative-value -Wno-unknown-pragmas -Wno-incompatible-library-redeclaration -fno-asynchronous-unwind-tables -mno-sse -mno-mmx -msoft-float -mno-implicit-float -ftrap-function=undefined_behavior_has_been_optimized_away_by_clang -funsigned-char -fno-ms-extensions -Wno-null-dereference
-
-###########################
-# CLANG38 IA32 definitions
-###########################
-*_CLANG38_IA32_OBJCOPY_PATH = objcopy
-*_CLANG38_IA32_CC_PATH = DEF(CLANG38_IA32_PREFIX)clang
-*_CLANG38_IA32_SLINK_PATH = DEF(CLANG38_IA32_PREFIX)llvm-ar
-*_CLANG38_IA32_DLINK_PATH = DEF(CLANG38_IA32_PREFIX)clang
-*_CLANG38_IA32_ASLDLINK_PATH = DEF(CLANG38_IA32_PREFIX)clang
-*_CLANG38_IA32_ASM_PATH = DEF(CLANG38_IA32_PREFIX)clang
-*_CLANG38_IA32_PP_PATH = DEF(CLANG38_IA32_PREFIX)clang
-*_CLANG38_IA32_VFRPP_PATH = DEF(CLANG38_IA32_PREFIX)clang
-*_CLANG38_IA32_ASLCC_PATH = DEF(CLANG38_IA32_PREFIX)clang
-*_CLANG38_IA32_ASLPP_PATH = DEF(CLANG38_IA32_PREFIX)clang
-*_CLANG38_IA32_RC_PATH = objcopy
-
-*_CLANG38_IA32_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -m32 -fno-lto DEF(CLANG38_IA32_TARGET)
-*_CLANG38_IA32_ASLDLINK_FLAGS = DEF(GCC5_IA32_X64_ASLDLINK_FLAGS) -Wl,-m,elf_i386
-*_CLANG38_IA32_ASM_FLAGS = DEF(GCC5_ASM_FLAGS) -m32 -march=i386 DEF(CLANG38_IA32_TARGET)
-*_CLANG38_IA32_RC_FLAGS = DEF(GCC_IA32_RC_FLAGS)
-*_CLANG38_IA32_OBJCOPY_FLAGS =
-*_CLANG38_IA32_NASM_FLAGS = -f elf32
-*_CLANG38_IA32_PP_FLAGS = DEF(GCC_PP_FLAGS) DEF(CLANG38_IA32_TARGET)
-*_CLANG38_IA32_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) DEF(CLANG38_IA32_TARGET)
-*_CLANG38_IA32_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) DEF(CLANG38_IA32_TARGET)
-
-DEBUG_CLANG38_IA32_CC_FLAGS = DEF(CLANG38_ALL_CC_FLAGS) -m32 -Oz -flto -march=i586 DEF(CLANG38_IA32_TARGET) -g
-DEBUG_CLANG38_IA32_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -flto -Wl,-Oz -Wl,-melf_i386 -Wl,--oformat=elf32-i386
-DEBUG_CLANG38_IA32_DLINK2_FLAGS = DEF(GCC5_IA32_DLINK2_FLAGS) -O3
-
-RELEASE_CLANG38_IA32_CC_FLAGS = DEF(CLANG38_ALL_CC_FLAGS) -m32 -Oz -flto -march=i586 DEF(CLANG38_IA32_TARGET)
-RELEASE_CLANG38_IA32_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -flto -Wl,-Oz -Wl,-melf_i386 -Wl,--oformat=elf32-i386
-RELEASE_CLANG38_IA32_DLINK2_FLAGS = DEF(GCC5_IA32_DLINK2_FLAGS) -O3
-
-NOOPT_CLANG38_IA32_CC_FLAGS = DEF(CLANG38_ALL_CC_FLAGS) -m32 -O0 -march=i586 DEF(CLANG38_IA32_TARGET) -g
-NOOPT_CLANG38_IA32_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -Wl,-O0 -Wl,-melf_i386 -Wl,--oformat=elf32-i386
-NOOPT_CLANG38_IA32_DLINK2_FLAGS = DEF(GCC5_IA32_DLINK2_FLAGS) -O0
-
-##########################
-# CLANG38 X64 definitions
-##########################
-*_CLANG38_X64_OBJCOPY_PATH = objcopy
-*_CLANG38_X64_CC_PATH = DEF(CLANG38_X64_PREFIX)clang
-*_CLANG38_X64_SLINK_PATH = DEF(CLANG38_X64_PREFIX)llvm-ar
-*_CLANG38_X64_DLINK_PATH = DEF(CLANG38_X64_PREFIX)clang
-*_CLANG38_X64_ASLDLINK_PATH = DEF(CLANG38_X64_PREFIX)clang
-*_CLANG38_X64_ASM_PATH = DEF(CLANG38_X64_PREFIX)clang
-*_CLANG38_X64_PP_PATH = DEF(CLANG38_X64_PREFIX)clang
-*_CLANG38_X64_VFRPP_PATH = DEF(CLANG38_X64_PREFIX)clang
-*_CLANG38_X64_ASLCC_PATH = DEF(CLANG38_X64_PREFIX)clang
-*_CLANG38_X64_ASLPP_PATH = DEF(CLANG38_X64_PREFIX)clang
-*_CLANG38_X64_RC_PATH = objcopy
-
-*_CLANG38_X64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -m64 -fno-lto DEF(CLANG38_X64_TARGET)
-*_CLANG38_X64_ASLDLINK_FLAGS = DEF(GCC5_IA32_X64_ASLDLINK_FLAGS) -Wl,-m,elf_x86_64
-*_CLANG38_X64_ASM_FLAGS = DEF(GCC5_ASM_FLAGS) -m64 DEF(CLANG38_X64_TARGET)
-*_CLANG38_X64_RC_FLAGS = DEF(GCC_X64_RC_FLAGS)
-*_CLANG38_X64_OBJCOPY_FLAGS =
-*_CLANG38_X64_NASM_FLAGS = -f elf64
-*_CLANG38_X64_PP_FLAGS = DEF(GCC_PP_FLAGS) DEF(CLANG38_X64_TARGET)
-*_CLANG38_X64_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) DEF(CLANG38_X64_TARGET)
-*_CLANG38_X64_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) DEF(CLANG38_X64_TARGET)
-
-DEBUG_CLANG38_X64_CC_FLAGS = DEF(CLANG38_ALL_CC_FLAGS) -m64 "-DEFIAPI=__attribute__((ms_abi))" -mno-red-zone -mcmodel=small -fpie -Oz -flto DEF(CLANG38_X64_TARGET) -g
-DEBUG_CLANG38_X64_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -flto -Wl,-Oz -Wl,-melf_x86_64 -Wl,--oformat=elf64-x86-64 -Wl,-pie -mcmodel=small
-DEBUG_CLANG38_X64_DLINK2_FLAGS = DEF(GCC5_X64_DLINK2_FLAGS) -O3
-
-RELEASE_CLANG38_X64_CC_FLAGS = DEF(CLANG38_ALL_CC_FLAGS) -m64 "-DEFIAPI=__attribute__((ms_abi))" -mno-red-zone -mcmodel=small -fpie -Oz -flto DEF(CLANG38_X64_TARGET)
-RELEASE_CLANG38_X64_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -flto -Wl,-Oz -Wl,-melf_x86_64 -Wl,--oformat=elf64-x86-64 -Wl,-pie -mcmodel=small
-RELEASE_CLANG38_X64_DLINK2_FLAGS = DEF(GCC5_X64_DLINK2_FLAGS) -O3
-
-NOOPT_CLANG38_X64_CC_FLAGS = DEF(CLANG38_ALL_CC_FLAGS) -m64 "-DEFIAPI=__attribute__((ms_abi))" -mno-red-zone -mcmodel=small -fpie -O0 DEF(CLANG38_X64_TARGET) -g
-NOOPT_CLANG38_X64_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -Wl,-O0 -Wl,-melf_x86_64 -Wl,--oformat=elf64-x86-64 -Wl,-pie -mcmodel=small
-NOOPT_CLANG38_X64_DLINK2_FLAGS = DEF(GCC5_X64_DLINK2_FLAGS) -O0
##################
-# CLANG38 ARM definitions
+# GCC RISCV64 definitions
##################
-DEFINE CLANG38_ARM_TARGET = -target arm-linux-gnueabi
-DEFINE CLANG38_ARM_CC_FLAGS = DEF(GCC_ARM_CC_FLAGS) DEF(CLANG38_ARM_TARGET) DEF(CLANG38_WARNING_OVERRIDES) -mno-movt
-DEFINE CLANG38_ARM_DLINK_FLAGS = DEF(CLANG38_ARM_TARGET) DEF(GCC_ARM_DLINK_FLAGS)
+*_GCC_RISCV64_OBJCOPY_PATH = ENV(GCC_RISCV64_PREFIX)objcopy
+*_GCC_RISCV64_CC_PATH = ENV(GCC_RISCV64_PREFIX)gcc
+*_GCC_RISCV64_SLINK_PATH = ENV(GCC_RISCV64_PREFIX)gcc-ar
+*_GCC_RISCV64_DLINK_PATH = ENV(GCC_RISCV64_PREFIX)gcc
+*_GCC_RISCV64_ASLDLINK_PATH = ENV(GCC_RISCV64_PREFIX)gcc
+*_GCC_RISCV64_ASM_PATH = ENV(GCC_RISCV64_PREFIX)gcc
+*_GCC_RISCV64_PP_PATH = ENV(GCC_RISCV64_PREFIX)gcc
+*_GCC_RISCV64_VFRPP_PATH = ENV(GCC_RISCV64_PREFIX)gcc
+*_GCC_RISCV64_ASLCC_PATH = ENV(GCC_RISCV64_PREFIX)gcc
+*_GCC_RISCV64_ASLPP_PATH = ENV(GCC_RISCV64_PREFIX)gcc
+*_GCC_RISCV64_RC_PATH = ENV(GCC_RISCV64_PREFIX)objcopy
-*_CLANG38_ARM_PP_FLAGS = DEF(GCC_PP_FLAGS)
-*_CLANG38_ARM_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
-*_CLANG38_ARM_APP_FLAGS =
-*_CLANG38_ARM_ASL_FLAGS = DEF(IASL_FLAGS)
-*_CLANG38_ARM_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS)
-*_CLANG38_ARM_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)
-
-*_CLANG38_ARM_CC_PATH = ENV(CLANG38_BIN)clang
-*_CLANG38_ARM_ASM_PATH = ENV(CLANG38_BIN)clang
-*_CLANG38_ARM_PP_PATH = ENV(CLANG38_BIN)clang
-*_CLANG38_ARM_VFRPP_PATH = ENV(CLANG38_BIN)clang
-*_CLANG38_ARM_ASLCC_PATH = ENV(CLANG38_BIN)clang
-*_CLANG38_ARM_ASLPP_PATH = ENV(CLANG38_BIN)clang
-*_CLANG38_ARM_DLINK_PATH = ENV(CLANG38_BIN)clang
-*_CLANG38_ARM_ASLDLINK_PATH = ENV(CLANG38_BIN)clang
-
-*_CLANG38_ARM_SLINK_PATH = ENV(CLANG38_BIN)llvm-ar
-*_CLANG38_ARM_RC_PATH = ENV(CLANG38_ARM_PREFIX)objcopy
-
-*_CLANG38_ARM_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -fno-lto
-*_CLANG38_ARM_ASLDLINK_FLAGS = DEF(CLANG38_ARM_TARGET) DEF(GCC_ARM_ASLDLINK_FLAGS)
-*_CLANG38_ARM_ASM_FLAGS = DEF(GCC_ASM_FLAGS) DEF(CLANG38_ARM_TARGET) $(ARCHASM_FLAGS) $(PLATFORM_FLAGS) -Qunused-arguments
-*_CLANG38_ARM_DLINK2_FLAGS = DEF(GCC_DLINK2_FLAGS_COMMON) -Wl,--defsym=PECOFF_HEADER_SIZE=0x220
-*_CLANG38_ARM_PLATFORM_FLAGS = -march=armv7-a
-*_CLANG38_ARM_PP_FLAGS = DEF(GCC_PP_FLAGS) DEF(CLANG38_ARM_TARGET) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS)
-*_CLANG38_ARM_RC_FLAGS = DEF(GCC_ARM_RC_FLAGS)
-*_CLANG38_ARM_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) DEF(CLANG38_ARM_TARGET) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS)
-*_CLANG38_ARM_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) DEF(CLANG38_ARM_TARGET)
-*_CLANG38_ARM_CC_XIPFLAGS = DEF(GCC_ARM_CC_XIPFLAGS)
-
- DEBUG_CLANG38_ARM_CC_FLAGS = DEF(CLANG38_ARM_CC_FLAGS) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -flto -O1
- DEBUG_CLANG38_ARM_DLINK_FLAGS = DEF(CLANG38_ARM_DLINK_FLAGS) -flto -Wl,-O1 -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-arm -Wl,-plugin-opt=-pass-through=-llto-arm
- NOOPT_CLANG38_ARM_CC_FLAGS = DEF(CLANG38_ARM_CC_FLAGS) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -O0
- NOOPT_CLANG38_ARM_DLINK_FLAGS = DEF(CLANG38_ARM_DLINK_FLAGS)
-RELEASE_CLANG38_ARM_CC_FLAGS = DEF(CLANG38_ARM_CC_FLAGS) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -flto -O3
-RELEASE_CLANG38_ARM_DLINK_FLAGS = DEF(CLANG38_ARM_DLINK_FLAGS) -flto -Wl,-O3 -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-arm -Wl,-plugin-opt=-pass-through=-llto-arm
+*_GCC_RISCV64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
+*_GCC_RISCV64_ASLDLINK_FLAGS = DEF(GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS)
+*_GCC_RISCV64_ASM_FLAGS = DEF(GCC5_RISCV64_ASM_FLAGS)
+*_GCC_RISCV64_CC_FLAGS = DEF(GCC5_RISCV64_CC_FLAGS) -save-temps
+*_GCC_RISCV64_DLINK_FLAGS = DEF(GCC5_RISCV64_DLINK_FLAGS)
+*_GCC_RISCV64_DLINK2_FLAGS = DEF(GCC5_RISCV64_DLINK2_FLAGS)
+*_GCC_RISCV64_RC_FLAGS = DEF(GCC_RISCV64_RC_FLAGS)
+*_GCC_RISCV64_OBJCOPY_FLAGS =
+*_GCC_RISCV64_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)
+*_GCC_RISCV64_PP_FLAGS = DEF(GCC_PP_FLAGS) DEF(GCC5_RISCV_OPENSBI_TYPES)
##################
-# CLANG38 AARCH64 definitions
+# GCC LOONGARCH64 definitions
##################
-DEFINE CLANG38_AARCH64_TARGET = -target aarch64-linux-gnu
-DEFINE CLANG38_AARCH64_CC_FLAGS = DEF(GCC_AARCH64_CC_FLAGS) DEF(CLANG38_AARCH64_TARGET) -mcmodel=small DEF(CLANG38_WARNING_OVERRIDES)
-DEFINE CLANG38_AARCH64_DLINK_FLAGS = DEF(CLANG38_AARCH64_TARGET) DEF(GCC_AARCH64_DLINK_FLAGS) -z common-page-size=0x1000
+*_GCC_LOONGARCH64_OBJCOPY_PATH = ENV(GCC_LOONGARCH64_PREFIX)objcopy
+*_GCC_LOONGARCH64_CC_PATH = ENV(GCC_LOONGARCH64_PREFIX)gcc
+*_GCC_LOONGARCH64_SLINK_PATH = ENV(GCC_LOONGARCH64_PREFIX)gcc-ar
+*_GCC_LOONGARCH64_DLINK_PATH = ENV(GCC_LOONGARCH64_PREFIX)gcc
+*_GCC_LOONGARCH64_ASLDLINK_PATH = ENV(GCC_LOONGARCH64_PREFIX)gcc
+*_GCC_LOONGARCH64_ASM_PATH = ENV(GCC_LOONGARCH64_PREFIX)gcc
+*_GCC_LOONGARCH64_PP_PATH = ENV(GCC_LOONGARCH64_PREFIX)gcc
+*_GCC_LOONGARCH64_VFRPP_PATH = ENV(GCC_LOONGARCH64_PREFIX)gcc
+*_GCC_LOONGARCH64_ASLCC_PATH = ENV(GCC_LOONGARCH64_PREFIX)gcc
+*_GCC_LOONGARCH64_ASLPP_PATH = ENV(GCC_LOONGARCH64_PREFIX)gcc
+*_GCC_LOONGARCH64_RC_PATH = ENV(GCC_LOONGARCH64_PREFIX)objcopy
-*_CLANG38_AARCH64_PP_FLAGS = DEF(GCC_PP_FLAGS)
-*_CLANG38_AARCH64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
-*_CLANG38_AARCH64_APP_FLAGS =
-*_CLANG38_AARCH64_ASL_FLAGS = DEF(IASL_FLAGS)
-*_CLANG38_AARCH64_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS)
-*_CLANG38_AARCH64_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)
+*_GCC_LOONGARCH64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
+*_GCC_LOONGARCH64_ASLDLINK_FLAGS = DEF(GCC5_LOONGARCH64_ASLDLINK_FLAGS)
+*_GCC_LOONGARCH64_ASM_FLAGS = DEF(GCC5_LOONGARCH64_ASM_FLAGS)
+*_GCC_LOONGARCH64_DLINK_FLAGS = DEF(GCC5_LOONGARCH64_DLINK_FLAGS)
+*_GCC_LOONGARCH64_DLINK2_FLAGS = DEF(GCC5_LOONGARCH64_DLINK2_FLAGS)
+*_GCC_LOONGARCH64_RC_FLAGS = DEF(GCC_LOONGARCH64_RC_FLAGS)
+*_GCC_LOONGARCH64_OBJCOPY_FLAGS =
+*_GCC_LOONGARCH64_NASM_FLAGS = -f elf32
+*_GCC_LOONGARCH64_PP_FLAGS = DEF(GCC5_LOONGARCH64_PP_FLAGS)
-*_CLANG38_AARCH64_CC_PATH = ENV(CLANG38_BIN)clang
-*_CLANG38_AARCH64_ASM_PATH = ENV(CLANG38_BIN)clang
-*_CLANG38_AARCH64_PP_PATH = ENV(CLANG38_BIN)clang
-*_CLANG38_AARCH64_VFRPP_PATH = ENV(CLANG38_BIN)clang
-*_CLANG38_AARCH64_ASLCC_PATH = ENV(CLANG38_BIN)clang
-*_CLANG38_AARCH64_ASLPP_PATH = ENV(CLANG38_BIN)clang
-*_CLANG38_AARCH64_DLINK_PATH = ENV(CLANG38_BIN)clang
-*_CLANG38_AARCH64_ASLDLINK_PATH = ENV(CLANG38_BIN)clang
-
-*_CLANG38_AARCH64_SLINK_PATH = ENV(CLANG38_BIN)llvm-ar
-*_CLANG38_AARCH64_RC_PATH = ENV(CLANG38_AARCH64_PREFIX)objcopy
-
-*_CLANG38_AARCH64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -fno-lto
-*_CLANG38_AARCH64_ASLDLINK_FLAGS = DEF(CLANG38_AARCH64_TARGET) DEF(GCC_AARCH64_ASLDLINK_FLAGS)
-*_CLANG38_AARCH64_ASM_FLAGS = DEF(GCC_ASM_FLAGS) DEF(CLANG38_AARCH64_TARGET) $(ARCHASM_FLAGS) $(PLATFORM_FLAGS) -Qunused-arguments
-*_CLANG38_AARCH64_DLINK_FLAGS = DEF(CLANG38_AARCH64_TARGET) DEF(GCC_AARCH64_DLINK_FLAGS) -z common-page-size=0x1000
-*_CLANG38_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20
-*_CLANG38_AARCH64_DLINK2_FLAGS = DEF(GCC_DLINK2_FLAGS_COMMON) -Wl,--defsym=PECOFF_HEADER_SIZE=0x228
-*_CLANG38_AARCH64_PLATFORM_FLAGS =
-*_CLANG38_AARCH64_PP_FLAGS = DEF(GCC_PP_FLAGS) DEF(CLANG38_AARCH64_TARGET) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS)
-*_CLANG38_AARCH64_RC_FLAGS = DEF(GCC_AARCH64_RC_FLAGS)
-*_CLANG38_AARCH64_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) DEF(CLANG38_AARCH64_TARGET) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS)
-*_CLANG38_AARCH64_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) DEF(CLANG38_AARCH64_TARGET)
-*_CLANG38_AARCH64_CC_XIPFLAGS = DEF(GCC_AARCH64_CC_XIPFLAGS)
-
- DEBUG_CLANG38_AARCH64_CC_FLAGS = DEF(CLANG38_AARCH64_CC_FLAGS) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -flto -O1
- DEBUG_CLANG38_AARCH64_DLINK_FLAGS = DEF(CLANG38_AARCH64_DLINK_FLAGS) -flto -Wl,-O1 -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-aarch64 -Wl,-plugin-opt=-pass-through=-llto-aarch64
- NOOPT_CLANG38_AARCH64_CC_FLAGS = DEF(CLANG38_AARCH64_CC_FLAGS) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -O0
- NOOPT_CLANG38_AARCH64_DLINK_FLAGS = DEF(CLANG38_AARCH64_DLINK_FLAGS)
-RELEASE_CLANG38_AARCH64_CC_FLAGS = DEF(CLANG38_AARCH64_CC_FLAGS) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -flto -O3
-RELEASE_CLANG38_AARCH64_DLINK_FLAGS = DEF(CLANG38_AARCH64_DLINK_FLAGS) -flto -Wl,-O3 -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-aarch64 -Wl,-plugin-opt=-pass-through=-llto-aarch64
+DEBUG_GCC_LOONGARCH64_CC_FLAGS = DEF(GCC5_LOONGARCH64_CC_FLAGS)
+RELEASE_GCC_LOONGARCH64_CC_FLAGS = DEF(GCC5_LOONGARCH64_CC_FLAGS) -Wno-unused-but-set-variable -Wno-unused-variable
####################################################################################
#
@@ -2781,7 +1754,7 @@ DEFINE CLANGPDB_X64_PREFIX = ENV(CLANG_BIN)
DEFINE CLANGPDB_IA32_TARGET = -target i686-unknown-windows-gnu
DEFINE CLANGPDB_X64_TARGET = -target x86_64-unknown-windows-gnu
-DEFINE CLANGPDB_WARNING_OVERRIDES = -Wno-parentheses-equality -Wno-tautological-compare -Wno-tautological-constant-out-of-range-compare -Wno-empty-body -Wno-unused-const-variable -Wno-varargs -Wno-unknown-warning-option -Wno-microsoft-enum-forward-reference
+DEFINE CLANGPDB_WARNING_OVERRIDES = -Wno-parentheses-equality -Wno-tautological-compare -Wno-tautological-constant-out-of-range-compare -Wno-empty-body -Wno-unused-const-variable -Wno-varargs -Wno-unknown-warning-option -Wno-unused-but-set-variable -Wno-unused-const-variable -Wno-unaligned-access -Wno-microsoft-enum-forward-reference
DEFINE CLANGPDB_ALL_CC_FLAGS = DEF(GCC48_ALL_CC_FLAGS) DEF(CLANGPDB_WARNING_OVERRIDES) -fno-stack-protector -funsigned-char -ftrap-function=undefined_behavior_has_been_optimized_away_by_clang -Wno-address -Wno-shift-negative-value -Wno-unknown-pragmas -Wno-incompatible-library-redeclaration -Wno-null-dereference -mno-implicit-float -mms-bitfields -mno-stack-arg-probe -nostdlib -nostdlibinc -fseh-exceptions
###########################
@@ -2806,15 +1779,15 @@ DEFINE CLANGPDB_ALL_CC_FLAGS = DEF(GCC48_ALL_CC_FLAGS) DEF(CLANGPDB_WARN
*_CLANGPDB_IA32_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) DEF(CLANGPDB_IA32_TARGET)
*_CLANGPDB_IA32_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) DEF(CLANGPDB_IA32_TARGET)
-DEBUG_CLANGPDB_IA32_CC_FLAGS = DEF(CLANGPDB_ALL_CC_FLAGS) -m32 -Oz -flto -march=i586 DEF(CLANGPDB_IA32_TARGET) -gcodeview
+DEBUG_CLANGPDB_IA32_CC_FLAGS = DEF(CLANGPDB_ALL_CC_FLAGS) -m32 -Oz -flto -march=i586 DEF(CLANGPDB_IA32_TARGET) -gcodeview -malign-double
DEBUG_CLANGPDB_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /ALIGN:32 /FILEALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DEBUG:GHASH /MLLVM:-exception-model=wineh /lldmap
DEBUG_CLANGPDB_IA32_DLINK2_FLAGS =
-RELEASE_CLANGPDB_IA32_CC_FLAGS = DEF(CLANGPDB_ALL_CC_FLAGS) -m32 -Oz -flto -march=i586 DEF(CLANGPDB_IA32_TARGET)
+RELEASE_CLANGPDB_IA32_CC_FLAGS = DEF(CLANGPDB_ALL_CC_FLAGS) -m32 -Oz -flto -march=i586 DEF(CLANGPDB_IA32_TARGET) -malign-double
RELEASE_CLANGPDB_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /ALIGN:32 /FILEALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /MERGE:.rdata=.data /MLLVM:-exception-model=wineh /lldmap
RELEASE_CLANGPDB_IA32_DLINK2_FLAGS =
-NOOPT_CLANGPDB_IA32_CC_FLAGS = DEF(CLANGPDB_ALL_CC_FLAGS) -m32 -O0 -march=i586 DEF(CLANGPDB_IA32_TARGET) -gcodeview
+NOOPT_CLANGPDB_IA32_CC_FLAGS = DEF(CLANGPDB_ALL_CC_FLAGS) -m32 -O0 -march=i586 DEF(CLANGPDB_IA32_TARGET) -gcodeview -malign-double
NOOPT_CLANGPDB_IA32_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /ALIGN:32 /FILEALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:X86 /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DEBUG:GHASH /MLLVM:-exception-model=wineh /lldmap
NOOPT_CLANGPDB_IA32_DLINK2_FLAGS =
@@ -2862,7 +1835,7 @@ NOOPT_CLANGPDB_X64_GENFW_FLAGS = --keepexceptiontable
#
####################################################################################
*_CLANGDWARF_*_*_FAMILY = GCC
-*_CLANGDWARF_*_*_BUILDRULEFAMILY = CLANGGCC
+
*_CLANGDWARF_*_MAKE_PATH = ENV(CLANG_HOST_BIN)make
*_CLANGDWARF_*_*_DLL = ENV(CLANGDWARF_DLL)
*_CLANGDWARF_*_ASL_PATH = DEF(UNIX_IASL_BIN)
@@ -2879,10 +1852,16 @@ DEFINE CLANGDWARF_X64_PREFIX = ENV(CLANG_BIN)
DEFINE CLANGDWARF_IA32_X64_DLINK_COMMON = -nostdlib -Wl,-q,--gc-sections -z max-page-size=0x40
DEFINE CLANGDWARF_DLINK2_FLAGS_COMMON = -Wl,--script=$(EDK_TOOLS_PATH)/Scripts/ClangBase.lds
DEFINE CLANGDWARF_IA32_X64_ASLDLINK_FLAGS = DEF(CLANGDWARF_IA32_X64_DLINK_COMMON) -Wl,--defsym=PECOFF_HEADER_SIZE=0 DEF(CLANGDWARF_DLINK2_FLAGS_COMMON) -Wl,--entry,ReferenceAcpiTable -u ReferenceAcpiTable
-DEFINE CLANGDWARF_IA32_X64_DLINK_FLAGS = DEF(CLANGDWARF_IA32_X64_DLINK_COMMON) -Wl,--entry,$(IMAGE_ENTRY_POINT) -u $(IMAGE_ENTRY_POINT) -Wl,-Map,$(DEST_DIR_DEBUG)/$(BASE_NAME).map,--whole-archive
+DEFINE CLANGDWARF_IA32_X64_DLINK_FLAGS = DEF(CLANGDWARF_IA32_X64_DLINK_COMMON) -Wl,--entry,$(IMAGE_ENTRY_POINT) -u $(IMAGE_ENTRY_POINT) -Wl,-Map,$(DEST_DIR_DEBUG)/$(BASE_NAME).map,--whole-archive -Wl,-z,notext
DEFINE CLANGDWARF_IA32_DLINK2_FLAGS = -Wl,--defsym=PECOFF_HEADER_SIZE=0x220 DEF(CLANGDWARF_DLINK2_FLAGS_COMMON)
DEFINE CLANGDWARF_X64_DLINK2_FLAGS = -Wl,--defsym=PECOFF_HEADER_SIZE=0x228 DEF(CLANGDWARF_DLINK2_FLAGS_COMMON)
+DEFINE CLANGDWARF_IA32_TARGET = -target i686-pc-linux-gnu
+DEFINE CLANGDWARF_X64_TARGET = -target x86_64-pc-linux-gnu
+
+DEFINE CLANGDWARF_WARNING_OVERRIDES = -Wno-parentheses-equality -Wno-empty-body -Wno-unused-const-variable -Wno-varargs -Wno-unknown-warning-option -Wno-unused-but-set-variable -Wno-unused-const-variable -Wno-unaligned-access -Wno-unneeded-internal-declaration
+DEFINE CLANGDWARF_ALL_CC_FLAGS = DEF(GCC48_ALL_CC_FLAGS) DEF(CLANGDWARF_WARNING_OVERRIDES) -fno-stack-protector -mms-bitfields -Wno-address -Wno-shift-negative-value -Wno-unknown-pragmas -Wno-incompatible-library-redeclaration -fno-asynchronous-unwind-tables -mno-sse -mno-mmx -msoft-float -mno-implicit-float -ftrap-function=undefined_behavior_has_been_optimized_away_by_clang -funsigned-char -fno-ms-extensions -Wno-null-dereference
+
###########################
# CLANGDWARF IA32 definitions
###########################
@@ -2895,29 +1874,29 @@ DEFINE CLANGDWARF_X64_DLINK2_FLAGS = -Wl,--defsym=PECOFF_HEADER_SIZE=0x22
*_CLANGDWARF_IA32_VFRPP_PATH = DEF(CLANGDWARF_IA32_PREFIX)clang
*_CLANGDWARF_IA32_ASLCC_PATH = DEF(CLANGDWARF_IA32_PREFIX)clang
*_CLANGDWARF_IA32_ASLPP_PATH = DEF(CLANGDWARF_IA32_PREFIX)clang
-*_CLANGDWARF_IA32_RC_PATH = DEF(CLANGDWARF_IA32_PREFIX)llvm-rc
+*_CLANGDWARF_IA32_RC_PATH = DEF(CLANGDWARF_IA32_PREFIX)llvm-objcopy
-*_CLANGDWARF_IA32_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -m32 -fno-lto DEF(CLANG38_IA32_TARGET)
-*_CLANGDWARF_IA32_ASLDLINK_FLAGS = DEF(CLANGDWARF_IA32_X64_ASLDLINK_FLAGS) -Wl,-m,elf_i386 -fuse-ld=lld
-*_CLANGDWARF_IA32_ASM_FLAGS = DEF(GCC5_ASM_FLAGS) -m32 -march=i386 DEF(CLANG38_IA32_TARGET)
+*_CLANGDWARF_IA32_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -m32 -fno-lto DEF(CLANGDWARF_IA32_TARGET)
+*_CLANGDWARF_IA32_ASLDLINK_FLAGS = DEF(CLANGDWARF_IA32_X64_ASLDLINK_FLAGS) -Wl,-m,elf_i386 -fuse-ld=lld -no-pie
+*_CLANGDWARF_IA32_ASM_FLAGS = DEF(GCC5_ASM_FLAGS) -m32 -march=i386 DEF(CLANGDWARF_IA32_TARGET)
*_CLANGDWARF_IA32_RC_FLAGS = DEF(GCC_IA32_RC_FLAGS)
*_CLANGDWARF_IA32_OBJCOPY_FLAGS =
*_CLANGDWARF_IA32_NASM_FLAGS = -f elf32
-*_CLANGDWARF_IA32_PP_FLAGS = DEF(GCC_PP_FLAGS) DEF(CLANG38_IA32_TARGET)
-*_CLANGDWARF_IA32_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) DEF(CLANG38_IA32_TARGET)
-*_CLANGDWARF_IA32_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) DEF(CLANG38_IA32_TARGET)
+*_CLANGDWARF_IA32_PP_FLAGS = DEF(GCC_PP_FLAGS) DEF(CLANGDWARF_IA32_TARGET)
+*_CLANGDWARF_IA32_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) DEF(CLANGDWARF_IA32_TARGET)
+*_CLANGDWARF_IA32_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) DEF(CLANGDWARF_IA32_TARGET)
-DEBUG_CLANGDWARF_IA32_CC_FLAGS = DEF(CLANG38_ALL_CC_FLAGS) -m32 -Oz -flto -march=i586 DEF(CLANG38_IA32_TARGET) -g
+DEBUG_CLANGDWARF_IA32_CC_FLAGS = DEF(CLANGDWARF_ALL_CC_FLAGS) -fno-pic -fno-pie -m32 -Oz -flto -march=i586 DEF(CLANGDWARF_IA32_TARGET) -g -malign-double
DEBUG_CLANGDWARF_IA32_DLINK_FLAGS = DEF(CLANGDWARF_IA32_X64_DLINK_FLAGS) -flto -Wl,-O3 -Wl,-melf_i386 -Wl,--oformat,elf32-i386
-DEBUG_CLANGDWARF_IA32_DLINK2_FLAGS = DEF(CLANGDWARF_IA32_DLINK2_FLAGS) -O3 -fuse-ld=lld
+DEBUG_CLANGDWARF_IA32_DLINK2_FLAGS = DEF(CLANGDWARF_IA32_DLINK2_FLAGS) -O3 -fuse-ld=lld -no-pie
-RELEASE_CLANGDWARF_IA32_CC_FLAGS = DEF(CLANG38_ALL_CC_FLAGS) -m32 -Oz -flto -march=i586 DEF(CLANG38_IA32_TARGET)
+RELEASE_CLANGDWARF_IA32_CC_FLAGS = DEF(CLANGDWARF_ALL_CC_FLAGS) -fno-pic -fno-pie -m32 -Oz -flto -march=i586 DEF(CLANGDWARF_IA32_TARGET) -malign-double
RELEASE_CLANGDWARF_IA32_DLINK_FLAGS = DEF(CLANGDWARF_IA32_X64_DLINK_FLAGS) -flto -Wl,-O3 -Wl,-melf_i386 -Wl,--oformat,elf32-i386
-RELEASE_CLANGDWARF_IA32_DLINK2_FLAGS = DEF(CLANGDWARF_IA32_DLINK2_FLAGS) -O3 -fuse-ld=lld
+RELEASE_CLANGDWARF_IA32_DLINK2_FLAGS = DEF(CLANGDWARF_IA32_DLINK2_FLAGS) -O3 -fuse-ld=lld -no-pie
-NOOPT_CLANGDWARF_IA32_CC_FLAGS = DEF(CLANG38_ALL_CC_FLAGS) -m32 -O0 -march=i586 DEF(CLANG38_IA32_TARGET) -g
+NOOPT_CLANGDWARF_IA32_CC_FLAGS = DEF(CLANGDWARF_ALL_CC_FLAGS) -fno-pic -fno-pie -m32 -O0 -march=i586 DEF(CLANGDWARF_IA32_TARGET) -g -malign-double
NOOPT_CLANGDWARF_IA32_DLINK_FLAGS = DEF(CLANGDWARF_IA32_X64_DLINK_FLAGS) -Wl,-O0 -Wl,-melf_i386 -Wl,--oformat,elf32-i386
-NOOPT_CLANGDWARF_IA32_DLINK2_FLAGS = DEF(CLANGDWARF_IA32_DLINK2_FLAGS) -O0 -fuse-ld=lld
+NOOPT_CLANGDWARF_IA32_DLINK2_FLAGS = DEF(CLANGDWARF_IA32_DLINK2_FLAGS) -O0 -fuse-ld=lld -no-pie
##########################
# CLANGDWARF X64 definitions
@@ -2931,30 +1910,172 @@ NOOPT_CLANGDWARF_IA32_DLINK2_FLAGS = DEF(CLANGDWARF_IA32_DLINK2_FLAGS) -O0 -
*_CLANGDWARF_X64_VFRPP_PATH = DEF(CLANGDWARF_X64_PREFIX)clang
*_CLANGDWARF_X64_ASLCC_PATH = DEF(CLANGDWARF_X64_PREFIX)clang
*_CLANGDWARF_X64_ASLPP_PATH = DEF(CLANGDWARF_X64_PREFIX)clang
-*_CLANGDWARF_X64_RC_PATH = DEF(CLANGDWARF_X64_PREFIX)llvm-rc
+*_CLANGDWARF_X64_RC_PATH = DEF(CLANGDWARF_X64_PREFIX)llvm-objcopy
-*_CLANGDWARF_X64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -m64 -fno-lto DEF(CLANG38_X64_TARGET)
+*_CLANGDWARF_X64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -m64 -fno-lto DEF(CLANGDWARF_X64_TARGET)
*_CLANGDWARF_X64_ASLDLINK_FLAGS = DEF(CLANGDWARF_IA32_X64_ASLDLINK_FLAGS) -Wl,-m,elf_x86_64 -fuse-ld=lld
-*_CLANGDWARF_X64_ASM_FLAGS = DEF(GCC5_ASM_FLAGS) -m64 DEF(CLANG38_X64_TARGET)
+*_CLANGDWARF_X64_ASM_FLAGS = DEF(GCC5_ASM_FLAGS) -m64 DEF(CLANGDWARF_X64_TARGET)
*_CLANGDWARF_X64_RC_FLAGS = DEF(GCC_X64_RC_FLAGS)
*_CLANGDWARF_X64_OBJCOPY_FLAGS =
*_CLANGDWARF_X64_NASM_FLAGS = -f elf64
-*_CLANGDWARF_X64_PP_FLAGS = DEF(GCC_PP_FLAGS) DEF(CLANG38_X64_TARGET)
-*_CLANGDWARF_X64_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) DEF(CLANG38_X64_TARGET)
-*_CLANGDWARF_X64_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) DEF(CLANG38_X64_TARGET)
+*_CLANGDWARF_X64_PP_FLAGS = DEF(GCC_PP_FLAGS) DEF(CLANGDWARF_X64_TARGET)
+*_CLANGDWARF_X64_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) DEF(CLANGDWARF_X64_TARGET)
+*_CLANGDWARF_X64_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) DEF(CLANGDWARF_X64_TARGET)
-DEBUG_CLANGDWARF_X64_CC_FLAGS = DEF(CLANG38_ALL_CC_FLAGS) -m64 "-DEFIAPI=__attribute__((ms_abi))" -mno-red-zone -mcmodel=small -fpie -Oz -flto DEF(CLANG38_X64_TARGET) -g
+DEBUG_CLANGDWARF_X64_CC_FLAGS = DEF(CLANGDWARF_ALL_CC_FLAGS) -m64 "-DEFIAPI=__attribute__((ms_abi))" -mno-red-zone -mcmodel=small -fpie -fdirect-access-external-data -Oz -flto DEF(CLANGDWARF_X64_TARGET) -g
DEBUG_CLANGDWARF_X64_DLINK_FLAGS = DEF(CLANGDWARF_IA32_X64_DLINK_FLAGS) -flto -Wl,-O3 -Wl,-melf_x86_64 -Wl,--oformat,elf64-x86-64 -Wl,-pie -mcmodel=small -Wl,--apply-dynamic-relocs
DEBUG_CLANGDWARF_X64_DLINK2_FLAGS = DEF(CLANGDWARF_X64_DLINK2_FLAGS) -O3 -fuse-ld=lld
-RELEASE_CLANGDWARF_X64_CC_FLAGS = DEF(CLANG38_ALL_CC_FLAGS) -m64 "-DEFIAPI=__attribute__((ms_abi))" -mno-red-zone -mcmodel=small -fpie -Oz -flto DEF(CLANG38_X64_TARGET)
+RELEASE_CLANGDWARF_X64_CC_FLAGS = DEF(CLANGDWARF_ALL_CC_FLAGS) -m64 "-DEFIAPI=__attribute__((ms_abi))" -mno-red-zone -mcmodel=small -fpie -fdirect-access-external-data -Oz -flto DEF(CLANGDWARF_X64_TARGET)
RELEASE_CLANGDWARF_X64_DLINK_FLAGS = DEF(CLANGDWARF_IA32_X64_DLINK_FLAGS) -flto -Wl,-O3 -Wl,-melf_x86_64 -Wl,--oformat,elf64-x86-64 -Wl,-pie -mcmodel=small -Wl,--apply-dynamic-relocs
RELEASE_CLANGDWARF_X64_DLINK2_FLAGS = DEF(CLANGDWARF_X64_DLINK2_FLAGS) -O3 -fuse-ld=lld
-NOOPT_CLANGDWARF_X64_CC_FLAGS = DEF(CLANG38_ALL_CC_FLAGS) -m64 "-DEFIAPI=__attribute__((ms_abi))" -mno-red-zone -mcmodel=small -fpie -O0 DEF(CLANG38_X64_TARGET) -g
+NOOPT_CLANGDWARF_X64_CC_FLAGS = DEF(CLANGDWARF_ALL_CC_FLAGS) -m64 "-DEFIAPI=__attribute__((ms_abi))" -mno-red-zone -mcmodel=small -fpie -fdirect-access-external-data -O0 DEF(CLANGDWARF_X64_TARGET) -g
NOOPT_CLANGDWARF_X64_DLINK_FLAGS = DEF(CLANGDWARF_IA32_X64_DLINK_FLAGS) -Wl,-O0 -Wl,-melf_x86_64 -Wl,--oformat,elf64-x86-64 -Wl,-pie -mcmodel=small -Wl,--apply-dynamic-relocs
NOOPT_CLANGDWARF_X64_DLINK2_FLAGS = DEF(CLANGDWARF_X64_DLINK2_FLAGS) -O0 -fuse-ld=lld
+##################
+# CLANGDWARF ARM definitions
+##################
+DEFINE CLANGDWARF_ARM_TARGET = -target arm-linux-gnueabi
+DEFINE CLANGDWARF_ARM_CC_FLAGS = DEF(GCC_ARM_CC_FLAGS) DEF(CLANGDWARF_ARM_TARGET) DEF(CLANGDWARF_WARNING_OVERRIDES) -mno-movt
+DEFINE CLANGDWARF_ARM_DLINK_FLAGS = DEF(CLANGDWARF_ARM_TARGET) DEF(GCC_ARM_DLINK_FLAGS)
+
+*_CLANGDWARF_ARM_PP_FLAGS = DEF(GCC_PP_FLAGS)
+*_CLANGDWARF_ARM_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
+*_CLANGDWARF_ARM_APP_FLAGS =
+*_CLANGDWARF_ARM_ASL_FLAGS = DEF(IASL_FLAGS)
+*_CLANGDWARF_ARM_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS)
+*_CLANGDWARF_ARM_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)
+
+*_CLANGDWARF_ARM_CC_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_ARM_ASM_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_ARM_PP_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_ARM_VFRPP_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_ARM_ASLCC_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_ARM_ASLPP_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_ARM_DLINK_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_ARM_ASLDLINK_PATH = ENV(CLANGDWARF_BIN)clang
+
+*_CLANGDWARF_ARM_SLINK_PATH = ENV(CLANGDWARF_BIN)llvm-ar
+*_CLANGDWARF_ARM_RC_PATH = ENV(CLANGDWARF_BIN)llvm-objcopy
+
+*_CLANGDWARF_ARM_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -fno-lto
+*_CLANGDWARF_ARM_ASLDLINK_FLAGS = DEF(CLANGDWARF_ARM_TARGET) DEF(GCC_ARM_ASLDLINK_FLAGS)
+*_CLANGDWARF_ARM_ASM_FLAGS = DEF(GCC_ASM_FLAGS) DEF(CLANGDWARF_ARM_TARGET) $(PLATFORM_FLAGS) -Qunused-arguments
+*_CLANGDWARF_ARM_DLINK2_FLAGS = DEF(GCC_DLINK2_FLAGS_COMMON) -Wl,--defsym=PECOFF_HEADER_SIZE=0x220
+*_CLANGDWARF_ARM_PLATFORM_FLAGS = -march=armv7-a
+*_CLANGDWARF_ARM_PP_FLAGS = DEF(GCC_PP_FLAGS) DEF(CLANGDWARF_ARM_TARGET) $(PLATFORM_FLAGS)
+*_CLANGDWARF_ARM_RC_FLAGS = DEF(GCC_ARM_RC_FLAGS)
+*_CLANGDWARF_ARM_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) DEF(CLANGDWARF_ARM_TARGET) $(PLATFORM_FLAGS)
+*_CLANGDWARF_ARM_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) DEF(CLANGDWARF_ARM_TARGET)
+*_CLANGDWARF_ARM_CC_XIPFLAGS = DEF(GCC_ARM_CC_XIPFLAGS)
+
+ DEBUG_CLANGDWARF_ARM_CC_FLAGS = DEF(CLANGDWARF_ARM_CC_FLAGS) $(PLATFORM_FLAGS) -flto -O1
+ DEBUG_CLANGDWARF_ARM_DLINK_FLAGS = DEF(CLANGDWARF_ARM_DLINK_FLAGS) -flto -Wl,-O1 -fuse-ld=lld -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-arm -Wl,-plugin-opt=-pass-through=-llto-arm -Wl,--no-pie,--no-relax
+ NOOPT_CLANGDWARF_ARM_CC_FLAGS = DEF(CLANGDWARF_ARM_CC_FLAGS) $(PLATFORM_FLAGS) -O0
+ NOOPT_CLANGDWARF_ARM_DLINK_FLAGS = DEF(CLANGDWARF_ARM_DLINK_FLAGS) -fuse-ld=lld -Wl,--no-pie,--no-relax
+RELEASE_CLANGDWARF_ARM_CC_FLAGS = DEF(CLANGDWARF_ARM_CC_FLAGS) $(PLATFORM_FLAGS) -flto -O3
+RELEASE_CLANGDWARF_ARM_DLINK_FLAGS = DEF(CLANGDWARF_ARM_DLINK_FLAGS) -flto -Wl,-O3 -fuse-ld=lld -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-arm -Wl,-plugin-opt=-pass-through=-llto-arm -Wl,--no-pie,--no-relax
+
+##################
+# CLANGDWARF AARCH64 definitions
+##################
+DEFINE CLANGDWARF_AARCH64_TARGET = -target aarch64-linux-gnu
+DEFINE CLANGDWARF_AARCH64_CC_FLAGS = DEF(GCC_AARCH64_CC_FLAGS) DEF(CLANGDWARF_AARCH64_TARGET) -mcmodel=small DEF(CLANGDWARF_WARNING_OVERRIDES)
+DEFINE CLANGDWARF_AARCH64_DLINK_FLAGS = DEF(CLANGDWARF_AARCH64_TARGET) DEF(GCC_AARCH64_DLINK_FLAGS) -z common-page-size=0x1000
+
+*_CLANGDWARF_AARCH64_PP_FLAGS = DEF(GCC_PP_FLAGS)
+*_CLANGDWARF_AARCH64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
+*_CLANGDWARF_AARCH64_APP_FLAGS =
+*_CLANGDWARF_AARCH64_ASL_FLAGS = DEF(IASL_FLAGS)
+*_CLANGDWARF_AARCH64_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS)
+*_CLANGDWARF_AARCH64_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)
+
+*_CLANGDWARF_AARCH64_CC_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_AARCH64_ASM_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_AARCH64_PP_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_AARCH64_VFRPP_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_AARCH64_ASLCC_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_AARCH64_ASLPP_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_AARCH64_DLINK_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_AARCH64_ASLDLINK_PATH = ENV(CLANGDWARF_BIN)clang
+
+*_CLANGDWARF_AARCH64_SLINK_PATH = ENV(CLANGDWARF_BIN)llvm-ar
+*_CLANGDWARF_AARCH64_RC_PATH = ENV(CLANGDWARF_BIN)llvm-objcopy
+
+*_CLANGDWARF_AARCH64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -fno-lto
+*_CLANGDWARF_AARCH64_ASLDLINK_FLAGS = DEF(CLANGDWARF_AARCH64_TARGET) DEF(GCC_AARCH64_ASLDLINK_FLAGS)
+*_CLANGDWARF_AARCH64_ASM_FLAGS = DEF(GCC_ASM_FLAGS) DEF(CLANGDWARF_AARCH64_TARGET) $(PLATFORM_FLAGS) -Qunused-arguments
+*_CLANGDWARF_AARCH64_DLINK_FLAGS = DEF(CLANGDWARF_AARCH64_TARGET) DEF(GCC_AARCH64_DLINK_FLAGS) -z common-page-size=0x1000
+*_CLANGDWARF_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20
+*_CLANGDWARF_AARCH64_DLINK2_FLAGS = DEF(GCC_DLINK2_FLAGS_COMMON) -Wl,--defsym=PECOFF_HEADER_SIZE=0x228
+*_CLANGDWARF_AARCH64_PLATFORM_FLAGS =
+*_CLANGDWARF_AARCH64_PP_FLAGS = DEF(GCC_PP_FLAGS) DEF(CLANGDWARF_AARCH64_TARGET) $(PLATFORM_FLAGS)
+*_CLANGDWARF_AARCH64_RC_FLAGS = DEF(GCC_AARCH64_RC_FLAGS) DEF(GCC_AARCH64_RC_BTI_FLAGS)
+*_CLANGDWARF_AARCH64_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) DEF(CLANGDWARF_AARCH64_TARGET) $(PLATFORM_FLAGS)
+*_CLANGDWARF_AARCH64_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) DEF(CLANGDWARF_AARCH64_TARGET)
+*_CLANGDWARF_AARCH64_CC_XIPFLAGS = -mstrict-align
+
+ DEBUG_CLANGDWARF_AARCH64_CC_FLAGS = DEF(CLANGDWARF_AARCH64_CC_FLAGS) $(PLATFORM_FLAGS) -flto -O1
+ DEBUG_CLANGDWARF_AARCH64_DLINK_FLAGS = DEF(CLANGDWARF_AARCH64_DLINK_FLAGS) -flto -Wl,-O1 -fuse-ld=lld -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-aarch64 -Wl,-plugin-opt=-pass-through=-llto-aarch64 -Wl,--no-pie,--no-relax
+ NOOPT_CLANGDWARF_AARCH64_CC_FLAGS = DEF(CLANGDWARF_AARCH64_CC_FLAGS) $(PLATFORM_FLAGS) -O0
+ NOOPT_CLANGDWARF_AARCH64_DLINK_FLAGS = DEF(CLANGDWARF_AARCH64_DLINK_FLAGS) -fuse-ld=lld -Wl,--no-pie,--no-relax
+RELEASE_CLANGDWARF_AARCH64_CC_FLAGS = DEF(CLANGDWARF_AARCH64_CC_FLAGS) $(PLATFORM_FLAGS) -flto -O3
+RELEASE_CLANGDWARF_AARCH64_DLINK_FLAGS = DEF(CLANGDWARF_AARCH64_DLINK_FLAGS) -flto -Wl,-O3 -fuse-ld=lld -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-aarch64 -Wl,-plugin-opt=-pass-through=-llto-aarch64 -Wl,--no-pie,--no-relax
+
+##################
+# CLANGDWARF RISCV64 definitions
+##################
+DEFINE CLANGDWARF_RISCV64_TARGET = -target riscv64-linux-gnu
+DEFINE CLANGDWARF_RISCV64_CC_COMMON = DEF(GCC5_RISCV_ALL_CC_FLAGS) DEF(GCC5_RISCV_ALL_CC_FLAGS_WARNING_DISABLE) DEF(GCC5_RISCV_OPENSBI_TYPES) -march=DEF(GCC5_RISCV64_ARCH) -fno-builtin -fno-builtin-memcpy -fno-stack-protector -Wno-address -fno-asynchronous-unwind-tables -fno-unwind-tables -Wno-unused-but-set-variable -fpack-struct=8 -mcmodel=medany -mabi=lp64 -mno-relax
+DEFINE CLANGDWARF_RISCV64_CC_FLAGS = DEF(CLANGDWARF_RISCV64_CC_COMMON) DEF(CLANGDWARF_RISCV64_TARGET) DEF(CLANGDWARF_WARNING_OVERRIDES)
+
+# This is similar to GCC flags but without -n
+DEFINE CLANGDWARF_RISCV64_ALL_DLINK_COMMON = -nostdlib -Wl,-q,--gc-sections -z common-page-size=0x40
+DEFINE CLANGDWARF_RISCV64_ALL_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_ALL_DLINK_COMMON) -Wl,--entry,$(IMAGE_ENTRY_POINT) -u $(IMAGE_ENTRY_POINT) -Wl,-Map,$(DEST_DIR_DEBUG)/$(BASE_NAME).map
+DEFINE CLANGDWARF_RISCV64_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_TARGET) DEF(CLANGDWARF_RISCV64_ALL_DLINK_FLAGS) -Wl,-melf64lriscv,--oformat=elf64-littleriscv,--no-relax
+
+*_CLANGDWARF_RISCV64_PP_FLAGS = DEF(GCC_PP_FLAGS)
+*_CLANGDWARF_RISCV64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
+*_CLANGDWARF_RISCV64_APP_FLAGS =
+*_CLANGDWARF_RISCV64_ASL_FLAGS = DEF(IASL_FLAGS)
+*_CLANGDWARF_RISCV64_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS)
+*_CLANGDWARF_RISCV64_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)
+*_CLANGDWARF_RISCV64_DEPS_FLAGS = DEF(GCC_DEPS_FLAGS)
+
+*_CLANGDWARF_RISCV64_CC_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_RISCV64_ASM_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_RISCV64_PP_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_RISCV64_VFRPP_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_RISCV64_ASLCC_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_RISCV64_ASLPP_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_RISCV64_DLINK_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_RISCV64_ASLDLINK_PATH = ENV(CLANGDWARF_BIN)clang
+
+*_CLANGDWARF_RISCV64_SLINK_PATH = ENV(CLANGDWARF_BIN)llvm-ar
+*_CLANGDWARF_RISCV64_RC_PATH = ENV(CLANGDWARF_BIN)llvm-objcopy
+
+*_CLANGDWARF_RISCV64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -fno-lto
+*_CLANGDWARF_RISCV64_ASLDLINK_FLAGS = DEF(CLANGDWARF_RISCV64_TARGET) DEF(GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS)
+*_CLANGDWARF_RISCV64_ASM_FLAGS = DEF(GCC_ASM_FLAGS) DEF(CLANGDWARF_RISCV64_TARGET) $(PLATFORM_FLAGS) -Qunused-arguments -mabi=lp64 -mno-relax
+*_CLANGDWARF_RISCV64_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_TARGET) DEF(GCC5_RISCV64_DLINK_FLAGS)
+*_CLANGDWARF_RISCV64_DLINK_XIPFLAGS = -z common-page-size=0x20
+*_CLANGDWARF_RISCV64_DLINK2_FLAGS = DEF(GCC_DLINK2_FLAGS_COMMON) -Wl,--defsym=PECOFF_HEADER_SIZE=0x240
+*_CLANGDWARF_RISCV64_PLATFORM_FLAGS =
+*_CLANGDWARF_RISCV64_PP_FLAGS = DEF(GCC_PP_FLAGS) DEF(CLANGDWARF_RISCV64_TARGET) $(PLATFORM_FLAGS)
+*_CLANGDWARF_RISCV64_RC_FLAGS = DEF(GCC_RISCV64_RC_FLAGS)
+*_CLANGDWARF_RISCV64_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) DEF(CLANGDWARF_RISCV64_TARGET) $(PLATFORM_FLAGS)
+*_CLANGDWARF_RISCV64_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) DEF(CLANGDWARF_RISCV64_TARGET)
+*_CLANGDWARF_RISCV64_CC_XIPFLAGS = DEF(GCC_RISCV64_CC_XIPFLAGS)
+
+ DEBUG_CLANGDWARF_RISCV64_CC_FLAGS = DEF(CLANGDWARF_RISCV64_CC_FLAGS) $(PLATFORM_FLAGS) -flto -O1
+ DEBUG_CLANGDWARF_RISCV64_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_DLINK_FLAGS) -flto -Wl,-O1 -fuse-ld=lld -Wl,--no-pie,--no-relax
+ NOOPT_CLANGDWARF_RISCV64_CC_FLAGS = DEF(CLANGDWARF_RISCV64_CC_FLAGS) $(PLATFORM_FLAGS) -O0
+ NOOPT_CLANGDWARF_RISCV64_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_DLINK_FLAGS) -fuse-ld=lld -Wl,--no-pie,--no-relax
+RELEASE_CLANGDWARF_RISCV64_CC_FLAGS = DEF(CLANGDWARF_RISCV64_CC_FLAGS) $(PLATFORM_FLAGS) -flto -O3
+RELEASE_CLANGDWARF_RISCV64_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_DLINK_FLAGS) -flto -Wl,-O3 -fuse-ld=lld -Wl,--no-pie,--no-relax
+
#
#
# XCODE5 support
diff --git a/BaseTools/Edk2ToolsBuild.py b/BaseTools/Edk2ToolsBuild.py
index 9ccea239..81acb930 100644
--- a/BaseTools/Edk2ToolsBuild.py
+++ b/BaseTools/Edk2ToolsBuild.py
@@ -133,8 +133,13 @@ class Edk2ToolsBuild(BaseAbstractInvocable):
shell_env.insert_path(self.OutputDir)
# Actually build the tools.
+ output_stream = edk2_logging.create_output_stream()
ret = RunCmd('nmake.exe', None,
workingdir=shell_env.get_shell_var("EDK_TOOLS_PATH"))
+ edk2_logging.remove_output_stream(output_stream)
+ problems = edk2_logging.scan_compiler_output(output_stream)
+ for level, problem in problems:
+ logging.log(level, problem)
if ret != 0:
raise Exception("Failed to build.")
@@ -143,7 +148,13 @@ class Edk2ToolsBuild(BaseAbstractInvocable):
elif self.tool_chain_tag.lower().startswith("gcc"):
cpu_count = self.GetCpuThreads()
+
+ output_stream = edk2_logging.create_output_stream()
ret = RunCmd("make", f"-C . -j {cpu_count}", workingdir=shell_env.get_shell_var("EDK_TOOLS_PATH"))
+ edk2_logging.remove_output_stream(output_stream)
+ problems = edk2_logging.scan_compiler_output(output_stream)
+ for level, problem in problems:
+ logging.log(level, problem)
if ret != 0:
raise Exception("Failed to build.")
diff --git a/BaseTools/ReadMe.rst b/BaseTools/ReadMe.rst
index ea0cf364..c1517c8f 100644
--- a/BaseTools/ReadMe.rst
+++ b/BaseTools/ReadMe.rst
@@ -1,3 +1,13 @@
+::
+
+ Note: New build instructions are available. It is recommended to start with
+ the new instructions if learning how to build edk2 and/or BaseTools for the
+ first time. This page is retained for reference.
+
+New instructions: `Build Instructions`_
+
+.. _`Build Instructions`: https://github.com/tianocore/tianocore.github.io/wiki/Build-Instructions
+
This directory contains the EDK II build tools and template files.
Templates are located in the Conf directory, while the tools executables for
Microsoft Windows Operating Systems are located in the Bin\\Win32 directory, other
@@ -23,9 +33,6 @@ After this, you can run the toolsetup.bat file, which is in the same
directory as this file. It should setup the remainder of the environment,
and build the tools if necessary.
-Please also refer to the ``BuildNotes.txt`` file for more information on
-building under Windows.
-
Unix-like operating systems
===========================
diff --git a/BaseTools/Scripts/GccBase.lds b/BaseTools/Scripts/GccBase.lds
index e7df2657..6081a66d 100644
--- a/BaseTools/Scripts/GccBase.lds
+++ b/BaseTools/Scripts/GccBase.lds
@@ -59,6 +59,16 @@ SECTIONS {
KEEP (*(.hii))
}
+ .got : {
+ *(.got)
+ }
+ ASSERT(SIZEOF(.got) == 0, "Unexpected GOT entries detected!")
+
+ .got.plt (INFO) : {
+ *(.got.plt)
+ }
+ ASSERT(SIZEOF(.got.plt) == 0 || SIZEOF(.got.plt) == 0xc || SIZEOF(.got.plt) == 0x18, "Unexpected GOT/PLT entries detected!")
+
/*
* Retain the GNU build id but in a non-allocatable section so GenFw
* does not copy it into the PE/COFF image.
diff --git a/BaseTools/Scripts/PatchCheck.py b/BaseTools/Scripts/PatchCheck.py
index e8f43496..11f4dfaf 100644
--- a/BaseTools/Scripts/PatchCheck.py
+++ b/BaseTools/Scripts/PatchCheck.py
@@ -372,7 +372,10 @@ class GitDiffCheck:
#
self.force_notabs = False
if os.path.basename(self.filename) == 'GNUmakefile' or \
- os.path.basename(self.filename) == 'Makefile':
+ os.path.basename(self.filename).lower() == 'makefile' or \
+ os.path.splitext(self.filename)[1] == '.makefile' or \
+ self.filename.startswith(
+ 'BaseTools/Source/C/VfrCompile/Pccts/'):
self.force_notabs = False
elif len(line.rstrip()) != 0:
self.format_error("didn't find diff command")
@@ -402,7 +405,7 @@ class GitDiffCheck:
self.format_error("didn't find diff hunk marker (@@)")
self.line_num += 1
elif self.state == PATCH:
- if self.binary:
+ if self.binary or self.filename.endswith(".rtf"):
pass
elif line.startswith('-'):
pass
@@ -501,6 +504,12 @@ class GitDiffCheck:
'but DEBUG_' + mo.group(1) +
' is now recommended', line)
+ rp_file = os.path.realpath(self.filename)
+ rp_script = os.path.realpath(__file__)
+ if line.find('__FUNCTION__') != -1 and rp_file != rp_script:
+ self.added_line_error('__FUNCTION__ was used, but __func__ '
+ 'is now recommended', line)
+
split_diff_re = re.compile(r'''
(?P
^ diff \s+ --git \s+ a/.+ \s+ b/.+ $
diff --git a/BaseTools/Source/C/Common/BasePeCoff.c b/BaseTools/Source/C/Common/BasePeCoff.c
index 89a81379..3de81781 100755
--- a/BaseTools/Source/C/Common/BasePeCoff.c
+++ b/BaseTools/Source/C/Common/BasePeCoff.c
@@ -77,6 +77,16 @@ PeCoffLoaderRelocateLoongArch64Image (
IN UINT64 Adjust
);
+/**
+ Retrieves the PE or TE Header from a PE/COFF or TE image
+
+ @param ImageContext The context of the image being loaded
+ @param PeHdr The buffer in which to return the PE header
+ @param TeHdr The buffer in which to return the TE header
+
+ @return RETURN_SUCCESS if the PE or TE Header is read,
+ Otherwise, the error status from reading the PE/COFF or TE image using the ImageRead function.
+**/
STATIC
RETURN_STATUS
PeCoffLoaderGetPeHeader (
@@ -84,26 +94,6 @@ PeCoffLoaderGetPeHeader (
OUT EFI_IMAGE_OPTIONAL_HEADER_UNION **PeHdr,
OUT EFI_TE_IMAGE_HEADER **TeHdr
)
-/*++
-
-Routine Description:
-
- Retrieves the PE or TE Header from a PE/COFF or TE image
-
-Arguments:
-
- ImageContext - The context of the image being loaded
-
- PeHdr - The buffer in which to return the PE header
-
- TeHdr - The buffer in which to return the TE header
-
-Returns:
-
- RETURN_SUCCESS if the PE or TE Header is read,
- Otherwise, the error status from reading the PE/COFF or TE image using the ImageRead function.
-
---*/
{
RETURN_STATUS Status;
EFI_IMAGE_DOS_HEADER DosHdr;
@@ -150,6 +140,17 @@ Returns:
return RETURN_SUCCESS;
}
+/**
+ Checks the PE or TE header of a PE/COFF or TE image to determine if it supported
+
+ @param ImageContext The context of the image being loaded
+ @param PeHdr The buffer in which to return the PE header
+ @param TeHdr The buffer in which to return the TE header
+
+ @retval RETURN_SUCCESS if the PE/COFF or TE image is supported
+ @retval RETURN_UNSUPPORTED of the PE/COFF or TE image is not supported.
+
+**/
STATIC
RETURN_STATUS
PeCoffLoaderCheckImageType (
@@ -157,26 +158,6 @@ PeCoffLoaderCheckImageType (
IN EFI_IMAGE_OPTIONAL_HEADER_UNION *PeHdr,
IN EFI_TE_IMAGE_HEADER *TeHdr
)
-/*++
-
-Routine Description:
-
- Checks the PE or TE header of a PE/COFF or TE image to determine if it supported
-
-Arguments:
-
- ImageContext - The context of the image being loaded
-
- PeHdr - The buffer in which to return the PE header
-
- TeHdr - The buffer in which to return the TE header
-
-Returns:
-
- RETURN_SUCCESS if the PE/COFF or TE image is supported
- RETURN_UNSUPPORTED of the PE/COFF or TE image is not supported.
-
---*/
{
//
// See if the machine type is supported.
@@ -188,32 +169,17 @@ Returns:
ImageContext->Machine = TeHdr->Machine;
}
- if (ImageContext->Machine != EFI_IMAGE_MACHINE_IA32 && \
- ImageContext->Machine != EFI_IMAGE_MACHINE_X64 && \
- ImageContext->Machine != EFI_IMAGE_MACHINE_ARMT && \
- ImageContext->Machine != EFI_IMAGE_MACHINE_EBC && \
- ImageContext->Machine != EFI_IMAGE_MACHINE_AARCH64 && \
- ImageContext->Machine != EFI_IMAGE_MACHINE_RISCV64 && \
- ImageContext->Machine != EFI_IMAGE_MACHINE_LOONGARCH64) {
- if (ImageContext->Machine == IMAGE_FILE_MACHINE_ARM) {
- //
- // There are two types of ARM images. Pure ARM and ARM/Thumb.
- // If we see the ARM say it is the ARM/Thumb so there is only
- // a single machine type we need to check for ARM.
- //
- ImageContext->Machine = EFI_IMAGE_MACHINE_ARMT;
- if (ImageContext->IsTeImage == FALSE) {
- PeHdr->Pe32.FileHeader.Machine = ImageContext->Machine;
- } else {
- TeHdr->Machine = ImageContext->Machine;
- }
-
- } else {
- //
- // unsupported PeImage machine type
- //
- return RETURN_UNSUPPORTED;
- }
+ if (ImageContext->Machine != IMAGE_FILE_MACHINE_I386 && \
+ ImageContext->Machine != IMAGE_FILE_MACHINE_X64 && \
+ ImageContext->Machine != IMAGE_FILE_MACHINE_ARMTHUMB_MIXED && \
+ ImageContext->Machine != IMAGE_FILE_MACHINE_EBC && \
+ ImageContext->Machine != IMAGE_FILE_MACHINE_ARM64 && \
+ ImageContext->Machine != IMAGE_FILE_MACHINE_RISCV64 && \
+ ImageContext->Machine != IMAGE_FILE_MACHINE_LOONGARCH64) {
+ //
+ // unsupported PeImage machine type
+ //
+ return RETURN_UNSUPPORTED;
}
//
@@ -239,31 +205,24 @@ Returns:
return RETURN_SUCCESS;
}
+/**
+ Retrieves information on a PE/COFF image
+
+ @param This Calling context
+ @param ImageContext The context of the image being loaded
+
+ @retval RETURN_SUCCESS The information on the PE/COFF image was collected.
+ @retval RETURN_INVALID_PARAMETER ImageContext is NULL.
+ @retval RETURN_UNSUPPORTED The PE/COFF image is not supported.
+ @retval Otherwise The error status from reading the PE/COFF image using the
+ ImageContext->ImageRead() function
+
+**/
RETURN_STATUS
EFIAPI
PeCoffLoaderGetImageInfo (
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
)
-/*++
-
-Routine Description:
-
- Retrieves information on a PE/COFF image
-
-Arguments:
-
- This - Calling context
- ImageContext - The context of the image being loaded
-
-Returns:
-
- RETURN_SUCCESS - The information on the PE/COFF image was collected.
- RETURN_INVALID_PARAMETER - ImageContext is NULL.
- RETURN_UNSUPPORTED - The PE/COFF image is not supported.
- Otherwise - The error status from reading the PE/COFF image using the
- ImageContext->ImageRead() function
-
---*/
{
RETURN_STATUS Status;
EFI_IMAGE_OPTIONAL_HEADER_UNION *PeHdr;
@@ -539,29 +498,21 @@ Returns:
return RETURN_SUCCESS;
}
+/**
+ Converts an image address to the loaded address
+
+ @param ImageContext The context of the image being loaded
+ @param Address The address to be converted to the loaded address
+
+ @return NULL if the address can not be converted, otherwise, the converted address
+
+--*/
STATIC
VOID *
PeCoffLoaderImageAddress (
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext,
IN UINTN Address
)
-/*++
-
-Routine Description:
-
- Converts an image address to the loaded address
-
-Arguments:
-
- ImageContext - The context of the image being loaded
-
- Address - The address to be converted to the loaded address
-
-Returns:
-
- NULL if the address can not be converted, otherwise, the converted address
-
---*/
{
if (Address >= ImageContext->ImageSize) {
ImageContext->ImageError = IMAGE_ERROR_INVALID_IMAGE_ADDRESS;
@@ -571,30 +522,22 @@ Returns:
return (UINT8 *) ((UINTN) ImageContext->ImageAddress + Address);
}
+/**
+ Relocates a PE/COFF image in memory
+
+ @param This Calling context
+ @param ImageContext Contains information on the loaded image to relocate
+
+ @retval RETURN_SUCCESS if the PE/COFF image was relocated
+ @retval RETURN_LOAD_ERROR if the image is not a valid PE/COFF image
+ @retval RETURN_UNSUPPORTED not support
+
+**/
RETURN_STATUS
EFIAPI
PeCoffLoaderRelocateImage (
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
)
-/*++
-
-Routine Description:
-
- Relocates a PE/COFF image in memory
-
-Arguments:
-
- This - Calling context
-
- ImageContext - Contains information on the loaded image to relocate
-
-Returns:
-
- RETURN_SUCCESS if the PE/COFF image was relocated
- RETURN_LOAD_ERROR if the image is not a valid PE/COFF image
- RETURN_UNSUPPORTED not support
-
---*/
{
RETURN_STATUS Status;
EFI_IMAGE_OPTIONAL_HEADER_UNION *PeHdr;
@@ -816,16 +759,16 @@ Returns:
default:
switch (MachineType) {
- case EFI_IMAGE_MACHINE_IA32:
+ case IMAGE_FILE_MACHINE_I386:
Status = PeCoffLoaderRelocateIa32Image (Reloc, Fixup, &FixupData, Adjust);
break;
- case EFI_IMAGE_MACHINE_ARMT:
+ case IMAGE_FILE_MACHINE_ARMTHUMB_MIXED:
Status = PeCoffLoaderRelocateArmImage (&Reloc, Fixup, &FixupData, Adjust);
break;
- case EFI_IMAGE_MACHINE_RISCV64:
+ case IMAGE_FILE_MACHINE_RISCV64:
Status = PeCoffLoaderRelocateRiscVImage (Reloc, Fixup, &FixupData, Adjust);
break;
- case EFI_IMAGE_MACHINE_LOONGARCH64:
+ case IMAGE_FILE_MACHINE_LOONGARCH64:
Status = PeCoffLoaderRelocateLoongArch64Image (Reloc, Fixup, &FixupData, Adjust);
break;
default:
@@ -853,31 +796,23 @@ Returns:
return RETURN_SUCCESS;
}
+/**
+ Loads a PE/COFF image into memory
+
+ @param This Calling context
+ @param ImageContext Contains information on image to load into memory
+
+ @retval RETURN_SUCCESS if the PE/COFF image was loaded
+ @retval RETURN_BUFFER_TOO_SMALL if the caller did not provide a large enough buffer
+ @retval RETURN_LOAD_ERROR if the image is a runtime driver with no relocations
+ @retval RETURN_INVALID_PARAMETER if the image address is invalid
+
+**/
RETURN_STATUS
EFIAPI
PeCoffLoaderLoadImage (
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
)
-/*++
-
-Routine Description:
-
- Loads a PE/COFF image into memory
-
-Arguments:
-
- This - Calling context
-
- ImageContext - Contains information on image to load into memory
-
-Returns:
-
- RETURN_SUCCESS if the PE/COFF image was loaded
- RETURN_BUFFER_TOO_SMALL if the caller did not provide a large enough buffer
- RETURN_LOAD_ERROR if the image is a runtime driver with no relocations
- RETURN_INVALID_PARAMETER if the image address is invalid
-
---*/
{
RETURN_STATUS Status;
EFI_IMAGE_OPTIONAL_HEADER_UNION *PeHdr;
@@ -1320,14 +1255,14 @@ PeCoffLoaderGetPdbPointer (
// generate PE32+ image with PE32 Magic.
//
switch (Hdr.Pe32->FileHeader.Machine) {
- case EFI_IMAGE_MACHINE_IA32:
- case EFI_IMAGE_MACHINE_ARMT:
+ case IMAGE_FILE_MACHINE_I386:
+ case IMAGE_FILE_MACHINE_ARMTHUMB_MIXED:
//
// Assume PE32 image with IA32 Machine field.
//
Magic = EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC;
break;
- case EFI_IMAGE_MACHINE_X64:
+ case IMAGE_FILE_MACHINE_X64:
//
// Assume PE32+ image with X64 Machine field
//
diff --git a/BaseTools/Source/C/Common/CommonLib.c b/BaseTools/Source/C/Common/CommonLib.c
index ecda9d70..e224cd01 100644
--- a/BaseTools/Source/C/Common/CommonLib.c
+++ b/BaseTools/Source/C/Common/CommonLib.c
@@ -26,28 +26,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
} \
} while (FALSE)
+/**
+ Set Buffer to zero for Size bytes.
+
+ @param Buffer Memory to set.
+ @param Size Number of bytes to set
+**/
VOID
PeiZeroMem (
IN VOID *Buffer,
IN UINTN Size
)
-/*++
-
-Routine Description:
-
- Set Buffer to zero for Size bytes.
-
-Arguments:
-
- Buffer - Memory to set.
-
- Size - Number of bytes to set
-
-Returns:
-
- None
-
---*/
{
INT8 *Ptr;
@@ -57,31 +46,19 @@ Returns:
}
}
+/**
+ Copy Length bytes from Source to Destination.
+
+ @param Destination Target of copy
+ @param Source Place to copy from
+ @param Length Number of bytes to copy
+**/
VOID
PeiCopyMem (
IN VOID *Destination,
IN VOID *Source,
IN UINTN Length
)
-/*++
-
-Routine Description:
-
- Copy Length bytes from Source to Destination.
-
-Arguments:
-
- Destination - Target of copy
-
- Source - Place to copy from
-
- Length - Number of bytes to copy
-
-Returns:
-
- None
-
---*/
{
CHAR8 *Destination8;
CHAR8 *Source8;
@@ -112,27 +89,20 @@ CopyMem (
PeiCopyMem (Destination, Source, Length);
}
+/**
+ Compares to GUIDs
+
+ @param Guid1 guid to compare
+ @param Guid2 guid to compare
+
+ @retval = 0 if Guid1 == Guid2
+ @retval != 0 if Guid1 != Guid2
+**/
INTN
CompareGuid (
IN EFI_GUID *Guid1,
IN EFI_GUID *Guid2
)
-/*++
-
-Routine Description:
-
- Compares to GUIDs
-
-Arguments:
-
- Guid1 - guid to compare
- Guid2 - guid to compare
-
-Returns:
- = 0 if Guid1 == Guid2
- != 0 if Guid1 != Guid2
-
---*/
{
INT32 *g1;
INT32 *g2;
@@ -152,34 +122,25 @@ Returns:
return r;
}
+/**
+ This function opens a file and reads it into a memory buffer. The function
+ will allocate the memory buffer and returns the size of the buffer.
+ @param InputFileName The name of the file to read.
+ @param InputFileImage A pointer to the memory buffer.
+ @param BytesRead The size of the memory buffer.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_INVALID_PARAMETER One of the input parameters was invalid.
+ @retval EFI_ABORTED An error occurred.
+ @retval EFI_OUT_OF_RESOURCES No resource to complete operations.
+**/
EFI_STATUS
GetFileImage (
IN CHAR8 *InputFileName,
OUT CHAR8 **InputFileImage,
OUT UINT32 *BytesRead
)
-/*++
-
-Routine Description:
-
- This function opens a file and reads it into a memory buffer. The function
- will allocate the memory buffer and returns the size of the buffer.
-
-Arguments:
-
- InputFileName The name of the file to read.
- InputFileImage A pointer to the memory buffer.
- BytesRead The size of the memory buffer.
-
-Returns:
-
- EFI_SUCCESS The function completed successfully.
- EFI_INVALID_PARAMETER One of the input parameters was invalid.
- EFI_ABORTED An error occurred.
- EFI_OUT_OF_RESOURCES No resource to complete operations.
-
---*/
{
FILE *InputFile;
UINT32 FileSize;
@@ -255,32 +216,24 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ This function opens a file and writes OutputFileImage into the file.
+
+ @param OutputFileName The name of the file to write.
+ @param OutputFileImage A pointer to the memory buffer.
+ @param BytesToWrite The size of the memory buffer.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_INVALID_PARAMETER One of the input parameters was invalid.
+ @retval EFI_ABORTED An error occurred.
+ @retval EFI_OUT_OF_RESOURCES No resource to complete operations.
+**/
EFI_STATUS
PutFileImage (
IN CHAR8 *OutputFileName,
IN CHAR8 *OutputFileImage,
IN UINT32 BytesToWrite
)
-/*++
-
-Routine Description:
-
- This function opens a file and writes OutputFileImage into the file.
-
-Arguments:
-
- OutputFileName The name of the file to write.
- OutputFileImage A pointer to the memory buffer.
- BytesToWrite The size of the memory buffer.
-
-Returns:
-
- EFI_SUCCESS The function completed successfully.
- EFI_INVALID_PARAMETER One of the input parameters was invalid.
- EFI_ABORTED An error occurred.
- EFI_OUT_OF_RESOURCES No resource to complete operations.
-
---*/
{
FILE *OutputFile;
UINT32 BytesWrote;
@@ -320,52 +273,36 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ This function calculates the value needed for a valid UINT8 checksum
+
+ @param Buffer Pointer to buffer containing byte data of component.
+ @param Size Size of the buffer
+
+ @return The 8 bit checksum value needed.
+**/
UINT8
CalculateChecksum8 (
IN UINT8 *Buffer,
IN UINTN Size
)
-/*++
-
-Routine Description:
-
- This function calculates the value needed for a valid UINT8 checksum
-
-Arguments:
-
- Buffer Pointer to buffer containing byte data of component.
- Size Size of the buffer
-
-Returns:
-
- The 8 bit checksum value needed.
-
---*/
{
return (UINT8) (0x100 - CalculateSum8 (Buffer, Size));
}
+/**
+ This function calculates the UINT8 sum for the requested region.
+
+ @param Buffer Pointer to buffer containing byte data of component.
+ @param Size Size of the buffer
+
+ @return The 8 bit checksum value needed.
+**/
UINT8
CalculateSum8 (
IN UINT8 *Buffer,
IN UINTN Size
)
-/*++
-
-Routine Description::
-
- This function calculates the UINT8 sum for the requested region.
-
-Arguments:
-
- Buffer Pointer to buffer containing byte data of component.
- Size Size of the buffer
-
-Returns:
-
- The 8 bit checksum value needed.
-
---*/
{
UINTN Index;
UINT8 Sum;
@@ -382,52 +319,36 @@ Returns:
return Sum;
}
+/**
+ This function calculates the value needed for a valid UINT16 checksum
+
+ @param Buffer Pointer to buffer containing byte data of component.
+ @param Size Size of the buffer
+
+ @return The 16 bit checksum value needed.
+**/
UINT16
CalculateChecksum16 (
IN UINT16 *Buffer,
IN UINTN Size
)
-/*++
-
-Routine Description::
-
- This function calculates the value needed for a valid UINT16 checksum
-
-Arguments:
-
- Buffer Pointer to buffer containing byte data of component.
- Size Size of the buffer
-
-Returns:
-
- The 16 bit checksum value needed.
-
---*/
{
return (UINT16) (0x10000 - CalculateSum16 (Buffer, Size));
}
+/**
+ This function calculates the UINT16 sum for the requested region.
+
+ @param Buffer Pointer to buffer containing byte data of component.
+ @param Size Size of the buffer
+
+ @return The 16 bit checksum
+**/
UINT16
CalculateSum16 (
IN UINT16 *Buffer,
IN UINTN Size
)
-/*++
-
-Routine Description:
-
- This function calculates the UINT16 sum for the requested region.
-
-Arguments:
-
- Buffer Pointer to buffer containing byte data of component.
- Size Size of the buffer
-
-Returns:
-
- The 16 bit checksum
-
---*/
{
UINTN Index;
UINT16 Sum;
@@ -444,26 +365,18 @@ Returns:
return (UINT16) Sum;
}
+/**
+ This function prints a GUID to STDOUT.
+
+ @param Guid Pointer to a GUID to print.
+
+ @retval EFI_SUCCESS The GUID was printed.
+ @retval EFI_INVALID_PARAMETER The input was NULL.
+**/
EFI_STATUS
PrintGuid (
IN EFI_GUID *Guid
)
-/*++
-
-Routine Description:
-
- This function prints a GUID to STDOUT.
-
-Arguments:
-
- Guid Pointer to a GUID to print.
-
-Returns:
-
- EFI_SUCCESS The GUID was printed.
- EFI_INVALID_PARAMETER The input was NULL.
-
---*/
{
if (Guid == NULL) {
Error (NULL, 0, 2000, "Invalid parameter", "PrintGuidToBuffer() called with a NULL value");
@@ -487,6 +400,18 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ This function prints a GUID to a buffer
+
+ @param Guid Pointer to a GUID to print.
+ @param Buffer Pointer to a user-provided buffer to print to
+ @param BufferLen Size of the Buffer
+ @param Uppercase If use upper case.
+
+ @retval EFI_SUCCESS The GUID was printed.
+ @retval EFI_INVALID_PARAMETER The input was NULL.
+ @retval EFI_BUFFER_TOO_SMALL The input buffer was not big enough
+**/
EFI_STATUS
PrintGuidToBuffer (
IN EFI_GUID *Guid,
@@ -494,26 +419,6 @@ PrintGuidToBuffer (
IN UINT32 BufferLen,
IN BOOLEAN Uppercase
)
-/*++
-
-Routine Description:
-
- This function prints a GUID to a buffer
-
-Arguments:
-
- Guid - Pointer to a GUID to print.
- Buffer - Pointer to a user-provided buffer to print to
- BufferLen - Size of the Buffer
- Uppercase - If use upper case.
-
-Returns:
-
- EFI_SUCCESS The GUID was printed.
- EFI_INVALID_PARAMETER The input was NULL.
- EFI_BUFFER_TOO_SMALL The input buffer was not big enough
-
---*/
{
if (Guid == NULL) {
Error (NULL, 0, 2000, "Invalid parameter", "PrintGuidToBuffer() called with a NULL value");
@@ -591,22 +496,17 @@ char *strlwr(char *s)
//
CHAR8 mCommonLibFullPath[MAX_LONG_FILE_PATH];
+/**
+ Convert FileName to the long file path, which can support larger than 260 length.
+
+ @param FileName FileName.
+
+ @return LongFilePath A pointer to the converted long file path.
+**/
CHAR8 *
LongFilePath (
IN CHAR8 *FileName
)
-/*++
-
-Routine Description:
- Convert FileName to the long file path, which can support larger than 260 length.
-
-Arguments:
- FileName - FileName.
-
-Returns:
- LongFilePath A pointer to the converted long file path.
-
---*/
{
#ifdef __GNUC__
//
@@ -2188,4 +2088,3 @@ SplitStr (
*List = Str;
return ReturnStr;
}
-
diff --git a/BaseTools/Source/C/Common/CommonLib.h b/BaseTools/Source/C/Common/CommonLib.h
index 2fa4b576..5a3f1149 100644
--- a/BaseTools/Source/C/Common/CommonLib.h
+++ b/BaseTools/Source/C/Common/CommonLib.h
@@ -95,13 +95,6 @@ GetFileImage (
)
;
-EFI_STATUS
-PutFileImage (
- IN CHAR8 *OutputFileName,
- IN CHAR8 *OutputFileImage,
- IN UINT32 BytesToWrite
- )
-;
/*++
Routine Description:
@@ -122,6 +115,13 @@ Returns:
EFI_OUT_OF_RESOURCES No resource to complete operations.
**/
+EFI_STATUS
+PutFileImage (
+ IN CHAR8 *OutputFileName,
+ IN CHAR8 *OutputFileImage,
+ IN UINT32 BytesToWrite
+ )
+;
UINT8
CalculateChecksum8 (
diff --git a/BaseTools/Source/C/Common/Compress.h b/BaseTools/Source/C/Common/Compress.h
index bacc8183..17773459 100644
--- a/BaseTools/Source/C/Common/Compress.h
+++ b/BaseTools/Source/C/Common/Compress.h
@@ -15,13 +15,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "CommonLib.h"
#include
-/*++
-
-Routine Description:
+/**
Tiano compression routine.
-
---*/
+**/
EFI_STATUS
TianoCompress (
IN UINT8 *SrcBuffer,
@@ -31,13 +28,9 @@ TianoCompress (
)
;
-/*++
-
-Routine Description:
-
+/**
Efi compression routine.
-
---*/
+**/
EFI_STATUS
EfiCompress (
IN UINT8 *SrcBuffer,
@@ -47,29 +40,21 @@ EfiCompress (
)
;
-/*++
-
-Routine Description:
-
+/**
The compression routine.
-Arguments:
+ @param SrcBuffer The buffer storing the source data
+ @param SrcSize The size of source data
+ @param DstBuffer The buffer to store the compressed data
+ @param DstSize On input, the size of DstBuffer; On output,
+ the size of the actual compressed data.
- SrcBuffer - The buffer storing the source data
- SrcSize - The size of source data
- DstBuffer - The buffer to store the compressed data
- DstSize - On input, the size of DstBuffer; On output,
- the size of the actual compressed data.
-
-Returns:
-
- EFI_BUFFER_TOO_SMALL - The DstBuffer is too small. In this case,
+ @retval EFI_BUFFER_TOO_SMALL The DstBuffer is too small. In this case,
DstSize contains the size needed.
- EFI_SUCCESS - Compression is successful.
- EFI_OUT_OF_RESOURCES - No resource to complete function.
- EFI_INVALID_PARAMETER - Parameter supplied is wrong.
-
---*/
+ @retval EFI_SUCCESS Compression is successful.
+ @retval EFI_OUT_OF_RESOURCES No resource to complete function.
+ @retval EFI_INVALID_PARAMETER Parameter supplied is wrong.
+**/
typedef
EFI_STATUS
(*COMPRESS_FUNCTION) (
diff --git a/BaseTools/Source/C/Common/Crc32.c b/BaseTools/Source/C/Common/Crc32.c
index df823283..b5a154f4 100644
--- a/BaseTools/Source/C/Common/Crc32.c
+++ b/BaseTools/Source/C/Common/Crc32.c
@@ -268,31 +268,23 @@ UINT32 mCrcTable[256] = {
0x2D02EF8D
};
+/**
+ The CalculateCrc32 routine.
+
+ @param Data The buffer containing the data to be processed
+ @param DataSize The size of data to be processed
+ @param CrcOut A pointer to the caller allocated UINT32 that on
+ contains the CRC32 checksum of Data
+
+ @retval EFI_SUCCESS Calculation is successful.
+ @retval EFI_INVALID_PARAMETER Data / CrcOut = NULL, or DataSize = 0
+**/
EFI_STATUS
CalculateCrc32 (
IN UINT8 *Data,
IN UINTN DataSize,
IN OUT UINT32 *CrcOut
)
-/*++
-
-Routine Description:
-
- The CalculateCrc32 routine.
-
-Arguments:
-
- Data - The buffer containing the data to be processed
- DataSize - The size of data to be processed
- CrcOut - A pointer to the caller allocated UINT32 that on
- contains the CRC32 checksum of Data
-
-Returns:
-
- EFI_SUCCESS - Calculation is successful.
- EFI_INVALID_PARAMETER - Data / CrcOut = NULL, or DataSize = 0
-
---*/
{
UINT32 Crc;
UINTN Index;
diff --git a/BaseTools/Source/C/Common/Crc32.h b/BaseTools/Source/C/Common/Crc32.h
index a8c855c4..b8922fa8 100644
--- a/BaseTools/Source/C/Common/Crc32.h
+++ b/BaseTools/Source/C/Common/Crc32.h
@@ -11,31 +11,23 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include
+/**
+ The CalculateCrc32 routine.
+
+ @param Data The buffer containing the data to be processed
+ @param DataSize The size of data to be processed
+ @param CrcOut A pointer to the caller allocated UINT32 that on
+ contains the CRC32 checksum of Data
+
+ @retval EFI_SUCCESS - Calculation is successful.
+ @retval EFI_INVALID_PARAMETER - Data / CrcOut = NULL, or DataSize = 0
+**/
EFI_STATUS
CalculateCrc32 (
IN UINT8 *Data,
IN UINTN DataSize,
IN OUT UINT32 *CrcOut
)
-/*++
-
-Routine Description:
-
- The CalculateCrc32 routine.
-
-Arguments:
-
- Data - The buffer containing the data to be processed
- DataSize - The size of data to be processed
- CrcOut - A pointer to the caller allocated UINT32 that on
- contains the CRC32 checksum of Data
-
-Returns:
-
- EFI_SUCCESS - Calculation is successful.
- EFI_INVALID_PARAMETER - Data / CrcOut = NULL, or DataSize = 0
-
---*/
;
#endif
diff --git a/BaseTools/Source/C/Common/Decompress.c b/BaseTools/Source/C/Common/Decompress.c
index e494437a..27bc04eb 100644
--- a/BaseTools/Source/C/Common/Decompress.c
+++ b/BaseTools/Source/C/Common/Decompress.c
@@ -15,6 +15,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// Decompression algorithm begins here
//
+#define UINT8_MAX 0xff
#define BITBUFSIZ 32
#define MAXMATCH 256
#define THRESHOLD 3
@@ -62,26 +63,18 @@ typedef struct {
STATIC UINT16 mPbit = EFIPBIT;
+/**
+ Shift mBitBuf NumOfBits left. Read in NumOfBits of bits from source.
+
+ @param Sd The global scratch data
+ @param NumOfBit The number of bits to shift and read.
+**/
STATIC
VOID
FillBuf (
IN SCRATCH_DATA *Sd,
IN UINT16 NumOfBits
)
-/*++
-
-Routine Description:
-
- Shift mBitBuf NumOfBits left. Read in NumOfBits of bits from source.
-
-Arguments:
-
- Sd - The global scratch data
- NumOfBit - The number of bits to shift and read.
-
-Returns: (VOID)
-
---*/
{
Sd->mBitBuf = (UINT32) (((UINT64)Sd->mBitBuf) << NumOfBits);
@@ -112,30 +105,22 @@ Returns: (VOID)
Sd->mBitBuf |= Sd->mSubBitBuf >> Sd->mBitCount;
}
+/**
+ Get NumOfBits of bits out from mBitBuf. Fill mBitBuf with subsequent
+ NumOfBits of bits from source. Returns NumOfBits of bits that are
+ popped out.
+
+ @param Sd The global scratch data.
+ @param NumOfBits The number of bits to pop and read.
+
+ @return The bits that are popped out.
+**/
STATIC
UINT32
GetBits (
IN SCRATCH_DATA *Sd,
IN UINT16 NumOfBits
)
-/*++
-
-Routine Description:
-
- Get NumOfBits of bits out from mBitBuf. Fill mBitBuf with subsequent
- NumOfBits of bits from source. Returns NumOfBits of bits that are
- popped out.
-
-Arguments:
-
- Sd - The global scratch data.
- NumOfBits - The number of bits to pop and read.
-
-Returns:
-
- The bits that are popped out.
-
---*/
{
UINT32 OutBits;
@@ -146,6 +131,18 @@ Returns:
return OutBits;
}
+/**
+ Creates Huffman Code mapping table according to code length array.
+
+ @param Sd The global scratch data
+ @param NumOfChar Number of symbols in the symbol set
+ @param BitLen Code length array
+ @param TableBits The width of the mapping table
+ @param Table The table
+
+ @retval 0 - OK.
+ @retval BAD_TABLE - The table is corrupted.
+**/
STATIC
UINT16
MakeTable (
@@ -155,26 +152,6 @@ MakeTable (
IN UINT16 TableBits,
OUT UINT16 *Table
)
-/*++
-
-Routine Description:
-
- Creates Huffman Code mapping table according to code length array.
-
-Arguments:
-
- Sd - The global scratch data
- NumOfChar - Number of symbols in the symbol set
- BitLen - Code length array
- TableBits - The width of the mapping table
- Table - The table
-
-Returns:
-
- 0 - OK.
- BAD_TABLE - The table is corrupted.
-
---*/
{
UINT16 Count[17];
UINT16 Weight[17];
@@ -290,26 +267,18 @@ Returns:
return 0;
}
+/**
+ Decodes a position value.
+
+ @param Sd the global scratch data
+
+ @return The position value decoded.
+**/
STATIC
UINT32
DecodeP (
IN SCRATCH_DATA *Sd
)
-/*++
-
-Routine Description:
-
- Decodes a position value.
-
-Arguments:
-
- Sd - the global scratch data
-
-Returns:
-
- The position value decoded.
-
---*/
{
UINT16 Val;
UINT32 Mask;
@@ -344,6 +313,17 @@ Returns:
return Pos;
}
+/**
+ Reads code lengths for the Extra Set or the Position Set
+
+ @param Sd The global scratch data
+ @param nn Number of symbols
+ @param nbit Number of bits needed to represent nn
+ @param Special The special symbol that needs to be taken care of
+
+ @retval 0 - OK.
+ @retval BAD_TABLE - Table is corrupted.
+**/
STATIC
UINT16
ReadPTLen (
@@ -352,25 +332,6 @@ ReadPTLen (
IN UINT16 nbit,
IN UINT16 Special
)
-/*++
-
-Routine Description:
-
- Reads code lengths for the Extra Set or the Position Set
-
-Arguments:
-
- Sd - The global scratch data
- nn - Number of symbols
- nbit - Number of bits needed to represent nn
- Special - The special symbol that needs to be taken care of
-
-Returns:
-
- 0 - OK.
- BAD_TABLE - Table is corrupted.
-
---*/
{
UINT16 Number;
UINT16 CharC;
@@ -430,24 +391,16 @@ Returns:
return MakeTable (Sd, nn, Sd->mPTLen, 8, Sd->mPTTable);
}
+/**
+ Reads code lengths for Char&Len Set.
+
+ @param Sd the global scratch data
+**/
STATIC
VOID
ReadCLen (
SCRATCH_DATA *Sd
)
-/*++
-
-Routine Description:
-
- Reads code lengths for Char&Len Set.
-
-Arguments:
-
- Sd - the global scratch data
-
-Returns: (VOID)
-
---*/
{
UINT16 Number;
UINT16 CharC;
@@ -526,26 +479,18 @@ Returns: (VOID)
return ;
}
+/**
+ Decode a character/length value.
+
+ @param Sd The global scratch data.
+
+ @return The value decoded.
+**/
STATIC
UINT16
DecodeC (
SCRATCH_DATA *Sd
)
-/*++
-
-Routine Description:
-
- Decode a character/length value.
-
-Arguments:
-
- Sd - The global scratch data.
-
-Returns:
-
- The value decoded.
-
---*/
{
UINT16 Index2;
UINT32 Mask;
@@ -592,24 +537,16 @@ Returns:
return Index2;
}
+/**
+ Decode the source data and put the resulting data into the destination buffer.
+
+ @param Sd The global scratch data
+ **/
STATIC
VOID
Decode (
SCRATCH_DATA *Sd
)
-/*++
-
-Routine Description:
-
- Decode the source data and put the resulting data into the destination buffer.
-
-Arguments:
-
- Sd - The global scratch data
-
-Returns: (VOID)
-
- --*/
{
UINT16 BytesRemain;
UINT32 DataIdx;
@@ -669,6 +606,17 @@ Returns: (VOID)
return ;
}
+/**
+ The implementation of EFI_DECOMPRESS_PROTOCOL.GetInfo().
+
+ @param Source The source buffer containing the compressed data.
+ @param SrcSize The size of source buffer
+ @param DstSize The size of destination buffer.
+ @param ScratchSize The size of scratch buffer.
+
+ @retval EFI_SUCCESS - The size of destination buffer and the size of scratch buffer are successfully retrieved.
+ @retval EFI_INVALID_PARAMETER - The source data is corrupted
+**/
EFI_STATUS
GetInfo (
IN VOID *Source,
@@ -676,25 +624,6 @@ GetInfo (
OUT UINT32 *DstSize,
OUT UINT32 *ScratchSize
)
-/*++
-
-Routine Description:
-
- The implementation of EFI_DECOMPRESS_PROTOCOL.GetInfo().
-
-Arguments:
-
- Source - The source buffer containing the compressed data.
- SrcSize - The size of source buffer
- DstSize - The size of destination buffer.
- ScratchSize - The size of scratch buffer.
-
-Returns:
-
- EFI_SUCCESS - The size of destination buffer and the size of scratch buffer are successfully retrieved.
- EFI_INVALID_PARAMETER - The source data is corrupted
-
---*/
{
UINT8 *Src;
UINT32 CompSize;
@@ -716,6 +645,19 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ The implementation Efi and Tiano Decompress().
+
+ @param Source - The source buffer containing the compressed data.
+ @param SrcSize - The size of source buffer
+ @param Destination - The destination buffer to store the decompressed data
+ @param DstSize - The size of destination buffer.
+ @param Scratch - The buffer used internally by the decompress routine. This buffer is needed to store intermediate data.
+ @param ScratchSize - The size of scratch buffer.
+
+ @retval EFI_SUCCESS - Decompression is successful
+ @retval EFI_INVALID_PARAMETER - The source data is corrupted
+**/
EFI_STATUS
Decompress (
IN VOID *Source,
@@ -725,27 +667,6 @@ Decompress (
IN OUT VOID *Scratch,
IN UINT32 ScratchSize
)
-/*++
-
-Routine Description:
-
- The implementation Efi and Tiano Decompress().
-
-Arguments:
-
- Source - The source buffer containing the compressed data.
- SrcSize - The size of source buffer
- Destination - The destination buffer to store the decompressed data
- DstSize - The size of destination buffer.
- Scratch - The buffer used internally by the decompress routine. This buffer is needed to store intermediate data.
- ScratchSize - The size of scratch buffer.
-
-Returns:
-
- EFI_SUCCESS - Decompression is successful
- EFI_INVALID_PARAMETER - The source data is corrupted
-
---*/
{
UINT32 Index;
UINT32 CompSize;
@@ -811,6 +732,17 @@ Returns:
return Status;
}
+/**
+ The implementation Efi Decompress GetInfo().
+
+ @param Source The source buffer containing the compressed data.
+ @param SrcSize The size of source buffer
+ @param DstSize The size of destination buffer.
+ @param ScratchSize The size of scratch buffer.
+
+ @retval EFI_SUCCESS The size of destination buffer and the size of scratch buffer are successfully retrieved.
+ @retval EFI_INVALID_PARAMETER The source data is corrupted
+**/
EFI_STATUS
EfiGetInfo (
IN VOID *Source,
@@ -818,29 +750,21 @@ EfiGetInfo (
OUT UINT32 *DstSize,
OUT UINT32 *ScratchSize
)
-/*++
-
-Routine Description:
-
- The implementation Efi Decompress GetInfo().
-
-Arguments:
-
- Source - The source buffer containing the compressed data.
- SrcSize - The size of source buffer
- DstSize - The size of destination buffer.
- ScratchSize - The size of scratch buffer.
-
-Returns:
-
- EFI_SUCCESS - The size of destination buffer and the size of scratch buffer are successfully retrieved.
- EFI_INVALID_PARAMETER - The source data is corrupted
-
---*/
{
return GetInfo (Source, SrcSize, DstSize, ScratchSize);
}
+/**
+ The implementation Tiano Decompress GetInfo().
+
+ @param Source The source buffer containing the compressed data.
+ @param SrcSize The size of source buffer
+ @param DstSize The size of destination buffer.
+ @param ScratchSize The size of scratch buffer.
+
+ @retval EFI_SUCCESS The size of destination buffer and the size of scratch buffer are successfully retrieved.
+ @retval EFI_INVALID_PARAMETER The source data is corrupted
+**/
EFI_STATUS
TianoGetInfo (
IN VOID *Source,
@@ -848,29 +772,23 @@ TianoGetInfo (
OUT UINT32 *DstSize,
OUT UINT32 *ScratchSize
)
-/*++
-
-Routine Description:
-
- The implementation Tiano Decompress GetInfo().
-
-Arguments:
-
- Source - The source buffer containing the compressed data.
- SrcSize - The size of source buffer
- DstSize - The size of destination buffer.
- ScratchSize - The size of scratch buffer.
-
-Returns:
-
- EFI_SUCCESS - The size of destination buffer and the size of scratch buffer are successfully retrieved.
- EFI_INVALID_PARAMETER - The source data is corrupted
-
---*/
{
return GetInfo (Source, SrcSize, DstSize, ScratchSize);
}
+/**
+ The implementation of Efi Decompress().
+
+ @param Source The source buffer containing the compressed data.
+ @param SrcSize The size of source buffer
+ @param Destination The destination buffer to store the decompressed data
+ @param DstSize The size of destination buffer.
+ @param Scratch The buffer used internally by the decompress routine. This buffer is needed to store intermediate data.
+ @param ScratchSize The size of scratch buffer.
+
+ @retval EFI_SUCCESS Decompression is successful
+ @retval EFI_INVALID_PARAMETER The source data is corrupted
+**/
EFI_STATUS
EfiDecompress (
IN VOID *Source,
@@ -880,32 +798,24 @@ EfiDecompress (
IN OUT VOID *Scratch,
IN UINT32 ScratchSize
)
-/*++
-
-Routine Description:
-
- The implementation of Efi Decompress().
-
-Arguments:
-
- Source - The source buffer containing the compressed data.
- SrcSize - The size of source buffer
- Destination - The destination buffer to store the decompressed data
- DstSize - The size of destination buffer.
- Scratch - The buffer used internally by the decompress routine. This buffer is needed to store intermediate data.
- ScratchSize - The size of scratch buffer.
-
-Returns:
-
- EFI_SUCCESS - Decompression is successful
- EFI_INVALID_PARAMETER - The source data is corrupted
-
---*/
{
mPbit = EFIPBIT;
return Decompress (Source, SrcSize, Destination, DstSize, Scratch, ScratchSize);
}
+/**
+ The implementation of Tiano Decompress().
+
+ @param Source The source buffer containing the compressed data.
+ @param SrcSize The size of source buffer
+ @param Destination The destination buffer to store the decompressed data
+ @param DstSize The size of destination buffer.
+ @param Scratch The buffer used internally by the decompress routine. This buffer is needed to store intermediate data.
+ @param ScratchSize The size of scratch buffer.
+
+ @retval EFI_SUCCESS Decompression is successful
+ @retval EFI_INVALID_PARAMETER The source data is corrupted
+**/
EFI_STATUS
TianoDecompress (
IN VOID *Source,
@@ -915,27 +825,6 @@ TianoDecompress (
IN OUT VOID *Scratch,
IN UINT32 ScratchSize
)
-/*++
-
-Routine Description:
-
- The implementation of Tiano Decompress().
-
-Arguments:
-
- Source - The source buffer containing the compressed data.
- SrcSize - The size of source buffer
- Destination - The destination buffer to store the decompressed data
- DstSize - The size of destination buffer.
- Scratch - The buffer used internally by the decompress routine. This buffer is needed to store intermediate data.
- ScratchSize - The size of scratch buffer.
-
-Returns:
-
- EFI_SUCCESS - Decompression is successful
- EFI_INVALID_PARAMETER - The source data is corrupted
-
---*/
{
mPbit = MAXPBIT;
return Decompress (Source, SrcSize, Destination, DstSize, Scratch, ScratchSize);
diff --git a/BaseTools/Source/C/Common/Decompress.h b/BaseTools/Source/C/Common/Decompress.h
index 2df9a14b..73e35966 100644
--- a/BaseTools/Source/C/Common/Decompress.h
+++ b/BaseTools/Source/C/Common/Decompress.h
@@ -11,13 +11,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include
-EFI_STATUS
-EfiGetInfo (
- IN VOID *Source,
- IN UINT32 SrcSize,
- OUT UINT32 *DstSize,
- OUT UINT32 *ScratchSize
- );
/**
Routine Description:
@@ -37,7 +30,27 @@ Returns:
EFI_INVALID_PARAMETER - The source data is corrupted
**/
+EFI_STATUS
+EfiGetInfo (
+ IN VOID *Source,
+ IN UINT32 SrcSize,
+ OUT UINT32 *DstSize,
+ OUT UINT32 *ScratchSize
+ );
+/**
+ The implementation of Efi Decompress().
+
+ @param Source The source buffer containing the compressed data.
+ @param SrcSize The size of source buffer
+ @param Destination The destination buffer to store the decompressed data
+ @param DstSize The size of destination buffer.
+ @param Scratch The buffer used internally by the decompress routine. This buffer is needed to store intermediate data.
+ @param ScratchSize The size of scratch buffer.
+
+ @retval EFI_SUCCESS Decompression is successful
+ @retval EFI_INVALID_PARAMETER The source data is corrupted
+**/
EFI_STATUS
EfiDecompress (
IN VOID *Source,
@@ -47,28 +60,18 @@ EfiDecompress (
IN OUT VOID *Scratch,
IN UINT32 ScratchSize
);
+
/**
+ The implementation Tiano Decompress GetInfo().
-Routine Description:
-
- The implementation of Efi Decompress().
-
-Arguments:
-
- Source - The source buffer containing the compressed data.
- SrcSize - The size of source buffer
- Destination - The destination buffer to store the decompressed data
- DstSize - The size of destination buffer.
- Scratch - The buffer used internally by the decompress routine. This buffer is needed to store intermediate data.
- ScratchSize - The size of scratch buffer.
-
-Returns:
-
- EFI_SUCCESS - Decompression is successful
- EFI_INVALID_PARAMETER - The source data is corrupted
+ @param Source The source buffer containing the compressed data.
+ @param SrcSize The size of source buffer
+ @param DstSize The size of destination buffer.
+ @param ScratchSize The size of scratch buffer.
+ @retval EFI_SUCCESS The size of destination buffer and the size of scratch buffer are successfully retrieved.
+ @retval EFI_INVALID_PARAMETER The source data is corrupted
**/
-
EFI_STATUS
TianoGetInfo (
IN VOID *Source,
@@ -76,26 +79,20 @@ TianoGetInfo (
OUT UINT32 *DstSize,
OUT UINT32 *ScratchSize
);
+
/**
+ The implementation of Tiano Decompress().
-Routine Description:
-
- The implementation Tiano Decompress GetInfo().
-
-Arguments:
-
- Source - The source buffer containing the compressed data.
- SrcSize - The size of source buffer
- DstSize - The size of destination buffer.
- ScratchSize - The size of scratch buffer.
-
-Returns:
-
- EFI_SUCCESS - The size of destination buffer and the size of scratch buffer are successfully retrieved.
- EFI_INVALID_PARAMETER - The source data is corrupted
+ @param Source The source buffer containing the compressed data.
+ @param SrcSize The size of source buffer
+ @param Destination The destination buffer to store the decompressed data
+ @param DstSize The size of destination buffer.
+ @param Scratch The buffer used internally by the decompress routine. This buffer is needed to store intermediate data.
+ @param ScratchSize The size of scratch buffer.
+ @retval EFI_SUCCESS Decompression is successful
+ @retval EFI_INVALID_PARAMETER The source data is corrupted
**/
-
EFI_STATUS
TianoDecompress (
IN VOID *Source,
@@ -105,27 +102,6 @@ TianoDecompress (
IN OUT VOID *Scratch,
IN UINT32 ScratchSize
);
-/**
-
-Routine Description:
-
- The implementation of Tiano Decompress().
-
-Arguments:
-
- Source - The source buffer containing the compressed data.
- SrcSize - The size of source buffer
- Destination - The destination buffer to store the decompressed data
- DstSize - The size of destination buffer.
- Scratch - The buffer used internally by the decompress routine. This buffer is needed to store intermediate data.
- ScratchSize - The size of scratch buffer.
-
-Returns:
-
- EFI_SUCCESS - Decompression is successful
- EFI_INVALID_PARAMETER - The source data is corrupted
-
-**/
typedef
EFI_STATUS
diff --git a/BaseTools/Source/C/Common/EfiCompress.c b/BaseTools/Source/C/Common/EfiCompress.c
index 4cbd49b5..913bef7c 100644
--- a/BaseTools/Source/C/Common/EfiCompress.c
+++ b/BaseTools/Source/C/Common/EfiCompress.c
@@ -250,6 +250,20 @@ STATIC NODE mPos, mMatchPos, mAvail, *mPosition, *mParent, *mPrev, *mNext = NU
// functions
//
+/**
+ The main compression routine.
+
+ @param SrcBuffer The buffer storing the source data
+ @param SrcSize The size of source data
+ @param DstBuffer The buffer to store the compressed data
+ @param DstSize On input, the size of DstBuffer; On output,
+ the size of the actual compressed data.
+
+ @retval EFI_BUFFER_TOO_SMALL The DstBuffer is too small. In this case,
+ DstSize contains the size needed.
+ @retval EFI_SUCCESS Compression is successful.
+
+**/
EFI_STATUS
EfiCompress (
IN UINT8 *SrcBuffer,
@@ -257,27 +271,6 @@ EfiCompress (
IN UINT8 *DstBuffer,
IN OUT UINT32 *DstSize
)
-/*++
-
-Routine Description:
-
- The main compression routine.
-
-Arguments:
-
- SrcBuffer - The buffer storing the source data
- SrcSize - The size of source data
- DstBuffer - The buffer to store the compressed data
- DstSize - On input, the size of DstBuffer; On output,
- the size of the actual compressed data.
-
-Returns:
-
- EFI_BUFFER_TOO_SMALL - The DstBuffer is too small. In this case,
- DstSize contains the size needed.
- EFI_SUCCESS - Compression is successful.
-
---*/
{
EFI_STATUS Status = EFI_SUCCESS;
@@ -345,24 +338,16 @@ Returns:
}
+/**
+ Put a dword to output stream
+
+ @param Data the dword to put
+**/
STATIC
VOID
PutDword(
IN UINT32 Data
)
-/*++
-
-Routine Description:
-
- Put a dword to output stream
-
-Arguments:
-
- Data - the dword to put
-
-Returns: (VOID)
-
---*/
{
if (mDst < mDstUpperLimit) {
*mDst++ = (UINT8)(((UINT8)(Data )) & 0xff);
@@ -381,23 +366,15 @@ Returns: (VOID)
}
}
+/**
+ Allocate memory spaces for data structures used in compression process
+
+ @retval EFI_SUCCESS Memory is allocated successfully
+ @retva; EFI_OUT_OF_RESOURCES Allocation fails
+**/
STATIC
EFI_STATUS
AllocateMemory ()
-/*++
-
-Routine Description:
-
- Allocate memory spaces for data structures used in compression process
-
-Arguments: (VOID)
-
-Returns:
-
- EFI_SUCCESS - Memory is allocated successfully
- EFI_OUT_OF_RESOURCES - Allocation fails
-
---*/
{
UINT32 i;
@@ -432,19 +409,11 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ Called when compression is completed to free memory previously allocated.
+**/
VOID
FreeMemory ()
-/*++
-
-Routine Description:
-
- Called when compression is completed to free memory previously allocated.
-
-Arguments: (VOID)
-
-Returns: (VOID)
-
---*/
{
if (mText) {
free (mText);
@@ -481,21 +450,12 @@ Returns: (VOID)
return;
}
-
+/**
+ Initialize String Info Log data structures
+**/
STATIC
VOID
InitSlide ()
-/*++
-
-Routine Description:
-
- Initialize String Info Log data structures
-
-Arguments: (VOID)
-
-Returns: (VOID)
-
---*/
{
NODE i;
@@ -517,29 +477,20 @@ Returns: (VOID)
}
}
+/**
+ Find child node given the parent node and the edge character
+ @param q the parent node
+ @param c the edge character
+
+ @return The child node (NIL if not found)
+**/
STATIC
NODE
Child (
IN NODE q,
IN UINT8 c
)
-/*++
-
-Routine Description:
-
- Find child node given the parent node and the edge character
-
-Arguments:
-
- q - the parent node
- c - the edge character
-
-Returns:
-
- The child node (NIL if not found)
-
---*/
{
NODE r;
@@ -552,6 +503,13 @@ Returns:
return r;
}
+/**
+ Create a new child for a given parent node.
+
+ @param q the parent node
+ @param c the edge character
+ @param r the child node
+**/
STATIC
VOID
MakeChild (
@@ -559,21 +517,6 @@ MakeChild (
IN UINT8 c,
IN NODE r
)
-/*++
-
-Routine Description:
-
- Create a new child for a given parent node.
-
-Arguments:
-
- q - the parent node
- c - the edge character
- r - the child node
-
-Returns: (VOID)
-
---*/
{
NODE h, t;
@@ -587,24 +530,16 @@ Returns: (VOID)
mChildCount[q]++;
}
+/**
+ Split a node.
+
+ @param Old the node to split
+**/
STATIC
VOID
Split (
NODE Old
)
-/*++
-
-Routine Description:
-
- Split a node.
-
-Arguments:
-
- Old - the node to split
-
-Returns: (VOID)
-
---*/
{
NODE New, t;
@@ -624,20 +559,12 @@ Returns: (VOID)
MakeChild(New, mText[mPos + mMatchLen], mPos);
}
+/**
+ Insert string info for current position into the String Info Log
+**/
STATIC
VOID
InsertNode ()
-/*++
-
-Routine Description:
-
- Insert string info for current position into the String Info Log
-
-Arguments: (VOID)
-
-Returns: (VOID)
-
---*/
{
NODE q, r, j, t;
UINT8 c, *t1, *t2;
@@ -739,21 +666,13 @@ Returns: (VOID)
}
+/**
+ Delete outdated string info. (The Usage of PERC_FLAG
+ ensures a clean deletion)
+**/
STATIC
VOID
DeleteNode ()
-/*++
-
-Routine Description:
-
- Delete outdated string info. (The Usage of PERC_FLAG
- ensures a clean deletion)
-
-Arguments: (VOID)
-
-Returns: (VOID)
-
---*/
{
NODE q, r, s, t, u;
@@ -813,21 +732,13 @@ Returns: (VOID)
mAvail = r;
}
+/**
+ Advance the current position (read in new data if needed).
+ Delete outdated string info. Find a match string for current position.
+**/
STATIC
VOID
GetNextMatch ()
-/*++
-
-Routine Description:
-
- Advance the current position (read in new data if needed).
- Delete outdated string info. Find a match string for current position.
-
-Arguments: (VOID)
-
-Returns: (VOID)
-
---*/
{
INT32 n;
@@ -842,23 +753,15 @@ Returns: (VOID)
InsertNode();
}
+/**
+ The main controlling routine for compression process.
+
+ @retval EFI_SUCCESS The compression is successful
+ @retval EFI_OUT_0F_RESOURCES Not enough memory for compression process
+**/
STATIC
EFI_STATUS
Encode ()
-/*++
-
-Routine Description:
-
- The main controlling routine for compression process.
-
-Arguments: (VOID)
-
-Returns:
-
- EFI_SUCCESS - The compression is successful
- EFI_OUT_0F_RESOURCES - Not enough memory for compression process
-
---*/
{
EFI_STATUS Status;
INT32 LastMatchLen;
@@ -920,20 +823,12 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ Count the frequencies for the Extra Set
+**/
STATIC
VOID
CountTFreq ()
-/*++
-
-Routine Description:
-
- Count the frequencies for the Extra Set
-
-Arguments: (VOID)
-
-Returns: (VOID)
-
---*/
{
INT32 i, k, n, Count;
@@ -969,6 +864,13 @@ Returns: (VOID)
}
}
+/**
+ Outputs the code length array for the Extra Set or the Position Set.
+
+ @param n the number of symbols
+ @param nbit the number of bits needed to represent 'n'
+ @param Special the special symbol that needs to be take care of
+**/
STATIC
VOID
WritePTLen (
@@ -976,21 +878,6 @@ WritePTLen (
IN INT32 nbit,
IN INT32 Special
)
-/*++
-
-Routine Description:
-
- Outputs the code length array for the Extra Set or the Position Set.
-
-Arguments:
-
- n - the number of symbols
- nbit - the number of bits needed to represent 'n'
- Special - the special symbol that needs to be take care of
-
-Returns: (VOID)
-
---*/
{
INT32 i, k;
@@ -1015,20 +902,12 @@ Returns: (VOID)
}
}
+/**
+ Outputs the code length array for Char&Length Set
+**/
STATIC
VOID
WriteCLen ()
-/*++
-
-Routine Description:
-
- Outputs the code length array for Char&Length Set
-
-Arguments: (VOID)
-
-Returns: (VOID)
-
---*/
{
INT32 i, k, n, Count;
@@ -1096,20 +975,12 @@ EncodeP (
}
}
+/**
+ Huffman code the block and output it.
+**/
STATIC
VOID
SendBlock ()
-/*++
-
-Routine Description:
-
- Huffman code the block and output it.
-
-Argument: (VOID)
-
-Returns: (VOID)
-
---*/
{
UINT32 i, k, Flags, Root, Pos, Size;
Flags = 0;
@@ -1164,27 +1035,18 @@ Returns: (VOID)
}
}
+/**
+ Outputs an Original Character or a Pointer
+ @param c The original character or the 'String Length' element of a Pointer
+ @param p The 'Position' field of a Pointer
+**/
STATIC
VOID
Output (
IN UINT32 c,
IN UINT32 p
)
-/*++
-
-Routine Description:
-
- Outputs an Original Character or a Pointer
-
-Arguments:
-
- c - The original character or the 'String Length' element of a Pointer
- p - The 'Position' field of a Pointer
-
-Returns: (VOID)
-
---*/
{
STATIC UINT32 CPos;
@@ -1263,26 +1125,18 @@ MakeCrcTable ()
}
}
+/**
+ Outputs rightmost n bits of x
+
+ @param n the rightmost n bits of the data is used
+ @param x the data
+**/
STATIC
VOID
PutBits (
IN INT32 n,
IN UINT32 x
)
-/*++
-
-Routine Description:
-
- Outputs rightmost n bits of x
-
-Arguments:
-
- n - the rightmost n bits of the data is used
- x - the data
-
-Returns: (VOID)
-
---*/
{
UINT8 Temp;
@@ -1311,28 +1165,20 @@ Returns: (VOID)
}
}
+/**
+ Read in source data
+
+ @param p the buffer to hold the data
+ @param n number of bytes to read
+
+ @return number of bytes actually read
+**/
STATIC
INT32
FreadCrc (
OUT UINT8 *p,
IN INT32 n
)
-/*++
-
-Routine Description:
-
- Read in source data
-
-Arguments:
-
- p - the buffer to hold the data
- n - number of bytes to read
-
-Returns:
-
- number of bytes actually read
-
---*/
{
INT32 i;
@@ -1358,24 +1204,16 @@ InitPutBits ()
mSubBitBuf = 0;
}
+/**
+ Count the number of each code length for a Huffman tree.
+
+ @param i the top node
+**/
STATIC
VOID
CountLen (
IN INT32 i
)
-/*++
-
-Routine Description:
-
- Count the number of each code length for a Huffman tree.
-
-Arguments:
-
- i - the top node
-
-Returns: (VOID)
-
---*/
{
STATIC INT32 Depth = 0;
@@ -1389,22 +1227,16 @@ Returns: (VOID)
}
}
+/**
+ Create code length array for a Huffman tree
+
+ @param Root the root of the tree
+**/
STATIC
VOID
MakeLen (
IN INT32 Root
)
-/*++
-
-Routine Description:
-
- Create code length array for a Huffman tree
-
-Arguments:
-
- Root - the root of the tree
-
---*/
{
INT32 i, k;
UINT32 Cum;
@@ -1468,6 +1300,13 @@ DownHeap (
mHeap[i] = (INT16)k;
}
+/**
+ Assign code to each symbol based on the code length array
+
+ @param n number of symbols
+ @param Len the code length array
+ @param Code stores codes for each symbol
+**/
STATIC
VOID
MakeCode (
@@ -1475,21 +1314,6 @@ MakeCode (
IN UINT8 Len[],
OUT UINT16 Code[]
)
-/*++
-
-Routine Description:
-
- Assign code to each symbol based on the code length array
-
-Arguments:
-
- n - number of symbols
- Len - the code length array
- Code - stores codes for each symbol
-
-Returns: (VOID)
-
---*/
{
INT32 i;
UINT16 Start[18];
@@ -1503,6 +1327,16 @@ Returns: (VOID)
}
}
+/**
+ Generates Huffman codes given a frequency distribution of symbols
+
+ @param NParm number of symbols
+ @param FreqParm frequency of each symbol
+ @param LenParm code length for each symbol
+ @param CodeParm code for each symbol
+
+ @return Root of the Huffman tree.
+**/
STATIC
INT32
MakeTree (
@@ -1511,24 +1345,6 @@ MakeTree (
OUT UINT8 LenParm[],
OUT UINT16 CodeParm[]
)
-/*++
-
-Routine Description:
-
- Generates Huffman codes given a frequency distribution of symbols
-
-Arguments:
-
- NParm - number of symbols
- FreqParm - frequency of each symbol
- LenParm - code length for each symbol
- CodeParm - code for each symbol
-
-Returns:
-
- Root of the Huffman tree.
-
---*/
{
INT32 i, j, k, Avail;
diff --git a/BaseTools/Source/C/Common/EfiUtilityMsgs.c b/BaseTools/Source/C/Common/EfiUtilityMsgs.c
index 69b9f899..a40ad93c 100755
--- a/BaseTools/Source/C/Common/EfiUtilityMsgs.c
+++ b/BaseTools/Source/C/Common/EfiUtilityMsgs.c
@@ -36,6 +36,50 @@ PrintLimitExceeded (
VOID
);
+/**
+ Prints an error message.
+
+ All arguments are optional, though the printed message may be useless if
+ at least something valid is not specified.
+
+ @note:
+ We print the following (similar to the Warn() and Debug()
+ W
+ Typical error/warning message format:
+
+ bin\VfrCompile.cpp(330) : error C2660: 'AddVfrDataStructField' : function does not take 2 parameters
+
+ BUGBUG -- these three utility functions are almost identical, and
+ should be modified to share code.
+
+ Visual Studio does not find error messages with:
+
+ " error :"
+ " error 1:"
+ " error c1:"
+ " error 1000:"
+ " error c100:"
+
+ It does find:
+ " error c1000:"
+
+ @param FileName name of the file or application. If not specified, then the
+ utility name (as set by the utility calling SetUtilityName()
+ earlier) is used. Otherwise "Unknown utility" is used.
+
+ @param LineNumber the line number of error, typically used by parsers. If the
+ utility is not a parser, then 0 should be specified. Otherwise
+ the FileName and LineNumber info can be used to cause
+ MS Visual Studio to jump to the error.
+
+ @param MessageCode an application-specific error code that can be referenced in
+ other documentation.
+
+ @param Text the text in question, typically used by parsers.
+
+ @param MsgFmt the format string for the error message. Can contain formatting
+ controls for use with the varargs.
+**/
VOID
Error (
CHAR8 *FileName,
@@ -45,56 +89,6 @@ Error (
CHAR8 *MsgFmt,
...
)
-/*++
-
-Routine Description:
- Prints an error message.
-
-Arguments:
- All arguments are optional, though the printed message may be useless if
- at least something valid is not specified.
-
- FileName - name of the file or application. If not specified, then the
- utility name (as set by the utility calling SetUtilityName()
- earlier) is used. Otherwise "Unknown utility" is used.
-
- LineNumber - the line number of error, typically used by parsers. If the
- utility is not a parser, then 0 should be specified. Otherwise
- the FileName and LineNumber info can be used to cause
- MS Visual Studio to jump to the error.
-
- MessageCode - an application-specific error code that can be referenced in
- other documentation.
-
- Text - the text in question, typically used by parsers.
-
- MsgFmt - the format string for the error message. Can contain formatting
- controls for use with the varargs.
-
-Returns:
- None.
-
-Notes:
- We print the following (similar to the Warn() and Debug()
- W
- Typical error/warning message format:
-
- bin\VfrCompile.cpp(330) : error C2660: 'AddVfrDataStructField' : function does not take 2 parameters
-
- BUGBUG -- these three utility functions are almost identical, and
- should be modified to share code.
-
- Visual Studio does not find error messages with:
-
- " error :"
- " error 1:"
- " error c1:"
- " error 1000:"
- " error c100:"
-
- It does find:
- " error c1000:"
---*/
{
va_list List;
//
@@ -127,6 +121,14 @@ Notes:
va_end (List);
}
+/**
+ Print a parser error, using the source file name and line number
+ set by a previous call to SetParserPosition().
+
+ @param MessageCode application-specific error code
+ @param Text text to print in the error message
+ @param MsgFmt format string to print at the end of the error message
+**/
VOID
ParserError (
UINT32 MessageCode,
@@ -134,21 +136,6 @@ ParserError (
CHAR8 *MsgFmt,
...
)
-/*++
-
-Routine Description:
- Print a parser error, using the source file name and line number
- set by a previous call to SetParserPosition().
-
-Arguments:
- MessageCode - application-specific error code
- Text - text to print in the error message
- MsgFmt - format string to print at the end of the error message
-
-Returns:
- NA
-
---*/
{
va_list List;
//
@@ -181,6 +168,14 @@ Returns:
va_end (List);
}
+/**
+ Print a parser warning, using the source file name and line number
+ set by a previous call to SetParserPosition().
+
+ @param ErrorCode application-specific error code
+ @param OffendingText text to print in the warning message
+ @param MsgFmt format string to print at the end of the warning message
+**/
VOID
ParserWarning (
UINT32 ErrorCode,
@@ -188,21 +183,6 @@ ParserWarning (
CHAR8 *MsgFmt,
...
)
-/*++
-
-Routine Description:
- Print a parser warning, using the source file name and line number
- set by a previous call to SetParserPosition().
-
-Arguments:
- ErrorCode - application-specific error code
- OffendingText - text to print in the warning message
- MsgFmt - format string to print at the end of the warning message
-
-Returns:
- NA
-
---*/
{
va_list List;
//
@@ -241,6 +221,19 @@ Returns:
// }
}
+/**
+ Print a warning message.
+
+ @param FileName name of the file where the warning was detected, or the name
+ of the application that detected the warning
+ @param LineNumber the line number where the warning was detected (parsers).
+ 0 should be specified if the utility is not a parser.
+ @param MessageCode an application-specific warning code that can be referenced in
+ other documentation.
+ @param Text the text in question (parsers)
+ @param MsgFmt the format string for the warning message. Can contain formatting
+ controls for use with varargs.
+**/
VOID
Warning (
CHAR8 *FileName,
@@ -250,30 +243,6 @@ Warning (
CHAR8 *MsgFmt,
...
)
-/*++
-
-Routine Description:
- Print a warning message.
-
-Arguments:
- FileName - name of the file where the warning was detected, or the name
- of the application that detected the warning
-
- LineNumber - the line number where the warning was detected (parsers).
- 0 should be specified if the utility is not a parser.
-
- MessageCode - an application-specific warning code that can be referenced in
- other documentation.
-
- Text - the text in question (parsers)
-
- MsgFmt - the format string for the warning message. Can contain formatting
- controls for use with varargs.
-
-Returns:
- None.
-
---*/
{
va_list List;
@@ -313,6 +282,18 @@ Returns:
va_end (List);
}
+/**
+ Print a Debug message.
+
+ @param FileName typically the name of the utility printing the debug message, but
+ can be the name of a file being parsed.
+ @param LineNumber the line number in FileName (parsers)
+ @param MsgLevel Debug message print level (0~9)
+ @param Text the text in question (parsers)
+ @param MsgFmt the format string for the debug message. Can contain formatting
+ controls for use with varargs.
+
+**/
VOID
DebugMsg (
CHAR8 *FileName,
@@ -322,28 +303,6 @@ DebugMsg (
CHAR8 *MsgFmt,
...
)
-/*++
-
-Routine Description:
- Print a Debug message.
-
-Arguments:
- FileName - typically the name of the utility printing the debug message, but
- can be the name of a file being parsed.
-
- LineNumber - the line number in FileName (parsers)
-
- MsgLevel - Debug message print level (0~9)
-
- Text - the text in question (parsers)
-
- MsgFmt - the format string for the debug message. Can contain formatting
- controls for use with varargs.
-
-Returns:
- None.
-
---*/
{
va_list List;
//
@@ -358,6 +317,42 @@ Returns:
va_end (List);
}
+/**
+ Worker routine for all the utility printing services. Prints the message in
+ a format that Visual Studio will find when scanning build outputs for
+ errors or warnings.
+
+ @note:
+ If FileName == NULL then this utility will use the string passed into SetUtilityName().
+
+ LineNumber is only used if the caller is a parser, in which case FileName refers to the
+ file being parsed.
+
+ Text and MsgFmt are both optional, though it would be of little use calling this function with
+ them both NULL.
+
+ Output will typically be of the form:
+ () : : :
+
+ Parser (LineNumber != 0)
+ VfrCompile.cpp(330) : error E2660: AddVfrDataStructField : function does not take 2 parameters
+ Generic utility (LineNumber == 0)
+ UtilityName : error E1234 : Text string : MsgFmt string and args
+
+ @param Type "warning" or "error" string to insert into the message to be
+ printed. The first character of this string (converted to uppercase)
+ is used to precede the MessageCode value in the output string.
+ @param FileName name of the file where the warning was detected, or the name
+ of the application that detected the warning
+ @param LineNumber the line number where the warning was detected (parsers).
+ 0 should be specified if the utility is not a parser.
+ @param MessageCode an application-specific warning code that can be referenced in
+ other documentation.
+ @param Text part of the message to print
+ @param MsgFmt the format string for the message. Can contain formatting
+ controls for use with varargs.
+ @param List the variable list.
+**/
VOID
PrintMessage (
CHAR8 *Type,
@@ -368,54 +363,6 @@ PrintMessage (
CHAR8 *MsgFmt,
va_list List
)
-/*++
-
-Routine Description:
- Worker routine for all the utility printing services. Prints the message in
- a format that Visual Studio will find when scanning build outputs for
- errors or warnings.
-
-Arguments:
- Type - "warning" or "error" string to insert into the message to be
- printed. The first character of this string (converted to uppercase)
- is used to precede the MessageCode value in the output string.
-
- FileName - name of the file where the warning was detected, or the name
- of the application that detected the warning
-
- LineNumber - the line number where the warning was detected (parsers).
- 0 should be specified if the utility is not a parser.
-
- MessageCode - an application-specific warning code that can be referenced in
- other documentation.
-
- Text - part of the message to print
-
- MsgFmt - the format string for the message. Can contain formatting
- controls for use with varargs.
- List - the variable list.
-
-Returns:
- None.
-
-Notes:
- If FileName == NULL then this utility will use the string passed into SetUtilityName().
-
- LineNumber is only used if the caller is a parser, in which case FileName refers to the
- file being parsed.
-
- Text and MsgFmt are both optional, though it would be of little use calling this function with
- them both NULL.
-
- Output will typically be of the form:
- () : : :
-
- Parser (LineNumber != 0)
- VfrCompile.cpp(330) : error E2660: AddVfrDataStructField : function does not take 2 parameters
- Generic utility (LineNumber == 0)
- UtilityName : error E1234 : Text string : MsgFmt string and args
-
---*/
{
CHAR8 Line[MAX_LINE_LEN];
CHAR8 Line2[MAX_LINE_LEN];
@@ -523,24 +470,19 @@ Notes:
}
+/**
+ Print message into stdout.
+
+ @param MsgFmt the format string for the message. Can contain formatting
+ controls for use with varargs.
+ @param List the variable list.
+**/
STATIC
VOID
PrintSimpleMessage (
CHAR8 *MsgFmt,
va_list List
)
-/*++
-Routine Description:
- Print message into stdout.
-
-Arguments:
- MsgFmt - the format string for the message. Can contain formatting
- controls for use with varargs.
- List - the variable list.
-
-Returns:
- None.
---*/
{
CHAR8 Line[MAX_LINE_LEN];
//
@@ -552,51 +494,37 @@ Returns:
}
}
+/**
+ Set the position in a file being parsed. This can be used to
+ print error messages deeper down in a parser.
+
+ @param SourceFileName name of the source file being parsed
+ @param LineNum line number of the source file being parsed
+**/
VOID
ParserSetPosition (
CHAR8 *SourceFileName,
UINT32 LineNum
)
-/*++
-
-Routine Description:
- Set the position in a file being parsed. This can be used to
- print error messages deeper down in a parser.
-
-Arguments:
- SourceFileName - name of the source file being parsed
- LineNum - line number of the source file being parsed
-
-Returns:
- NA
-
---*/
{
mSourceFileName = SourceFileName;
mSourceFileLineNum = LineNum;
}
-VOID
-SetUtilityName (
- CHAR8 *UtilityName
- )
-/*++
-
-Routine Description:
+/**
All printed error/warning/debug messages follow the same format, and
typically will print a filename or utility name followed by the error
text. However if a filename is not passed to the print routines, then
they'll print the utility name if you call this function early in your
app to set the utility name.
-Arguments:
- UtilityName - name of the utility, which will be printed with all
- error/warning/debug messages.
-
-Returns:
- NA
-
---*/
+ @param UtilityName name of the utility, which will be printed with all
+ error/warning/debug messages.
+**/
+VOID
+SetUtilityName (
+ CHAR8 *UtilityName
+ )
{
//
// Save the name of the utility in our local variable. Make sure its
@@ -613,69 +541,48 @@ Returns:
}
}
-STATUS
-GetUtilityStatus (
- VOID
- )
-/*++
-
-Routine Description:
+/**
When you call Error() or Warning(), this module keeps track of it and
sets a local mStatus to STATUS_ERROR or STATUS_WARNING. When the utility
exits, it can call this function to get the status and use it as a return
value.
-Arguments:
- None.
-
-Returns:
- Worst-case status reported, as defined by which print function was called.
-
---*/
+ @return Worst-case status reported, as defined by which print function was called.
+**/
+STATUS
+GetUtilityStatus (
+ VOID
+ )
{
return mStatus;
}
+/**
+ Set the printing message Level. This is used by the PrintMsg() function
+ to determine when/if a message should be printed.
+
+ @param LogLevel 0~50 to specify the different level message.
+**/
VOID
SetPrintLevel (
UINT64 LogLevel
)
-/*++
-
-Routine Description:
- Set the printing message Level. This is used by the PrintMsg() function
- to determine when/if a message should be printed.
-
-Arguments:
- LogLevel - 0~50 to specify the different level message.
-
-Returns:
- NA
-
---*/
{
mPrintLogLevel = LogLevel;
}
+/**
+ Print a verbose level message.
+
+ @param MsgFmt the format string for the message. Can contain formatting
+ controls for use with varargs.
+ @param List the variable list.
+**/
VOID
VerboseMsg (
CHAR8 *MsgFmt,
...
)
-/*++
-
-Routine Description:
- Print a verbose level message.
-
-Arguments:
- MsgFmt - the format string for the message. Can contain formatting
- controls for use with varargs.
- List - the variable list.
-
-Returns:
- NA
-
---*/
{
va_list List;
//
@@ -690,25 +597,18 @@ Returns:
va_end (List);
}
+/**
+ Print a default level message.
+
+ @param MsgFmt the format string for the message. Can contain formatting
+ controls for use with varargs.
+ @param List the variable list.
+**/
VOID
NormalMsg (
CHAR8 *MsgFmt,
...
)
-/*++
-
-Routine Description:
- Print a default level message.
-
-Arguments:
- MsgFmt - the format string for the message. Can contain formatting
- controls for use with varargs.
- List - the variable list.
-
-Returns:
- NA
-
---*/
{
va_list List;
//
@@ -723,25 +623,18 @@ Returns:
va_end (List);
}
+/**
+ Print a key level message.
+
+ @param MsgFmt the format string for the message. Can contain formatting
+ controls for use with varargs.
+ @param List the variable list.
+**/
VOID
KeyMsg (
CHAR8 *MsgFmt,
...
)
-/*++
-
-Routine Description:
- Print a key level message.
-
-Arguments:
- MsgFmt - the format string for the message. Can contain formatting
- controls for use with varargs.
- List - the variable list.
-
-Returns:
- NA
-
---*/
{
va_list List;
//
@@ -756,28 +649,21 @@ Returns:
va_end (List);
}
+/**
+ Set the limits of how many errors, warnings, and errors+warnings
+ we will print.
+
+ @param MaxErrors maximum number of error messages to print
+ @param MaxWarnings maximum number of warning messages to print
+ @param MaxWarningsPlusErrors
+ maximum number of errors+warnings to print
+**/
VOID
SetPrintLimits (
UINT32 MaxErrors,
UINT32 MaxWarnings,
UINT32 MaxWarningsPlusErrors
)
-/*++
-
-Routine Description:
- Set the limits of how many errors, warnings, and errors+warnings
- we will print.
-
-Arguments:
- MaxErrors - maximum number of error messages to print
- MaxWarnings - maximum number of warning messages to print
- MaxWarningsPlusErrors
- - maximum number of errors+warnings to print
-
-Returns:
- NA
-
---*/
{
mMaxErrors = MaxErrors;
mMaxWarnings = MaxWarnings;
diff --git a/BaseTools/Source/C/Common/FirmwareVolumeBuffer.c b/BaseTools/Source/C/Common/FirmwareVolumeBuffer.c
index fcf62e70..f8f117bc 100644
--- a/BaseTools/Source/C/Common/FirmwareVolumeBuffer.c
+++ b/BaseTools/Source/C/Common/FirmwareVolumeBuffer.c
@@ -78,29 +78,21 @@ FvBufCalculateChecksum8 (
// Procedures start
//
+/**
+ Clears out all files from the Fv buffer in memory
+
+ @param SourceFv Address of the Fv in memory, this firmware volume will
+ be modified, if SourceFfsFile exists
+ @param SourceFfsFile Input FFS file to replace
+
+ @retval EFI_SUCCESS
+ @retval EFI_NOT_FOUND
+**/
EFI_STATUS
FvBufRemoveFileNew (
IN OUT VOID *Fv,
IN EFI_GUID *Name
)
-/*++
-
-Routine Description:
-
- Clears out all files from the Fv buffer in memory
-
-Arguments:
-
- SourceFv - Address of the Fv in memory, this firmware volume volume will
- be modified, if SourceFfsFile exists
- SourceFfsFile - Input FFS file to replace
-
-Returns:
-
- EFI_SUCCESS
- EFI_NOT_FOUND
-
---*/
{
EFI_STATUS Status;
EFI_FFS_FILE_HEADER* FileToRm;
@@ -127,30 +119,21 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ Clears out all files from the Fv buffer in memory
+ @param SourceFv Address of the Fv in memory, this firmware volume will
+ be modified, if SourceFfsFile exists
+ @param SourceFfsFile Input FFS file to replace
+
+ @retval EFI_SUCCESS
+ @retval EFI_NOT_FOUND
+**/
EFI_STATUS
FvBufRemoveFile (
IN OUT VOID *Fv,
IN EFI_GUID *Name
)
-/*++
-
-Routine Description:
-
- Clears out all files from the Fv buffer in memory
-
-Arguments:
-
- SourceFv - Address of the Fv in memory, this firmware volume volume will
- be modified, if SourceFfsFile exists
- SourceFfsFile - Input FFS file to replace
-
-Returns:
-
- EFI_SUCCESS
- EFI_NOT_FOUND
-
---*/
{
EFI_STATUS Status;
EFI_FFS_FILE_HEADER *NextFile;
@@ -216,27 +199,18 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ Clears out all files from the Fv buffer in memory
+ @param SourceFfsFile Input FFS file to update the checksum for
+
+ @retval EFI_SUCCESS
+ @retval EFI_NOT_FOUND
+**/
EFI_STATUS
FvBufChecksumFile (
IN OUT VOID *FfsFile
)
-/*++
-
-Routine Description:
-
- Clears out all files from the Fv buffer in memory
-
-Arguments:
-
- SourceFfsFile - Input FFS file to update the checksum for
-
-Returns:
-
- EFI_SUCCESS
- EFI_NOT_FOUND
-
---*/
{
EFI_FFS_FILE_HEADER* File = (EFI_FFS_FILE_HEADER*)FfsFile;
EFI_FFS_FILE_STATE StateBackup;
@@ -272,29 +246,20 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ Clears out all files from the Fv buffer in memory
+ @param SourceFv Address of the Fv in memory, this firmware volume will
+ be modified, if SourceFfsFile exists
+ @param SourceFfsFile Input FFS file to replace
+
+ @retval EFI_SUCCESS
+ @retval EFI_NOT_FOUND
+**/
EFI_STATUS
FvBufChecksumHeader (
IN OUT VOID *Fv
)
-/*++
-
-Routine Description:
-
- Clears out all files from the Fv buffer in memory
-
-Arguments:
-
- SourceFv - Address of the Fv in memory, this firmware volume volume will
- be modified, if SourceFfsFile exists
- SourceFfsFile - Input FFS file to replace
-
-Returns:
-
- EFI_SUCCESS
- EFI_NOT_FOUND
-
---*/
{
EFI_FIRMWARE_VOLUME_HEADER* FvHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Fv;
@@ -308,31 +273,22 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ Clears out all files from the Fv buffer in memory
+ @param SourceFv - Address of the Fv in memory
+ @param DestinationFv - Output for destination Fv
+ DestinationFv == NULL - invalid parameter
+ *DestinationFv == NULL - memory will be allocated
+ *DestinationFv != NULL - this address will be the destination
+
+ @retval EFI_SUCCESS
+**/
EFI_STATUS
FvBufDuplicate (
IN VOID *SourceFv,
IN OUT VOID **DestinationFv
)
-/*++
-
-Routine Description:
-
- Clears out all files from the Fv buffer in memory
-
-Arguments:
-
- SourceFv - Address of the Fv in memory
- DestinationFv - Output for destination Fv
- DestinationFv == NULL - invalid parameter
- *DestinationFv == NULL - memory will be allocated
- *DestinationFv != NULL - this address will be the destination
-
-Returns:
-
- EFI_SUCCESS
-
---*/
{
EFI_STATUS Status;
UINTN size;
@@ -358,35 +314,26 @@ Returns:
return EFI_SUCCESS;
}
-
-EFI_STATUS
-FvBufExtend (
- IN VOID **Fv,
- IN UINTN Size
- )
-/*++
-
-Routine Description:
-
+/**
Extends a firmware volume by the given number of bytes.
BUGBUG: Does not handle the case where the firmware volume has a
VTF (Volume Top File). The VTF will not be moved to the
end of the extended FV.
-Arguments:
+ @param Fv Source and destination firmware volume.
+ Note: The original firmware volume buffer is freed!
- Fv - Source and destination firmware volume.
- Note: The original firmware volume buffer is freed!
+ @param Size The minimum size that the firmware volume is to be extended by.
+ The FV may be extended more than this size.
- Size - The minimum size that the firmware volume is to be extended by.
- The FV may be extended more than this size.
-
-Returns:
-
- EFI_SUCCESS
-
---*/
+ @retval EFI_SUCCESS
+**/
+EFI_STATUS
+FvBufExtend (
+ IN VOID **Fv,
+ IN UINTN Size
+ )
{
EFI_STATUS Status;
UINTN OldSize;
@@ -469,27 +416,17 @@ Returns:
}
+/**
+ Clears out all files from the Fv buffer in memory
+ @param Fv Address of the Fv in memory
+
+ @retval EFI_SUCCESS
+**/
EFI_STATUS
FvBufClearAllFiles (
IN OUT VOID *Fv
)
-/*++
-
-Routine Description:
-
- Clears out all files from the Fv buffer in memory
-
-Arguments:
-
- Fv - Address of the Fv in memory
-
-Returns:
-
- EFI_SUCCESS
-
---*/
-
{
EFI_FIRMWARE_VOLUME_HEADER *hdr = (EFI_FIRMWARE_VOLUME_HEADER*)Fv;
EFI_STATUS Status;
@@ -509,28 +446,18 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ Clears out all files from the Fv buffer in memory
+ @param Fv Address of the Fv in memory
+
+ @retval EFI_SUCCESS
+**/
EFI_STATUS
FvBufGetSize (
IN VOID *Fv,
OUT UINTN *Size
)
-/*++
-
-Routine Description:
-
- Clears out all files from the Fv buffer in memory
-
-Arguments:
-
- Fv - Address of the Fv in memory
-
-Returns:
-
- EFI_SUCCESS
-
---*/
-
{
EFI_FIRMWARE_VOLUME_HEADER *hdr = (EFI_FIRMWARE_VOLUME_HEADER*)Fv;
EFI_FV_BLOCK_MAP_ENTRY *blk = hdr->BlockMap;
@@ -554,28 +481,19 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ Adds a new FFS file
+ @param Fv Address of the Fv in memory
+ @param File FFS file to add to Fv
+
+ @retval EFI_SUCCESS
+**/
EFI_STATUS
FvBufAddFile (
IN OUT VOID *Fv,
IN VOID *File
)
-/*++
-
-Routine Description:
-
- Adds a new FFS file
-
-Arguments:
-
- Fv - Address of the Fv in memory
- File - FFS file to add to Fv
-
-Returns:
-
- EFI_SUCCESS
-
---*/
{
EFI_FIRMWARE_VOLUME_HEADER *hdr = (EFI_FIRMWARE_VOLUME_HEADER*)Fv;
@@ -652,32 +570,23 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ Adds a new FFS file. Extends the firmware volume if needed.
+ @param Fv Source and destination firmware volume.
+ Note: If the FV is extended, then the original firmware volume
+ buffer is freed!
+
+ @param Size The minimum size that the firmware volume is to be extended by.
+ The FV may be extended more than this size.
+
+ @retval EFI_SUCCESS
+**/
EFI_STATUS
FvBufAddFileWithExtend (
IN OUT VOID **Fv,
IN VOID *File
)
-/*++
-
-Routine Description:
-
- Adds a new FFS file. Extends the firmware volume if needed.
-
-Arguments:
-
- Fv - Source and destination firmware volume.
- Note: If the FV is extended, then the original firmware volume
- buffer is freed!
-
- Size - The minimum size that the firmware volume is to be extended by.
- The FV may be extended more than this size.
-
-Returns:
-
- EFI_SUCCESS
-
---*/
{
EFI_STATUS Status;
EFI_FFS_FILE_HEADER* NewFile;
@@ -706,29 +615,20 @@ Returns:
return Status;
}
+/**
+ Adds a new FFS VFT (Volume Top File) file. In other words, adds the
+ file to the end of the firmware volume.
+ @param Fv Address of the Fv in memory
+ @param File FFS file to add to Fv
+
+ @retval EFI_SUCCESS
+**/
EFI_STATUS
FvBufAddVtfFile (
IN OUT VOID *Fv,
IN VOID *File
)
-/*++
-
-Routine Description:
-
- Adds a new FFS VFT (Volume Top File) file. In other words, adds the
- file to the end of the firmware volume.
-
-Arguments:
-
- Fv - Address of the Fv in memory
- File - FFS file to add to Fv
-
-Returns:
-
- EFI_SUCCESS
-
---*/
{
EFI_STATUS Status;
@@ -811,52 +711,35 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ Expands the 3 byte size commonly used in Firmware Volume data structures
+ @param Size Address of the 3 byte array representing the size
+
+ @return UINT32
+**/
VOID
FvBufCompact3ByteSize (
OUT VOID* SizeDest,
IN UINT32 Size
)
-/*++
-
-Routine Description:
-
- Expands the 3 byte size commonly used in Firmware Volume data structures
-
-Arguments:
-
- Size - Address of the 3 byte array representing the size
-
-Returns:
-
- UINT32
-
---*/
{
((UINT8*)SizeDest)[0] = (UINT8)Size;
((UINT8*)SizeDest)[1] = (UINT8)(Size >> 8);
((UINT8*)SizeDest)[2] = (UINT8)(Size >> 16);
}
+/**
+ Get the FFS file size.
+
+ @param Ffs Pointer to FFS header
+
+ @return UINT32
+**/
UINT32
FvBufGetFfsFileSize (
IN EFI_FFS_FILE_HEADER *Ffs
)
-/*++
-
-Routine Description:
-
- Get the FFS file size.
-
-Arguments:
-
- Ffs - Pointer to FFS header
-
-Returns:
-
- UINT32
-
---*/
{
if (Ffs == NULL) {
return 0;
@@ -867,25 +750,17 @@ Returns:
return FvBufExpand3ByteSize(Ffs->Size);
}
+/**
+ Get the FFS header size.
+
+ @param Ffs Pointer to FFS header
+
+ @return UINT32
+**/
UINT32
FvBufGetFfsHeaderSize (
IN EFI_FFS_FILE_HEADER *Ffs
)
-/*++
-
-Routine Description:
-
- Get the FFS header size.
-
-Arguments:
-
- Ffs - Pointer to FFS header
-
-Returns:
-
- UINT32
-
---*/
{
if (Ffs == NULL) {
return 0;
@@ -896,60 +771,44 @@ Returns:
return sizeof(EFI_FFS_FILE_HEADER);
}
+/**
+ Expands the 3 byte size commonly used in Firmware Volume data structures
+
+ @param Size Address of the 3 byte array representing the size
+
+ @return UINT32
+**/
UINT32
FvBufExpand3ByteSize (
IN VOID* Size
)
-/*++
-
-Routine Description:
-
- Expands the 3 byte size commonly used in Firmware Volume data structures
-
-Arguments:
-
- Size - Address of the 3 byte array representing the size
-
-Returns:
-
- UINT32
-
---*/
{
return (((UINT8*)Size)[2] << 16) +
(((UINT8*)Size)[1] << 8) +
((UINT8*)Size)[0];
}
+/**
+ Iterates through the files contained within the firmware volume
+
+ @param Fv Address of the Fv in memory
+ @param Key Should be 0 to get the first file. After that, it should be
+ passed back in without modifying its contents to retrieve
+ subsequent files.
+ @param File Output file pointer
+ File == NULL - invalid parameter
+ otherwise - *File will be update to the location of the file
+
+ @retval EFI_SUCCESS
+ @retval EFI_NOT_FOUND
+ @retval EFI_VOLUME_CORRUPTED
+**/
EFI_STATUS
FvBufFindNextFile (
IN VOID *Fv,
IN OUT UINTN *Key,
OUT VOID **File
)
-/*++
-
-Routine Description:
-
- Iterates through the files contained within the firmware volume
-
-Arguments:
-
- Fv - Address of the Fv in memory
- Key - Should be 0 to get the first file. After that, it should be
- passed back in without modifying its contents to retrieve
- subsequent files.
- File - Output file pointer
- File == NULL - invalid parameter
- otherwise - *File will be update to the location of the file
-
-Returns:
-
- EFI_SUCCESS
- EFI_NOT_FOUND
- EFI_VOLUME_CORRUPTED
-
---*/
{
EFI_FIRMWARE_VOLUME_HEADER *hdr = (EFI_FIRMWARE_VOLUME_HEADER*)Fv;
@@ -1028,35 +887,26 @@ Returns:
return EFI_NOT_FOUND;
}
+/**
+ Searches the Fv for a file by its name
+ @param Fv Address of the Fv in memory
+ @param Name Guid filename to search for in the firmware volume
+ @param File Output file pointer
+ File == NULL - Only determine if the file exists, based on return
+ value from the function call.
+ otherwise - *File will be update to the location of the file
+
+ @retval EFI_SUCCESS
+ @retval EFI_NOT_FOUND
+ @retval EFI_VOLUME_CORRUPTED
+**/
EFI_STATUS
FvBufFindFileByName (
IN VOID *Fv,
IN EFI_GUID *Name,
OUT VOID **File
)
-/*++
-
-Routine Description:
-
- Searches the Fv for a file by its name
-
-Arguments:
-
- Fv - Address of the Fv in memory
- Name - Guid filename to search for in the firmware volume
- File - Output file pointer
- File == NULL - Only determine if the file exists, based on return
- value from the function call.
- otherwise - *File will be update to the location of the file
-
-Returns:
-
- EFI_SUCCESS
- EFI_NOT_FOUND
- EFI_VOLUME_CORRUPTED
-
---*/
{
EFI_STATUS Status;
UINTN Key;
@@ -1080,35 +930,26 @@ Returns:
return EFI_NOT_FOUND;
}
+/**
+ Searches the Fv for a file by its type
+ @param Fv Address of the Fv in memory
+ @param Type FFS FILE type to search for
+ @param File Output file pointer
+ (File == NULL) -> Only determine if the file exists, based on return
+ value from the function call.
+ otherwise -> *File will be update to the location of the file
+
+ @retval EFI_SUCCESS
+ @retval EFI_NOT_FOUND
+ @retval EFI_VOLUME_CORRUPTED
+**/
EFI_STATUS
FvBufFindFileByType (
IN VOID *Fv,
IN EFI_FV_FILETYPE Type,
OUT VOID **File
)
-/*++
-
-Routine Description:
-
- Searches the Fv for a file by its type
-
-Arguments:
-
- Fv - Address of the Fv in memory
- Type - FFS FILE type to search for
- File - Output file pointer
- (File == NULL) -> Only determine if the file exists, based on return
- value from the function call.
- otherwise -> *File will be update to the location of the file
-
-Returns:
-
- EFI_SUCCESS
- EFI_NOT_FOUND
- EFI_VOLUME_CORRUPTED
-
---*/
{
EFI_STATUS Status;
UINTN Key;
@@ -1132,34 +973,25 @@ Returns:
return EFI_NOT_FOUND;
}
+/**
+ Searches the requested file for raw data.
+ This routine either returns all the payload of a EFI_FV_FILETYPE_RAW file,
+ or finds the EFI_SECTION_RAW section within the file and returns its data.
+
+ @param FfsFile Address of the FFS file in memory
+ @param RawData Pointer to the raw data within the file
+ (This is NOT allocated. It is within the file.)
+ @param RawDataSize Size of the raw data within the file
+
+ @return EFI_STATUS
+**/
EFI_STATUS
FvBufGetFileRawData (
IN VOID* FfsFile,
OUT VOID** RawData,
OUT UINTN* RawDataSize
)
-/*++
-
-Routine Description:
-
- Searches the requested file for raw data.
-
- This routine either returns all the payload of a EFI_FV_FILETYPE_RAW file,
- or finds the EFI_SECTION_RAW section within the file and returns its data.
-
-Arguments:
-
- FfsFile - Address of the FFS file in memory
- RawData - Pointer to the raw data within the file
- (This is NOT allocated. It is within the file.)
- RawDataSize - Size of the raw data within the file
-
-Returns:
-
- EFI_STATUS
-
---*/
{
EFI_STATUS Status;
EFI_FFS_FILE_HEADER* File;
@@ -1195,7 +1027,19 @@ Returns:
}
+/**
+ Packages up a FFS file containing the input raw data.
+ The file created will have a type of EFI_FV_FILETYPE_FREEFORM, and will
+ contain one EFI_FV_FILETYPE_RAW section.
+
+ @param RawData Pointer to the raw data to be packed
+ @param RawDataSize Size of the raw data to be packed
+ @param FfsFile Address of the packaged FFS file.
+ Note: The called must deallocate this memory!
+
+ @return EFI_STATUS
+**/
EFI_STATUS
FvBufPackageFreeformRawFile (
IN EFI_GUID* Filename,
@@ -1203,27 +1047,6 @@ FvBufPackageFreeformRawFile (
IN UINTN RawDataSize,
OUT VOID** FfsFile
)
-/*++
-
-Routine Description:
-
- Packages up a FFS file containing the input raw data.
-
- The file created will have a type of EFI_FV_FILETYPE_FREEFORM, and will
- contain one EFI_FV_FILETYPE_RAW section.
-
-Arguments:
-
- RawData - Pointer to the raw data to be packed
- RawDataSize - Size of the raw data to be packed
- FfsFile - Address of the packaged FFS file.
- Note: The called must deallocate this memory!
-
-Returns:
-
- EFI_STATUS
-
---*/
{
EFI_FFS_FILE_HEADER* NewFile;
UINT32 NewFileSize;
@@ -1304,7 +1127,22 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ Iterates through the sections contained within a given array of sections
+ @param SectionsStart Address of the start of the FFS sections array
+ @param TotalSectionsSize Total size of all the sections
+ @param Key Should be 0 to get the first section. After that, it should be
+ passed back in without modifying its contents to retrieve
+ subsequent files.
+ @param Section Output section pointer
+ (Section == NULL) -> invalid parameter
+ otherwise -> *Section will be update to the location of the file
+
+ @retval EFI_SUCCESS
+ @retval EFI_NOT_FOUND
+ @retval EFI_VOLUME_CORRUPTED
+**/
EFI_STATUS
FvBufFindNextSection (
IN VOID *SectionsStart,
@@ -1312,30 +1150,6 @@ FvBufFindNextSection (
IN OUT UINTN *Key,
OUT VOID **Section
)
-/*++
-
-Routine Description:
-
- Iterates through the sections contained within a given array of sections
-
-Arguments:
-
- SectionsStart - Address of the start of the FFS sections array
- TotalSectionsSize - Total size of all the sections
- Key - Should be 0 to get the first section. After that, it should be
- passed back in without modifying its contents to retrieve
- subsequent files.
- Section - Output section pointer
- (Section == NULL) -> invalid parameter
- otherwise -> *Section will be update to the location of the file
-
-Returns:
-
- EFI_SUCCESS
- EFI_NOT_FOUND
- EFI_VOLUME_CORRUPTED
-
---*/
{
EFI_COMMON_SECTION_HEADER *sectionHdr;
UINTN sectionSize;
@@ -1363,31 +1177,22 @@ Returns:
}
+/**
+ Searches the FFS file and counts the number of sections found.
+ The sections are NOT recursed.
+ @param FfsFile Address of the FFS file in memory
+ @param Count The location to store the section count in
+
+ @retval EFI_SUCCESS
+ @retval EFI_NOT_FOUND
+ @retval EFI_VOLUME_CORRUPTED
+**/
EFI_STATUS
FvBufCountSections (
IN VOID* FfsFile,
IN UINTN* Count
)
-/*++
-
-Routine Description:
-
- Searches the FFS file and counts the number of sections found.
- The sections are NOT recursed.
-
-Arguments:
-
- FfsFile - Address of the FFS file in memory
- Count - The location to store the section count in
-
-Returns:
-
- EFI_SUCCESS
- EFI_NOT_FOUND
- EFI_VOLUME_CORRUPTED
-
---*/
{
EFI_STATUS Status;
UINTN Key;
@@ -1424,35 +1229,26 @@ Returns:
return EFI_NOT_FOUND;
}
+/**
+ Searches the FFS file for a section by its type
+ @param FfsFile Address of the FFS file in memory
+ @param Type FFS FILE section type to search for
+ @param Section Output section pointer
+ (Section == NULL) -> Only determine if the section exists, based on return
+ value from the function call.
+ otherwise -> *Section will be update to the location of the file
+
+ @retval EFI_SUCCESS
+ @retval EFI_NOT_FOUND
+ @retval EFI_VOLUME_CORRUPTED
+**/
EFI_STATUS
FvBufFindSectionByType (
IN VOID *FfsFile,
IN UINT8 Type,
OUT VOID **Section
)
-/*++
-
-Routine Description:
-
- Searches the FFS file for a section by its type
-
-Arguments:
-
- FfsFile - Address of the FFS file in memory
- Type - FFS FILE section type to search for
- Section - Output section pointer
- (Section == NULL) -> Only determine if the section exists, based on return
- value from the function call.
- otherwise -> *Section will be update to the location of the file
-
-Returns:
-
- EFI_SUCCESS
- EFI_NOT_FOUND
- EFI_VOLUME_CORRUPTED
-
---*/
{
EFI_STATUS Status;
UINTN Key;
@@ -1487,30 +1283,21 @@ Returns:
return EFI_NOT_FOUND;
}
-
-EFI_STATUS
-FvBufShrinkWrap (
- IN VOID *Fv
- )
-/*++
-
-Routine Description:
-
+/**
Shrinks a firmware volume (in place) to provide a minimal FV.
BUGBUG: Does not handle the case where the firmware volume has a
VTF (Volume Top File). The VTF will not be moved to the
end of the extended FV.
-Arguments:
+ @param Fv Firmware volume.
- Fv - Firmware volume.
-
-Returns:
-
- EFI_SUCCESS
-
---*/
+ @retval EFI_SUCCESS
+**/
+EFI_STATUS
+FvBufShrinkWrap (
+ IN VOID *Fv
+ )
{
EFI_STATUS Status;
UINTN OldSize;
@@ -1569,32 +1356,23 @@ Returns:
}
+/**
+ Searches the FFS file for a section by its type
+ @param Fv Address of the Fv in memory
+ @param BlockSize The size of the blocks to convert the Fv to. If the total size
+ of the Fv is not evenly divisible by this size, then
+ EFI_INVALID_PARAMETER will be returned.
+
+ @retval EFI_SUCCESS
+ @retval EFI_NOT_FOUND
+ @retval EFI_VOLUME_CORRUPTED
+**/
EFI_STATUS
FvBufUnifyBlockSizes (
IN OUT VOID *Fv,
IN UINTN BlockSize
)
-/*++
-
-Routine Description:
-
- Searches the FFS file for a section by its type
-
-Arguments:
-
- Fv - Address of the Fv in memory
- BlockSize - The size of the blocks to convert the Fv to. If the total size
- of the Fv is not evenly divisible by this size, then
- EFI_INVALID_PARAMETER will be returned.
-
-Returns:
-
- EFI_SUCCESS
- EFI_NOT_FOUND
- EFI_VOLUME_CORRUPTED
-
---*/
{
EFI_FIRMWARE_VOLUME_HEADER *hdr = (EFI_FIRMWARE_VOLUME_HEADER*)Fv;
EFI_FV_BLOCK_MAP_ENTRY *blk = hdr->BlockMap;
@@ -1641,28 +1419,20 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ This function calculates the UINT16 sum for the requested region.
+
+ @param Buffer Pointer to buffer containing byte data of component.
+ @param Size Size of the buffer
+
+ @return The 16 bit checksum
+**/
STATIC
UINT16
FvBufCalculateSum16 (
IN UINT16 *Buffer,
IN UINTN Size
)
-/*++
-
-Routine Description:
-
- This function calculates the UINT16 sum for the requested region.
-
-Arguments:
-
- Buffer Pointer to buffer containing byte data of component.
- Size Size of the buffer
-
-Returns:
-
- The 16 bit checksum
-
---*/
{
UINTN Index;
UINT16 Sum;
@@ -1679,56 +1449,38 @@ Returns:
return (UINT16) Sum;
}
+/**
+ This function calculates the value needed for a valid UINT16 checksum
+ @param Buffer Pointer to buffer containing byte data of component.
+ @param Size Size of the buffer
+
+ @return The 16 bit checksum value needed.
+**/
STATIC
UINT16
FvBufCalculateChecksum16 (
IN UINT16 *Buffer,
IN UINTN Size
)
-/*++
-
-Routine Description::
-
- This function calculates the value needed for a valid UINT16 checksum
-
-Arguments:
-
- Buffer Pointer to buffer containing byte data of component.
- Size Size of the buffer
-
-Returns:
-
- The 16 bit checksum value needed.
-
---*/
{
return (UINT16)(0x10000 - FvBufCalculateSum16 (Buffer, Size));
}
+/**
+ This function calculates the UINT8 sum for the requested region.
+ @param Buffer Pointer to buffer containing byte data of component.
+ @param Size Size of the buffer
+
+ @return The 8 bit checksum value needed.
+**/
STATIC
UINT8
FvBufCalculateSum8 (
IN UINT8 *Buffer,
IN UINTN Size
)
-/*++
-
-Description:
-
- This function calculates the UINT8 sum for the requested region.
-
-Input:
-
- Buffer Pointer to buffer containing byte data of component.
- Size Size of the buffer
-
-Return:
-
- The 8 bit checksum value needed.
-
---*/
{
UINTN Index;
UINT8 Sum;
@@ -1745,29 +1497,20 @@ Return:
return Sum;
}
+/**
+ This function calculates the value needed for a valid UINT8 checksum
+ @param Buffer Pointer to buffer containing byte data of component.
+ @param Size Size of the buffer
+
+ @return The 8 bit checksum value needed.
+**/
STATIC
UINT8
FvBufCalculateChecksum8 (
IN UINT8 *Buffer,
IN UINTN Size
)
-/*++
-
-Description:
-
- This function calculates the value needed for a valid UINT8 checksum
-
-Input:
-
- Buffer Pointer to buffer containing byte data of component.
- Size Size of the buffer
-
-Return:
-
- The 8 bit checksum value needed.
-
---*/
{
return (UINT8)(0x100 - FvBufCalculateSum8 (Buffer, Size));
}
diff --git a/BaseTools/Source/C/Common/FvLib.c b/BaseTools/Source/C/Common/FvLib.c
index d9f45930..2b1b7746 100644
--- a/BaseTools/Source/C/Common/FvLib.c
+++ b/BaseTools/Source/C/Common/FvLib.c
@@ -22,29 +22,22 @@ UINT32 mFvLength = 0;
//
// External function implementations
//
+
+/**
+ This initializes the FV lib with a pointer to the FV and length. It does not
+ verify the FV in any way.
+
+ @param Fv Buffer containing the FV.
+ @param FvLength Length of the FV
+
+ @retval EFI_SUCCESS Function Completed successfully.
+ @retval EFI_INVALID_PARAMETER A required parameter was NULL.
+**/
EFI_STATUS
InitializeFvLib (
IN VOID *Fv,
IN UINT32 FvLength
)
-/*++
-
-Routine Description:
-
- This initializes the FV lib with a pointer to the FV and length. It does not
- verify the FV in any way.
-
-Arguments:
-
- Fv Buffer containing the FV.
- FvLength Length of the FV
-
-Returns:
-
- EFI_SUCCESS Function Completed successfully.
- EFI_INVALID_PARAMETER A required parameter was NULL.
-
---*/
{
//
// Verify input arguments
@@ -59,29 +52,21 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ This function returns a pointer to the current FV and the size.
+
+ @param FvHeader Pointer to the FV buffer.
+ @param FvLength Length of the FV
+
+ @retval EFI_SUCCESS Function Completed successfully.
+ @retval EFI_INVALID_PARAMETER A required parameter was NULL.
+ @retvalEFI_ABORTED The library needs to be initialized.
+**/
EFI_STATUS
GetFvHeader (
OUT EFI_FIRMWARE_VOLUME_HEADER **FvHeader,
OUT UINT32 *FvLength
)
-/*++
-
-Routine Description:
-
- This function returns a pointer to the current FV and the size.
-
-Arguments:
-
- FvHeader Pointer to the FV buffer.
- FvLength Length of the FV
-
-Returns:
-
- EFI_SUCCESS Function Completed successfully.
- EFI_INVALID_PARAMETER A required parameter was NULL.
- EFI_ABORTED The library needs to be initialized.
-
---*/
{
//
// Verify library has been initialized.
@@ -101,31 +86,23 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ This function returns the next file. If the current file is NULL, it returns
+ the first file in the FV. If the function returns EFI_SUCCESS and the file
+ pointer is NULL, then there are no more files in the FV.
+
+ @param CurrentFile Pointer to the current file, must be within the current FV.
+ @param NextFile Pointer to the next file in the FV.
+
+ @retval EFI_SUCCESS Function completed successfully.
+ @retval EFI_INVALID_PARAMETER A required parameter was NULL or is out of range.
+ @retval EFI_ABORTED The library needs to be initialized.
+**/
EFI_STATUS
GetNextFile (
IN EFI_FFS_FILE_HEADER *CurrentFile,
OUT EFI_FFS_FILE_HEADER **NextFile
)
-/*++
-
-Routine Description:
-
- This function returns the next file. If the current file is NULL, it returns
- the first file in the FV. If the function returns EFI_SUCCESS and the file
- pointer is NULL, then there are no more files in the FV.
-
-Arguments:
-
- CurrentFile Pointer to the current file, must be within the current FV.
- NextFile Pointer to the next file in the FV.
-
-Returns:
-
- EFI_SUCCESS Function completed successfully.
- EFI_INVALID_PARAMETER A required parameter was NULL or is out of range.
- EFI_ABORTED The library needs to be initialized.
-
---*/
{
EFI_STATUS Status;
@@ -214,29 +191,21 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ Find a file by name. The function will return NULL if the file is not found.
+
+ @param FileName The GUID file name of the file to search for.
+ @param File Return pointer. In the case of an error, contents are undefined.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_ABORTED An error was encountered.
+ @retval EFI_INVALID_PARAMETER One of the parameters was NULL.
+**/
EFI_STATUS
GetFileByName (
IN EFI_GUID *FileName,
OUT EFI_FFS_FILE_HEADER **File
)
-/*++
-
-Routine Description:
-
- Find a file by name. The function will return NULL if the file is not found.
-
-Arguments:
-
- FileName The GUID file name of the file to search for.
- File Return pointer. In the case of an error, contents are undefined.
-
-Returns:
-
- EFI_SUCCESS The function completed successfully.
- EFI_ABORTED An error was encountered.
- EFI_INVALID_PARAMETER One of the parameters was NULL.
-
---*/
{
EFI_FFS_FILE_HEADER *CurrentFile;
EFI_STATUS Status;
@@ -295,33 +264,25 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ Find a file by type and instance. An instance of 1 is the first instance.
+ The function will return NULL if a matching file cannot be found.
+ File type EFI_FV_FILETYPE_ALL means any file type is valid.
+
+ @param FileType Type of file to search for.
+ @param Instance Instance of the file type to return.
+ @param File Return pointer. In the case of an error, contents are undefined.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_ABORTED An error was encountered.
+ @retval EFI_INVALID_PARAMETER One of the parameters was NULL.
+**/
EFI_STATUS
GetFileByType (
IN EFI_FV_FILETYPE FileType,
IN UINTN Instance,
OUT EFI_FFS_FILE_HEADER **File
)
-/*++
-
-Routine Description:
-
- Find a file by type and instance. An instance of 1 is the first instance.
- The function will return NULL if a matching file cannot be found.
- File type EFI_FV_FILETYPE_ALL means any file type is valid.
-
-Arguments:
-
- FileType Type of file to search for.
- Instance Instance of the file type to return.
- File Return pointer. In the case of an error, contents are undefined.
-
-Returns:
-
- EFI_SUCCESS The function completed successfully.
- EFI_ABORTED An error was encountered.
- EFI_INVALID_PARAMETER One of the parameters was NULL.
-
---*/
{
EFI_FFS_FILE_HEADER *CurrentFile;
EFI_STATUS Status;
@@ -383,6 +344,23 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ Helper function to search a sequence of sections from the section pointed
+ by FirstSection to SearchEnd for the Instance-th section of type SectionType.
+ The current counter is saved in StartIndex and when the section is found, it's
+ saved in Section. GUID-defined sections, if special processing is not required,
+ are searched recursively in a depth-first manner.
+
+ @param FirstSection The first section to start searching from.
+ @param SearchEnd The end address to stop search.
+ @param SectionType The type of section to search.
+ @param StartIndex The current counter is saved.
+ @param Instance The requested n-th section number.
+ @param Section The found section returned.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NOT_FOUND The section is not found.
+**/
EFI_STATUS
SearchSectionByType (
IN EFI_FILE_SECTION_POINTER FirstSection,
@@ -392,30 +370,6 @@ SearchSectionByType (
IN UINTN Instance,
OUT EFI_FILE_SECTION_POINTER *Section
)
-/*++
-
-Routine Description:
-
- Helper function to search a sequence of sections from the section pointed
- by FirstSection to SearchEnd for the Instance-th section of type SectionType.
- The current counter is saved in StartIndex and when the section is found, it's
- saved in Section. GUID-defined sections, if special processing is not required,
- are searched recursively in a depth-first manner.
-
-Arguments:
-
- FirstSection The first section to start searching from.
- SearchEnd The end address to stop search.
- SectionType The type of section to search.
- StartIndex The current counter is saved.
- Instance The requested n-th section number.
- Section The found section returned.
-
-Returns:
-
- EFI_SUCCESS The function completed successfully.
- EFI_NOT_FOUND The section is not found.
---*/
{
EFI_FILE_SECTION_POINTER CurrentSection;
EFI_FILE_SECTION_POINTER InnerSection;
@@ -479,6 +433,22 @@ Returns:
return EFI_NOT_FOUND;
}
+/**
+ Find a section in a file by type and instance. An instance of 1 is the first
+ instance. The function will return NULL if a matching section cannot be found.
+ GUID-defined sections, if special processing is not needed, are handled in a
+ depth-first manner.
+
+ @param File The file to search.
+ @param SectionType Type of file to search for.
+ @param Instance Instance of the section to return.
+ @param Section Return pointer. In the case of an error, contents are undefined.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_ABORTED An error was encountered.
+ @retval EFI_INVALID_PARAMETER One of the parameters was NULL.
+ @retval EFI_NOT_FOUND No found.
+**/
EFI_STATUS
GetSectionByType (
IN EFI_FFS_FILE_HEADER *File,
@@ -486,29 +456,6 @@ GetSectionByType (
IN UINTN Instance,
OUT EFI_FILE_SECTION_POINTER *Section
)
-/*++
-
-Routine Description:
-
- Find a section in a file by type and instance. An instance of 1 is the first
- instance. The function will return NULL if a matching section cannot be found.
- GUID-defined sections, if special processing is not needed, are handled in a
- depth-first manner.
-
-Arguments:
-
- File The file to search.
- SectionType Type of file to search for.
- Instance Instance of the section to return.
- Section Return pointer. In the case of an error, contents are undefined.
-
-Returns:
-
- EFI_SUCCESS The function completed successfully.
- EFI_ABORTED An error was encountered.
- EFI_INVALID_PARAMETER One of the parameters was NULL.
- EFI_NOT_FOUND No found.
---*/
{
EFI_FILE_SECTION_POINTER CurrentSection;
EFI_STATUS Status;
@@ -560,31 +507,25 @@ Returns:
return EFI_NOT_FOUND;
}
}
+
//
// will not parse compressed sections
//
+
+/**
+ Verify the current pointer points to a valid FV header.
+
+ @param FvHeader Pointer to an alleged FV file.
+
+ @retval EFI_SUCCESS The FV header is valid.
+ @retval EFI_VOLUME_CORRUPTED The FV header is not valid.
+ @retval EFI_INVALID_PARAMETER A required parameter was NULL.
+ @retval EFI_ABORTED Operation aborted.
+**/
EFI_STATUS
VerifyFv (
IN EFI_FIRMWARE_VOLUME_HEADER *FvHeader
)
-/*++
-
-Routine Description:
-
- Verify the current pointer points to a valid FV header.
-
-Arguments:
-
- FvHeader Pointer to an alleged FV file.
-
-Returns:
-
- EFI_SUCCESS The FV header is valid.
- EFI_VOLUME_CORRUPTED The FV header is not valid.
- EFI_INVALID_PARAMETER A required parameter was NULL.
- EFI_ABORTED Operation aborted.
-
---*/
{
UINT16 Checksum;
@@ -612,28 +553,20 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ Verify the current pointer points to a FFS file header.
+
+ @param FfsHeader Pointer to an alleged FFS file.
+
+ @retval EFI_SUCCESS The Ffs header is valid.
+ @retval EFI_NOT_FOUND This "file" is the beginning of free space.
+ @retval EFI_VOLUME_CORRUPTED The Ffs header is not valid.
+ @retval EFI_ABORTED The erase polarity is not known.
+**/
EFI_STATUS
VerifyFfsFile (
IN EFI_FFS_FILE_HEADER *FfsHeader
)
-/*++
-
-Routine Description:
-
- Verify the current pointer points to a FFS file header.
-
-Arguments:
-
- FfsHeader Pointer to an alleged FFS file.
-
-Returns:
-
- EFI_SUCCESS The Ffs header is valid.
- EFI_NOT_FOUND This "file" is the beginning of free space.
- EFI_VOLUME_CORRUPTED The Ffs header is not valid.
- EFI_ABORTED The erase polarity is not known.
-
---*/
{
BOOLEAN ErasePolarity;
EFI_STATUS Status;
@@ -754,25 +687,17 @@ GetSectionHeaderLength(
return sizeof(EFI_COMMON_SECTION_HEADER);
}
+/**
+ Get FFS file length including FFS header.
+
+ @param FfsHeader Pointer to EFI_FFS_FILE_HEADER.
+
+ @return UINT32 Length of FFS file header.
+**/
UINT32
GetFfsFileLength (
EFI_FFS_FILE_HEADER *FfsHeader
)
-/*++
-
-Routine Description:
-
- Get FFS file length including FFS header.
-
-Arguments:
-
- FfsHeader Pointer to EFI_FFS_FILE_HEADER.
-
-Returns:
-
- UINT32 Length of FFS file header.
-
---*/
{
if (FfsHeader == NULL) {
return 0;
@@ -800,25 +725,17 @@ GetSectionFileLength (
return Length;
}
+/**
+ Converts a three byte length value into a UINT32.
+
+ @param ThreeByteLength Pointer to the first of the 3 byte length.
+
+ @return UINT32 Size of the section
+**/
UINT32
GetLength (
UINT8 *ThreeByteLength
)
-/*++
-
-Routine Description:
-
- Converts a three byte length value into a UINT32.
-
-Arguments:
-
- ThreeByteLength Pointer to the first of the 3 byte length.
-
-Returns:
-
- UINT32 Size of the section
-
---*/
{
UINT32 Length;
@@ -832,28 +749,20 @@ Returns:
return Length;
}
+/**
+ This function returns with the FV erase polarity. If the erase polarity
+ for a bit is 1, the function return TRUE.
+
+ @param ErasePolarity A pointer to the erase polarity.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_INVALID_PARAMETER One of the input parameters was invalid.
+ @retval EFI_ABORTED Operation aborted.
+**/
EFI_STATUS
GetErasePolarity (
OUT BOOLEAN *ErasePolarity
)
-/*++
-
-Routine Description:
-
- This function returns with the FV erase polarity. If the erase polarity
- for a bit is 1, the function return TRUE.
-
-Arguments:
-
- ErasePolarity A pointer to the erase polarity.
-
-Returns:
-
- EFI_SUCCESS The function completed successfully.
- EFI_INVALID_PARAMETER One of the input parameters was invalid.
- EFI_ABORTED Operation aborted.
-
---*/
{
EFI_STATUS Status;
@@ -886,28 +795,20 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ This function returns a the highest state bit in the FFS that is set.
+ It in no way validate the FFS file.
+
+ @param ErasePolarity The erase polarity for the file state bits.
+ @param FfsHeader Pointer to a FFS file.
+
+ @retval UINT8 The hightest set state of the file.
+**/
UINT8
GetFileState (
IN BOOLEAN ErasePolarity,
IN EFI_FFS_FILE_HEADER *FfsHeader
)
-/*++
-
-Routine Description:
-
- This function returns a the highest state bit in the FFS that is set.
- It in no way validate the FFS file.
-
-Arguments:
-
- ErasePolarity The erase polarity for the file state bits.
- FfsHeader Pointer to a FFS file.
-
-Returns:
-
- UINT8 The hightest set state of the file.
-
---*/
{
UINT8 FileState;
UINT8 HighestBit;
diff --git a/BaseTools/Source/C/Common/MemoryFile.c b/BaseTools/Source/C/Common/MemoryFile.c
index 68277e98..556d1a35 100644
--- a/BaseTools/Source/C/Common/MemoryFile.c
+++ b/BaseTools/Source/C/Common/MemoryFile.c
@@ -27,29 +27,21 @@ CheckMemoryFileState (
// Function implementations
//
+/**
+ This opens a file, reads it into memory and returns a memory file
+ object.
+
+ @param InputFile Memory file image.
+ @param OutputMemoryFile Handle to memory file
+
+ @return EFI_STATUS
+ OutputMemoryFile is valid if !EFI_ERROR
+**/
EFI_STATUS
GetMemoryFile (
IN CHAR8 *InputFileName,
OUT EFI_HANDLE *OutputMemoryFile
)
-/*++
-
-Routine Description:
-
- This opens a file, reads it into memory and returns a memory file
- object.
-
-Arguments:
-
- InputFile Memory file image.
- OutputMemoryFile Handle to memory file
-
-Returns:
-
- EFI_STATUS
- OutputMemoryFile is valid if !EFI_ERROR
-
---*/
{
EFI_STATUS Status;
CHAR8 *InputFileImage;
@@ -78,26 +70,17 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ Frees all memory associated with the input memory file.
+ @param InputMemoryFile Handle to memory file
+
+ @return EFI_STATUS
+**/
EFI_STATUS
FreeMemoryFile (
IN EFI_HANDLE InputMemoryFile
)
-/*++
-
-Routine Description:
-
- Frees all memory associated with the input memory file.
-
-Arguments:
-
- InputMemoryFile Handle to memory file
-
-Returns:
-
- EFI_STATUS
-
---*/
{
MEMORY_FILE *MemoryFile;
@@ -118,31 +101,22 @@ Returns:
return EFI_SUCCESS;
}
-
-CHAR8 *
-ReadMemoryFileLine (
- IN EFI_HANDLE InputMemoryFile
- )
-/*++
-
-Routine Description:
-
+/**
This function reads a line from the memory file. The newline characters
are stripped and a null terminated string is returned.
If the string pointer returned is non-NULL, then the caller must free the
memory associated with this string.
-Arguments:
+ @param InputMemoryFile Handle to memory file
- InputMemoryFile Handle to memory file
-
-Returns:
-
- NULL if error or EOF
- NULL character termincated string otherwise (MUST BE FREED BY CALLER)
-
---*/
+ @retval NULL if error or EOF
+ @retval NULL character termincated string otherwise (MUST BE FREED BY CALLER)
+**/
+CHAR8 *
+ReadMemoryFileLine (
+ IN EFI_HANDLE InputMemoryFile
+ )
{
CHAR8 *EndOfLine;
UINTN CharsToCopy;
diff --git a/BaseTools/Source/C/Common/MemoryFile.h b/BaseTools/Source/C/Common/MemoryFile.h
index 56a11d89..a466bbf8 100644
--- a/BaseTools/Source/C/Common/MemoryFile.h
+++ b/BaseTools/Source/C/Common/MemoryFile.h
@@ -27,79 +27,53 @@ typedef struct {
// Functions declarations
//
+/**
+ This opens a file, reads it into memory and returns a memory file
+ object.
+
+ @param InputFile Memory file image.
+ @param OutputMemoryFile Handle to memory file
+
+ @return EFI_STATUS
+ OutputMemoryFile is valid if !EFI_ERROR
+**/
EFI_STATUS
GetMemoryFile (
IN CHAR8 *InputFileName,
OUT EFI_HANDLE *OutputMemoryFile
)
;
+
/**
+ Frees all memory associated with the input memory file.
-Routine Description:
-
- This opens a file, reads it into memory and returns a memory file
- object.
-
-Arguments:
-
- InputFile Memory file image.
- OutputMemoryFile Handle to memory file
-
-Returns:
-
- EFI_STATUS
- OutputMemoryFile is valid if !EFI_ERROR
+ @param InputMemoryFile Handle to memory file
+ @return EFI_STATUS
**/
-
-
EFI_STATUS
FreeMemoryFile (
IN EFI_HANDLE InputMemoryFile
)
;
+
/**
-
-Routine Description:
-
- Frees all memory associated with the input memory file.
-
-Arguments:
-
- InputMemoryFile Handle to memory file
-
-Returns:
-
- EFI_STATUS
-
-**/
-
-
-CHAR8 *
-ReadMemoryFileLine (
- IN EFI_HANDLE InputMemoryFile
- )
-;
-/**
-
-Routine Description:
-
This function reads a line from the memory file. The newline characters
are stripped and a null terminated string is returned.
If the string pointer returned is non-NULL, then the caller must free the
memory associated with this string.
-Arguments:
-
- InputMemoryFile Handle to memory file
-
-Returns:
-
- NULL if error or EOF
- NULL character termincated string otherwise (MUST BE FREED BY CALLER)
+ @param InputMemoryFile Handle to memory file
+ @retval NULL if error or EOF
+ @retval NULL character termincated string otherwise (MUST BE FREED BY CALLER)
**/
+CHAR8 *
+ReadMemoryFileLine (
+ IN EFI_HANDLE InputMemoryFile
+ )
+;
#endif
diff --git a/BaseTools/Source/C/Common/MyAlloc.c b/BaseTools/Source/C/Common/MyAlloc.c
index dacb07ec..d2ebcb24 100644
--- a/BaseTools/Source/C/Common/MyAlloc.c
+++ b/BaseTools/Source/C/Common/MyAlloc.c
@@ -27,40 +27,23 @@ STATIC MY_ALLOC_STRUCT *MyAllocData = NULL;
STATIC UINT32 MyAllocHeadMagik = MYALLOC_HEAD_MAGIK;
STATIC UINT32 MyAllocTailMagik = MYALLOC_TAIL_MAGIK;
-//
-// ////////////////////////////////////////////////////////////////////////////
-//
-//
+/**
+ Check for corruptions in the allocated memory chain. If a corruption
+ is detection program operation stops w/ an exit(1) call.
+
+ @param Final When FALSE, MyCheck() returns if the allocated memory chain
+ has not been corrupted. When TRUE, MyCheck() returns if there
+ are no un-freed allocations. If there are un-freed allocations,
+ they are displayed and exit(1) is called.
+ @param File Set to __FILE__ by macro expansion.
+ @param Line Set to __LINE__ by macro expansion.
+**/
VOID
MyCheck (
BOOLEAN Final,
UINT8 File[],
UINTN Line
)
-// *++
-// Description:
-//
-// Check for corruptions in the allocated memory chain. If a corruption
-// is detection program operation stops w/ an exit(1) call.
-//
-// Parameters:
-//
-// Final := When FALSE, MyCheck() returns if the allocated memory chain
-// has not been corrupted. When TRUE, MyCheck() returns if there
-// are no un-freed allocations. If there are un-freed allocations,
-// they are displayed and exit(1) is called.
-//
-//
-// File := Set to __FILE__ by macro expansion.
-//
-// Line := Set to __LINE__ by macro expansion.
-//
-// Returns:
-//
-// n/a
-//
-// --*/
-//
{
MY_ALLOC_STRUCT *Tmp;
@@ -155,39 +138,26 @@ MyCheck (
}
}
}
-//
-// ////////////////////////////////////////////////////////////////////////////
-//
-//
+
+/**
+ Allocate a new link in the allocation chain along with enough storage
+ for the File[] string, requested Size and alignment overhead. If
+ memory cannot be allocated or the allocation chain has been corrupted,
+ exit(1) will be called.
+
+ @param Size Number of bytes (UINT8) requested by the called.
+ Size cannot be zero.
+ @param File Set to __FILE__ by macro expansion.
+ @param Line Set to __LINE__ by macro expansion.
+
+ @return Pointer to the caller's buffer.
+**/
VOID *
MyAlloc (
UINTN Size,
UINT8 File[],
UINTN Line
)
-// *++
-// Description:
-//
-// Allocate a new link in the allocation chain along with enough storage
-// for the File[] string, requested Size and alignment overhead. If
-// memory cannot be allocated or the allocation chain has been corrupted,
-// exit(1) will be called.
-//
-// Parameters:
-//
-// Size := Number of bytes (UINT8) requested by the called.
-// Size cannot be zero.
-//
-// File := Set to __FILE__ by macro expansion.
-//
-// Line := Set to __LINE__ by macro expansion.
-//
-// Returns:
-//
-// Pointer to the caller's buffer.
-//
-// --*/
-//
{
MY_ALLOC_STRUCT *Tmp;
UINTN Len;
@@ -278,10 +248,19 @@ MyAlloc (
return Tmp->Buffer + sizeof (UINT32);
}
-//
-// ////////////////////////////////////////////////////////////////////////////
-//
-//
+
+/**
+ This does a MyAlloc(), memcpy() and MyFree(). There is no optimization
+ for shrinking or expanding buffers. An invalid parameter will cause
+ MyRealloc() to fail with a call to exit(1).
+
+ @param Ptr Pointer to the caller's buffer to be re-allocated.
+ @param Size Size of new buffer. Size cannot be zero.
+ @param File Set to __FILE__ by macro expansion.
+ @param Line Set to __LINE__ by macro expansion.
+
+ @return Pointer to new caller's buffer.
+**/
VOID *
MyRealloc (
VOID *Ptr,
@@ -289,29 +268,6 @@ MyRealloc (
UINT8 File[],
UINTN Line
)
-// *++
-// Description:
-//
-// This does a MyAlloc(), memcpy() and MyFree(). There is no optimization
-// for shrinking or expanding buffers. An invalid parameter will cause
-// MyRealloc() to fail with a call to exit(1).
-//
-// Parameters:
-//
-// Ptr := Pointer to the caller's buffer to be re-allocated.
-//
-// Size := Size of new buffer. Size cannot be zero.
-//
-// File := Set to __FILE__ by macro expansion.
-//
-// Line := Set to __LINE__ by macro expansion.
-//
-// Returns:
-//
-// Pointer to new caller's buffer.
-//
-// --*/
-//
{
MY_ALLOC_STRUCT *Tmp;
VOID *Buffer;
@@ -398,37 +354,22 @@ MyRealloc (
return Buffer;
}
-//
-// ////////////////////////////////////////////////////////////////////////////
-//
-//
+
+/**
+ Release a previously allocated buffer. Invalid parameters will cause
+ MyFree() to fail with an exit(1) call.
+
+ @param Ptr Pointer to the caller's buffer to be freed.
+ A NULL pointer will be ignored.
+ @param File Set to __FILE__ by macro expansion.
+ @param Line Set to __LINE__ by macro expansion.
+**/
VOID
MyFree (
VOID *Ptr,
UINT8 File[],
UINTN Line
)
-// *++
-// Description:
-//
-// Release a previously allocated buffer. Invalid parameters will cause
-// MyFree() to fail with an exit(1) call.
-//
-// Parameters:
-//
-// Ptr := Pointer to the caller's buffer to be freed.
-// A NULL pointer will be ignored.
-//
-// File := Set to __FILE__ by macro expansion.
-//
-// Line := Set to __LINE__ by macro expansion.
-//
-// Returns:
-//
-// n/a
-//
-// --*/
-//
{
MY_ALLOC_STRUCT *Tmp;
MY_ALLOC_STRUCT *Tmp2;
diff --git a/BaseTools/Source/C/Common/MyAlloc.h b/BaseTools/Source/C/Common/MyAlloc.h
index 005f477b..4ef6995d 100644
--- a/BaseTools/Source/C/Common/MyAlloc.h
+++ b/BaseTools/Source/C/Common/MyAlloc.h
@@ -71,6 +71,17 @@ typedef struct MyAllocStruct {
#define MYALLOC_HEAD_MAGIK 0xBADFACED
#define MYALLOC_TAIL_MAGIK 0xDEADBEEF
+/**
+ Check for corruptions in the allocated memory chain. If a corruption
+ is detection program operation stops w/ an exit(1) call.
+
+ @param Final When FALSE, MyCheck() returns if the allocated memory chain
+ has not been corrupted. When TRUE, MyCheck() returns if there
+ are no un-freed allocations. If there are un-freed allocations,
+ they are displayed and exit(1) is called.
+ @param File Set to __FILE__ by macro expansion.
+ @param Line Set to __LINE__ by macro expansion.
+**/
VOID
MyCheck (
BOOLEAN Final,
@@ -78,31 +89,20 @@ MyCheck (
UINTN Line
)
;
-//
-// *++
-// Description:
-//
-// Check for corruptions in the allocated memory chain. If a corruption
-// is detection program operation stops w/ an exit(1) call.
-//
-// Parameters:
-//
-// Final := When FALSE, MyCheck() returns if the allocated memory chain
-// has not been corrupted. When TRUE, MyCheck() returns if there
-// are no un-freed allocations. If there are un-freed allocations,
-// they are displayed and exit(1) is called.
-//
-//
-// File := Set to __FILE__ by macro expansion.
-//
-// Line := Set to __LINE__ by macro expansion.
-//
-// Returns:
-//
-// n/a
-//
-// --*/
-//
+
+/**
+ Allocate a new link in the allocation chain along with enough storage
+ for the File[] string, requested Size and alignment overhead. If
+ memory cannot be allocated or the allocation chain has been corrupted,
+ exit(1) will be called.
+
+ @param Size Number of bytes (UINT8) requested by the called.
+ Size cannot be zero.
+ @param File Set to __FILE__ by macro expansion.
+ @param Line Set to __LINE__ by macro expansion.
+
+ @return Pointer to the caller's buffer.
+**/
VOID *
MyAlloc (
UINTN Size,
@@ -110,30 +110,20 @@ MyAlloc (
UINTN Line
)
;
-//
-// *++
-// Description:
-//
-// Allocate a new link in the allocation chain along with enough storage
-// for the File[] string, requested Size and alignment overhead. If
-// memory cannot be allocated or the allocation chain has been corrupted,
-// exit(1) will be called.
-//
-// Parameters:
-//
-// Size := Number of bytes (UINT8) requested by the called.
-// Size cannot be zero.
-//
-// File := Set to __FILE__ by macro expansion.
-//
-// Line := Set to __LINE__ by macro expansion.
-//
-// Returns:
-//
-// Pointer to the caller's buffer.
-//
-// --*/
-//
+
+/**
+ This does a MyAlloc(), memcpy() and MyFree(). There is no optimization
+ for shrinking or expanding buffers. An invalid parameter will cause
+ MyRealloc() to fail with a call to exit(1).
+
+ @param Ptr Pointer to the caller's buffer to be re-allocated.
+ Ptr cannot be NULL.
+ @param Size Size of new buffer. Size cannot be zero.
+ @param File Set to __FILE__ by macro expansion.
+ @param Line Set to __LINE__ by macro expansion.
+
+ @return Pointer to new caller's buffer.
+**/
VOID *
MyRealloc (
VOID *Ptr,
@@ -142,31 +132,16 @@ MyRealloc (
UINTN Line
)
;
-//
-// *++
-// Description:
-//
-// This does a MyAlloc(), memcpy() and MyFree(). There is no optimization
-// for shrinking or expanding buffers. An invalid parameter will cause
-// MyRealloc() to fail with a call to exit(1).
-//
-// Parameters:
-//
-// Ptr := Pointer to the caller's buffer to be re-allocated.
-// Ptr cannot be NULL.
-//
-// Size := Size of new buffer. Size cannot be zero.
-//
-// File := Set to __FILE__ by macro expansion.
-//
-// Line := Set to __LINE__ by macro expansion.
-//
-// Returns:
-//
-// Pointer to new caller's buffer.
-//
-// --*/
-//
+
+/**
+ Release a previously allocated buffer. Invalid parameters will cause
+ MyFree() to fail with an exit(1) call.
+
+ @param Ptr Pointer to the caller's buffer to be freed.
+ A NULL pointer will be ignored.
+ @param File Set to __FILE__ by macro expansion.
+ @param Line Set to __LINE__ by macro expansion.
+**/
VOID
MyFree (
VOID *Ptr,
@@ -174,28 +149,7 @@ MyFree (
UINTN Line
)
;
-//
-// *++
-// Description:
-//
-// Release a previously allocated buffer. Invalid parameters will cause
-// MyFree() to fail with an exit(1) call.
-//
-// Parameters:
-//
-// Ptr := Pointer to the caller's buffer to be freed.
-// A NULL pointer will be ignored.
-//
-// File := Set to __FILE__ by macro expansion.
-//
-// Line := Set to __LINE__ by macro expansion.
-//
-// Returns:
-//
-// n/a
-//
-// --*/
-//
+
#else /* USE_MYALLOC */
//
diff --git a/BaseTools/Source/C/Common/OsPath.c b/BaseTools/Source/C/Common/OsPath.c
index 04e1557d..5dcb0dc8 100644
--- a/BaseTools/Source/C/Common/OsPath.c
+++ b/BaseTools/Source/C/Common/OsPath.c
@@ -20,14 +20,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// BUGBUG: Not fully implemented yet.
//
-CHAR8*
-OsPathDirName (
- IN CHAR8 *FilePath
- )
-/*++
-
-Routine Description:
+/**
This function returns the directory path which contains the particular path.
Some examples:
"a/b/c" -> "a/b"
@@ -40,15 +34,15 @@ Routine Description:
The caller must free the string returned.
-Arguments:
+ @param FilePath Path name of file to get the parent directory for.
- FilePath Path name of file to get the parent directory for.
+ @return NULL if error
+**/
+CHAR8*
+OsPathDirName (
+ IN CHAR8 *FilePath
+ )
-Returns:
-
- NULL if error
-
---*/
{
CHAR8 *Return;
CHAR8 *Pos;
@@ -97,14 +91,8 @@ Returns:
//
// BUGBUG: Not fully implemented yet.
//
-VOID
-OsPathNormPathInPlace (
- IN CHAR8 *Path
- )
-/*++
-
-Routine Description:
+/**
This function returns the directory path which contains the particular path.
Some examples:
"a/b/../c" -> "a/c"
@@ -113,15 +101,14 @@ Routine Description:
This function does not check for the existence of the file.
-Arguments:
+ @param Path Path name of file to normalize
- Path Path name of file to normalize
-
-Returns:
-
- The string is altered in place.
-
---*/
+ @return The string is altered in place.
+**/
+VOID
+OsPathNormPathInPlace (
+ IN CHAR8 *Path
+ )
{
CHAR8 *Pos;
INTN Offset;
@@ -200,16 +187,7 @@ Returns:
}
#endif
-
-CHAR8*
-OsPathPeerFilePath (
- IN CHAR8 *OldPath,
- IN CHAR8 *Peer
- )
-/*++
-
-Routine Description:
-
+/**
This function replaces the final portion of a path with an alternative
'peer' filename. For example:
"a/b/../c", "peer" -> "a/b/../peer"
@@ -219,16 +197,16 @@ Routine Description:
This function does not check for the existence of the file.
-Arguments:
+ @param OldPath Path name of replace the final segment
+ @param Peer The new path name to concatenate to become the peer path
- OldPath Path name of replace the final segment
- Peer The new path name to concatenate to become the peer path
-
-Returns:
-
- A CHAR8* string, which must be freed by the caller
-
---*/
+ @return A CHAR8* string, which must be freed by the caller
+**/
+CHAR8*
+OsPathPeerFilePath (
+ IN CHAR8 *OldPath,
+ IN CHAR8 *Peer
+ )
{
CHAR8 *Result;
INTN Offset;
@@ -259,27 +237,18 @@ Returns:
return Result;
}
+/**
+ Checks if a file exists
+ @param InputFileName The name of the file to check for existence
+
+ @retval TRUE The file exists
+ @retval FALSE The file does not exist
+**/
BOOLEAN
OsPathExists (
IN CHAR8 *InputFileName
)
-/*++
-
-Routine Description:
-
- Checks if a file exists
-
-Arguments:
-
- InputFileName The name of the file to check for existence
-
-Returns:
-
- TRUE The file exists
- FALSE The file does not exist
-
---*/
{
FILE *InputFile;
InputFile = fopen (LongFilePath (InputFileName), "rb");
diff --git a/BaseTools/Source/C/Common/OsPath.h b/BaseTools/Source/C/Common/OsPath.h
index 1b0640bd..7b17b6fb 100644
--- a/BaseTools/Source/C/Common/OsPath.h
+++ b/BaseTools/Source/C/Common/OsPath.h
@@ -16,15 +16,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// Functions declarations
//
-CHAR8*
-OsPathDirName (
- IN CHAR8 *FilePath
- )
-;
/**
-
-Routine Description:
-
This function returns the directory path which contains the particular path.
Some examples:
"a/b/c" -> "a/b"
@@ -37,26 +29,17 @@ Routine Description:
The caller must free the string returned.
-Arguments:
-
- FilePath Path name of file to get the parent directory for.
-
-Returns:
-
- NULL if error
+ @param FilePath Path name of file to get the parent directory for.
+ @return NULL if error
**/
-
-
-VOID
-OsPathNormPathInPlace (
- IN CHAR8 *Path
+CHAR8*
+OsPathDirName (
+ IN CHAR8 *FilePath
)
;
+
/**
-
-Routine Description:
-
This function returns the directory path which contains the particular path.
Some examples:
"a/b/../c" -> "a/c"
@@ -65,27 +48,17 @@ Routine Description:
This function does not check for the existence of the file.
-Arguments:
-
- Path Path name of file to normalize
-
-Returns:
-
- The string is altered in place.
+ @param Path Path name of file to normalize
+ @return The string is altered in place.
**/
-
-
-CHAR8*
-OsPathPeerFilePath (
- IN CHAR8 *OldPath,
- IN CHAR8 *Peer
+VOID
+OsPathNormPathInPlace (
+ IN CHAR8 *Path
)
;
+
/**
-
-Routine Description:
-
This function replaces the final portion of a path with an alternative
'peer' filename. For example:
"a/b/../c", "peer" -> "a/b/../peer"
@@ -95,39 +68,30 @@ Routine Description:
This function does not check for the existence of the file.
-Arguments:
-
- OldPath Path name of replace the final segment
- Peer The new path name to concatenate to become the peer path
-
-Returns:
-
- A CHAR8* string, which must be freed by the caller
+ @param OldPath Path name of replace the final segment
+ @param Peer The new path name to concatenate to become the peer path
+ @return A CHAR8* string, which must be freed by the caller
**/
+CHAR8*
+OsPathPeerFilePath (
+ IN CHAR8 *OldPath,
+ IN CHAR8 *Peer
+ )
+;
+/**
+ Checks if a file exists
+ @param InputFileName The name of the file to check for existence
+
+ @retval TRUE The file exists
+ @retval FALSE The file does not exist
+**/
BOOLEAN
OsPathExists (
IN CHAR8 *InputFileName
)
;
-/**
-
-Routine Description:
-
- Checks if a file exists
-
-Arguments:
-
- InputFileName The name of the file to check for existence
-
-Returns:
-
- TRUE The file exists
- FALSE The file does not exist
-
-**/
-
#endif
diff --git a/BaseTools/Source/C/Common/ParseGuidedSectionTools.c b/BaseTools/Source/C/Common/ParseGuidedSectionTools.c
index f8b8f061..f274bc49 100644
--- a/BaseTools/Source/C/Common/ParseGuidedSectionTools.c
+++ b/BaseTools/Source/C/Common/ParseGuidedSectionTools.c
@@ -33,30 +33,22 @@ typedef struct _GUID_SEC_TOOL_ENTRY {
// Function Implementation
//
-EFI_HANDLE
-ParseGuidedSectionToolsFile (
- IN CHAR8 *InputFile
- )
-/*++
-
-Routine Description:
-
+/**
This function parses the tools_def.txt file. It returns a
EFI_HANDLE object which can be used for the other library
functions and should be passed to FreeParsedGuidedSectionToolsHandle
to free resources when the tools_def.txt information is no
longer needed.
-Arguments:
+ @param InputFile Path name of file to read
- InputFile Path name of file to read
-
-Returns:
-
- NULL if error parsing
- A non-NULL EFI_HANDLE otherwise
-
---*/
+ @retval NULL if error parsing
+ @retval A non-NULL EFI_HANDLE otherwise
+**/
+EFI_HANDLE
+ParseGuidedSectionToolsFile (
+ IN CHAR8 *InputFile
+ )
{
EFI_STATUS Status;
EFI_HANDLE MemoryFile;
@@ -74,31 +66,22 @@ Returns:
return ParsedGuidedSectionTools;
}
-
-EFI_HANDLE
-ParseGuidedSectionToolsMemoryFile (
- IN EFI_HANDLE InputFile
- )
-/*++
-
-Routine Description:
-
+/**
This function parses the tools_def.txt file. It returns a
EFI_HANDLE object which can be used for the other library
functions and should be passed to FreeParsedGuidedSectionToolsHandle
to free resources when the tools_def.txt information is no
longer needed.
-Arguments:
+ @param InputFile Memory file image.
- InputFile Memory file image.
-
-Returns:
-
- NULL if error or EOF
- InputBuffer otherwise
-
---*/
+ @retval NULL if error or EOF
+ @retval InputBuffer otherwise
+**/
+EFI_HANDLE
+ParseGuidedSectionToolsMemoryFile (
+ IN EFI_HANDLE InputFile
+ )
{
EFI_STATUS Status;
CHAR8 *NextLine;
@@ -160,31 +143,22 @@ Returns:
return FirstGuidTool;
}
+/**
+ This function looks up the appropriate tool to use for extracting
+ a GUID defined FV section.
+ @param ParsedGuidedSectionToolsHandle A parsed GUID section tools handle.
+ @param SectionGuid The GUID for the section.
+
+ @retval NULL if no tool is found or there is another error
+ @retval Non-NULL The tool to use to access the section contents. (The caller
+ must free the memory associated with this string.)
+**/
CHAR8*
LookupGuidedSectionToolPath (
IN EFI_HANDLE ParsedGuidedSectionToolsHandle,
IN EFI_GUID *SectionGuid
)
-/*++
-
-Routine Description:
-
- This function looks up the appropriate tool to use for extracting
- a GUID defined FV section.
-
-Arguments:
-
- ParsedGuidedSectionToolsHandle A parsed GUID section tools handle.
- SectionGuid The GUID for the section.
-
-Returns:
-
- NULL - if no tool is found or there is another error
- Non-NULL - The tool to use to access the section contents. (The caller
- must free the memory associated with this string.)
-
---*/
{
GUID_SEC_TOOL_ENTRY *GuidTool;
diff --git a/BaseTools/Source/C/Common/ParseGuidedSectionTools.h b/BaseTools/Source/C/Common/ParseGuidedSectionTools.h
index 6b7bf1a7..5c96ea65 100644
--- a/BaseTools/Source/C/Common/ParseGuidedSectionTools.h
+++ b/BaseTools/Source/C/Common/ParseGuidedSectionTools.h
@@ -15,106 +15,73 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// Functions declarations
//
+/**
+ This function parses the tools_def.txt file. It returns a
+ EFI_HANDLE object which can be used for the other library
+ functions and should be passed to FreeParsedToolsDefHandle
+ to free resources when the tools_def.txt information is no
+ longer needed.
+
+ @param InputFile Path name of file to read
+
+ @retval NULL if error parsing
+ @retval A non-NULL EFI_HANDLE otherwise
+**/
EFI_HANDLE
ParseGuidedSectionToolsFile (
IN CHAR8 *InputFile
)
;
+
/**
-
-Routine Description:
-
This function parses the tools_def.txt file. It returns a
EFI_HANDLE object which can be used for the other library
functions and should be passed to FreeParsedToolsDefHandle
to free resources when the tools_def.txt information is no
longer needed.
-Arguments:
-
- InputFile Path name of file to read
-
-Returns:
-
- NULL if error parsing
- A non-NULL EFI_HANDLE otherwise
+ @param InputFile Memory file image.
+ @retval NULL if error parsing
+ @retval A non-NULL EFI_HANDLE otherwise
**/
-
-
EFI_HANDLE
ParseGuidedSectionToolsMemoryFile (
IN EFI_HANDLE InputFile
)
;
+
/**
+ This function looks up the appropriate tool to use for extracting
+ a GUID defined FV section.
-Routine Description:
-
- This function parses the tools_def.txt file. It returns a
- EFI_HANDLE object which can be used for the other library
- functions and should be passed to FreeParsedToolsDefHandle
- to free resources when the tools_def.txt information is no
- longer needed.
-
-Arguments:
-
- InputFile Memory file image.
-
-Returns:
-
- NULL if error parsing
- A non-NULL EFI_HANDLE otherwise
+ @param ParsedGuidedSectionToolsHandle A parsed GUID section tools handle.
+ @param SectionGuid The GUID for the section.
+ @retval NULL if no tool is found or there is another error
+ @retval Non-NULL The tool to use to access the section contents. (The caller
+ must free the memory associated with this string.)
**/
-
CHAR8*
LookupGuidedSectionToolPath (
IN EFI_HANDLE ParsedGuidedSectionToolsHandle,
IN EFI_GUID *SectionGuid
)
;
+
/**
+ Frees resources that were allocated by ParseGuidedSectionToolsFile.
+ After freeing these resources, the information that was parsed
+ is no longer accessible.
-Routine Description:
-
- This function looks up the appropriate tool to use for extracting
- a GUID defined FV section.
-
-Arguments:
-
- ParsedGuidedSectionToolsHandle A parsed GUID section tools handle.
- SectionGuid The GUID for the section.
-
-Returns:
-
- NULL - if no tool is found or there is another error
- Non-NULL - The tool to use to access the section contents. (The caller
- must free the memory associated with this string.)
+ @param ParsedToolDefHandle Handle returned from ParseGuidedSectionToolsFile
+ @return EFI_STATUS
**/
-
EFI_STATUS
FreeParsedGuidedSectionToolsHandle (
IN EFI_HANDLE ParsedGuidedSectionToolsHandle
)
;
-/**
-
-Routine Description:
-
- Frees resources that were allocated by ParseGuidedSectionToolsFile.
- After freeing these resources, the information that was parsed
- is no longer accessible.
-
-Arguments:
-
- ParsedToolDefHandle Handle returned from ParseGuidedSectionToolsFile
-
-Returns:
-
- EFI_STATUS
-
-**/
#endif
diff --git a/BaseTools/Source/C/Common/ParseInf.c b/BaseTools/Source/C/Common/ParseInf.c
index cc0b04ad..ca3c4142 100644
--- a/BaseTools/Source/C/Common/ParseInf.c
+++ b/BaseTools/Source/C/Common/ParseInf.c
@@ -14,16 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "ParseInf.h"
#include "CommonLib.h"
-CHAR8 *
-ReadLine (
- IN MEMORY_FILE *InputFile,
- IN OUT CHAR8 *InputBuffer,
- IN UINTN MaxLength
- )
-/*++
-
-Routine Description:
-
+/**
This function reads a line, stripping any comments.
The function reads a string from the input stream argument and stores it in
the input string. ReadLine reads characters from the current file position
@@ -31,18 +22,20 @@ Routine Description:
until the number of characters read is equal to MaxLength - 1, whichever
comes first. The newline character, if read, is replaced with a \0.
-Arguments:
+ @param InputFile Memory file image.
+ @param InputBuffer Buffer to read into, must be MaxLength size.
+ @param MaxLength The maximum size of the input buffer.
- InputFile Memory file image.
- InputBuffer Buffer to read into, must be MaxLength size.
- MaxLength The maximum size of the input buffer.
+ @retval NULL if error or EOF
+ @retval InputBuffer otherwise
+**/
+CHAR8 *
+ReadLine (
+ IN MEMORY_FILE *InputFile,
+ IN OUT CHAR8 *InputBuffer,
+ IN UINTN MaxLength
+ )
-Returns:
-
- NULL if error or EOF
- InputBuffer otherwise
-
---*/
{
CHAR8 *CharPtr;
CHAR8 *EndOfLine;
@@ -129,29 +122,21 @@ Returns:
return InputBuffer;
}
+/**
+ This function parses a file from the beginning to find a section.
+ The section string may be anywhere within a line.
+
+ @param InputFile Memory file image.
+ @param Section Section to search for
+
+ @retval FALSE if error or EOF
+ @retval TRUE if section found
+**/
BOOLEAN
FindSection (
IN MEMORY_FILE *InputFile,
IN CHAR8 *Section
)
-/*++
-
-Routine Description:
-
- This function parses a file from the beginning to find a section.
- The section string may be anywhere within a line.
-
-Arguments:
-
- InputFile Memory file image.
- Section Section to search for
-
-Returns:
-
- FALSE if error or EOF
- TRUE if section found
-
---*/
{
CHAR8 InputBuffer[MAX_LONG_FILE_PATH];
CHAR8 *CurrentToken;
@@ -190,6 +175,21 @@ Returns:
return FALSE;
}
+/**
+ Finds a token value given the section and token to search for.
+
+ @param InputFile Memory file image.
+ @param Section The section to search for, a string within [].
+ @param Token The token to search for, e.g. EFI_PEIM_RECOVERY, followed by an = in the INF file.
+ @param Instance The instance of the token to search for. Zero is the first instance.
+ @param Value The string that holds the value following the =. Must be MAX_LONG_FILE_PATH in size.
+
+ @retval EFI_SUCCESS Value found.
+ @retval EFI_ABORTED Format error detected in INF file.
+ @retval EFI_INVALID_PARAMETER Input argument was null.
+ @retval EFI_LOAD_ERROR Error reading from the file.
+ @retval EFI_NOT_FOUND Section/Token/Value not found.
+**/
EFI_STATUS
FindToken (
IN MEMORY_FILE *InputFile,
@@ -198,29 +198,6 @@ FindToken (
IN UINTN Instance,
OUT CHAR8 *Value
)
-/*++
-
-Routine Description:
-
- Finds a token value given the section and token to search for.
-
-Arguments:
-
- InputFile Memory file image.
- Section The section to search for, a string within [].
- Token The token to search for, e.g. EFI_PEIM_RECOVERY, followed by an = in the INF file.
- Instance The instance of the token to search for. Zero is the first instance.
- Value The string that holds the value following the =. Must be MAX_LONG_FILE_PATH in size.
-
-Returns:
-
- EFI_SUCCESS Value found.
- EFI_ABORTED Format error detected in INF file.
- EFI_INVALID_PARAMETER Input argument was null.
- EFI_LOAD_ERROR Error reading from the file.
- EFI_NOT_FOUND Section/Token/Value not found.
-
---*/
{
CHAR8 InputBuffer[MAX_LONG_FILE_PATH];
CHAR8 *CurrentToken;
@@ -359,30 +336,22 @@ Returns:
return EFI_NOT_FOUND;
}
+/**
+ Converts a string to an EFI_GUID. The string must be in the
+ xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx format.
+
+ @param AsciiGuidBuffer pointer to ascii string
+ @param GuidBuffer pointer to destination Guid
+
+ @retval EFI_ABORTED Could not convert the string
+ @retval EFI_SUCCESS The string was successfully converted
+ @retval EFI_INVALID_PARAMETER Input parameter is invalid.
+**/
EFI_STATUS
StringToGuid (
IN CHAR8 *AsciiGuidBuffer,
OUT EFI_GUID *GuidBuffer
)
-/*++
-
-Routine Description:
-
- Converts a string to an EFI_GUID. The string must be in the
- xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx format.
-
-Arguments:
-
- AsciiGuidBuffer - pointer to ascii string
- GuidBuffer - pointer to destination Guid
-
-Returns:
-
- EFI_ABORTED Could not convert the string
- EFI_SUCCESS The string was successfully converted
- EFI_INVALID_PARAMETER Input parameter is invalid.
-
---*/
{
INT32 Index;
int Data1;
@@ -461,33 +430,25 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ Converts a null terminated ascii string that represents a number into a
+ UINT64 value. A hex number may be preceded by a 0x, but may not be
+ succeeded by an h. A number without 0x or 0X is considered to be base 10
+ unless the IsHex input is true.
+
+ @param AsciiString The string to convert.
+ @param IsHex Force the string to be treated as a hex number.
+ @param ReturnValue The return value.
+
+ @retval EFI_SUCCESS Number successfully converted.
+ @retval EFI_ABORTED Invalid character encountered.
+**/
EFI_STATUS
AsciiStringToUint64 (
IN CONST CHAR8 *AsciiString,
IN BOOLEAN IsHex,
OUT UINT64 *ReturnValue
)
-/*++
-
-Routine Description:
-
- Converts a null terminated ascii string that represents a number into a
- UINT64 value. A hex number may be preceded by a 0x, but may not be
- succeeded by an h. A number without 0x or 0X is considered to be base 10
- unless the IsHex input is true.
-
-Arguments:
-
- AsciiString The string to convert.
- IsHex Force the string to be treated as a hex number.
- ReturnValue The return value.
-
-Returns:
-
- EFI_SUCCESS Number successfully converted.
- EFI_ABORTED Invalid character encountered.
-
---*/
{
UINT8 Index;
UINT64 Value;
@@ -577,29 +538,21 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ This function reads a line, stripping any comments.
+ // BUGBUG: This is obsolete once genmake goes away...
+
+ @param InputFile Stream pointer.
+ @param InputBuffer Buffer to read into, must be MAX_LONG_FILE_PATH size.
+
+ @retval NULL if error or EOF
+ @retval InputBuffer otherwise
+**/
CHAR8 *
ReadLineInStream (
IN FILE *InputFile,
IN OUT CHAR8 *InputBuffer
)
-/*++
-
-Routine Description:
-
- This function reads a line, stripping any comments.
- // BUGBUG: This is obsolete once genmake goes away...
-
-Arguments:
-
- InputFile Stream pointer.
- InputBuffer Buffer to read into, must be MAX_LONG_FILE_PATH size.
-
-Returns:
-
- NULL if error or EOF
- InputBuffer otherwise
-
---*/
{
CHAR8 *CharPtr;
@@ -633,30 +586,22 @@ Returns:
return InputBuffer;
}
+/**
+ This function parses a stream file from the beginning to find a section.
+ The section string may be anywhere within a line.
+ // BUGBUG: This is obsolete once genmake goes away...
+
+ @param InputFile Stream pointer.
+ @param Section Section to search for
+
+ @retval FALSE if error or EOF
+ @retval TRUE if section found
+**/
BOOLEAN
FindSectionInStream (
IN FILE *InputFile,
IN CHAR8 *Section
)
-/*++
-
-Routine Description:
-
- This function parses a stream file from the beginning to find a section.
- The section string may be anywhere within a line.
- // BUGBUG: This is obsolete once genmake goes away...
-
-Arguments:
-
- InputFile Stream pointer.
- Section Section to search for
-
-Returns:
-
- FALSE if error or EOF
- TRUE if section found
-
---*/
{
CHAR8 InputBuffer[MAX_LONG_FILE_PATH];
CHAR8 *CurrentToken;
diff --git a/BaseTools/Source/C/Common/ParseInf.h b/BaseTools/Source/C/Common/ParseInf.h
index 69c92cc1..3778fe9e 100644
--- a/BaseTools/Source/C/Common/ParseInf.h
+++ b/BaseTools/Source/C/Common/ParseInf.h
@@ -20,6 +20,22 @@ extern "C" {
//
// Functions declarations
//
+
+/**
+ This function reads a line, stripping any comments.
+ The function reads a string from the input stream argument and stores it in
+ the input string. ReadLine reads characters from the current file position
+ to and including the first newline character, to the end of the stream, or
+ until the number of characters read is equal to MaxLength - 1, whichever
+ comes first. The newline character, if read, is replaced with a \0.
+
+ @param InputFile Memory file image.
+ @param InputBuffer Buffer to read into, must be MaxLength size.
+ @param MaxLength The maximum size of the input buffer.
+
+ @retval NULL if error or EOF
+ @retval InputBuffer otherwise
+**/
CHAR8 *
ReadLine (
IN MEMORY_FILE *InputFile,
@@ -28,29 +44,16 @@ ReadLine (
)
;
-/*++
+/**
+ This function parses a file from the beginning to find a section.
+ The section string may be anywhere within a line.
-Routine Description:
+ @param InputFile Memory file image.
+ @param Section Section to search for
- This function reads a line, stripping any comments.
- The function reads a string from the input stream argument and stores it in
- the input string. ReadLine reads characters from the current file position
- to and including the first newline character, to the end of the stream, or
- until the number of characters read is equal to MaxLength - 1, whichever
- comes first. The newline character, if read, is replaced with a \0.
-
-Arguments:
-
- InputFile Memory file image.
- InputBuffer Buffer to read into, must be MaxLength size.
- MaxLength The maximum size of the input buffer.
-
-Returns:
-
- NULL if error or EOF
- InputBuffer otherwise
-
---*/
+ @retval FALSE if error or EOF
+ @retval TRUE if section found
+**/
BOOLEAN
FindSection (
IN MEMORY_FILE *InputFile,
@@ -58,24 +61,21 @@ FindSection (
)
;
-/*++
+/**
+ Finds a token value given the section and token to search for.
-Routine Description:
+ @param InputFile Memory file image.
+ @param Section The section to search for, a string within [].
+ @param Token The token to search for, e.g. EFI_PEIM_RECOVERY, followed by an = in the INF file.
+ @param Instance The instance of the token to search for. Zero is the first instance.
+ @param Value The string that holds the value following the =. Must be MAX_LONG_FILE_PATH in size.
- This function parses a file from the beginning to find a section.
- The section string may be anywhere within a line.
-
-Arguments:
-
- InputFile Memory file image.
- Section Section to search for
-
-Returns:
-
- FALSE if error or EOF
- TRUE if section found
-
---*/
+ @retval EFI_SUCCESS Value found.
+ @retval EFI_ABORTED Format error detected in INF file.
+ @retval EFI_INVALID_PARAMETER Input argument was null.
+ @retval EFI_LOAD_ERROR Error reading from the file.
+ @retval EFI_NOT_FOUND Section/Token/Value not found.
+**/
EFI_STATUS
FindToken (
IN MEMORY_FILE *InputFile,
@@ -86,29 +86,16 @@ FindToken (
)
;
-/*++
+/**
+ Converts a string to an EFI_GUID. The string must be in the
+ xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx format.
-Routine Description:
+ @param GuidBuffer pointer to destination Guid
+ @param AsciiGuidBuffer pointer to ascii string
- Finds a token value given the section and token to search for.
-
-Arguments:
-
- InputFile Memory file image.
- Section The section to search for, a string within [].
- Token The token to search for, e.g. EFI_PEIM_RECOVERY, followed by an = in the INF file.
- Instance The instance of the token to search for. Zero is the first instance.
- Value The string that holds the value following the =. Must be MAX_LONG_FILE_PATH in size.
-
-Returns:
-
- EFI_SUCCESS Value found.
- EFI_ABORTED Format error detected in INF file.
- EFI_INVALID_PARAMETER Input argument was null.
- EFI_LOAD_ERROR Error reading from the file.
- EFI_NOT_FOUND Section/Token/Value not found.
-
---*/
+ @retval EFI_ABORTED Could not convert the string
+ @retval EFI_SUCCESS The string was successfully converted
+**/
EFI_STATUS
StringToGuid (
IN CHAR8 *AsciiGuidBuffer,
@@ -116,24 +103,19 @@ StringToGuid (
)
;
-/*++
+/**
+ Converts a null terminated ascii string that represents a number into a
+ UINT64 value. A hex number may be preceded by a 0x, but may not be
+ succeeded by an h. A number without 0x or 0X is considered to be base 10
+ unless the IsHex input is true.
-Routine Description:
+ @param AsciiString The string to convert.
+ @param IsHex Force the string to be treated as a hex number.
+ @param ReturnValue The return value.
- Converts a string to an EFI_GUID. The string must be in the
- xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx format.
-
-Arguments:
-
- GuidBuffer - pointer to destination Guid
- AsciiGuidBuffer - pointer to ascii string
-
-Returns:
-
- EFI_ABORTED Could not convert the string
- EFI_SUCCESS The string was successfully converted
-
---*/
+ @retval EFI_SUCCESS Number successfully converted.
+ @retval EFI_ABORTED Invalid character encountered.
+**/
EFI_STATUS
AsciiStringToUint64 (
IN CONST CHAR8 *AsciiString,
@@ -142,27 +124,15 @@ AsciiStringToUint64 (
)
;
-/*++
+/**
+ This function reads a line, stripping any comments.
-Routine Description:
+ @param InputFile Stream pointer.
+ @param InputBuffer Buffer to read into, must be MAX_LONG_FILE_PATH size.
- Converts a null terminated ascii string that represents a number into a
- UINT64 value. A hex number may be preceded by a 0x, but may not be
- succeeded by an h. A number without 0x or 0X is considered to be base 10
- unless the IsHex input is true.
-
-Arguments:
-
- AsciiString The string to convert.
- IsHex Force the string to be treated as a hex number.
- ReturnValue The return value.
-
-Returns:
-
- EFI_SUCCESS Number successfully converted.
- EFI_ABORTED Invalid character encountered.
-
---*/
+ @retval NULL if error or EOF
+ @retval InputBuffer otherwise
+**/
CHAR8 *
ReadLineInStream (
IN FILE *InputFile,
@@ -170,23 +140,16 @@ ReadLineInStream (
)
;
-/*++
+/**
+ This function parses a stream file from the beginning to find a section.
+ The section string may be anywhere within a line.
-Routine Description:
+ @param InputFile Stream pointer.
+ @param Section Section to search for
- This function reads a line, stripping any comments.
-
-Arguments:
-
- InputFile Stream pointer.
- InputBuffer Buffer to read into, must be MAX_LONG_FILE_PATH size.
-
-Returns:
-
- NULL if error or EOF
- InputBuffer otherwise
-
---*/
+ @retval FALSE if error or EOF
+ @retval TRUE if section found
+**/
BOOLEAN
FindSectionInStream (
IN FILE *InputFile,
@@ -194,25 +157,6 @@ FindSectionInStream (
)
;
-/*++
-
-Routine Description:
-
- This function parses a stream file from the beginning to find a section.
- The section string may be anywhere within a line.
-
-Arguments:
-
- InputFile Stream pointer.
- Section Section to search for
-
-Returns:
-
- FALSE if error or EOF
- TRUE if section found
-
---*/
-
#ifdef __cplusplus
}
#endif
diff --git a/BaseTools/Source/C/Common/PcdValueCommon.c b/BaseTools/Source/C/Common/PcdValueCommon.c
index de3b7446..8f4bcee1 100644
--- a/BaseTools/Source/C/Common/PcdValueCommon.c
+++ b/BaseTools/Source/C/Common/PcdValueCommon.c
@@ -35,6 +35,15 @@ typedef struct {
PCD_ENTRY *PcdList;
UINT32 PcdListLength;
+/**
+ Record new token information
+
+ @param FileBuffer File Buffer to be record
+ @param PcdIndex Index of PCD in database
+ @param TokenIndex Index of Token
+ @param TokenStart Start of Token
+ @param TokenEnd End of Token
+**/
VOID
STATIC
RecordToken (
@@ -44,24 +53,7 @@ RecordToken (
UINT32 TokenStart,
UINT32 TokenEnd
)
-/*++
-Routine Description:
-
- Record new token information
-
-Arguments:
-
- FileBuffer File Buffer to be record
- PcdIndex Index of PCD in database
- TokenIndex Index of Token
- TokenStart Start of Token
- TokenEnd End of Token
-
-Returns:
-
- None
---*/
{
CHAR8 *Token;
@@ -109,6 +101,16 @@ Returns:
}
}
+/**
+ Get PCD index in Pcd database
+
+ @param SkuName SkuName String
+ @param DefaultValueName DefaultValueName String
+ @param TokenSpaceGuidName TokenSpaceGuidName String
+ @param TokenName TokenName String
+
+ @return Index of PCD in Pcd database
+**/
int
STATIC
LookupPcdIndex (
@@ -117,23 +119,6 @@ LookupPcdIndex (
CHAR8 *TokenSpaceGuidName,
CHAR8 *TokenName
)
-/*++
-
-Routine Description:
-
- Get PCD index in Pcd database
-
-Arguments:
-
- SkuName SkuName String
- DefaultValueName DefaultValueName String
- TokenSpaceGuidName TokenSpaceGuidName String
- TokenName TokenName String
-
-Returns:
-
- Index of PCD in Pcd database
---*/
{
UINT32 Index;
@@ -161,6 +146,16 @@ Returns:
return -1;
}
+/**
+ Get PCD value
+
+ @param SkuName SkuName String
+ @param DefaultValueName DefaultValueName String
+ @param TokenSpaceGuidName TokenSpaceGuidName String
+ @param TokenName TokenName String
+
+ @return PCD value
+**/
UINT64
__PcdGet (
CHAR8 *SkuName OPTIONAL,
@@ -168,23 +163,6 @@ __PcdGet (
CHAR8 *TokenSpaceGuidName,
CHAR8 *TokenName
)
-/*++
-
-Routine Description:
-
- Get PCD value
-
-Arguments:
-
- SkuName SkuName String
- DefaultValueName DefaultValueName String
- TokenSpaceGuidName TokenSpaceGuidName String
- TokenName TokenName String
-
-Returns:
-
- PCD value
---*/
{
int Index;
CHAR8 *End;
@@ -212,6 +190,15 @@ Returns:
return 0;
}
+/**
+ Set PCD value
+
+ @param SkuName SkuName String
+ @param DefaultValueName DefaultValueName String
+ @param TokenSpaceGuidName TokenSpaceGuidName String
+ @param TokenName TokenName String
+ @param Value PCD value to be set
+**/
VOID
__PcdSet (
CHAR8 *SkuName OPTIONAL,
@@ -220,24 +207,6 @@ __PcdSet (
CHAR8 *TokenName,
UINT64 Value
)
-/*++
-
-Routine Description:
-
- Set PCD value
-
-Arguments:
-
- SkuName SkuName String
- DefaultValueName DefaultValueName String
- TokenSpaceGuidName TokenSpaceGuidName String
- TokenName TokenName String
- Value PCD value to be set
-
-Returns:
-
- None
---*/
{
int Index;
@@ -275,6 +244,17 @@ Returns:
}
}
+/**
+ Get PCD value buffer
+
+ @param SkuName SkuName String
+ @param DefaultValueName DefaultValueName String
+ @param TokenSpaceGuidName TokenSpaceGuidName String
+ @param TokenName TokenName String
+ @param Size Size of PCD value buffer
+
+ @return PCD value buffer
+**/
VOID *
__PcdGetPtr (
CHAR8 *SkuName OPTIONAL,
@@ -283,24 +263,6 @@ __PcdGetPtr (
CHAR8 *TokenName,
UINT32 *Size
)
-/*++
-
-Routine Description:
-
- Get PCD value buffer
-
-Arguments:
-
- SkuName SkuName String
- DefaultValueName DefaultValueName String
- TokenSpaceGuidName TokenSpaceGuidName String
- TokenName TokenName String
- Size Size of PCD value buffer
-
-Returns:
-
- PCD value buffer
---*/
{
int Index;
CHAR8 *Value;
@@ -341,6 +303,16 @@ Returns:
return 0;
}
+/**
+ Set PCD value buffer
+
+ @param SkuName SkuName String
+ @param DefaultValueName DefaultValueName String
+ @param TokenSpaceGuidName TokenSpaceGuidName String
+ @param TokenName TokenName String
+ @param Size Size of PCD value
+ @param Value Pointer to the updated PCD value buffer
+**/
VOID
__PcdSetPtr (
CHAR8 *SkuName OPTIONAL,
@@ -350,25 +322,6 @@ __PcdSetPtr (
UINT32 Size,
UINT8 *Value
)
-/*++
-
-Routine Description:
-
- Set PCD value buffer
-
-Arguments:
-
- SkuName SkuName String
- DefaultValueName DefaultValueName String
- TokenSpaceGuidName TokenSpaceGuidName String
- TokenName TokenName String
- Size Size of PCD value
- Value Pointer to the updated PCD value buffer
-
-Returns:
-
- None
---*/
{
int Index;
UINT32 ValueIndex;
@@ -400,6 +353,13 @@ Returns:
}
}
+/**
+ Read the file buffer from the input file.
+
+ @param InputFileName Point to the input file name.
+ @param FileBuffer Point to the input file buffer.
+ @param FileSize Size of the file buffer.
+**/
VOID
STATIC
ReadInputFile (
@@ -407,22 +367,6 @@ ReadInputFile (
UINT8 **FileBuffer,
UINT32 *FileSize
)
-/*++
-
-Routine Description:
-
- Read the file buffer from the input file.
-
-Arguments:
-
- InputFileName Point to the input file name.
- FileBuffer Point to the input file buffer.
- FileSize Size of the file buffer.
-
-Returns:
-
- None
---*/
{
FILE *InputFile;
UINT32 BytesRead;
@@ -492,27 +436,18 @@ Returns:
fclose (InputFile);
}
+/**
+ Read the initial PCD value from the input file buffer.
+
+ @param FileBuffer Point to the input file buffer.
+ @param FileSize Size of the file buffer.
+**/
VOID
STATIC
ParseFile (
UINT8 *FileBuffer,
UINT32 FileSize
)
-/*++
-
-Routine Description:
-
- Read the initial PCD value from the input file buffer.
-
-Arguments:
-
- FileBuffer Point to the input file buffer.
- FileSize Size of the file buffer.
-
-Returns:
-
- None
---*/
{
UINT32 Index;
UINT32 NumLines;
@@ -552,25 +487,16 @@ Returns:
}
}
+/**
+ Write the updated PCD value into the output file name.
+
+ @param OutputFileName Point to the output file name.
+**/
VOID
STATIC
WriteOutputFile (
CHAR8 *OutputFileName
)
-/*++
-
-Routine Description:
-
- Write the updated PCD value into the output file name.
-
-Arguments:
-
- OutputFileName Point to the output file name.
-
-Returns:
-
- None
---*/
{
FILE *OutputFile;
UINT32 Index;
@@ -605,26 +531,14 @@ Returns:
}
}
+/**
+ Displays the utility usage syntax to STDOUT
+**/
VOID
STATIC
Usage (
VOID
)
-/*++
-
-Routine Description:
-
- Displays the utility usage syntax to STDOUT
-
-Arguments:
-
- None
-
-Returns:
-
- None
-
---*/
{
fprintf (stdout, "Usage: -i -o \n\n");
fprintf (stdout, "optional arguments:\n");
@@ -635,6 +549,14 @@ Returns:
PCD Database Output file name\n");
}
+/**
+ Parse the input parameters to get the input/output file name.
+
+ @param argc Number of command line parameters.
+ @param argv Array of pointers to parameter strings.
+ @param InputFileName Point to the input file name.
+ @param OutputFileName Point to the output file name.
+**/
VOID
STATIC
ParseArguments (
@@ -643,23 +565,6 @@ ParseArguments (
CHAR8 **InputFileName,
CHAR8 **OutputFileName
)
-/*++
-
-Routine Description:
-
- Parse the input parameters to get the input/output file name.
-
-Arguments:
-
- argc Number of command line parameters.
- argv Array of pointers to parameter strings.
- InputFileName Point to the input file name.
- OutputFileName Point to the output file name.
-
-Returns:
-
- None
---*/
{
if (argc == 1) {
fprintf (stderr, "Missing options\n");
@@ -722,25 +627,19 @@ Returns:
}
}
+/**
+ Main function updates PCD values.
+
+ @param argc Number of command line parameters.
+ @param argv Array of pointers to parameter strings.
+
+ @retval EXIT_SUCCESS
+**/
int
PcdValueMain (
int argc,
char *argv[]
)
-/*++
-
-Routine Description:
-
- Main function updates PCD values.
-
-Arguments:
-
- argc Number of command line parameters.
- argv Array of pointers to parameter strings.
-
-Returns:
- EXIT_SUCCESS
---*/
{
CHAR8 *InputFileName;
CHAR8 *OutputFileName;
diff --git a/BaseTools/Source/C/Common/PcdValueCommon.h b/BaseTools/Source/C/Common/PcdValueCommon.h
index f53d8a4b..2ec8a5a6 100644
--- a/BaseTools/Source/C/Common/PcdValueCommon.h
+++ b/BaseTools/Source/C/Common/PcdValueCommon.h
@@ -24,101 +24,80 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define __STATIC_ASSERT _Static_assert
#endif
+/**
+ Main function updates PCD values. It is auto generated by Build
+**/
VOID
PcdEntryPoint (
VOID
)
-/*++
-Routine Description:
-
- Main function updates PCD values. It is auto generated by Build
-
-Arguments:
-
- None
-
-Returns:
- None
---*/
;
+/**
+ Main function updates PCD values.
+
+ @param argc Number of command line parameters.
+ @param argv Array of pointers to parameter strings.
+
+ @retval EXIT_SUCCESS
+**/
int
PcdValueMain (
int argc,
char *argv[]
)
-/*++
-
-Routine Description:
-
- Main function updates PCD values.
-
-Arguments:
-
- argc Number of command line parameters.
- argv Array of pointers to parameter strings.
-
-Returns:
- EXIT_SUCCESS
---*/
;
-VOID
-__PcdSet (
- CHAR8 *SkuName OPTIONAL,
- CHAR8 *DefaultValueName OPTIONAL,
- CHAR8 *TokenSpaceGuidName,
- CHAR8 *TokenName,
- UINT64 Value
- )
-/*++
-
-Routine Description:
-
- Get PCD value
-
-Arguments:
-
- SkuName SkuName String
- DefaultValueName DefaultValueName String
- TokenSpaceGuidName TokenSpaceGuidName String
- TokenName TokenName String
-
-Returns:
-
- PCD value
---*/
-;
-
-VOID
-__PcdSet (
- CHAR8 *SkuName OPTIONAL,
- CHAR8 *DefaultValueName OPTIONAL,
- CHAR8 *TokenSpaceGuidName,
- CHAR8 *TokenName,
- UINT64 Value
- )
-/*++
-
-Routine Description:
-
+/**
Set PCD value
-Arguments:
-
- SkuName SkuName String
- DefaultValueName DefaultValueName String
- TokenSpaceGuidName TokenSpaceGuidName String
- TokenName TokenName String
- Value PCD value to be set
-
-Returns:
-
- None
---*/
+ @param SkuName SkuName String
+ @param DefaultValueName DefaultValueName String
+ @param TokenSpaceGuidName TokenSpaceGuidName String
+ @param TokenName TokenName String
+ @param Value PCD value to be set
+**/
+VOID
+__PcdSet (
+ CHAR8 *SkuName OPTIONAL,
+ CHAR8 *DefaultValueName OPTIONAL,
+ CHAR8 *TokenSpaceGuidName,
+ CHAR8 *TokenName,
+ UINT64 Value
+ )
;
+/**
+ Get PCD value
+
+ @param SkuName SkuName String
+ @param DefaultValueName DefaultValueName String
+ @param TokenSpaceGuidName TokenSpaceGuidName String
+ @param TokenName TokenName String
+
+ @return PCD value
+**/
+UINT64
+__PcdGet (
+ CHAR8 *SkuName OPTIONAL,
+ CHAR8 *DefaultValueName OPTIONAL,
+ CHAR8 *TokenSpaceGuidName,
+ CHAR8 *TokenName
+ )
+;
+
+/**
+ Get PCD value buffer
+
+ @param SkuName SkuName String
+ @param DefaultValueName DefaultValueName String
+ @param TokenSpaceGuidName TokenSpaceGuidName String
+ @param TokenName TokenName String
+ @param Size Size of PCD value buffer
+
+ @return PCD value buffer
+**/
VOID *
__PcdGetPtr (
CHAR8 *SkuName OPTIONAL,
@@ -127,26 +106,18 @@ __PcdGetPtr (
CHAR8 *TokenName,
UINT32 *Size
)
-/*++
-
-Routine Description:
-
- Get PCD value buffer
-
-Arguments:
-
- SkuName SkuName String
- DefaultValueName DefaultValueName String
- TokenSpaceGuidName TokenSpaceGuidName String
- TokenName TokenName String
- Size Size of PCD value buffer
-
-Returns:
-
- PCD value buffer
---*/
;
+/**
+ Set PCD value buffer
+
+ @param SkuName SkuName String
+ @param DefaultValueName DefaultValueName String
+ @param TokenSpaceGuidName TokenSpaceGuidName String
+ @param TokenName TokenName String
+ @param Size Size of PCD value
+ @param Value Pointer to the updated PCD value buffer
+**/
VOID
__PcdSetPtr (
CHAR8 *SkuName OPTIONAL,
@@ -156,25 +127,6 @@ __PcdSetPtr (
UINT32 Size,
UINT8 *Value
)
-/*++
-
-Routine Description:
-
- Set PCD value buffer
-
-Arguments:
-
- SkuName SkuName String
- DefaultValueName DefaultValueName String
- TokenSpaceGuidName TokenSpaceGuidName String
- TokenName TokenName String
- Size Size of PCD value
- Value Pointer to the updated PCD value buffer
-
-Returns:
-
- None
---*/
;
#define PcdGet(A, B, C, D) __PcdGet(#A, #B, #C, #D)
diff --git a/BaseTools/Source/C/Common/PeCoffLoaderEx.c b/BaseTools/Source/C/Common/PeCoffLoaderEx.c
index 15788272..c7fa7f49 100644
--- a/BaseTools/Source/C/Common/PeCoffLoaderEx.c
+++ b/BaseTools/Source/C/Common/PeCoffLoaderEx.c
@@ -65,6 +65,16 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
UINT32 *RiscVHi20Fixup = NULL;
+/**
+ Performs an IA-32 specific relocation fixup
+
+ @param Reloc Pointer to the relocation record
+ @param Fixup Pointer to the address to fix up
+ @param FixupData Pointer to a buffer to log the fixups
+ @param Adjust The offset to adjust the fixup
+
+ @retval EFI_UNSUPPORTED - Unsupported now
+**/
RETURN_STATUS
PeCoffLoaderRelocateIa32Image (
IN UINT16 *Reloc,
@@ -72,52 +82,20 @@ PeCoffLoaderRelocateIa32Image (
IN OUT CHAR8 **FixupData,
IN UINT64 Adjust
)
-/*++
-
-Routine Description:
-
- Performs an IA-32 specific relocation fixup
-
-Arguments:
-
- Reloc - Pointer to the relocation record
-
- Fixup - Pointer to the address to fix up
-
- FixupData - Pointer to a buffer to log the fixups
-
- Adjust - The offset to adjust the fixup
-
-Returns:
-
- EFI_UNSUPPORTED - Unsupported now
-
---*/
{
return RETURN_UNSUPPORTED;
}
-/*++
-
-Routine Description:
-
+/**
Performs an RISC-V specific relocation fixup
-Arguments:
+ @param Reloc Pointer to the relocation record
+ @param Fixup Pointer to the address to fix up
+ @param FixupData Pointer to a buffer to log the fixups
+ @param Adjust The offset to adjust the fixup
- Reloc - Pointer to the relocation record
-
- Fixup - Pointer to the address to fix up
-
- FixupData - Pointer to a buffer to log the fixups
-
- Adjust - The offset to adjust the fixup
-
-Returns:
-
- Status code
-
---*/
+ @return Status code
+**/
RETURN_STATUS
PeCoffLoaderRelocateRiscVImage (
IN UINT16 *Reloc,
diff --git a/BaseTools/Source/C/Common/SimpleFileParsing.c b/BaseTools/Source/C/Common/SimpleFileParsing.c
index 337899ed..2dcc8659 100644
--- a/BaseTools/Source/C/Common/SimpleFileParsing.c
+++ b/BaseTools/Source/C/Common/SimpleFileParsing.c
@@ -152,65 +152,43 @@ SetFilePosition (
FILE_POSITION *Fpos
);
+/**
+ @retval STATUS_SUCCESS always
+**/
STATUS
SFPInit (
VOID
)
-/*++
-
-Routine Description:
-
-Arguments:
- None.
-
-Returns:
- STATUS_SUCCESS always
-
---*/
{
memset ((VOID *) &mGlobals, 0, sizeof (mGlobals));
return STATUS_SUCCESS;
}
+/**
+ Return the line number of the file we're parsing. Used
+ for error reporting purposes.
+
+ @return The line number, or 0 if no file is being processed
+**/
UINTN
SFPGetLineNumber (
VOID
)
-/*++
-
-Routine Description:
- Return the line number of the file we're parsing. Used
- for error reporting purposes.
-
-Arguments:
- None.
-
-Returns:
- The line number, or 0 if no file is being processed
-
---*/
{
return mGlobals.SourceFile.LineNum;
}
+/**
+ Return the name of the file we're parsing. Used
+ for error reporting purposes.
+
+ @return A pointer to the file name. Null if no file is being
+ processed.
+**/
CHAR8 *
SFPGetFileName (
VOID
)
-/*++
-
-Routine Description:
- Return the name of the file we're parsing. Used
- for error reporting purposes.
-
-Arguments:
- None.
-
-Returns:
- A pointer to the file name. Null if no file is being
- processed.
-
---*/
{
if (mGlobals.SourceFile.FileName[0]) {
return mGlobals.SourceFile.FileName;
@@ -219,22 +197,15 @@ Returns:
return NULL;
}
+/**
+ Open a file for parsing.
+
+ @param FileName name of the file to parse
+**/
STATUS
SFPOpenFile (
CHAR8 *FileName
)
-/*++
-
-Routine Description:
- Open a file for parsing.
-
-Arguments:
- FileName - name of the file to parse
-
-Returns:
-
-
---*/
{
STATUS Status;
t_strcpy (mGlobals.SourceFile.FileName, FileName);
@@ -242,31 +213,26 @@ Returns:
return Status;
}
+/**
+ Check to see if the specified token is found at
+ the current position in the input file.
+
+ @note:
+ We do a simple string comparison on this function. It is
+ the responsibility of the caller to ensure that the token
+ is not a subset of some other token.
+
+ The file pointer is advanced past the token in the input file.
+
+ @param Str the token to look for
+
+ @retval TRUE the token is next
+ @retval FALSE the token is not next
+**/
BOOLEAN
SFPIsToken (
CHAR8 *Str
)
-/*++
-
-Routine Description:
- Check to see if the specified token is found at
- the current position in the input file.
-
-Arguments:
- Str - the token to look for
-
-Returns:
- TRUE - the token is next
- FALSE - the token is not next
-
-Notes:
- We do a simple string comparison on this function. It is
- the responsibility of the caller to ensure that the token
- is not a subset of some other token.
-
- The file pointer is advanced past the token in the input file.
-
---*/
{
UINTN Len;
SkipWhiteSpace (&mGlobals.SourceFile);
@@ -286,28 +252,23 @@ Notes:
return FALSE;
}
+/**
+ Check to see if the specified keyword is found at
+ the current position in the input file.
+
+ @note:
+ A keyword is defined as a "special" string that has a non-alphanumeric
+ character following it.
+
+ @param Str keyword to look for
+
+ @retval TRUE the keyword is next
+ @retval FALSE the keyword is not next
+**/
BOOLEAN
SFPIsKeyword (
CHAR8 *Str
)
-/*++
-
-Routine Description:
- Check to see if the specified keyword is found at
- the current position in the input file.
-
-Arguments:
- Str - keyword to look for
-
-Returns:
- TRUE - the keyword is next
- FALSE - the keyword is not next
-
-Notes:
- A keyword is defined as a "special" string that has a non-alphanumeric
- character following it.
-
---*/
{
UINTN Len;
SkipWhiteSpace (&mGlobals.SourceFile);
@@ -331,30 +292,25 @@ Notes:
return FALSE;
}
+/**
+ Get the next token from the input stream.
+
+ @note:
+ Preceding white space is ignored.
+ The parser's buffer pointer is advanced past the end of the
+ token.
+
+ @param Str pointer to a copy of the next token
+ @param Len size of buffer pointed to by Str
+
+ @retval TRUE next token successfully returned
+ @retval FALSE otherwise
+**/
BOOLEAN
SFPGetNextToken (
CHAR8 *Str,
UINTN Len
)
-/*++
-
-Routine Description:
- Get the next token from the input stream.
-
-Arguments:
- Str - pointer to a copy of the next token
- Len - size of buffer pointed to by Str
-
-Returns:
- TRUE - next token successfully returned
- FALSE - otherwise
-
-Notes:
- Preceding white space is ignored.
- The parser's buffer pointer is advanced past the end of the
- token.
-
---*/
{
UINTN Index;
CHAR8 TempChar;
@@ -436,25 +392,20 @@ Notes:
return FALSE;
}
+/**
+ Parse a GUID from the input stream. Stop when you discover white space.
+
+ @param Str pointer to a copy of the next token
+ @param Len size of buffer pointed to by Str
+
+ @retval TRUE GUID string returned successfully
+ @retval FALSE otherwise
+**/
BOOLEAN
SFPGetGuidToken (
CHAR8 *Str,
UINT32 Len
)
-/*++
-
-Routine Description:
- Parse a GUID from the input stream. Stop when you discover white space.
-
-Arguments:
- Str - pointer to a copy of the next token
- Len - size of buffer pointed to by Str
-
-Returns:
- TRUE - GUID string returned successfully
- FALSE - otherwise
-
---*/
{
UINT32 Index;
SkipWhiteSpace (&mGlobals.SourceFile);
@@ -505,24 +456,19 @@ SFPSkipToToken (
return FALSE;
}
+/**
+ Check the token at the current file position for a numeric value.
+ May be either decimal or hex.
+
+ @param Value pointer where to store the value
+
+ @retval FALSE current token is not a number
+ @retval TRUE current token is a number
+**/
BOOLEAN
SFPGetNumber (
UINTN *Value
)
-/*++
-
-Routine Description:
- Check the token at the current file position for a numeric value.
- May be either decimal or hex.
-
-Arguments:
- Value - pointer where to store the value
-
-Returns:
- FALSE - current token is not a number
- TRUE - current token is a number
-
---*/
{
int Val;
@@ -561,23 +507,16 @@ Returns:
}
}
+/**
+ Close the file being parsed.
+
+ @retval STATUS_SUCCESS the file was closed
+ @retval STATUS_ERROR no file is currently open
+**/
STATUS
SFPCloseFile (
VOID
)
-/*++
-
-Routine Description:
- Close the file being parsed.
-
-Arguments:
- None.
-
-Returns:
- STATUS_SUCCESS - the file was closed
- STATUS_ERROR - no file is currently open
-
---*/
{
if (mGlobals.SourceFile.FileBuffer != NULL) {
free (mGlobals.SourceFile.FileBuffer);
@@ -588,28 +527,20 @@ Returns:
return STATUS_ERROR;
}
+/**
+ Given a source file, open the file and parse it
+
+ @param SourceFile name of file to parse
+ @param ParentSourceFile for error reporting purposes, the file that #included SourceFile.
+
+ @return Standard status.
+**/
STATIC
STATUS
ProcessIncludeFile (
SOURCE_FILE *SourceFile,
SOURCE_FILE *ParentSourceFile
)
-/*++
-
-Routine Description:
-
- Given a source file, open the file and parse it
-
-Arguments:
-
- SourceFile - name of file to parse
- ParentSourceFile - for error reporting purposes, the file that #included SourceFile.
-
-Returns:
-
- Standard status.
-
---*/
{
STATIC UINTN NestDepth = 0;
CHAR8 FoundFileName[MAX_PATH];
@@ -657,27 +588,19 @@ Finish:
return Status;
}
+/**
+ Given a source file that's been opened, read the contents into an internal
+ buffer and pre-process it to remove comments.
+
+ @param SourceFile structure containing info on the file to process
+
+ @return Standard status.
+**/
STATIC
STATUS
ProcessFile (
SOURCE_FILE *SourceFile
)
-/*++
-
-Routine Description:
-
- Given a source file that's been opened, read the contents into an internal
- buffer and pre-process it to remove comments.
-
-Arguments:
-
- SourceFile - structure containing info on the file to process
-
-Returns:
-
- Standard status.
-
---*/
{
//
// Get the file size, and then read the entire thing into memory.
@@ -706,24 +629,17 @@ Returns:
return STATUS_SUCCESS;
}
+/**
+ Preprocess a file to replace all carriage returns with NULLs so
+ we can print lines (as part of error messages) from the file to the screen.
+
+ @param SourceFile structure that we use to keep track of an input file.
+**/
STATIC
VOID
PreprocessFile (
SOURCE_FILE *SourceFile
)
-/*++
-
-Routine Description:
- Preprocess a file to replace all carriage returns with NULLs so
- we can print lines (as part of error messages) from the file to the screen.
-
-Arguments:
- SourceFile - structure that we use to keep track of an input file.
-
-Returns:
- Nothing.
-
---*/
{
BOOLEAN InComment;
BOOLEAN SlashSlashComment;
@@ -812,26 +728,21 @@ Returns:
}
}
+/**
+ Retrieve a quoted-string from the input file.
+
+ @param Str pointer to a copy of the quoted string parsed
+ @param Length size of buffer pointed to by Str
+
+ @retval TRUE next token in input stream was a quoted string, and
+ the string value was returned in Str
+ @retval FALSE otherwise
+**/
BOOLEAN
SFPGetQuotedString (
CHAR8 *Str,
INTN Length
)
-/*++
-
-Routine Description:
- Retrieve a quoted-string from the input file.
-
-Arguments:
- Str - pointer to a copy of the quoted string parsed
- Length - size of buffer pointed to by Str
-
-Returns:
- TRUE - next token in input stream was a quoted string, and
- the string value was returned in Str
- FALSE - otherwise
-
---*/
{
SkipWhiteSpace (&mGlobals.SourceFile);
if (EndOfFile (&mGlobals.SourceFile)) {
@@ -866,24 +777,17 @@ Returns:
return FALSE;
}
+/**
+ Return TRUE of FALSE to indicate whether or not we've reached the end of the
+ file we're parsing.
+
+ @retval TRUE EOF reached
+ @retval FALSE otherwise
+**/
BOOLEAN
SFPIsEOF (
VOID
)
-/*++
-
-Routine Description:
- Return TRUE of FALSE to indicate whether or not we've reached the end of the
- file we're parsing.
-
-Arguments:
- NA
-
-Returns:
- TRUE - EOF reached
- FALSE - otherwise
-
---*/
{
SkipWhiteSpace (&mGlobals.SourceFile);
return EndOfFile (&mGlobals.SourceFile);
@@ -1112,27 +1016,22 @@ SkipWhiteSpace (
return Count;
}
+/**
+ Compare two strings for equality. The string pointed to by 'Buffer' may or may not be null-terminated,
+ so only compare up to the length of Str.
+
+ @param Buffer pointer to first (possibly not null-terminated) string
+ @param Str pointer to null-terminated string to compare to Buffer
+
+ @retval Number of bytes matched if exact match
+ @retval 0 if Buffer does not start with Str
+**/
STATIC
UINTN
t_strcmp (
CHAR8 *Buffer,
CHAR8 *Str
)
-/*++
-
-Routine Description:
- Compare two strings for equality. The string pointed to by 'Buffer' may or may not be null-terminated,
- so only compare up to the length of Str.
-
-Arguments:
- Buffer - pointer to first (possibly not null-terminated) string
- Str - pointer to null-terminated string to compare to Buffer
-
-Returns:
- Number of bytes matched if exact match
- 0 if Buffer does not start with Str
-
---*/
{
UINTN Len;
@@ -1245,28 +1144,23 @@ GetHexChars (
return Len;
}
+/**
+ Parse a GUID from the input stream. Stop when you discover white space.
+
+ GUID styles
+ Style[0] 12345678-1234-5678-AAAA-BBBBCCCCDDDD
+
+ @param GuidStyle Style of the following GUID token
+ @param Value pointer to EFI_GUID struct for output
+
+ @retval TRUE GUID string parsed successfully
+ @retval FALSE otherwise
+**/
BOOLEAN
SFPGetGuid (
INTN GuidStyle,
EFI_GUID *Value
)
-/*++
-
-Routine Description:
- Parse a GUID from the input stream. Stop when you discover white space.
-
-Arguments:
- GuidStyle - Style of the following GUID token
- Value - pointer to EFI_GUID struct for output
-
-Returns:
- TRUE - GUID string parsed successfully
- FALSE - otherwise
-
- GUID styles
- Style[0] 12345678-1234-5678-AAAA-BBBBCCCCDDDD
-
---*/
{
INT32 Value32;
UINT32 Index;
diff --git a/BaseTools/Source/C/Common/StringFuncs.c b/BaseTools/Source/C/Common/StringFuncs.c
index 2d092869..90c53541 100644
--- a/BaseTools/Source/C/Common/StringFuncs.c
+++ b/BaseTools/Source/C/Common/StringFuncs.c
@@ -14,25 +14,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// Functions implementations
//
+/**
+ Allocates a new string and copies 'String' to clone it
+
+ @param String The string to clone
+
+ @return CHAR8* - NULL if there are not enough resources
+**/
CHAR8*
CloneString (
IN CHAR8 *String
)
-/*++
-
-Routine Description:
-
- Allocates a new string and copies 'String' to clone it
-
-Arguments:
-
- String The string to clone
-
-Returns:
-
- CHAR8* - NULL if there are not enough resources
-
---*/
{
CHAR8* NewString;
@@ -44,26 +36,17 @@ Returns:
return NewString;
}
+/**
+ Remove all comments, leading and trailing whitespace from the string.
+ @param String The string to 'strip'
+
+ @return EFI_STATUS
+**/
EFI_STATUS
StripInfDscStringInPlace (
IN CHAR8 *String
)
-/*++
-
-Routine Description:
-
- Remove all comments, leading and trailing whitespace from the string.
-
-Arguments:
-
- String The string to 'strip'
-
-Returns:
-
- EFI_STATUS
-
---*/
{
CHAR8 *Pos;
@@ -110,27 +93,18 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ Creates and returns a 'split' STRING_LIST by splitting the string
+ on whitespace boundaries.
+ @param String The string to 'split'
+
+ @return EFI_STATUS
+**/
STRING_LIST*
SplitStringByWhitespace (
IN CHAR8 *String
)
-/*++
-
-Routine Description:
-
- Creates and returns a 'split' STRING_LIST by splitting the string
- on whitespace boundaries.
-
-Arguments:
-
- String The string to 'split'
-
-Returns:
-
- EFI_STATUS
-
---*/
{
CHAR8 *Pos;
CHAR8 *EndOfSubString;
@@ -172,21 +146,14 @@ Returns:
return Output;
}
+/**
+ Creates a new STRING_LIST with 0 strings.
+ @return STRING_LIST* - Null if there is not enough resources to create the object.
+**/
STRING_LIST*
NewStringList (
)
-/*++
-
-Routine Description:
-
- Creates a new STRING_LIST with 0 strings.
-
-Returns:
-
- STRING_LIST* - Null if there is not enough resources to create the object.
-
---*/
{
STRING_LIST *NewList;
NewList = AllocateStringListStruct (0);
@@ -196,24 +163,17 @@ Returns:
return NewList;
}
+/**
+ Adds String to StringList. A new copy of String is made before it is
+ added to StringList.
+ @return EFI_STATUS
+**/
EFI_STATUS
AppendCopyOfStringToList (
IN OUT STRING_LIST **StringList,
IN CHAR8 *String
)
-/*++
-
-Routine Description:
-
- Adds String to StringList. A new copy of String is made before it is
- added to StringList.
-
-Returns:
-
- EFI_STATUS
-
---*/
{
STRING_LIST *OldList;
STRING_LIST *NewList;
@@ -245,27 +205,18 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ Removes the last string from StringList and frees the memory associated
+ with it.
+ @param StringList The string list to remove the string from
+
+ @return EFI_STATUS
+**/
EFI_STATUS
RemoveLastStringFromList (
IN STRING_LIST *StringList
)
-/*++
-
-Routine Description:
-
- Removes the last string from StringList and frees the memory associated
- with it.
-
-Arguments:
-
- StringList The string list to remove the string from
-
-Returns:
-
- EFI_STATUS
-
---*/
{
if (StringList->Count == 0) {
return EFI_INVALID_PARAMETER;
@@ -276,49 +227,30 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ Allocates a STRING_LIST structure that can store StringCount strings.
+ @param StringCount The number of strings that need to be stored
+
+ @return EFI_STATUS
+**/
STRING_LIST*
AllocateStringListStruct (
IN UINTN StringCount
)
-/*++
-
-Routine Description:
-
- Allocates a STRING_LIST structure that can store StringCount strings.
-
-Arguments:
-
- StringCount The number of strings that need to be stored
-
-Returns:
-
- EFI_STATUS
-
---*/
{
return malloc (OFFSET_OF(STRING_LIST, Strings[StringCount + 1]));
}
+/**
+ Frees all memory associated with StringList.
+ @param StringList The string list to free
+**/
VOID
FreeStringList (
IN STRING_LIST *StringList
)
-/*++
-
-Routine Description:
-
- Frees all memory associated with StringList.
-
-Arguments:
-
- StringList The string list to free
-
-Returns:
-
- VOID
---*/
{
while (StringList->Count > 0) {
RemoveLastStringFromList (StringList);
@@ -327,27 +259,18 @@ Returns:
free (StringList);
}
+/**
+ Generates a string that represents the STRING_LIST
+ @param StringList The string list to convert to a string
+
+ @return CHAR8* - The string list represented with a single string. The returned
+ string must be freed by the caller.
+**/
CHAR8*
StringListToString (
IN STRING_LIST *StringList
)
-/*++
-
-Routine Description:
-
- Generates a string that represents the STRING_LIST
-
-Arguments:
-
- StringList The string list to convert to a string
-
-Returns:
-
- CHAR8* - The string list represented with a single string. The returned
- string must be freed by the caller.
-
---*/
{
UINTN Count;
UINTN Length;
@@ -381,26 +304,17 @@ Returns:
return NewString;
}
+/**
+ Prints out the string list
+ @param StringList The string list to print
+
+ @return EFI_STATUS
+**/
VOID
PrintStringList (
IN STRING_LIST *StringList
)
-/*++
-
-Routine Description:
-
- Prints out the string list
-
-Arguments:
-
- StringList The string list to print
-
-Returns:
-
- EFI_STATUS
-
---*/
{
CHAR8* String;
String = StringListToString (StringList);
diff --git a/BaseTools/Source/C/Common/StringFuncs.h b/BaseTools/Source/C/Common/StringFuncs.h
index 937abcd9..e29d9be4 100644
--- a/BaseTools/Source/C/Common/StringFuncs.h
+++ b/BaseTools/Source/C/Common/StringFuncs.h
@@ -29,216 +29,139 @@ typedef struct {
// Functions declarations
//
+/**
+ Allocates a new string and copies 'String' to clone it
+
+ @param String The string to clone
+
+ @return CHAR8* - NULL if there are not enough resources
+**/
CHAR8*
CloneString (
IN CHAR8 *String
)
;
+
/**
+ Remove all comments, leading and trailing whitespace from the string.
-Routine Description:
-
- Allocates a new string and copies 'String' to clone it
-
-Arguments:
-
- String The string to clone
-
-Returns:
-
- CHAR8* - NULL if there are not enough resources
+ @param String The string to 'strip'
+ @return EFI_STATUS
**/
-
-
EFI_STATUS
StripInfDscStringInPlace (
IN CHAR8 *String
)
;
+
/**
+ Creates and returns a 'split' STRING_LIST by splitting the string
+ on whitespace boundaries.
-Routine Description:
-
- Remove all comments, leading and trailing whitespace from the string.
-
-Arguments:
-
- String The string to 'strip'
-
-Returns:
-
- EFI_STATUS
+ @param String The string to 'split'
+ @return EFI_STATUS
**/
-
-
STRING_LIST*
SplitStringByWhitespace (
IN CHAR8 *String
)
;
+
/**
+ Creates a new STRING_LIST with 0 strings.
-Routine Description:
-
- Creates and returns a 'split' STRING_LIST by splitting the string
- on whitespace boundaries.
-
-Arguments:
-
- String The string to 'split'
-
-Returns:
-
- EFI_STATUS
-
+ @return STRING_LIST* - Null if there is not enough resources to create the object.
**/
-
-
STRING_LIST*
NewStringList (
)
;
+
+
/**
+ Adds String to StringList. A new copy of String is made before it is
+ added to StringList.
-Routine Description:
-
- Creates a new STRING_LIST with 0 strings.
-
-Returns:
-
- STRING_LIST* - Null if there is not enough resources to create the object.
-
+ @return EFI_STATUS
**/
-
-
EFI_STATUS
AppendCopyOfStringToList (
IN OUT STRING_LIST **StringList,
IN CHAR8 *String
)
;
+
/**
+ Removes the last string from StringList and frees the memory associated
+ with it.
-Routine Description:
-
- Adds String to StringList. A new copy of String is made before it is
- added to StringList.
-
-Returns:
-
- EFI_STATUS
+ @param StringList The string list to remove the string from
+ @return EFI_STATUS
**/
-
-
EFI_STATUS
RemoveLastStringFromList (
IN STRING_LIST *StringList
)
;
+
+
/**
+ Allocates a STRING_LIST structure that can store StringCount strings.
-Routine Description:
-
- Removes the last string from StringList and frees the memory associated
- with it.
-
-Arguments:
-
- StringList The string list to remove the string from
-
-Returns:
-
- EFI_STATUS
+ @param StringCount The number of strings that need to be stored
+ @return EFI_STATUS
**/
-
-
STRING_LIST*
AllocateStringListStruct (
IN UINTN StringCount
)
;
+
+
/**
+ Frees all memory associated with StringList.
-Routine Description:
-
- Allocates a STRING_LIST structure that can store StringCount strings.
-
-Arguments:
-
- StringCount The number of strings that need to be stored
-
-Returns:
-
- EFI_STATUS
+ @param StringList The string list to free
+ @return EFI_STATUS
**/
-
-
VOID
FreeStringList (
IN STRING_LIST *StringList
)
;
+
+
/**
+ Generates a string that represents the STRING_LIST
-Routine Description:
-
- Frees all memory associated with StringList.
-
-Arguments:
-
- StringList The string list to free
-
-Returns:
-
- EFI_STATUS
+ @param StringList The string list to convert to a string
+ @return CHAR8* The string list represented with a single string. The returned
+ string must be freed by the caller.
**/
-
-
CHAR8*
StringListToString (
IN STRING_LIST *StringList
)
;
+
+
/**
+ Prints out the string list
-Routine Description:
-
- Generates a string that represents the STRING_LIST
-
-Arguments:
-
- StringList The string list to convert to a string
-
-Returns:
-
- CHAR8* - The string list represented with a single string. The returned
- string must be freed by the caller.
-
+ @param StringList The string list to print
**/
-
-
VOID
PrintStringList (
IN STRING_LIST *StringList
)
;
-/**
-Routine Description:
-
- Prints out the string list
-
-Arguments:
-
- StringList The string list to print
-
-**/
#endif
diff --git a/BaseTools/Source/C/Common/TianoCompress.c b/BaseTools/Source/C/Common/TianoCompress.c
index b5aea760..d53ee59a 100644
--- a/BaseTools/Source/C/Common/TianoCompress.c
+++ b/BaseTools/Source/C/Common/TianoCompress.c
@@ -256,6 +256,25 @@ STATIC NODE mPos, mMatchPos, mAvail, *mPosition, *mParent, *mPrev, *mNext = NU
//
// functions
//
+
+/**
+ The internal implementation of [Efi/Tiano]Compress().
+
+ @param SrcBuffer The buffer storing the source data
+ @param SrcSize The size of source data
+ @param DstBuffer The buffer to store the compressed data
+ @param DstSize On input, the size of DstBuffer; On output,
+ the size of the actual compressed data.
+ @param Version The version of de/compression algorithm.
+ Version 1 for UEFI 2.0 de/compression algorithm.
+ Version 2 for Tiano de/compression algorithm.
+
+ @retval EFI_BUFFER_TOO_SMALL The DstBuffer is too small. In this case,
+ DstSize contains the size needed.
+ @retval EFI_SUCCESS Compression is successful.
+ @retval EFI_OUT_OF_RESOURCES No resource to complete function.
+ @retval EFI_INVALID_PARAMETER Parameter supplied is wrong.
+**/
EFI_STATUS
TianoCompress (
IN UINT8 *SrcBuffer,
@@ -263,32 +282,6 @@ TianoCompress (
IN UINT8 *DstBuffer,
IN OUT UINT32 *DstSize
)
-/*++
-
-Routine Description:
-
- The internal implementation of [Efi/Tiano]Compress().
-
-Arguments:
-
- SrcBuffer - The buffer storing the source data
- SrcSize - The size of source data
- DstBuffer - The buffer to store the compressed data
- DstSize - On input, the size of DstBuffer; On output,
- the size of the actual compressed data.
- Version - The version of de/compression algorithm.
- Version 1 for UEFI 2.0 de/compression algorithm.
- Version 2 for Tiano de/compression algorithm.
-
-Returns:
-
- EFI_BUFFER_TOO_SMALL - The DstBuffer is too small. In this case,
- DstSize contains the size needed.
- EFI_SUCCESS - Compression is successful.
- EFI_OUT_OF_RESOURCES - No resource to complete function.
- EFI_INVALID_PARAMETER - Parameter supplied is wrong.
-
---*/
{
EFI_STATUS Status;
@@ -351,24 +344,16 @@ Returns:
}
+/**
+ Put a dword to output stream
+
+ @param Data the dword to put
+**/
STATIC
VOID
PutDword (
IN UINT32 Data
)
-/*++
-
-Routine Description:
-
- Put a dword to output stream
-
-Arguments:
-
- Data - the dword to put
-
-Returns: (VOID)
-
---*/
{
if (mDst < mDstUpperLimit) {
*mDst++ = (UINT8) (((UINT8) (Data)) & 0xff);
@@ -387,26 +372,17 @@ Returns: (VOID)
}
}
+/**
+ Allocate memory spaces for data structures used in compression process
+
+ @retval EFI_SUCCESS Memory is allocated successfully
+ @retval EFI_OUT_OF_RESOURCES Allocation fails
+**/
STATIC
EFI_STATUS
AllocateMemory (
VOID
)
-/*++
-
-Routine Description:
-
- Allocate memory spaces for data structures used in compression process
-
-Arguments:
- VOID
-
-Returns:
-
- EFI_SUCCESS - Memory is allocated successfully
- EFI_OUT_OF_RESOURCES - Allocation fails
-
---*/
{
UINT32 Index;
@@ -445,21 +421,13 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ Called when compression is completed to free memory previously allocated.
+**/
VOID
FreeMemory (
VOID
)
-/*++
-
-Routine Description:
-
- Called when compression is completed to free memory previously allocated.
-
-Arguments: (VOID)
-
-Returns: (VOID)
-
---*/
{
if (mText != NULL) {
free (mText);
@@ -496,22 +464,14 @@ Returns: (VOID)
return ;
}
+/**
+ Initialize String Info Log data structures
+**/
STATIC
VOID
InitSlide (
VOID
)
-/*++
-
-Routine Description:
-
- Initialize String Info Log data structures
-
-Arguments: (VOID)
-
-Returns: (VOID)
-
---*/
{
NODE Index;
@@ -535,28 +495,20 @@ Returns: (VOID)
}
}
+/**
+ Find child node given the parent node and the edge character
+
+ @param NodeQ the parent node
+ @param CharC the edge character
+
+ @return The child node (NIL if not found)
+**/
STATIC
NODE
Child (
IN NODE NodeQ,
IN UINT8 CharC
)
-/*++
-
-Routine Description:
-
- Find child node given the parent node and the edge character
-
-Arguments:
-
- NodeQ - the parent node
- CharC - the edge character
-
-Returns:
-
- The child node (NIL if not found)
-
---*/
{
NODE NodeR;
@@ -572,6 +524,13 @@ Returns:
return NodeR;
}
+/**
+ Create a new child for a given parent node.
+
+ @param Parent the parent node
+ @param CharC the edge character
+ @param Child the child node
+**/
STATIC
VOID
MakeChild (
@@ -579,21 +538,6 @@ MakeChild (
IN UINT8 CharC,
IN NODE Child
)
-/*++
-
-Routine Description:
-
- Create a new child for a given parent node.
-
-Arguments:
-
- Parent - the parent node
- CharC - the edge character
- Child - the child node
-
-Returns: (VOID)
-
---*/
{
NODE Node1;
NODE Node2;
@@ -608,24 +552,16 @@ Returns: (VOID)
mChildCount[Parent]++;
}
+/**
+ Split a node.
+
+ @param Old the node to split
+**/
STATIC
VOID
Split (
NODE Old
)
-/*++
-
-Routine Description:
-
- Split a node.
-
-Arguments:
-
- Old - the node to split
-
-Returns: (VOID)
-
---*/
{
NODE New;
NODE TempNode;
@@ -646,22 +582,14 @@ Returns: (VOID)
MakeChild (New, mText[mPos + mMatchLen], mPos);
}
+/**
+ Insert string info for current position into the String Info Log
+**/
STATIC
VOID
InsertNode (
VOID
)
-/*++
-
-Routine Description:
-
- Insert string info for current position into the String Info Log
-
-Arguments: (VOID)
-
-Returns: (VOID)
-
---*/
{
NODE NodeQ;
NODE NodeR;
@@ -778,23 +706,15 @@ Returns: (VOID)
}
+/**
+ Delete outdated string info. (The Usage of PERC_FLAG
+ ensures a clean deletion)
+**/
STATIC
VOID
DeleteNode (
VOID
)
-/*++
-
-Routine Description:
-
- Delete outdated string info. (The Usage of PERC_FLAG
- ensures a clean deletion)
-
-Arguments: (VOID)
-
-Returns: (VOID)
-
---*/
{
NODE NodeQ;
NODE NodeR;
@@ -873,23 +793,15 @@ Returns: (VOID)
mAvail = NodeR;
}
+/**
+ Advance the current position (read in new data if needed).
+ Delete outdated string info. Find a match string for current position.
+**/
STATIC
VOID
GetNextMatch (
VOID
)
-/*++
-
-Routine Description:
-
- Advance the current position (read in new data if needed).
- Delete outdated string info. Find a match string for current position.
-
-Arguments: (VOID)
-
-Returns: (VOID)
-
---*/
{
INT32 Number;
@@ -906,25 +818,17 @@ Returns: (VOID)
InsertNode ();
}
+/**
+ The main controlling routine for compression process.
+
+ @retval EFI_SUCCESS The compression is successful
+ @retval EFI_OUT_0F_RESOURCES Not enough memory for compression process
+**/
STATIC
EFI_STATUS
Encode (
VOID
)
-/*++
-
-Routine Description:
-
- The main controlling routine for compression process.
-
-Arguments: (VOID)
-
-Returns:
-
- EFI_SUCCESS - The compression is successful
- EFI_OUT_0F_RESOURCES - Not enough memory for compression process
-
---*/
{
EFI_STATUS Status;
INT32 LastMatchLen;
@@ -996,22 +900,14 @@ Returns:
return EFI_SUCCESS;
}
+/**
+ Count the frequencies for the Extra Set
+**/
STATIC
VOID
CountTFreq (
VOID
)
-/*++
-
-Routine Description:
-
- Count the frequencies for the Extra Set
-
-Arguments: (VOID)
-
-Returns: (VOID)
-
---*/
{
INT32 Index;
INT32 Index3;
@@ -1053,6 +949,13 @@ Returns: (VOID)
}
}
+/**
+ Outputs the code length array for the Extra Set or the Position Set.
+
+ @param Number the number of symbols
+ @param nbit the number of bits needed to represent 'n'
+ @param Special the special symbol that needs to be take care of
+**/
STATIC
VOID
WritePTLen (
@@ -1060,21 +963,6 @@ WritePTLen (
IN INT32 nbit,
IN INT32 Special
)
-/*++
-
-Routine Description:
-
- Outputs the code length array for the Extra Set or the Position Set.
-
-Arguments:
-
- Number - the number of symbols
- nbit - the number of bits needed to represent 'n'
- Special - the special symbol that needs to be take care of
-
-Returns: (VOID)
-
---*/
{
INT32 Index;
INT32 Index3;
@@ -1103,22 +991,14 @@ Returns: (VOID)
}
}
+/**
+ Outputs the code length array for Char&Length Set
+**/
STATIC
VOID
WriteCLen (
VOID
)
-/*++
-
-Routine Description:
-
- Outputs the code length array for Char&Length Set
-
-Arguments: (VOID)
-
-Returns: (VOID)
-
---*/
{
INT32 Index;
INT32 Index3;
@@ -1193,24 +1073,14 @@ EncodeP (
}
}
+/**
+ Huffman code the block and output it.
+**/
STATIC
VOID
SendBlock (
VOID
)
-/*++
-
-Routine Description:
-
- Huffman code the block and output it.
-
-Arguments:
- (VOID)
-
-Returns:
- (VOID)
-
---*/
{
UINT32 Index;
UINT32 Index2;
@@ -1281,26 +1151,18 @@ Returns:
}
}
+/**
+ Outputs an Original Character or a Pointer
+
+ @param CharC The original character or the 'String Length' element of a Pointer
+ @param Pos The 'Position' field of a Pointer
+**/
STATIC
VOID
Output (
IN UINT32 CharC,
IN UINT32 Pos
)
-/*++
-
-Routine Description:
-
- Outputs an Original Character or a Pointer
-
-Arguments:
-
- CharC - The original character or the 'String Length' element of a Pointer
- Pos - The 'Position' field of a Pointer
-
-Returns: (VOID)
-
---*/
{
STATIC UINT32 CPos;
@@ -1399,26 +1261,18 @@ MakeCrcTable (
}
}
+/**
+ Outputs rightmost n bits of x
+
+ @param Number the rightmost n bits of the data is used
+ @param x the data
+**/
STATIC
VOID
PutBits (
IN INT32 Number,
IN UINT32 Value
)
-/*++
-
-Routine Description:
-
- Outputs rightmost n bits of x
-
-Arguments:
-
- Number - the rightmost n bits of the data is used
- x - the data
-
-Returns: (VOID)
-
---*/
{
UINT8 Temp;
@@ -1439,28 +1293,20 @@ Returns: (VOID)
mSubBitBuf |= Value << (mBitCount -= Number);
}
+/**
+ Read in source data
+
+ @param Pointer - the buffer to hold the data
+ @param Number - number of bytes to read
+
+ @return number of bytes actually read
+**/
STATIC
INT32
FreadCrc (
OUT UINT8 *Pointer,
IN INT32 Number
)
-/*++
-
-Routine Description:
-
- Read in source data
-
-Arguments:
-
- Pointer - the buffer to hold the data
- Number - number of bytes to read
-
-Returns:
-
- number of bytes actually read
-
---*/
{
INT32 Index;
@@ -1491,24 +1337,16 @@ InitPutBits (
mSubBitBuf = 0;
}
+/**
+ Count the number of each code length for a Huffman tree.
+
+ @param Index the top node
+**/
STATIC
VOID
CountLen (
IN INT32 Index
)
-/*++
-
-Routine Description:
-
- Count the number of each code length for a Huffman tree.
-
-Arguments:
-
- Index - the top node
-
-Returns: (VOID)
-
---*/
{
STATIC INT32 Depth = 0;
@@ -1522,26 +1360,16 @@ Returns: (VOID)
}
}
+/**
+ Create code length array for a Huffman tree
+
+ @param Root the root of the tree
+**/
STATIC
VOID
MakeLen (
IN INT32 Root
)
-/*++
-
-Routine Description:
-
- Create code length array for a Huffman tree
-
-Arguments:
-
- Root - the root of the tree
-
-Returns:
-
- VOID
-
---*/
{
INT32 Index;
INT32 Index3;
@@ -1616,6 +1444,13 @@ DownHeap (
mHeap[Index] = (INT16) Index3;
}
+/**
+ Assign code to each symbol based on the code length array
+
+ @param Number number of symbols
+ @param Len the code length array
+ @param Code stores codes for each symbol
+**/
STATIC
VOID
MakeCode (
@@ -1623,21 +1458,6 @@ MakeCode (
IN UINT8 Len[ ],
OUT UINT16 Code[]
)
-/*++
-
-Routine Description:
-
- Assign code to each symbol based on the code length array
-
-Arguments:
-
- Number - number of symbols
- Len - the code length array
- Code - stores codes for each symbol
-
-Returns: (VOID)
-
---*/
{
INT32 Index;
UINT16 Start[18];
@@ -1652,6 +1472,16 @@ Returns: (VOID)
}
}
+/**
+ Generates Huffman codes given a frequency distribution of symbols
+
+ @param NParm number of symbols
+ @param FreqParm frequency of each symbol
+ @param LenParm code length for each symbol
+ @param CodeParm code for each symbol
+
+ @return Root of the Huffman tree.
+**/
STATIC
INT32
MakeTree (
@@ -1660,24 +1490,6 @@ MakeTree (
OUT UINT8 LenParm[ ],
OUT UINT16 CodeParm[]
)
-/*++
-
-Routine Description:
-
- Generates Huffman codes given a frequency distribution of symbols
-
-Arguments:
-
- NParm - number of symbols
- FreqParm - frequency of each symbol
- LenParm - code length for each symbol
- CodeParm - code for each symbol
-
-Returns:
-
- Root of the Huffman tree.
-
---*/
{
INT32 Index;
INT32 Index2;
diff --git a/BaseTools/Source/C/Common/WinNtInclude.h b/BaseTools/Source/C/Common/WinNtInclude.h
deleted file mode 100644
index f30e6c69..00000000
--- a/BaseTools/Source/C/Common/WinNtInclude.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/** @file
-Include file for the WinNt Library
-
-Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __WIN_NT_INCLUDE_H__
-#define __WIN_NT_INCLUDE_H__
-
-#define GUID _WINNT_DUP_GUID_____
-#define _LIST_ENTRY _WINNT_DUP_LIST_ENTRY_FORWARD
-#define LIST_ENTRY _WINNT_DUP_LIST_ENTRY
-
-#if (_MSC_VER < 1800)
-#define InterlockedIncrement _WINNT_DUP_InterlockedIncrement
-#define InterlockedDecrement _WINNT_DUP_InterlockedDecrement
-#define InterlockedCompareExchange64 _WINNT_DUP_InterlockedCompareExchange64
-#endif
-
-#undef UNALIGNED
-#undef CONST
-#undef VOID
-
-#ifndef __GNUC__
-#include "windows.h"
-
-//
-// Win32 include files do not compile clean with /W4, so we use the warning
-// pragma to suppress the warnings for Win32 only. This way our code can still
-// compile at /W4 (highest warning level) with /WX (warnings cause build
-// errors).
-//
-#pragma warning(disable : 4115)
-#pragma warning(disable : 4201)
-#pragma warning(disable : 4214)
-#pragma warning(disable : 4028)
-#pragma warning(disable : 4133)
-
-//
-// Set the warnings back on as the EFI code must be /W4.
-//
-#pragma warning(default : 4115)
-#pragma warning(default : 4201)
-#pragma warning(default : 4214)
-
-#endif
-
-#undef GUID
-#undef _LIST_ENTRY
-#undef LIST_ENTRY
-#undef InterlockedIncrement
-#undef InterlockedDecrement
-#undef InterlockedCompareExchange64
-#undef InterlockedCompareExchangePointer
-
-#define VOID void
-
-//
-// Prevent collisions with Windows API name macros that deal with Unicode/Not issues
-//
-#undef LoadImage
-#undef CreateEvent
-
-#endif
diff --git a/BaseTools/Source/C/GenFv/GNUmakefile b/BaseTools/Source/C/GenFv/GNUmakefile
index 608d9b48..ac13a217 100644
--- a/BaseTools/Source/C/GenFv/GNUmakefile
+++ b/BaseTools/Source/C/GenFv/GNUmakefile
@@ -14,10 +14,6 @@ include $(MAKEROOT)/Makefiles/app.makefile
LIBS = -lCommon
ifeq ($(CYGWIN), CYGWIN)
- LIBS += -L/lib/e2fsprogs -luuid
-endif
-
-ifeq ($(LINUX), Linux)
- LIBS += -luuid
+ LIBS += -L/lib/e2fsprogs
endif
diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
index f7f3d4b6..545a6945 100644
--- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
+++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
@@ -14,11 +14,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// Include files
//
-#if defined(__FreeBSD__)
-#include
-#elif defined(__GNUC__)
-#include
-#endif
#ifdef __GNUC__
#include
#endif
@@ -30,7 +25,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include
-#include "WinNtInclude.h"
#include "GenFvInternalLib.h"
#include "FvLib.h"
#include "PeCoffLib.h"
@@ -122,63 +116,6 @@ CHAR8 *mFvbAlignmentName[] = {
EFI_FVB2_ALIGNMENT_2G_STRING
};
-//
-// This data array will be located at the base of the Firmware Volume Header (FVH)
-// in the boot block. It must not exceed 14 bytes of code. The last 2 bytes
-// will be used to keep the FVH checksum consistent.
-// This code will be run in response to a startup IPI for HT-enabled systems.
-//
-#define SIZEOF_STARTUP_DATA_ARRAY 0x10
-
-UINT8 m128kRecoveryStartupApDataArray[SIZEOF_STARTUP_DATA_ARRAY] = {
- //
- // EA D0 FF 00 F0 ; far jmp F000:FFD0
- // 0, 0, 0, 0, 0, 0, 0, 0, 0, ; Reserved bytes
- // 0, 0 ; Checksum Padding
- //
- 0xEA,
- 0xD0,
- 0xFF,
- 0x0,
- 0xF0,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00
-};
-
-UINT8 m64kRecoveryStartupApDataArray[SIZEOF_STARTUP_DATA_ARRAY] = {
- //
- // EB CE ; jmp short ($-0x30)
- // ; (from offset 0x0 to offset 0xFFD0)
- // 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ; Reserved bytes
- // 0, 0 ; Checksum Padding
- //
- 0xEB,
- 0xCE,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00
-};
-
FV_INFO mFvDataInfo;
CAP_INFO mCapDataInfo;
BOOLEAN mIsLargeFfs = FALSE;
@@ -1574,12 +1511,6 @@ Returns:
EFI_PHYSICAL_ADDRESS SecCorePhysicalAddress;
INT32 Ia32SecEntryOffset;
UINT32 *Ia32ResetAddressPtr;
- UINT8 *BytePointer;
- UINT8 *BytePointer2;
- UINT16 *WordPointer;
- UINT16 CheckSum;
- UINT32 IpiVector;
- UINTN Index;
EFI_FFS_FILE_STATE SavedState;
BOOLEAN Vtf0Detected;
UINT32 FfsHeaderSize;
@@ -1661,8 +1592,8 @@ Returns:
if (
Vtf0Detected &&
- (MachineType == EFI_IMAGE_MACHINE_IA32 ||
- MachineType == EFI_IMAGE_MACHINE_X64)
+ (MachineType == IMAGE_FILE_MACHINE_I386 ||
+ MachineType == IMAGE_FILE_MACHINE_X64)
) {
//
// If the SEC core code is IA32 or X64 and the VTF-0 signature
@@ -1720,7 +1651,7 @@ Returns:
DebugMsg (NULL, 0, 9, "PeiCore physical entry point address", "Address = 0x%llX", (unsigned long long) PeiCorePhysicalAddress);
}
-if (MachineType == EFI_IMAGE_MACHINE_IA32 || MachineType == EFI_IMAGE_MACHINE_X64) {
+if (MachineType == IMAGE_FILE_MACHINE_I386 || MachineType == IMAGE_FILE_MACHINE_X64) {
if (PeiCorePhysicalAddress != 0) {
//
// Get the location to update
@@ -1751,71 +1682,12 @@ if (MachineType == EFI_IMAGE_MACHINE_IA32 || MachineType == EFI_IMAGE_MACHINE_X6
Ia32ResetAddressPtr = (UINT32 *) ((UINTN) FvImage->Eof - 4);
*Ia32ResetAddressPtr = (UINT32) (FvInfo->BaseAddress);
DebugMsg (NULL, 0, 9, "update BFV base address in the top FV image", "BFV base address = 0x%llX.", (unsigned long long) FvInfo->BaseAddress);
-
- //
- // Update the Startup AP in the FVH header block ZeroVector region.
- //
- BytePointer = (UINT8 *) ((UINTN) FvImage->FileImage);
- if (FvInfo->Size <= 0x10000) {
- BytePointer2 = m64kRecoveryStartupApDataArray;
- } else if (FvInfo->Size <= 0x20000) {
- BytePointer2 = m128kRecoveryStartupApDataArray;
- } else {
- BytePointer2 = m128kRecoveryStartupApDataArray;
- //
- // Find the position to place Ap reset vector, the offset
- // between the position and the end of Fvrecovery.fv file
- // should not exceed 128kB to prevent Ap reset vector from
- // outside legacy E and F segment
- //
- Status = FindApResetVectorPosition (FvImage, &BytePointer);
- if (EFI_ERROR (Status)) {
- Error (NULL, 0, 3000, "Invalid", "FV image does not have enough space to place AP reset vector. The FV image needs to reserve at least 4KB of unused space.");
- return EFI_ABORTED;
- }
- }
-
- for (Index = 0; Index < SIZEOF_STARTUP_DATA_ARRAY; Index++) {
- BytePointer[Index] = BytePointer2[Index];
- }
- //
- // Calculate the checksum
- //
- CheckSum = 0x0000;
- WordPointer = (UINT16 *) (BytePointer);
- for (Index = 0; Index < SIZEOF_STARTUP_DATA_ARRAY / 2; Index++) {
- CheckSum = (UINT16) (CheckSum + ((UINT16) *WordPointer));
- WordPointer++;
- }
- //
- // Update the checksum field
- //
- WordPointer = (UINT16 *) (BytePointer + SIZEOF_STARTUP_DATA_ARRAY - 2);
- *WordPointer = (UINT16) (0x10000 - (UINT32) CheckSum);
-
- //
- // IpiVector at the 4k aligned address in the top 2 blocks in the PEI FV.
- //
- IpiVector = (UINT32) (FV_IMAGES_TOP_ADDRESS - ((UINTN) FvImage->Eof - (UINTN) BytePointer));
- DebugMsg (NULL, 0, 9, "Startup AP Vector address", "IpiVector at 0x%X", (unsigned) IpiVector);
- if ((IpiVector & 0xFFF) != 0) {
- Error (NULL, 0, 3000, "Invalid", "Startup AP Vector address are not 4K aligned, because the FV size is not 4K aligned");
- return EFI_ABORTED;
- }
- IpiVector = IpiVector >> 12;
- IpiVector = IpiVector & 0xFF;
-
- //
- // Write IPI Vector at Offset FvrecoveryFileSize - 8
- //
- Ia32ResetAddressPtr = (UINT32 *) ((UINTN) FvImage->Eof - 8);
- *Ia32ResetAddressPtr = IpiVector;
- } else if (MachineType == EFI_IMAGE_MACHINE_ARMT) {
+ } else if (MachineType == IMAGE_FILE_MACHINE_ARMTHUMB_MIXED) {
//
// Since the ARM reset vector is in the FV Header you really don't need a
// Volume Top File, but if you have one for some reason don't crash...
//
- } else if (MachineType == EFI_IMAGE_MACHINE_AARCH64) {
+ } else if (MachineType == IMAGE_FILE_MACHINE_ARM64) {
//
// Since the AArch64 reset vector is in the FV Header you really don't need a
// Volume Top File, but if you have one for some reason don't crash...
@@ -2210,7 +2082,7 @@ Returns:
return EFI_SUCCESS;
}
- if (MachineType == EFI_IMAGE_MACHINE_ARMT) {
+ if (MachineType == IMAGE_FILE_MACHINE_ARMTHUMB_MIXED) {
// ARM: Array of 4 UINT32s:
// 0 - is branch relative to SEC entry point
// 1 - PEI Entry Point
@@ -2264,7 +2136,7 @@ Returns:
//
memcpy(FvImage->FileImage, ResetVector, sizeof (ResetVector));
- } else if (MachineType == EFI_IMAGE_MACHINE_AARCH64) {
+ } else if (MachineType == IMAGE_FILE_MACHINE_ARM64) {
// AArch64: Used as UINT64 ResetVector[2]
// 0 - is branch relative to SEC entry point
// 1 - PEI Entry Point
@@ -2383,7 +2255,7 @@ Returns:
return EFI_ABORTED;
}
- if (MachineType != EFI_IMAGE_MACHINE_RISCV64) {
+ if (MachineType != IMAGE_FILE_MACHINE_RISCV64) {
Error(NULL, 0, 3000, "Invalid", "Could not update SEC core because Machine type is not RiscV.");
return EFI_ABORTED;
}
@@ -2484,7 +2356,7 @@ Returns:
if (!UpdateVectorSec)
return EFI_SUCCESS;
- if (MachineType == EFI_IMAGE_MACHINE_LOONGARCH64) {
+ if (MachineType == IMAGE_FILE_MACHINE_LOONGARCH64) {
UINT32 ResetVector[1];
memset(ResetVector, 0, sizeof (ResetVector));
@@ -2601,9 +2473,9 @@ Returns:
//
// Verify machine type is supported
//
- if ((*MachineType != EFI_IMAGE_MACHINE_IA32) && (*MachineType != EFI_IMAGE_MACHINE_X64) && (*MachineType != EFI_IMAGE_MACHINE_EBC) &&
- (*MachineType != EFI_IMAGE_MACHINE_ARMT) && (*MachineType != EFI_IMAGE_MACHINE_AARCH64) &&
- (*MachineType != EFI_IMAGE_MACHINE_RISCV64) && (*MachineType != EFI_IMAGE_MACHINE_LOONGARCH64)) {
+ if ((*MachineType != IMAGE_FILE_MACHINE_I386) && (*MachineType != IMAGE_FILE_MACHINE_X64) && (*MachineType != IMAGE_FILE_MACHINE_EBC) &&
+ (*MachineType != IMAGE_FILE_MACHINE_ARMTHUMB_MIXED) && (*MachineType != IMAGE_FILE_MACHINE_ARM64) &&
+ (*MachineType != IMAGE_FILE_MACHINE_RISCV64) && (*MachineType != IMAGE_FILE_MACHINE_LOONGARCH64)) {
Error (NULL, 0, 3000, "Invalid", "Unrecognized machine type in the PE32 file.");
return EFI_UNSUPPORTED;
}
@@ -3553,13 +3425,13 @@ Returns:
}
// machine type is ARM, set a flag so ARM reset vector processing occurs
- if ((MachineType == EFI_IMAGE_MACHINE_ARMT) || (MachineType == EFI_IMAGE_MACHINE_AARCH64)) {
+ if ((MachineType == IMAGE_FILE_MACHINE_ARMTHUMB_MIXED) || (MachineType == IMAGE_FILE_MACHINE_ARM64)) {
VerboseMsg("Located ARM/AArch64 SEC/PEI core in child FV");
mArm = TRUE;
}
// Machine type is LOONGARCH64, set a flag so LoongArch64 reset vector processed.
- if (MachineType == EFI_IMAGE_MACHINE_LOONGARCH64) {
+ if (MachineType == IMAGE_FILE_MACHINE_LOONGARCH64) {
VerboseMsg("Located LoongArch64 SEC core in child FV");
mLoongArch = TRUE;
}
@@ -3712,16 +3584,16 @@ Returns:
return Status;
}
- if ( (ImageContext.Machine == EFI_IMAGE_MACHINE_ARMT) ||
- (ImageContext.Machine == EFI_IMAGE_MACHINE_AARCH64) ) {
+ if ( (ImageContext.Machine == IMAGE_FILE_MACHINE_ARMTHUMB_MIXED) ||
+ (ImageContext.Machine == IMAGE_FILE_MACHINE_ARM64) ) {
mArm = TRUE;
}
- if (ImageContext.Machine == EFI_IMAGE_MACHINE_RISCV64) {
+ if (ImageContext.Machine == IMAGE_FILE_MACHINE_RISCV64) {
mRiscV = TRUE;
}
- if (ImageContext.Machine == EFI_IMAGE_MACHINE_LOONGARCH64) {
+ if (ImageContext.Machine == IMAGE_FILE_MACHINE_LOONGARCH64) {
mLoongArch = TRUE;
}
@@ -3997,12 +3869,12 @@ Returns:
return Status;
}
- if ( (ImageContext.Machine == EFI_IMAGE_MACHINE_ARMT) ||
- (ImageContext.Machine == EFI_IMAGE_MACHINE_AARCH64) ) {
+ if ( (ImageContext.Machine == IMAGE_FILE_MACHINE_ARMTHUMB_MIXED) ||
+ (ImageContext.Machine == IMAGE_FILE_MACHINE_ARM64) ) {
mArm = TRUE;
}
- if (ImageContext.Machine == EFI_IMAGE_MACHINE_LOONGARCH64) {
+ if (ImageContext.Machine == IMAGE_FILE_MACHINE_LOONGARCH64) {
mLoongArch = TRUE;
}
@@ -4196,83 +4068,6 @@ Returns:
return EFI_SUCCESS;
}
-EFI_STATUS
-FindApResetVectorPosition (
- IN MEMORY_FILE *FvImage,
- OUT UINT8 **Pointer
- )
-/*++
-
-Routine Description:
-
- Find the position in this FvImage to place Ap reset vector.
-
-Arguments:
-
- FvImage Memory file for the FV memory image.
- Pointer Pointer to pointer to position.
-
-Returns:
-
- EFI_NOT_FOUND - No satisfied position is found.
- EFI_SUCCESS - The suitable position is return.
-
---*/
-{
- EFI_FFS_FILE_HEADER *PadFile;
- UINT32 Index;
- EFI_STATUS Status;
- UINT8 *FixPoint;
- UINT32 FileLength;
-
- for (Index = 1; ;Index ++) {
- //
- // Find Pad File to add ApResetVector info
- //
- Status = GetFileByType (EFI_FV_FILETYPE_FFS_PAD, Index, &PadFile);
- if (EFI_ERROR (Status) || (PadFile == NULL)) {
- //
- // No Pad file to be found.
- //
- break;
- }
- //
- // Get Pad file size.
- //
- FileLength = GetFfsFileLength(PadFile);
- FileLength = (FileLength + EFI_FFS_FILE_HEADER_ALIGNMENT - 1) & ~(EFI_FFS_FILE_HEADER_ALIGNMENT - 1);
- //
- // FixPoint must be align on 0x1000 relative to FvImage Header
- //
- FixPoint = (UINT8*) PadFile + GetFfsHeaderLength(PadFile);
- FixPoint = FixPoint + 0x1000 - (((UINTN) FixPoint - (UINTN) FvImage->FileImage) & 0xFFF);
- //
- // FixPoint be larger at the last place of one fv image.
- //
- while (((UINTN) FixPoint + SIZEOF_STARTUP_DATA_ARRAY - (UINTN) PadFile) <= FileLength) {
- FixPoint += 0x1000;
- }
- FixPoint -= 0x1000;
-
- if ((UINTN) FixPoint < ((UINTN) PadFile + GetFfsHeaderLength(PadFile))) {
- //
- // No alignment FixPoint in this Pad File.
- //
- continue;
- }
-
- if ((UINTN) FvImage->Eof - (UINTN)FixPoint <= 0x20000) {
- //
- // Find the position to place ApResetVector
- //
- *Pointer = FixPoint;
- return EFI_SUCCESS;
- }
- }
-
- return EFI_NOT_FOUND;
-}
-
EFI_STATUS
ParseCapInf (
IN MEMORY_FILE *InfFile,
diff --git a/BaseTools/Source/C/GenFw/Elf32Convert.c b/BaseTools/Source/C/GenFw/Elf32Convert.c
index 0c5b1db7..ccd59889 100755
--- a/BaseTools/Source/C/GenFw/Elf32Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf32Convert.c
@@ -9,8 +9,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
-#include "WinNtInclude.h"
-
#ifndef __GNUC__
#include
#include
@@ -555,16 +553,16 @@ ScanSections32 (
switch (mEhdr->e_machine) {
case EM_386:
- NtHdr->Pe32.FileHeader.Machine = EFI_IMAGE_MACHINE_IA32;
+ NtHdr->Pe32.FileHeader.Machine = IMAGE_FILE_MACHINE_I386;
NtHdr->Pe32.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC;
break;
case EM_ARM:
- NtHdr->Pe32.FileHeader.Machine = EFI_IMAGE_MACHINE_ARMT;
+ NtHdr->Pe32.FileHeader.Machine = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED;
NtHdr->Pe32.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC;
break;
default:
VerboseMsg ("%s unknown e_machine type %hu. Assume IA-32", mInImageName, mEhdr->e_machine);
- NtHdr->Pe32.FileHeader.Machine = EFI_IMAGE_MACHINE_IA32;
+ NtHdr->Pe32.FileHeader.Machine = IMAGE_FILE_MACHINE_I386;
NtHdr->Pe32.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC;
}
diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
index 63e92bc6..46165b97 100644
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -10,8 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
-#include "WinNtInclude.h"
-
#ifndef __GNUC__
#include
#include
@@ -770,6 +768,49 @@ WriteSectionRiscV64 (
}
}
+STATIC UINT16 mDllCharacteristicsEx;
+
+STATIC
+VOID
+ParseNoteSection (
+ CONST Elf_Shdr *Shdr
+ )
+{
+ CONST Elf_Note *Note;
+ CONST UINT32 *Prop;
+ UINT32 Prop0;
+ UINT32 Prop2;
+
+ Note = (Elf_Note *)((UINT8 *)mEhdr + Shdr->sh_offset);
+
+ if ((Note->n_type == NT_GNU_PROPERTY_TYPE_0) &&
+ (Note->n_namesz == sizeof ("GNU")) &&
+ (strcmp ((CHAR8 *)(Note + 1), "GNU") == 0) &&
+ (Note->n_descsz > sizeof (UINT32[2]))) {
+ Prop = (UINT32 *)((UINT8 *)(Note + 1) + sizeof("GNU"));
+
+ switch (mEhdr->e_machine) {
+ case EM_AARCH64:
+ Prop0 = GNU_PROPERTY_AARCH64_FEATURE_1_AND;
+ Prop2 = GNU_PROPERTY_AARCH64_FEATURE_1_BTI;
+ break;
+
+ case EM_X86_64:
+ Prop0 = GNU_PROPERTY_X86_FEATURE_1_AND;
+ Prop2 = GNU_PROPERTY_X86_FEATURE_1_IBT;
+ break;
+
+ default:
+ return;
+ }
+ if ((Prop[0] == Prop0) &&
+ (Prop[1] >= sizeof (UINT32)) &&
+ ((Prop[2] & Prop2) != 0)) {
+ mDllCharacteristicsEx |= EFI_IMAGE_DLLCHARACTERISTICS_EX_FORWARD_CFI_COMPAT;
+ }
+ }
+}
+
//
// Elf functions interface implementation
//
@@ -826,6 +867,13 @@ ScanSections64 (
}
}
+ for (i = 0; i < mEhdr->e_shnum; i++) {
+ Elf_Shdr *shdr = GetShdrByIndex(i);
+ if (shdr->sh_type == SHT_NOTE) {
+ ParseNoteSection (shdr);
+ }
+ }
+
//
// Check if mCoffAlignment is larger than MAX_COFF_ALIGNMENT
//
@@ -942,6 +990,16 @@ ScanSections64 (
sizeof(EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY) +
strlen(mInImageName) + 1;
+ //
+ // Add more space in the .debug data region for the DllCharacteristicsEx
+ // field.
+ //
+ if (mDllCharacteristicsEx != 0) {
+ mCoffOffset = DebugRvaAlign(mCoffOffset) +
+ sizeof (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY) +
+ sizeof (EFI_IMAGE_DEBUG_EX_DLLCHARACTERISTICS_ENTRY);
+ }
+
mCoffOffset = CoffAlign(mCoffOffset);
if (SectionCount == 0) {
mDataOffset = mCoffOffset;
@@ -1079,25 +1137,25 @@ ScanSections64 (
switch (mEhdr->e_machine) {
case EM_X86_64:
- NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_X64;
+ NtHdr->Pe32Plus.FileHeader.Machine = IMAGE_FILE_MACHINE_X64;
NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
break;
case EM_AARCH64:
- NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_AARCH64;
+ NtHdr->Pe32Plus.FileHeader.Machine = IMAGE_FILE_MACHINE_ARM64;
NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
break;
case EM_RISCV64:
- NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_RISCV64;
+ NtHdr->Pe32Plus.FileHeader.Machine = IMAGE_FILE_MACHINE_RISCV64;
NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
break;
case EM_LOONGARCH:
- NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_LOONGARCH64;
+ NtHdr->Pe32Plus.FileHeader.Machine = IMAGE_FILE_MACHINE_LOONGARCH64;
NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
break;
default:
VerboseMsg ("%u unknown e_machine type. Assume X64", (UINTN)mEhdr->e_machine);
- NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_X64;
+ NtHdr->Pe32Plus.FileHeader.Machine = IMAGE_FILE_MACHINE_X64;
NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
}
@@ -1720,7 +1778,17 @@ WriteSections64 (
case R_LARCH_TLS_LD64_HI20:
case R_LARCH_TLS_GD_PC_HI20:
case R_LARCH_TLS_GD64_HI20:
+ case R_LARCH_32_PCREL:
case R_LARCH_RELAX:
+ case R_LARCH_DELETE:
+ case R_LARCH_ALIGN:
+ case R_LARCH_PCREL20_S2:
+ case R_LARCH_CFA:
+ case R_LARCH_ADD6:
+ case R_LARCH_SUB6:
+ case R_LARCH_ADD_ULEB128:
+ case R_LARCH_SUB_ULEB128:
+ case R_LARCH_64_PCREL:
//
// These types are not used or do not require fixup.
//
@@ -2127,7 +2195,17 @@ WriteRelocations64 (
case R_LARCH_TLS_LD64_HI20:
case R_LARCH_TLS_GD_PC_HI20:
case R_LARCH_TLS_GD64_HI20:
+ case R_LARCH_32_PCREL:
case R_LARCH_RELAX:
+ case R_LARCH_DELETE:
+ case R_LARCH_ALIGN:
+ case R_LARCH_PCREL20_S2:
+ case R_LARCH_CFA:
+ case R_LARCH_ADD6:
+ case R_LARCH_SUB6:
+ case R_LARCH_ADD_ULEB128:
+ case R_LARCH_SUB_ULEB128:
+ case R_LARCH_64_PCREL:
//
// These types are not used or do not require fixup in PE format files.
//
@@ -2194,29 +2272,47 @@ WriteDebug64 (
VOID
)
{
- UINT32 Len;
- EFI_IMAGE_OPTIONAL_HEADER_UNION *NtHdr;
- EFI_IMAGE_DATA_DIRECTORY *DataDir;
- EFI_IMAGE_DEBUG_DIRECTORY_ENTRY *Dir;
- EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY *Nb10;
+ UINT32 Len;
+ EFI_IMAGE_OPTIONAL_HEADER_UNION *NtHdr;
+ EFI_IMAGE_DATA_DIRECTORY *DataDir;
+ EFI_IMAGE_DEBUG_DIRECTORY_ENTRY *Dir;
+ EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY *Nb10;
+ EFI_IMAGE_DEBUG_EX_DLLCHARACTERISTICS_ENTRY *DllEntry;
Len = strlen(mInImageName) + 1;
- Dir = (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY*)(mCoffFile + mDebugOffset);
- Dir->Type = EFI_IMAGE_DEBUG_TYPE_CODEVIEW;
- Dir->SizeOfData = sizeof(EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY) + Len;
- Dir->RVA = mDebugOffset + sizeof(EFI_IMAGE_DEBUG_DIRECTORY_ENTRY);
- Dir->FileOffset = mDebugOffset + sizeof(EFI_IMAGE_DEBUG_DIRECTORY_ENTRY);
-
- Nb10 = (EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY*)(Dir + 1);
- Nb10->Signature = CODEVIEW_SIGNATURE_NB10;
- strcpy ((char *)(Nb10 + 1), mInImageName);
-
-
NtHdr = (EFI_IMAGE_OPTIONAL_HEADER_UNION *)(mCoffFile + mNtHdrOffset);
DataDir = &NtHdr->Pe32Plus.OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_DEBUG];
DataDir->VirtualAddress = mDebugOffset;
- DataDir->Size = sizeof(EFI_IMAGE_DEBUG_DIRECTORY_ENTRY);
+ DataDir->Size = sizeof (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY);
+
+ Dir = (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY*)(mCoffFile + mDebugOffset);
+
+ if (mDllCharacteristicsEx != 0) {
+ DataDir->Size += sizeof (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY);
+
+ Dir->Type = EFI_IMAGE_DEBUG_TYPE_EX_DLLCHARACTERISTICS;
+ Dir->SizeOfData = sizeof (EFI_IMAGE_DEBUG_EX_DLLCHARACTERISTICS_ENTRY);
+ Dir->FileOffset = mDebugOffset + DataDir->Size +
+ sizeof (EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY) +
+ DebugRvaAlign(Len);
+ Dir->RVA = Dir->FileOffset;
+
+ DllEntry = (VOID *)(mCoffFile + Dir->FileOffset);
+
+ DllEntry->DllCharacteristicsEx = mDllCharacteristicsEx;
+
+ Dir++;
+ }
+
+ Dir->Type = EFI_IMAGE_DEBUG_TYPE_CODEVIEW;
+ Dir->SizeOfData = sizeof(EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY) + Len;
+ Dir->RVA = mDebugOffset + DataDir->Size;
+ Dir->FileOffset = mDebugOffset + DataDir->Size;
+
+ Nb10 = (EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY*)(Dir + 1);
+ Nb10->Signature = CODEVIEW_SIGNATURE_NB10;
+ strcpy ((char *)(Nb10 + 1), mInImageName);
}
STATIC
diff --git a/BaseTools/Source/C/GenFw/ElfConvert.c b/BaseTools/Source/C/GenFw/ElfConvert.c
index 70ee944f..3a8dfe00 100644
--- a/BaseTools/Source/C/GenFw/ElfConvert.c
+++ b/BaseTools/Source/C/GenFw/ElfConvert.c
@@ -7,8 +7,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
-#include "WinNtInclude.h"
-
#ifndef __GNUC__
#include
#include
diff --git a/BaseTools/Source/C/GenFw/GenFw.c b/BaseTools/Source/C/GenFw/GenFw.c
index da7d0296..25a24aea 100644
--- a/BaseTools/Source/C/GenFw/GenFw.c
+++ b/BaseTools/Source/C/GenFw/GenFw.c
@@ -6,8 +6,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
-#include "WinNtInclude.h"
-
#ifndef __GNUC__
#include
#include
@@ -28,9 +26,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// Acpi Table definition
//
#include
-#include
-#include
-#include
+#include
+#include
+#include
#include
#include "CommonLib.h"
@@ -88,6 +86,7 @@ UINT32 mImageSize = 0;
UINT32 mOutImageType = FW_DUMMY_IMAGE;
BOOLEAN mIsConvertXip = FALSE;
BOOLEAN mExportFlag = FALSE;
+BOOLEAN mNoNxCompat = FALSE;
STATIC
EFI_STATUS
@@ -283,6 +282,9 @@ Returns:
write export table into PE-COFF.\n\
This option can be used together with -e.\n\
It doesn't work for other options.\n");
+ fprintf (stdout, " --nonxcompat Do not set the IMAGE_DLLCHARACTERISTICS_NX_COMPAT bit \n\
+ of the optional header in the PE header even if the \n\
+ requirements are met.\n");
fprintf (stdout, " -v, --verbose Turn on verbose output with informational messages.\n");
fprintf (stdout, " -q, --quiet Disable all messages except key message and fatal error\n");
fprintf (stdout, " -d, --debug level Enable debug messages, at input debug level.\n");
@@ -370,7 +372,7 @@ Returns:
if (Facs->Version > EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) {
break;
}
- if ((Facs->Version != EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) &&
+ if ((Facs->Version != 0 /* field is reserved in ACPI 1.0 */) &&
(Facs->Version != EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) &&
(Facs->Version != EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION)){
Error (NULL, 0, 3000, "Invalid", "FACS version check failed.");
@@ -443,6 +445,59 @@ Returns:
return STATUS_SUCCESS;
}
+/**
+
+ Checks if the Pe image is nxcompat compliant.
+
+ Must meet the following conditions:
+ 1. The PE is 64bit
+ 2. The section alignment is evenly divisible by 4k
+ 3. No section is writable and executable.
+
+ @param PeHdr - The PE header
+
+ @retval TRUE - The PE is nx compat compliant
+ @retval FALSE - The PE is not nx compat compliant
+
+**/
+STATIC
+BOOLEAN
+IsNxCompatCompliant (
+ EFI_IMAGE_OPTIONAL_HEADER_UNION *PeHdr
+ )
+{
+ EFI_IMAGE_SECTION_HEADER *SectionHeader;
+ UINT32 Index;
+ UINT32 Mask;
+
+ // Must have an optional header to perform verification
+ if (PeHdr->Pe32.FileHeader.SizeOfOptionalHeader == 0) {
+ return FALSE;
+ }
+
+ // Verify PE is 64 bit
+ if (!(PeHdr->Pe32.OptionalHeader.Magic == EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC)) {
+ return FALSE;
+ }
+
+ // Verify Section Alignment is divisible by 4K
+ if (!((PeHdr->Pe32Plus.OptionalHeader.SectionAlignment % EFI_PAGE_SIZE) == 0)) {
+ return FALSE;
+ }
+
+ // Verify sections are not Write & Execute
+ Mask = EFI_IMAGE_SCN_MEM_EXECUTE | EFI_IMAGE_SCN_MEM_WRITE;
+ SectionHeader = (EFI_IMAGE_SECTION_HEADER *) ((UINT8 *) &(PeHdr->Pe32Plus.OptionalHeader) + PeHdr->Pe32Plus.FileHeader.SizeOfOptionalHeader);
+ for (Index = 0; Index < PeHdr->Pe32Plus.FileHeader.NumberOfSections; Index ++, SectionHeader ++) {
+ if ((SectionHeader->Characteristics & Mask) == Mask) {
+ return FALSE;
+ }
+ }
+
+ // Passed all requirements, return TRUE
+ return TRUE;
+}
+
VOID
SetHiiResourceHeader (
UINT8 *HiiBinData,
@@ -1454,6 +1509,13 @@ Returns:
continue;
}
+ if (stricmp (argv[0], "--nonxcompat") == 0) {
+ mNoNxCompat = TRUE;
+ argc --;
+ argv ++;
+ continue;
+ }
+
if (argv[0][0] == '-') {
Error (NULL, 0, 1000, "Unknown option", argv[0]);
goto Finish;
@@ -2199,12 +2261,6 @@ Returns:
}
}
- if (PeHdr->Pe32.FileHeader.Machine == IMAGE_FILE_MACHINE_ARM) {
- // Some tools kick out IMAGE_FILE_MACHINE_ARM (0x1c0) vs IMAGE_FILE_MACHINE_ARMT (0x1c2)
- // so patch back to the official UEFI value.
- PeHdr->Pe32.FileHeader.Machine = IMAGE_FILE_MACHINE_ARMT;
- }
-
//
// Set new base address into image
//
@@ -2466,6 +2522,11 @@ Returns:
TEImageHeader.BaseOfCode = Optional64->BaseOfCode;
TEImageHeader.ImageBase = (UINT64) (Optional64->ImageBase);
+ // Set NxCompat flag
+ if (IsNxCompatCompliant (PeHdr) && !mNoNxCompat) {
+ Optional64->DllCharacteristics |= IMAGE_DLLCHARACTERISTICS_NX_COMPAT;
+ }
+
if (Optional64->NumberOfRvaAndSizes > EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC) {
TEImageHeader.DataDirectory[EFI_TE_IMAGE_DIRECTORY_ENTRY_BASERELOC].VirtualAddress = Optional64->DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC].VirtualAddress;
TEImageHeader.DataDirectory[EFI_TE_IMAGE_DIRECTORY_ENTRY_BASERELOC].Size = Optional64->DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC].Size;
@@ -2932,7 +2993,8 @@ Returns:
if (mIsConvertXip) {
DebugEntry->FileOffset = DebugEntry->RVA;
}
- if (ZeroDebugFlag || DebugEntry->Type != EFI_IMAGE_DEBUG_TYPE_CODEVIEW) {
+ if ((ZeroDebugFlag || DebugEntry->Type != EFI_IMAGE_DEBUG_TYPE_CODEVIEW) &&
+ (DebugEntry->Type != EFI_IMAGE_DEBUG_TYPE_EX_DLLCHARACTERISTICS)) {
memset (FileBuffer + DebugEntry->FileOffset, 0, DebugEntry->SizeOfData);
memset (DebugEntry, 0, sizeof (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY));
}
@@ -3118,7 +3180,7 @@ Returns:
// Get Debug, Export and Resource EntryTable RVA address.
// Resource Directory entry need to review.
//
- if (FileHdr->Machine == EFI_IMAGE_MACHINE_IA32) {
+ if (FileHdr->Machine == IMAGE_FILE_MACHINE_I386) {
Optional32Hdr = (EFI_IMAGE_OPTIONAL_HEADER32 *) ((UINT8*) FileHdr + sizeof (EFI_IMAGE_FILE_HEADER));
SectionHeader = (EFI_IMAGE_SECTION_HEADER *) ((UINT8 *) Optional32Hdr + FileHdr->SizeOfOptionalHeader);
if (Optional32Hdr->NumberOfRvaAndSizes > EFI_IMAGE_DIRECTORY_ENTRY_EXPORT && \
diff --git a/BaseTools/Source/C/GenFw/elf_common.h b/BaseTools/Source/C/GenFw/elf_common.h
index 4e6f5361..80b95343 100755
--- a/BaseTools/Source/C/GenFw/elf_common.h
+++ b/BaseTools/Source/C/GenFw/elf_common.h
@@ -59,6 +59,15 @@ typedef struct {
UINT32 n_type; /* Type of this note. */
} Elf_Note;
+#define NT_GNU_PROPERTY_TYPE_0 5
+
+#define GNU_PROPERTY_X86_FEATURE_1_AND 0xc0000002
+#define GNU_PROPERTY_X86_FEATURE_1_IBT 0x1
+
+#define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000
+#define GNU_PROPERTY_AARCH64_FEATURE_1_BTI 0x1
+#define GNU_PROPERTY_AARCH64_FEATURE_1_PAC 0x2
+
/* Indexes into the e_ident array. Keep synced with
http://www.sco.com/developers/gabi/latest/ch4.eheader.html */
#define EI_MAG0 0 /* Magic number, byte 0. */
@@ -1135,5 +1144,16 @@ typedef struct {
#define R_LARCH_TLS_LD64_HI20 96
#define R_LARCH_TLS_GD_PC_HI20 97
#define R_LARCH_TLS_GD64_HI20 98
-#define R_LARCH_RELAX 99
+#define R_LARCH_32_PCREL 99
+#define R_LARCH_RELAX 100
+#define R_LARCH_DELETE 101
+#define R_LARCH_ALIGN 102
+#define R_LARCH_PCREL20_S2 103
+#define R_LARCH_CFA 104
+#define R_LARCH_ADD6 105
+#define R_LARCH_SUB6 106
+#define R_LARCH_ADD_ULEB128 107
+#define R_LARCH_SUB_ULEB128 108
+#define R_LARCH_64_PCREL 109
+
#endif /* !_SYS_ELF_COMMON_H_ */
diff --git a/BaseTools/Source/C/Include/AArch64/ProcessorBind.h b/BaseTools/Source/C/Include/AArch64/ProcessorBind.h
deleted file mode 100644
index 93d656f5..00000000
--- a/BaseTools/Source/C/Include/AArch64/ProcessorBind.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/** @file
- Processor or Compiler specific defines and types for AArch64.
-
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
- Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- Portions copyright (c) 2013, ARM Ltd. All rights reserved.
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __PROCESSOR_BIND_H__
-#define __PROCESSOR_BIND_H__
-
-///
-/// Define the processor type so other code can make processor based choices
-///
-#define MDE_CPU_AARCH64
-
-//
-// Make sure we are using the correct packing rules per EFI specification
-//
-#ifndef __GNUC__
-#pragma pack()
-#endif
-
-#if _MSC_EXTENSIONS
- //
- // use Microsoft* C compiler dependent integer width types
- //
- typedef unsigned __int64 UINT64;
- typedef __int64 INT64;
- typedef unsigned __int32 UINT32;
- typedef __int32 INT32;
- typedef unsigned short UINT16;
- typedef unsigned short CHAR16;
- typedef short INT16;
- typedef unsigned char BOOLEAN;
- typedef unsigned char UINT8;
- typedef char CHAR8;
- typedef signed char INT8;
-#else
- //
- // Use ANSI C 2000 stdint.h integer width declarations
- //
- #include
- typedef uint8_t BOOLEAN;
- typedef int8_t INT8;
- typedef uint8_t UINT8;
- typedef int16_t INT16;
- typedef uint16_t UINT16;
- typedef int32_t INT32;
- typedef uint32_t UINT32;
- typedef int64_t INT64;
- typedef uint64_t UINT64;
- typedef char CHAR8;
- typedef uint16_t CHAR16;
-
-#endif
-
-///
-/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
-/// 8 bytes on supported 64-bit processor instructions)
-///
-typedef UINT64 UINTN;
-
-///
-/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
-/// 8 bytes on supported 64-bit processor instructions)
-///
-typedef INT64 INTN;
-
-//
-// Processor specific defines
-//
-
-///
-/// A value of native width with the highest bit set.
-///
-#define MAX_BIT 0x8000000000000000
-
-///
-/// A value of native width with the two highest bits set.
-///
-#define MAX_2_BITS 0xC000000000000000
-
-///
-/// The stack alignment required for AARCH64
-///
-#define CPU_STACK_ALIGNMENT 16
-
-//
-// Modifier to ensure that all protocol member functions and EFI intrinsics
-// use the correct C calling convention. All protocol member functions and
-// EFI intrinsics are required to modify their member functions with EFIAPI.
-//
-#define EFIAPI
-
-#if defined(__GNUC__)
- ///
- /// For GNU assembly code, .global or .globl can declare global symbols.
- /// Define this macro to unify the usage.
- ///
- #define ASM_GLOBAL .globl
-
- #if !defined(__APPLE__)
- ///
- /// ARM EABI defines that the linker should not manipulate call relocations
- /// (do bl/blx conversion) unless the target symbol has function type.
- /// CodeSourcery 2010.09 started requiring the .type to function properly
- ///
- #define INTERWORK_FUNC(func__) .type ASM_PFX(func__), %function
-
- #define GCC_ASM_EXPORT(func__) \
- .global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\
- .type ASM_PFX(func__), %function
-
- #define GCC_ASM_IMPORT(func__) \
- .extern _CONCATENATE (__USER_LABEL_PREFIX__, func__)
-
- #else
- //
- // .type not supported by Apple Xcode tools
- //
- #define INTERWORK_FUNC(func__)
-
- #define GCC_ASM_EXPORT(func__) \
- .globl _CONCATENATE (__USER_LABEL_PREFIX__, func__) \
-
- #define GCC_ASM_IMPORT(name)
-
- #endif
-#endif
-
-/**
- Return the pointer to the first instruction of a function given a function pointer.
- On ARM CPU architectures, these two pointer values are the same,
- so the implementation of this macro is very simple.
-
- @param FunctionPointer A pointer to a function.
-
- @return The pointer to the first instruction of a function given a function pointer.
-
-**/
-#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
-
-#endif
-
diff --git a/BaseTools/Source/C/Include/Arm/ProcessorBind.h b/BaseTools/Source/C/Include/Arm/ProcessorBind.h
deleted file mode 100644
index de5c5a0a..00000000
--- a/BaseTools/Source/C/Include/Arm/ProcessorBind.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/** @file
- Processor or Compiler specific defines and types for ARM.
-
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
- Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __PROCESSOR_BIND_H__
-#define __PROCESSOR_BIND_H__
-
-///
-/// Define the processor type so other code can make processor based choices
-///
-#define MDE_CPU_ARM
-
-//
-// Make sure we are using the correct packing rules per EFI specification
-//
-#ifndef __GNUC__
-#pragma pack()
-#endif
-
-#if _MSC_EXTENSIONS
- //
- // use Microsoft* C compiler dependent integer width types
- //
- typedef unsigned __int64 UINT64;
- typedef __int64 INT64;
- typedef unsigned __int32 UINT32;
- typedef __int32 INT32;
- typedef unsigned short UINT16;
- typedef unsigned short CHAR16;
- typedef short INT16;
- typedef unsigned char BOOLEAN;
- typedef unsigned char UINT8;
- typedef char CHAR8;
- typedef signed char INT8;
-#else
- //
- // Assume standard ARM alignment.
- //
- typedef unsigned long long UINT64;
- typedef long long INT64;
- typedef unsigned int UINT32;
- typedef int INT32;
- typedef unsigned short UINT16;
- typedef unsigned short CHAR16;
- typedef short INT16;
- typedef unsigned char BOOLEAN;
- typedef unsigned char UINT8;
- typedef char CHAR8;
- typedef signed char INT8;
-
- #define UINT8_MAX 0xff
-#endif
-
-///
-/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
-/// 8 bytes on supported 64-bit processor instructions)
-///
-typedef UINT32 UINTN;
-
-///
-/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
-/// 8 bytes on supported 64-bit processor instructions)
-///
-typedef INT32 INTN;
-
-//
-// Processor specific defines
-//
-
-///
-/// A value of native width with the highest bit set.
-///
-#define MAX_BIT 0x80000000
-
-///
-/// A value of native width with the two highest bits set.
-///
-#define MAX_2_BITS 0xC0000000
-
-///
-/// The stack alignment required for ARM
-///
-#define CPU_STACK_ALIGNMENT sizeof(UINT64)
-
-//
-// Modifier to ensure that all protocol member functions and EFI intrinsics
-// use the correct C calling convention. All protocol member functions and
-// EFI intrinsics are required to modify their member functions with EFIAPI.
-//
-#define EFIAPI
-
-#if defined(__GNUC__)
- ///
- /// For GNU assembly code, .global or .globl can declare global symbols.
- /// Define this macro to unify the usage.
- ///
- #define ASM_GLOBAL .globl
-
- #if !defined(__APPLE__)
- ///
- /// ARM EABI defines that the linker should not manipulate call relocations
- /// (do bl/blx conversion) unless the target symbol has function type.
- /// CodeSourcery 2010.09 started requiring the .type to function properly
- ///
- #define INTERWORK_FUNC(func__) .type ASM_PFX(func__), %function
-
- #define GCC_ASM_EXPORT(func__) \
- .global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\
- .type ASM_PFX(func__), %function
-
- #define GCC_ASM_IMPORT(func__) \
- .extern _CONCATENATE (__USER_LABEL_PREFIX__, func__)
-
- #else
- //
- // .type not supported by Apple Xcode tools
- //
- #define INTERWORK_FUNC(func__)
-
- #define GCC_ASM_EXPORT(func__) \
- .globl _CONCATENATE (__USER_LABEL_PREFIX__, func__) \
-
- #define GCC_ASM_IMPORT(name)
-
- #endif
-#endif
-
-/**
- Return the pointer to the first instruction of a function given a function pointer.
- On ARM CPU architectures, these two pointer values are the same,
- so the implementation of this macro is very simple.
-
- @param FunctionPointer A pointer to a function.
-
- @return The pointer to the first instruction of a function given a function pointer.
-
-**/
-#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
-
-#endif
-
-
diff --git a/BaseTools/Source/C/Include/Common/BaseTypes.h b/BaseTools/Source/C/Include/Common/BaseTypes.h
index dd5b1cb1..d8c275f0 100644
--- a/BaseTools/Source/C/Include/Common/BaseTypes.h
+++ b/BaseTools/Source/C/Include/Common/BaseTypes.h
@@ -58,6 +58,7 @@
#endif
#define PACKED
+
//
// Support for variable length argument lists using the ANSI standard.
//
diff --git a/BaseTools/Source/C/Include/Ia32/ProcessorBind.h b/BaseTools/Source/C/Include/Ia32/ProcessorBind.h
deleted file mode 100644
index 9b63b462..00000000
--- a/BaseTools/Source/C/Include/Ia32/ProcessorBind.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/** @file
- Processor or Compiler specific defines and types for x64.
-
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __PROCESSOR_BIND_H__
-#define __PROCESSOR_BIND_H__
-
-//
-// Define the processor type so other code can make processor based choices
-//
-#define MDE_CPU_IA32
-
-//
-// Make sure we are useing the correct packing rules per EFI specification
-//
-#ifndef __GNUC__
-#pragma pack()
-#endif
-
-#if _MSC_EXTENSIONS
-
-//
-// Disable warning that make it impossible to compile at /W4
-// This only works for Microsoft* tools
-//
-
-//
-// Disabling bitfield type checking warnings.
-//
-#pragma warning ( disable : 4214 )
-
-//
-// Disabling the unreferenced formal parameter warnings.
-//
-#pragma warning ( disable : 4100 )
-
-//
-// Disable slightly different base types warning as CHAR8 * can not be set
-// to a constant string.
-//
-#pragma warning ( disable : 4057 )
-
-//
-// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning
-//
-#pragma warning ( disable : 4127 )
-
-
-#endif
-
-
-#if !defined(__GNUC__) && (__STDC_VERSION__ < 199901L)
- //
- // No ANSI C 2000 stdint.h integer width declarations, so define equivalents
- //
-
- #if _MSC_EXTENSIONS
-
- //
- // use Microsoft* C compiler dependent integer width types
- //
- typedef unsigned __int64 UINT64;
- typedef __int64 INT64;
- typedef unsigned __int32 UINT32;
- typedef __int32 INT32;
- typedef unsigned short UINT16;
- typedef unsigned short CHAR16;
- typedef short INT16;
- typedef unsigned char BOOLEAN;
- typedef unsigned char UINT8;
- typedef char CHAR8;
- typedef char INT8;
- #else
-
- //
- // Assume standard IA-32 alignment.
- // BugBug: Need to check portability of long long
- //
- typedef unsigned long long UINT64;
- typedef long long INT64;
- typedef unsigned int UINT32;
- typedef int INT32;
- typedef unsigned short UINT16;
- typedef unsigned short CHAR16;
- typedef short INT16;
- typedef unsigned char BOOLEAN;
- typedef unsigned char UINT8;
- typedef char CHAR8;
- typedef char INT8;
- #endif
-
- #define UINT8_MAX 0xff
-
-#else
- //
- // Use ANSI C 2000 stdint.h integer width declarations
- //
- #include "stdint.h"
- typedef uint8_t BOOLEAN;
- typedef int8_t INT8;
- typedef uint8_t UINT8;
- typedef int16_t INT16;
- typedef uint16_t UINT16;
- typedef int32_t INT32;
- typedef uint32_t UINT32;
- typedef int64_t INT64;
- typedef uint64_t UINT64;
- typedef char CHAR8;
- typedef uint16_t CHAR16;
-
-#endif
-
-typedef UINT32 UINTN;
-typedef INT32 INTN;
-
-
-//
-// Processor specific defines
-//
-#define MAX_BIT 0x80000000
-#define MAX_2_BITS 0xC0000000
-
-//
-// Modifier to ensure that all protocol member functions and EFI intrinsics
-// use the correct C calling convention. All protocol member functions and
-// EFI intrinsics are required to modify their member functions with EFIAPI.
-//
-#if _MSC_EXTENSIONS
- //
- // Microsoft* compiler requires _EFIAPI usage, __cdecl is Microsoft* specific C.
- //
- #define EFIAPI __cdecl
-#endif
-
-#if __GNUC__
- #define EFIAPI __attribute__((cdecl))
-#endif
-
-//
-// The Microsoft* C compiler can removed references to unreferenced data items
-// if the /OPT:REF linker option is used. We defined a macro as this is a
-// a non standard extension
-//
-#if _MSC_EXTENSIONS
- #define GLOBAL_REMOVE_IF_UNREFERENCED __declspec(selectany)
-#else
- #define GLOBAL_REMOVE_IF_UNREFERENCED
-#endif
-
-#endif
diff --git a/BaseTools/Source/C/Include/IndustryStandard/Acpi.h b/BaseTools/Source/C/Include/IndustryStandard/Acpi.h
deleted file mode 100644
index 72577a22..00000000
--- a/BaseTools/Source/C/Include/IndustryStandard/Acpi.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/** @file
- This file contains some basic ACPI definitions that are consumed by drivers
- that do not care about ACPI versions.
-
- Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef _ACPI_H_
-#define _ACPI_H_
-
-//
-// Common table header, this prefaces all ACPI tables, including FACS, but
-// excluding the RSD PTR structure
-//
-typedef struct {
- UINT32 Signature;
- UINT32 Length;
-} EFI_ACPI_COMMON_HEADER;
-
-//
-// Common ACPI description table header. This structure prefaces most ACPI tables.
-//
-#pragma pack(1)
-
-typedef struct {
- UINT32 Signature;
- UINT32 Length;
- UINT8 Revision;
- UINT8 Checksum;
- UINT8 OemId[6];
- UINT64 OemTableId;
- UINT32 OemRevision;
- UINT32 CreatorId;
- UINT32 CreatorRevision;
-} EFI_ACPI_DESCRIPTION_HEADER;
-
-#pragma pack()
-//
-// Define for Pci Host Bridge Resource Allocation
-//
-#define ACPI_ADDRESS_SPACE_DESCRIPTOR 0x8A
-#define ACPI_END_TAG_DESCRIPTOR 0x79
-
-#define ACPI_ADDRESS_SPACE_TYPE_MEM 0x00
-#define ACPI_ADDRESS_SPACE_TYPE_IO 0x01
-#define ACPI_ADDRESS_SPACE_TYPE_BUS 0x02
-
-//
-// Power Management Timer frequency is fixed at 3.579545MHz
-//
-#define ACPI_TIMER_FREQUENCY 3579545
-
-//
-// Make sure structures match spec
-//
-#pragma pack(1)
-
-typedef struct {
- UINT8 Desc;
- UINT16 Len;
- UINT8 ResType;
- UINT8 GenFlag;
- UINT8 SpecificFlag;
- UINT64 AddrSpaceGranularity;
- UINT64 AddrRangeMin;
- UINT64 AddrRangeMax;
- UINT64 AddrTranslationOffset;
- UINT64 AddrLen;
-} EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR;
-
-typedef struct {
- UINT8 Desc;
- UINT8 Checksum;
-} EFI_ACPI_END_TAG_DESCRIPTOR;
-
-//
-// General use definitions
-//
-#define EFI_ACPI_RESERVED_BYTE 0x00
-#define EFI_ACPI_RESERVED_WORD 0x0000
-#define EFI_ACPI_RESERVED_DWORD 0x00000000
-#define EFI_ACPI_RESERVED_QWORD 0x0000000000000000
-
-//
-// Resource Type Specific Flags
-// Ref ACPI specification 6.4.3.5.5
-//
-// Bit [0] : Write Status, _RW
-//
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_WRITE (1 << 0)
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_ONLY (0 << 0)
-//
-// Bit [2:1] : Memory Attributes, _MEM
-//
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_NON_CACHEABLE (0 << 1)
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE (1 << 1)
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_WRITE_COMBINING (2 << 1)
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE (3 << 1)
-//
-// Bit [4:3] : Memory Attributes, _MTP
-//
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_MEMORY (0 << 3)
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_RESERVED (1 << 3)
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_ACPI (2 << 3)
-#define EFI_APCI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_NVS (3 << 3)
-//
-// Bit [5] : Memory to I/O Translation, _TTP
-//
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_TRANSLATION (1 << 5)
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_STATIC (0 << 5)
-
-#pragma pack()
-
-#endif
diff --git a/BaseTools/Source/C/Include/IndustryStandard/Acpi1_0.h b/BaseTools/Source/C/Include/IndustryStandard/Acpi1_0.h
deleted file mode 100644
index 55b9168a..00000000
--- a/BaseTools/Source/C/Include/IndustryStandard/Acpi1_0.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/** @file
- ACPI 1.0b definitions from the ACPI Specification, revision 1.0b
-
- Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef _ACPI_1_0_H_
-#define _ACPI_1_0_H_
-
-#include "IndustryStandard/Acpi.h"
-
-//
-// Ensure proper structure formats
-//
-#pragma pack(1)
-//
-// ACPI 1.0b table structures
-//
-//
-// Root System Description Pointer Structure
-//
-typedef struct {
- UINT64 Signature;
- UINT8 Checksum;
- UINT8 OemId[6];
- UINT8 Reserved;
- UINT32 RsdtAddress;
-} EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
-
-//
-// Root System Description Table
-// No definition needed as it is a common description table header followed by a
-// variable number of UINT32 table pointers.
-//
-//
-// RSDT Revision (as defined in ACPI 1.0b spec.)
-//
-#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
-
-//
-// Fixed ACPI Description Table Structure (FADT)
-//
-typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 FirmwareCtrl;
- UINT32 Dsdt;
- UINT8 IntModel;
- UINT8 Reserved1;
- UINT16 SciInt;
- UINT32 SmiCmd;
- UINT8 AcpiEnable;
- UINT8 AcpiDisable;
- UINT8 S4BiosReq;
- UINT8 Reserved2;
- UINT32 Pm1aEvtBlk;
- UINT32 Pm1bEvtBlk;
- UINT32 Pm1aCntBlk;
- UINT32 Pm1bCntBlk;
- UINT32 Pm2CntBlk;
- UINT32 PmTmrBlk;
- UINT32 Gpe0Blk;
- UINT32 Gpe1Blk;
- UINT8 Pm1EvtLen;
- UINT8 Pm1CntLen;
- UINT8 Pm2CntLen;
- UINT8 PmTmLen;
- UINT8 Gpe0BlkLen;
- UINT8 Gpe1BlkLen;
- UINT8 Gpe1Base;
- UINT8 Reserved3;
- UINT16 PLvl2Lat;
- UINT16 PLvl3Lat;
- UINT16 FlushSize;
- UINT16 FlushStride;
- UINT8 DutyOffset;
- UINT8 DutyWidth;
- UINT8 DayAlrm;
- UINT8 MonAlrm;
- UINT8 Century;
- UINT8 Reserved4;
- UINT8 Reserved5;
- UINT8 Reserved6;
- UINT32 Flags;
-} EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE;
-
-//
-// FADT Version (as defined in ACPI 1.0b spec.)
-//
-#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x01
-
-//
-// Fixed ACPI Description Table Fixed Feature Flags
-// All other bits are reserved and must be set to 0.
-//
-#define EFI_ACPI_1_0_WBINVD (1 << 0)
-#define EFI_ACPI_1_0_WBINVD_FLUSH (1 << 1)
-#define EFI_ACPI_1_0_PROC_C1 (1 << 2)
-#define EFI_ACPI_1_0_P_LVL2_UP (1 << 3)
-#define EFI_ACPI_1_0_PWR_BUTTON (1 << 4)
-#define EFI_ACPI_1_0_SLP_BUTTON (1 << 5)
-#define EFI_ACPI_1_0_FIX_RTC (1 << 6)
-#define EFI_ACPI_1_0_RTC_S4 (1 << 7)
-#define EFI_ACPI_1_0_TMR_VAL_EXT (1 << 8)
-#define EFI_ACPI_1_0_DCK_CAP (1 << 9)
-
-#define EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x0
-//
-// Firmware ACPI Control Structure
-//
-typedef struct {
- UINT32 Signature;
- UINT32 Length;
- UINT32 HardwareSignature;
- UINT32 FirmwareWakingVector;
- UINT32 GlobalLock;
- UINT32 Flags;
- UINT8 Reserved[40];
-} EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
-
-//
-// Firmware Control Structure Feature Flags
-// All other bits are reserved and must be set to 0.
-//
-#define EFI_ACPI_1_0_S4BIOS_F (1 << 0)
-
-//
-// Multiple APIC Description Table header definition. The rest of the table
-// must be defined in a platform specific manner.
-//
-typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 LocalApicAddress;
- UINT32 Flags;
-} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
-
-//
-// MADT Revision (as defined in ACPI 1.0b spec.)
-//
-#define EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01
-
-//
-// Multiple APIC Flags
-// All other bits are reserved and must be set to 0.
-//
-#define EFI_ACPI_1_0_PCAT_COMPAT (1 << 0)
-
-//
-// Multiple APIC Description Table APIC structure types
-// All other values between 0x09 an 0xFF are reserved and
-// will be ignored by OSPM.
-//
-#define EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC 0x00
-#define EFI_ACPI_1_0_IO_APIC 0x01
-#define EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE 0x02
-#define EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
-#define EFI_ACPI_1_0_LOCAL_APIC_NMI 0x04
-
-//
-// APIC Structure Definitions
-//
-//
-// Processor Local APIC Structure Definition
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT8 ApicId;
- UINT32 Flags;
-} EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
-
-//
-// Local APIC Flags. All other bits are reserved and must be 0.
-//
-#define EFI_ACPI_1_0_LOCAL_APIC_ENABLED (1 << 0)
-
-//
-// IO APIC Structure
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 IoApicAddress;
- UINT32 SystemVectorBase;
-} EFI_ACPI_1_0_IO_APIC_STRUCTURE;
-
-//
-// Interrupt Source Override Structure
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Bus;
- UINT8 Source;
- UINT32 GlobalSystemInterruptVector;
- UINT16 Flags;
-} EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
-
-//
-// Non-Maskable Interrupt Source Structure
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT32 GlobalSystemInterruptVector;
-} EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
-
-//
-// Local APIC NMI Structure
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT16 Flags;
- UINT8 LocalApicInti;
-} EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE;
-
-//
-// Smart Battery Description Table (SBST)
-//
-typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 WarningEnergyLevel;
- UINT32 LowEnergyLevel;
- UINT32 CriticalEnergyLevel;
-} EFI_ACPI_1_0_SMART_BATTERY_DESCRIPTION_TABLE;
-
-//
-// Known table signatures
-//
-//
-// "RSD PTR " Root System Description Pointer
-//
-#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE 0x2052545020445352ULL
-
-//
-// "APIC" Multiple APIC Description Table
-//
-#define EFI_ACPI_1_0_APIC_SIGNATURE 0x43495041
-
-//
-// "DSDT" Differentiated System Description Table
-//
-#define EFI_ACPI_1_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445344
-
-//
-// "FACS" Firmware ACPI Control Structure
-//
-#define EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE 0x53434146
-
-//
-// "FACP" Fixed ACPI Description Table
-//
-#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE 0x50434146
-
-//
-// "PSDT" Persistent System Description Table
-//
-#define EFI_ACPI_1_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445350
-
-//
-// "RSDT" Root System Description Table
-//
-#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445352
-
-//
-// "SBST" Smart Battery Specification Table
-//
-#define EFI_ACPI_1_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE 0x54534253
-
-//
-// "SSDT" Secondary System Description Table
-//
-#define EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445353
-
-#pragma pack()
-
-#endif
diff --git a/BaseTools/Source/C/Include/IndustryStandard/Acpi2_0.h b/BaseTools/Source/C/Include/IndustryStandard/Acpi2_0.h
deleted file mode 100644
index 22ce87f8..00000000
--- a/BaseTools/Source/C/Include/IndustryStandard/Acpi2_0.h
+++ /dev/null
@@ -1,520 +0,0 @@
-/** @file
- ACPI 2.0 definitions from the ACPI Specification, revision 2.0
-
- Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef _ACPI_2_0_H_
-#define _ACPI_2_0_H_
-
-#include "IndustryStandard/Acpi.h"
-
-//
-// Ensure proper structure formats
-//
-#pragma pack(1)
-//
-// ACPI Specification Revision
-//
-#define EFI_ACPI_2_0_REVISION 0x02
-
-//
-// BUGBUG: OEM values need to be moved somewhere else, probably read from data hub
-// and produced by a platform specific driver.
-//
-//
-// ACPI OEM ID
-//
-#define EFI_ACPI_2_0_OEM_ID "INTEL "
-#define EFI_ACPI_2_0_OEM_TABLE_ID 0x5034303738543245 // "E2T8704P"
-//
-// ACPI OEM Revision
-//
-#define EFI_ACPI_2_0_OEM_REVISION 0x00000002
-
-//
-// ACPI table creator ID
-//
-#define EFI_ACPI_2_0_CREATOR_ID 0x5446534D // TBD "MSFT"
-//
-// ACPI table creator revision
-//
-#define EFI_ACPI_2_0_CREATOR_REVISION 0x01000013 // TBD
-//
-// ACPI 2.0 Generic Address Space definition
-//
-typedef struct {
- UINT8 AddressSpaceId;
- UINT8 RegisterBitWidth;
- UINT8 RegisterBitOffset;
- UINT8 Reserved;
- UINT64 Address;
-} EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE;
-
-//
-// Generic Address Space Address IDs
-//
-#define EFI_ACPI_2_0_SYSTEM_MEMORY 0
-#define EFI_ACPI_2_0_SYSTEM_IO 1
-#define EFI_ACPI_2_0_PCI_CONFIGURATION_SPACE 2
-#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER 3
-#define EFI_ACPI_2_0_SMBUS 4
-#define EFI_ACPI_2_0_FUNCTIONAL_FIXED_HARDWARE 0x7F
-
-//
-// ACPI 2.0 table structures
-//
-//
-// Root System Description Pointer Structure
-//
-typedef struct {
- UINT64 Signature;
- UINT8 Checksum;
- UINT8 OemId[6];
- UINT8 Revision;
- UINT32 RsdtAddress;
- UINT32 Length;
- UINT64 XsdtAddress;
- UINT8 ExtendedChecksum;
- UINT8 Reserved[3];
-} EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
-
-//
-// RSD_PTR Revision (as defined in ACPI 2.0 spec.)
-//
-#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02
-
-//
-// Common table header, this prefaces all ACPI tables, including FACS, but
-// excluding the RSD PTR structure
-//
-typedef struct {
- UINT32 Signature;
- UINT32 Length;
-} EFI_ACPI_2_0_COMMON_HEADER;
-
-//
-// Root System Description Table
-// No definition needed as it is a common description table header followed by a
-// variable number of UINT32 table pointers.
-//
-//
-// RSDT Revision (as defined in ACPI 2.0 spec.)
-//
-#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
-
-//
-// Extended System Description Table
-// No definition needed as it is a common description table header followed by a
-// variable number of UINT64 table pointers.
-//
-//
-// XSDT Revision (as defined in ACPI 2.0 spec.)
-//
-#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
-
-//
-// Fixed ACPI Description Table Structure (FADT)
-//
-typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 FirmwareCtrl;
- UINT32 Dsdt;
- UINT8 Reserved0;
- UINT8 PreferredPmProfile;
- UINT16 SciInt;
- UINT32 SmiCmd;
- UINT8 AcpiEnable;
- UINT8 AcpiDisable;
- UINT8 S4BiosReq;
- UINT8 PstateCnt;
- UINT32 Pm1aEvtBlk;
- UINT32 Pm1bEvtBlk;
- UINT32 Pm1aCntBlk;
- UINT32 Pm1bCntBlk;
- UINT32 Pm2CntBlk;
- UINT32 PmTmrBlk;
- UINT32 Gpe0Blk;
- UINT32 Gpe1Blk;
- UINT8 Pm1EvtLen;
- UINT8 Pm1CntLen;
- UINT8 Pm2CntLen;
- UINT8 PmTmrLen;
- UINT8 Gpe0BlkLen;
- UINT8 Gpe1BlkLen;
- UINT8 Gpe1Base;
- UINT8 CstCnt;
- UINT16 PLvl2Lat;
- UINT16 PLvl3Lat;
- UINT16 FlushSize;
- UINT16 FlushStride;
- UINT8 DutyOffset;
- UINT8 DutyWidth;
- UINT8 DayAlrm;
- UINT8 MonAlrm;
- UINT8 Century;
- UINT16 IaPcBootArch;
- UINT8 Reserved1;
- UINT32 Flags;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
- UINT8 ResetValue;
- UINT8 Reserved2[3];
- UINT64 XFirmwareCtrl;
- UINT64 XDsdt;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
-} EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE;
-
-//
-// FADT Version (as defined in ACPI 2.0 spec.)
-//
-#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x03
-
-//
-// Fixed ACPI Description Table Boot Architecture Flags
-// All other bits are reserved and must be set to 0.
-//
-#define EFI_ACPI_2_0_LEGACY_DEVICES (1 << 0)
-#define EFI_ACPI_2_0_8042 (1 << 1)
-
-//
-// Fixed ACPI Description Table Fixed Feature Flags
-// All other bits are reserved and must be set to 0.
-//
-#define EFI_ACPI_2_0_WBINVD (1 << 0)
-#define EFI_ACPI_2_0_WBINVD_FLUSH (1 << 1)
-#define EFI_ACPI_2_0_PROC_C1 (1 << 2)
-#define EFI_ACPI_2_0_P_LVL2_UP (1 << 3)
-#define EFI_ACPI_2_0_PWR_BUTTON (1 << 4)
-#define EFI_ACPI_2_0_SLP_BUTTON (1 << 5)
-#define EFI_ACPI_2_0_FIX_RTC (1 << 6)
-#define EFI_ACPI_2_0_RTC_S4 (1 << 7)
-#define EFI_ACPI_2_0_TMR_VAL_EXT (1 << 8)
-#define EFI_ACPI_2_0_DCK_CAP (1 << 9)
-#define EFI_ACPI_2_0_RESET_REG_SUP (1 << 10)
-#define EFI_ACPI_2_0_SEALED_CASE (1 << 11)
-#define EFI_ACPI_2_0_HEADLESS (1 << 12)
-#define EFI_ACPI_2_0_CPU_SW_SLP (1 << 13)
-
-//
-// Firmware ACPI Control Structure
-//
-typedef struct {
- UINT32 Signature;
- UINT32 Length;
- UINT32 HardwareSignature;
- UINT32 FirmwareWakingVector;
- UINT32 GlobalLock;
- UINT32 Flags;
- UINT64 XFirmwareWakingVector;
- UINT8 Version;
- UINT8 Reserved[31];
-} EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
-
-//
-// FACS Version (as defined in ACPI 2.0 spec.)
-//
-#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x01
-
-//
-// Firmware Control Structure Feature Flags
-// All other bits are reserved and must be set to 0.
-//
-#define EFI_ACPI_2_0_S4BIOS_F (1 << 0)
-
-//
-// Multiple APIC Description Table header definition. The rest of the table
-// must be defined in a platform specific manner.
-//
-typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 LocalApicAddress;
- UINT32 Flags;
-} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
-
-//
-// MADT Revision (as defined in ACPI 2.0 spec.)
-//
-#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01
-
-//
-// Multiple APIC Flags
-// All other bits are reserved and must be set to 0.
-//
-#define EFI_ACPI_2_0_PCAT_COMPAT (1 << 0)
-
-//
-// Multiple APIC Description Table APIC structure types
-// All other values between 0x09 an 0xFF are reserved and
-// will be ignored by OSPM.
-//
-#define EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC 0x00
-#define EFI_ACPI_2_0_IO_APIC 0x01
-#define EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE 0x02
-#define EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
-#define EFI_ACPI_2_0_LOCAL_APIC_NMI 0x04
-#define EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
-#define EFI_ACPI_2_0_IO_SAPIC 0x06
-#define EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC 0x07
-#define EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES 0x08
-
-//
-// APIC Structure Definitions
-//
-//
-// Processor Local APIC Structure Definition
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT8 ApicId;
- UINT32 Flags;
-} EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
-
-//
-// Local APIC Flags. All other bits are reserved and must be 0.
-//
-#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED (1 << 0)
-
-//
-// IO APIC Structure
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 IoApicAddress;
- UINT32 GlobalSystemInterruptBase;
-} EFI_ACPI_2_0_IO_APIC_STRUCTURE;
-
-//
-// Interrupt Source Override Structure
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Bus;
- UINT8 Source;
- UINT32 GlobalSystemInterrupt;
- UINT16 Flags;
-} EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
-
-//
-// Non-Maskable Interrupt Source Structure
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT32 GlobalSystemInterrupt;
-} EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
-
-//
-// Local APIC NMI Structure
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT16 Flags;
- UINT8 LocalApicLint;
-} EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE;
-
-//
-// Local APIC Address Override Structure
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT64 LocalApicAddress;
-} EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
-
-//
-// IO SAPIC Structure
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 GlobalSystemInterruptBase;
- UINT64 IoSapicAddress;
-} EFI_ACPI_2_0_IO_SAPIC_STRUCTURE;
-
-//
-// Local SAPIC Structure
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT8 LocalSapicId;
- UINT8 LocalSapicEid;
- UINT8 Reserved[3];
- UINT32 Flags;
-} EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
-
-//
-// Platform Interrupt Sources Structure
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT8 InterruptType;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT8 IoSapicVector;
- UINT32 GlobalSystemInterrupt;
- UINT32 Reserved;
-} EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
-
-//
-// Smart Battery Description Table (SBST)
-//
-typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 WarningEnergyLevel;
- UINT32 LowEnergyLevel;
- UINT32 CriticalEnergyLevel;
-} EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE;
-
-//
-// SBST Version (as defined in ACPI 2.0 spec.)
-//
-#define EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
-
-//
-// Embedded Controller Boot Resources Table (ECDT)
-// The table is followed by a null terminated ASCII string that contains
-// a fully qualified reference to the name space object.
-//
-typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcControl;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcData;
- UINT32 Uid;
- UINT8 GpeBit;
-} EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
-
-//
-// ECDT Version (as defined in ACPI 2.0 spec.)
-//
-#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
-
-//
-// Known table signatures
-//
-//
-// "RSD PTR " Root System Description Pointer
-//
-#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE 0x2052545020445352
-
-//
-// "SPIC" Multiple SAPIC Description Table
-//
-// BUGBUG: Don't know where this came from except SR870BN4 uses it.
-// #define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE 0x43495053
-//
-#define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE 0x43495041
-
-//
-// "BOOT" MS Simple Boot Spec
-//
-#define EFI_ACPI_2_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE 0x544F4F42
-
-//
-// "DBGP" MS Bebug Port Spec
-//
-#define EFI_ACPI_2_0_DEBUG_PORT_TABLE_SIGNATURE 0x50474244
-
-//
-// "DSDT" Differentiated System Description Table
-//
-#define EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445344
-
-//
-// "ECDT" Embedded Controller Boot Resources Table
-//
-#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE 0x54444345
-
-//
-// "ETDT" Event Timer Description Table
-//
-#define EFI_ACPI_2_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE 0x54445445
-
-//
-// "FACS" Firmware ACPI Control Structure
-//
-#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE 0x53434146
-
-//
-// "FACP" Fixed ACPI Description Table
-//
-#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE 0x50434146
-
-//
-// "APIC" Multiple APIC Description Table
-//
-#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE 0x43495041
-
-//
-// "PSDT" Persistent System Description Table
-//
-#define EFI_ACPI_2_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445350
-
-//
-// "RSDT" Root System Description Table
-//
-#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445352
-
-//
-// "SBST" Smart Battery Specification Table
-//
-#define EFI_ACPI_2_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE 0x54534253
-
-//
-// "SLIT" System Locality Information Table
-//
-#define EFI_ACPI_2_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE 0x54494C53
-
-//
-// "SPCR" Serial Port Console Redirection Table
-//
-#define EFI_ACPI_2_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE 0x52435053
-
-//
-// "SRAT" Static Resource Affinity Table
-//
-#define EFI_ACPI_2_0_STATIC_RESOURCE_AFFINITY_TABLE_SIGNATURE 0x54415253
-
-//
-// "SSDT" Secondary System Description Table
-//
-#define EFI_ACPI_2_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445353
-
-//
-// "SPMI" Server Platform Management Interface Table
-//
-#define EFI_ACPI_2_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_SIGNATURE 0x494D5053
-
-//
-// "XSDT" Extended System Description Table
-//
-#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445358
-
-#pragma pack()
-
-#endif
diff --git a/BaseTools/Source/C/Include/IndustryStandard/Acpi3_0.h b/BaseTools/Source/C/Include/IndustryStandard/Acpi3_0.h
deleted file mode 100644
index 3fd85f60..00000000
--- a/BaseTools/Source/C/Include/IndustryStandard/Acpi3_0.h
+++ /dev/null
@@ -1,668 +0,0 @@
-/** @file
- ACPI 3.0 definitions from the ACPI Specification Revision 3.0 September 2, 2004
-
- Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef _ACPI_3_0_H_
-#define _ACPI_3_0_H_
-
-#include "IndustryStandard/Acpi.h"
-
-//
-// Ensure proper structure formats
-//
-#pragma pack(1)
-//
-// ACPI Specification Revision
-//
-#define EFI_ACPI_3_0_REVISION 0x03 // BUGBUG: Not in spec yet.
-//
-// BUGBUG: OEM values need to be moved somewhere else, probably read from data hub
-// and produced by a platform specific driver.
-//
-//
-// ACPI 3.0 Generic Address Space definition
-//
-typedef struct {
- UINT8 AddressSpaceId;
- UINT8 RegisterBitWidth;
- UINT8 RegisterBitOffset;
- UINT8 AccessSize;
- UINT64 Address;
-} EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE;
-
-//
-// Generic Address Space Address IDs
-//
-#define EFI_ACPI_3_0_SYSTEM_MEMORY 0
-#define EFI_ACPI_3_0_SYSTEM_IO 1
-#define EFI_ACPI_3_0_PCI_CONFIGURATION_SPACE 2
-#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER 3
-#define EFI_ACPI_3_0_SMBUS 4
-#define EFI_ACPI_3_0_FUNCTIONAL_FIXED_HARDWARE 0x7F
-
-//
-// Generic Address Space Access Sizes
-//
-#define EFI_ACPI_3_0_UNDEFINED 0
-#define EFI_ACPI_3_0_BYTE 1
-#define EFI_ACPI_3_0_WORD 2
-#define EFI_ACPI_3_0_DWORD 3
-#define EFI_ACPI_3_0_QWORD 4
-
-//
-// ACPI 3.0 table structures
-//
-//
-// Root System Description Pointer Structure
-//
-typedef struct {
- UINT64 Signature;
- UINT8 Checksum;
- UINT8 OemId[6];
- UINT8 Revision;
- UINT32 RsdtAddress;
- UINT32 Length;
- UINT64 XsdtAddress;
- UINT8 ExtendedChecksum;
- UINT8 Reserved[3];
-} EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
-
-//
-// RSD_PTR Revision (as defined in ACPI 3.0 spec.)
-//
-#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 // ACPISpec30 (Revision 3.0 September 2, 2004) says current value is 2
-//
-// Common table header, this prefaces all ACPI tables, including FACS, but
-// excluding the RSD PTR structure
-//
-typedef struct {
- UINT32 Signature;
- UINT32 Length;
-} EFI_ACPI_3_0_COMMON_HEADER;
-
-//
-// Root System Description Table
-// No definition needed as it is a common description table header followed by a
-// variable number of UINT32 table pointers.
-//
-//
-// RSDT Revision (as defined in ACPI 3.0 spec.)
-//
-#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
-
-//
-// Extended System Description Table
-// No definition needed as it is a common description table header followed by a
-// variable number of UINT64 table pointers.
-//
-//
-// XSDT Revision (as defined in ACPI 3.0 spec.)
-//
-#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
-
-//
-// Fixed ACPI Description Table Structure (FADT)
-//
-typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 FirmwareCtrl;
- UINT32 Dsdt;
- UINT8 Reserved0;
- UINT8 PreferredPmProfile;
- UINT16 SciInt;
- UINT32 SmiCmd;
- UINT8 AcpiEnable;
- UINT8 AcpiDisable;
- UINT8 S4BiosReq;
- UINT8 PstateCnt;
- UINT32 Pm1aEvtBlk;
- UINT32 Pm1bEvtBlk;
- UINT32 Pm1aCntBlk;
- UINT32 Pm1bCntBlk;
- UINT32 Pm2CntBlk;
- UINT32 PmTmrBlk;
- UINT32 Gpe0Blk;
- UINT32 Gpe1Blk;
- UINT8 Pm1EvtLen;
- UINT8 Pm1CntLen;
- UINT8 Pm2CntLen;
- UINT8 PmTmrLen;
- UINT8 Gpe0BlkLen;
- UINT8 Gpe1BlkLen;
- UINT8 Gpe1Base;
- UINT8 CstCnt;
- UINT16 PLvl2Lat;
- UINT16 PLvl3Lat;
- UINT16 FlushSize;
- UINT16 FlushStride;
- UINT8 DutyOffset;
- UINT8 DutyWidth;
- UINT8 DayAlrm;
- UINT8 MonAlrm;
- UINT8 Century;
- UINT16 IaPcBootArch;
- UINT8 Reserved1;
- UINT32 Flags;
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
- UINT8 ResetValue;
- UINT8 Reserved2[3];
- UINT64 XFirmwareCtrl;
- UINT64 XDsdt;
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
-} EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE;
-
-//
-// FADT Version (as defined in ACPI 3.0 spec.)
-//
-#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x04
-
-//
-// Fixed ACPI Description Table Preferred Power Management Profile
-//
-#define EFI_ACPI_3_0_PM_PROFILE_UNSPECIFIED 0
-#define EFI_ACPI_3_0_PM_PROFILE_DESKTOP 1
-#define EFI_ACPI_3_0_PM_PROFILE_MOBILE 2
-#define EFI_ACPI_3_0_PM_PROFILE_WORKSTATION 3
-#define EFI_ACPI_3_0_PM_PROFILE_ENTERPRISE_SERVER 4
-#define EFI_ACPI_3_0_PM_PROFILE_SOHO_SERVER 5
-#define EFI_ACPI_3_0_PM_PROFILE_APPLIANCE_PC 6
-#define EFI_ACPI_3_0_PM_PROFILE_PERFORMANCE_SERVER 7
-
-//
-// Fixed ACPI Description Table Boot Architecture Flags
-// All other bits are reserved and must be set to 0.
-//
-#define EFI_ACPI_3_0_LEGACY_DEVICES (1 << 0)
-#define EFI_ACPI_3_0_8042 (1 << 1)
-#define EFI_ACPI_3_0_VGA_NOT_PRESENT (1 << 2)
-#define EFI_ACPI_3_0_MSI_NOT_SUPPORTED (1 << 3)
-//
-// Fixed ACPI Description Table Fixed Feature Flags
-// All other bits are reserved and must be set to 0.
-//
-#define EFI_ACPI_3_0_WBINVD (1 << 0)
-#define EFI_ACPI_3_0_WBINVD_FLUSH (1 << 1)
-#define EFI_ACPI_3_0_PROC_C1 (1 << 2)
-#define EFI_ACPI_3_0_P_LVL2_UP (1 << 3)
-#define EFI_ACPI_3_0_PWR_BUTTON (1 << 4)
-#define EFI_ACPI_3_0_SLP_BUTTON (1 << 5)
-#define EFI_ACPI_3_0_FIX_RTC (1 << 6)
-#define EFI_ACPI_3_0_RTC_S4 (1 << 7)
-#define EFI_ACPI_3_0_TMR_VAL_EXT (1 << 8)
-#define EFI_ACPI_3_0_DCK_CAP (1 << 9)
-#define EFI_ACPI_3_0_RESET_REG_SUP (1 << 10)
-#define EFI_ACPI_3_0_SEALED_CASE (1 << 11)
-#define EFI_ACPI_3_0_HEADLESS (1 << 12)
-#define EFI_ACPI_3_0_CPU_SW_SLP (1 << 13)
-#define EFI_ACPI_3_0_PCI_EXP_WAK (1 << 14)
-#define EFI_ACPI_3_0_USE_PLATFORM_CLOCK (1 << 15)
-#define EFI_ACPI_3_0_S4_RTC_STS_VALID (1 << 16)
-#define EFI_ACPI_3_0_REMOTE_POWER_ON_CAPABLE (1 << 17)
-#define EFI_ACPI_3_0_FORCE_APIC_CLUSTER_MODEL (1 << 18)
-#define EFI_ACPI_3_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE (1 << 19)
-
-//
-// Firmware ACPI Control Structure
-//
-typedef struct {
- UINT32 Signature;
- UINT32 Length;
- UINT32 HardwareSignature;
- UINT32 FirmwareWakingVector;
- UINT32 GlobalLock;
- UINT32 Flags;
- UINT64 XFirmwareWakingVector;
- UINT8 Version;
- UINT8 Reserved[31];
-} EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
-
-//
-// FACS Version (as defined in ACPI 3.0 spec.)
-//
-#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x01
-
-//
-// Firmware Control Structure Feature Flags
-// All other bits are reserved and must be set to 0.
-//
-#define EFI_ACPI_3_0_S4BIOS_F (1 << 0)
-
-//
-// Differentiated System Description Table,
-// Secondary System Description Table
-// and Persistent System Description Table,
-// no definition needed as they are common description table header followed by a
-// definition block.
-//
-#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
-#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
-
-//
-// Multiple APIC Description Table header definition. The rest of the table
-// must be defined in a platform specific manner.
-//
-typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 LocalApicAddress;
- UINT32 Flags;
-} EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
-
-//
-// MADT Revision (as defined in ACPI 3.0 spec.)
-//
-#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x02
-
-//
-// Multiple APIC Flags
-// All other bits are reserved and must be set to 0.
-//
-#define EFI_ACPI_3_0_PCAT_COMPAT (1 << 0)
-
-//
-// Multiple APIC Description Table APIC structure types
-// All other values between 0x09 an 0xFF are reserved and
-// will be ignored by OSPM.
-//
-#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC 0x00
-#define EFI_ACPI_3_0_IO_APIC 0x01
-#define EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE 0x02
-#define EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
-#define EFI_ACPI_3_0_LOCAL_APIC_NMI 0x04
-#define EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
-#define EFI_ACPI_3_0_IO_SAPIC 0x06
-#define EFI_ACPI_3_0_LOCAL_SAPIC 0x07
-#define EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES 0x08
-
-//
-// APIC Structure Definitions
-//
-//
-// Processor Local APIC Structure Definition
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT8 ApicId;
- UINT32 Flags;
-} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
-
-//
-// Local APIC Flags. All other bits are reserved and must be 0.
-//
-#define EFI_ACPI_3_0_LOCAL_APIC_ENABLED (1 << 0)
-
-//
-// IO APIC Structure
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 IoApicAddress;
- UINT32 GlobalSystemInterruptBase;
-} EFI_ACPI_3_0_IO_APIC_STRUCTURE;
-
-//
-// Interrupt Source Override Structure
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Bus;
- UINT8 Source;
- UINT32 GlobalSystemInterrupt;
- UINT16 Flags;
-} EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
-
-//
-// Platform Interrupt Sources Structure Definition
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT8 InterruptType;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT8 IoSapicVector;
- UINT32 GlobalSystemInterrupt;
- UINT32 PlatformInterruptSourceFlags;
- UINT8 CpeiProcessorOverride;
- UINT8 Reserved[31];
-} EFI_ACPI_3_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;
-
-//
-// MPS INTI flags.
-// All other bits are reserved and must be set to 0.
-//
-#define EFI_ACPI_3_0_POLARITY (3 << 0)
-#define EFI_ACPI_3_0_TRIGGER_MODE (3 << 2)
-
-//
-// Non-Maskable Interrupt Source Structure
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT32 GlobalSystemInterrupt;
-} EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
-
-//
-// Local APIC NMI Structure
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT16 Flags;
- UINT8 LocalApicLint;
-} EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE;
-
-//
-// Local APIC Address Override Structure
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT64 LocalApicAddress;
-} EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
-
-//
-// IO SAPIC Structure
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 GlobalSystemInterruptBase;
- UINT64 IoSapicAddress;
-} EFI_ACPI_3_0_IO_SAPIC_STRUCTURE;
-
-//
-// Local SAPIC Structure
-// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT8 LocalSapicId;
- UINT8 LocalSapicEid;
- UINT8 Reserved[3];
- UINT32 Flags;
- UINT32 ACPIProcessorUIDValue;
-} EFI_ACPI_3_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
-
-//
-// Platform Interrupt Sources Structure
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT8 InterruptType;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT8 IoSapicVector;
- UINT32 GlobalSystemInterrupt;
- UINT32 PlatformInterruptSourceFlags;
-} EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
-
-//
-// Platform Interrupt Source Flags.
-// All other bits are reserved and must be set to 0.
-//
-#define EFI_ACPI_3_0_CPEI_PROCESSOR_OVERRIDE (1 << 0)
-
-//
-// Smart Battery Description Table (SBST)
-//
-typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 WarningEnergyLevel;
- UINT32 LowEnergyLevel;
- UINT32 CriticalEnergyLevel;
-} EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE;
-
-//
-// SBST Version (as defined in ACPI 3.0 spec.)
-//
-#define EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
-
-//
-// Embedded Controller Boot Resources Table (ECDT)
-// The table is followed by a null terminated ASCII string that contains
-// a fully qualified reference to the name space object.
-//
-typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcControl;
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcData;
- UINT32 Uid;
- UINT8 GpeBit;
-} EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
-
-//
-// ECDT Version (as defined in ACPI 3.0 spec.)
-//
-#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
-
-//
-// System Resource Affinity Table (SRAT. The rest of the table
-// must be defined in a platform specific manner.
-//
-typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Reserved1; // Must be set to 1
- UINT64 Reserved2;
-} EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
-
-//
-// SRAT Version (as defined in ACPI 3.0 spec.)
-//
-#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x02
-
-//
-// SRAT structure types.
-// All other values between 0x02 an 0xFF are reserved and
-// will be ignored by OSPM.
-//
-#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00
-#define EFI_ACPI_3_0_MEMORY_AFFINITY 0x01
-
-//
-// Processor Local APIC/SAPIC Affinity Structure Definition
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 ProximityDomain7To0;
- UINT8 ApicId;
- UINT32 Flags;
- UINT8 LocalSapicEid;
- UINT8 ProximityDomain31To8[3];
- UINT8 Reserved[4];
-} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
-
-//
-// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
-//
-#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
-
-//
-// Memory Affinity Structure Definition
-//
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 ProximityDomain;
- UINT16 Reserved1;
- UINT32 AddressBaseLow;
- UINT32 AddressBaseHigh;
- UINT32 LengthLow;
- UINT32 LengthHigh;
- UINT32 Reserved2;
- UINT32 Flags;
- UINT64 Reserved3;
-} EFI_ACPI_3_0_MEMORY_AFFINITY_STRUCTURE;
-
-//
-// Memory Flags. All other bits are reserved and must be 0.
-//
-#define EFI_ACPI_3_0_MEMORY_ENABLED (1 << 0)
-#define EFI_ACPI_3_0_MEMORY_HOT_PLUGGABLE (1 << 1)
-#define EFI_ACPI_3_0_MEMORY_NONVOLATILE (1 << 2)
-
-//
-// System Locality Distance Information Table (SLIT).
-// The rest of the table is a matrix.
-//
-typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 NumberOfSystemLocalities;
-} EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
-
-//
-// SLIT Version (as defined in ACPI 3.0 spec.)
-//
-#define EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01
-
-//
-// Known table signatures
-//
-//
-// "RSD PTR " Root System Description Pointer
-//
-#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE 0x2052545020445352ULL
-
-//
-// "APIC" Multiple APIC Description Table
-//
-#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE 0x43495041
-
-//
-// "DSDT" Differentiated System Description Table
-//
-#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445344
-
-//
-// "ECDT" Embedded Controller Boot Resources Table
-//
-#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE 0x54444345
-
-//
-// "FACP" Fixed ACPI Description Table
-//
-#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE 0x50434146
-
-//
-// "FACS" Firmware ACPI Control Structure
-//
-#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE 0x53434146
-
-//
-// "PSDT" Persistent System Description Table
-//
-#define EFI_ACPI_3_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445350
-
-//
-// "RSDT" Root System Description Table
-//
-#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445352
-
-//
-// "SBST" Smart Battery Specification Table
-//
-#define EFI_ACPI_3_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE 0x54534253
-
-//
-// "SLIT" System Locality Information Table
-//
-#define EFI_ACPI_3_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE 0x54494C53
-
-//
-// "SRAT" System Resource Affinity Table
-//
-#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE 0x54415253
-
-//
-// "SSDT" Secondary System Description Table
-//
-#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445353
-
-//
-// "XSDT" Extended System Description Table
-//
-#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445358
-
-//
-// "BOOT" MS Simple Boot Spec
-//
-#define EFI_ACPI_3_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE 0x544F4F42
-
-//
-// "CPEP" Corrected Platform Error Polling Table
-// See
-//
-#define EFI_ACPI_3_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE 0x50455043
-
-//
-// "DBGP" MS Debug Port Spec
-//
-#define EFI_ACPI_3_0_DEBUG_PORT_TABLE_SIGNATURE 0x50474244
-
-//
-// "ETDT" Event Timer Description Table
-//
-#define EFI_ACPI_3_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE 0x54445445
-
-//
-// "HPET" IA-PC High Precision Event Timer Table
-//
-#define EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE 0x54455048
-
-//
-// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
-//
-#define EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE 0x4746434D
-
-//
-// "SPCR" Serial Port Console Redirection Table
-//
-#define EFI_ACPI_3_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE 0x52435053
-
-//
-// "SPMI" Server Platform Management Interface Table
-//
-#define EFI_ACPI_3_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE 0x494D5053
-
-//
-// "TCPA" Trusted Computing Platform Alliance Capabilities Table
-//
-#define EFI_ACPI_3_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE 0x41504354
-
-//
-// "WDRT" Watchdog Resource Table
-//
-#define EFI_ACPI_3_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE 0x54524457
-
-#pragma pack()
-
-#endif
diff --git a/BaseTools/Source/C/Include/IndustryStandard/Bluetooth.h b/BaseTools/Source/C/Include/IndustryStandard/Bluetooth.h
deleted file mode 100644
index 0e8c5227..00000000
--- a/BaseTools/Source/C/Include/IndustryStandard/Bluetooth.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/** @file
- This file contains the Bluetooth definitions that are consumed by drivers.
- These definitions are from Bluetooth Core Specification Version 4.0 June, 2010
-
- Copyright (c) 2017, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef _BLUETOOTH_H_
-#define _BLUETOOTH_H_
-
-#pragma pack(1)
-
-///
-/// BLUETOOTH_ADDRESS
-///
-typedef struct {
- ///
- /// 48bit Bluetooth device address.
- ///
- UINT8 Address[6];
-} BLUETOOTH_ADDRESS;
-
-///
-/// BLUETOOTH_CLASS_OF_DEVICE. See Bluetooth specification for detail.
-///
-typedef struct {
- UINT8 FormatType:2;
- UINT8 MinorDeviceClass: 6;
- UINT16 MajorDeviceClass: 5;
- UINT16 MajorServiceClass:11;
-} BLUETOOTH_CLASS_OF_DEVICE;
-
-///
-/// BLUETOOTH_LE_ADDRESS
-///
-typedef struct {
- ///
- /// 48-bit Bluetooth device address
- ///
- UINT8 Address[6];
- ///
- /// 0x00 - Public Device Address
- /// 0x01 - Random Device Address
- ///
- UINT8 Type;
-} BLUETOOTH_LE_ADDRESS;
-
-#pragma pack()
-
-#define BLUETOOTH_HCI_COMMAND_LOCAL_READABLE_NAME_MAX_SIZE 248
-
-#define BLUETOOTH_HCI_LINK_KEY_SIZE 16
-
-#endif
diff --git a/BaseTools/Source/C/Include/IndustryStandard/EfiPci.h b/BaseTools/Source/C/Include/IndustryStandard/EfiPci.h
deleted file mode 100644
index 27fa8bd4..00000000
--- a/BaseTools/Source/C/Include/IndustryStandard/EfiPci.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/** @file
- Support for EFI PCI specification.
-
- Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef _EFI_PCI_H_
-#define _EFI_PCI_H_
-
-//#include "pci22.h"
-//#include "pci23.h"
-//#include "pci30.h"
-
-#pragma pack(push, 1)
-
-typedef struct {
- UINT8 Register;
- UINT8 Function;
- UINT8 Device;
- UINT8 Bus;
- UINT8 Reserved[4];
-} DEFIO_PCI_ADDR;
-
-#define EFI_ROOT_BRIDGE_LIST 'eprb'
-#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1
-
-typedef struct {
- UINT16 Signature; // 0xaa55
- UINT16 InitializationSize;
- UINT32 EfiSignature; // 0x0EF1
- UINT16 EfiSubsystem;
- UINT16 EfiMachineType;
- UINT16 CompressionType;
- UINT8 Reserved[8];
- UINT16 EfiImageHeaderOffset;
- UINT16 PcirOffset;
-} EFI_PCI_EXPANSION_ROM_HEADER;
-
-typedef union {
- UINT8 *Raw;
- PCI_EXPANSION_ROM_HEADER *Generic;
- EFI_PCI_EXPANSION_ROM_HEADER *Efi;
- EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;
-} EFI_PCI_ROM_HEADER;
-
-#pragma pack(pop)
-
-#endif
diff --git a/BaseTools/Source/C/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h b/BaseTools/Source/C/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h
deleted file mode 100644
index 5b90a229..00000000
--- a/BaseTools/Source/C/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/** @file
- ACPI memory mapped configuration space access table definition, defined at
- in the PCI Firmware Specification, version 3.0 draft version 0.5.
- Specification is available at http://www.pcisig.com.
-
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_
-#define _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_
-
-//
-// Ensure proper structure formats
-//
-#pragma pack(1)
-//
-// Memory Mapped Configuration Space Access Table (MCFG)
-// This table is a basic description table header followed by
-// a number of base address allocation structures.
-//
-typedef struct {
- UINT64 BaseAddress;
- UINT16 PciSegmentGroupNumber;
- UINT8 StartBusNumber;
- UINT8 EndBusNumber;
- UINT32 Reserved;
-} EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE;
-
-//
-// MCFG Revision (defined in spec)
-//
-#define EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION 0x01
-
-#pragma pack()
-
-#endif
diff --git a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
deleted file mode 100755
index 593c7d2c..00000000
--- a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
+++ /dev/null
@@ -1,778 +0,0 @@
-/** @file
- EFI image format for PE32+. Please note some data structures are different
- for IA-32 and Itanium-based images, look for UINTN and the #ifdef EFI_IA64
-
- @bug Fix text - doc as defined in MSFT EFI specification.
-
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
- Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
- Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
- Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __PE_IMAGE_H__
-#define __PE_IMAGE_H__
-
-//
-// PE32+ Subsystem type for EFI images
-//
-#define EFI_IMAGE_SUBSYSTEM_EFI_APPLICATION 10
-#define EFI_IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER 11
-#define EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER 12
-#define EFI_IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER 13
-
-//
-// BugBug: Need to get a real answer for this problem. This is not in the
-// PE specification.
-//
-// A SAL runtime driver does not get fixed up when a transition to
-// virtual mode is made. In all other cases it should be treated
-// like a EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER image
-//
-#define EFI_IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER 13
-
-//
-// PE32+ Machine type for EFI images
-//
-#define IMAGE_FILE_MACHINE_I386 0x014c
-#define IMAGE_FILE_MACHINE_EBC 0x0EBC
-#define IMAGE_FILE_MACHINE_X64 0x8664
-#define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only
-#define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM and Thumb/Thumb 2 Little Endian
-#define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM Architecture, Little Endian
-#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA
-#define IMAGE_FILE_MACHINE_LOONGARCH64 0x6264 // 64bit LoongArch Architecture
-
-//
-// Support old names for backward compatible
-//
-#define EFI_IMAGE_MACHINE_IA32 IMAGE_FILE_MACHINE_I386
-#define EFI_IMAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC
-#define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64
-#define EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT
-#define EFI_IMAGE_MACHINE_AARCH64 IMAGE_FILE_MACHINE_ARM64
-#define EFI_IMAGE_MACHINE_RISCV64 IMAGE_FILE_MACHINE_RISCV64
-#define EFI_IMAGE_MACHINE_LOONGARCH64 IMAGE_FILE_MACHINE_LOONGARCH64
-
-#define EFI_IMAGE_DOS_SIGNATURE 0x5A4D // MZ
-#define EFI_IMAGE_OS2_SIGNATURE 0x454E // NE
-#define EFI_IMAGE_OS2_SIGNATURE_LE 0x454C // LE
-#define EFI_IMAGE_NT_SIGNATURE 0x00004550 // PE00
-#define EFI_IMAGE_EDOS_SIGNATURE 0x44454550 // PEED
-
-///
-/// PE images can start with an optional DOS header, so if an image is run
-/// under DOS it can print an error message.
-///
-typedef struct {
- UINT16 e_magic; // Magic number
- UINT16 e_cblp; // Bytes on last page of file
- UINT16 e_cp; // Pages in file
- UINT16 e_crlc; // Relocations
- UINT16 e_cparhdr; // Size of header in paragraphs
- UINT16 e_minalloc; // Minimum extra paragraphs needed
- UINT16 e_maxalloc; // Maximum extra paragraphs needed
- UINT16 e_ss; // Initial (relative) SS value
- UINT16 e_sp; // Initial SP value
- UINT16 e_csum; // Checksum
- UINT16 e_ip; // Initial IP value
- UINT16 e_cs; // Initial (relative) CS value
- UINT16 e_lfarlc; // File address of relocation table
- UINT16 e_ovno; // Overlay number
- UINT16 e_res[4]; // Reserved words
- UINT16 e_oemid; // OEM identifier (for e_oeminfo)
- UINT16 e_oeminfo; // OEM information; e_oemid specific
- UINT16 e_res2[10]; // Reserved words
- UINT32 e_lfanew; // File address of new exe header
-} EFI_IMAGE_DOS_HEADER;
-
-///
-/// File header format.
-///
-typedef struct {
- UINT16 Machine;
- UINT16 NumberOfSections;
- UINT32 TimeDateStamp;
- UINT32 PointerToSymbolTable;
- UINT32 NumberOfSymbols;
- UINT16 SizeOfOptionalHeader;
- UINT16 Characteristics;
-} EFI_IMAGE_FILE_HEADER;
-
-#define EFI_IMAGE_SIZEOF_FILE_HEADER 20
-
-#define EFI_IMAGE_FILE_RELOCS_STRIPPED 0x0001 // Relocation info stripped from file.
-#define EFI_IMAGE_FILE_EXECUTABLE_IMAGE 0x0002 // File is executable (i.e. no unresolved externel references).
-#define EFI_IMAGE_FILE_LINE_NUMS_STRIPPED 0x0004 // Line nunbers stripped from file.
-#define EFI_IMAGE_FILE_LOCAL_SYMS_STRIPPED 0x0008 // Local symbols stripped from file.
-#define EFI_IMAGE_FILE_LARGE_ADDRESS_AWARE 0x0020 // Supports addresses > 2-GB
-#define EFI_IMAGE_FILE_BYTES_REVERSED_LO 0x0080 // Bytes of machine word are reversed.
-#define EFI_IMAGE_FILE_32BIT_MACHINE 0x0100 // 32 bit word machine.
-#define EFI_IMAGE_FILE_DEBUG_STRIPPED 0x0200 // Debugging info stripped from file in .DBG file
-#define EFI_IMAGE_FILE_SYSTEM 0x1000 // System File.
-#define EFI_IMAGE_FILE_DLL 0x2000 // File is a DLL.
-#define EFI_IMAGE_FILE_BYTES_REVERSED_HI 0x8000 // Bytes of machine word are reversed.
-#define EFI_IMAGE_FILE_MACHINE_UNKNOWN 0
-#define EFI_IMAGE_FILE_MACHINE_I386 0x14c // Intel 386.
-#define EFI_IMAGE_FILE_MACHINE_R3000 0x162 // MIPS* little-endian, 0540 big-endian
-#define EFI_IMAGE_FILE_MACHINE_R4000 0x166 // MIPS* little-endian
-#define EFI_IMAGE_FILE_MACHINE_ALPHA 0x184 // Alpha_AXP*
-#define EFI_IMAGE_FILE_MACHINE_POWERPC 0x1F0 // IBM* PowerPC Little-Endian
-#define EFI_IMAGE_FILE_MACHINE_TAHOE 0x7cc // Intel EM machine
-//
-// * Other names and brands may be claimed as the property of others.
-//
-
-///
-/// Directory format.
-///
-typedef struct {
- UINT32 VirtualAddress;
- UINT32 Size;
-} EFI_IMAGE_DATA_DIRECTORY;
-
-#define EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES 16
-
-typedef struct {
- UINT16 Magic;
- UINT8 MajorLinkerVersion;
- UINT8 MinorLinkerVersion;
- UINT32 SizeOfCode;
- UINT32 SizeOfInitializedData;
- UINT32 SizeOfUninitializedData;
- UINT32 AddressOfEntryPoint;
- UINT32 BaseOfCode;
- UINT32 BaseOfData;
- UINT32 BaseOfBss;
- UINT32 GprMask;
- UINT32 CprMask[4];
- UINT32 GpValue;
-} EFI_IMAGE_ROM_OPTIONAL_HEADER;
-
-#define EFI_IMAGE_ROM_OPTIONAL_HDR_MAGIC 0x107
-#define EFI_IMAGE_SIZEOF_ROM_OPTIONAL_HEADER sizeof (EFI_IMAGE_ROM_OPTIONAL_HEADER)
-
-typedef struct {
- EFI_IMAGE_FILE_HEADER FileHeader;
- EFI_IMAGE_ROM_OPTIONAL_HEADER OptionalHeader;
-} EFI_IMAGE_ROM_HEADERS;
-
-///
-/// @attention
-/// EFI_IMAGE_OPTIONAL_HEADER32 and EFI_IMAGE_OPTIONAL_HEADER64
-/// are for use ONLY by tools. All proper EFI code MUST use
-/// EFI_IMAGE_OPTIONAL_HEADER ONLY!!!
-///
-#define EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC 0x10b
-
-typedef struct {
- //
- // Standard fields.
- //
- UINT16 Magic;
- UINT8 MajorLinkerVersion;
- UINT8 MinorLinkerVersion;
- UINT32 SizeOfCode;
- UINT32 SizeOfInitializedData;
- UINT32 SizeOfUninitializedData;
- UINT32 AddressOfEntryPoint;
- UINT32 BaseOfCode;
- UINT32 BaseOfData;
- //
- // NT additional fields.
- //
- UINT32 ImageBase;
- UINT32 SectionAlignment;
- UINT32 FileAlignment;
- UINT16 MajorOperatingSystemVersion;
- UINT16 MinorOperatingSystemVersion;
- UINT16 MajorImageVersion;
- UINT16 MinorImageVersion;
- UINT16 MajorSubsystemVersion;
- UINT16 MinorSubsystemVersion;
- UINT32 Win32VersionValue;
- UINT32 SizeOfImage;
- UINT32 SizeOfHeaders;
- UINT32 CheckSum;
- UINT16 Subsystem;
- UINT16 DllCharacteristics;
- UINT32 SizeOfStackReserve;
- UINT32 SizeOfStackCommit;
- UINT32 SizeOfHeapReserve;
- UINT32 SizeOfHeapCommit;
- UINT32 LoaderFlags;
- UINT32 NumberOfRvaAndSizes;
- EFI_IMAGE_DATA_DIRECTORY DataDirectory[EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES];
-} EFI_IMAGE_OPTIONAL_HEADER32;
-
-///
-/// @attention
-/// EFI_IMAGE_OPTIONAL_HEADER32 and EFI_IMAGE_OPTIONAL_HEADER64
-/// are for use ONLY by tools. All proper EFI code MUST use
-/// EFI_IMAGE_OPTIONAL_HEADER ONLY!!!
-///
-#define EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC 0x20b
-
-typedef struct {
- //
- // Standard fields.
- //
- UINT16 Magic;
- UINT8 MajorLinkerVersion;
- UINT8 MinorLinkerVersion;
- UINT32 SizeOfCode;
- UINT32 SizeOfInitializedData;
- UINT32 SizeOfUninitializedData;
- UINT32 AddressOfEntryPoint;
- UINT32 BaseOfCode;
- //
- // NT additional fields.
- //
- UINT64 ImageBase;
- UINT32 SectionAlignment;
- UINT32 FileAlignment;
- UINT16 MajorOperatingSystemVersion;
- UINT16 MinorOperatingSystemVersion;
- UINT16 MajorImageVersion;
- UINT16 MinorImageVersion;
- UINT16 MajorSubsystemVersion;
- UINT16 MinorSubsystemVersion;
- UINT32 Win32VersionValue;
- UINT32 SizeOfImage;
- UINT32 SizeOfHeaders;
- UINT32 CheckSum;
- UINT16 Subsystem;
- UINT16 DllCharacteristics;
- UINT64 SizeOfStackReserve;
- UINT64 SizeOfStackCommit;
- UINT64 SizeOfHeapReserve;
- UINT64 SizeOfHeapCommit;
- UINT32 LoaderFlags;
- UINT32 NumberOfRvaAndSizes;
- EFI_IMAGE_DATA_DIRECTORY DataDirectory[EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES];
-} EFI_IMAGE_OPTIONAL_HEADER64;
-
-///
-/// @attention
-/// EFI_IMAGE_NT_HEADERS32 and EFI_IMAGE_HEADERS64 are for use ONLY
-/// by tools. All proper EFI code MUST use EFI_IMAGE_NT_HEADERS ONLY!!!
-///
-typedef struct {
- UINT32 Signature;
- EFI_IMAGE_FILE_HEADER FileHeader;
- EFI_IMAGE_OPTIONAL_HEADER32 OptionalHeader;
-} EFI_IMAGE_NT_HEADERS32;
-
-#define EFI_IMAGE_SIZEOF_NT_OPTIONAL32_HEADER sizeof (EFI_IMAGE_NT_HEADERS32)
-
-typedef struct {
- UINT32 Signature;
- EFI_IMAGE_FILE_HEADER FileHeader;
- EFI_IMAGE_OPTIONAL_HEADER64 OptionalHeader;
-} EFI_IMAGE_NT_HEADERS64;
-
-#define EFI_IMAGE_SIZEOF_NT_OPTIONAL64_HEADER sizeof (EFI_IMAGE_NT_HEADERS64)
-
-//
-// Subsystem Values
-//
-#define EFI_IMAGE_SUBSYSTEM_UNKNOWN 0
-#define EFI_IMAGE_SUBSYSTEM_NATIVE 1
-#define EFI_IMAGE_SUBSYSTEM_WINDOWS_GUI 2
-#define EFI_IMAGE_SUBSYSTEM_WINDOWS_CUI 3.
-#define EFI_IMAGE_SUBSYSTEM_OS2_CUI 5
-#define EFI_IMAGE_SUBSYSTEM_POSIX_CUI 7
-
-//
-// Directory Entries
-//
-#define EFI_IMAGE_DIRECTORY_ENTRY_EXPORT 0
-#define EFI_IMAGE_DIRECTORY_ENTRY_IMPORT 1
-#define EFI_IMAGE_DIRECTORY_ENTRY_RESOURCE 2
-#define EFI_IMAGE_DIRECTORY_ENTRY_EXCEPTION 3
-#define EFI_IMAGE_DIRECTORY_ENTRY_SECURITY 4
-#define EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC 5
-#define EFI_IMAGE_DIRECTORY_ENTRY_DEBUG 6
-#define EFI_IMAGE_DIRECTORY_ENTRY_COPYRIGHT 7
-#define EFI_IMAGE_DIRECTORY_ENTRY_GLOBALPTR 8
-#define EFI_IMAGE_DIRECTORY_ENTRY_TLS 9
-#define EFI_IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG 10
-
-//
-// Section header format.
-//
-#define EFI_IMAGE_SIZEOF_SHORT_NAME 8
-
-typedef struct {
- UINT8 Name[EFI_IMAGE_SIZEOF_SHORT_NAME];
- union {
- UINT32 PhysicalAddress;
- UINT32 VirtualSize;
- } Misc;
- UINT32 VirtualAddress;
- UINT32 SizeOfRawData;
- UINT32 PointerToRawData;
- UINT32 PointerToRelocations;
- UINT32 PointerToLinenumbers;
- UINT16 NumberOfRelocations;
- UINT16 NumberOfLinenumbers;
- UINT32 Characteristics;
-} EFI_IMAGE_SECTION_HEADER;
-
-#define EFI_IMAGE_SIZEOF_SECTION_HEADER 40
-
-#define EFI_IMAGE_SCN_TYPE_NO_PAD 0x00000008 // Reserved.
-#define EFI_IMAGE_SCN_CNT_CODE 0x00000020
-#define EFI_IMAGE_SCN_CNT_INITIALIZED_DATA 0x00000040
-#define EFI_IMAGE_SCN_CNT_UNINITIALIZED_DATA 0x00000080
-
-#define EFI_IMAGE_SCN_LNK_OTHER 0x00000100 // Reserved.
-#define EFI_IMAGE_SCN_LNK_INFO 0x00000200 // Section contains comments or some other type of information.
-#define EFI_IMAGE_SCN_LNK_REMOVE 0x00000800 // Section contents will not become part of image.
-#define EFI_IMAGE_SCN_LNK_COMDAT 0x00001000
-
-#define EFI_IMAGE_SCN_ALIGN_1BYTES 0x00100000
-#define EFI_IMAGE_SCN_ALIGN_2BYTES 0x00200000
-#define EFI_IMAGE_SCN_ALIGN_4BYTES 0x00300000
-#define EFI_IMAGE_SCN_ALIGN_8BYTES 0x00400000
-#define EFI_IMAGE_SCN_ALIGN_16BYTES 0x00500000
-#define EFI_IMAGE_SCN_ALIGN_32BYTES 0x00600000
-#define EFI_IMAGE_SCN_ALIGN_64BYTES 0x00700000
-
-#define EFI_IMAGE_SCN_MEM_DISCARDABLE 0x02000000
-#define EFI_IMAGE_SCN_MEM_NOT_CACHED 0x04000000
-#define EFI_IMAGE_SCN_MEM_NOT_PAGED 0x08000000
-#define EFI_IMAGE_SCN_MEM_SHARED 0x10000000
-#define EFI_IMAGE_SCN_MEM_EXECUTE 0x20000000
-#define EFI_IMAGE_SCN_MEM_READ 0x40000000
-#define EFI_IMAGE_SCN_MEM_WRITE 0x80000000
-
-///
-/// Symbol format.
-///
-#define EFI_IMAGE_SIZEOF_SYMBOL 18
-
-//
-// Section values.
-//
-// Symbols have a section number of the section in which they are
-// defined. Otherwise, section numbers have the following meanings:
-//
-#define EFI_IMAGE_SYM_UNDEFINED (UINT16) 0 // Symbol is undefined or is common.
-#define EFI_IMAGE_SYM_ABSOLUTE (UINT16) -1 // Symbol is an absolute value.
-#define EFI_IMAGE_SYM_DEBUG (UINT16) -2 // Symbol is a special debug item.
-//
-// Type (fundamental) values.
-//
-#define EFI_IMAGE_SYM_TYPE_NULL 0 // no type.
-#define EFI_IMAGE_SYM_TYPE_VOID 1 //
-#define EFI_IMAGE_SYM_TYPE_CHAR 2 // type character.
-#define EFI_IMAGE_SYM_TYPE_SHORT 3 // type short integer.
-#define EFI_IMAGE_SYM_TYPE_INT 4
-#define EFI_IMAGE_SYM_TYPE_LONG 5
-#define EFI_IMAGE_SYM_TYPE_FLOAT 6
-#define EFI_IMAGE_SYM_TYPE_DOUBLE 7
-#define EFI_IMAGE_SYM_TYPE_STRUCT 8
-#define EFI_IMAGE_SYM_TYPE_UNION 9
-#define EFI_IMAGE_SYM_TYPE_ENUM 10 // enumeration.
-#define EFI_IMAGE_SYM_TYPE_MOE 11 // member of enumeration.
-#define EFI_IMAGE_SYM_TYPE_BYTE 12
-#define EFI_IMAGE_SYM_TYPE_WORD 13
-#define EFI_IMAGE_SYM_TYPE_UINT 14
-#define EFI_IMAGE_SYM_TYPE_DWORD 15
-
-//
-// Type (derived) values.
-//
-#define EFI_IMAGE_SYM_DTYPE_NULL 0 // no derived type.
-#define EFI_IMAGE_SYM_DTYPE_POINTER 1
-#define EFI_IMAGE_SYM_DTYPE_FUNCTION 2
-#define EFI_IMAGE_SYM_DTYPE_ARRAY 3
-
-//
-// Storage classes.
-//
-#define EFI_IMAGE_SYM_CLASS_END_OF_FUNCTION (UINT8) -1
-#define EFI_IMAGE_SYM_CLASS_NULL 0
-#define EFI_IMAGE_SYM_CLASS_AUTOMATIC 1
-#define EFI_IMAGE_SYM_CLASS_EXTERNAL 2
-#define EFI_IMAGE_SYM_CLASS_STATIC 3
-#define EFI_IMAGE_SYM_CLASS_REGISTER 4
-#define EFI_IMAGE_SYM_CLASS_EXTERNAL_DEF 5
-#define EFI_IMAGE_SYM_CLASS_LABEL 6
-#define EFI_IMAGE_SYM_CLASS_UNDEFINED_LABEL 7
-#define EFI_IMAGE_SYM_CLASS_MEMBER_OF_STRUCT 8
-#define EFI_IMAGE_SYM_CLASS_ARGUMENT 9
-#define EFI_IMAGE_SYM_CLASS_STRUCT_TAG 10
-#define EFI_IMAGE_SYM_CLASS_MEMBER_OF_UNION 11
-#define EFI_IMAGE_SYM_CLASS_UNION_TAG 12
-#define EFI_IMAGE_SYM_CLASS_TYPE_DEFINITION 13
-#define EFI_IMAGE_SYM_CLASS_UNDEFINED_STATIC 14
-#define EFI_IMAGE_SYM_CLASS_ENUM_TAG 15
-#define EFI_IMAGE_SYM_CLASS_MEMBER_OF_ENUM 16
-#define EFI_IMAGE_SYM_CLASS_REGISTER_PARAM 17
-#define EFI_IMAGE_SYM_CLASS_BIT_FIELD 18
-#define EFI_IMAGE_SYM_CLASS_BLOCK 100
-#define EFI_IMAGE_SYM_CLASS_FUNCTION 101
-#define EFI_IMAGE_SYM_CLASS_END_OF_STRUCT 102
-#define EFI_IMAGE_SYM_CLASS_FILE 103
-#define EFI_IMAGE_SYM_CLASS_SECTION 104
-#define EFI_IMAGE_SYM_CLASS_WEAK_EXTERNAL 105
-
-//
-// type packing constants
-//
-#define EFI_IMAGE_N_BTMASK 017
-#define EFI_IMAGE_N_TMASK 060
-#define EFI_IMAGE_N_TMASK1 0300
-#define EFI_IMAGE_N_TMASK2 0360
-#define EFI_IMAGE_N_BTSHFT 4
-#define EFI_IMAGE_N_TSHIFT 2
-
-//
-// Communal selection types.
-//
-#define EFI_IMAGE_COMDAT_SELECT_NODUPLICATES 1
-#define EFI_IMAGE_COMDAT_SELECT_ANY 2
-#define EFI_IMAGE_COMDAT_SELECT_SAME_SIZE 3
-#define EFI_IMAGE_COMDAT_SELECT_EXACT_MATCH 4
-#define EFI_IMAGE_COMDAT_SELECT_ASSOCIATIVE 5
-
-#define EFI_IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY 1
-#define EFI_IMAGE_WEAK_EXTERN_SEARCH_LIBRARY 2
-#define EFI_IMAGE_WEAK_EXTERN_SEARCH_ALIAS 3
-
-///
-/// Relocation format.
-///
-typedef struct {
- UINT32 VirtualAddress;
- UINT32 SymbolTableIndex;
- UINT16 Type;
-} EFI_IMAGE_RELOCATION;
-
-#define EFI_IMAGE_SIZEOF_RELOCATION 10
-
-//
-// I386 relocation types.
-//
-#define EFI_IMAGE_REL_I386_ABSOLUTE 0 // Reference is absolute, no relocation is necessary
-#define EFI_IMAGE_REL_I386_DIR16 01 // Direct 16-bit reference to the symbols virtual address
-#define EFI_IMAGE_REL_I386_REL16 02 // PC-relative 16-bit reference to the symbols virtual address
-#define EFI_IMAGE_REL_I386_DIR32 06 // Direct 32-bit reference to the symbols virtual address
-#define EFI_IMAGE_REL_I386_DIR32NB 07 // Direct 32-bit reference to the symbols virtual address, base not included
-#define EFI_IMAGE_REL_I386_SEG12 09 // Direct 16-bit reference to the segment-selector bits of a 32-bit virtual address
-#define EFI_IMAGE_REL_I386_SECTION 010
-#define EFI_IMAGE_REL_I386_SECREL 011
-#define EFI_IMAGE_REL_I386_REL32 020 // PC-relative 32-bit reference to the symbols virtual address
-
-//
-// x64 processor relocation types.
-//
-#define IMAGE_REL_AMD64_ABSOLUTE 0x0000
-#define IMAGE_REL_AMD64_ADDR64 0x0001
-#define IMAGE_REL_AMD64_ADDR32 0x0002
-#define IMAGE_REL_AMD64_ADDR32NB 0x0003
-#define IMAGE_REL_AMD64_REL32 0x0004
-#define IMAGE_REL_AMD64_REL32_1 0x0005
-#define IMAGE_REL_AMD64_REL32_2 0x0006
-#define IMAGE_REL_AMD64_REL32_3 0x0007
-#define IMAGE_REL_AMD64_REL32_4 0x0008
-#define IMAGE_REL_AMD64_REL32_5 0x0009
-#define IMAGE_REL_AMD64_SECTION 0x000A
-#define IMAGE_REL_AMD64_SECREL 0x000B
-#define IMAGE_REL_AMD64_SECREL7 0x000C
-#define IMAGE_REL_AMD64_TOKEN 0x000D
-#define IMAGE_REL_AMD64_SREL32 0x000E
-#define IMAGE_REL_AMD64_PAIR 0x000F
-#define IMAGE_REL_AMD64_SSPAN32 0x0010
-
-///
-/// Based relocation format.
-///
-typedef struct {
- UINT32 VirtualAddress;
- UINT32 SizeOfBlock;
-} EFI_IMAGE_BASE_RELOCATION;
-
-#define EFI_IMAGE_SIZEOF_BASE_RELOCATION 8
-
-//
-// Based relocation types.
-//
-#define EFI_IMAGE_REL_BASED_ABSOLUTE 0
-#define EFI_IMAGE_REL_BASED_HIGH 1
-#define EFI_IMAGE_REL_BASED_LOW 2
-#define EFI_IMAGE_REL_BASED_HIGHLOW 3
-#define EFI_IMAGE_REL_BASED_HIGHADJ 4
-#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5
-#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5
-#define EFI_IMAGE_REL_BASED_RISCV_HI20 5
-#define EFI_IMAGE_REL_BASED_ARM_MOV32T 7
-#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7
-#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8
-#define EFI_IMAGE_REL_BASED_LOONGARCH32_MARK_LA 8
-#define EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA 8
-#define EFI_IMAGE_REL_BASED_IA64_IMM64 9
-#define EFI_IMAGE_REL_BASED_DIR64 10
-
-
-///
-/// Line number format.
-///
-typedef struct {
- union {
- UINT32 SymbolTableIndex; // Symbol table index of function name if Linenumber is 0.
- UINT32 VirtualAddress; // Virtual address of line number.
- } Type;
- UINT16 Linenumber; // Line number.
-} EFI_IMAGE_LINENUMBER;
-
-#define EFI_IMAGE_SIZEOF_LINENUMBER 6
-
-//
-// Archive format.
-//
-#define EFI_IMAGE_ARCHIVE_START_SIZE 8
-#define EFI_IMAGE_ARCHIVE_START "!\n"
-#define EFI_IMAGE_ARCHIVE_END "`\n"
-#define EFI_IMAGE_ARCHIVE_PAD "\n"
-#define EFI_IMAGE_ARCHIVE_LINKER_MEMBER "/ "
-#define EFI_IMAGE_ARCHIVE_LONGNAMES_MEMBER "// "
-
-typedef struct {
- UINT8 Name[16]; // File member name - `/' terminated.
- UINT8 Date[12]; // File member date - decimal.
- UINT8 UserID[6]; // File member user id - decimal.
- UINT8 GroupID[6]; // File member group id - decimal.
- UINT8 Mode[8]; // File member mode - octal.
- UINT8 Size[10]; // File member size - decimal.
- UINT8 EndHeader[2]; // String to end header.
-} EFI_IMAGE_ARCHIVE_MEMBER_HEADER;
-
-#define EFI_IMAGE_SIZEOF_ARCHIVE_MEMBER_HDR 60
-
-//
-// DLL support.
-//
-
-///
-/// DLL Export Format
-///
-typedef struct {
- UINT32 Characteristics;
- UINT32 TimeDateStamp;
- UINT16 MajorVersion;
- UINT16 MinorVersion;
- UINT32 Name;
- UINT32 Base;
- UINT32 NumberOfFunctions;
- UINT32 NumberOfNames;
- UINT32 AddressOfFunctions;
- UINT32 AddressOfNames;
- UINT32 AddressOfNameOrdinals;
-} EFI_IMAGE_EXPORT_DIRECTORY;
-
-//
-// Based export types.
-//
-#define EFI_IMAGE_EXPORT_ORDINAL_BASE 1
-#define EFI_IMAGE_EXPORT_ADDR_SIZE 4
-#define EFI_IMAGE_EXPORT_ORDINAL_SIZE 2
-
-///
-/// DLL support.
-/// Import Format
-///
-typedef struct {
- UINT16 Hint;
- UINT8 Name[1];
-} EFI_IMAGE_IMPORT_BY_NAME;
-
-typedef struct {
- union {
- UINT32 Function;
- UINT32 Ordinal;
- EFI_IMAGE_IMPORT_BY_NAME *AddressOfData;
- } u1;
-} EFI_IMAGE_THUNK_DATA;
-
-#define EFI_IMAGE_ORDINAL_FLAG 0x80000000
-#define EFI_IMAGE_SNAP_BY_ORDINAL(Ordinal) ((Ordinal & EFI_IMAGE_ORDINAL_FLAG) != 0)
-#define EFI_IMAGE_ORDINAL(Ordinal) (Ordinal & 0xffff)
-
-typedef struct {
- UINT32 Characteristics;
- UINT32 TimeDateStamp;
- UINT32 ForwarderChain;
- UINT32 Name;
- EFI_IMAGE_THUNK_DATA *FirstThunk;
-} EFI_IMAGE_IMPORT_DESCRIPTOR;
-
-///
-/// Debug Format
-///
-#define EFI_IMAGE_DEBUG_TYPE_CODEVIEW 2
-
-typedef struct {
- UINT32 Characteristics;
- UINT32 TimeDateStamp;
- UINT16 MajorVersion;
- UINT16 MinorVersion;
- UINT32 Type;
- UINT32 SizeOfData;
- UINT32 RVA;
- UINT32 FileOffset;
-} EFI_IMAGE_DEBUG_DIRECTORY_ENTRY;
-
-#define CODEVIEW_SIGNATURE_NB10 0x3031424E // "NB10"
-typedef struct {
- UINT32 Signature; // "NB10"
- UINT32 Unknown;
- UINT32 Unknown2;
- UINT32 Unknown3;
- //
- // Filename of .PDB goes here
- //
-} EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY;
-
-#define CODEVIEW_SIGNATURE_RSDS 0x53445352 // "RSDS"
-typedef struct {
- UINT32 Signature; // "RSDS"
- UINT32 Unknown;
- UINT32 Unknown2;
- UINT32 Unknown3;
- UINT32 Unknown4;
- UINT32 Unknown5;
- //
- // Filename of .PDB goes here
- //
-} EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY;
-
-///
-/// Debug Data Structure defined by Apple Mach-O to Coff utility
-///
-#define CODEVIEW_SIGNATURE_MTOC SIGNATURE_32('M', 'T', 'O', 'C')
-typedef struct {
- UINT32 Signature; ///< "MTOC"
- EFI_GUID MachOUuid;
- //
- // Filename of .DLL (Mach-O with debug info) goes here
- //
-} EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY;
-
-//
-// .pdata entries for X64
-//
-typedef struct {
- UINT32 FunctionStartAddress;
- UINT32 FunctionEndAddress;
- UINT32 UnwindInfoAddress;
-} RUNTIME_FUNCTION;
-
-typedef struct {
- UINT8 Version:3;
- UINT8 Flags:5;
- UINT8 SizeOfProlog;
- UINT8 CountOfUnwindCodes;
- UINT8 FrameRegister:4;
- UINT8 FrameRegisterOffset:4;
-} UNWIND_INFO;
-
-///
-/// Resource format.
-///
-typedef struct {
- UINT32 Characteristics;
- UINT32 TimeDateStamp;
- UINT16 MajorVersion;
- UINT16 MinorVersion;
- UINT16 NumberOfNamedEntries;
- UINT16 NumberOfIdEntries;
- //
- // Array of EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY entries goes here.
- //
-} EFI_IMAGE_RESOURCE_DIRECTORY;
-
-///
-/// Resource directory entry format.
-///
-typedef struct {
- union {
- struct {
- UINT32 NameOffset:31;
- UINT32 NameIsString:1;
- } s;
- UINT32 Id;
- } u1;
- union {
- UINT32 OffsetToData;
- struct {
- UINT32 OffsetToDirectory:31;
- UINT32 DataIsDirectory:1;
- } s;
- } u2;
-} EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY;
-
-///
-/// Resource directory entry for string.
-///
-typedef struct {
- UINT16 Length;
- CHAR16 String[1];
-} EFI_IMAGE_RESOURCE_DIRECTORY_STRING;
-
-///
-/// Resource directory entry for data array.
-///
-typedef struct {
- UINT32 OffsetToData;
- UINT32 Size;
- UINT32 CodePage;
- UINT32 Reserved;
-} EFI_IMAGE_RESOURCE_DATA_ENTRY;
-
-///
-/// Header format for TE images
-///
-typedef struct {
- UINT16 Signature; // signature for TE format = "VZ"
- UINT16 Machine; // from the original file header
- UINT8 NumberOfSections; // from the original file header
- UINT8 Subsystem; // from original optional header
- UINT16 StrippedSize; // how many bytes we removed from the header
- UINT32 AddressOfEntryPoint; // offset to entry point -- from original optional header
- UINT32 BaseOfCode; // from original image -- required for ITP debug
- UINT64 ImageBase; // from original file header
- EFI_IMAGE_DATA_DIRECTORY DataDirectory[2]; // only base relocation and debug directory
-} EFI_TE_IMAGE_HEADER;
-
-#define EFI_TE_IMAGE_HEADER_SIGNATURE 0x5A56 // "VZ"
-
-//
-// Data directory indexes in our TE image header
-//
-#define EFI_TE_IMAGE_DIRECTORY_ENTRY_BASERELOC 0
-#define EFI_TE_IMAGE_DIRECTORY_ENTRY_DEBUG 1
-
-
-//
-// Union of PE32, PE32+, and TE headers
-//
-typedef union {
- EFI_IMAGE_NT_HEADERS32 Pe32;
- EFI_IMAGE_NT_HEADERS64 Pe32Plus;
- EFI_TE_IMAGE_HEADER Te;
-} EFI_IMAGE_OPTIONAL_HEADER_UNION;
-
-typedef union {
- EFI_IMAGE_NT_HEADERS32 *Pe32;
- EFI_IMAGE_NT_HEADERS64 *Pe32Plus;
- EFI_TE_IMAGE_HEADER *Te;
- EFI_IMAGE_OPTIONAL_HEADER_UNION *Union;
-} EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION;
-
-#endif
diff --git a/BaseTools/Source/C/Include/IndustryStandard/pci22.h b/BaseTools/Source/C/Include/IndustryStandard/pci22.h
deleted file mode 100644
index 616bc473..00000000
--- a/BaseTools/Source/C/Include/IndustryStandard/pci22.h
+++ /dev/null
@@ -1,536 +0,0 @@
-/** @file
- Support for PCI 2.2 standard.
-
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef _PCI22_H
-#define _PCI22_H
-
-#define PCI_MAX_SEGMENT 0
-
-#define PCI_MAX_BUS 255
-
-#define PCI_MAX_DEVICE 31
-#define PCI_MAX_FUNC 7
-
-//
-// Command
-//
-#define PCI_VGA_PALETTE_SNOOP_DISABLED 0x20
-
-#pragma pack(push, 1)
-typedef struct {
- UINT16 VendorId;
- UINT16 DeviceId;
- UINT16 Command;
- UINT16 Status;
- UINT8 RevisionID;
- UINT8 ClassCode[3];
- UINT8 CacheLineSize;
- UINT8 LatencyTimer;
- UINT8 HeaderType;
- UINT8 BIST;
-} PCI_DEVICE_INDEPENDENT_REGION;
-
-typedef struct {
- UINT32 Bar[6];
- UINT32 CISPtr;
- UINT16 SubsystemVendorID;
- UINT16 SubsystemID;
- UINT32 ExpansionRomBar;
- UINT8 CapabilityPtr;
- UINT8 Reserved1[3];
- UINT32 Reserved2;
- UINT8 InterruptLine;
- UINT8 InterruptPin;
- UINT8 MinGnt;
- UINT8 MaxLat;
-} PCI_DEVICE_HEADER_TYPE_REGION;
-
-typedef struct {
- PCI_DEVICE_INDEPENDENT_REGION Hdr;
- PCI_DEVICE_HEADER_TYPE_REGION Device;
-} PCI_TYPE00;
-
-typedef struct {
- UINT32 Bar[2];
- UINT8 PrimaryBus;
- UINT8 SecondaryBus;
- UINT8 SubordinateBus;
- UINT8 SecondaryLatencyTimer;
- UINT8 IoBase;
- UINT8 IoLimit;
- UINT16 SecondaryStatus;
- UINT16 MemoryBase;
- UINT16 MemoryLimit;
- UINT16 PrefetchableMemoryBase;
- UINT16 PrefetchableMemoryLimit;
- UINT32 PrefetchableBaseUpper32;
- UINT32 PrefetchableLimitUpper32;
- UINT16 IoBaseUpper16;
- UINT16 IoLimitUpper16;
- UINT8 CapabilityPtr;
- UINT8 Reserved[3];
- UINT32 ExpansionRomBAR;
- UINT8 InterruptLine;
- UINT8 InterruptPin;
- UINT16 BridgeControl;
-} PCI_BRIDGE_CONTROL_REGISTER;
-
-typedef struct {
- PCI_DEVICE_INDEPENDENT_REGION Hdr;
- PCI_BRIDGE_CONTROL_REGISTER Bridge;
-} PCI_TYPE01;
-
-typedef union {
- PCI_TYPE00 Device;
- PCI_TYPE01 Bridge;
-} PCI_TYPE_GENERIC;
-
-typedef struct {
- UINT32 CardBusSocketReg; // Cardbus Socket/ExCA Base
- // Address Register
- //
- UINT16 Reserved;
- UINT16 SecondaryStatus; // Secondary Status
- UINT8 PciBusNumber; // PCI Bus Number
- UINT8 CardBusBusNumber; // CardBus Bus Number
- UINT8 SubordinateBusNumber; // Subordinate Bus Number
- UINT8 CardBusLatencyTimer; // CardBus Latency Timer
- UINT32 MemoryBase0; // Memory Base Register 0
- UINT32 MemoryLimit0; // Memory Limit Register 0
- UINT32 MemoryBase1;
- UINT32 MemoryLimit1;
- UINT32 IoBase0;
- UINT32 IoLimit0; // I/O Base Register 0
- UINT32 IoBase1; // I/O Limit Register 0
- UINT32 IoLimit1;
- UINT8 InterruptLine; // Interrupt Line
- UINT8 InterruptPin; // Interrupt Pin
- UINT16 BridgeControl; // Bridge Control
-} PCI_CARDBUS_CONTROL_REGISTER;
-
-//
-// Definitions of PCI class bytes and manipulation macros.
-//
-#define PCI_CLASS_OLD 0x00
-#define PCI_CLASS_OLD_OTHER 0x00
-#define PCI_CLASS_OLD_VGA 0x01
-
-#define PCI_CLASS_MASS_STORAGE 0x01
-#define PCI_CLASS_MASS_STORAGE_SCSI 0x00
-#define PCI_CLASS_MASS_STORAGE_IDE 0x01 // obsolete
-#define PCI_CLASS_IDE 0x01
-#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
-#define PCI_CLASS_MASS_STORAGE_IPI 0x03
-#define PCI_CLASS_MASS_STORAGE_RAID 0x04
-#define PCI_CLASS_MASS_STORAGE_OTHER 0x80
-
-#define PCI_CLASS_NETWORK 0x02
-#define PCI_CLASS_NETWORK_ETHERNET 0x00
-#define PCI_CLASS_ETHERNET 0x00 // obsolete
-#define PCI_CLASS_NETWORK_TOKENRING 0x01
-#define PCI_CLASS_NETWORK_FDDI 0x02
-#define PCI_CLASS_NETWORK_ATM 0x03
-#define PCI_CLASS_NETWORK_ISDN 0x04
-#define PCI_CLASS_NETWORK_OTHER 0x80
-
-#define PCI_CLASS_DISPLAY 0x03
-#define PCI_CLASS_DISPLAY_CTRL 0x03 // obsolete
-#define PCI_CLASS_DISPLAY_VGA 0x00
-#define PCI_CLASS_VGA 0x00 // obsolete
-#define PCI_CLASS_DISPLAY_XGA 0x01
-#define PCI_CLASS_DISPLAY_3D 0x02
-#define PCI_CLASS_DISPLAY_OTHER 0x80
-#define PCI_CLASS_DISPLAY_GFX 0x80
-#define PCI_CLASS_GFX 0x80 // obsolete
-#define PCI_CLASS_BRIDGE 0x06
-#define PCI_CLASS_BRIDGE_HOST 0x00
-#define PCI_CLASS_BRIDGE_ISA 0x01
-#define PCI_CLASS_ISA 0x01 // obsolete
-#define PCI_CLASS_BRIDGE_EISA 0x02
-#define PCI_CLASS_BRIDGE_MCA 0x03
-#define PCI_CLASS_BRIDGE_P2P 0x04
-#define PCI_CLASS_BRIDGE_PCMCIA 0x05
-#define PCI_CLASS_BRIDGE_NUBUS 0x06
-#define PCI_CLASS_BRIDGE_CARDBUS 0x07
-#define PCI_CLASS_BRIDGE_RACEWAY 0x08
-#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
-#define PCI_CLASS_ISA_POSITIVE_DECODE 0x80 // obsolete
-
-#define PCI_CLASS_SCC 0x07 // Simple communications controllers
-#define PCI_SUBCLASS_SERIAL 0x00
-#define PCI_IF_GENERIC_XT 0x00
-#define PCI_IF_16450 0x01
-#define PCI_IF_16550 0x02
-#define PCI_IF_16650 0x03
-#define PCI_IF_16750 0x04
-#define PCI_IF_16850 0x05
-#define PCI_IF_16950 0x06
-#define PCI_SUBCLASS_PARALLEL 0x01
-#define PCI_IF_PARALLEL_PORT 0x00
-#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
-#define PCI_IF_ECP_PARALLEL_PORT 0x02
-#define PCI_IF_1284_CONTROLLER 0x03
-#define PCI_IF_1284_DEVICE 0xFE
-#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
-#define PCI_SUBCLASS_MODEM 0x03
-#define PCI_IF_GENERIC_MODEM 0x00
-#define PCI_IF_16450_MODEM 0x01
-#define PCI_IF_16550_MODEM 0x02
-#define PCI_IF_16650_MODEM 0x03
-#define PCI_IF_16750_MODEM 0x04
-#define PCI_SUBCLASS_OTHER 0x80
-
-#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
-#define PCI_SUBCLASS_PIC 0x00
-#define PCI_IF_8259_PIC 0x00
-#define PCI_IF_ISA_PIC 0x01
-#define PCI_IF_EISA_PIC 0x02
-#define PCI_IF_APIC_CONTROLLER 0x10 // I/O APIC interrupt controller , 32 byte none-prefetchable memory.
-#define PCI_IF_APIC_CONTROLLER2 0x20
-#define PCI_SUBCLASS_TIMER 0x02
-#define PCI_IF_8254_TIMER 0x00
-#define PCI_IF_ISA_TIMER 0x01
-#define PCI_EISA_TIMER 0x02
-#define PCI_SUBCLASS_RTC 0x03
-#define PCI_IF_GENERIC_RTC 0x00
-#define PCI_IF_ISA_RTC 0x00
-#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 // HotPlug Controller
-
-#define PCI_CLASS_INPUT_DEVICE 0x09
-#define PCI_SUBCLASS_KEYBOARD 0x00
-#define PCI_SUBCLASS_PEN 0x01
-#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
-#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
-#define PCI_SUBCLASS_GAMEPORT 0x04
-
-#define PCI_CLASS_DOCKING_STATION 0x0A
-
-#define PCI_CLASS_PROCESSOR 0x0B
-#define PCI_SUBCLASS_PROC_386 0x00
-#define PCI_SUBCLASS_PROC_486 0x01
-#define PCI_SUBCLASS_PROC_PENTIUM 0x02
-#define PCI_SUBCLASS_PROC_ALPHA 0x10
-#define PCI_SUBCLASS_PROC_POWERPC 0x20
-#define PCI_SUBCLASS_PROC_MIPS 0x30
-#define PCI_SUBCLASS_PROC_CO_PORC 0x40 // Co-Processor
-
-#define PCI_CLASS_SERIAL 0x0C
-#define PCI_CLASS_SERIAL_FIREWIRE 0x00
-#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
-#define PCI_CLASS_SERIAL_SSA 0x02
-#define PCI_CLASS_SERIAL_USB 0x03
-#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
-#define PCI_CLASS_SERIAL_SMB 0x05
-
-#define PCI_CLASS_WIRELESS 0x0D
-#define PCI_SUBCLASS_IRDA 0x00
-#define PCI_SUBCLASS_IR 0x01
-#define PCI_SUBCLASS_RF 0x02
-
-#define PCI_CLASS_INTELLIGENT_IO 0x0E
-
-#define PCI_CLASS_SATELLITE 0x0F
-#define PCI_SUBCLASS_TV 0x01
-#define PCI_SUBCLASS_AUDIO 0x02
-#define PCI_SUBCLASS_VOICE 0x03
-#define PCI_SUBCLASS_DATA 0x04
-
-#define PCI_SECURITY_CONTROLLER 0x10 // Encryption and decryption controller
-#define PCI_SUBCLASS_NET_COMPUT 0x00
-#define PCI_SUBCLASS_ENTERTAINMENT 0x10
-
-#define PCI_CLASS_DPIO 0x11
-
-#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
-#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
-#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
-
-#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
-#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)
-#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)
-#define IS_PCI_GFX(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)
-#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
-#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
-#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
-#define IS_PCI_SCSI(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)
-#define IS_PCI_RAID(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)
-#define IS_PCI_LPC(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)
-#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)
-#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)
-#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
-
-#define HEADER_TYPE_DEVICE 0x00
-#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
-#define HEADER_TYPE_CARDBUS_BRIDGE 0x02
-
-#define HEADER_TYPE_MULTI_FUNCTION 0x80
-#define HEADER_LAYOUT_CODE 0x7f
-
-#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
-#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
-#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
-
-#define PCI_DEVICE_ROMBAR 0x30
-#define PCI_BRIDGE_ROMBAR 0x38
-
-#define PCI_MAX_BAR 0x0006
-#define PCI_MAX_CONFIG_OFFSET 0x0100
-
-#define PCI_VENDOR_ID_OFFSET 0x00
-#define PCI_DEVICE_ID_OFFSET 0x02
-#define PCI_COMMAND_OFFSET 0x04
-#define PCI_PRIMARY_STATUS_OFFSET 0x06
-#define PCI_REVISION_ID_OFFSET 0x08
-#define PCI_CLASSCODE_OFFSET 0x09
-#define PCI_CACHELINE_SIZE_OFFSET 0x0C
-#define PCI_LATENCY_TIMER_OFFSET 0x0D
-#define PCI_HEADER_TYPE_OFFSET 0x0E
-#define PCI_BIST_OFFSET 0x0F
-#define PCI_BASE_ADDRESSREG_OFFSET 0x10
-#define PCI_CARDBUS_CIS_OFFSET 0x28
-#define PCI_SVID_OFFSET 0x2C // SubSystem Vendor id
-#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
-#define PCI_SID_OFFSET 0x2E // SubSystem ID
-#define PCI_SUBSYSTEM_ID_OFFSET 0x2E
-#define PCI_EXPANSION_ROM_BASE 0x30
-#define PCI_CAPBILITY_POINTER_OFFSET 0x34
-#define PCI_INT_LINE_OFFSET 0x3C // Interrupt Line Register
-#define PCI_INT_PIN_OFFSET 0x3D // Interrupt Pin Register
-#define PCI_MAXGNT_OFFSET 0x3E // Max Grant Register
-#define PCI_MAXLAT_OFFSET 0x3F // Max Latency Register
-
-#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
-#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
-
-#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
-#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
-#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
-
-typedef union {
- struct {
- UINT32 Reg : 8;
- UINT32 Func : 3;
- UINT32 Dev : 5;
- UINT32 Bus : 8;
- UINT32 Reserved : 7;
- UINT32 Enable : 1;
- } Bits;
- UINT32 Uint32;
-} PCI_CONFIG_ACCESS_CF8;
-
-#pragma pack()
-
-#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
-#define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')
-#define PCI_CODE_TYPE_PCAT_IMAGE 0x00
-#define PCI_CODE_TYPE_EFI_IMAGE 0x03
-#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001
-
-#define EFI_PCI_COMMAND_IO_SPACE 0x0001
-#define EFI_PCI_COMMAND_MEMORY_SPACE 0x0002
-#define EFI_PCI_COMMAND_BUS_MASTER 0x0004
-#define EFI_PCI_COMMAND_SPECIAL_CYCLE 0x0008
-#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE 0x0010
-#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP 0x0020
-#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND 0x0040
-#define EFI_PCI_COMMAND_STEPPING_CONTROL 0x0080
-#define EFI_PCI_COMMAND_SERR 0x0100
-#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK 0x0200
-
-#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE 0x0001
-#define EFI_PCI_BRIDGE_CONTROL_SERR 0x0002
-#define EFI_PCI_BRIDGE_CONTROL_ISA 0x0004
-#define EFI_PCI_BRIDGE_CONTROL_VGA 0x0008
-#define EFI_PCI_BRIDGE_CONTROL_VGA_16 0x0010
-#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT 0x0020
-#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS 0x0040
-#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK 0x0080
-#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER 0x0100
-#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER 0x0200
-#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS 0x0400
-#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR 0x0800
-
-//
-// Following are the PCI-CARDBUS bridge control bit
-//
-#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE 0x0080
-#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE 0x0100
-#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE 0x0200
-#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE 0x0400
-
-//
-// Following are the PCI status control bit
-//
-#define EFI_PCI_STATUS_CAPABILITY 0x0010
-#define EFI_PCI_STATUS_66MZ_CAPABLE 0x0020
-#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE 0x0080
-#define EFI_PCI_MASTER_DATA_PARITY_ERROR 0x0100
-
-#define EFI_PCI_CAPABILITY_PTR 0x34
-#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
-
-#pragma pack(1)
-typedef struct {
- UINT16 Signature; // 0xaa55
- UINT8 Reserved[0x16];
- UINT16 PcirOffset;
-} PCI_EXPANSION_ROM_HEADER;
-
-typedef struct {
- UINT16 Signature; // 0xaa55
- UINT8 Size512;
- UINT8 InitEntryPoint[3];
- UINT8 Reserved[0x12];
- UINT16 PcirOffset;
-} EFI_LEGACY_EXPANSION_ROM_HEADER;
-
-typedef struct {
- UINT32 Signature; // "PCIR"
- UINT16 VendorId;
- UINT16 DeviceId;
- UINT16 Reserved0;
- UINT16 Length;
- UINT8 Revision;
- UINT8 ClassCode[3];
- UINT16 ImageLength;
- UINT16 CodeRevision;
- UINT8 CodeType;
- UINT8 Indicator;
- UINT16 Reserved1;
-} PCI_DATA_STRUCTURE;
-
-//
-// PCI Capability List IDs and records
-//
-#define EFI_PCI_CAPABILITY_ID_PMI 0x01
-#define EFI_PCI_CAPABILITY_ID_AGP 0x02
-#define EFI_PCI_CAPABILITY_ID_VPD 0x03
-#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
-#define EFI_PCI_CAPABILITY_ID_MSI 0x05
-#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
-#define EFI_PCI_CAPABILITY_ID_PCIX 0x07
-
-typedef struct {
- UINT8 CapabilityID;
- UINT8 NextItemPtr;
-} EFI_PCI_CAPABILITY_HDR;
-
-//
-// Capability EFI_PCI_CAPABILITY_ID_PMI
-//
-typedef struct {
- EFI_PCI_CAPABILITY_HDR Hdr;
- UINT16 PMC;
- UINT16 PMCSR;
- UINT8 BridgeExtention;
- UINT8 Data;
-} EFI_PCI_CAPABILITY_PMI;
-
-//
-// Capability EFI_PCI_CAPABILITY_ID_AGP
-//
-typedef struct {
- EFI_PCI_CAPABILITY_HDR Hdr;
- UINT8 Rev;
- UINT8 Reserved;
- UINT32 Status;
- UINT32 Command;
-} EFI_PCI_CAPABILITY_AGP;
-
-//
-// Capability EFI_PCI_CAPABILITY_ID_VPD
-//
-typedef struct {
- EFI_PCI_CAPABILITY_HDR Hdr;
- UINT16 AddrReg;
- UINT32 DataReg;
-} EFI_PCI_CAPABILITY_VPD;
-
-//
-// Capability EFI_PCI_CAPABILITY_ID_SLOTID
-//
-typedef struct {
- EFI_PCI_CAPABILITY_HDR Hdr;
- UINT8 ExpnsSlotReg;
- UINT8 ChassisNo;
-} EFI_PCI_CAPABILITY_SLOTID;
-
-//
-// Capability EFI_PCI_CAPABILITY_ID_MSI
-//
-typedef struct {
- EFI_PCI_CAPABILITY_HDR Hdr;
- UINT16 MsgCtrlReg;
- UINT32 MsgAddrReg;
- UINT16 MsgDataReg;
-} EFI_PCI_CAPABILITY_MSI32;
-
-typedef struct {
- EFI_PCI_CAPABILITY_HDR Hdr;
- UINT16 MsgCtrlReg;
- UINT32 MsgAddrRegLsdw;
- UINT32 MsgAddrRegMsdw;
- UINT16 MsgDataReg;
-} EFI_PCI_CAPABILITY_MSI64;
-
-//
-// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG
-//
-typedef struct {
- EFI_PCI_CAPABILITY_HDR Hdr;
- //
- // not finished - fields need to go here
- //
-} EFI_PCI_CAPABILITY_HOTPLUG;
-
-//
-// Capability EFI_PCI_CAPABILITY_ID_PCIX
-//
-typedef struct {
- EFI_PCI_CAPABILITY_HDR Hdr;
- UINT16 CommandReg;
- UINT32 StatusReg;
-} EFI_PCI_CAPABILITY_PCIX;
-
-typedef struct {
- EFI_PCI_CAPABILITY_HDR Hdr;
- UINT16 SecStatusReg;
- UINT32 StatusReg;
- UINT32 SplitTransCtrlRegUp;
- UINT32 SplitTransCtrlRegDn;
-} EFI_PCI_CAPABILITY_PCIX_BRDG;
-
-#define DEVICE_ID_NOCARE 0xFFFF
-
-#define PCI_ACPI_UNUSED 0
-#define PCI_BAR_NOCHANGE 0
-#define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL
-#define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
-#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
-#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
-
-#define PCI_BAR_IDX0 0x00
-#define PCI_BAR_IDX1 0x01
-#define PCI_BAR_IDX2 0x02
-#define PCI_BAR_IDX3 0x03
-#define PCI_BAR_IDX4 0x04
-#define PCI_BAR_IDX5 0x05
-#define PCI_BAR_ALL 0xFF
-
-#pragma pack(pop)
-
-//
-// NOTE: The following header files are included here for
-// compatibility consideration.
-//
-#include "pci23.h"
-#include "pci30.h"
-#include "EfiPci.h"
-
-#endif
diff --git a/BaseTools/Source/C/Include/IndustryStandard/pci23.h b/BaseTools/Source/C/Include/IndustryStandard/pci23.h
deleted file mode 100644
index 256b7989..00000000
--- a/BaseTools/Source/C/Include/IndustryStandard/pci23.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/** @file
- Support for PCI 2.3 standard.
-
- Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef _PCI23_H
-#define _PCI23_H
-
-//#include "pci22.h"
-
-#define PCI_EXP_MAX_CONFIG_OFFSET 0x1000
-#define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10
-
-#endif
diff --git a/BaseTools/Source/C/Include/IndustryStandard/pci30.h b/BaseTools/Source/C/Include/IndustryStandard/pci30.h
deleted file mode 100644
index c1ffa9a0..00000000
--- a/BaseTools/Source/C/Include/IndustryStandard/pci30.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/** @file
- Support for PCI 3.0 standard.
-
- Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef _PCI30_H
-#define _PCI30_H
-
-//#include "pci23.h"
-
-#define PCI_CLASS_MASS_STORAGE_SATADPA 0x06
-
-#pragma pack(push, 1)
-
-typedef struct {
- UINT32 Signature; // "PCIR"
- UINT16 VendorId;
- UINT16 DeviceId;
- UINT16 DeviceListOffset;
- UINT16 Length;
- UINT8 Revision;
- UINT8 ClassCode[3];
- UINT16 ImageLength;
- UINT16 CodeRevision;
- UINT8 CodeType;
- UINT8 Indicator;
- UINT16 MaxRuntimeImageLength;
- UINT16 ConfigUtilityCodeHeaderOffset;
- UINT16 DMTFCLPEntryPointOffset;
-} PCI_3_0_DATA_STRUCTURE;
-
-#pragma pack(pop)
-
-#endif
diff --git a/BaseTools/Source/C/Include/Protocol/DevicePath.h b/BaseTools/Source/C/Include/Protocol/DevicePath.h
index 644499b6..80ebaf98 100644
--- a/BaseTools/Source/C/Include/Protocol/DevicePath.h
+++ b/BaseTools/Source/C/Include/Protocol/DevicePath.h
@@ -14,7 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define __EFI_DEVICE_PATH_H__
#include
-#include
+#include
#include
///
diff --git a/BaseTools/Source/C/Include/X64/ProcessorBind.h b/BaseTools/Source/C/Include/X64/ProcessorBind.h
deleted file mode 100644
index 9d9b7660..00000000
--- a/BaseTools/Source/C/Include/X64/ProcessorBind.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/** @file
- Processor or Compiler specific defines and types x64 (Intel(r) EM64T, AMD64).
-
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __PROCESSOR_BIND_H__
-#define __PROCESSOR_BIND_H__
-
-//
-// Define the processor type so other code can make processor based choices
-//
-#define MDE_CPU_X64
-
-
-//
-// Make sure we are useing the correct packing rules per EFI specification
-//
-#ifndef __GNUC__
-#pragma pack()
-#endif
-
-
-#if _MSC_EXTENSIONS
-
-//
-// Disable warning that make it impossible to compile at /W4
-// This only works for Microsoft* tools
-//
-
-//
-// Disabling bitfield type checking warnings.
-//
-#pragma warning ( disable : 4214 )
-
-//
-// Disabling the unreferenced formal parameter warnings.
-//
-#pragma warning ( disable : 4100 )
-
-//
-// Disable slightly different base types warning as CHAR8 * can not be set
-// to a constant string.
-//
-#pragma warning ( disable : 4057 )
-
-//
-// ASSERT(FALSE) or while (TRUE) are legal constructes so supress this warning
-//
-#pragma warning ( disable : 4127 )
-
-
-#endif
-
-
-#if !defined(__GNUC__) && (__STDC_VERSION__ < 199901L)
- //
- // No ANSI C 2000 stdint.h integer width declarations, so define equivalents
- //
-
- #if _MSC_EXTENSIONS
-
-
- //
- // use Microsoft C compiler dependent integer width types
- //
- typedef unsigned __int64 UINT64;
- typedef __int64 INT64;
- typedef unsigned __int32 UINT32;
- typedef __int32 INT32;
- typedef unsigned short UINT16;
- typedef unsigned short CHAR16;
- typedef short INT16;
- typedef unsigned char BOOLEAN;
- typedef unsigned char UINT8;
- typedef char CHAR8;
- typedef char INT8;
- #else
- #ifdef _EFI_P64
- //
- // P64 - is Intel Itanium(TM) speak for pointers being 64-bit and longs and ints
- // are 32-bits
- //
- typedef unsigned long long UINT64;
- typedef long long INT64;
- typedef unsigned int UINT32;
- typedef int INT32;
- typedef unsigned short CHAR16;
- typedef unsigned short UINT16;
- typedef short INT16;
- typedef unsigned char BOOLEAN;
- typedef unsigned char UINT8;
- typedef char CHAR8;
- typedef char INT8;
- #else
- //
- // Assume LP64 - longs and pointers are 64-bit. Ints are 32-bit.
- //
- typedef unsigned long UINT64;
- typedef long INT64;
- typedef unsigned int UINT32;
- typedef int INT32;
- typedef unsigned short UINT16;
- typedef unsigned short CHAR16;
- typedef short INT16;
- typedef unsigned char BOOLEAN;
- typedef unsigned char UINT8;
- typedef char CHAR8;
- typedef char INT8;
- #endif
- #endif
-
- #define UINT8_MAX 0xff
-
-#else
- //
- // Use ANSI C 2000 stdint.h integer width declarations
- //
- #include
- typedef uint8_t BOOLEAN;
- typedef int8_t INT8;
- typedef uint8_t UINT8;
- typedef int16_t INT16;
- typedef uint16_t UINT16;
- typedef int32_t INT32;
- typedef uint32_t UINT32;
- typedef int64_t INT64;
- typedef uint64_t UINT64;
- typedef char CHAR8;
- typedef uint16_t CHAR16;
-
-#endif
-
-typedef UINT64 UINTN;
-typedef INT64 INTN;
-
-
-//
-// Processor specific defines
-//
-#define MAX_BIT 0x8000000000000000ULL
-#define MAX_2_BITS 0xC000000000000000ULL
-
-//
-// Modifier to ensure that all protocol member functions and EFI intrinsics
-// use the correct C calling convention. All protocol member functions and
-// EFI intrinsics are required to modify their member functions with EFIAPI.
-//
-#if _MSC_EXTENSIONS
- ///
- /// Define the standard calling convention regardless of optimization level.
- /// __cdecl is Microsoft* specific C extension.
- ///
- #define EFIAPI __cdecl
-#elif __GNUC__
- ///
- /// Define the standard calling convention regardless of optimization level.
- /// efidecl is an extension to GCC that supports the differnece between x64
- /// GCC ABI and x64 Microsoft* ABI. EFI is closer to the Microsoft* ABI and
- /// EFIAPI makes sure the right ABI is used for public interfaces.
- /// eficecl is a work in progress and we do not yet have the compiler
- ///
- #define EFIAPI
-#else
- #define EFIAPI
-#endif
-
-//
-// The Microsoft* C compiler can removed references to unreferenced data items
-// if the /OPT:REF linker option is used. We defined a macro as this is a
-// a non standard extension
-//
-#if _MSC_EXTENSIONS
- #define GLOBAL_REMOVE_IF_UNREFERENCED __declspec(selectany)
-#else
- #define GLOBAL_REMOVE_IF_UNREFERENCED
-#endif
-
-#endif
-
diff --git a/BaseTools/Source/C/LzmaCompress/GNUmakefile b/BaseTools/Source/C/LzmaCompress/GNUmakefile
index d8eb9cb4..4fc20a34 100644
--- a/BaseTools/Source/C/LzmaCompress/GNUmakefile
+++ b/BaseTools/Source/C/LzmaCompress/GNUmakefile
@@ -24,4 +24,4 @@ OBJECTS = \
include $(MAKEROOT)/Makefiles/app.makefile
-BUILD_CFLAGS += -D_7ZIP_ST
+CFLAGS += -D_7ZIP_ST
diff --git a/BaseTools/Source/C/Makefiles/NmakeSubdirs.py b/BaseTools/Source/C/Makefiles/NmakeSubdirs.py
index 155eb223..6c64d2d0 100644
--- a/BaseTools/Source/C/Makefiles/NmakeSubdirs.py
+++ b/BaseTools/Source/C/Makefiles/NmakeSubdirs.py
@@ -132,7 +132,7 @@ class ThreadControl(object):
break
self.runningLock.acquire(True)
- self.running.remove(threading.currentThread())
+ self.running.remove(threading.current_thread())
self.runningLock.release()
def Run():
diff --git a/BaseTools/Source/C/Makefiles/app.makefile b/BaseTools/Source/C/Makefiles/app.makefile
index 2be73e2e..426e0c3a 100644
--- a/BaseTools/Source/C/Makefiles/app.makefile
+++ b/BaseTools/Source/C/Makefiles/app.makefile
@@ -12,10 +12,10 @@ include $(MAKEROOT)/Makefiles/header.makefile
APPLICATION = $(MAKEROOT)/bin/$(APPNAME)
.PHONY:all
-all: $(MAKEROOT)/bin $(APPLICATION)
+all: $(MAKEROOT)/bin $(APPLICATION)
-$(APPLICATION): $(OBJECTS)
- $(LINKER) -o $(APPLICATION) $(BUILD_LFLAGS) $(OBJECTS) -L$(MAKEROOT)/libs $(LIBS)
+$(APPLICATION): $(OBJECTS)
+ $(LINKER) -o $(APPLICATION) $(LDFLAGS) $(OBJECTS) -L$(MAKEROOT)/libs $(LIBS)
$(OBJECTS): $(MAKEROOT)/Include/Common/BuildVersion.h
diff --git a/BaseTools/Source/C/Makefiles/footer.makefile b/BaseTools/Source/C/Makefiles/footer.makefile
index 2d6c5695..bd641593 100644
--- a/BaseTools/Source/C/Makefiles/footer.makefile
+++ b/BaseTools/Source/C/Makefiles/footer.makefile
@@ -14,14 +14,14 @@ $(MAKEROOT)/libs-$(HOST_ARCH):
install: $(MAKEROOT)/libs-$(HOST_ARCH) $(LIBRARY)
cp $(LIBRARY) $(MAKEROOT)/libs-$(HOST_ARCH)
-$(LIBRARY): $(OBJECTS)
- $(BUILD_AR) crs $@ $^
+$(LIBRARY): $(OBJECTS)
+ $(AR) crs $@ $^
-%.o : %.c
- $(BUILD_CC) -c $(BUILD_CPPFLAGS) $(BUILD_CFLAGS) $< -o $@
+%.o : %.c
+ $(CC) -c $(CPPFLAGS) $(CFLAGS) $< -o $@
%.o : %.cpp
- $(BUILD_CXX) -c $(BUILD_CPPFLAGS) $(BUILD_CXXFLAGS) $< -o $@
+ $(CXX) -c $(CPPFLAGS) $(CXXFLAGS) $< -o $@
.PHONY: clean
clean:
diff --git a/BaseTools/Source/C/Makefiles/header.makefile b/BaseTools/Source/C/Makefiles/header.makefile
index 9de7444f..b9727e27 100755
--- a/BaseTools/Source/C/Makefiles/header.makefile
+++ b/BaseTools/Source/C/Makefiles/header.makefile
@@ -8,6 +8,8 @@
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent
+EDK2_PATH ?= $(MAKEROOT)/../../..
+
ifndef HOST_ARCH
#
# If HOST_ARCH is not defined, then we use 'uname -m' to attempt
@@ -44,71 +46,73 @@ endif
CYGWIN:=$(findstring CYGWIN, $(shell uname -s))
LINUX:=$(findstring Linux, $(shell uname -s))
DARWIN:=$(findstring Darwin, $(shell uname -s))
-ifeq ($(CXX), llvm)
-BUILD_CC ?= $(CLANG_BIN)clang
-BUILD_CXX ?= $(CLANG_BIN)clang++
-BUILD_AS ?= $(CLANG_BIN)clang
-BUILD_AR ?= $(CLANG_BIN)llvm-ar
-BUILD_LD ?= $(CLANG_BIN)llvm-ld
-else
-BUILD_CC ?= gcc
-BUILD_CXX ?= g++
-BUILD_AS ?= gcc
-BUILD_AR ?= ar
-BUILD_LD ?= ld
+CLANG:=$(shell $(CC) --version | grep clang)
+ifneq ($(CLANG),)
+CC ?= $(CLANG_BIN)clang
+CXX ?= $(CLANG_BIN)clang++
+AS ?= $(CLANG_BIN)clang
+AR ?= $(CLANG_BIN)llvm-ar
+LD ?= $(CLANG_BIN)llvm-ld
+else ifeq ($(origin CC),default)
+CC = gcc
+CXX = g++
+AS = gcc
+AR = ar
+LD = ld
endif
-LINKER ?= $(BUILD_CC)
+LINKER ?= $(CC)
ifeq ($(HOST_ARCH), IA32)
-ARCH_INCLUDE = -I $(MAKEROOT)/Include/Ia32/
+ARCH_INCLUDE = -I $(EDK2_PATH)/MdePkg/Include/Ia32/
else ifeq ($(HOST_ARCH), X64)
-ARCH_INCLUDE = -I $(MAKEROOT)/Include/X64/
+ARCH_INCLUDE = -I $(EDK2_PATH)/MdePkg/Include/X64/
else ifeq ($(HOST_ARCH), ARM)
-ARCH_INCLUDE = -I $(MAKEROOT)/Include/Arm/
+ARCH_INCLUDE = -I $(EDK2_PATH)/MdePkg/Include/Arm/
else ifeq ($(HOST_ARCH), AARCH64)
-ARCH_INCLUDE = -I $(MAKEROOT)/Include/AArch64/
+ARCH_INCLUDE = -I $(EDK2_PATH)/MdePkg/Include/AArch64/
else ifeq ($(HOST_ARCH), RISCV64)
-ARCH_INCLUDE = -I $(MAKEROOT)/Include/RiscV64/
+ARCH_INCLUDE = -I $(EDK2_PATH)/MdePkg/Include/RiscV64/
else ifeq ($(HOST_ARCH), LOONGARCH64)
-ARCH_INCLUDE = -I $(MAKEROOT)/Include/LoongArch64/
+ARCH_INCLUDE = -I $(EDK2_PATH)/MdePkg/Include/LoongArch64/
else
$(error Bad HOST_ARCH)
endif
INCLUDE = $(TOOL_INCLUDE) -I $(MAKEROOT) -I $(MAKEROOT)/Include/Common -I $(MAKEROOT)/Include/ -I $(MAKEROOT)/Include/IndustryStandard -I $(MAKEROOT)/Common/ -I .. -I . $(ARCH_INCLUDE)
-BUILD_CPPFLAGS = $(INCLUDE)
+INCLUDE += -I $(EDK2_PATH)/MdePkg/Include
+CPPFLAGS = $(INCLUDE)
# keep EXTRA_OPTFLAGS last
BUILD_OPTFLAGS = -O2 $(EXTRA_OPTFLAGS)
ifeq ($(DARWIN),Darwin)
# assume clang or clang compatible flags on OS X
-BUILD_CFLAGS = -MD -fshort-wchar -fno-strict-aliasing -Wall -Werror \
+CFLAGS = -MD -fshort-wchar -fno-strict-aliasing -Wall -Werror \
-Wno-deprecated-declarations -Wno-self-assign -Wno-unused-result -nostdlib -g
else
-ifeq ($(CXX), llvm)
-BUILD_CFLAGS = -MD -fshort-wchar -fno-strict-aliasing -fwrapv \
+ifneq ($(CLANG),)
+CFLAGS = -MD -fshort-wchar -fno-strict-aliasing -fwrapv \
-fno-delete-null-pointer-checks -Wall -Werror \
-Wno-deprecated-declarations -Wno-self-assign \
-Wno-unused-result -nostdlib -g
else
-BUILD_CFLAGS = -MD -fshort-wchar -fno-strict-aliasing -fwrapv \
+CFLAGS = -MD -fshort-wchar -fno-strict-aliasing -fwrapv \
-fno-delete-null-pointer-checks -Wall -Werror \
-Wno-deprecated-declarations -Wno-stringop-truncation -Wno-restrict \
-Wno-unused-result -nostdlib -g
endif
endif
-ifeq ($(CXX), llvm)
-BUILD_LFLAGS =
-BUILD_CXXFLAGS = -Wno-deprecated-register -Wno-unused-result
+ifneq ($(CLANG),)
+LDFLAGS =
+CXXFLAGS = -Wno-deprecated-register -Wno-unused-result -std=c++14
else
-BUILD_LFLAGS =
-BUILD_CXXFLAGS = -Wno-unused-result
+LDFLAGS =
+CXXFLAGS = -Wno-unused-result
endif
ifeq ($(HOST_ARCH), IA32)
#
@@ -117,18 +121,18 @@ ifeq ($(HOST_ARCH), IA32)
# so only do this is uname -m returns i386.
#
ifeq ($(DARWIN),Darwin)
- BUILD_CFLAGS += -arch i386
- BUILD_CPPFLAGS += -arch i386
- BUILD_LFLAGS += -arch i386
+ CFLAGS += -arch i386
+ CPPFLAGS += -arch i386
+ LDFLAGS += -arch i386
endif
endif
# keep BUILD_OPTFLAGS last
-BUILD_CFLAGS += $(BUILD_OPTFLAGS)
-BUILD_CXXFLAGS += $(BUILD_OPTFLAGS)
+CFLAGS += $(BUILD_OPTFLAGS)
+CXXFLAGS += $(BUILD_OPTFLAGS)
# keep EXTRA_LDFLAGS last
-BUILD_LFLAGS += $(EXTRA_LDFLAGS)
+LDFLAGS += $(EXTRA_LDFLAGS)
.PHONY: all
.PHONY: install
diff --git a/BaseTools/Source/C/Makefiles/lib.makefile b/BaseTools/Source/C/Makefiles/lib.makefile
index e4bec8c3..ea6bf247 100644
--- a/BaseTools/Source/C/Makefiles/lib.makefile
+++ b/BaseTools/Source/C/Makefiles/lib.makefile
@@ -9,6 +9,6 @@ include $(MAKEROOT)/Makefiles/header.makefile
LIBRARY = $(MAKEROOT)/libs/lib$(LIBNAME).a
-all: $(MAKEROOT)/libs $(LIBRARY)
+all: $(MAKEROOT)/libs $(LIBRARY)
include $(MAKEROOT)/Makefiles/footer.makefile
diff --git a/BaseTools/Source/C/Makefiles/ms.common b/BaseTools/Source/C/Makefiles/ms.common
index 9811fd99..fb94837d 100644
--- a/BaseTools/Source/C/Makefiles/ms.common
+++ b/BaseTools/Source/C/Makefiles/ms.common
@@ -17,6 +17,14 @@
HOST_ARCH = IA32
!ENDIF
+!IFNDEF MAKEROOT
+MAKEROOT = $(SOURCE_PATH)
+!ENDIF
+
+!IFNDEF EDK2_PATH
+EDK2_PATH = $(MAKEROOT)\..\..\..
+!ENDIF
+
MAKE = nmake -nologo
# DOS del command doesn't support ":\\" in the file path, such as j:\\BaseTools. Convert ":\\" to ":\"
@@ -31,14 +39,14 @@ SYS_BIN_PATH=$(EDK_TOOLS_PATH)\Bin
SYS_LIB_PATH=$(EDK_TOOLS_PATH)\Lib
!IF "$(HOST_ARCH)"=="IA32"
-ARCH_INCLUDE = $(SOURCE_PATH)\Include\Ia32
+ARCH_INCLUDE = $(EDK2_PATH)\MdePkg\Include\Ia32
BIN_PATH = $(BASE_TOOLS_PATH)\Bin\Win32
LIB_PATH = $(BASE_TOOLS_PATH)\Lib\Win32
SYS_BIN_PATH = $(EDK_TOOLS_PATH)\Bin\Win32
SYS_LIB_PATH = $(EDK_TOOLS_PATH)\Lib\Win32
!ELSEIF "$(HOST_ARCH)"=="X64"
-ARCH_INCLUDE = $(SOURCE_PATH)\Include\X64
+ARCH_INCLUDE = $(EDK2_PATH)\MdePkg\Include\X64
BIN_PATH = $(BASE_TOOLS_PATH)\Bin\Win64
LIB_PATH = $(BASE_TOOLS_PATH)\Lib\Win64
SYS_BIN_PATH = $(EDK_TOOLS_PATH)\Bin\Win64
@@ -56,6 +64,7 @@ LD = link.exe
LINKER = $(LD)
INC = $(INC) -I . -I $(SOURCE_PATH)\Include -I $(ARCH_INCLUDE) -I $(SOURCE_PATH)\Common
+INC = $(INC) -I $(EDK2_PATH)\MdePkg\Include
CFLAGS = $(CFLAGS) /nologo /Z7 /c /O2 /MT /W4 /WX /D _CRT_SECURE_NO_DEPRECATE /D _CRT_NONSTDC_NO_DEPRECATE
CPPFLAGS = $(CPPFLAGS) /EHsc /nologo /Z7 /c /O2 /MT /D _CRT_SECURE_NO_DEPRECATE /D _CRT_NONSTDC_NO_DEPRECATE
diff --git a/BaseTools/Source/Python/Makefile b/BaseTools/Source/Python/Makefile
index a76766e0..7b4f62d2 100644
--- a/BaseTools/Source/Python/Makefile
+++ b/BaseTools/Source/Python/Makefile
@@ -8,6 +8,6 @@
all:
clean:
-cleanall:
+cleanall:
@del /f /q $(BASE_TOOLS_PATH)\Source\Python\*.pyc
diff --git a/BaseTools/Source/Python/Trim/Trim.py b/BaseTools/Source/Python/Trim/Trim.py
index 548f53a2..5998ea2c 100644
--- a/BaseTools/Source/Python/Trim/Trim.py
+++ b/BaseTools/Source/Python/Trim/Trim.py
@@ -281,10 +281,10 @@ def DoInclude(Source, Indent='', IncludePathList=[], LocalSearchPath=None, Inclu
F = File.readlines()
break
else:
- EdkLogger.warn("Trim", "Failed to find include file %s" % Source)
+ EdkLogger.error("Trim", "Failed to find include file %s" % Source)
return []
except:
- EdkLogger.warn("Trim", FILE_OPEN_FAILURE, ExtraData=Source)
+ EdkLogger.error("Trim", FILE_OPEN_FAILURE, ExtraData=Source)
return []
diff --git a/BaseTools/Source/Python/Workspace/DscBuildData.py b/BaseTools/Source/Python/Workspace/DscBuildData.py
index 4133bdff..84832c80 100644
--- a/BaseTools/Source/Python/Workspace/DscBuildData.py
+++ b/BaseTools/Source/Python/Workspace/DscBuildData.py
@@ -89,7 +89,7 @@ PcdMakefileHeader = '''
'''
WindowsCFLAGS = 'CFLAGS = $(CFLAGS) /wd4200 /wd4034 /wd4101 '
-LinuxCFLAGS = 'BUILD_CFLAGS += -Wno-pointer-to-int-cast -Wno-unused-variable '
+LinuxCFLAGS = 'CFLAGS += -Wno-pointer-to-int-cast -Wno-unused-variable '
PcdMakefileEnd = '''
!INCLUDE $(BASE_TOOLS_PATH)\Source\C\Makefiles\ms.common
!INCLUDE $(BASE_TOOLS_PATH)\Source\C\Makefiles\ms.app
diff --git a/BaseTools/Source/Python/build/BuildReport.py b/BaseTools/Source/Python/build/BuildReport.py
index 45edeabd..b5501245 100644
--- a/BaseTools/Source/Python/build/BuildReport.py
+++ b/BaseTools/Source/Python/build/BuildReport.py
@@ -10,6 +10,8 @@
## Import Modules
#
+import json
+from pathlib import Path
import Common.LongFilePathOs as os
import re
import platform
@@ -41,6 +43,7 @@ from Common.DataType import *
import collections
from Common.Expression import *
from GenFds.AprioriSection import DXE_APRIORI_GUID, PEI_APRIORI_GUID
+from AutoGen.IncludesAutoGen import IncludesAutoGen
## Pattern to extract contents in EDK DXS files
gDxsDependencyPattern = re.compile(r"DEPENDENCY_START(.+)DEPENDENCY_END", re.DOTALL)
@@ -2298,6 +2301,10 @@ class BuildReport(object):
def GenerateReport(self, BuildDuration, AutoGenTime, MakeTime, GenFdsTime):
if self.ReportFile:
try:
+
+ if "COMPILE_INFO" in self.ReportType:
+ self.GenerateCompileInfo()
+
File = []
for (Wa, MaList) in self.ReportList:
PlatformReport(Wa, MaList, self.ReportType).GenerateReport(File, BuildDuration, AutoGenTime, MakeTime, GenFdsTime, self.ReportType)
@@ -2310,7 +2317,141 @@ class BuildReport(object):
EdkLogger.error("BuildReport", CODE_ERROR, "Unknown fatal error when generating build report", ExtraData=self.ReportFile, RaiseError=False)
EdkLogger.quiet("(Python %s on %s\n%s)" % (platform.python_version(), sys.platform, traceback.format_exc()))
+
+ ##
+ # Generates compile data files to be used by external tools.
+ # Compile information will be generated in ///CompileInfo
+ # Files generated: compile_commands.json, cscope.files, modules_report.json
+ #
+ # @param self The object pointer
+ #
+ def GenerateCompileInfo(self):
+ try:
+ # Lists for the output elements
+ compile_commands = []
+ used_files = set()
+ module_report = []
+
+ for (Wa, MaList) in self.ReportList:
+ # Obtain list of all processed Workspace files
+ for file_path in Wa._GetMetaFiles(Wa.BuildTarget, Wa.ToolChain):
+ used_files.add(file_path)
+
+ for autoGen in Wa.AutoGenObjectList:
+
+ # Loop through all modules
+ for module in (autoGen.LibraryAutoGenList + autoGen.ModuleAutoGenList):
+
+ used_files.add(module.MetaFile.Path)
+
+ # Main elements of module report
+ module_report_data = {}
+ module_report_data["Name"] = module.Name
+ module_report_data["Arch"] = module.Arch
+ module_report_data["Path"] = module.MetaFile.Path
+ module_report_data["Guid"] = module.Guid
+ module_report_data["BuildType"] = module.BuildType
+ module_report_data["IsLibrary"] = module.IsLibrary
+ module_report_data["SourceDir"] = module.SourceDir
+ module_report_data["Files"] = []
+ module_report_data["LibraryClass"] = module.Module.LibraryClass
+ module_report_data["ModuleEntryPointList"] = module.Module.ModuleEntryPointList
+ module_report_data["ConstructorList"] = module.Module.ConstructorList
+ module_report_data["DestructorList"] = module.Module.DestructorList
+
+ # Files used by module
+ for data_file in module.SourceFileList:
+ module_report_data["Files"].append({"Name": data_file.Name, "Path": data_file.Path})
+
+ # Libraries used by module
+ module_report_data["Libraries"] = []
+ for data_library in module.LibraryAutoGenList:
+ module_report_data["Libraries"].append({"Path": data_library.MetaFile.Path})
+
+ # Packages used by module
+ module_report_data["Packages"] = []
+ for data_package in module.PackageList:
+ module_report_data["Packages"].append({"Path": data_package.MetaFile.Path, "Includes": []})
+ # Includes path used in package
+ for data_package_include in data_package.Includes:
+ module_report_data["Packages"][-1]["Includes"].append(data_package_include.Path)
+
+ # PPI's in module
+ module_report_data["PPI"] = []
+ for data_ppi in module.PpiList.keys():
+ module_report_data["PPI"].append({"Name": data_ppi, "Guid": module.PpiList[data_ppi]})
+
+ # Protocol's in module
+ module_report_data["Protocol"] = []
+ for data_protocol in module.ProtocolList.keys():
+ module_report_data["Protocol"].append({"Name": data_protocol, "Guid": module.ProtocolList[data_protocol]})
+
+ # PCD's in module
+ module_report_data["Pcd"] = []
+ for data_pcd in module.LibraryPcdList:
+ module_report_data["Pcd"].append({"Space": data_pcd.TokenSpaceGuidCName,
+ "Name": data_pcd.TokenCName,
+ "Value": data_pcd.TokenValue,
+ "Guid": data_pcd.TokenSpaceGuidValue,
+ "DatumType": data_pcd.DatumType,
+ "Type": data_pcd.Type,
+ "DefaultValue": data_pcd.DefaultValue})
+ # Add module to report
+ module_report.append(module_report_data)
+
+ # Include file dependencies to used files
+ includes_autogen = IncludesAutoGen(module.MakeFileDir, module)
+ for dep in includes_autogen.DepsCollection:
+ used_files.add(dep)
+
+ inc_flag = "-I" # Default include flag
+ if module.BuildRuleFamily == TAB_COMPILER_MSFT:
+ inc_flag = "/I"
+
+ for source in module.SourceFileList:
+ used_files.add(source.Path)
+ compile_command = {}
+ if source.Ext in [".c", ".cc", ".cpp"]:
+ #
+ # Generate compile command for each c file
+ #
+ compile_command["file"] = source.Path
+ compile_command["directory"] = source.Dir
+ build_command = module.BuildRules[source.Ext].CommandList[0]
+ build_command_variables = re.findall(r"\$\((.*?)\)", build_command)
+ for var in build_command_variables:
+ var_tokens = var.split("_")
+ var_main = var_tokens[0]
+ if len(var_tokens) == 1:
+ var_value = module.BuildOption[var_main]["PATH"]
+ else:
+ var_value = module.BuildOption[var_main][var_tokens[1]]
+ build_command = build_command.replace(f"$({var})", var_value)
+ include_files = f" {inc_flag}".join(module.IncludePathList)
+ build_command = build_command.replace("${src}", include_files)
+ build_command = build_command.replace("${dst}", module.OutputDir)
+
+ # Remove un defined macros
+ compile_command["command"] = re.sub(r"\$\(.*?\)", "", build_command)
+ compile_commands.append(compile_command)
+
+ # Create output folder if doesn't exist
+ compile_info_folder = Path(Wa.BuildDir).joinpath("CompileInfo")
+ compile_info_folder.mkdir(exist_ok=True)
+
+ # Sort and save files
+ compile_commands.sort(key=lambda x: x["file"])
+ SaveFileOnChange(compile_info_folder.joinpath(f"compile_commands.json"),json.dumps(compile_commands, indent=2), False)
+
+ SaveFileOnChange(compile_info_folder.joinpath(f"cscope.files"), "\n".join(sorted(used_files)), False)
+
+ module_report.sort(key=lambda x: x["Path"])
+ SaveFileOnChange(compile_info_folder.joinpath(f"module_report.json"), json.dumps(module_report, indent=2), False)
+
+ except:
+ EdkLogger.error("BuildReport", CODE_ERROR, "Unknown fatal error when generating build report compile information", ExtraData=self.ReportFile, RaiseError=False)
+ EdkLogger.quiet("(Python %s on %s\n%s)" % (platform.python_version(), sys.platform, traceback.format_exc()))
+
# This acts like the main() function for the script, unless it is 'import'ed into another script.
if __name__ == '__main__':
pass
-
diff --git a/BaseTools/Source/Python/build/build.py b/BaseTools/Source/Python/build/build.py
index de7965e0..b0c02718 100755
--- a/BaseTools/Source/Python/build/build.py
+++ b/BaseTools/Source/Python/build/build.py
@@ -205,7 +205,7 @@ class MakeSubProc(Popen):
#
# This method will call subprocess.Popen to execute an external program with
# given options in specified directory. Because of the dead-lock issue during
-# redirecting output of the external program, threads are used to to do the
+# redirecting output of the external program, threads are used to do the
# redirection work.
#
# @param Command A list or string containing the call of the program
diff --git a/BaseTools/Source/Python/build/buildoptions.py b/BaseTools/Source/Python/build/buildoptions.py
index 2c98cd37..b4ce18e3 100644
--- a/BaseTools/Source/Python/build/buildoptions.py
+++ b/BaseTools/Source/Python/build/buildoptions.py
@@ -84,8 +84,8 @@ class MyOptionParser():
Parser.add_option("-D", "--define", action="append", type="string", dest="Macros", help="Macro: \"Name [= Value]\".")
Parser.add_option("-y", "--report-file", action="store", dest="ReportFile", help="Create/overwrite the report to the specified filename.")
- Parser.add_option("-Y", "--report-type", action="append", type="choice", choices=['PCD', 'LIBRARY', 'FLASH', 'DEPEX', 'BUILD_FLAGS', 'FIXED_ADDRESS', 'HASH', 'EXECUTION_ORDER'], dest="ReportType", default=[],
- help="Flags that control the type of build report to generate. Must be one of: [PCD, LIBRARY, FLASH, DEPEX, BUILD_FLAGS, FIXED_ADDRESS, HASH, EXECUTION_ORDER]. "\
+ Parser.add_option("-Y", "--report-type", action="append", type="choice", choices=['PCD', 'LIBRARY', 'FLASH', 'DEPEX', 'BUILD_FLAGS', 'FIXED_ADDRESS', 'HASH', 'EXECUTION_ORDER', 'COMPILE_INFO'], dest="ReportType", default=[],
+ help="Flags that control the type of build report to generate. Must be one of: [PCD, LIBRARY, FLASH, DEPEX, BUILD_FLAGS, FIXED_ADDRESS, HASH, EXECUTION_ORDER, COMPILE_INFO]. "\
"To specify more than one flag, repeat this option on the command line and the default flag set is [PCD, LIBRARY, FLASH, DEPEX, HASH, BUILD_FLAGS, FIXED_ADDRESS]")
Parser.add_option("-F", "--flag", action="store", type="string", dest="Flag",
help="Specify the specific option to parse EDK UNI file. Must be one of: [-c, -s]. -c is for EDK framework UNI file, and -s is for EDK UEFI UNI file. "\
diff --git a/BaseTools/get_vsvars.bat b/BaseTools/get_vsvars.bat
index 4f7b78ed..dd9062af 100644
--- a/BaseTools/get_vsvars.bat
+++ b/BaseTools/get_vsvars.bat
@@ -13,8 +13,6 @@ if "%1"=="" goto main
if /I "%1"=="VS2019" goto VS2019Vars
if /I "%1"=="VS2017" goto VS2017Vars
if /I "%1"=="VS2015" goto VS2015Vars
-if /I "%1"=="VS2013" goto VS2013Vars
-if /I "%1"=="VS2012" goto VS2012Vars
:set_vsvars
if defined VCINSTALLDIR goto :EOF
@@ -85,16 +83,5 @@ if defined VCINSTALLDIR goto :done
:VS2015Vars
if defined VS140COMNTOOLS (call :read_vsvars "%VS140COMNTOOLS%") else (if /I "%1"=="VS2015" goto ToolNotInstall)
- :VS2013Vars
- if defined VS120COMNTOOLS ( call :read_vsvars "%VS120COMNTOOLS%") else (if /I "%1"=="VS2013" goto ToolNotInstall)
-
- :VS2012Vars
- if defined VS110COMNTOOLS (call :read_vsvars "%VS110COMNTOOLS%") else (if /I "%1"=="VS2012" goto ToolNotInstall)
-
- if defined VS100COMNTOOLS call :read_vsvars "%VS100COMNTOOLS%"
- if defined VS90COMNTOOLS call :read_vsvars "%VS90COMNTOOLS%"
- if defined VS80COMNTOOLS call :read_vsvars "%VS80COMNTOOLS%"
- if defined VS71COMNTOOLS call :read_vsvars "%VS71COMNTOOLS%"
-
:done
set GET_VSVARS_BAT_CHECK_DIR=
diff --git a/BaseTools/set_vsprefix_envs.bat b/BaseTools/set_vsprefix_envs.bat
index 7f576408..045a4f59 100644
--- a/BaseTools/set_vsprefix_envs.bat
+++ b/BaseTools/set_vsprefix_envs.bat
@@ -21,8 +21,6 @@ goto :EOF
if /I "%1"=="VS2019" goto SetVS2019
if /I "%1"=="VS2017" goto SetVS2017
if /I "%1"=="VS2015" goto SetVS2015
-if /I "%1"=="VS2013" goto SetVS2013
-if /I "%1"=="VS2012" goto SetVS2012
if defined VS71COMNTOOLS (
if not defined VS2003_PREFIX (
@@ -30,68 +28,6 @@ if defined VS71COMNTOOLS (
)
)
-if defined VS80COMNTOOLS (
- if not defined VS2005_PREFIX (
- set "VS2005_PREFIX=%VS80COMNTOOLS:~0,-14%"
- )
-)
-
-if defined VS90COMNTOOLS (
- if not defined VS2008_PREFIX (
- set "VS2008_PREFIX=%VS90COMNTOOLS:~0,-14%"
- )
- if not defined WINSDK_PREFIX (
- set "WINSDK_PREFIX=c:\Program Files\Microsoft SDKs\Windows\v6.0A\bin\"
- )
- if not defined WINSDKx86_PREFIX (
- set "WINSDKx86_PREFIX=c:\Program Files (x86)\Microsoft SDKs\Windows\v6.0A\bin\"
- )
-)
-
-if defined VS100COMNTOOLS (
- if not defined VS2010_PREFIX (
- set "VS2010_PREFIX=%VS100COMNTOOLS:~0,-14%"
- )
- if not defined WINSDK7_PREFIX (
- set "WINSDK7_PREFIX=c:\Program Files\Microsoft SDKs\Windows\v7.0A\Bin\"
- )
- if not defined WINSDK7x86_PREFIX (
- set "WINSDK7x86_PREFIX=c:\Program Files (x86)\Microsoft SDKs\Windows\v7.0A\Bin\"
- )
-)
-
-:SetVS2012
-if defined VS110COMNTOOLS (
- if not defined VS2012_PREFIX (
- set "VS2012_PREFIX=%VS110COMNTOOLS:~0,-14%"
- )
- if not defined WINSDK71_PREFIX (
- set "WINSDK71_PREFIX=c:\Program Files\Microsoft SDKs\Windows\v7.1A\Bin\"
- )
- if not defined WINSDK71x86_PREFIX (
- set "WINSDK71x86_PREFIX=c:\Program Files (x86)\Microsoft SDKs\Windows\v7.1A\Bin\"
- )
-) else (
- if /I "%1"=="VS2012" goto ToolNotInstall
-)
-if /I "%1"=="VS2012" goto SetWinDDK
-
-:SetVS2013
-if defined VS120COMNTOOLS (
- if not defined VS2013_PREFIX (
- set "VS2013_PREFIX=%VS120COMNTOOLS:~0,-14%"
- )
- if not defined WINSDK8_PREFIX (
- set "WINSDK8_PREFIX=c:\Program Files\Windows Kits\8.0\bin\"
- )
- if not defined WINSDK8x86_PREFIX (
- set "WINSDK8x86_PREFIX=c:\Program Files (x86)\Windows Kits\8.0\bin\"
- )
-) else (
- if /I "%1"=="VS2013" goto ToolNotInstall
-)
-if /I "%1"=="VS2013" goto SetWinDDK
-
:SetVS2015
if defined VS140COMNTOOLS (
if not defined VS2015_PREFIX (
diff --git a/BaseTools/toolsetup.bat b/BaseTools/toolsetup.bat
index 617cc4aa..4082b77d 100644
--- a/BaseTools/toolsetup.bat
+++ b/BaseTools/toolsetup.bat
@@ -12,6 +12,8 @@
@echo off
pushd .
set SCRIPT_ERROR=0
+set PYTHON_VER_MAJOR=3
+set PYTHON_VER_MINOR=6
@REM ##############################################################
@REM # You should not have to modify anything below this line
@@ -60,18 +62,6 @@ if /I "%1"=="/?" goto Usage
set VSTool=VS2015
goto loop
)
- if /I "%1"=="VS2013" (
- shift
- set VS2013=TRUE
- set VSTool=VS2013
- goto loop
- )
- if /I "%1"=="VS2012" (
- shift
- set VS2012=TRUE
- set VSTool=VS2012
- goto loop
- )
if "%1"=="" goto setup_workspace
if exist %1 (
if not defined BASE_TOOLS_PATH (
@@ -189,12 +179,6 @@ if defined VS2019 (
) else if defined VS2015 (
call %EDK_TOOLS_PATH%\set_vsprefix_envs.bat VS2015
call %EDK_TOOLS_PATH%\get_vsvars.bat VS2015
-) else if defined VS2013 (
- call %EDK_TOOLS_PATH%\set_vsprefix_envs.bat VS2013
- call %EDK_TOOLS_PATH%\get_vsvars.bat VS2013
-) else if defined VS2012 (
- call %EDK_TOOLS_PATH%\set_vsprefix_envs.bat VS2012
- call %EDK_TOOLS_PATH%\get_vsvars.bat VS2012
) else (
call %EDK_TOOLS_PATH%\set_vsprefix_envs.bat
call %EDK_TOOLS_PATH%\get_vsvars.bat
@@ -266,24 +250,6 @@ if NOT exist %CONF_PATH%\build_rule.txt (
if defined RECONFIG copy /Y %EDK_TOOLS_PATH%\Conf\build_rule.template %CONF_PATH%\build_rule.txt > nul
)
-echo PATH = %PATH%
-echo.
-if defined WORKSPACE (
- echo WORKSPACE = %WORKSPACE%
-)
-if defined PACKAGES_PATH (
- echo PACKAGES_PATH = %PACKAGES_PATH%
-)
-echo EDK_TOOLS_PATH = %EDK_TOOLS_PATH%
-if defined BASE_TOOLS_PATH (
- echo BASE_TOOLS_PATH = %BASE_TOOLS_PATH%
-)
-if defined EDK_TOOLS_BIN (
- echo EDK_TOOLS_BIN = %EDK_TOOLS_BIN%
-)
-echo CONF_PATH = %CONF_PATH%
-echo.
-
:skip_reconfig
@REM
@@ -322,113 +288,100 @@ goto check_build_environment
)
)
-:defined_python
-if defined PYTHON_COMMAND if not defined PYTHON3_ENABLE (
- goto check_python_available
-)
-if defined PYTHON3_ENABLE (
- if "%PYTHON3_ENABLE%" EQU "TRUE" (
- set PYTHON_COMMAND=py -3
- goto check_python_available
- ) else (
- goto check_python2
- )
-)
-if not defined PYTHON_COMMAND if not defined PYTHON3_ENABLE (
+@REM Check Python environment
+
+if not defined PYTHON_COMMAND (
set PYTHON_COMMAND=py -3
- py -3 %BASE_TOOLS_PATH%\Tests\PythonTest.py >PythonCheck.txt 2>&1
- setlocal enabledelayedexpansion
- set /p PythonCheck=<"PythonCheck.txt"
- del PythonCheck.txt
- if "!PythonCheck!" NEQ "TRUE" (
+ py -3 %BASE_TOOLS_PATH%\Tests\PythonTest.py %PYTHON_VER_MAJOR% %PYTHON_VER_MINOR% >NUL 2>NUL
+ if %ERRORLEVEL% EQU 1 (
+ echo.
+ echo !!! ERROR !!! Python %PYTHON_VER_MAJOR%.%PYTHON_VER_MINOR% or newer is required.
+ echo.
+ goto end
+ )
+ if %ERRORLEVEL% NEQ 0 (
if not defined PYTHON_HOME if not defined PYTHONHOME (
- endlocal
set PYTHON_COMMAND=
echo.
echo !!! ERROR !!! Binary python tools are missing.
- echo PYTHON_COMMAND, PYTHON3_ENABLE or PYTHON_HOME
- echo Environment variable is not set successfully.
- echo They is required to build or execute the python tools.
+ echo PYTHON_COMMAND or PYTHON_HOME
+ echo Environment variable is not set correctly.
+ echo They are required to build or execute the python tools.
echo.
goto end
- ) else (
- goto check_python2
)
- ) else (
- goto check_freezer_path
)
)
-:check_python2
+if not defined PYTHON_COMMAND (
+ if defined PYTHON_HOME (
+ if EXIST "%PYTHON_HOME%" (
+ set PYTHON_COMMAND=%PYTHON_HOME%\python.exe
+ ) else (
+ echo .
+ echo !!! ERROR !!! PYTHON_HOME="%PYTHON_HOME%" does not exist.
+ echo .
+ goto end
+ )
+ )
+)
+
+%PYTHON_COMMAND% %BASE_TOOLS_PATH%\Tests\PythonTest.py %PYTHON_VER_MAJOR% %PYTHON_VER_MINOR% >NUL 2>NUL
+if %ERRORLEVEL% EQU 1 (
+ echo.
+ echo !!! ERROR !!! Python %PYTHON_VER_MAJOR%.%PYTHON_VER_MINOR% or newer is required.
+ echo.
+ goto end
+)
+if %ERRORLEVEL% NEQ 0 (
+ echo.
+ echo !!! ERROR !!! PYTHON_COMMAND="%PYTHON_COMMAND%" does not exist or is not a Python interpreter.
+ echo.
+ goto end
+)
+
endlocal
-if defined PYTHON_HOME (
- if EXIST "%PYTHON_HOME%" (
- set PYTHON_COMMAND=%PYTHON_HOME%\python.exe
- goto check_python_available
- )
+
+%PYTHON_COMMAND% -c "import edk2basetools" >NUL 2>NUL
+if %ERRORLEVEL% EQU 0 (
+ goto use_pip_basetools
+) else (
+ REM reset ERRORLEVEL
+ type nul>nul
+ goto use_builtin_basetools
)
-if defined PYTHONHOME (
- if EXIST "%PYTHONHOME%" (
- set PYTHON_HOME=%PYTHONHOME%
- set PYTHON_COMMAND=%PYTHON_HOME%\python.exe
- goto check_python_available
- )
-)
-echo.
-echo !!! ERROR !!! PYTHON_HOME is not defined or The value of this variable does not exist
-echo.
-goto end
-:check_python_available
-%PYTHON_COMMAND% %BASE_TOOLS_PATH%\Tests\PythonTest.py >PythonCheck.txt 2>&1
- setlocal enabledelayedexpansion
- set /p PythonCheck=<"PythonCheck.txt"
- del PythonCheck.txt
- if "!PythonCheck!" NEQ "TRUE" (
- echo.
- echo ! ERROR ! "%PYTHON_COMMAND%" is not installed or added to environment variables
- echo.
- goto end
- ) else (
- goto check_freezer_path
- )
-
-
-
-:check_freezer_path
- endlocal
-
- %PYTHON_COMMAND% -c "import edk2basetools" >NUL 2>NUL
- if %ERRORLEVEL% EQU 0 (
- goto use_pip_basetools
- ) else (
- REM reset ERRORLEVEL
- type nul>nul
- goto use_builtin_basetools
- )
:use_builtin_basetools
@echo Using EDK2 in-source Basetools
if defined BASETOOLS_PYTHON_SOURCE goto print_python_info
set "PATH=%BASE_TOOLS_PATH%\BinWrappers\WindowsLike;%PATH%"
- set BASETOOLS_PYTHON_SOURCE=%BASE_TOOLS_PATH%\Source\Python
- set PYTHONPATH=%BASETOOLS_PYTHON_SOURCE%;%PYTHONPATH%
+ set PYTHONPATH=%BASE_TOOLS_PATH%\Source\Python;%PYTHONPATH%
goto print_python_info
:use_pip_basetools
@echo Using Pip Basetools
set "PATH=%BASE_TOOLS_PATH%\BinPipWrappers\WindowsLike;%PATH%"
- set BASETOOLS_PYTHON_SOURCE=edk2basetools
+ set PYTHONPATH=%BASE_TOOLS_PATH%\Source\Python;%PYTHONPATH%
goto print_python_info
:print_python_info
- echo PATH = %PATH%
- if defined PYTHON3_ENABLE if "%PYTHON3_ENABLE%" EQU "TRUE" (
- echo PYTHON3_ENABLE = %PYTHON3_ENABLE%
- echo PYTHON3 = %PYTHON_COMMAND%
- ) else (
- echo PYTHON3_ENABLE = FALSE
- echo PYTHON_COMMAND = %PYTHON_COMMAND%
+ echo PATH = %PATH%
+ echo.
+ if defined WORKSPACE (
+ echo WORKSPACE = %WORKSPACE%
)
+ if defined PACKAGES_PATH (
+ echo PACKAGES_PATH = %PACKAGES_PATH%
+ )
+ echo EDK_TOOLS_PATH = %EDK_TOOLS_PATH%
+ if defined BASE_TOOLS_PATH (
+ echo BASE_TOOLS_PATH = %BASE_TOOLS_PATH%
+ )
+ if defined EDK_TOOLS_BIN (
+ echo EDK_TOOLS_BIN = %EDK_TOOLS_BIN%
+ )
+ echo CONF_PATH = %CONF_PATH%
+ echo PYTHON_COMMAND = %PYTHON_COMMAND%
echo PYTHONPATH = %PYTHONPATH%
echo.
@@ -472,7 +425,7 @@ goto end
:Usage
@echo.
- echo Usage: "%0 [-h | -help | --help | /h | /help | /?] [ Rebuild | ForceRebuild ] [Reconfig] [base_tools_path [edk_tools_path]] [VS2019] [VS2017] [VS2015] [VS2013] [VS2012]"
+ echo Usage: "%0 [-h | -help | --help | /h | /help | /?] [ Rebuild | ForceRebuild ] [Reconfig] [base_tools_path [edk_tools_path]] [VS2019] [VS2017] [VS2015]"
@echo.
@echo base_tools_path BaseTools project path, BASE_TOOLS_PATH will be set to this path.
@echo edk_tools_path EDK_TOOLS_PATH will be set to this path.
@@ -481,8 +434,6 @@ goto end
@echo ForceRebuild If sources are available, rebuild all tools regardless of
@echo whether they have been updated or not.
@echo Reconfig Reinstall target.txt, tools_def.txt and build_rule.txt.
- @echo VS2012 Set the env for VS2012 build.
- @echo VS2013 Set the env for VS2013 build.
@echo VS2015 Set the env for VS2015 build.
@echo VS2017 Set the env for VS2017 build.
@echo VS2019 Set the env for VS2019 build.
@@ -495,8 +446,7 @@ set RECONFIG=
set VS2019=
set VS2017=
set VS2015=
-set VS2013=
-set VS2012=
set VSTool=
+set PYTHON_VER_MAJOR=
+set PYTHON_VER_MINOR=
popd
-
diff --git a/BootloaderCommonPkg/Include/Register/Intel/LocalApic.h b/BootloaderCommonPkg/Include/Register/Intel/LocalApic.h
deleted file mode 100644
index a2f1aab0..00000000
--- a/BootloaderCommonPkg/Include/Register/Intel/LocalApic.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/** @file
- IA32 Local APIC Definitions.
-
- Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __INTEL_LOCAL_APIC_H__
-#define __INTEL_LOCAL_APIC_H__
-
-//
-// Definition for Local APIC registers and related values
-//
-#define XAPIC_ID_OFFSET 0x20
-#define XAPIC_VERSION_OFFSET 0x30
-#define XAPIC_EOI_OFFSET 0x0b0
-#define XAPIC_ICR_DFR_OFFSET 0x0e0
-#define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0
-#define XAPIC_ICR_LOW_OFFSET 0x300
-#define XAPIC_ICR_HIGH_OFFSET 0x310
-#define XAPIC_LVT_TIMER_OFFSET 0x320
-#define XAPIC_LVT_LINT0_OFFSET 0x350
-#define XAPIC_LVT_LINT1_OFFSET 0x360
-#define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380
-#define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390
-#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0
-
-#define X2APIC_MSR_BASE_ADDRESS 0x800
-#define X2APIC_MSR_ICR_ADDRESS 0x830
-
-#define LOCAL_APIC_DELIVERY_MODE_FIXED 0
-#define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1
-#define LOCAL_APIC_DELIVERY_MODE_SMI 2
-#define LOCAL_APIC_DELIVERY_MODE_NMI 4
-#define LOCAL_APIC_DELIVERY_MODE_INIT 5
-#define LOCAL_APIC_DELIVERY_MODE_STARTUP 6
-#define LOCAL_APIC_DELIVERY_MODE_EXTINT 7
-
-#define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0
-#define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1
-#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2
-#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3
-
-//
-// Local APIC Version Register.
-//
-typedef union {
- struct {
- UINT32 Version: 8; ///< The version numbers of the local APIC.
- UINT32 Reserved0: 8; ///< Reserved.
- UINT32 MaxLvtEntry: 8; ///< Number of LVT entries minus 1.
- UINT32 EoiBroadcastSuppression: 1; ///< 1 if EOI-broadcast suppression supported.
- UINT32 Reserved1: 7; ///< Reserved.
- } Bits;
- UINT32 Uint32;
-} LOCAL_APIC_VERSION;
-
-//
-// Low half of Interrupt Command Register (ICR).
-//
-typedef union {
- struct {
- UINT32 Vector: 8; ///< The vector number of the interrupt being sent.
- UINT32 DeliveryMode: 3; ///< Specifies the type of IPI to be sent.
- UINT32 DestinationMode: 1; ///< 0: physical destination mode, 1: logical destination mode.
- UINT32 DeliveryStatus: 1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.
- UINT32 Reserved0: 1; ///< Reserved.
- UINT32 Level: 1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.
- UINT32 TriggerMode: 1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.
- UINT32 Reserved1: 2; ///< Reserved.
- UINT32 DestinationShorthand: 2; ///< A shorthand notation to specify the destination of the interrupt.
- UINT32 Reserved2: 12; ///< Reserved.
- } Bits;
- UINT32 Uint32;
-} LOCAL_APIC_ICR_LOW;
-
-//
-// High half of Interrupt Command Register (ICR)
-//
-typedef union {
- struct {
- UINT32 Reserved0: 24; ///< Reserved.
- UINT32 Destination: 8; ///< Specifies the target processor or processors in xAPIC mode.
- } Bits;
- UINT32 Uint32; ///< Destination field expanded to 32-bit in x2APIC mode.
-} LOCAL_APIC_ICR_HIGH;
-
-//
-// Spurious-Interrupt Vector Register (SVR)
-//
-typedef union {
- struct {
- UINT32 SpuriousVector: 8; ///< Spurious Vector.
- UINT32 SoftwareEnable: 1; ///< APIC Software Enable/Disable.
- UINT32 FocusProcessorChecking: 1; ///< Focus Processor Checking.
- UINT32 Reserved0: 2; ///< Reserved.
- UINT32 EoiBroadcastSuppression: 1; ///< EOI-Broadcast Suppression.
- UINT32 Reserved1: 19; ///< Reserved.
- } Bits;
- UINT32 Uint32;
-} LOCAL_APIC_SVR;
-
-//
-// Divide Configuration Register (DCR)
-//
-typedef union {
- struct {
- UINT32 DivideValue1: 2; ///< Low 2 bits of the divide value.
- UINT32 Reserved0: 1; ///< Always 0.
- UINT32 DivideValue2: 1; ///< Highest 1 bit of the divide value.
- UINT32 Reserved1: 28; ///< Reserved.
- } Bits;
- UINT32 Uint32;
-} LOCAL_APIC_DCR;
-
-//
-// LVT Timer Register
-//
-typedef union {
- struct {
- UINT32 Vector: 8; ///< The vector number of the interrupt being sent.
- UINT32 Reserved0: 4; ///< Reserved.
- UINT32 DeliveryStatus: 1; ///< 0: Idle, 1: send pending.
- UINT32 Reserved1: 3; ///< Reserved.
- UINT32 Mask: 1; ///< 0: Not masked, 1: Masked.
- UINT32 TimerMode: 1; ///< 0: One-shot, 1: Periodic.
- UINT32 Reserved2: 14; ///< Reserved.
- } Bits;
- UINT32 Uint32;
-} LOCAL_APIC_LVT_TIMER;
-
-//
-// LVT LINT0/LINT1 Register
-//
-typedef union {
- struct {
- UINT32 Vector: 8; ///< The vector number of the interrupt being sent.
- UINT32 DeliveryMode: 3; ///< Specifies the type of interrupt to be sent.
- UINT32 Reserved0: 1; ///< Reserved.
- UINT32 DeliveryStatus: 1; ///< 0: Idle, 1: send pending.
- UINT32 InputPinPolarity: 1; ///< Interrupt Input Pin Polarity.
- UINT32 RemoteIrr: 1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.
- UINT32 TriggerMode: 1; ///< 0:edge, 1:level.
- UINT32 Mask: 1; ///< 0: Not masked, 1: Masked.
- UINT32 Reserved1: 15; ///< Reserved.
- } Bits;
- UINT32 Uint32;
-} LOCAL_APIC_LVT_LINT;
-
-//
-// MSI Address Register
-//
-typedef union {
- struct {
- UINT32 Reserved0: 2; ///< Reserved
- UINT32 DestinationMode: 1; ///< Specifies the Destination Mode.
- UINT32 RedirectionHint: 1; ///< Specifies the Redirection Hint.
- UINT32 Reserved1: 8; ///< Reserved.
- UINT32 DestinationId: 8; ///< Specifies the Destination ID.
- UINT32 BaseAddress: 12; ///< Must be 0FEEH
- } Bits;
- UINT32 Uint32;
-} LOCAL_APIC_MSI_ADDRESS;
-
-//
-// MSI Address Register
-//
-typedef union {
- struct {
- UINT32 Vector: 8; ///< Interrupt vector in range 010h..0FEH
- UINT32 DeliveryMode: 3; ///< Specifies the type of interrupt to be sent.
- UINT32 Reserved0: 3; ///< Reserved.
- UINT32 Level: 1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts.
- UINT32 TriggerMode: 1; ///< 0:Edge, 1:Level.
- UINT32 Reserved1: 16; ///< Reserved.
- UINT32 Reserved2: 32; ///< Reserved.
- } Bits;
- UINT64 Uint64;
-} LOCAL_APIC_MSI_DATA;
-
-#endif
-
diff --git a/BootloaderCommonPkg/Library/UfsBlockIoLib/UfsInternal.h b/BootloaderCommonPkg/Library/UfsBlockIoLib/UfsInternal.h
index 38f5b870..f2907779 100644
--- a/BootloaderCommonPkg/Library/UfsBlockIoLib/UfsInternal.h
+++ b/BootloaderCommonPkg/Library/UfsBlockIoLib/UfsInternal.h
@@ -151,8 +151,6 @@ typedef struct _UFS_PEIM_HC_PRIVATE_DATA {
#define ROUNDUP8(x) (((x) % 8 == 0) ? (x) : ((x) / 8 + 1) * 8)
-#define IS_ALIGNED(addr, size) (((UINTN) (addr) & (size - 1)) == 0)
-
#define UFS_SCSI_OP_LENGTH_SIX 0x6
#define UFS_SCSI_OP_LENGTH_TEN 0xa
#define UFS_SCSI_OP_LENGTH_SIXTEEN 0x10
diff --git a/MdePkg/Include/Base.h b/MdePkg/Include/Base.h
index aa1dbdbc..f7c481d1 100644
--- a/MdePkg/Include/Base.h
+++ b/MdePkg/Include/Base.h
@@ -12,7 +12,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
-
#ifndef __BASE_H__
#define __BASE_H__
@@ -21,11 +20,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
#include
-#if defined(_MSC_EXTENSIONS)
+#if defined (_MSC_EXTENSIONS)
//
// Disable warning when last field of data structure is a zero sized array.
//
-#pragma warning ( disable : 4200 )
+ #pragma warning ( disable : 4200 )
#endif
//
@@ -33,20 +32,20 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// if the /OPT:REF linker option is used. We defined a macro as this is a
// a non standard extension
//
-#if defined(_MSC_VER) && _MSC_VER < 1800 && !defined (MDE_CPU_EBC)
- ///
- /// Remove global variable from the linked image if there are no references to
- /// it after all compiler and linker optimizations have been performed.
- ///
- ///
- #define GLOBAL_REMOVE_IF_UNREFERENCED __declspec(selectany)
+#if defined (_MSC_VER) && _MSC_VER < 1800 && !defined (MDE_CPU_EBC)
+///
+/// Remove global variable from the linked image if there are no references to
+/// it after all compiler and linker optimizations have been performed.
+///
+///
+#define GLOBAL_REMOVE_IF_UNREFERENCED __declspec(selectany)
#else
- ///
- /// Remove the global variable from the linked image if there are no references
- /// to it after all compiler and linker optimizations have been performed.
- ///
- ///
- #define GLOBAL_REMOVE_IF_UNREFERENCED
+///
+/// Remove the global variable from the linked image if there are no references
+/// to it after all compiler and linker optimizations have been performed.
+///
+///
+#define GLOBAL_REMOVE_IF_UNREFERENCED
#endif
//
@@ -55,27 +54,27 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
#ifndef UNREACHABLE
#ifdef __GNUC__
- ///
- /// Signal compilers and analyzers that this call is not reachable. It is
- /// up to the compiler to remove any code past that point.
- ///
- #define UNREACHABLE() __builtin_unreachable ()
+///
+/// Signal compilers and analyzers that this call is not reachable. It is
+/// up to the compiler to remove any code past that point.
+///
+#define UNREACHABLE() __builtin_unreachable ()
#elif defined (__has_feature)
#if __has_builtin (__builtin_unreachable)
- ///
- /// Signal compilers and analyzers that this call is not reachable. It is
- /// up to the compiler to remove any code past that point.
- ///
- #define UNREACHABLE() __builtin_unreachable ()
+///
+/// Signal compilers and analyzers that this call is not reachable. It is
+/// up to the compiler to remove any code past that point.
+///
+#define UNREACHABLE() __builtin_unreachable ()
#endif
#endif
#ifndef UNREACHABLE
- ///
- /// Signal compilers and analyzers that this call is not reachable. It is
- /// up to the compiler to remove any code past that point.
- ///
- #define UNREACHABLE()
+///
+/// Signal compilers and analyzers that this call is not reachable. It is
+/// up to the compiler to remove any code past that point.
+///
+#define UNREACHABLE()
#endif
#endif
@@ -86,26 +85,26 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
#ifndef NORETURN
#if defined (__GNUC__) || defined (__clang__)
- ///
- /// Signal compilers and analyzers that the function cannot return.
- /// It is up to the compiler to remove any code past a call to functions
- /// flagged with this attribute.
- ///
- #define NORETURN __attribute__((noreturn))
- #elif defined(_MSC_EXTENSIONS) && !defined(MDE_CPU_EBC)
- ///
- /// Signal compilers and analyzers that the function cannot return.
- /// It is up to the compiler to remove any code past a call to functions
- /// flagged with this attribute.
- ///
- #define NORETURN __declspec(noreturn)
+///
+/// Signal compilers and analyzers that the function cannot return.
+/// It is up to the compiler to remove any code past a call to functions
+/// flagged with this attribute.
+///
+#define NORETURN __attribute__((noreturn))
+ #elif defined (_MSC_EXTENSIONS) && !defined (MDE_CPU_EBC)
+///
+/// Signal compilers and analyzers that the function cannot return.
+/// It is up to the compiler to remove any code past a call to functions
+/// flagged with this attribute.
+///
+#define NORETURN __declspec(noreturn)
#else
- ///
- /// Signal compilers and analyzers that the function cannot return.
- /// It is up to the compiler to remove any code past a call to functions
- /// flagged with this attribute.
- ///
- #define NORETURN
+///
+/// Signal compilers and analyzers that the function cannot return.
+/// It is up to the compiler to remove any code past a call to functions
+/// flagged with this attribute.
+///
+#define NORETURN
#endif
#endif
@@ -116,20 +115,20 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef ANALYZER_UNREACHABLE
#ifdef __clang_analyzer__
#if __has_builtin (__builtin_unreachable)
- ///
- /// Signal the analyzer that this call is not reachable.
- /// This excludes compilers.
- ///
- #define ANALYZER_UNREACHABLE() __builtin_unreachable ()
+///
+/// Signal the analyzer that this call is not reachable.
+/// This excludes compilers.
+///
+#define ANALYZER_UNREACHABLE() __builtin_unreachable ()
#endif
#endif
#ifndef ANALYZER_UNREACHABLE
- ///
- /// Signal the analyzer that this call is not reachable.
- /// This excludes compilers.
- ///
- #define ANALYZER_UNREACHABLE()
+///
+/// Signal the analyzer that this call is not reachable.
+/// This excludes compilers.
+///
+#define ANALYZER_UNREACHABLE()
#endif
#endif
@@ -142,20 +141,20 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef ANALYZER_NORETURN
#ifdef __has_feature
#if __has_feature (attribute_analyzer_noreturn)
- ///
- /// Signal analyzers that the function cannot return.
- /// This excludes compilers.
- ///
- #define ANALYZER_NORETURN __attribute__((analyzer_noreturn))
+///
+/// Signal analyzers that the function cannot return.
+/// This excludes compilers.
+///
+#define ANALYZER_NORETURN __attribute__((analyzer_noreturn))
#endif
#endif
#ifndef ANALYZER_NORETURN
- ///
- /// Signal the analyzer that the function cannot return.
- /// This excludes compilers.
- ///
- #define ANALYZER_NORETURN
+///
+/// Signal the analyzer that the function cannot return.
+/// This excludes compilers.
+///
+#define ANALYZER_NORETURN
#endif
#endif
@@ -165,17 +164,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
///
#ifndef RETURNS_TWICE
#if defined (__GNUC__) || defined (__clang__)
- ///
- /// Tell the code optimizer that the function will return twice.
- /// This prevents wrong optimizations which can cause bugs.
- ///
- #define RETURNS_TWICE __attribute__((returns_twice))
+///
+/// Tell the code optimizer that the function will return twice.
+/// This prevents wrong optimizations which can cause bugs.
+///
+#define RETURNS_TWICE __attribute__((returns_twice))
#else
- ///
- /// Tell the code optimizer that the function will return twice.
- /// This prevents wrong optimizations which can cause bugs.
- ///
- #define RETURNS_TWICE
+///
+/// Tell the code optimizer that the function will return twice.
+/// This prevents wrong optimizations which can cause bugs.
+///
+#define RETURNS_TWICE
#endif
#endif
@@ -186,58 +185,50 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
///
/// Private worker functions for ASM_PFX()
///
-#define _CONCATENATE(a, b) __CONCATENATE(a, b)
-#define __CONCATENATE(a, b) a ## b
+#define _CONCATENATE(a, b) __CONCATENATE(a, b)
+#define __CONCATENATE(a, b) a ## b
///
/// The __USER_LABEL_PREFIX__ macro predefined by GNUC represents the prefix
/// on symbols in assembly language.
///
-#define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name)
+#define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name)
#ifdef __APPLE__
- //
- // Apple extension that is used by the linker to optimize code size
- // with assembly functions. Put at the end of your .S files
- //
- #define ASM_FUNCTION_REMOVE_IF_UNREFERENCED .subsections_via_symbols
+//
+// Apple extension that is used by the linker to optimize code size
+// with assembly functions. Put at the end of your .S files
+//
+#define ASM_FUNCTION_REMOVE_IF_UNREFERENCED .subsections_via_symbols
#else
- #define ASM_FUNCTION_REMOVE_IF_UNREFERENCED
+#define ASM_FUNCTION_REMOVE_IF_UNREFERENCED
#endif
-#ifdef __CC_ARM
- //
- // Older RVCT ARM compilers don't fully support #pragma pack and require __packed
- // as a prefix for the structure.
- //
- #define PACKED __packed
-#else
- #define PACKED
-#endif
+#define PACKED
///
/// 128 bit buffer containing a unique identifier value.
/// Unless otherwise specified, aligned on a 64 bit boundary.
///
typedef struct {
- UINT32 Data1;
- UINT16 Data2;
- UINT16 Data3;
- UINT8 Data4[8];
+ UINT32 Data1;
+ UINT16 Data2;
+ UINT16 Data3;
+ UINT8 Data4[8];
} GUID;
///
/// 4-byte buffer. An IPv4 internet protocol address.
///
typedef struct {
- UINT8 Addr[4];
+ UINT8 Addr[4];
} IPv4_ADDRESS;
///
/// 16-byte buffer. An IPv6 internet protocol address.
///
typedef struct {
- UINT8 Addr[16];
+ UINT8 Addr[16];
} IPv6_ADDRESS;
//
@@ -254,8 +245,8 @@ typedef struct _LIST_ENTRY LIST_ENTRY;
/// _LIST_ENTRY structure definition.
///
struct _LIST_ENTRY {
- LIST_ENTRY *ForwardLink;
- LIST_ENTRY *BackLink;
+ LIST_ENTRY *ForwardLink;
+ LIST_ENTRY *BackLink;
};
//
@@ -265,17 +256,17 @@ struct _LIST_ENTRY {
///
/// Datum is read-only.
///
-#define CONST const
+#define CONST const
///
/// Datum is scoped to the current file or function.
///
-#define STATIC static
+#define STATIC static
///
/// Undeclared type.
///
-#define VOID void
+#define VOID void
//
// Modifiers for Data Types used to self document code.
@@ -313,17 +304,25 @@ struct _LIST_ENTRY {
/// Boolean false value. UEFI Specification defines this value to be 0,
/// but this form is more portable.
///
-#define FALSE ((BOOLEAN)(0==1))
+#define FALSE ((BOOLEAN)(0==1))
///
/// NULL pointer (VOID *)
///
+#if defined (__cplusplus)
+ #if defined (_MSC_EXTENSIONS)
+#define NULL nullptr
+ #else
+#define NULL __null
+ #endif
+#else
#define NULL ((VOID *) 0)
+#endif
//
// Null character
//
-#define CHAR_NULL 0x0000
+#define CHAR_NULL 0x0000
///
/// Maximum values for common UEFI Data Types
@@ -345,70 +344,70 @@ struct _LIST_ENTRY {
#define MIN_INT32 (((INT32) -2147483647) - 1)
#define MIN_INT64 (((INT64) -9223372036854775807LL) - 1)
-#define BIT0 0x00000001
-#define BIT1 0x00000002
-#define BIT2 0x00000004
-#define BIT3 0x00000008
-#define BIT4 0x00000010
-#define BIT5 0x00000020
-#define BIT6 0x00000040
-#define BIT7 0x00000080
-#define BIT8 0x00000100
-#define BIT9 0x00000200
-#define BIT10 0x00000400
-#define BIT11 0x00000800
-#define BIT12 0x00001000
-#define BIT13 0x00002000
-#define BIT14 0x00004000
-#define BIT15 0x00008000
-#define BIT16 0x00010000
-#define BIT17 0x00020000
-#define BIT18 0x00040000
-#define BIT19 0x00080000
-#define BIT20 0x00100000
-#define BIT21 0x00200000
-#define BIT22 0x00400000
-#define BIT23 0x00800000
-#define BIT24 0x01000000
-#define BIT25 0x02000000
-#define BIT26 0x04000000
-#define BIT27 0x08000000
-#define BIT28 0x10000000
-#define BIT29 0x20000000
-#define BIT30 0x40000000
-#define BIT31 0x80000000
-#define BIT32 0x0000000100000000ULL
-#define BIT33 0x0000000200000000ULL
-#define BIT34 0x0000000400000000ULL
-#define BIT35 0x0000000800000000ULL
-#define BIT36 0x0000001000000000ULL
-#define BIT37 0x0000002000000000ULL
-#define BIT38 0x0000004000000000ULL
-#define BIT39 0x0000008000000000ULL
-#define BIT40 0x0000010000000000ULL
-#define BIT41 0x0000020000000000ULL
-#define BIT42 0x0000040000000000ULL
-#define BIT43 0x0000080000000000ULL
-#define BIT44 0x0000100000000000ULL
-#define BIT45 0x0000200000000000ULL
-#define BIT46 0x0000400000000000ULL
-#define BIT47 0x0000800000000000ULL
-#define BIT48 0x0001000000000000ULL
-#define BIT49 0x0002000000000000ULL
-#define BIT50 0x0004000000000000ULL
-#define BIT51 0x0008000000000000ULL
-#define BIT52 0x0010000000000000ULL
-#define BIT53 0x0020000000000000ULL
-#define BIT54 0x0040000000000000ULL
-#define BIT55 0x0080000000000000ULL
-#define BIT56 0x0100000000000000ULL
-#define BIT57 0x0200000000000000ULL
-#define BIT58 0x0400000000000000ULL
-#define BIT59 0x0800000000000000ULL
-#define BIT60 0x1000000000000000ULL
-#define BIT61 0x2000000000000000ULL
-#define BIT62 0x4000000000000000ULL
-#define BIT63 0x8000000000000000ULL
+#define BIT0 0x00000001
+#define BIT1 0x00000002
+#define BIT2 0x00000004
+#define BIT3 0x00000008
+#define BIT4 0x00000010
+#define BIT5 0x00000020
+#define BIT6 0x00000040
+#define BIT7 0x00000080
+#define BIT8 0x00000100
+#define BIT9 0x00000200
+#define BIT10 0x00000400
+#define BIT11 0x00000800
+#define BIT12 0x00001000
+#define BIT13 0x00002000
+#define BIT14 0x00004000
+#define BIT15 0x00008000
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+#define BIT32 0x0000000100000000ULL
+#define BIT33 0x0000000200000000ULL
+#define BIT34 0x0000000400000000ULL
+#define BIT35 0x0000000800000000ULL
+#define BIT36 0x0000001000000000ULL
+#define BIT37 0x0000002000000000ULL
+#define BIT38 0x0000004000000000ULL
+#define BIT39 0x0000008000000000ULL
+#define BIT40 0x0000010000000000ULL
+#define BIT41 0x0000020000000000ULL
+#define BIT42 0x0000040000000000ULL
+#define BIT43 0x0000080000000000ULL
+#define BIT44 0x0000100000000000ULL
+#define BIT45 0x0000200000000000ULL
+#define BIT46 0x0000400000000000ULL
+#define BIT47 0x0000800000000000ULL
+#define BIT48 0x0001000000000000ULL
+#define BIT49 0x0002000000000000ULL
+#define BIT50 0x0004000000000000ULL
+#define BIT51 0x0008000000000000ULL
+#define BIT52 0x0010000000000000ULL
+#define BIT53 0x0020000000000000ULL
+#define BIT54 0x0040000000000000ULL
+#define BIT55 0x0080000000000000ULL
+#define BIT56 0x0100000000000000ULL
+#define BIT57 0x0200000000000000ULL
+#define BIT58 0x0400000000000000ULL
+#define BIT59 0x0800000000000000ULL
+#define BIT60 0x1000000000000000ULL
+#define BIT61 0x2000000000000000ULL
+#define BIT62 0x4000000000000000ULL
+#define BIT63 0x8000000000000000ULL
#define SIZE_1KB 0x00000400
#define SIZE_2KB 0x00000800
@@ -577,53 +576,23 @@ struct _LIST_ENTRY {
@return The aligned size.
**/
-#define _INT_SIZE_OF(n) ((sizeof (n) + sizeof (UINTN) - 1) &~(sizeof (UINTN) - 1))
+#define _INT_SIZE_OF(n) ((sizeof (n) + sizeof (UINTN) - 1) &~(sizeof (UINTN) - 1))
-#if defined(__CC_ARM)
-//
-// RVCT ARM variable argument list support.
-//
-
-///
-/// Variable used to traverse the list of arguments. This type can vary by
-/// implementation and could be an array or structure.
-///
-#ifdef __APCS_ADSABI
- typedef int *va_list[1];
- #define VA_LIST va_list
-#else
- typedef struct __va_list { void *__ap; } va_list;
- #define VA_LIST va_list
-#endif
-
-#define VA_START(Marker, Parameter) __va_start(Marker, Parameter)
-
-#define VA_ARG(Marker, TYPE) __va_arg(Marker, TYPE)
-
-#define VA_END(Marker) ((void)0)
-
-// For some ARM RVCT compilers, __va_copy is not defined
-#ifndef __va_copy
- #define __va_copy(dest, src) ((void)((dest) = (src)))
-#endif
-
-#define VA_COPY(Dest, Start) __va_copy (Dest, Start)
-
-#elif defined(_M_ARM) || defined(_M_ARM64)
+#if defined (_M_ARM) || defined (_M_ARM64)
//
// MSFT ARM variable argument list support.
//
-typedef char* VA_LIST;
+typedef char *VA_LIST;
-#define VA_START(Marker, Parameter) __va_start (&Marker, &Parameter, _INT_SIZE_OF (Parameter), __alignof(Parameter), &Parameter)
-#define VA_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _INT_SIZE_OF (TYPE) + ((-(INTN)Marker) & (sizeof(TYPE) - 1))) - _INT_SIZE_OF (TYPE)))
-#define VA_END(Marker) (Marker = (VA_LIST) 0)
-#define VA_COPY(Dest, Start) ((void)((Dest) = (Start)))
+#define VA_START(Marker, Parameter) __va_start (&Marker, &Parameter, _INT_SIZE_OF (Parameter), __alignof(Parameter), &Parameter)
+#define VA_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _INT_SIZE_OF (TYPE) + ((-(INTN)Marker) & (sizeof(TYPE) - 1))) - _INT_SIZE_OF (TYPE)))
+#define VA_END(Marker) (Marker = (VA_LIST) 0)
+#define VA_COPY(Dest, Start) ((void)((Dest) = (Start)))
-#elif defined(__GNUC__) || defined(__clang__)
+#elif defined (__GNUC__) || defined (__clang__)
-#if defined(MDE_CPU_X64) && !defined(NO_MSABI_VA_FUNCS)
+ #if defined (MDE_CPU_X64) && !defined (NO_MSABI_VA_FUNCS)
//
// X64 only. Use MS ABI version of GCC built-in macros for variable argument lists.
//
@@ -639,13 +608,13 @@ typedef __builtin_ms_va_list VA_LIST;
#define VA_START(Marker, Parameter) __builtin_ms_va_start (Marker, Parameter)
-#define VA_ARG(Marker, TYPE) ((sizeof (TYPE) < sizeof (UINTN)) ? (TYPE)(__builtin_va_arg (Marker, UINTN)) : (TYPE)(__builtin_va_arg (Marker, TYPE)))
+#define VA_ARG(Marker, TYPE) ((sizeof (TYPE) < sizeof (UINTN)) ? (TYPE)(__builtin_va_arg (Marker, UINTN)) : (TYPE)(__builtin_va_arg (Marker, TYPE)))
-#define VA_END(Marker) __builtin_ms_va_end (Marker)
+#define VA_END(Marker) __builtin_ms_va_end (Marker)
-#define VA_COPY(Dest, Start) __builtin_ms_va_copy (Dest, Start)
+#define VA_COPY(Dest, Start) __builtin_ms_va_copy (Dest, Start)
-#else
+ #else
//
// Use GCC built-in macros for variable argument lists.
//
@@ -658,13 +627,13 @@ typedef __builtin_va_list VA_LIST;
#define VA_START(Marker, Parameter) __builtin_va_start (Marker, Parameter)
-#define VA_ARG(Marker, TYPE) ((sizeof (TYPE) < sizeof (UINTN)) ? (TYPE)(__builtin_va_arg (Marker, UINTN)) : (TYPE)(__builtin_va_arg (Marker, TYPE)))
+#define VA_ARG(Marker, TYPE) ((sizeof (TYPE) < sizeof (UINTN)) ? (TYPE)(__builtin_va_arg (Marker, UINTN)) : (TYPE)(__builtin_va_arg (Marker, TYPE)))
-#define VA_END(Marker) __builtin_va_end (Marker)
+#define VA_END(Marker) __builtin_va_end (Marker)
-#define VA_COPY(Dest, Start) __builtin_va_copy (Dest, Start)
+#define VA_COPY(Dest, Start) __builtin_va_copy (Dest, Start)
-#endif
+ #endif
#else
///
@@ -689,7 +658,7 @@ typedef CHAR8 *VA_LIST;
@return A pointer to the beginning of a variable argument list.
**/
-#define VA_START(Marker, Parameter) (Marker = (VA_LIST) ((UINTN) & (Parameter) + _INT_SIZE_OF (Parameter)))
+#define VA_START(Marker, Parameter) (Marker = (VA_LIST) ((UINTN) & (Parameter) + _INT_SIZE_OF (Parameter)))
/**
Returns an argument of a specified type from a variable argument list and updates
@@ -707,7 +676,7 @@ typedef CHAR8 *VA_LIST;
@return An argument of the type specified by TYPE.
**/
-#define VA_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _INT_SIZE_OF (TYPE)) - _INT_SIZE_OF (TYPE)))
+#define VA_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _INT_SIZE_OF (TYPE)) - _INT_SIZE_OF (TYPE)))
/**
Terminates the use of a variable argument list.
@@ -719,7 +688,7 @@ typedef CHAR8 *VA_LIST;
@param Marker VA_LIST used to traverse the list of arguments.
**/
-#define VA_END(Marker) (Marker = (VA_LIST) 0)
+#define VA_END(Marker) (Marker = (VA_LIST) 0)
/**
Initializes a VA_LIST as a copy of an existing VA_LIST.
@@ -739,7 +708,7 @@ typedef CHAR8 *VA_LIST;
///
/// Pointer to the start of a variable argument list stored in a memory buffer. Same as UINT8 *.
///
-typedef UINTN *BASE_LIST;
+typedef UINTN *BASE_LIST;
/**
Returns the size of a data type in sizeof(UINTN) units rounded up to the nearest UINTN boundary.
@@ -748,7 +717,7 @@ typedef UINTN *BASE_LIST;
@return The size of TYPE in sizeof (UINTN) units rounded up to the nearest UINTN boundary.
**/
-#define _BASE_INT_SIZE_OF(TYPE) ((sizeof (TYPE) + sizeof (UINTN) - 1) / sizeof (UINTN))
+#define _BASE_INT_SIZE_OF(TYPE) ((sizeof (TYPE) + sizeof (UINTN) - 1) / sizeof (UINTN))
/**
Returns an argument of a specified type from a variable argument list and updates
@@ -766,7 +735,7 @@ typedef UINTN *BASE_LIST;
@return An argument of the type specified by TYPE.
**/
-#define BASE_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _BASE_INT_SIZE_OF (TYPE)) - _BASE_INT_SIZE_OF (TYPE)))
+#define BASE_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _BASE_INT_SIZE_OF (TYPE)) - _BASE_INT_SIZE_OF (TYPE)))
/**
The macro that returns the byte offset of a field in a data structure.
@@ -781,12 +750,46 @@ typedef UINTN *BASE_LIST;
@return Offset, in bytes, of field.
**/
-#if (defined(__GNUC__) && __GNUC__ >= 4) || defined(__clang__)
-#define OFFSET_OF(TYPE, Field) ((UINTN) __builtin_offsetof(TYPE, Field))
+#if (defined (__GNUC__) && __GNUC__ >= 4) || defined (__clang__)
+#define OFFSET_OF(TYPE, Field) ((UINTN) __builtin_offsetof(TYPE, Field))
#endif
#ifndef OFFSET_OF
-#define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field))
+#define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field))
+#endif
+
+/**
+ Returns the alignment requirement of a type.
+
+ @param TYPE The name of the type to retrieve the alignment requirement of.
+
+ @return Alignment requirement, in Bytes, of TYPE.
+**/
+#if defined (__cplusplus)
+//
+// Standard C++ operator.
+//
+#define ALIGNOF(TYPE) alignof (TYPE)
+#elif defined (__GNUC__) || defined (__clang__) || (defined (_MSC_VER) && _MSC_VER >= 1900)
+//
+// All supported versions of GCC and Clang, as well as MSVC 2015 and later,
+// support the standard operator _Alignof.
+//
+#define ALIGNOF(TYPE) _Alignof (TYPE)
+#elif defined (_MSC_EXTENSIONS)
+//
+// Earlier versions of MSVC, at least MSVC 2008 and later, support the vendor
+// extension __alignof.
+//
+#define ALIGNOF(TYPE) __alignof (TYPE)
+#else
+//
+// For compilers that do not support inbuilt alignof operators, use OFFSET_OF.
+// CHAR8 is known to have both a size and an alignment requirement of 1 Byte.
+// As such, A must be located exactly at the offset equal to its alignment
+// requirement.
+//
+#define ALIGNOF(TYPE) OFFSET_OF (struct { CHAR8 C; TYPE A; }, A)
#endif
/**
@@ -798,11 +801,11 @@ typedef UINTN *BASE_LIST;
**/
#ifdef MDE_CPU_EBC
- #define STATIC_ASSERT(Expression, Message)
-#elif defined(_MSC_EXTENSIONS)
- #define STATIC_ASSERT static_assert
+#define STATIC_ASSERT(Expression, Message)
+#elif defined (_MSC_EXTENSIONS) || defined (__cplusplus)
+#define STATIC_ASSERT static_assert
#else
- #define STATIC_ASSERT _Static_assert
+#define STATIC_ASSERT _Static_assert
#endif
//
@@ -824,12 +827,27 @@ STATIC_ASSERT (sizeof (CHAR16) == 2, "sizeof (CHAR16) does not meet UEFI Specif
STATIC_ASSERT (sizeof (L'A') == 2, "sizeof (L'A') does not meet UEFI Specification Data Type requirements");
STATIC_ASSERT (sizeof (L"A") == 4, "sizeof (L\"A\") does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (ALIGNOF (BOOLEAN) == sizeof (BOOLEAN), "Alignment of BOOLEAN does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (ALIGNOF (INT8) == sizeof (INT8), "Alignment of INT8 does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (ALIGNOF (UINT8) == sizeof (UINT8), "Alignment of INT16 does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (ALIGNOF (INT16) == sizeof (INT16), "Alignment of INT16 does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (ALIGNOF (UINT16) == sizeof (UINT16), "Alignment of UINT16 does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (ALIGNOF (INT32) == sizeof (INT32), "Alignment of INT32 does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (ALIGNOF (UINT32) == sizeof (UINT32), "Alignment of UINT32 does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (ALIGNOF (INT64) == sizeof (INT64), "Alignment of INT64 does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (ALIGNOF (UINT64) == sizeof (UINT64), "Alignment of UINT64 does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (ALIGNOF (CHAR8) == sizeof (CHAR8), "Alignment of CHAR8 does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (ALIGNOF (CHAR16) == sizeof (CHAR16), "Alignment of CHAR16 does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (ALIGNOF (INTN) == sizeof (INTN), "Alignment of INTN does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (ALIGNOF (UINTN) == sizeof (UINTN), "Alignment of UINTN does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (ALIGNOF (VOID *) == sizeof (VOID *), "Alignment of VOID * does not meet UEFI Specification Data Type requirements");
+
//
// The following three enum types are used to verify that the compiler
// configuration for enum types is compliant with Section 2.3.1 of the
-// UEFI 2.3 Specification. These enum types and enum values are not
-// intended to be used. A prefix of '__' is used avoid conflicts with
-// other types.
+// UEFI 2.3.1 Errata C Specification. These enum types and enum values
+// are not intended to be used. A prefix of '__' is used avoid
+// conflicts with other types.
//
typedef enum {
__VerifyUint8EnumValue = 0xff
@@ -840,12 +858,16 @@ typedef enum {
} __VERIFY_UINT16_ENUM_SIZE;
typedef enum {
- __VerifyUint32EnumValue = 0xffffffff
-} __VERIFY_UINT32_ENUM_SIZE;
+ __VerifyInt32EnumValue = 0x7fffffff
+} __VERIFY_INT32_ENUM_SIZE;
STATIC_ASSERT (sizeof (__VERIFY_UINT8_ENUM_SIZE) == 4, "Size of enum does not meet UEFI Specification Data Type requirements");
STATIC_ASSERT (sizeof (__VERIFY_UINT16_ENUM_SIZE) == 4, "Size of enum does not meet UEFI Specification Data Type requirements");
-STATIC_ASSERT (sizeof (__VERIFY_UINT32_ENUM_SIZE) == 4, "Size of enum does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (__VERIFY_INT32_ENUM_SIZE) == 4, "Size of enum does not meet UEFI Specification Data Type requirements");
+
+STATIC_ASSERT (ALIGNOF (__VERIFY_UINT8_ENUM_SIZE) == sizeof (__VERIFY_UINT8_ENUM_SIZE), "Alignment of enum does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (ALIGNOF (__VERIFY_UINT16_ENUM_SIZE) == sizeof (__VERIFY_UINT16_ENUM_SIZE), "Alignment of enum does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (ALIGNOF (__VERIFY_INT32_ENUM_SIZE) == sizeof (__VERIFY_INT32_ENUM_SIZE), "Alignment of enum does not meet UEFI Specification Data Type requirements");
/**
Macro that returns a pointer to the data structure that contains a specified field of
@@ -868,6 +890,49 @@ STATIC_ASSERT (sizeof (__VERIFY_UINT32_ENUM_SIZE) == 4, "Size of enum does not m
**/
#define BASE_CR(Record, TYPE, Field) ((TYPE *) ((CHAR8 *) (Record) - OFFSET_OF (TYPE, Field)))
+/**
+ Checks whether a value is a power of two.
+
+ @param Value The value to check.
+
+ @retval TRUE Value is a power of two.
+ @retval FALSE Value is not a power of two.
+**/
+#define IS_POW2(Value) ((Value) != 0U && ((Value) & ((Value) - 1U)) == 0U)
+
+/**
+ Checks whether a value is aligned by a specified alignment.
+
+ @param Value The value to check.
+ @param Alignment The alignment boundary used to check against.
+
+ @retval TRUE Value is aligned by Alignment.
+ @retval FALSE Value is not aligned by Alignment.
+**/
+#define IS_ALIGNED(Value, Alignment) (((Value) & ((Alignment) - 1U)) == 0U)
+
+/**
+ Checks whether a pointer or address is aligned by a specified alignment.
+
+ @param Address The pointer or address to check.
+ @param Alignment The alignment boundary used to check against.
+
+ @retval TRUE Address is aligned by Alignment.
+ @retval FALSE Address is not aligned by Alignment.
+**/
+#define ADDRESS_IS_ALIGNED(Address, Alignment) IS_ALIGNED ((UINTN) (Address), Alignment)
+
+/**
+ Determines the addend to add to a value to round it up to the next boundary of
+ a specified alignment.
+
+ @param Value The value to round up.
+ @param Alignment The alignment boundary used to return the addend.
+
+ @return Addend to round Value up to alignment boundary Alignment.
+**/
+#define ALIGN_VALUE_ADDEND(Value, Alignment) (((Alignment) - (Value)) & ((Alignment) - 1U))
+
/**
Rounds a value up to the next boundary using a specified alignment.
@@ -880,7 +945,7 @@ STATIC_ASSERT (sizeof (__VERIFY_UINT32_ENUM_SIZE) == 4, "Size of enum does not m
@return A value up to the next boundary.
**/
-#define ALIGN_VALUE(Value, Alignment) ((Value) + (((Alignment) - (Value)) & ((Alignment) - 1)))
+#define ALIGN_VALUE(Value, Alignment) ((Value) + ALIGN_VALUE_ADDEND (Value, Alignment))
/**
Adjust a pointer by adding the minimum offset required for it to be aligned on
@@ -895,7 +960,7 @@ STATIC_ASSERT (sizeof (__VERIFY_UINT32_ENUM_SIZE) == 4, "Size of enum does not m
@return Pointer to the aligned address.
**/
-#define ALIGN_POINTER(Pointer, Alignment) ((VOID *) (ALIGN_VALUE ((UINTN)(Pointer), (Alignment))))
+#define ALIGN_POINTER(Pointer, Alignment) ((VOID *) (ALIGN_VALUE ((UINTN)(Pointer), (Alignment))))
/**
Rounds a value up to the next natural boundary for the current CPU.
@@ -911,7 +976,6 @@ STATIC_ASSERT (sizeof (__VERIFY_UINT32_ENUM_SIZE) == 4, "Size of enum does not m
**/
#define ALIGN_VARIABLE(Value) ALIGN_VALUE ((Value), sizeof (UINTN))
-
/**
Return the maximum of two operands.
@@ -970,7 +1034,7 @@ typedef UINTN RETURN_STATUS;
@return The value specified by StatusCode with the highest bit set.
**/
-#define ENCODE_ERROR(StatusCode) ((RETURN_STATUS)(MAX_BIT | (StatusCode)))
+#define ENCODE_ERROR(StatusCode) ((RETURN_STATUS)(MAX_BIT | (StatusCode)))
/**
Produces a RETURN_STATUS code with the highest bit clear.
@@ -981,7 +1045,7 @@ typedef UINTN RETURN_STATUS;
@return The value specified by StatusCode with the highest bit clear.
**/
-#define ENCODE_WARNING(StatusCode) ((RETURN_STATUS)(StatusCode))
+#define ENCODE_WARNING(StatusCode) ((RETURN_STATUS)(StatusCode))
/**
Returns TRUE if a specified RETURN_STATUS code is an error code.
@@ -994,138 +1058,138 @@ typedef UINTN RETURN_STATUS;
@retval FALSE The high bit of StatusCode is clear.
**/
-#define RETURN_ERROR(StatusCode) (((INTN)(RETURN_STATUS)(StatusCode)) < 0)
+#define RETURN_ERROR(StatusCode) (((INTN)(RETURN_STATUS)(StatusCode)) < 0)
///
/// The operation completed successfully.
///
-#define RETURN_SUCCESS 0
+#define RETURN_SUCCESS (RETURN_STATUS)(0)
///
/// The image failed to load.
///
-#define RETURN_LOAD_ERROR ENCODE_ERROR (1)
+#define RETURN_LOAD_ERROR ENCODE_ERROR (1)
///
/// The parameter was incorrect.
///
-#define RETURN_INVALID_PARAMETER ENCODE_ERROR (2)
+#define RETURN_INVALID_PARAMETER ENCODE_ERROR (2)
///
/// The operation is not supported.
///
-#define RETURN_UNSUPPORTED ENCODE_ERROR (3)
+#define RETURN_UNSUPPORTED ENCODE_ERROR (3)
///
/// The buffer was not the proper size for the request.
///
-#define RETURN_BAD_BUFFER_SIZE ENCODE_ERROR (4)
+#define RETURN_BAD_BUFFER_SIZE ENCODE_ERROR (4)
///
/// The buffer was not large enough to hold the requested data.
/// The required buffer size is returned in the appropriate
/// parameter when this error occurs.
///
-#define RETURN_BUFFER_TOO_SMALL ENCODE_ERROR (5)
+#define RETURN_BUFFER_TOO_SMALL ENCODE_ERROR (5)
///
/// There is no data pending upon return.
///
-#define RETURN_NOT_READY ENCODE_ERROR (6)
+#define RETURN_NOT_READY ENCODE_ERROR (6)
///
/// The physical device reported an error while attempting the
/// operation.
///
-#define RETURN_DEVICE_ERROR ENCODE_ERROR (7)
+#define RETURN_DEVICE_ERROR ENCODE_ERROR (7)
///
/// The device can not be written to.
///
-#define RETURN_WRITE_PROTECTED ENCODE_ERROR (8)
+#define RETURN_WRITE_PROTECTED ENCODE_ERROR (8)
///
/// The resource has run out.
///
-#define RETURN_OUT_OF_RESOURCES ENCODE_ERROR (9)
+#define RETURN_OUT_OF_RESOURCES ENCODE_ERROR (9)
///
/// An inconsistency was detected on the file system causing the
/// operation to fail.
///
-#define RETURN_VOLUME_CORRUPTED ENCODE_ERROR (10)
+#define RETURN_VOLUME_CORRUPTED ENCODE_ERROR (10)
///
/// There is no more space on the file system.
///
-#define RETURN_VOLUME_FULL ENCODE_ERROR (11)
+#define RETURN_VOLUME_FULL ENCODE_ERROR (11)
///
/// The device does not contain any medium to perform the
/// operation.
///
-#define RETURN_NO_MEDIA ENCODE_ERROR (12)
+#define RETURN_NO_MEDIA ENCODE_ERROR (12)
///
/// The medium in the device has changed since the last
/// access.
///
-#define RETURN_MEDIA_CHANGED ENCODE_ERROR (13)
+#define RETURN_MEDIA_CHANGED ENCODE_ERROR (13)
///
/// The item was not found.
///
-#define RETURN_NOT_FOUND ENCODE_ERROR (14)
+#define RETURN_NOT_FOUND ENCODE_ERROR (14)
///
/// Access was denied.
///
-#define RETURN_ACCESS_DENIED ENCODE_ERROR (15)
+#define RETURN_ACCESS_DENIED ENCODE_ERROR (15)
///
/// The server was not found or did not respond to the request.
///
-#define RETURN_NO_RESPONSE ENCODE_ERROR (16)
+#define RETURN_NO_RESPONSE ENCODE_ERROR (16)
///
/// A mapping to the device does not exist.
///
-#define RETURN_NO_MAPPING ENCODE_ERROR (17)
+#define RETURN_NO_MAPPING ENCODE_ERROR (17)
///
/// A timeout time expired.
///
-#define RETURN_TIMEOUT ENCODE_ERROR (18)
+#define RETURN_TIMEOUT ENCODE_ERROR (18)
///
/// The protocol has not been started.
///
-#define RETURN_NOT_STARTED ENCODE_ERROR (19)
+#define RETURN_NOT_STARTED ENCODE_ERROR (19)
///
/// The protocol has already been started.
///
-#define RETURN_ALREADY_STARTED ENCODE_ERROR (20)
+#define RETURN_ALREADY_STARTED ENCODE_ERROR (20)
///
/// The operation was aborted.
///
-#define RETURN_ABORTED ENCODE_ERROR (21)
+#define RETURN_ABORTED ENCODE_ERROR (21)
///
/// An ICMP error occurred during the network operation.
///
-#define RETURN_ICMP_ERROR ENCODE_ERROR (22)
+#define RETURN_ICMP_ERROR ENCODE_ERROR (22)
///
/// A TFTP error occurred during the network operation.
///
-#define RETURN_TFTP_ERROR ENCODE_ERROR (23)
+#define RETURN_TFTP_ERROR ENCODE_ERROR (23)
///
/// A protocol error occurred during the network operation.
///
-#define RETURN_PROTOCOL_ERROR ENCODE_ERROR (24)
+#define RETURN_PROTOCOL_ERROR ENCODE_ERROR (24)
///
/// A function encountered an internal version that was
@@ -1136,74 +1200,83 @@ typedef UINTN RETURN_STATUS;
///
/// The function was not performed due to a security violation.
///
-#define RETURN_SECURITY_VIOLATION ENCODE_ERROR (26)
+#define RETURN_SECURITY_VIOLATION ENCODE_ERROR (26)
///
/// A CRC error was detected.
///
-#define RETURN_CRC_ERROR ENCODE_ERROR (27)
+#define RETURN_CRC_ERROR ENCODE_ERROR (27)
///
/// The beginning or end of media was reached.
///
-#define RETURN_END_OF_MEDIA ENCODE_ERROR (28)
+#define RETURN_END_OF_MEDIA ENCODE_ERROR (28)
///
/// The end of the file was reached.
///
-#define RETURN_END_OF_FILE ENCODE_ERROR (31)
+#define RETURN_END_OF_FILE ENCODE_ERROR (31)
///
/// The language specified was invalid.
///
-#define RETURN_INVALID_LANGUAGE ENCODE_ERROR (32)
+#define RETURN_INVALID_LANGUAGE ENCODE_ERROR (32)
///
/// The security status of the data is unknown or compromised
/// and the data must be updated or replaced to restore a valid
/// security status.
///
-#define RETURN_COMPROMISED_DATA ENCODE_ERROR (33)
+#define RETURN_COMPROMISED_DATA ENCODE_ERROR (33)
+
+///
+/// There is an address conflict address allocation.
+///
+#define RETURN_IP_ADDRESS_CONFLICT ENCODE_ERROR (34)
///
/// A HTTP error occurred during the network operation.
///
-#define RETURN_HTTP_ERROR ENCODE_ERROR (35)
+#define RETURN_HTTP_ERROR ENCODE_ERROR (35)
///
/// The string contained one or more characters that
/// the device could not render and were skipped.
///
-#define RETURN_WARN_UNKNOWN_GLYPH ENCODE_WARNING (1)
+#define RETURN_WARN_UNKNOWN_GLYPH ENCODE_WARNING (1)
///
/// The handle was closed, but the file was not deleted.
///
-#define RETURN_WARN_DELETE_FAILURE ENCODE_WARNING (2)
+#define RETURN_WARN_DELETE_FAILURE ENCODE_WARNING (2)
///
/// The handle was closed, but the data to the file was not
/// flushed properly.
///
-#define RETURN_WARN_WRITE_FAILURE ENCODE_WARNING (3)
+#define RETURN_WARN_WRITE_FAILURE ENCODE_WARNING (3)
///
/// The resulting buffer was too small, and the data was
/// truncated to the buffer size.
///
-#define RETURN_WARN_BUFFER_TOO_SMALL ENCODE_WARNING (4)
+#define RETURN_WARN_BUFFER_TOO_SMALL ENCODE_WARNING (4)
///
/// The data has not been updated within the timeframe set by
/// local policy for this type of data.
///
-#define RETURN_WARN_STALE_DATA ENCODE_WARNING (5)
+#define RETURN_WARN_STALE_DATA ENCODE_WARNING (5)
///
/// The resulting buffer contains UEFI-compliant file system.
///
-#define RETURN_WARN_FILE_SYSTEM ENCODE_WARNING (6)
+#define RETURN_WARN_FILE_SYSTEM ENCODE_WARNING (6)
+///
+/// The operation will be processed across a system reset.
+///
+#define RETURN_WARN_RESET_REQUIRED ENCODE_WARNING (7)
/**
Returns a 16-bit signature built from 2 ASCII characters.
@@ -1217,7 +1290,7 @@ typedef UINTN RETURN_STATUS;
@return A 16-bit value built from the two ASCII characters specified by A and B.
**/
-#define SIGNATURE_16(A, B) ((A) | (B << 8))
+#define SIGNATURE_16(A, B) ((A) | (B << 8))
/**
Returns a 32-bit signature built from 4 ASCII characters.
@@ -1258,45 +1331,52 @@ typedef UINTN RETURN_STATUS;
#define SIGNATURE_64(A, B, C, D, E, F, G, H) \
(SIGNATURE_32 (A, B, C, D) | ((UINT64) (SIGNATURE_32 (E, F, G, H)) << 32))
-#if defined(_MSC_EXTENSIONS) && !defined (__INTEL_COMPILER) && !defined (MDE_CPU_EBC)
- void * _ReturnAddress(void);
+#if defined (_MSC_EXTENSIONS) && !defined (__INTEL_COMPILER) && !defined (MDE_CPU_EBC)
+void *
+_ReturnAddress (
+ void
+ );
+
#pragma intrinsic(_ReturnAddress)
- /**
- Get the return address of the calling function.
- Based on intrinsic function _ReturnAddress that provides the address of
- the instruction in the calling function that will be executed after
- control returns to the caller.
+/**
+ Get the return address of the calling function.
- @param L Return Level.
+ Based on intrinsic function _ReturnAddress that provides the address of
+ the instruction in the calling function that will be executed after
+ control returns to the caller.
- @return The return address of the calling function or 0 if L != 0.
+ @param L Return Level.
- **/
- #define RETURN_ADDRESS(L) ((L == 0) ? _ReturnAddress() : (VOID *) 0)
+ @return The return address of the calling function or 0 if L != 0.
+
+**/
+#define RETURN_ADDRESS(L) ((L == 0) ? _ReturnAddress() : (VOID *) 0)
#elif defined (__GNUC__) || defined (__clang__)
- /**
- Get the return address of the calling function.
- Based on built-in Function __builtin_return_address that returns
- the return address of the current function, or of one of its callers.
+/**
+ Get the return address of the calling function.
- @param L Return Level.
+ Based on built-in Function __builtin_return_address that returns
+ the return address of the current function, or of one of its callers.
- @return The return address of the calling function.
+ @param L Return Level.
- **/
- #define RETURN_ADDRESS(L) __builtin_return_address (L)
+ @return The return address of the calling function.
+
+**/
+#define RETURN_ADDRESS(L) __builtin_return_address (L)
#else
- /**
- Get the return address of the calling function.
- @param L Return Level.
+/**
+ Get the return address of the calling function.
- @return 0 as compilers don't support this feature.
+ @param L Return Level.
- **/
- #define RETURN_ADDRESS(L) ((VOID *) 0)
+ @return 0 as compilers don't support this feature.
+
+**/
+#define RETURN_ADDRESS(L) ((VOID *) 0)
#endif
/**
@@ -1310,7 +1390,6 @@ typedef UINTN RETURN_STATUS;
@return The number of elements in Array. The result has type UINTN.
**/
-#define ARRAY_SIZE(Array) (sizeof (Array) / sizeof ((Array)[0]))
+#define ARRAY_SIZE(Array) (sizeof (Array) / sizeof ((Array)[0]))
#endif
-
diff --git a/MdePkg/Include/Guid/GraphicsInfoHob.h b/MdePkg/Include/Guid/GraphicsInfoHob.h
index cd1965c3..20f8b0c3 100644
--- a/MdePkg/Include/Guid/GraphicsInfoHob.h
+++ b/MdePkg/Include/Guid/GraphicsInfoHob.h
@@ -25,21 +25,21 @@
}
typedef struct {
- EFI_PHYSICAL_ADDRESS FrameBufferBase;
- UINT32 FrameBufferSize;
- EFI_GRAPHICS_OUTPUT_MODE_INFORMATION GraphicsMode;
+ EFI_PHYSICAL_ADDRESS FrameBufferBase;
+ UINT32 FrameBufferSize;
+ EFI_GRAPHICS_OUTPUT_MODE_INFORMATION GraphicsMode;
} EFI_PEI_GRAPHICS_INFO_HOB;
typedef struct {
- UINT16 VendorId; ///< Ignore if the value is 0xFFFF.
- UINT16 DeviceId; ///< Ignore if the value is 0xFFFF.
- UINT16 SubsystemVendorId; ///< Ignore if the value is 0xFFFF.
- UINT16 SubsystemId; ///< Ignore if the value is 0xFFFF.
- UINT8 RevisionId; ///< Ignore if the value is 0xFF.
- UINT8 BarIndex; ///< Ignore if the value is 0xFF.
+ UINT16 VendorId; ///< Ignore if the value is 0xFFFF.
+ UINT16 DeviceId; ///< Ignore if the value is 0xFFFF.
+ UINT16 SubsystemVendorId; ///< Ignore if the value is 0xFFFF.
+ UINT16 SubsystemId; ///< Ignore if the value is 0xFFFF.
+ UINT8 RevisionId; ///< Ignore if the value is 0xFF.
+ UINT8 BarIndex; ///< Ignore if the value is 0xFF.
} EFI_PEI_GRAPHICS_DEVICE_INFO_HOB;
-extern EFI_GUID gEfiGraphicsInfoHobGuid;
-extern EFI_GUID gEfiGraphicsDeviceInfoHobGuid;
+extern EFI_GUID gEfiGraphicsInfoHobGuid;
+extern EFI_GUID gEfiGraphicsDeviceInfoHobGuid;
#endif
diff --git a/MdePkg/Include/Guid/PcAnsi.h b/MdePkg/Include/Guid/PcAnsi.h
index 312df6bd..867dfb4d 100644
--- a/MdePkg/Include/Guid/PcAnsi.h
+++ b/MdePkg/Include/Guid/PcAnsi.h
@@ -42,11 +42,11 @@
0xd487ddb4, 0x008b, 0x11d9, {0xaf, 0xdc, 0x00, 0x10, 0x83, 0xff, 0xca, 0x4d } \
}
-extern EFI_GUID gEfiPcAnsiGuid;
-extern EFI_GUID gEfiVT100Guid;
-extern EFI_GUID gEfiVT100PlusGuid;
-extern EFI_GUID gEfiVTUTF8Guid;
-extern EFI_GUID gEfiUartDevicePathGuid;
-extern EFI_GUID gEfiSasDevicePathGuid;
+extern EFI_GUID gEfiPcAnsiGuid;
+extern EFI_GUID gEfiVT100Guid;
+extern EFI_GUID gEfiVT100PlusGuid;
+extern EFI_GUID gEfiVTUTF8Guid;
+extern EFI_GUID gEfiUartDevicePathGuid;
+extern EFI_GUID gEfiSasDevicePathGuid;
#endif
diff --git a/MdePkg/Include/Guid/SmramMemoryReserve.h b/MdePkg/Include/Guid/SmramMemoryReserve.h
index 955b2fb0..44052802 100644
--- a/MdePkg/Include/Guid/SmramMemoryReserve.h
+++ b/MdePkg/Include/Guid/SmramMemoryReserve.h
@@ -31,15 +31,14 @@ typedef struct {
/// Designates the number of possible regions in the system
/// that can be usable for SMRAM.
///
- UINT32 NumberOfSmmReservedRegions;
+ UINT32 NumberOfSmmReservedRegions;
///
/// Used throughout this protocol to describe the candidate
/// regions for SMRAM that are supported by this platform.
///
- EFI_SMRAM_DESCRIPTOR Descriptor[1];
+ EFI_SMRAM_DESCRIPTOR Descriptor[1];
} EFI_SMRAM_HOB_DESCRIPTOR_BLOCK;
-extern EFI_GUID gEfiSmmSmramMemoryGuid;
+extern EFI_GUID gEfiSmmSmramMemoryGuid;
#endif
-
diff --git a/MdePkg/Include/Guid/SystemResourceTable.h b/MdePkg/Include/Guid/SystemResourceTable.h
index 75d1bbc1..46106660 100644
--- a/MdePkg/Include/Guid/SystemResourceTable.h
+++ b/MdePkg/Include/Guid/SystemResourceTable.h
@@ -10,7 +10,6 @@
**/
-
#ifndef _SYSTEM_RESOURCE_TABLE_H__
#define _SYSTEM_RESOURCE_TABLE_H__
@@ -35,14 +34,14 @@
///
/// Last Attempt Status Values
///
-#define LAST_ATTEMPT_STATUS_SUCCESS 0x00000000
-#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL 0x00000001
-#define LAST_ATTEMPT_STATUS_ERROR_INSUFFICIENT_RESOURCES 0x00000002
-#define LAST_ATTEMPT_STATUS_ERROR_INCORRECT_VERSION 0x00000003
-#define LAST_ATTEMPT_STATUS_ERROR_INVALID_FORMAT 0x00000004
-#define LAST_ATTEMPT_STATUS_ERROR_AUTH_ERROR 0x00000005
-#define LAST_ATTEMPT_STATUS_ERROR_PWR_EVT_AC 0x00000006
-#define LAST_ATTEMPT_STATUS_ERROR_PWR_EVT_BATT 0x00000007
+#define LAST_ATTEMPT_STATUS_SUCCESS 0x00000000
+#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL 0x00000001
+#define LAST_ATTEMPT_STATUS_ERROR_INSUFFICIENT_RESOURCES 0x00000002
+#define LAST_ATTEMPT_STATUS_ERROR_INCORRECT_VERSION 0x00000003
+#define LAST_ATTEMPT_STATUS_ERROR_INVALID_FORMAT 0x00000004
+#define LAST_ATTEMPT_STATUS_ERROR_AUTH_ERROR 0x00000005
+#define LAST_ATTEMPT_STATUS_ERROR_PWR_EVT_AC 0x00000006
+#define LAST_ATTEMPT_STATUS_ERROR_PWR_EVT_BATT 0x00000007
#define LAST_ATTEMPT_STATUS_ERROR_UNSATISFIED_DEPENDENCIES 0x00000008
///
@@ -54,8 +53,8 @@
/// When the UEFI Specification is updated, this comment block can be
/// removed.
///
-#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MIN 0x00001000
-#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MAX 0x00003FFF
+#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MIN 0x00001000
+#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MAX 0x00003FFF
typedef struct {
///
@@ -63,28 +62,28 @@ typedef struct {
/// that can be updated via UpdateCapsule(). This GUID must be unique within all
/// entries of the ESRT.
///
- EFI_GUID FwClass;
+ EFI_GUID FwClass;
///
/// Identifies the type of firmware resource.
///
- UINT32 FwType;
+ UINT32 FwType;
///
/// The firmware version field represents the current version of the firmware
/// resource, value must always increase as a larger number represents a newer
/// version.
///
- UINT32 FwVersion;
+ UINT32 FwVersion;
///
/// The lowest firmware resource version to which a firmware resource can be
/// rolled back for the given system/device. Generally this is used to protect
/// against known and fixed security issues.
///
- UINT32 LowestSupportedFwVersion;
+ UINT32 LowestSupportedFwVersion;
///
/// The capsule flags field contains the CapsuleGuid flags (bits 0- 15) as defined
/// in the EFI_CAPSULE_HEADER that will be set in the capsule header.
///
- UINT32 CapsuleFlags;
+ UINT32 CapsuleFlags;
///
/// The last attempt version field describes the last firmware version for which
/// an update was attempted (uses the same format as Firmware Version).
@@ -95,7 +94,7 @@ typedef struct {
/// in the case of a removable device, this value is set to 0 in cases where the
/// device has not been updated since being added to the system.
///
- UINT32 LastAttemptVersion;
+ UINT32 LastAttemptVersion;
///
/// The last attempt status field describes the result of the last firmware update
/// attempt for the firmware resource entry.
@@ -104,30 +103,30 @@ typedef struct {
/// If a firmware update has never been attempted or is unknown, for example after
/// fresh insertion of a removable device, LastAttemptStatus must be set to Success.
///
- UINT32 LastAttemptStatus;
+ UINT32 LastAttemptStatus;
} EFI_SYSTEM_RESOURCE_ENTRY;
typedef struct {
///
/// The number of firmware resources in the table, must not be zero.
///
- UINT32 FwResourceCount;
+ UINT32 FwResourceCount;
///
/// The maximum number of resource array entries that can be within the table
/// without reallocating the table, must not be zero.
///
- UINT32 FwResourceCountMax;
+ UINT32 FwResourceCountMax;
///
/// The version of the EFI_SYSTEM_RESOURCE_ENTRY entities used in this table.
/// This field should be set to 1.
///
- UINT64 FwResourceVersion;
+ UINT64 FwResourceVersion;
///
/// Array of EFI_SYSTEM_RESOURCE_ENTRY
///
- //EFI_SYSTEM_RESOURCE_ENTRY Entries[];
+ // EFI_SYSTEM_RESOURCE_ENTRY Entries[];
} EFI_SYSTEM_RESOURCE_TABLE;
-extern EFI_GUID gEfiSystemResourceTableGuid;
+extern EFI_GUID gEfiSystemResourceTableGuid;
#endif
diff --git a/MdePkg/Include/Guid/WinCertificate.h b/MdePkg/Include/Guid/WinCertificate.h
index c44bb388..72d766d2 100644
--- a/MdePkg/Include/Guid/WinCertificate.h
+++ b/MdePkg/Include/Guid/WinCertificate.h
@@ -14,9 +14,9 @@
//
// _WIN_CERTIFICATE.wCertificateType
//
-#define WIN_CERT_TYPE_PKCS_SIGNED_DATA 0x0002
-#define WIN_CERT_TYPE_EFI_PKCS115 0x0EF0
-#define WIN_CERT_TYPE_EFI_GUID 0x0EF1
+#define WIN_CERT_TYPE_PKCS_SIGNED_DATA 0x0002
+#define WIN_CERT_TYPE_EFI_PKCS115 0x0EF0
+#define WIN_CERT_TYPE_EFI_GUID 0x0EF1
///
/// The WIN_CERTIFICATE structure is part of the PE/COFF specification.
@@ -26,18 +26,18 @@ typedef struct {
/// The length of the entire certificate,
/// including the length of the header, in bytes.
///
- UINT32 dwLength;
+ UINT32 dwLength;
///
/// The revision level of the WIN_CERTIFICATE
/// structure. The current revision level is 0x0200.
///
- UINT16 wRevision;
+ UINT16 wRevision;
///
/// The certificate type. See WIN_CERT_TYPE_xxx for the UEFI
/// certificate types. The UEFI specification reserves the range of
/// certificate type values from 0x0EF0 to 0x0EFF.
///
- UINT16 wCertificateType;
+ UINT16 wCertificateType;
///
/// The following is the actual certificate. The format of
/// the certificate depends on wCertificateType.
@@ -56,12 +56,11 @@ typedef struct {
/// WIN_CERTIFICATE_UEFI_GUID.CertData
///
typedef struct {
- EFI_GUID HashType;
- UINT8 PublicKey[256];
- UINT8 Signature[256];
+ EFI_GUID HashType;
+ UINT8 PublicKey[256];
+ UINT8 Signature[256];
} EFI_CERT_BLOCK_RSA_2048_SHA256;
-
///
/// Certificate which encapsulates a GUID-specific digital signature
///
@@ -70,22 +69,21 @@ typedef struct {
/// This is the standard WIN_CERTIFICATE header, where
/// wCertificateType is set to WIN_CERT_TYPE_EFI_GUID.
///
- WIN_CERTIFICATE Hdr;
+ WIN_CERTIFICATE Hdr;
///
/// This is the unique id which determines the
/// format of the CertData. .
///
- EFI_GUID CertType;
+ EFI_GUID CertType;
///
/// The following is the certificate data. The format of
/// the data is determined by the CertType.
/// If CertType is EFI_CERT_TYPE_RSA2048_SHA256_GUID,
/// the CertData will be EFI_CERT_BLOCK_RSA_2048_SHA256 structure.
///
- UINT8 CertData[1];
+ UINT8 CertData[1];
} WIN_CERTIFICATE_UEFI_GUID;
-
///
/// Certificate which encapsulates the RSASSA_PKCS1-v1_5 digital signature.
///
@@ -99,12 +97,12 @@ typedef struct {
/// This is the standard WIN_CERTIFICATE header, where
/// wCertificateType is set to WIN_CERT_TYPE_UEFI_PKCS1_15.
///
- WIN_CERTIFICATE Hdr;
+ WIN_CERTIFICATE Hdr;
///
/// This is the hashing algorithm which was performed on the
/// UEFI executable when creating the digital signature.
///
- EFI_GUID HashAlgorithm;
+ EFI_GUID HashAlgorithm;
///
/// The following is the actual digital signature. The
/// size of the signature is the same size as the key
@@ -117,6 +115,6 @@ typedef struct {
///
} WIN_CERTIFICATE_EFI_PKCS1_15;
-extern EFI_GUID gEfiCertTypeRsa2048Sha256Guid;
+extern EFI_GUID gEfiCertTypeRsa2048Sha256Guid;
#endif
diff --git a/MdePkg/Include/Ia32/Nasm.inc b/MdePkg/Include/Ia32/Nasm.inc
index 8ff51935..dbd3d7a2 100644
--- a/MdePkg/Include/Ia32/Nasm.inc
+++ b/MdePkg/Include/Ia32/Nasm.inc
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
+; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
@@ -9,30 +9,6 @@
;
;------------------------------------------------------------------------------
-%macro SAVEPREVSSP 0
- DB 0xF3, 0x0F, 0x01, 0xEA
-%endmacro
-
-%macro CLRSSBSY_EAX 0
- DB 0x67, 0xF3, 0x0F, 0xAE, 0x30
-%endmacro
-
-%macro RSTORSSP_EAX 0
- DB 0x67, 0xF3, 0x0F, 0x01, 0x28
-%endmacro
-
-%macro SETSSBSY 0
- DB 0xF3, 0x0F, 0x01, 0xE8
-%endmacro
-
-%macro READSSP_EAX 0
- DB 0xF3, 0x0F, 0x1E, 0xC8
-%endmacro
-
-%macro INCSSP_EAX 0
- DB 0xF3, 0x0F, 0xAE, 0xE8
-%endmacro
-
; NASM provides built-in macros STRUC and ENDSTRUC for structure definition.
; For example, to define a structure called mytype containing a longword,
; a word, a byte and a string of bytes, you might code
diff --git a/MdePkg/Include/Ia32/ProcessorBind.h b/MdePkg/Include/Ia32/ProcessorBind.h
index b10c641e..0c4613b5 100644
--- a/MdePkg/Include/Ia32/ProcessorBind.h
+++ b/MdePkg/Include/Ia32/ProcessorBind.h
@@ -17,39 +17,38 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// Make sure we are using the correct packing rules per EFI specification
//
-#if !defined(__GNUC__)
-#pragma pack()
+#if !defined (__GNUC__)
+ #pragma pack()
#endif
-#if defined(__INTEL_COMPILER)
+#if defined (__INTEL_COMPILER)
//
// Disable ICC's remark #869: "Parameter" was never referenced warning.
// This is legal ANSI C code so we disable the remark that is turned on with -Wall
//
-#pragma warning ( disable : 869 )
+ #pragma warning ( disable : 869 )
//
// Disable ICC's remark #1418: external function definition with no prior declaration.
// This is legal ANSI C code so we disable the remark that is turned on with /W4
//
-#pragma warning ( disable : 1418 )
+ #pragma warning ( disable : 1418 )
//
// Disable ICC's remark #1419: external declaration in primary source file
// This is legal ANSI C code so we disable the remark that is turned on with /W4
//
-#pragma warning ( disable : 1419 )
+ #pragma warning ( disable : 1419 )
//
// Disable ICC's remark #593: "Variable" was set but never used.
// This is legal ANSI C code so we disable the remark that is turned on with /W4
//
-#pragma warning ( disable : 593 )
+ #pragma warning ( disable : 593 )
#endif
-
-#if defined(_MSC_EXTENSIONS)
+#if defined (_MSC_EXTENSIONS)
//
// Disable warning that make it impossible to compile at /W4
@@ -59,168 +58,163 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// Disabling bitfield type checking warnings.
//
-#pragma warning ( disable : 4214 )
+ #pragma warning ( disable : 4214 )
//
// Disabling the unreferenced formal parameter warnings.
//
-#pragma warning ( disable : 4100 )
+ #pragma warning ( disable : 4100 )
//
// Disable slightly different base types warning as CHAR8 * can not be set
// to a constant string.
//
-#pragma warning ( disable : 4057 )
+ #pragma warning ( disable : 4057 )
//
// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning
//
-#pragma warning ( disable : 4127 )
+ #pragma warning ( disable : 4127 )
//
// This warning is caused by functions defined but not used. For precompiled header only.
//
-#pragma warning ( disable : 4505 )
+ #pragma warning ( disable : 4505 )
//
// This warning is caused by empty (after preprocessing) source file. For precompiled header only.
//
-#pragma warning ( disable : 4206 )
+ #pragma warning ( disable : 4206 )
-#if defined(_MSC_VER) && _MSC_VER >= 1800
-
-//
-// Disable these warnings for VS2013.
-//
+ #if defined (_MSC_VER) && _MSC_VER >= 1800
//
// This warning is for potentially uninitialized local variable, and it may cause false
-// positive issues in VS2013 and VS2015 build
+// positive issues in VS2015 build
//
-#pragma warning ( disable : 4701 )
+ #pragma warning ( disable : 4701 )
//
// This warning is for potentially uninitialized local pointer variable, and it may cause
-// false positive issues in VS2013 and VS2015 build
+// false positive issues in VS2015 build
//
-#pragma warning ( disable : 4703 )
+ #pragma warning ( disable : 4703 )
+
+ #endif
#endif
-#endif
+#if defined (_MSC_EXTENSIONS)
+//
+// use Microsoft C compiler dependent integer width types
+//
-#if defined(_MSC_EXTENSIONS)
-
- //
- // use Microsoft C compiler dependent integer width types
- //
-
- ///
- /// 8-byte unsigned value.
- ///
- typedef unsigned __int64 UINT64;
- ///
- /// 8-byte signed value.
- ///
- typedef __int64 INT64;
- ///
- /// 4-byte unsigned value.
- ///
- typedef unsigned __int32 UINT32;
- ///
- /// 4-byte signed value.
- ///
- typedef __int32 INT32;
- ///
- /// 2-byte unsigned value.
- ///
- typedef unsigned short UINT16;
- ///
- /// 2-byte Character. Unless otherwise specified all strings are stored in the
- /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
- ///
- typedef unsigned short CHAR16;
- ///
- /// 2-byte signed value.
- ///
- typedef short INT16;
- ///
- /// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
- /// values are undefined.
- ///
- typedef unsigned char BOOLEAN;
- ///
- /// 1-byte unsigned value.
- ///
- typedef unsigned char UINT8;
- ///
- /// 1-byte Character.
- ///
- typedef char CHAR8;
- ///
- /// 1-byte signed value.
- ///
- typedef signed char INT8;
+///
+/// 8-byte unsigned value.
+///
+typedef unsigned __int64 UINT64;
+///
+/// 8-byte signed value.
+///
+typedef __int64 INT64;
+///
+/// 4-byte unsigned value.
+///
+typedef unsigned __int32 UINT32;
+///
+/// 4-byte signed value.
+///
+typedef __int32 INT32;
+///
+/// 2-byte unsigned value.
+///
+typedef unsigned short UINT16;
+///
+/// 2-byte Character. Unless otherwise specified all strings are stored in the
+/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
+///
+typedef unsigned short CHAR16;
+///
+/// 2-byte signed value.
+///
+typedef short INT16;
+///
+/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
+/// values are undefined.
+///
+typedef unsigned char BOOLEAN;
+///
+/// 1-byte unsigned value.
+///
+typedef unsigned char UINT8;
+///
+/// 1-byte Character.
+///
+typedef char CHAR8;
+///
+/// 1-byte signed value.
+///
+typedef signed char INT8;
#else
- ///
- /// 8-byte unsigned value.
- ///
- typedef unsigned long long UINT64;
- ///
- /// 8-byte signed value.
- ///
- typedef long long INT64;
- ///
- /// 4-byte unsigned value.
- ///
- typedef unsigned int UINT32;
- ///
- /// 4-byte signed value.
- ///
- typedef int INT32;
- ///
- /// 2-byte unsigned value.
- ///
- typedef unsigned short UINT16;
- ///
- /// 2-byte Character. Unless otherwise specified all strings are stored in the
- /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
- ///
- typedef unsigned short CHAR16;
- ///
- /// 2-byte signed value.
- ///
- typedef short INT16;
- ///
- /// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
- /// values are undefined.
- ///
- typedef unsigned char BOOLEAN;
- ///
- /// 1-byte unsigned value.
- ///
- typedef unsigned char UINT8;
- ///
- /// 1-byte Character
- ///
- typedef char CHAR8;
- ///
- /// 1-byte signed value
- ///
- typedef signed char INT8;
+///
+/// 8-byte unsigned value.
+///
+typedef unsigned long long UINT64;
+///
+/// 8-byte signed value.
+///
+typedef long long INT64;
+///
+/// 4-byte unsigned value.
+///
+typedef unsigned int UINT32;
+///
+/// 4-byte signed value.
+///
+typedef int INT32;
+///
+/// 2-byte unsigned value.
+///
+typedef unsigned short UINT16;
+///
+/// 2-byte Character. Unless otherwise specified all strings are stored in the
+/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
+///
+typedef unsigned short CHAR16;
+///
+/// 2-byte signed value.
+///
+typedef short INT16;
+///
+/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
+/// values are undefined.
+///
+typedef unsigned char BOOLEAN;
+///
+/// 1-byte unsigned value.
+///
+typedef unsigned char UINT8;
+///
+/// 1-byte Character
+///
+typedef char CHAR8;
+///
+/// 1-byte signed value
+///
+typedef signed char INT8;
#endif
///
/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions;
/// 8 bytes on supported 64-bit processor instructions.)
///
-typedef UINT32 UINTN;
+typedef UINT32 UINTN;
///
/// Signed value of native width. (4 bytes on supported 32-bit processor instructions;
/// 8 bytes on supported 64-bit processor instructions.)
///
-typedef INT32 INTN;
+typedef INT32 INTN;
//
// Processor specific defines
@@ -229,7 +223,7 @@ typedef INT32 INTN;
///
/// A value of native width with the highest bit set.
///
-#define MAX_BIT 0x80000000
+#define MAX_BIT 0x80000000
///
/// A value of native width with the two highest bits set.
///
@@ -238,12 +232,12 @@ typedef INT32 INTN;
///
/// Maximum legal IA-32 address.
///
-#define MAX_ADDRESS 0xFFFFFFFF
+#define MAX_ADDRESS 0xFFFFFFFF
///
/// Maximum usable address at boot time
///
-#define MAX_ALLOC_ADDRESS MAX_ADDRESS
+#define MAX_ALLOC_ADDRESS MAX_ADDRESS
///
/// Maximum legal IA-32 INTN and UINTN values.
@@ -254,18 +248,18 @@ typedef INT32 INTN;
///
/// Minimum legal IA-32 INTN value.
///
-#define MIN_INTN (((INTN)-2147483647) - 1)
+#define MIN_INTN (((INTN)-2147483647) - 1)
///
/// The stack alignment required for IA-32.
///
-#define CPU_STACK_ALIGNMENT sizeof(UINTN)
+#define CPU_STACK_ALIGNMENT sizeof(UINTN)
///
/// Page allocation granularity for IA-32.
///
-#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
-#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)
+#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
+#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)
//
// Modifier to ensure that all protocol member functions and EFI intrinsics
@@ -273,33 +267,33 @@ typedef INT32 INTN;
// EFI intrinsics are required to modify their member functions with EFIAPI.
//
#ifdef EFIAPI
- ///
- /// If EFIAPI is already defined, then we use that definition.
- ///
-#elif defined(_MSC_EXTENSIONS)
- ///
- /// Microsoft* compiler specific method for EFIAPI calling convention.
- ///
- #define EFIAPI __cdecl
-#elif defined(__GNUC__) || defined(__clang__)
- ///
- /// GCC specific method for EFIAPI calling convention.
- ///
- #define EFIAPI __attribute__((cdecl))
+///
+/// If EFIAPI is already defined, then we use that definition.
+///
+#elif defined (_MSC_EXTENSIONS)
+///
+/// Microsoft* compiler specific method for EFIAPI calling convention.
+///
+#define EFIAPI __cdecl
+#elif defined (__GNUC__) || defined (__clang__)
+///
+/// GCC specific method for EFIAPI calling convention.
+///
+#define EFIAPI __attribute__((cdecl))
#else
- ///
- /// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI
- /// is the standard.
- ///
- #define EFIAPI
+///
+/// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI
+/// is the standard.
+///
+#define EFIAPI
#endif
-#if defined(__GNUC__) || defined(__clang__)
- ///
- /// For GNU assembly code, .global or .globl can declare global symbols.
- /// Define this macro to unify the usage.
- ///
- #define ASM_GLOBAL .globl
+#if defined (__GNUC__) || defined (__clang__)
+///
+/// For GNU assembly code, .global or .globl can declare global symbols.
+/// Define this macro to unify the usage.
+///
+#define ASM_GLOBAL .globl
#endif
/**
@@ -312,11 +306,10 @@ typedef INT32 INTN;
@return The pointer to the first instruction of a function given a function pointer.
**/
-#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
+#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
#ifndef __USER_LABEL_PREFIX__
-#define __USER_LABEL_PREFIX__ _
+#define __USER_LABEL_PREFIX__ _
#endif
#endif
-
diff --git a/MdePkg/Include/IndustryStandard/Acpi.h b/MdePkg/Include/IndustryStandard/Acpi.h
index 929d259c..718b3934 100644
--- a/MdePkg/Include/IndustryStandard/Acpi.h
+++ b/MdePkg/Include/IndustryStandard/Acpi.h
@@ -4,6 +4,7 @@
Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
Copyright (c) 2019 - 2021, ARM Ltd. All rights reserved.
+ Copyright (c) 2023, Loongson Technology Corporation Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -11,6 +12,6 @@
#ifndef _ACPI_H_
#define _ACPI_H_
-#include
+#include
#endif
diff --git a/MdePkg/Include/IndustryStandard/Acpi10.h b/MdePkg/Include/IndustryStandard/Acpi10.h
index 7a09adc2..fb920d8b 100644
--- a/MdePkg/Include/IndustryStandard/Acpi10.h
+++ b/MdePkg/Include/IndustryStandard/Acpi10.h
@@ -16,8 +16,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
/// excluding the RSD PTR structure.
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
+ UINT32 Signature;
+ UINT32 Length;
} EFI_ACPI_COMMON_HEADER;
#pragma pack(1)
@@ -25,84 +25,84 @@ typedef struct {
/// The common ACPI description table header. This structure prefaces most ACPI tables.
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
- UINT8 Revision;
- UINT8 Checksum;
- UINT8 OemId[6];
- UINT64 OemTableId;
- UINT32 OemRevision;
- UINT32 CreatorId;
- UINT32 CreatorRevision;
+ UINT32 Signature;
+ UINT32 Length;
+ UINT8 Revision;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT64 OemTableId;
+ UINT32 OemRevision;
+ UINT32 CreatorId;
+ UINT32 CreatorRevision;
} EFI_ACPI_DESCRIPTION_HEADER;
#pragma pack()
//
// Define for Descriptor
//
-#define ACPI_SMALL_ITEM_FLAG 0x00
-#define ACPI_LARGE_ITEM_FLAG 0x01
+#define ACPI_SMALL_ITEM_FLAG 0x00
+#define ACPI_LARGE_ITEM_FLAG 0x01
//
// Small Item Descriptor Name
//
-#define ACPI_SMALL_IRQ_DESCRIPTOR_NAME 0x04
-#define ACPI_SMALL_DMA_DESCRIPTOR_NAME 0x05
-#define ACPI_SMALL_START_DEPENDENT_DESCRIPTOR_NAME 0x06
-#define ACPI_SMALL_END_DEPENDENT_DESCRIPTOR_NAME 0x07
-#define ACPI_SMALL_IO_PORT_DESCRIPTOR_NAME 0x08
-#define ACPI_SMALL_FIXED_IO_PORT_DESCRIPTOR_NAME 0x09
-#define ACPI_SMALL_VENDOR_DEFINED_DESCRIPTOR_NAME 0x0E
-#define ACPI_SMALL_END_TAG_DESCRIPTOR_NAME 0x0F
+#define ACPI_SMALL_IRQ_DESCRIPTOR_NAME 0x04
+#define ACPI_SMALL_DMA_DESCRIPTOR_NAME 0x05
+#define ACPI_SMALL_START_DEPENDENT_DESCRIPTOR_NAME 0x06
+#define ACPI_SMALL_END_DEPENDENT_DESCRIPTOR_NAME 0x07
+#define ACPI_SMALL_IO_PORT_DESCRIPTOR_NAME 0x08
+#define ACPI_SMALL_FIXED_IO_PORT_DESCRIPTOR_NAME 0x09
+#define ACPI_SMALL_VENDOR_DEFINED_DESCRIPTOR_NAME 0x0E
+#define ACPI_SMALL_END_TAG_DESCRIPTOR_NAME 0x0F
//
// Large Item Descriptor Name
//
-#define ACPI_LARGE_24_BIT_MEMORY_RANGE_DESCRIPTOR_NAME 0x01
-#define ACPI_LARGE_VENDOR_DEFINED_DESCRIPTOR_NAME 0x04
-#define ACPI_LARGE_32_BIT_MEMORY_RANGE_DESCRIPTOR_NAME 0x05
-#define ACPI_LARGE_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR_NAME 0x06
-#define ACPI_LARGE_DWORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x07
-#define ACPI_LARGE_WORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x08
-#define ACPI_LARGE_EXTENDED_IRQ_DESCRIPTOR_NAME 0x09
-#define ACPI_LARGE_QWORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x0A
+#define ACPI_LARGE_24_BIT_MEMORY_RANGE_DESCRIPTOR_NAME 0x01
+#define ACPI_LARGE_VENDOR_DEFINED_DESCRIPTOR_NAME 0x04
+#define ACPI_LARGE_32_BIT_MEMORY_RANGE_DESCRIPTOR_NAME 0x05
+#define ACPI_LARGE_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR_NAME 0x06
+#define ACPI_LARGE_DWORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x07
+#define ACPI_LARGE_WORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x08
+#define ACPI_LARGE_EXTENDED_IRQ_DESCRIPTOR_NAME 0x09
+#define ACPI_LARGE_QWORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x0A
//
// Small Item Descriptor Value
//
-#define ACPI_IRQ_NOFLAG_DESCRIPTOR 0x22
-#define ACPI_IRQ_DESCRIPTOR 0x23
-#define ACPI_DMA_DESCRIPTOR 0x2A
-#define ACPI_START_DEPENDENT_DESCRIPTOR 0x30
-#define ACPI_START_DEPENDENT_EX_DESCRIPTOR 0x31
-#define ACPI_END_DEPENDENT_DESCRIPTOR 0x38
-#define ACPI_IO_PORT_DESCRIPTOR 0x47
-#define ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR 0x4B
-#define ACPI_END_TAG_DESCRIPTOR 0x79
+#define ACPI_IRQ_NOFLAG_DESCRIPTOR 0x22
+#define ACPI_IRQ_DESCRIPTOR 0x23
+#define ACPI_DMA_DESCRIPTOR 0x2A
+#define ACPI_START_DEPENDENT_DESCRIPTOR 0x30
+#define ACPI_START_DEPENDENT_EX_DESCRIPTOR 0x31
+#define ACPI_END_DEPENDENT_DESCRIPTOR 0x38
+#define ACPI_IO_PORT_DESCRIPTOR 0x47
+#define ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR 0x4B
+#define ACPI_END_TAG_DESCRIPTOR 0x79
//
// Large Item Descriptor Value
//
-#define ACPI_24_BIT_MEMORY_RANGE_DESCRIPTOR 0x81
-#define ACPI_32_BIT_MEMORY_RANGE_DESCRIPTOR 0x85
-#define ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR 0x86
-#define ACPI_DWORD_ADDRESS_SPACE_DESCRIPTOR 0x87
-#define ACPI_WORD_ADDRESS_SPACE_DESCRIPTOR 0x88
-#define ACPI_EXTENDED_INTERRUPT_DESCRIPTOR 0x89
-#define ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR 0x8A
-#define ACPI_ADDRESS_SPACE_DESCRIPTOR 0x8A
+#define ACPI_24_BIT_MEMORY_RANGE_DESCRIPTOR 0x81
+#define ACPI_32_BIT_MEMORY_RANGE_DESCRIPTOR 0x85
+#define ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR 0x86
+#define ACPI_DWORD_ADDRESS_SPACE_DESCRIPTOR 0x87
+#define ACPI_WORD_ADDRESS_SPACE_DESCRIPTOR 0x88
+#define ACPI_EXTENDED_INTERRUPT_DESCRIPTOR 0x89
+#define ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR 0x8A
+#define ACPI_ADDRESS_SPACE_DESCRIPTOR 0x8A
//
// Resource Type
//
-#define ACPI_ADDRESS_SPACE_TYPE_MEM 0x00
-#define ACPI_ADDRESS_SPACE_TYPE_IO 0x01
-#define ACPI_ADDRESS_SPACE_TYPE_BUS 0x02
+#define ACPI_ADDRESS_SPACE_TYPE_MEM 0x00
+#define ACPI_ADDRESS_SPACE_TYPE_IO 0x01
+#define ACPI_ADDRESS_SPACE_TYPE_BUS 0x02
///
/// Power Management Timer frequency is fixed at 3.579545MHz.
///
-#define ACPI_TIMER_FREQUENCY 3579545
+#define ACPI_TIMER_FREQUENCY 3579545
//
// Ensure proper structure formats
@@ -114,83 +114,83 @@ typedef struct {
/// Address Space Descriptors.
///
typedef PACKED struct {
- UINT8 Desc;
- UINT16 Len;
- UINT8 ResType;
- UINT8 GenFlag;
- UINT8 SpecificFlag;
- UINT64 AddrSpaceGranularity;
- UINT64 AddrRangeMin;
- UINT64 AddrRangeMax;
- UINT64 AddrTranslationOffset;
- UINT64 AddrLen;
+ UINT8 Desc;
+ UINT16 Len;
+ UINT8 ResType;
+ UINT8 GenFlag;
+ UINT8 SpecificFlag;
+ UINT64 AddrSpaceGranularity;
+ UINT64 AddrRangeMin;
+ UINT64 AddrRangeMax;
+ UINT64 AddrTranslationOffset;
+ UINT64 AddrLen;
} EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR;
typedef PACKED union {
- UINT8 Byte;
+ UINT8 Byte;
PACKED struct {
- UINT8 Length : 3;
- UINT8 Name : 4;
- UINT8 Type : 1;
+ UINT8 Length : 3;
+ UINT8 Name : 4;
+ UINT8 Type : 1;
} Bits;
} ACPI_SMALL_RESOURCE_HEADER;
typedef PACKED struct {
PACKED union {
- UINT8 Byte;
+ UINT8 Byte;
PACKED struct {
- UINT8 Name : 7;
- UINT8 Type : 1;
- }Bits;
+ UINT8 Name : 7;
+ UINT8 Type : 1;
+ } Bits;
} Header;
- UINT16 Length;
+ UINT16 Length;
} ACPI_LARGE_RESOURCE_HEADER;
///
/// IRQ Descriptor.
///
typedef PACKED struct {
- ACPI_SMALL_RESOURCE_HEADER Header;
- UINT16 Mask;
+ ACPI_SMALL_RESOURCE_HEADER Header;
+ UINT16 Mask;
} EFI_ACPI_IRQ_NOFLAG_DESCRIPTOR;
///
/// IRQ Descriptor.
///
typedef PACKED struct {
- ACPI_SMALL_RESOURCE_HEADER Header;
- UINT16 Mask;
- UINT8 Information;
+ ACPI_SMALL_RESOURCE_HEADER Header;
+ UINT16 Mask;
+ UINT8 Information;
} EFI_ACPI_IRQ_DESCRIPTOR;
///
/// DMA Descriptor.
///
typedef PACKED struct {
- ACPI_SMALL_RESOURCE_HEADER Header;
- UINT8 ChannelMask;
- UINT8 Information;
+ ACPI_SMALL_RESOURCE_HEADER Header;
+ UINT8 ChannelMask;
+ UINT8 Information;
} EFI_ACPI_DMA_DESCRIPTOR;
///
/// I/O Port Descriptor
///
typedef PACKED struct {
- ACPI_SMALL_RESOURCE_HEADER Header;
- UINT8 Information;
- UINT16 BaseAddressMin;
- UINT16 BaseAddressMax;
- UINT8 Alignment;
- UINT8 Length;
+ ACPI_SMALL_RESOURCE_HEADER Header;
+ UINT8 Information;
+ UINT16 BaseAddressMin;
+ UINT16 BaseAddressMax;
+ UINT8 Alignment;
+ UINT8 Length;
} EFI_ACPI_IO_PORT_DESCRIPTOR;
///
/// Fixed Location I/O Port Descriptor.
///
typedef PACKED struct {
- ACPI_SMALL_RESOURCE_HEADER Header;
- UINT16 BaseAddress;
- UINT8 Length;
+ ACPI_SMALL_RESOURCE_HEADER Header;
+ UINT16 BaseAddress;
+ UINT8 Length;
} EFI_ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR;
///
@@ -288,17 +288,17 @@ typedef PACKED struct {
/// The End tag identifies an end of resource data.
///
typedef struct {
- UINT8 Desc;
- UINT8 Checksum;
+ UINT8 Desc;
+ UINT8 Checksum;
} EFI_ACPI_END_TAG_DESCRIPTOR;
//
// General use definitions
//
-#define EFI_ACPI_RESERVED_BYTE 0x00
-#define EFI_ACPI_RESERVED_WORD 0x0000
-#define EFI_ACPI_RESERVED_DWORD 0x00000000
-#define EFI_ACPI_RESERVED_QWORD 0x0000000000000000
+#define EFI_ACPI_RESERVED_BYTE 0x00
+#define EFI_ACPI_RESERVED_WORD 0x0000
+#define EFI_ACPI_RESERVED_DWORD 0x00000000
+#define EFI_ACPI_RESERVED_QWORD 0x0000000000000000
//
// Resource Type Specific Flags
@@ -306,86 +306,86 @@ typedef struct {
//
// Bit [0] : Write Status, _RW
//
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_WRITE (1 << 0)
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_ONLY (0 << 0)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_WRITE (1 << 0)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_ONLY (0 << 0)
//
// Bit [2:1] : Memory Attributes, _MEM
//
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_NON_CACHEABLE (0 << 1)
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE (1 << 1)
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_WRITE_COMBINING (2 << 1)
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE (3 << 1)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_NON_CACHEABLE (0 << 1)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE (1 << 1)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_WRITE_COMBINING (2 << 1)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE (3 << 1)
//
// Bit [4:3] : Memory Attributes, _MTP
//
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_MEMORY (0 << 3)
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_RESERVED (1 << 3)
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_ACPI (2 << 3)
-#define EFI_APCI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_NVS (3 << 3)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_MEMORY (0 << 3)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_RESERVED (1 << 3)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_ACPI (2 << 3)
+#define EFI_APCI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_NVS (3 << 3)
//
// Bit [5] : Memory to I/O Translation, _TTP
//
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_TRANSLATION (1 << 5)
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_STATIC (0 << 5)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_TRANSLATION (1 << 5)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_STATIC (0 << 5)
//
// IRQ Information
// Ref ACPI specification 6.4.2.1
//
-#define EFI_ACPI_IRQ_SHARABLE_MASK 0x10
-#define EFI_ACPI_IRQ_SHARABLE 0x10
+#define EFI_ACPI_IRQ_SHARABLE_MASK 0x10
+#define EFI_ACPI_IRQ_SHARABLE 0x10
-#define EFI_ACPI_IRQ_POLARITY_MASK 0x08
-#define EFI_ACPI_IRQ_HIGH_TRUE 0x00
-#define EFI_ACPI_IRQ_LOW_FALSE 0x08
+#define EFI_ACPI_IRQ_POLARITY_MASK 0x08
+#define EFI_ACPI_IRQ_HIGH_TRUE 0x00
+#define EFI_ACPI_IRQ_LOW_FALSE 0x08
-#define EFI_ACPI_IRQ_MODE 0x01
-#define EFI_ACPI_IRQ_LEVEL_TRIGGERED 0x00
-#define EFI_ACPI_IRQ_EDGE_TRIGGERED 0x01
+#define EFI_ACPI_IRQ_MODE 0x01
+#define EFI_ACPI_IRQ_LEVEL_TRIGGERED 0x00
+#define EFI_ACPI_IRQ_EDGE_TRIGGERED 0x01
//
// DMA Information
// Ref ACPI specification 6.4.2.2
//
-#define EFI_ACPI_DMA_SPEED_TYPE_MASK 0x60
-#define EFI_ACPI_DMA_SPEED_TYPE_COMPATIBILITY 0x00
-#define EFI_ACPI_DMA_SPEED_TYPE_A 0x20
-#define EFI_ACPI_DMA_SPEED_TYPE_B 0x40
-#define EFI_ACPI_DMA_SPEED_TYPE_F 0x60
+#define EFI_ACPI_DMA_SPEED_TYPE_MASK 0x60
+#define EFI_ACPI_DMA_SPEED_TYPE_COMPATIBILITY 0x00
+#define EFI_ACPI_DMA_SPEED_TYPE_A 0x20
+#define EFI_ACPI_DMA_SPEED_TYPE_B 0x40
+#define EFI_ACPI_DMA_SPEED_TYPE_F 0x60
-#define EFI_ACPI_DMA_BUS_MASTER_MASK 0x04
-#define EFI_ACPI_DMA_BUS_MASTER 0x04
+#define EFI_ACPI_DMA_BUS_MASTER_MASK 0x04
+#define EFI_ACPI_DMA_BUS_MASTER 0x04
-#define EFI_ACPI_DMA_TRANSFER_TYPE_MASK 0x03
-#define EFI_ACPI_DMA_TRANSFER_TYPE_8_BIT 0x00
-#define EFI_ACPI_DMA_TRANSFER_TYPE_8_BIT_AND_16_BIT 0x01
-#define EFI_ACPI_DMA_TRANSFER_TYPE_16_BIT 0x02
+#define EFI_ACPI_DMA_TRANSFER_TYPE_MASK 0x03
+#define EFI_ACPI_DMA_TRANSFER_TYPE_8_BIT 0x00
+#define EFI_ACPI_DMA_TRANSFER_TYPE_8_BIT_AND_16_BIT 0x01
+#define EFI_ACPI_DMA_TRANSFER_TYPE_16_BIT 0x02
//
// IO Information
// Ref ACPI specification 6.4.2.5
//
-#define EFI_ACPI_IO_DECODE_MASK 0x01
-#define EFI_ACPI_IO_DECODE_16_BIT 0x01
-#define EFI_ACPI_IO_DECODE_10_BIT 0x00
+#define EFI_ACPI_IO_DECODE_MASK 0x01
+#define EFI_ACPI_IO_DECODE_16_BIT 0x01
+#define EFI_ACPI_IO_DECODE_10_BIT 0x00
//
// Memory Information
// Ref ACPI specification 6.4.3.4
//
-#define EFI_ACPI_MEMORY_WRITE_STATUS_MASK 0x01
-#define EFI_ACPI_MEMORY_WRITABLE 0x01
-#define EFI_ACPI_MEMORY_NON_WRITABLE 0x00
+#define EFI_ACPI_MEMORY_WRITE_STATUS_MASK 0x01
+#define EFI_ACPI_MEMORY_WRITABLE 0x01
+#define EFI_ACPI_MEMORY_NON_WRITABLE 0x00
//
// Interrupt Vector Flags definitions for Extended Interrupt Descriptor
// Ref ACPI specification 6.4.3.6
//
-#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_PRODUCER_CONSUMER_MASK BIT0
-#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_MODE_MASK BIT1
-#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_POLARITY_MASK BIT2
-#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_SHARABLE_MASK BIT3
-#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_WAKE_CAPABLITY_MASK BIT4
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_PRODUCER_CONSUMER_MASK BIT0
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_MODE_MASK BIT1
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_POLARITY_MASK BIT2
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_SHARABLE_MASK BIT3
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_WAKE_CAPABLITY_MASK BIT4
//
// Ensure proper structure formats
@@ -399,11 +399,11 @@ typedef struct {
/// Root System Description Pointer Structure.
///
typedef struct {
- UINT64 Signature;
- UINT8 Checksum;
- UINT8 OemId[6];
- UINT8 Reserved;
- UINT32 RsdtAddress;
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Reserved;
+ UINT32 RsdtAddress;
} EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
//
@@ -415,52 +415,52 @@ typedef struct {
///
/// RSDT Revision (as defined in ACPI 1.0b specification).
///
-#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
///
/// Fixed ACPI Description Table Structure (FADT).
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 FirmwareCtrl;
- UINT32 Dsdt;
- UINT8 IntModel;
- UINT8 Reserved1;
- UINT16 SciInt;
- UINT32 SmiCmd;
- UINT8 AcpiEnable;
- UINT8 AcpiDisable;
- UINT8 S4BiosReq;
- UINT8 Reserved2;
- UINT32 Pm1aEvtBlk;
- UINT32 Pm1bEvtBlk;
- UINT32 Pm1aCntBlk;
- UINT32 Pm1bCntBlk;
- UINT32 Pm2CntBlk;
- UINT32 PmTmrBlk;
- UINT32 Gpe0Blk;
- UINT32 Gpe1Blk;
- UINT8 Pm1EvtLen;
- UINT8 Pm1CntLen;
- UINT8 Pm2CntLen;
- UINT8 PmTmLen;
- UINT8 Gpe0BlkLen;
- UINT8 Gpe1BlkLen;
- UINT8 Gpe1Base;
- UINT8 Reserved3;
- UINT16 PLvl2Lat;
- UINT16 PLvl3Lat;
- UINT16 FlushSize;
- UINT16 FlushStride;
- UINT8 DutyOffset;
- UINT8 DutyWidth;
- UINT8 DayAlrm;
- UINT8 MonAlrm;
- UINT8 Century;
- UINT8 Reserved4;
- UINT8 Reserved5;
- UINT8 Reserved6;
- UINT32 Flags;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 IntModel;
+ UINT8 Reserved1;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 Reserved2;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 Reserved3;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT8 Reserved4;
+ UINT8 Reserved5;
+ UINT8 Reserved6;
+ UINT32 Flags;
} EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE;
///
@@ -468,63 +468,63 @@ typedef struct {
///
#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x01
-#define EFI_ACPI_1_0_INT_MODE_DUAL_PIC 0
-#define EFI_ACPI_1_0_INT_MODE_MULTIPLE_APIC 1
+#define EFI_ACPI_1_0_INT_MODE_DUAL_PIC 0
+#define EFI_ACPI_1_0_INT_MODE_MULTIPLE_APIC 1
//
// Fixed ACPI Description Table Fixed Feature Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_1_0_WBINVD BIT0
-#define EFI_ACPI_1_0_WBINVD_FLUSH BIT1
-#define EFI_ACPI_1_0_PROC_C1 BIT2
-#define EFI_ACPI_1_0_P_LVL2_UP BIT3
-#define EFI_ACPI_1_0_PWR_BUTTON BIT4
-#define EFI_ACPI_1_0_SLP_BUTTON BIT5
-#define EFI_ACPI_1_0_FIX_RTC BIT6
-#define EFI_ACPI_1_0_RTC_S4 BIT7
-#define EFI_ACPI_1_0_TMR_VAL_EXT BIT8
-#define EFI_ACPI_1_0_DCK_CAP BIT9
+#define EFI_ACPI_1_0_WBINVD BIT0
+#define EFI_ACPI_1_0_WBINVD_FLUSH BIT1
+#define EFI_ACPI_1_0_PROC_C1 BIT2
+#define EFI_ACPI_1_0_P_LVL2_UP BIT3
+#define EFI_ACPI_1_0_PWR_BUTTON BIT4
+#define EFI_ACPI_1_0_SLP_BUTTON BIT5
+#define EFI_ACPI_1_0_FIX_RTC BIT6
+#define EFI_ACPI_1_0_RTC_S4 BIT7
+#define EFI_ACPI_1_0_TMR_VAL_EXT BIT8
+#define EFI_ACPI_1_0_DCK_CAP BIT9
///
/// Firmware ACPI Control Structure.
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
- UINT32 HardwareSignature;
- UINT32 FirmwareWakingVector;
- UINT32 GlobalLock;
- UINT32 Flags;
- UINT8 Reserved[40];
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT8 Reserved[40];
} EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
///
/// Firmware Control Structure Feature Flags.
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_1_0_S4BIOS_F BIT0
+#define EFI_ACPI_1_0_S4BIOS_F BIT0
///
/// Multiple APIC Description Table header definition. The rest of the table
/// must be defined in a platform-specific manner.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 LocalApicAddress;
- UINT32 Flags;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
///
/// MADT Revision (as defined in ACPI 1.0b specification).
///
-#define EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01
///
/// Multiple APIC Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_1_0_PCAT_COMPAT BIT0
+#define EFI_ACPI_1_0_PCAT_COMPAT BIT0
//
// Multiple APIC Description Table APIC structure types
@@ -545,71 +545,71 @@ typedef struct {
/// Processor Local APIC Structure Definition.
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT8 ApicId;
- UINT32 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 ApicId;
+ UINT32 Flags;
} EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
///
/// Local APIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_1_0_LOCAL_APIC_ENABLED BIT0
+#define EFI_ACPI_1_0_LOCAL_APIC_ENABLED BIT0
///
/// IO APIC Structure.
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 IoApicAddress;
- UINT32 SystemVectorBase;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 SystemVectorBase;
} EFI_ACPI_1_0_IO_APIC_STRUCTURE;
///
/// Interrupt Source Override Structure.
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Bus;
- UINT8 Source;
- UINT32 GlobalSystemInterruptVector;
- UINT16 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterruptVector;
+ UINT16 Flags;
} EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
///
/// Non-Maskable Interrupt Source Structure.
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT32 GlobalSystemInterruptVector;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterruptVector;
} EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
///
/// Local APIC NMI Structure.
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT16 Flags;
- UINT8 LocalApicInti;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT16 Flags;
+ UINT8 LocalApicInti;
} EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE;
///
/// Smart Battery Description Table (SBST)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 WarningEnergyLevel;
- UINT32 LowEnergyLevel;
- UINT32 CriticalEnergyLevel;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
} EFI_ACPI_1_0_SMART_BATTERY_DESCRIPTION_TABLE;
//
diff --git a/MdePkg/Include/IndustryStandard/Acpi20.h b/MdePkg/Include/IndustryStandard/Acpi20.h
index b4e19ae5..4e39452b 100644
--- a/MdePkg/Include/IndustryStandard/Acpi20.h
+++ b/MdePkg/Include/IndustryStandard/Acpi20.h
@@ -13,9 +13,9 @@
//
// Define for Descriptor
//
-#define ACPI_LARGE_GENERIC_REGISTER_DESCRIPTOR_NAME 0x02
+#define ACPI_LARGE_GENERIC_REGISTER_DESCRIPTOR_NAME 0x02
-#define ACPI_GENERIC_REGISTER_DESCRIPTOR 0x82
+#define ACPI_GENERIC_REGISTER_DESCRIPTOR 0x82
//
// Ensure proper structure formats
@@ -45,11 +45,11 @@ typedef PACKED struct {
/// ACPI 2.0 Generic Address Space definition
///
typedef struct {
- UINT8 AddressSpaceId;
- UINT8 RegisterBitWidth;
- UINT8 RegisterBitOffset;
- UINT8 Reserved;
- UINT64 Address;
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 Reserved;
+ UINT64 Address;
} EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE;
//
@@ -70,29 +70,29 @@ typedef struct {
/// Root System Description Pointer Structure
///
typedef struct {
- UINT64 Signature;
- UINT8 Checksum;
- UINT8 OemId[6];
- UINT8 Revision;
- UINT32 RsdtAddress;
- UINT32 Length;
- UINT64 XsdtAddress;
- UINT8 ExtendedChecksum;
- UINT8 Reserved[3];
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
} EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
///
/// RSD_PTR Revision (as defined in ACPI 2.0 spec.)
///
-#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02
///
/// Common table header, this prefaces all ACPI tables, including FACS, but
/// excluding the RSD PTR structure
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
+ UINT32 Signature;
+ UINT32 Length;
} EFI_ACPI_2_0_COMMON_HEADER;
//
@@ -104,7 +104,7 @@ typedef struct {
///
/// RSDT Revision (as defined in ACPI 2.0 spec.)
///
-#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
//
// Extended System Description Table
@@ -115,64 +115,64 @@ typedef struct {
///
/// XSDT Revision (as defined in ACPI 2.0 spec.)
///
-#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
///
/// Fixed ACPI Description Table Structure (FADT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 FirmwareCtrl;
- UINT32 Dsdt;
- UINT8 Reserved0;
- UINT8 PreferredPmProfile;
- UINT16 SciInt;
- UINT32 SmiCmd;
- UINT8 AcpiEnable;
- UINT8 AcpiDisable;
- UINT8 S4BiosReq;
- UINT8 PstateCnt;
- UINT32 Pm1aEvtBlk;
- UINT32 Pm1bEvtBlk;
- UINT32 Pm1aCntBlk;
- UINT32 Pm1bCntBlk;
- UINT32 Pm2CntBlk;
- UINT32 PmTmrBlk;
- UINT32 Gpe0Blk;
- UINT32 Gpe1Blk;
- UINT8 Pm1EvtLen;
- UINT8 Pm1CntLen;
- UINT8 Pm2CntLen;
- UINT8 PmTmrLen;
- UINT8 Gpe0BlkLen;
- UINT8 Gpe1BlkLen;
- UINT8 Gpe1Base;
- UINT8 CstCnt;
- UINT16 PLvl2Lat;
- UINT16 PLvl3Lat;
- UINT16 FlushSize;
- UINT16 FlushStride;
- UINT8 DutyOffset;
- UINT8 DutyWidth;
- UINT8 DayAlrm;
- UINT8 MonAlrm;
- UINT8 Century;
- UINT16 IaPcBootArch;
- UINT8 Reserved1;
- UINT32 Flags;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
- UINT8 ResetValue;
- UINT8 Reserved2[3];
- UINT64 XFirmwareCtrl;
- UINT64 XDsdt;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT8 Reserved2[3];
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
} EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE;
///
@@ -183,53 +183,53 @@ typedef struct {
//
// Fixed ACPI Description Table Preferred Power Management Profile
//
-#define EFI_ACPI_2_0_PM_PROFILE_UNSPECIFIED 0
-#define EFI_ACPI_2_0_PM_PROFILE_DESKTOP 1
-#define EFI_ACPI_2_0_PM_PROFILE_MOBILE 2
-#define EFI_ACPI_2_0_PM_PROFILE_WORKSTATION 3
-#define EFI_ACPI_2_0_PM_PROFILE_ENTERPRISE_SERVER 4
-#define EFI_ACPI_2_0_PM_PROFILE_SOHO_SERVER 5
-#define EFI_ACPI_2_0_PM_PROFILE_APPLIANCE_PC 6
+#define EFI_ACPI_2_0_PM_PROFILE_UNSPECIFIED 0
+#define EFI_ACPI_2_0_PM_PROFILE_DESKTOP 1
+#define EFI_ACPI_2_0_PM_PROFILE_MOBILE 2
+#define EFI_ACPI_2_0_PM_PROFILE_WORKSTATION 3
+#define EFI_ACPI_2_0_PM_PROFILE_ENTERPRISE_SERVER 4
+#define EFI_ACPI_2_0_PM_PROFILE_SOHO_SERVER 5
+#define EFI_ACPI_2_0_PM_PROFILE_APPLIANCE_PC 6
//
// Fixed ACPI Description Table Boot Architecture Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_2_0_LEGACY_DEVICES BIT0
-#define EFI_ACPI_2_0_8042 BIT1
+#define EFI_ACPI_2_0_LEGACY_DEVICES BIT0
+#define EFI_ACPI_2_0_8042 BIT1
//
// Fixed ACPI Description Table Fixed Feature Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_2_0_WBINVD BIT0
-#define EFI_ACPI_2_0_WBINVD_FLUSH BIT1
-#define EFI_ACPI_2_0_PROC_C1 BIT2
-#define EFI_ACPI_2_0_P_LVL2_UP BIT3
-#define EFI_ACPI_2_0_PWR_BUTTON BIT4
-#define EFI_ACPI_2_0_SLP_BUTTON BIT5
-#define EFI_ACPI_2_0_FIX_RTC BIT6
-#define EFI_ACPI_2_0_RTC_S4 BIT7
-#define EFI_ACPI_2_0_TMR_VAL_EXT BIT8
-#define EFI_ACPI_2_0_DCK_CAP BIT9
-#define EFI_ACPI_2_0_RESET_REG_SUP BIT10
-#define EFI_ACPI_2_0_SEALED_CASE BIT11
-#define EFI_ACPI_2_0_HEADLESS BIT12
-#define EFI_ACPI_2_0_CPU_SW_SLP BIT13
+#define EFI_ACPI_2_0_WBINVD BIT0
+#define EFI_ACPI_2_0_WBINVD_FLUSH BIT1
+#define EFI_ACPI_2_0_PROC_C1 BIT2
+#define EFI_ACPI_2_0_P_LVL2_UP BIT3
+#define EFI_ACPI_2_0_PWR_BUTTON BIT4
+#define EFI_ACPI_2_0_SLP_BUTTON BIT5
+#define EFI_ACPI_2_0_FIX_RTC BIT6
+#define EFI_ACPI_2_0_RTC_S4 BIT7
+#define EFI_ACPI_2_0_TMR_VAL_EXT BIT8
+#define EFI_ACPI_2_0_DCK_CAP BIT9
+#define EFI_ACPI_2_0_RESET_REG_SUP BIT10
+#define EFI_ACPI_2_0_SEALED_CASE BIT11
+#define EFI_ACPI_2_0_HEADLESS BIT12
+#define EFI_ACPI_2_0_CPU_SW_SLP BIT13
///
/// Firmware ACPI Control Structure
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
- UINT32 HardwareSignature;
- UINT32 FirmwareWakingVector;
- UINT32 GlobalLock;
- UINT32 Flags;
- UINT64 XFirmwareWakingVector;
- UINT8 Version;
- UINT8 Reserved[31];
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved[31];
} EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
///
@@ -241,28 +241,28 @@ typedef struct {
/// Firmware Control Structure Feature Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_2_0_S4BIOS_F BIT0
+#define EFI_ACPI_2_0_S4BIOS_F BIT0
///
/// Multiple APIC Description Table header definition. The rest of the table
/// must be defined in a platform specific manner.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 LocalApicAddress;
- UINT32 Flags;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
///
/// MADT Revision (as defined in ACPI 2.0 spec.)
///
-#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01
///
/// Multiple APIC Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_2_0_PCAT_COMPAT BIT0
+#define EFI_ACPI_2_0_PCAT_COMPAT BIT0
//
// Multiple APIC Description Table APIC structure types
@@ -287,127 +287,127 @@ typedef struct {
/// Processor Local APIC Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT8 ApicId;
- UINT32 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 ApicId;
+ UINT32 Flags;
} EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
///
/// Local APIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED BIT0
+#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED BIT0
///
/// IO APIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 IoApicAddress;
- UINT32 GlobalSystemInterruptBase;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
} EFI_ACPI_2_0_IO_APIC_STRUCTURE;
///
/// Interrupt Source Override Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Bus;
- UINT8 Source;
- UINT32 GlobalSystemInterrupt;
- UINT16 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
} EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
///
/// Non-Maskable Interrupt Source Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT32 GlobalSystemInterrupt;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
} EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
///
/// Local APIC NMI Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT16 Flags;
- UINT8 LocalApicLint;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
} EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE;
///
/// Local APIC Address Override Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT64 LocalApicAddress;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
} EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
///
/// IO SAPIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 GlobalSystemInterruptBase;
- UINT64 IoSapicAddress;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
} EFI_ACPI_2_0_IO_SAPIC_STRUCTURE;
///
/// Local SAPIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT8 LocalSapicId;
- UINT8 LocalSapicEid;
- UINT8 Reserved[3];
- UINT32 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
} EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
///
/// Platform Interrupt Sources Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT8 InterruptType;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT8 IoSapicVector;
- UINT32 GlobalSystemInterrupt;
- UINT32 Reserved;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 Reserved;
} EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
///
/// Smart Battery Description Table (SBST)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 WarningEnergyLevel;
- UINT32 LowEnergyLevel;
- UINT32 CriticalEnergyLevel;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
} EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE;
///
/// SBST Version (as defined in ACPI 2.0 spec.)
///
-#define EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
///
/// Embedded Controller Boot Resources Table (ECDT)
@@ -415,11 +415,11 @@ typedef struct {
/// a fully qualified reference to the name space object.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcControl;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcData;
- UINT32 Uid;
- UINT8 GpeBit;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
} EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
///
diff --git a/MdePkg/Include/IndustryStandard/Acpi30.h b/MdePkg/Include/IndustryStandard/Acpi30.h
index 4ef7bec7..24c565a3 100644
--- a/MdePkg/Include/IndustryStandard/Acpi30.h
+++ b/MdePkg/Include/IndustryStandard/Acpi30.h
@@ -13,9 +13,9 @@
//
// Define for Descriptor
//
-#define ACPI_LARGE_EXTENDED_ADDRESS_SPACE_DESCRIPTOR_NAME 0x0B
+#define ACPI_LARGE_EXTENDED_ADDRESS_SPACE_DESCRIPTOR_NAME 0x0B
-#define ACPI_EXTENDED_ADDRESS_SPACE_DESCRIPTOR 0x8B
+#define ACPI_EXTENDED_ADDRESS_SPACE_DESCRIPTOR 0x8B
//
// Ensure proper structure formats
@@ -45,12 +45,12 @@ typedef PACKED struct {
//
// Memory Type Specific Flags
//
-#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_UC 0x0000000000000001
-#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WC 0x0000000000000002
-#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WT 0x0000000000000004
-#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WB 0x0000000000000008
-#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_UCE 0x0000000000000010
-#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_NV 0x0000000000008000
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_UC 0x0000000000000001
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WC 0x0000000000000002
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WT 0x0000000000000004
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WB 0x0000000000000008
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_UCE 0x0000000000000010
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_NV 0x0000000000008000
//
// Ensure proper structure formats
@@ -61,11 +61,11 @@ typedef PACKED struct {
/// ACPI 3.0 Generic Address Space definition
///
typedef struct {
- UINT8 AddressSpaceId;
- UINT8 RegisterBitWidth;
- UINT8 RegisterBitOffset;
- UINT8 AccessSize;
- UINT64 Address;
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
} EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE;
//
@@ -95,29 +95,29 @@ typedef struct {
/// Root System Description Pointer Structure
///
typedef struct {
- UINT64 Signature;
- UINT8 Checksum;
- UINT8 OemId[6];
- UINT8 Revision;
- UINT32 RsdtAddress;
- UINT32 Length;
- UINT64 XsdtAddress;
- UINT8 ExtendedChecksum;
- UINT8 Reserved[3];
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
} EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
///
/// RSD_PTR Revision (as defined in ACPI 3.0b spec.)
///
-#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 3.0b) says current value is 2
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 3.0b) says current value is 2
///
/// Common table header, this prefaces all ACPI tables, including FACS, but
/// excluding the RSD PTR structure
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
+ UINT32 Signature;
+ UINT32 Length;
} EFI_ACPI_3_0_COMMON_HEADER;
//
@@ -129,7 +129,7 @@ typedef struct {
///
/// RSDT Revision (as defined in ACPI 3.0 spec.)
///
-#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
//
// Extended System Description Table
@@ -140,64 +140,64 @@ typedef struct {
///
/// XSDT Revision (as defined in ACPI 3.0 spec.)
///
-#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
///
/// Fixed ACPI Description Table Structure (FADT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 FirmwareCtrl;
- UINT32 Dsdt;
- UINT8 Reserved0;
- UINT8 PreferredPmProfile;
- UINT16 SciInt;
- UINT32 SmiCmd;
- UINT8 AcpiEnable;
- UINT8 AcpiDisable;
- UINT8 S4BiosReq;
- UINT8 PstateCnt;
- UINT32 Pm1aEvtBlk;
- UINT32 Pm1bEvtBlk;
- UINT32 Pm1aCntBlk;
- UINT32 Pm1bCntBlk;
- UINT32 Pm2CntBlk;
- UINT32 PmTmrBlk;
- UINT32 Gpe0Blk;
- UINT32 Gpe1Blk;
- UINT8 Pm1EvtLen;
- UINT8 Pm1CntLen;
- UINT8 Pm2CntLen;
- UINT8 PmTmrLen;
- UINT8 Gpe0BlkLen;
- UINT8 Gpe1BlkLen;
- UINT8 Gpe1Base;
- UINT8 CstCnt;
- UINT16 PLvl2Lat;
- UINT16 PLvl3Lat;
- UINT16 FlushSize;
- UINT16 FlushStride;
- UINT8 DutyOffset;
- UINT8 DutyWidth;
- UINT8 DayAlrm;
- UINT8 MonAlrm;
- UINT8 Century;
- UINT16 IaPcBootArch;
- UINT8 Reserved1;
- UINT32 Flags;
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
- UINT8 ResetValue;
- UINT8 Reserved2[3];
- UINT64 XFirmwareCtrl;
- UINT64 XDsdt;
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT8 Reserved2[3];
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
} EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE;
///
@@ -221,50 +221,50 @@ typedef struct {
// Fixed ACPI Description Table Boot Architecture Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_3_0_LEGACY_DEVICES BIT0
-#define EFI_ACPI_3_0_8042 BIT1
-#define EFI_ACPI_3_0_VGA_NOT_PRESENT BIT2
-#define EFI_ACPI_3_0_MSI_NOT_SUPPORTED BIT3
-#define EFI_ACPI_3_0_PCIE_ASPM_CONTROLS BIT4
+#define EFI_ACPI_3_0_LEGACY_DEVICES BIT0
+#define EFI_ACPI_3_0_8042 BIT1
+#define EFI_ACPI_3_0_VGA_NOT_PRESENT BIT2
+#define EFI_ACPI_3_0_MSI_NOT_SUPPORTED BIT3
+#define EFI_ACPI_3_0_PCIE_ASPM_CONTROLS BIT4
//
// Fixed ACPI Description Table Fixed Feature Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_3_0_WBINVD BIT0
-#define EFI_ACPI_3_0_WBINVD_FLUSH BIT1
-#define EFI_ACPI_3_0_PROC_C1 BIT2
-#define EFI_ACPI_3_0_P_LVL2_UP BIT3
-#define EFI_ACPI_3_0_PWR_BUTTON BIT4
-#define EFI_ACPI_3_0_SLP_BUTTON BIT5
-#define EFI_ACPI_3_0_FIX_RTC BIT6
-#define EFI_ACPI_3_0_RTC_S4 BIT7
-#define EFI_ACPI_3_0_TMR_VAL_EXT BIT8
-#define EFI_ACPI_3_0_DCK_CAP BIT9
-#define EFI_ACPI_3_0_RESET_REG_SUP BIT10
-#define EFI_ACPI_3_0_SEALED_CASE BIT11
-#define EFI_ACPI_3_0_HEADLESS BIT12
-#define EFI_ACPI_3_0_CPU_SW_SLP BIT13
-#define EFI_ACPI_3_0_PCI_EXP_WAK BIT14
-#define EFI_ACPI_3_0_USE_PLATFORM_CLOCK BIT15
-#define EFI_ACPI_3_0_S4_RTC_STS_VALID BIT16
-#define EFI_ACPI_3_0_REMOTE_POWER_ON_CAPABLE BIT17
-#define EFI_ACPI_3_0_FORCE_APIC_CLUSTER_MODEL BIT18
-#define EFI_ACPI_3_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+#define EFI_ACPI_3_0_WBINVD BIT0
+#define EFI_ACPI_3_0_WBINVD_FLUSH BIT1
+#define EFI_ACPI_3_0_PROC_C1 BIT2
+#define EFI_ACPI_3_0_P_LVL2_UP BIT3
+#define EFI_ACPI_3_0_PWR_BUTTON BIT4
+#define EFI_ACPI_3_0_SLP_BUTTON BIT5
+#define EFI_ACPI_3_0_FIX_RTC BIT6
+#define EFI_ACPI_3_0_RTC_S4 BIT7
+#define EFI_ACPI_3_0_TMR_VAL_EXT BIT8
+#define EFI_ACPI_3_0_DCK_CAP BIT9
+#define EFI_ACPI_3_0_RESET_REG_SUP BIT10
+#define EFI_ACPI_3_0_SEALED_CASE BIT11
+#define EFI_ACPI_3_0_HEADLESS BIT12
+#define EFI_ACPI_3_0_CPU_SW_SLP BIT13
+#define EFI_ACPI_3_0_PCI_EXP_WAK BIT14
+#define EFI_ACPI_3_0_USE_PLATFORM_CLOCK BIT15
+#define EFI_ACPI_3_0_S4_RTC_STS_VALID BIT16
+#define EFI_ACPI_3_0_REMOTE_POWER_ON_CAPABLE BIT17
+#define EFI_ACPI_3_0_FORCE_APIC_CLUSTER_MODEL BIT18
+#define EFI_ACPI_3_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
///
/// Firmware ACPI Control Structure
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
- UINT32 HardwareSignature;
- UINT32 FirmwareWakingVector;
- UINT32 GlobalLock;
- UINT32 Flags;
- UINT64 XFirmwareWakingVector;
- UINT8 Version;
- UINT8 Reserved[31];
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved[31];
} EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
///
@@ -276,7 +276,7 @@ typedef struct {
/// Firmware Control Structure Feature Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_3_0_S4BIOS_F BIT0
+#define EFI_ACPI_3_0_S4BIOS_F BIT0
//
// Differentiated System Description Table,
@@ -285,29 +285,29 @@ typedef struct {
// no definition needed as they are common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
//
-#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
-#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
///
/// Multiple APIC Description Table header definition. The rest of the table
/// must be defined in a platform specific manner.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 LocalApicAddress;
- UINT32 Flags;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
} EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
///
/// MADT Revision (as defined in ACPI 3.0 spec.)
///
-#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x02
///
/// Multiple APIC Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_3_0_PCAT_COMPAT BIT0
+#define EFI_ACPI_3_0_PCAT_COMPAT BIT0
//
// Multiple APIC Description Table APIC structure types
@@ -332,57 +332,57 @@ typedef struct {
/// Processor Local APIC Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT8 ApicId;
- UINT32 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 ApicId;
+ UINT32 Flags;
} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
///
/// Local APIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_3_0_LOCAL_APIC_ENABLED BIT0
+#define EFI_ACPI_3_0_LOCAL_APIC_ENABLED BIT0
///
/// IO APIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 IoApicAddress;
- UINT32 GlobalSystemInterruptBase;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
} EFI_ACPI_3_0_IO_APIC_STRUCTURE;
///
/// Interrupt Source Override Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Bus;
- UINT8 Source;
- UINT32 GlobalSystemInterrupt;
- UINT16 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
} EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
///
/// Platform Interrupt Sources Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT8 InterruptType;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT8 IoSapicVector;
- UINT32 GlobalSystemInterrupt;
- UINT32 PlatformInterruptSourceFlags;
- UINT8 CpeiProcessorOverride;
- UINT8 Reserved[31];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
} EFI_ACPI_3_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;
//
@@ -396,43 +396,43 @@ typedef struct {
/// Non-Maskable Interrupt Source Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT32 GlobalSystemInterrupt;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
} EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
///
/// Local APIC NMI Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT16 Flags;
- UINT8 LocalApicLint;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
} EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE;
///
/// Local APIC Address Override Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT64 LocalApicAddress;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
} EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
///
/// IO SAPIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 GlobalSystemInterruptBase;
- UINT64 IoSapicAddress;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
} EFI_ACPI_3_0_IO_SAPIC_STRUCTURE;
///
@@ -440,51 +440,51 @@ typedef struct {
/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT8 LocalSapicId;
- UINT8 LocalSapicEid;
- UINT8 Reserved[3];
- UINT32 Flags;
- UINT32 ACPIProcessorUIDValue;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
} EFI_ACPI_3_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
///
/// Platform Interrupt Sources Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT8 InterruptType;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT8 IoSapicVector;
- UINT32 GlobalSystemInterrupt;
- UINT32 PlatformInterruptSourceFlags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
} EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
///
/// Platform Interrupt Source Flags.
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_3_0_CPEI_PROCESSOR_OVERRIDE BIT0
+#define EFI_ACPI_3_0_CPEI_PROCESSOR_OVERRIDE BIT0
///
/// Smart Battery Description Table (SBST)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 WarningEnergyLevel;
- UINT32 LowEnergyLevel;
- UINT32 CriticalEnergyLevel;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
} EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE;
///
/// SBST Version (as defined in ACPI 3.0 spec.)
///
-#define EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
///
/// Embedded Controller Boot Resources Table (ECDT)
@@ -492,11 +492,11 @@ typedef struct {
/// a fully qualified reference to the name space object.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcControl;
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcData;
- UINT32 Uid;
- UINT8 GpeBit;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
} EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
///
@@ -509,9 +509,9 @@ typedef struct {
/// must be defined in a platform specific manner.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Reserved1; ///< Must be set to 1
- UINT64 Reserved2;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; ///< Must be set to 1
+ UINT64 Reserved2;
} EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
///
@@ -531,52 +531,52 @@ typedef struct {
/// Processor Local APIC/SAPIC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 ProximityDomain7To0;
- UINT8 ApicId;
- UINT32 Flags;
- UINT8 LocalSapicEid;
- UINT8 ProximityDomain31To8[3];
- UINT8 Reserved[4];
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT8 Reserved[4];
} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
///
/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
///
/// Memory Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 ProximityDomain;
- UINT16 Reserved1;
- UINT32 AddressBaseLow;
- UINT32 AddressBaseHigh;
- UINT32 LengthLow;
- UINT32 LengthHigh;
- UINT32 Reserved2;
- UINT32 Flags;
- UINT64 Reserved3;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
} EFI_ACPI_3_0_MEMORY_AFFINITY_STRUCTURE;
//
// Memory Flags. All other bits are reserved and must be 0.
//
-#define EFI_ACPI_3_0_MEMORY_ENABLED (1 << 0)
-#define EFI_ACPI_3_0_MEMORY_HOT_PLUGGABLE (1 << 1)
-#define EFI_ACPI_3_0_MEMORY_NONVOLATILE (1 << 2)
+#define EFI_ACPI_3_0_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_3_0_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_3_0_MEMORY_NONVOLATILE (1 << 2)
///
/// System Locality Distance Information Table (SLIT).
/// The rest of the table is a matrix.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 NumberOfSystemLocalities;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
} EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
///
diff --git a/MdePkg/Include/IndustryStandard/Acpi40.h b/MdePkg/Include/IndustryStandard/Acpi40.h
index cfd491d4..5e3493af 100644
--- a/MdePkg/Include/IndustryStandard/Acpi40.h
+++ b/MdePkg/Include/IndustryStandard/Acpi40.h
@@ -1,7 +1,7 @@
/** @file
ACPI 4.0 definitions from the ACPI Specification Revision 4.0a April 5, 2010
- Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -19,11 +19,11 @@
/// ACPI 4.0 Generic Address Space definition
///
typedef struct {
- UINT8 AddressSpaceId;
- UINT8 RegisterBitWidth;
- UINT8 RegisterBitOffset;
- UINT8 AccessSize;
- UINT64 Address;
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
} EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE;
//
@@ -53,29 +53,29 @@ typedef struct {
/// Root System Description Pointer Structure
///
typedef struct {
- UINT64 Signature;
- UINT8 Checksum;
- UINT8 OemId[6];
- UINT8 Revision;
- UINT32 RsdtAddress;
- UINT32 Length;
- UINT64 XsdtAddress;
- UINT8 ExtendedChecksum;
- UINT8 Reserved[3];
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
} EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
///
/// RSD_PTR Revision (as defined in ACPI 4.0b spec.)
///
-#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 4.0a) says current value is 2
+#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 4.0a) says current value is 2
///
/// Common table header, this prefaces all ACPI tables, including FACS, but
/// excluding the RSD PTR structure
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
+ UINT32 Signature;
+ UINT32 Length;
} EFI_ACPI_4_0_COMMON_HEADER;
//
@@ -87,7 +87,7 @@ typedef struct {
///
/// RSDT Revision (as defined in ACPI 4.0 spec.)
///
-#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
//
// Extended System Description Table
@@ -98,64 +98,64 @@ typedef struct {
///
/// XSDT Revision (as defined in ACPI 4.0 spec.)
///
-#define EFI_ACPI_4_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_4_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
///
/// Fixed ACPI Description Table Structure (FADT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 FirmwareCtrl;
- UINT32 Dsdt;
- UINT8 Reserved0;
- UINT8 PreferredPmProfile;
- UINT16 SciInt;
- UINT32 SmiCmd;
- UINT8 AcpiEnable;
- UINT8 AcpiDisable;
- UINT8 S4BiosReq;
- UINT8 PstateCnt;
- UINT32 Pm1aEvtBlk;
- UINT32 Pm1bEvtBlk;
- UINT32 Pm1aCntBlk;
- UINT32 Pm1bCntBlk;
- UINT32 Pm2CntBlk;
- UINT32 PmTmrBlk;
- UINT32 Gpe0Blk;
- UINT32 Gpe1Blk;
- UINT8 Pm1EvtLen;
- UINT8 Pm1CntLen;
- UINT8 Pm2CntLen;
- UINT8 PmTmrLen;
- UINT8 Gpe0BlkLen;
- UINT8 Gpe1BlkLen;
- UINT8 Gpe1Base;
- UINT8 CstCnt;
- UINT16 PLvl2Lat;
- UINT16 PLvl3Lat;
- UINT16 FlushSize;
- UINT16 FlushStride;
- UINT8 DutyOffset;
- UINT8 DutyWidth;
- UINT8 DayAlrm;
- UINT8 MonAlrm;
- UINT8 Century;
- UINT16 IaPcBootArch;
- UINT8 Reserved1;
- UINT32 Flags;
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
- UINT8 ResetValue;
- UINT8 Reserved2[3];
- UINT64 XFirmwareCtrl;
- UINT64 XDsdt;
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT8 Reserved2[3];
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
} EFI_ACPI_4_0_FIXED_ACPI_DESCRIPTION_TABLE;
///
@@ -179,52 +179,52 @@ typedef struct {
// Fixed ACPI Description Table Boot Architecture Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_4_0_LEGACY_DEVICES BIT0
-#define EFI_ACPI_4_0_8042 BIT1
-#define EFI_ACPI_4_0_VGA_NOT_PRESENT BIT2
-#define EFI_ACPI_4_0_MSI_NOT_SUPPORTED BIT3
-#define EFI_ACPI_4_0_PCIE_ASPM_CONTROLS BIT4
+#define EFI_ACPI_4_0_LEGACY_DEVICES BIT0
+#define EFI_ACPI_4_0_8042 BIT1
+#define EFI_ACPI_4_0_VGA_NOT_PRESENT BIT2
+#define EFI_ACPI_4_0_MSI_NOT_SUPPORTED BIT3
+#define EFI_ACPI_4_0_PCIE_ASPM_CONTROLS BIT4
//
// Fixed ACPI Description Table Fixed Feature Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_4_0_WBINVD BIT0
-#define EFI_ACPI_4_0_WBINVD_FLUSH BIT1
-#define EFI_ACPI_4_0_PROC_C1 BIT2
-#define EFI_ACPI_4_0_P_LVL2_UP BIT3
-#define EFI_ACPI_4_0_PWR_BUTTON BIT4
-#define EFI_ACPI_4_0_SLP_BUTTON BIT5
-#define EFI_ACPI_4_0_FIX_RTC BIT6
-#define EFI_ACPI_4_0_RTC_S4 BIT7
-#define EFI_ACPI_4_0_TMR_VAL_EXT BIT8
-#define EFI_ACPI_4_0_DCK_CAP BIT9
-#define EFI_ACPI_4_0_RESET_REG_SUP BIT10
-#define EFI_ACPI_4_0_SEALED_CASE BIT11
-#define EFI_ACPI_4_0_HEADLESS BIT12
-#define EFI_ACPI_4_0_CPU_SW_SLP BIT13
-#define EFI_ACPI_4_0_PCI_EXP_WAK BIT14
-#define EFI_ACPI_4_0_USE_PLATFORM_CLOCK BIT15
-#define EFI_ACPI_4_0_S4_RTC_STS_VALID BIT16
-#define EFI_ACPI_4_0_REMOTE_POWER_ON_CAPABLE BIT17
-#define EFI_ACPI_4_0_FORCE_APIC_CLUSTER_MODEL BIT18
-#define EFI_ACPI_4_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+#define EFI_ACPI_4_0_WBINVD BIT0
+#define EFI_ACPI_4_0_WBINVD_FLUSH BIT1
+#define EFI_ACPI_4_0_PROC_C1 BIT2
+#define EFI_ACPI_4_0_P_LVL2_UP BIT3
+#define EFI_ACPI_4_0_PWR_BUTTON BIT4
+#define EFI_ACPI_4_0_SLP_BUTTON BIT5
+#define EFI_ACPI_4_0_FIX_RTC BIT6
+#define EFI_ACPI_4_0_RTC_S4 BIT7
+#define EFI_ACPI_4_0_TMR_VAL_EXT BIT8
+#define EFI_ACPI_4_0_DCK_CAP BIT9
+#define EFI_ACPI_4_0_RESET_REG_SUP BIT10
+#define EFI_ACPI_4_0_SEALED_CASE BIT11
+#define EFI_ACPI_4_0_HEADLESS BIT12
+#define EFI_ACPI_4_0_CPU_SW_SLP BIT13
+#define EFI_ACPI_4_0_PCI_EXP_WAK BIT14
+#define EFI_ACPI_4_0_USE_PLATFORM_CLOCK BIT15
+#define EFI_ACPI_4_0_S4_RTC_STS_VALID BIT16
+#define EFI_ACPI_4_0_REMOTE_POWER_ON_CAPABLE BIT17
+#define EFI_ACPI_4_0_FORCE_APIC_CLUSTER_MODEL BIT18
+#define EFI_ACPI_4_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
///
/// Firmware ACPI Control Structure
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
- UINT32 HardwareSignature;
- UINT32 FirmwareWakingVector;
- UINT32 GlobalLock;
- UINT32 Flags;
- UINT64 XFirmwareWakingVector;
- UINT8 Version;
- UINT8 Reserved0[3];
- UINT32 OspmFlags;
- UINT8 Reserved1[24];
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved0[3];
+ UINT32 OspmFlags;
+ UINT8 Reserved1[24];
} EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
///
@@ -236,14 +236,14 @@ typedef struct {
/// Firmware Control Structure Feature Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_4_0_S4BIOS_F BIT0
-#define EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F BIT1
+#define EFI_ACPI_4_0_S4BIOS_F BIT0
+#define EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F BIT1
///
/// OSPM Enabled Firmware Control Structure Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_4_0_OSPM_64BIT_WAKE__F BIT0
+#define EFI_ACPI_4_0_OSPM_64BIT_WAKE__F BIT0
//
// Differentiated System Description Table,
@@ -252,29 +252,29 @@ typedef struct {
// no definition needed as they are common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
//
-#define EFI_ACPI_4_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
-#define EFI_ACPI_4_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_4_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_4_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
///
/// Multiple APIC Description Table header definition. The rest of the table
/// must be defined in a platform specific manner.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 LocalApicAddress;
- UINT32 Flags;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
} EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
///
/// MADT Revision (as defined in ACPI 4.0 spec.)
///
-#define EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03
+#define EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03
///
/// Multiple APIC Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_4_0_PCAT_COMPAT BIT0
+#define EFI_ACPI_4_0_PCAT_COMPAT BIT0
//
// Multiple APIC Description Table APIC structure types
@@ -301,57 +301,57 @@ typedef struct {
/// Processor Local APIC Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT8 ApicId;
- UINT32 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 ApicId;
+ UINT32 Flags;
} EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
///
/// Local APIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_4_0_LOCAL_APIC_ENABLED BIT0
+#define EFI_ACPI_4_0_LOCAL_APIC_ENABLED BIT0
///
/// IO APIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 IoApicAddress;
- UINT32 GlobalSystemInterruptBase;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
} EFI_ACPI_4_0_IO_APIC_STRUCTURE;
///
/// Interrupt Source Override Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Bus;
- UINT8 Source;
- UINT32 GlobalSystemInterrupt;
- UINT16 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
} EFI_ACPI_4_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
///
/// Platform Interrupt Sources Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT8 InterruptType;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT8 IoSapicVector;
- UINT32 GlobalSystemInterrupt;
- UINT32 PlatformInterruptSourceFlags;
- UINT8 CpeiProcessorOverride;
- UINT8 Reserved[31];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
} EFI_ACPI_4_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;
//
@@ -365,43 +365,43 @@ typedef struct {
/// Non-Maskable Interrupt Source Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT32 GlobalSystemInterrupt;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
} EFI_ACPI_4_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
///
/// Local APIC NMI Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT16 Flags;
- UINT8 LocalApicLint;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
} EFI_ACPI_4_0_LOCAL_APIC_NMI_STRUCTURE;
///
/// Local APIC Address Override Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT64 LocalApicAddress;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
} EFI_ACPI_4_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
///
/// IO SAPIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 GlobalSystemInterruptBase;
- UINT64 IoSapicAddress;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
} EFI_ACPI_4_0_IO_SAPIC_STRUCTURE;
///
@@ -409,75 +409,75 @@ typedef struct {
/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT8 LocalSapicId;
- UINT8 LocalSapicEid;
- UINT8 Reserved[3];
- UINT32 Flags;
- UINT32 ACPIProcessorUIDValue;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
} EFI_ACPI_4_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
///
/// Platform Interrupt Sources Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT8 InterruptType;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT8 IoSapicVector;
- UINT32 GlobalSystemInterrupt;
- UINT32 PlatformInterruptSourceFlags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
} EFI_ACPI_4_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
///
/// Platform Interrupt Source Flags.
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_4_0_CPEI_PROCESSOR_OVERRIDE BIT0
+#define EFI_ACPI_4_0_CPEI_PROCESSOR_OVERRIDE BIT0
///
/// Processor Local x2APIC Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[2];
- UINT32 X2ApicId;
- UINT32 Flags;
- UINT32 AcpiProcessorUid;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 AcpiProcessorUid;
} EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
///
/// Local x2APIC NMI Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT32 AcpiProcessorUid;
- UINT8 LocalX2ApicLint;
- UINT8 Reserved[3];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 AcpiProcessorUid;
+ UINT8 LocalX2ApicLint;
+ UINT8 Reserved[3];
} EFI_ACPI_4_0_LOCAL_X2APIC_NMI_STRUCTURE;
///
/// Smart Battery Description Table (SBST)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 WarningEnergyLevel;
- UINT32 LowEnergyLevel;
- UINT32 CriticalEnergyLevel;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
} EFI_ACPI_4_0_SMART_BATTERY_DESCRIPTION_TABLE;
///
/// SBST Version (as defined in ACPI 4.0 spec.)
///
-#define EFI_ACPI_4_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_4_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
///
/// Embedded Controller Boot Resources Table (ECDT)
@@ -485,11 +485,11 @@ typedef struct {
/// a fully qualified reference to the name space object.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE EcControl;
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE EcData;
- UINT32 Uid;
- UINT8 GpeBit;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
} EFI_ACPI_4_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
///
@@ -502,9 +502,9 @@ typedef struct {
/// must be defined in a platform specific manner.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Reserved1; ///< Must be set to 1
- UINT64 Reserved2;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; ///< Must be set to 1
+ UINT64 Reserved2;
} EFI_ACPI_4_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
///
@@ -525,57 +525,57 @@ typedef struct {
/// Processor Local APIC/SAPIC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 ProximityDomain7To0;
- UINT8 ApicId;
- UINT32 Flags;
- UINT8 LocalSapicEid;
- UINT8 ProximityDomain31To8[3];
- UINT32 ClockDomain;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT32 ClockDomain;
} EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
///
/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+#define EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
///
/// Memory Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 ProximityDomain;
- UINT16 Reserved1;
- UINT32 AddressBaseLow;
- UINT32 AddressBaseHigh;
- UINT32 LengthLow;
- UINT32 LengthHigh;
- UINT32 Reserved2;
- UINT32 Flags;
- UINT64 Reserved3;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
} EFI_ACPI_4_0_MEMORY_AFFINITY_STRUCTURE;
//
// Memory Flags. All other bits are reserved and must be 0.
//
-#define EFI_ACPI_4_0_MEMORY_ENABLED (1 << 0)
-#define EFI_ACPI_4_0_MEMORY_HOT_PLUGGABLE (1 << 1)
-#define EFI_ACPI_4_0_MEMORY_NONVOLATILE (1 << 2)
+#define EFI_ACPI_4_0_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_4_0_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_4_0_MEMORY_NONVOLATILE (1 << 2)
///
/// Processor Local x2APIC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved1[2];
- UINT32 ProximityDomain;
- UINT32 X2ApicId;
- UINT32 Flags;
- UINT32 ClockDomain;
- UINT8 Reserved2[4];
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1[2];
+ UINT32 ProximityDomain;
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+ UINT8 Reserved2[4];
} EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
///
@@ -583,8 +583,8 @@ typedef struct {
/// The rest of the table is a matrix.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 NumberOfSystemLocalities;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
} EFI_ACPI_4_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
///
@@ -596,14 +596,14 @@ typedef struct {
/// Corrected Platform Error Polling Table (CPEP)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 Reserved[8];
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[8];
} EFI_ACPI_4_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
///
/// CPEP Version (as defined in ACPI 4.0 spec.)
///
-#define EFI_ACPI_4_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+#define EFI_ACPI_4_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
//
// CPEP processor structure types.
@@ -614,82 +614,83 @@ typedef struct {
/// Corrected Platform Error Polling Processor Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT32 PollingInterval;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT32 PollingInterval;
} EFI_ACPI_4_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
///
/// Maximum System Characteristics Table (MSCT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 OffsetProxDomInfo;
- UINT32 MaximumNumberOfProximityDomains;
- UINT32 MaximumNumberOfClockDomains;
- UINT64 MaximumPhysicalAddress;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 OffsetProxDomInfo;
+ UINT32 MaximumNumberOfProximityDomains;
+ UINT32 MaximumNumberOfClockDomains;
+ UINT64 MaximumPhysicalAddress;
} EFI_ACPI_4_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
///
/// MSCT Version (as defined in ACPI 4.0 spec.)
///
-#define EFI_ACPI_4_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+#define EFI_ACPI_4_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
///
/// Maximum Proximity Domain Information Structure Definition
///
typedef struct {
- UINT8 Revision;
- UINT8 Length;
- UINT32 ProximityDomainRangeLow;
- UINT32 ProximityDomainRangeHigh;
- UINT32 MaximumProcessorCapacity;
- UINT64 MaximumMemoryCapacity;
+ UINT8 Revision;
+ UINT8 Length;
+ UINT32 ProximityDomainRangeLow;
+ UINT32 ProximityDomainRangeHigh;
+ UINT32 MaximumProcessorCapacity;
+ UINT64 MaximumMemoryCapacity;
} EFI_ACPI_4_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
///
/// Boot Error Record Table (BERT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 BootErrorRegionLength;
- UINT64 BootErrorRegion;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 BootErrorRegionLength;
+ UINT64 BootErrorRegion;
} EFI_ACPI_4_0_BOOT_ERROR_RECORD_TABLE_HEADER;
///
/// BERT Version (as defined in ACPI 4.0 spec.)
///
-#define EFI_ACPI_4_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+#define EFI_ACPI_4_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
///
/// Boot Error Region Block Status Definition
///
typedef struct {
- UINT32 UncorrectableErrorValid:1;
- UINT32 CorrectableErrorValid:1;
- UINT32 MultipleUncorrectableErrors:1;
- UINT32 MultipleCorrectableErrors:1;
- UINT32 ErrorDataEntryCount:10;
- UINT32 Reserved:18;
+ UINT32 UncorrectableErrorValid : 1;
+ UINT32 CorrectableErrorValid : 1;
+ UINT32 MultipleUncorrectableErrors : 1;
+ UINT32 MultipleCorrectableErrors : 1;
+ UINT32 ErrorDataEntryCount : 10;
+ UINT32 Reserved : 18;
} EFI_ACPI_4_0_ERROR_BLOCK_STATUS;
///
/// Boot Error Region Definition
///
typedef struct {
- EFI_ACPI_4_0_ERROR_BLOCK_STATUS BlockStatus;
- UINT32 RawDataOffset;
- UINT32 RawDataLength;
- UINT32 DataLength;
- UINT32 ErrorSeverity;
+ EFI_ACPI_4_0_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
} EFI_ACPI_4_0_BOOT_ERROR_REGION_STRUCTURE;
//
// Boot Error Severity types
//
#define EFI_ACPI_4_0_ERROR_SEVERITY_CORRECTABLE 0x00
+#define EFI_ACPI_4_0_ERROR_SEVERITY_RECOVERABLE 0x00
#define EFI_ACPI_4_0_ERROR_SEVERITY_FATAL 0x01
#define EFI_ACPI_4_0_ERROR_SEVERITY_CORRECTED 0x02
#define EFI_ACPI_4_0_ERROR_SEVERITY_NONE 0x03
@@ -698,14 +699,14 @@ typedef struct {
/// Generic Error Data Entry Definition
///
typedef struct {
- UINT8 SectionType[16];
- UINT32 ErrorSeverity;
- UINT16 Revision;
- UINT8 ValidationBits;
- UINT8 Flags;
- UINT32 ErrorDataLength;
- UINT8 FruId[16];
- UINT8 FruText[20];
+ UINT8 SectionType[16];
+ UINT32 ErrorSeverity;
+ UINT16 Revision;
+ UINT8 ValidationBits;
+ UINT8 Flags;
+ UINT32 ErrorDataLength;
+ UINT8 FruId[16];
+ UINT8 FruText[20];
} EFI_ACPI_4_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
///
@@ -717,14 +718,14 @@ typedef struct {
/// HEST - Hardware Error Source Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 ErrorSourceCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 ErrorSourceCount;
} EFI_ACPI_4_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
///
/// HEST Version (as defined in ACPI 4.0 spec.)
///
-#define EFI_ACPI_4_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+#define EFI_ACPI_4_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
//
// Error Source structure types.
@@ -740,383 +741,383 @@ typedef struct {
//
// Error Source structure flags.
//
-#define EFI_ACPI_4_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
-#define EFI_ACPI_4_0_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
+#define EFI_ACPI_4_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
+#define EFI_ACPI_4_0_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
///
/// IA-32 Architecture Machine Check Exception Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT64 GlobalCapabilityInitData;
- UINT64 GlobalControlInitData;
- UINT8 NumberOfHardwareBanks;
- UINT8 Reserved1[7];
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT64 GlobalCapabilityInitData;
+ UINT64 GlobalControlInitData;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[7];
} EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
///
/// IA-32 Architecture Machine Check Bank Structure Definition
///
typedef struct {
- UINT8 BankNumber;
- UINT8 ClearStatusOnInitialization;
- UINT8 StatusDataFormat;
- UINT8 Reserved0;
- UINT32 ControlRegisterMsrAddress;
- UINT64 ControlInitData;
- UINT32 StatusRegisterMsrAddress;
- UINT32 AddressRegisterMsrAddress;
- UINT32 MiscRegisterMsrAddress;
+ UINT8 BankNumber;
+ UINT8 ClearStatusOnInitialization;
+ UINT8 StatusDataFormat;
+ UINT8 Reserved0;
+ UINT32 ControlRegisterMsrAddress;
+ UINT64 ControlInitData;
+ UINT32 StatusRegisterMsrAddress;
+ UINT32 AddressRegisterMsrAddress;
+ UINT32 MiscRegisterMsrAddress;
} EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
///
/// IA-32 Architecture Machine Check Bank Structure MCA data format
///
-#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
-#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
-#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
+#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
+#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
+#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
//
// Hardware Error Notification types. All other values are reserved
//
-#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
-#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
-#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
-#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
-#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
+#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
+#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
+#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
+#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
+#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
///
/// Hardware Error Notification Configuration Write Enable Structure Definition
///
typedef struct {
- UINT16 Type:1;
- UINT16 PollInterval:1;
- UINT16 SwitchToPollingThresholdValue:1;
- UINT16 SwitchToPollingThresholdWindow:1;
- UINT16 ErrorThresholdValue:1;
- UINT16 ErrorThresholdWindow:1;
- UINT16 Reserved:10;
+ UINT16 Type : 1;
+ UINT16 PollInterval : 1;
+ UINT16 SwitchToPollingThresholdValue : 1;
+ UINT16 SwitchToPollingThresholdWindow : 1;
+ UINT16 ErrorThresholdValue : 1;
+ UINT16 ErrorThresholdWindow : 1;
+ UINT16 Reserved : 10;
} EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
///
/// Hardware Error Notification Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
- UINT32 PollInterval;
- UINT32 Vector;
- UINT32 SwitchToPollingThresholdValue;
- UINT32 SwitchToPollingThresholdWindow;
- UINT32 ErrorThresholdValue;
- UINT32 ErrorThresholdWindow;
+ UINT8 Type;
+ UINT8 Length;
+ EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
+ UINT32 PollInterval;
+ UINT32 Vector;
+ UINT32 SwitchToPollingThresholdValue;
+ UINT32 SwitchToPollingThresholdWindow;
+ UINT32 ErrorThresholdValue;
+ UINT32 ErrorThresholdWindow;
} EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
///
/// IA-32 Architecture Corrected Machine Check Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
- UINT8 NumberOfHardwareBanks;
- UINT8 Reserved1[3];
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
} EFI_ACPI_4_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
///
/// IA-32 Architecture NMI Error Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 MaxRawDataLength;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
} EFI_ACPI_4_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
///
/// PCI Express Root Port AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
- UINT32 RootErrorCommand;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 RootErrorCommand;
} EFI_ACPI_4_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
///
/// PCI Express Device AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
} EFI_ACPI_4_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
///
/// PCI Express Bridge AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
- UINT32 SecondaryUncorrectableErrorMask;
- UINT32 SecondaryUncorrectableErrorSeverity;
- UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 SecondaryUncorrectableErrorMask;
+ UINT32 SecondaryUncorrectableErrorSeverity;
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
} EFI_ACPI_4_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
///
/// Generic Hardware Error Source Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT16 RelatedSourceId;
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 MaxRawDataLength;
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
- EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
- UINT32 ErrorStatusBlockLength;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
} EFI_ACPI_4_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
///
/// Generic Error Status Definition
///
typedef struct {
- EFI_ACPI_4_0_ERROR_BLOCK_STATUS BlockStatus;
- UINT32 RawDataOffset;
- UINT32 RawDataLength;
- UINT32 DataLength;
- UINT32 ErrorSeverity;
+ EFI_ACPI_4_0_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
} EFI_ACPI_4_0_GENERIC_ERROR_STATUS_STRUCTURE;
///
/// ERST - Error Record Serialization Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 SerializationHeaderSize;
- UINT8 Reserved0[4];
- UINT32 InstructionEntryCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 SerializationHeaderSize;
+ UINT8 Reserved0[4];
+ UINT32 InstructionEntryCount;
} EFI_ACPI_4_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
///
/// ERST Version (as defined in ACPI 4.0 spec.)
///
-#define EFI_ACPI_4_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+#define EFI_ACPI_4_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
///
/// ERST Serialization Actions
///
-#define EFI_ACPI_4_0_ERST_BEGIN_WRITE_OPERATION 0x00
-#define EFI_ACPI_4_0_ERST_BEGIN_READ_OPERATION 0x01
-#define EFI_ACPI_4_0_ERST_BEGIN_CLEAR_OPERATION 0x02
-#define EFI_ACPI_4_0_ERST_END_OPERATION 0x03
-#define EFI_ACPI_4_0_ERST_SET_RECORD_OFFSET 0x04
-#define EFI_ACPI_4_0_ERST_EXECUTE_OPERATION 0x05
-#define EFI_ACPI_4_0_ERST_CHECK_BUSY_STATUS 0x06
-#define EFI_ACPI_4_0_ERST_GET_COMMAND_STATUS 0x07
-#define EFI_ACPI_4_0_ERST_GET_RECORD_IDENTIFIER 0x08
-#define EFI_ACPI_4_0_ERST_SET_RECORD_IDENTIFIER 0x09
-#define EFI_ACPI_4_0_ERST_GET_RECORD_COUNT 0x0A
-#define EFI_ACPI_4_0_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
-#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
-#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
-#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
+#define EFI_ACPI_4_0_ERST_BEGIN_WRITE_OPERATION 0x00
+#define EFI_ACPI_4_0_ERST_BEGIN_READ_OPERATION 0x01
+#define EFI_ACPI_4_0_ERST_BEGIN_CLEAR_OPERATION 0x02
+#define EFI_ACPI_4_0_ERST_END_OPERATION 0x03
+#define EFI_ACPI_4_0_ERST_SET_RECORD_OFFSET 0x04
+#define EFI_ACPI_4_0_ERST_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_4_0_ERST_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_4_0_ERST_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_4_0_ERST_GET_RECORD_IDENTIFIER 0x08
+#define EFI_ACPI_4_0_ERST_SET_RECORD_IDENTIFIER 0x09
+#define EFI_ACPI_4_0_ERST_GET_RECORD_COUNT 0x0A
+#define EFI_ACPI_4_0_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
+#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
+#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
+#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
///
/// ERST Action Command Status
///
-#define EFI_ACPI_4_0_EINJ_STATUS_SUCCESS 0x00
-#define EFI_ACPI_4_0_EINJ_STATUS_NOT_ENOUGH_SPACE 0x01
-#define EFI_ACPI_4_0_EINJ_STATUS_HARDWARE_NOT_AVAILABLE 0x02
-#define EFI_ACPI_4_0_EINJ_STATUS_FAILED 0x03
-#define EFI_ACPI_4_0_EINJ_STATUS_RECORD_STORE_EMPTY 0x04
-#define EFI_ACPI_4_0_EINJ_STATUS_RECORD_NOT_FOUND 0x05
+#define EFI_ACPI_4_0_EINJ_STATUS_SUCCESS 0x00
+#define EFI_ACPI_4_0_EINJ_STATUS_NOT_ENOUGH_SPACE 0x01
+#define EFI_ACPI_4_0_EINJ_STATUS_HARDWARE_NOT_AVAILABLE 0x02
+#define EFI_ACPI_4_0_EINJ_STATUS_FAILED 0x03
+#define EFI_ACPI_4_0_EINJ_STATUS_RECORD_STORE_EMPTY 0x04
+#define EFI_ACPI_4_0_EINJ_STATUS_RECORD_NOT_FOUND 0x05
///
/// ERST Serialization Instructions
///
-#define EFI_ACPI_4_0_ERST_READ_REGISTER 0x00
-#define EFI_ACPI_4_0_ERST_READ_REGISTER_VALUE 0x01
-#define EFI_ACPI_4_0_ERST_WRITE_REGISTER 0x02
-#define EFI_ACPI_4_0_ERST_WRITE_REGISTER_VALUE 0x03
-#define EFI_ACPI_4_0_ERST_NOOP 0x04
-#define EFI_ACPI_4_0_ERST_LOAD_VAR1 0x05
-#define EFI_ACPI_4_0_ERST_LOAD_VAR2 0x06
-#define EFI_ACPI_4_0_ERST_STORE_VAR1 0x07
-#define EFI_ACPI_4_0_ERST_ADD 0x08
-#define EFI_ACPI_4_0_ERST_SUBTRACT 0x09
-#define EFI_ACPI_4_0_ERST_ADD_VALUE 0x0A
-#define EFI_ACPI_4_0_ERST_SUBTRACT_VALUE 0x0B
-#define EFI_ACPI_4_0_ERST_STALL 0x0C
-#define EFI_ACPI_4_0_ERST_STALL_WHILE_TRUE 0x0D
-#define EFI_ACPI_4_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
-#define EFI_ACPI_4_0_ERST_GOTO 0x0F
-#define EFI_ACPI_4_0_ERST_SET_SRC_ADDRESS_BASE 0x10
-#define EFI_ACPI_4_0_ERST_SET_DST_ADDRESS_BASE 0x11
-#define EFI_ACPI_4_0_ERST_MOVE_DATA 0x12
+#define EFI_ACPI_4_0_ERST_READ_REGISTER 0x00
+#define EFI_ACPI_4_0_ERST_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_4_0_ERST_WRITE_REGISTER 0x02
+#define EFI_ACPI_4_0_ERST_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_4_0_ERST_NOOP 0x04
+#define EFI_ACPI_4_0_ERST_LOAD_VAR1 0x05
+#define EFI_ACPI_4_0_ERST_LOAD_VAR2 0x06
+#define EFI_ACPI_4_0_ERST_STORE_VAR1 0x07
+#define EFI_ACPI_4_0_ERST_ADD 0x08
+#define EFI_ACPI_4_0_ERST_SUBTRACT 0x09
+#define EFI_ACPI_4_0_ERST_ADD_VALUE 0x0A
+#define EFI_ACPI_4_0_ERST_SUBTRACT_VALUE 0x0B
+#define EFI_ACPI_4_0_ERST_STALL 0x0C
+#define EFI_ACPI_4_0_ERST_STALL_WHILE_TRUE 0x0D
+#define EFI_ACPI_4_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
+#define EFI_ACPI_4_0_ERST_GOTO 0x0F
+#define EFI_ACPI_4_0_ERST_SET_SRC_ADDRESS_BASE 0x10
+#define EFI_ACPI_4_0_ERST_SET_DST_ADDRESS_BASE 0x11
+#define EFI_ACPI_4_0_ERST_MOVE_DATA 0x12
///
/// ERST Instruction Flags
///
-#define EFI_ACPI_4_0_ERST_PRESERVE_REGISTER 0x01
+#define EFI_ACPI_4_0_ERST_PRESERVE_REGISTER 0x01
///
/// ERST Serialization Instruction Entry
///
typedef struct {
- UINT8 SerializationAction;
- UINT8 Instruction;
- UINT8 Flags;
- UINT8 Reserved0;
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
- UINT64 Value;
- UINT64 Mask;
+ UINT8 SerializationAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
} EFI_ACPI_4_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
///
/// EINJ - Error Injection Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 InjectionHeaderSize;
- UINT8 InjectionFlags;
- UINT8 Reserved0[3];
- UINT32 InjectionEntryCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 InjectionHeaderSize;
+ UINT8 InjectionFlags;
+ UINT8 Reserved0[3];
+ UINT32 InjectionEntryCount;
} EFI_ACPI_4_0_ERROR_INJECTION_TABLE_HEADER;
///
/// EINJ Version (as defined in ACPI 4.0 spec.)
///
-#define EFI_ACPI_4_0_ERROR_INJECTION_TABLE_REVISION 0x01
+#define EFI_ACPI_4_0_ERROR_INJECTION_TABLE_REVISION 0x01
///
/// EINJ Error Injection Actions
///
-#define EFI_ACPI_4_0_EINJ_BEGIN_INJECTION_OPERATION 0x00
-#define EFI_ACPI_4_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
-#define EFI_ACPI_4_0_EINJ_SET_ERROR_TYPE 0x02
-#define EFI_ACPI_4_0_EINJ_GET_ERROR_TYPE 0x03
-#define EFI_ACPI_4_0_EINJ_END_OPERATION 0x04
-#define EFI_ACPI_4_0_EINJ_EXECUTE_OPERATION 0x05
-#define EFI_ACPI_4_0_EINJ_CHECK_BUSY_STATUS 0x06
-#define EFI_ACPI_4_0_EINJ_GET_COMMAND_STATUS 0x07
-#define EFI_ACPI_4_0_EINJ_TRIGGER_ERROR 0xFF
+#define EFI_ACPI_4_0_EINJ_BEGIN_INJECTION_OPERATION 0x00
+#define EFI_ACPI_4_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
+#define EFI_ACPI_4_0_EINJ_SET_ERROR_TYPE 0x02
+#define EFI_ACPI_4_0_EINJ_GET_ERROR_TYPE 0x03
+#define EFI_ACPI_4_0_EINJ_END_OPERATION 0x04
+#define EFI_ACPI_4_0_EINJ_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_4_0_EINJ_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_4_0_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_4_0_EINJ_TRIGGER_ERROR 0xFF
///
/// EINJ Action Command Status
///
-#define EFI_ACPI_4_0_EINJ_STATUS_SUCCESS 0x00
-#define EFI_ACPI_4_0_EINJ_STATUS_UNKNOWN_FAILURE 0x01
-#define EFI_ACPI_4_0_EINJ_STATUS_INVALID_ACCESS 0x02
+#define EFI_ACPI_4_0_EINJ_STATUS_SUCCESS 0x00
+#define EFI_ACPI_4_0_EINJ_STATUS_UNKNOWN_FAILURE 0x01
+#define EFI_ACPI_4_0_EINJ_STATUS_INVALID_ACCESS 0x02
///
/// EINJ Error Type Definition
///
-#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
-#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
-#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
-#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
-#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
-#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
-#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
-#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
-#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
-#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
-#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
-#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
+#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
+#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
+#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
+#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
+#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
+#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
+#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
+#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
+#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
+#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
+#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
+#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
///
/// EINJ Injection Instructions
///
-#define EFI_ACPI_4_0_EINJ_READ_REGISTER 0x00
-#define EFI_ACPI_4_0_EINJ_READ_REGISTER_VALUE 0x01
-#define EFI_ACPI_4_0_EINJ_WRITE_REGISTER 0x02
-#define EFI_ACPI_4_0_EINJ_WRITE_REGISTER_VALUE 0x03
-#define EFI_ACPI_4_0_EINJ_NOOP 0x04
+#define EFI_ACPI_4_0_EINJ_READ_REGISTER 0x00
+#define EFI_ACPI_4_0_EINJ_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_4_0_EINJ_WRITE_REGISTER 0x02
+#define EFI_ACPI_4_0_EINJ_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_4_0_EINJ_NOOP 0x04
///
/// EINJ Instruction Flags
///
-#define EFI_ACPI_4_0_EINJ_PRESERVE_REGISTER 0x01
+#define EFI_ACPI_4_0_EINJ_PRESERVE_REGISTER 0x01
///
/// EINJ Injection Instruction Entry
///
typedef struct {
- UINT8 InjectionAction;
- UINT8 Instruction;
- UINT8 Flags;
- UINT8 Reserved0;
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
- UINT64 Value;
- UINT64 Mask;
+ UINT8 InjectionAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
} EFI_ACPI_4_0_EINJ_INJECTION_INSTRUCTION_ENTRY;
///
/// EINJ Trigger Action Table
///
typedef struct {
- UINT32 HeaderSize;
- UINT32 Revision;
- UINT32 TableSize;
- UINT32 EntryCount;
+ UINT32 HeaderSize;
+ UINT32 Revision;
+ UINT32 TableSize;
+ UINT32 EntryCount;
} EFI_ACPI_4_0_EINJ_TRIGGER_ACTION_TABLE;
//
diff --git a/MdePkg/Include/IndustryStandard/Acpi50.h b/MdePkg/Include/IndustryStandard/Acpi50.h
index 74795fcb..e02daf64 100644
--- a/MdePkg/Include/IndustryStandard/Acpi50.h
+++ b/MdePkg/Include/IndustryStandard/Acpi50.h
@@ -2,7 +2,7 @@
ACPI 5.0 definitions from the ACPI Specification Revision 5.0a November 13, 2013.
Copyright (c) 2014 Hewlett-Packard Development Company, L.P.
- Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2011 - 2022, Intel Corporation. All rights reserved.
Copyright (c) 2020, ARM Ltd. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -15,13 +15,13 @@
//
// Define for Descriptor
//
-#define ACPI_SMALL_FIXED_DMA_DESCRIPTOR_NAME 0x0A
-#define ACPI_LARGE_GPIO_CONNECTION_DESCRIPTOR_NAME 0x0C
-#define ACPI_LARGE_GENERIC_SERIAL_BUS_CONNECTION_DESCRIPTOR_NAME 0x0E
+#define ACPI_SMALL_FIXED_DMA_DESCRIPTOR_NAME 0x0A
+#define ACPI_LARGE_GPIO_CONNECTION_DESCRIPTOR_NAME 0x0C
+#define ACPI_LARGE_GENERIC_SERIAL_BUS_CONNECTION_DESCRIPTOR_NAME 0x0E
-#define ACPI_FIXED_DMA_DESCRIPTOR 0x55
-#define ACPI_GPIO_CONNECTION_DESCRIPTOR 0x8C
-#define ACPI_GENERIC_SERIAL_BUS_CONNECTION_DESCRIPTOR 0x8E
+#define ACPI_FIXED_DMA_DESCRIPTOR 0x55
+#define ACPI_GPIO_CONNECTION_DESCRIPTOR 0x8C
+#define ACPI_GENERIC_SERIAL_BUS_CONNECTION_DESCRIPTOR 0x8E
#pragma pack(1)
@@ -29,10 +29,10 @@
/// Generic DMA Descriptor.
///
typedef PACKED struct {
- ACPI_SMALL_RESOURCE_HEADER Header;
- UINT16 DmaRequestLine;
- UINT16 DmaChannel;
- UINT8 DmaTransferWidth;
+ ACPI_SMALL_RESOURCE_HEADER Header;
+ UINT16 DmaRequestLine;
+ UINT16 DmaChannel;
+ UINT8 DmaTransferWidth;
} EFI_ACPI_FIXED_DMA_DESCRIPTOR;
///
@@ -54,8 +54,8 @@ typedef PACKED struct {
UINT16 VendorDataLength;
} EFI_ACPI_GPIO_CONNECTION_DESCRIPTOR;
-#define EFI_ACPI_GPIO_CONNECTION_TYPE_INTERRUPT 0x0
-#define EFI_ACPI_GPIO_CONNECTION_TYPE_IO 0x1
+#define EFI_ACPI_GPIO_CONNECTION_TYPE_INTERRUPT 0x0
+#define EFI_ACPI_GPIO_CONNECTION_TYPE_IO 0x1
///
/// Serial Bus Resource Descriptor (Generic)
@@ -69,7 +69,7 @@ typedef PACKED struct {
UINT16 TypeSpecificFlags;
UINT8 TypeSpecificRevisionId;
UINT16 TypeDataLength;
-// Type specific data
+ // Type specific data
} EFI_ACPI_SERIAL_BUS_RESOURCE_DESCRIPTOR;
#define EFI_ACPI_SERIAL_BUS_RESOURCE_TYPE_I2C 0x1
@@ -141,21 +141,21 @@ typedef PACKED struct {
/// ACPI 5.0 Generic Address Space definition
///
typedef struct {
- UINT8 AddressSpaceId;
- UINT8 RegisterBitWidth;
- UINT8 RegisterBitOffset;
- UINT8 AccessSize;
- UINT64 Address;
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
} EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE;
//
// Generic Address Space Address IDs
//
-#define EFI_ACPI_5_0_SYSTEM_MEMORY 0
-#define EFI_ACPI_5_0_SYSTEM_IO 1
-#define EFI_ACPI_5_0_PCI_CONFIGURATION_SPACE 2
-#define EFI_ACPI_5_0_EMBEDDED_CONTROLLER 3
-#define EFI_ACPI_5_0_SMBUS 4
+#define EFI_ACPI_5_0_SYSTEM_MEMORY 0
+#define EFI_ACPI_5_0_SYSTEM_IO 1
+#define EFI_ACPI_5_0_PCI_CONFIGURATION_SPACE 2
+#define EFI_ACPI_5_0_EMBEDDED_CONTROLLER 3
+#define EFI_ACPI_5_0_SMBUS 4
#define EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL 0x0A
#define EFI_ACPI_5_0_FUNCTIONAL_FIXED_HARDWARE 0x7F
@@ -176,29 +176,29 @@ typedef struct {
/// Root System Description Pointer Structure
///
typedef struct {
- UINT64 Signature;
- UINT8 Checksum;
- UINT8 OemId[6];
- UINT8 Revision;
- UINT32 RsdtAddress;
- UINT32 Length;
- UINT64 XsdtAddress;
- UINT8 ExtendedChecksum;
- UINT8 Reserved[3];
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
} EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
///
/// RSD_PTR Revision (as defined in ACPI 5.0 spec.)
///
-#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 5.0) says current value is 2
+#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 5.0) says current value is 2
///
/// Common table header, this prefaces all ACPI tables, including FACS, but
/// excluding the RSD PTR structure
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
+ UINT32 Signature;
+ UINT32 Length;
} EFI_ACPI_5_0_COMMON_HEADER;
//
@@ -210,7 +210,7 @@ typedef struct {
///
/// RSDT Revision (as defined in ACPI 5.0 spec.)
///
-#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
//
// Extended System Description Table
@@ -221,66 +221,66 @@ typedef struct {
///
/// XSDT Revision (as defined in ACPI 5.0 spec.)
///
-#define EFI_ACPI_5_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_5_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
///
/// Fixed ACPI Description Table Structure (FADT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 FirmwareCtrl;
- UINT32 Dsdt;
- UINT8 Reserved0;
- UINT8 PreferredPmProfile;
- UINT16 SciInt;
- UINT32 SmiCmd;
- UINT8 AcpiEnable;
- UINT8 AcpiDisable;
- UINT8 S4BiosReq;
- UINT8 PstateCnt;
- UINT32 Pm1aEvtBlk;
- UINT32 Pm1bEvtBlk;
- UINT32 Pm1aCntBlk;
- UINT32 Pm1bCntBlk;
- UINT32 Pm2CntBlk;
- UINT32 PmTmrBlk;
- UINT32 Gpe0Blk;
- UINT32 Gpe1Blk;
- UINT8 Pm1EvtLen;
- UINT8 Pm1CntLen;
- UINT8 Pm2CntLen;
- UINT8 PmTmrLen;
- UINT8 Gpe0BlkLen;
- UINT8 Gpe1BlkLen;
- UINT8 Gpe1Base;
- UINT8 CstCnt;
- UINT16 PLvl2Lat;
- UINT16 PLvl3Lat;
- UINT16 FlushSize;
- UINT16 FlushStride;
- UINT8 DutyOffset;
- UINT8 DutyWidth;
- UINT8 DayAlrm;
- UINT8 MonAlrm;
- UINT8 Century;
- UINT16 IaPcBootArch;
- UINT8 Reserved1;
- UINT32 Flags;
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
- UINT8 ResetValue;
- UINT8 Reserved2[3];
- UINT64 XFirmwareCtrl;
- UINT64 XDsdt;
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT8 Reserved2[3];
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
} EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE;
///
@@ -305,55 +305,55 @@ typedef struct {
// Fixed ACPI Description Table Boot Architecture Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_5_0_LEGACY_DEVICES BIT0
-#define EFI_ACPI_5_0_8042 BIT1
-#define EFI_ACPI_5_0_VGA_NOT_PRESENT BIT2
-#define EFI_ACPI_5_0_MSI_NOT_SUPPORTED BIT3
-#define EFI_ACPI_5_0_PCIE_ASPM_CONTROLS BIT4
-#define EFI_ACPI_5_0_CMOS_RTC_NOT_PRESENT BIT5
+#define EFI_ACPI_5_0_LEGACY_DEVICES BIT0
+#define EFI_ACPI_5_0_8042 BIT1
+#define EFI_ACPI_5_0_VGA_NOT_PRESENT BIT2
+#define EFI_ACPI_5_0_MSI_NOT_SUPPORTED BIT3
+#define EFI_ACPI_5_0_PCIE_ASPM_CONTROLS BIT4
+#define EFI_ACPI_5_0_CMOS_RTC_NOT_PRESENT BIT5
//
// Fixed ACPI Description Table Fixed Feature Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_5_0_WBINVD BIT0
-#define EFI_ACPI_5_0_WBINVD_FLUSH BIT1
-#define EFI_ACPI_5_0_PROC_C1 BIT2
-#define EFI_ACPI_5_0_P_LVL2_UP BIT3
-#define EFI_ACPI_5_0_PWR_BUTTON BIT4
-#define EFI_ACPI_5_0_SLP_BUTTON BIT5
-#define EFI_ACPI_5_0_FIX_RTC BIT6
-#define EFI_ACPI_5_0_RTC_S4 BIT7
-#define EFI_ACPI_5_0_TMR_VAL_EXT BIT8
-#define EFI_ACPI_5_0_DCK_CAP BIT9
-#define EFI_ACPI_5_0_RESET_REG_SUP BIT10
-#define EFI_ACPI_5_0_SEALED_CASE BIT11
-#define EFI_ACPI_5_0_HEADLESS BIT12
-#define EFI_ACPI_5_0_CPU_SW_SLP BIT13
-#define EFI_ACPI_5_0_PCI_EXP_WAK BIT14
-#define EFI_ACPI_5_0_USE_PLATFORM_CLOCK BIT15
-#define EFI_ACPI_5_0_S4_RTC_STS_VALID BIT16
-#define EFI_ACPI_5_0_REMOTE_POWER_ON_CAPABLE BIT17
-#define EFI_ACPI_5_0_FORCE_APIC_CLUSTER_MODEL BIT18
-#define EFI_ACPI_5_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
-#define EFI_ACPI_5_0_HW_REDUCED_ACPI BIT20
-#define EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE BIT21
+#define EFI_ACPI_5_0_WBINVD BIT0
+#define EFI_ACPI_5_0_WBINVD_FLUSH BIT1
+#define EFI_ACPI_5_0_PROC_C1 BIT2
+#define EFI_ACPI_5_0_P_LVL2_UP BIT3
+#define EFI_ACPI_5_0_PWR_BUTTON BIT4
+#define EFI_ACPI_5_0_SLP_BUTTON BIT5
+#define EFI_ACPI_5_0_FIX_RTC BIT6
+#define EFI_ACPI_5_0_RTC_S4 BIT7
+#define EFI_ACPI_5_0_TMR_VAL_EXT BIT8
+#define EFI_ACPI_5_0_DCK_CAP BIT9
+#define EFI_ACPI_5_0_RESET_REG_SUP BIT10
+#define EFI_ACPI_5_0_SEALED_CASE BIT11
+#define EFI_ACPI_5_0_HEADLESS BIT12
+#define EFI_ACPI_5_0_CPU_SW_SLP BIT13
+#define EFI_ACPI_5_0_PCI_EXP_WAK BIT14
+#define EFI_ACPI_5_0_USE_PLATFORM_CLOCK BIT15
+#define EFI_ACPI_5_0_S4_RTC_STS_VALID BIT16
+#define EFI_ACPI_5_0_REMOTE_POWER_ON_CAPABLE BIT17
+#define EFI_ACPI_5_0_FORCE_APIC_CLUSTER_MODEL BIT18
+#define EFI_ACPI_5_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+#define EFI_ACPI_5_0_HW_REDUCED_ACPI BIT20
+#define EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE BIT21
///
/// Firmware ACPI Control Structure
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
- UINT32 HardwareSignature;
- UINT32 FirmwareWakingVector;
- UINT32 GlobalLock;
- UINT32 Flags;
- UINT64 XFirmwareWakingVector;
- UINT8 Version;
- UINT8 Reserved0[3];
- UINT32 OspmFlags;
- UINT8 Reserved1[24];
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved0[3];
+ UINT32 OspmFlags;
+ UINT8 Reserved1[24];
} EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
///
@@ -365,14 +365,14 @@ typedef struct {
/// Firmware Control Structure Feature Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_5_0_S4BIOS_F BIT0
-#define EFI_ACPI_5_0_64BIT_WAKE_SUPPORTED_F BIT1
+#define EFI_ACPI_5_0_S4BIOS_F BIT0
+#define EFI_ACPI_5_0_64BIT_WAKE_SUPPORTED_F BIT1
///
/// OSPM Enabled Firmware Control Structure Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_5_0_OSPM_64BIT_WAKE_F BIT0
+#define EFI_ACPI_5_0_OSPM_64BIT_WAKE_F BIT0
//
// Differentiated System Description Table,
@@ -381,29 +381,29 @@ typedef struct {
// no definition needed as they are common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
//
-#define EFI_ACPI_5_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
-#define EFI_ACPI_5_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_5_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_5_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
///
/// Multiple APIC Description Table header definition. The rest of the table
/// must be defined in a platform specific manner.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 LocalApicAddress;
- UINT32 Flags;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
} EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
///
/// MADT Revision (as defined in ACPI 5.0 spec.)
///
-#define EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03
+#define EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03
///
/// Multiple APIC Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_5_0_PCAT_COMPAT BIT0
+#define EFI_ACPI_5_0_PCAT_COMPAT BIT0
//
// Multiple APIC Description Table APIC structure types
@@ -432,57 +432,57 @@ typedef struct {
/// Processor Local APIC Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT8 ApicId;
- UINT32 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 ApicId;
+ UINT32 Flags;
} EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
///
/// Local APIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_5_0_LOCAL_APIC_ENABLED BIT0
+#define EFI_ACPI_5_0_LOCAL_APIC_ENABLED BIT0
///
/// IO APIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 IoApicAddress;
- UINT32 GlobalSystemInterruptBase;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
} EFI_ACPI_5_0_IO_APIC_STRUCTURE;
///
/// Interrupt Source Override Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Bus;
- UINT8 Source;
- UINT32 GlobalSystemInterrupt;
- UINT16 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
} EFI_ACPI_5_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
///
/// Platform Interrupt Sources Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT8 InterruptType;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT8 IoSapicVector;
- UINT32 GlobalSystemInterrupt;
- UINT32 PlatformInterruptSourceFlags;
- UINT8 CpeiProcessorOverride;
- UINT8 Reserved[31];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
} EFI_ACPI_5_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;
//
@@ -496,43 +496,43 @@ typedef struct {
/// Non-Maskable Interrupt Source Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT32 GlobalSystemInterrupt;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
} EFI_ACPI_5_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
///
/// Local APIC NMI Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT16 Flags;
- UINT8 LocalApicLint;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
} EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE;
///
/// Local APIC Address Override Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT64 LocalApicAddress;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
} EFI_ACPI_5_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
///
/// IO SAPIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 GlobalSystemInterruptBase;
- UINT64 IoSapicAddress;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
} EFI_ACPI_5_0_IO_SAPIC_STRUCTURE;
///
@@ -540,110 +540,110 @@ typedef struct {
/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT8 LocalSapicId;
- UINT8 LocalSapicEid;
- UINT8 Reserved[3];
- UINT32 Flags;
- UINT32 ACPIProcessorUIDValue;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
} EFI_ACPI_5_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
///
/// Platform Interrupt Sources Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT8 InterruptType;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT8 IoSapicVector;
- UINT32 GlobalSystemInterrupt;
- UINT32 PlatformInterruptSourceFlags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
} EFI_ACPI_5_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
///
/// Platform Interrupt Source Flags.
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_5_0_CPEI_PROCESSOR_OVERRIDE BIT0
+#define EFI_ACPI_5_0_CPEI_PROCESSOR_OVERRIDE BIT0
///
/// Processor Local x2APIC Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[2];
- UINT32 X2ApicId;
- UINT32 Flags;
- UINT32 AcpiProcessorUid;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 AcpiProcessorUid;
} EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
///
/// Local x2APIC NMI Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT32 AcpiProcessorUid;
- UINT8 LocalX2ApicLint;
- UINT8 Reserved[3];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 AcpiProcessorUid;
+ UINT8 LocalX2ApicLint;
+ UINT8 Reserved[3];
} EFI_ACPI_5_0_LOCAL_X2APIC_NMI_STRUCTURE;
///
/// GIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT32 GicId;
- UINT32 AcpiProcessorUid;
- UINT32 Flags;
- UINT32 ParkingProtocolVersion;
- UINT32 PerformanceInterruptGsiv;
- UINT64 ParkedAddress;
- UINT64 PhysicalBaseAddress;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 GicId;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ParkingProtocolVersion;
+ UINT32 PerformanceInterruptGsiv;
+ UINT64 ParkedAddress;
+ UINT64 PhysicalBaseAddress;
} EFI_ACPI_5_0_GIC_STRUCTURE;
///
/// GIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_5_0_GIC_ENABLED BIT0
-#define EFI_ACPI_5_0_PERFORMANCE_INTERRUPT_MODEL BIT1
+#define EFI_ACPI_5_0_GIC_ENABLED BIT0
+#define EFI_ACPI_5_0_PERFORMANCE_INTERRUPT_MODEL BIT1
///
/// GIC Distributor Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved1;
- UINT32 GicId;
- UINT64 PhysicalBaseAddress;
- UINT32 SystemVectorBase;
- UINT32 Reserved2;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 SystemVectorBase;
+ UINT32 Reserved2;
} EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE;
///
/// Smart Battery Description Table (SBST)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 WarningEnergyLevel;
- UINT32 LowEnergyLevel;
- UINT32 CriticalEnergyLevel;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
} EFI_ACPI_5_0_SMART_BATTERY_DESCRIPTION_TABLE;
///
/// SBST Version (as defined in ACPI 5.0 spec.)
///
-#define EFI_ACPI_5_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_5_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
///
/// Embedded Controller Boot Resources Table (ECDT)
@@ -651,11 +651,11 @@ typedef struct {
/// a fully qualified reference to the name space object.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE EcControl;
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE EcData;
- UINT32 Uid;
- UINT8 GpeBit;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
} EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
///
@@ -668,9 +668,9 @@ typedef struct {
/// must be defined in a platform specific manner.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Reserved1; ///< Must be set to 1
- UINT64 Reserved2;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; ///< Must be set to 1
+ UINT64 Reserved2;
} EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
///
@@ -691,57 +691,57 @@ typedef struct {
/// Processor Local APIC/SAPIC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 ProximityDomain7To0;
- UINT8 ApicId;
- UINT32 Flags;
- UINT8 LocalSapicEid;
- UINT8 ProximityDomain31To8[3];
- UINT32 ClockDomain;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT32 ClockDomain;
} EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
///
/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+#define EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
///
/// Memory Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 ProximityDomain;
- UINT16 Reserved1;
- UINT32 AddressBaseLow;
- UINT32 AddressBaseHigh;
- UINT32 LengthLow;
- UINT32 LengthHigh;
- UINT32 Reserved2;
- UINT32 Flags;
- UINT64 Reserved3;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
} EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE;
//
// Memory Flags. All other bits are reserved and must be 0.
//
-#define EFI_ACPI_5_0_MEMORY_ENABLED (1 << 0)
-#define EFI_ACPI_5_0_MEMORY_HOT_PLUGGABLE (1 << 1)
-#define EFI_ACPI_5_0_MEMORY_NONVOLATILE (1 << 2)
+#define EFI_ACPI_5_0_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_5_0_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_5_0_MEMORY_NONVOLATILE (1 << 2)
///
/// Processor Local x2APIC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved1[2];
- UINT32 ProximityDomain;
- UINT32 X2ApicId;
- UINT32 Flags;
- UINT32 ClockDomain;
- UINT8 Reserved2[4];
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1[2];
+ UINT32 ProximityDomain;
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+ UINT8 Reserved2[4];
} EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
///
@@ -749,8 +749,8 @@ typedef struct {
/// The rest of the table is a matrix.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 NumberOfSystemLocalities;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
} EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
///
@@ -762,14 +762,14 @@ typedef struct {
/// Corrected Platform Error Polling Table (CPEP)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 Reserved[8];
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[8];
} EFI_ACPI_5_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
///
/// CPEP Version (as defined in ACPI 5.0 spec.)
///
-#define EFI_ACPI_5_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+#define EFI_ACPI_5_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
//
// CPEP processor structure types.
@@ -780,66 +780,66 @@ typedef struct {
/// Corrected Platform Error Polling Processor Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT32 PollingInterval;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT32 PollingInterval;
} EFI_ACPI_5_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
///
/// Maximum System Characteristics Table (MSCT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 OffsetProxDomInfo;
- UINT32 MaximumNumberOfProximityDomains;
- UINT32 MaximumNumberOfClockDomains;
- UINT64 MaximumPhysicalAddress;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 OffsetProxDomInfo;
+ UINT32 MaximumNumberOfProximityDomains;
+ UINT32 MaximumNumberOfClockDomains;
+ UINT64 MaximumPhysicalAddress;
} EFI_ACPI_5_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
///
/// MSCT Version (as defined in ACPI 5.0 spec.)
///
-#define EFI_ACPI_5_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+#define EFI_ACPI_5_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
///
/// Maximum Proximity Domain Information Structure Definition
///
typedef struct {
- UINT8 Revision;
- UINT8 Length;
- UINT32 ProximityDomainRangeLow;
- UINT32 ProximityDomainRangeHigh;
- UINT32 MaximumProcessorCapacity;
- UINT64 MaximumMemoryCapacity;
+ UINT8 Revision;
+ UINT8 Length;
+ UINT32 ProximityDomainRangeLow;
+ UINT32 ProximityDomainRangeHigh;
+ UINT32 MaximumProcessorCapacity;
+ UINT64 MaximumMemoryCapacity;
} EFI_ACPI_5_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
///
/// ACPI RAS Feature Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 PlatformCommunicationChannelIdentifier[12];
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier[12];
} EFI_ACPI_5_0_RAS_FEATURE_TABLE;
///
/// RASF Version (as defined in ACPI 5.0 spec.)
///
-#define EFI_ACPI_5_0_RAS_FEATURE_TABLE_REVISION 0x01
+#define EFI_ACPI_5_0_RAS_FEATURE_TABLE_REVISION 0x01
///
/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
///
typedef struct {
- UINT32 Signature;
- UINT16 Command;
- UINT16 Status;
- UINT16 Version;
- UINT8 RASCapabilities[16];
- UINT8 SetRASCapabilities[16];
- UINT16 NumberOfRASFParameterBlocks;
- UINT32 SetRASCapabilitiesStatus;
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT16 Version;
+ UINT8 RASCapabilities[16];
+ UINT8 SetRASCapabilities[16];
+ UINT16 NumberOfRASFParameterBlocks;
+ UINT32 SetRASCapabilitiesStatus;
} EFI_ACPI_5_0_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
///
@@ -857,52 +857,52 @@ typedef struct {
/// ACPI RASF Parameter Block structure for PATROL_SCRUB
///
typedef struct {
- UINT16 Type;
- UINT16 Version;
- UINT16 Length;
- UINT16 PatrolScrubCommand;
- UINT64 RequestedAddressRange[2];
- UINT64 ActualAddressRange[2];
- UINT16 Flags;
- UINT8 RequestedSpeed;
+ UINT16 Type;
+ UINT16 Version;
+ UINT16 Length;
+ UINT16 PatrolScrubCommand;
+ UINT64 RequestedAddressRange[2];
+ UINT64 ActualAddressRange[2];
+ UINT16 Flags;
+ UINT8 RequestedSpeed;
} EFI_ACPI_5_0_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
///
/// ACPI RASF Patrol Scrub command
///
-#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
-#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
-#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
+#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
+#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
+#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
///
/// Memory Power State Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 PlatformCommunicationChannelIdentifier;
- UINT8 Reserved[3];
-// Memory Power Node Structure
-// Memory Power State Characteristics
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier;
+ UINT8 Reserved[3];
+ // Memory Power Node Structure
+ // Memory Power State Characteristics
} EFI_ACPI_5_0_MEMORY_POWER_STATUS_TABLE;
///
/// MPST Version (as defined in ACPI 5.0 spec.)
///
-#define EFI_ACPI_5_0_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+#define EFI_ACPI_5_0_MEMORY_POWER_STATE_TABLE_REVISION 0x01
///
/// MPST Platform Communication Channel Shared Memory Region definition.
///
typedef struct {
- UINT32 Signature;
- UINT16 Command;
- UINT16 Status;
- UINT32 MemoryPowerCommandRegister;
- UINT32 MemoryPowerStatusRegister;
- UINT32 PowerStateId;
- UINT32 MemoryPowerNodeId;
- UINT64 MemoryEnergyConsumed;
- UINT64 ExpectedAveragePowerComsuned;
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT32 MemoryPowerCommandRegister;
+ UINT32 MemoryPowerStatusRegister;
+ UINT32 PowerStateId;
+ UINT32 MemoryPowerNodeId;
+ UINT64 MemoryEnergyConsumed;
+ UINT64 ExpectedAveragePowerComsuned;
} EFI_ACPI_5_0_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
///
@@ -913,188 +913,188 @@ typedef struct {
///
/// ACPI MPST Memory Power command
///
-#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
-#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
-#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
-#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
///
/// MPST Memory Power Node Table
///
typedef struct {
- UINT8 PowerStateValue;
- UINT8 PowerStateInformationIndex;
+ UINT8 PowerStateValue;
+ UINT8 PowerStateInformationIndex;
} EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE;
typedef struct {
- UINT8 Flag;
- UINT8 Reserved;
- UINT16 MemoryPowerNodeId;
- UINT32 Length;
- UINT64 AddressBase;
- UINT64 AddressLength;
- UINT32 NumberOfPowerStates;
- UINT32 NumberOfPhysicalComponents;
-//EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
-//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+ UINT8 Flag;
+ UINT8 Reserved;
+ UINT16 MemoryPowerNodeId;
+ UINT32 Length;
+ UINT64 AddressBase;
+ UINT64 AddressLength;
+ UINT32 NumberOfPowerStates;
+ UINT32 NumberOfPhysicalComponents;
+ // EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
} EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE;
-#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
-#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
-#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
typedef struct {
- UINT16 MemoryPowerNodeCount;
- UINT8 Reserved[2];
+ UINT16 MemoryPowerNodeCount;
+ UINT8 Reserved[2];
} EFI_ACPI_5_0_MPST_MEMORY_POWER_NODE_TABLE;
///
/// MPST Memory Power State Characteristics Table
///
typedef struct {
- UINT8 PowerStateStructureID;
- UINT8 Flag;
- UINT16 Reserved;
- UINT32 AveragePowerConsumedInMPS0;
- UINT32 RelativePowerSavingToMPS0;
- UINT64 ExitLatencyToMPS0;
+ UINT8 PowerStateStructureID;
+ UINT8 Flag;
+ UINT16 Reserved;
+ UINT32 AveragePowerConsumedInMPS0;
+ UINT32 RelativePowerSavingToMPS0;
+ UINT64 ExitLatencyToMPS0;
} EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
-#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
-#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
-#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
typedef struct {
- UINT16 MemoryPowerStateCharacteristicsCount;
- UINT8 Reserved[2];
+ UINT16 MemoryPowerStateCharacteristicsCount;
+ UINT8 Reserved[2];
} EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
///
/// Memory Topology Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
} EFI_ACPI_5_0_MEMORY_TOPOLOGY_TABLE;
///
/// PMTT Version (as defined in ACPI 5.0 spec.)
///
-#define EFI_ACPI_5_0_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
+#define EFI_ACPI_5_0_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
///
/// Common Memory Aggregator Device Structure.
///
typedef struct {
- UINT8 Type;
- UINT8 Reserved;
- UINT16 Length;
- UINT16 Flags;
- UINT16 Reserved1;
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16 Length;
+ UINT16 Flags;
+ UINT16 Reserved1;
} EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// Memory Aggregator Device Type
///
-#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0
-#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
-#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2
+#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0
+#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
+#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2
///
/// Socket Memory Aggregator Device Structure.
///
typedef struct {
- EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
- UINT16 SocketIdentifier;
- UINT16 Reserved;
-//EFI_ACPI_5_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];
+ EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 SocketIdentifier;
+ UINT16 Reserved;
+ // EFI_ACPI_5_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];
} EFI_ACPI_5_0_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// MemoryController Memory Aggregator Device Structure.
///
typedef struct {
- EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
- UINT32 ReadLatency;
- UINT32 WriteLatency;
- UINT32 ReadBandwidth;
- UINT32 WriteBandwidth;
- UINT16 OptimalAccessUnit;
- UINT16 OptimalAccessAlignment;
- UINT16 Reserved;
- UINT16 NumberOfProximityDomains;
-//UINT32 ProximityDomain[NumberOfProximityDomains];
-//EFI_ACPI_5_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];
+ EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT32 ReadLatency;
+ UINT32 WriteLatency;
+ UINT32 ReadBandwidth;
+ UINT32 WriteBandwidth;
+ UINT16 OptimalAccessUnit;
+ UINT16 OptimalAccessAlignment;
+ UINT16 Reserved;
+ UINT16 NumberOfProximityDomains;
+ // UINT32 ProximityDomain[NumberOfProximityDomains];
+ // EFI_ACPI_5_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];
} EFI_ACPI_5_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// DIMM Memory Aggregator Device Structure.
///
typedef struct {
- EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
- UINT16 PhysicalComponentIdentifier;
- UINT16 Reserved;
- UINT32 SizeOfDimm;
- UINT32 SmbiosHandle;
+ EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 PhysicalComponentIdentifier;
+ UINT16 Reserved;
+ UINT32 SizeOfDimm;
+ UINT32 SmbiosHandle;
} EFI_ACPI_5_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// Boot Graphics Resource Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
///
/// 2-bytes (16 bit) version ID. This value must be 1.
///
- UINT16 Version;
+ UINT16 Version;
///
/// 1-byte status field indicating current status about the table.
/// Bits[7:1] = Reserved (must be zero)
/// Bit [0] = Valid. A one indicates the boot image graphic is valid.
///
- UINT8 Status;
+ UINT8 Status;
///
/// 1-byte enumerated type field indicating format of the image.
/// 0 = Bitmap
/// 1 - 255 Reserved (for future use)
///
- UINT8 ImageType;
+ UINT8 ImageType;
///
/// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
/// of the image bitmap.
///
- UINT64 ImageAddress;
+ UINT64 ImageAddress;
///
/// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
/// (X, Y) display offset of the top left corner of the boot image.
/// The top left corner of the display is at offset (0, 0).
///
- UINT32 ImageOffsetX;
+ UINT32 ImageOffsetX;
///
/// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
/// (X, Y) display offset of the top left corner of the boot image.
/// The top left corner of the display is at offset (0, 0).
///
- UINT32 ImageOffsetY;
+ UINT32 ImageOffsetY;
} EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE;
///
/// BGRT Revision
///
-#define EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+#define EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
///
/// BGRT Version
///
-#define EFI_ACPI_5_0_BGRT_VERSION 0x01
+#define EFI_ACPI_5_0_BGRT_VERSION 0x01
///
/// BGRT Status
///
-#define EFI_ACPI_5_0_BGRT_STATUS_NOT_DISPLAYED 0x00
-#define EFI_ACPI_5_0_BGRT_STATUS_DISPLAYED 0x01
-#define EFI_ACPI_5_0_BGRT_STATUS_INVALID EFI_ACPI_5_0_BGRT_STATUS_NOT_DISPLAYED
-#define EFI_ACPI_5_0_BGRT_STATUS_VALID EFI_ACPI_5_0_BGRT_STATUS_DISPLAYED
+#define EFI_ACPI_5_0_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_5_0_BGRT_STATUS_DISPLAYED 0x01
+#define EFI_ACPI_5_0_BGRT_STATUS_INVALID EFI_ACPI_5_0_BGRT_STATUS_NOT_DISPLAYED
+#define EFI_ACPI_5_0_BGRT_STATUS_VALID EFI_ACPI_5_0_BGRT_STATUS_DISPLAYED
///
/// BGRT Image Type
@@ -1104,26 +1104,26 @@ typedef struct {
///
/// FPDT Version (as defined in ACPI 5.0 spec.)
///
-#define EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+#define EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
///
/// FPDT Performance Record Types
///
-#define EFI_ACPI_5_0_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
-#define EFI_ACPI_5_0_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
+#define EFI_ACPI_5_0_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
+#define EFI_ACPI_5_0_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
///
/// FPDT Performance Record Revision
///
-#define EFI_ACPI_5_0_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
-#define EFI_ACPI_5_0_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+#define EFI_ACPI_5_0_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
+#define EFI_ACPI_5_0_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
///
/// FPDT Runtime Performance Record Types
///
-#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
-#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
-#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
+#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
+#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
+#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
///
/// FPDT Runtime Performance Record Revision
@@ -1136,77 +1136,77 @@ typedef struct {
/// FPDT Performance Record header
///
typedef struct {
- UINT16 Type;
- UINT8 Length;
- UINT8 Revision;
+ UINT16 Type;
+ UINT8 Length;
+ UINT8 Revision;
} EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER;
///
/// FPDT Performance Table header
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
+ UINT32 Signature;
+ UINT32 Length;
} EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER;
///
/// FPDT Firmware Basic Boot Performance Pointer Record Structure
///
typedef struct {
- EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
///
/// 64-bit processor-relative physical address of the Basic Boot Performance Table.
///
- UINT64 BootPerformanceTablePointer;
+ UINT64 BootPerformanceTablePointer;
} EFI_ACPI_5_0_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
///
/// FPDT S3 Performance Table Pointer Record Structure
///
typedef struct {
- EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
///
/// 64-bit processor-relative physical address of the S3 Performance Table.
///
- UINT64 S3PerformanceTablePointer;
+ UINT64 S3PerformanceTablePointer;
} EFI_ACPI_5_0_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
///
/// FPDT Firmware Basic Boot Performance Record Structure
///
typedef struct {
- EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
///
/// Timer value logged at the beginning of firmware image execution.
/// This may not always be zero or near zero.
///
- UINT64 ResetEnd;
+ UINT64 ResetEnd;
///
/// Timer value logged just prior to loading the OS boot loader into memory.
/// For non-UEFI compatible boots, this field must be zero.
///
- UINT64 OsLoaderLoadImageStart;
+ UINT64 OsLoaderLoadImageStart;
///
/// Timer value logged just prior to launching the previously loaded OS boot loader image.
/// For non-UEFI compatible boots, the timer value logged will be just prior
/// to the INT 19h handler invocation.
///
- UINT64 OsLoaderStartImageStart;
+ UINT64 OsLoaderStartImageStart;
///
/// Timer value logged at the point when the OS loader calls the
/// ExitBootServices function for UEFI compatible firmware.
/// For non-UEFI compatible boots, this field must be zero.
///
- UINT64 ExitBootServicesEntry;
+ UINT64 ExitBootServicesEntry;
///
/// Timer value logged at the point just prior to when the OS loader gaining
/// control back from calls the ExitBootServices function for UEFI compatible firmware.
/// For non-UEFI compatible boots, this field must be zero.
///
- UINT64 ExitBootServicesExit;
+ UINT64 ExitBootServicesExit;
} EFI_ACPI_5_0_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
///
@@ -1218,7 +1218,7 @@ typedef struct {
// FPDT Firmware Basic Boot Performance Table
//
typedef struct {
- EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER Header;
//
// one or more Performance Records.
//
@@ -1233,7 +1233,7 @@ typedef struct {
// FPDT Firmware S3 Boot Performance Table
//
typedef struct {
- EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER Header;
//
// one or more Performance Records.
//
@@ -1243,124 +1243,125 @@ typedef struct {
/// FPDT Basic S3 Resume Performance Record
///
typedef struct {
- EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
///
/// A count of the number of S3 resume cycles since the last full boot sequence.
///
- UINT32 ResumeCount;
+ UINT32 ResumeCount;
///
/// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
/// OS waking vector. Only the most recent resume cycle's time is retained.
///
- UINT64 FullResume;
+ UINT64 FullResume;
///
/// Average timer value of all resume cycles logged since the last full boot
/// sequence, including the most recent resume. Note that the entire log of
/// timer values does not need to be retained in order to calculate this average.
///
- UINT64 AverageResume;
+ UINT64 AverageResume;
} EFI_ACPI_5_0_FPDT_S3_RESUME_RECORD;
///
/// FPDT Basic S3 Suspend Performance Record
///
typedef struct {
- EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
///
/// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
/// Only the most recent suspend cycle's timer value is retained.
///
- UINT64 SuspendStart;
+ UINT64 SuspendStart;
///
/// Timer value recorded at the final firmware write to SLP_TYP (or other
/// mechanism) used to trigger hardware entry to S3.
/// Only the most recent suspend cycle's timer value is retained.
///
- UINT64 SuspendEnd;
+ UINT64 SuspendEnd;
} EFI_ACPI_5_0_FPDT_S3_SUSPEND_RECORD;
///
/// Firmware Performance Record Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
} EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_RECORD_TABLE;
///
/// Generic Timer Description Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 PhysicalAddress;
- UINT32 GlobalFlags;
- UINT32 SecurePL1TimerGSIV;
- UINT32 SecurePL1TimerFlags;
- UINT32 NonSecurePL1TimerGSIV;
- UINT32 NonSecurePL1TimerFlags;
- UINT32 VirtualTimerGSIV;
- UINT32 VirtualTimerFlags;
- UINT32 NonSecurePL2TimerGSIV;
- UINT32 NonSecurePL2TimerFlags;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 PhysicalAddress;
+ UINT32 GlobalFlags;
+ UINT32 SecurePL1TimerGSIV;
+ UINT32 SecurePL1TimerFlags;
+ UINT32 NonSecurePL1TimerGSIV;
+ UINT32 NonSecurePL1TimerFlags;
+ UINT32 VirtualTimerGSIV;
+ UINT32 VirtualTimerFlags;
+ UINT32 NonSecurePL2TimerGSIV;
+ UINT32 NonSecurePL2TimerFlags;
} EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE;
///
/// GTDT Version (as defined in ACPI 5.0 spec.)
///
-#define EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x01
///
/// Global Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT BIT0
-#define EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE BIT1
+#define EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT BIT0
+#define EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE BIT1
///
/// Timer Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
-#define EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
///
/// Boot Error Record Table (BERT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 BootErrorRegionLength;
- UINT64 BootErrorRegion;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 BootErrorRegionLength;
+ UINT64 BootErrorRegion;
} EFI_ACPI_5_0_BOOT_ERROR_RECORD_TABLE_HEADER;
///
/// BERT Version (as defined in ACPI 5.0 spec.)
///
-#define EFI_ACPI_5_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+#define EFI_ACPI_5_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
///
/// Boot Error Region Block Status Definition
///
typedef struct {
- UINT32 UncorrectableErrorValid:1;
- UINT32 CorrectableErrorValid:1;
- UINT32 MultipleUncorrectableErrors:1;
- UINT32 MultipleCorrectableErrors:1;
- UINT32 ErrorDataEntryCount:10;
- UINT32 Reserved:18;
+ UINT32 UncorrectableErrorValid : 1;
+ UINT32 CorrectableErrorValid : 1;
+ UINT32 MultipleUncorrectableErrors : 1;
+ UINT32 MultipleCorrectableErrors : 1;
+ UINT32 ErrorDataEntryCount : 10;
+ UINT32 Reserved : 18;
} EFI_ACPI_5_0_ERROR_BLOCK_STATUS;
///
/// Boot Error Region Definition
///
typedef struct {
- EFI_ACPI_5_0_ERROR_BLOCK_STATUS BlockStatus;
- UINT32 RawDataOffset;
- UINT32 RawDataLength;
- UINT32 DataLength;
- UINT32 ErrorSeverity;
+ EFI_ACPI_5_0_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
} EFI_ACPI_5_0_BOOT_ERROR_REGION_STRUCTURE;
//
// Boot Error Severity types
//
#define EFI_ACPI_5_0_ERROR_SEVERITY_CORRECTABLE 0x00
+#define EFI_ACPI_5_0_ERROR_SEVERITY_RECOVERABLE 0x00
#define EFI_ACPI_5_0_ERROR_SEVERITY_FATAL 0x01
#define EFI_ACPI_5_0_ERROR_SEVERITY_CORRECTED 0x02
#define EFI_ACPI_5_0_ERROR_SEVERITY_NONE 0x03
@@ -1369,14 +1370,14 @@ typedef struct {
/// Generic Error Data Entry Definition
///
typedef struct {
- UINT8 SectionType[16];
- UINT32 ErrorSeverity;
- UINT16 Revision;
- UINT8 ValidationBits;
- UINT8 Flags;
- UINT32 ErrorDataLength;
- UINT8 FruId[16];
- UINT8 FruText[20];
+ UINT8 SectionType[16];
+ UINT32 ErrorSeverity;
+ UINT16 Revision;
+ UINT8 ValidationBits;
+ UINT8 Flags;
+ UINT32 ErrorDataLength;
+ UINT8 FruId[16];
+ UINT8 FruText[20];
} EFI_ACPI_5_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
///
@@ -1388,14 +1389,14 @@ typedef struct {
/// HEST - Hardware Error Source Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 ErrorSourceCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 ErrorSourceCount;
} EFI_ACPI_5_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
///
/// HEST Version (as defined in ACPI 5.0 spec.)
///
-#define EFI_ACPI_5_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+#define EFI_ACPI_5_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
//
// Error Source structure types.
@@ -1411,403 +1412,403 @@ typedef struct {
//
// Error Source structure flags.
//
-#define EFI_ACPI_5_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
-#define EFI_ACPI_5_0_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
+#define EFI_ACPI_5_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
+#define EFI_ACPI_5_0_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
///
/// IA-32 Architecture Machine Check Exception Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT64 GlobalCapabilityInitData;
- UINT64 GlobalControlInitData;
- UINT8 NumberOfHardwareBanks;
- UINT8 Reserved1[7];
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT64 GlobalCapabilityInitData;
+ UINT64 GlobalControlInitData;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[7];
} EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
///
/// IA-32 Architecture Machine Check Bank Structure Definition
///
typedef struct {
- UINT8 BankNumber;
- UINT8 ClearStatusOnInitialization;
- UINT8 StatusDataFormat;
- UINT8 Reserved0;
- UINT32 ControlRegisterMsrAddress;
- UINT64 ControlInitData;
- UINT32 StatusRegisterMsrAddress;
- UINT32 AddressRegisterMsrAddress;
- UINT32 MiscRegisterMsrAddress;
+ UINT8 BankNumber;
+ UINT8 ClearStatusOnInitialization;
+ UINT8 StatusDataFormat;
+ UINT8 Reserved0;
+ UINT32 ControlRegisterMsrAddress;
+ UINT64 ControlInitData;
+ UINT32 StatusRegisterMsrAddress;
+ UINT32 AddressRegisterMsrAddress;
+ UINT32 MiscRegisterMsrAddress;
} EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
///
/// IA-32 Architecture Machine Check Bank Structure MCA data format
///
-#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
-#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
-#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
+#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
+#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
+#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
//
// Hardware Error Notification types. All other values are reserved
//
-#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
-#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
-#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
-#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
-#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
+#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
+#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
+#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
+#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
+#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
///
/// Hardware Error Notification Configuration Write Enable Structure Definition
///
typedef struct {
- UINT16 Type:1;
- UINT16 PollInterval:1;
- UINT16 SwitchToPollingThresholdValue:1;
- UINT16 SwitchToPollingThresholdWindow:1;
- UINT16 ErrorThresholdValue:1;
- UINT16 ErrorThresholdWindow:1;
- UINT16 Reserved:10;
+ UINT16 Type : 1;
+ UINT16 PollInterval : 1;
+ UINT16 SwitchToPollingThresholdValue : 1;
+ UINT16 SwitchToPollingThresholdWindow : 1;
+ UINT16 ErrorThresholdValue : 1;
+ UINT16 ErrorThresholdWindow : 1;
+ UINT16 Reserved : 10;
} EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
///
/// Hardware Error Notification Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
- UINT32 PollInterval;
- UINT32 Vector;
- UINT32 SwitchToPollingThresholdValue;
- UINT32 SwitchToPollingThresholdWindow;
- UINT32 ErrorThresholdValue;
- UINT32 ErrorThresholdWindow;
+ UINT8 Type;
+ UINT8 Length;
+ EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
+ UINT32 PollInterval;
+ UINT32 Vector;
+ UINT32 SwitchToPollingThresholdValue;
+ UINT32 SwitchToPollingThresholdWindow;
+ UINT32 ErrorThresholdValue;
+ UINT32 ErrorThresholdWindow;
} EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
///
/// IA-32 Architecture Corrected Machine Check Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
- UINT8 NumberOfHardwareBanks;
- UINT8 Reserved1[3];
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
} EFI_ACPI_5_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
///
/// IA-32 Architecture NMI Error Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 MaxRawDataLength;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
} EFI_ACPI_5_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
///
/// PCI Express Root Port AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
- UINT32 RootErrorCommand;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 RootErrorCommand;
} EFI_ACPI_5_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
///
/// PCI Express Device AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
} EFI_ACPI_5_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
///
/// PCI Express Bridge AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
- UINT32 SecondaryUncorrectableErrorMask;
- UINT32 SecondaryUncorrectableErrorSeverity;
- UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 SecondaryUncorrectableErrorMask;
+ UINT32 SecondaryUncorrectableErrorSeverity;
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
} EFI_ACPI_5_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
///
/// Generic Hardware Error Source Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT16 RelatedSourceId;
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 MaxRawDataLength;
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
- EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
- UINT32 ErrorStatusBlockLength;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
} EFI_ACPI_5_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
///
/// Generic Error Status Definition
///
typedef struct {
- EFI_ACPI_5_0_ERROR_BLOCK_STATUS BlockStatus;
- UINT32 RawDataOffset;
- UINT32 RawDataLength;
- UINT32 DataLength;
- UINT32 ErrorSeverity;
+ EFI_ACPI_5_0_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
} EFI_ACPI_5_0_GENERIC_ERROR_STATUS_STRUCTURE;
///
/// ERST - Error Record Serialization Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 SerializationHeaderSize;
- UINT8 Reserved0[4];
- UINT32 InstructionEntryCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 SerializationHeaderSize;
+ UINT8 Reserved0[4];
+ UINT32 InstructionEntryCount;
} EFI_ACPI_5_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
///
/// ERST Version (as defined in ACPI 5.0 spec.)
///
-#define EFI_ACPI_5_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+#define EFI_ACPI_5_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
///
/// ERST Serialization Actions
///
-#define EFI_ACPI_5_0_ERST_BEGIN_WRITE_OPERATION 0x00
-#define EFI_ACPI_5_0_ERST_BEGIN_READ_OPERATION 0x01
-#define EFI_ACPI_5_0_ERST_BEGIN_CLEAR_OPERATION 0x02
-#define EFI_ACPI_5_0_ERST_END_OPERATION 0x03
-#define EFI_ACPI_5_0_ERST_SET_RECORD_OFFSET 0x04
-#define EFI_ACPI_5_0_ERST_EXECUTE_OPERATION 0x05
-#define EFI_ACPI_5_0_ERST_CHECK_BUSY_STATUS 0x06
-#define EFI_ACPI_5_0_ERST_GET_COMMAND_STATUS 0x07
-#define EFI_ACPI_5_0_ERST_GET_RECORD_IDENTIFIER 0x08
-#define EFI_ACPI_5_0_ERST_SET_RECORD_IDENTIFIER 0x09
-#define EFI_ACPI_5_0_ERST_GET_RECORD_COUNT 0x0A
-#define EFI_ACPI_5_0_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
-#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
-#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
-#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
+#define EFI_ACPI_5_0_ERST_BEGIN_WRITE_OPERATION 0x00
+#define EFI_ACPI_5_0_ERST_BEGIN_READ_OPERATION 0x01
+#define EFI_ACPI_5_0_ERST_BEGIN_CLEAR_OPERATION 0x02
+#define EFI_ACPI_5_0_ERST_END_OPERATION 0x03
+#define EFI_ACPI_5_0_ERST_SET_RECORD_OFFSET 0x04
+#define EFI_ACPI_5_0_ERST_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_5_0_ERST_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_5_0_ERST_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_5_0_ERST_GET_RECORD_IDENTIFIER 0x08
+#define EFI_ACPI_5_0_ERST_SET_RECORD_IDENTIFIER 0x09
+#define EFI_ACPI_5_0_ERST_GET_RECORD_COUNT 0x0A
+#define EFI_ACPI_5_0_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
+#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
+#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
+#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
///
/// ERST Action Command Status
///
-#define EFI_ACPI_5_0_ERST_STATUS_SUCCESS 0x00
-#define EFI_ACPI_5_0_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
-#define EFI_ACPI_5_0_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
-#define EFI_ACPI_5_0_ERST_STATUS_FAILED 0x03
-#define EFI_ACPI_5_0_ERST_STATUS_RECORD_STORE_EMPTY 0x04
-#define EFI_ACPI_5_0_ERST_STATUS_RECORD_NOT_FOUND 0x05
+#define EFI_ACPI_5_0_ERST_STATUS_SUCCESS 0x00
+#define EFI_ACPI_5_0_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
+#define EFI_ACPI_5_0_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
+#define EFI_ACPI_5_0_ERST_STATUS_FAILED 0x03
+#define EFI_ACPI_5_0_ERST_STATUS_RECORD_STORE_EMPTY 0x04
+#define EFI_ACPI_5_0_ERST_STATUS_RECORD_NOT_FOUND 0x05
///
/// ERST Serialization Instructions
///
-#define EFI_ACPI_5_0_ERST_READ_REGISTER 0x00
-#define EFI_ACPI_5_0_ERST_READ_REGISTER_VALUE 0x01
-#define EFI_ACPI_5_0_ERST_WRITE_REGISTER 0x02
-#define EFI_ACPI_5_0_ERST_WRITE_REGISTER_VALUE 0x03
-#define EFI_ACPI_5_0_ERST_NOOP 0x04
-#define EFI_ACPI_5_0_ERST_LOAD_VAR1 0x05
-#define EFI_ACPI_5_0_ERST_LOAD_VAR2 0x06
-#define EFI_ACPI_5_0_ERST_STORE_VAR1 0x07
-#define EFI_ACPI_5_0_ERST_ADD 0x08
-#define EFI_ACPI_5_0_ERST_SUBTRACT 0x09
-#define EFI_ACPI_5_0_ERST_ADD_VALUE 0x0A
-#define EFI_ACPI_5_0_ERST_SUBTRACT_VALUE 0x0B
-#define EFI_ACPI_5_0_ERST_STALL 0x0C
-#define EFI_ACPI_5_0_ERST_STALL_WHILE_TRUE 0x0D
-#define EFI_ACPI_5_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
-#define EFI_ACPI_5_0_ERST_GOTO 0x0F
-#define EFI_ACPI_5_0_ERST_SET_SRC_ADDRESS_BASE 0x10
-#define EFI_ACPI_5_0_ERST_SET_DST_ADDRESS_BASE 0x11
-#define EFI_ACPI_5_0_ERST_MOVE_DATA 0x12
+#define EFI_ACPI_5_0_ERST_READ_REGISTER 0x00
+#define EFI_ACPI_5_0_ERST_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_5_0_ERST_WRITE_REGISTER 0x02
+#define EFI_ACPI_5_0_ERST_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_5_0_ERST_NOOP 0x04
+#define EFI_ACPI_5_0_ERST_LOAD_VAR1 0x05
+#define EFI_ACPI_5_0_ERST_LOAD_VAR2 0x06
+#define EFI_ACPI_5_0_ERST_STORE_VAR1 0x07
+#define EFI_ACPI_5_0_ERST_ADD 0x08
+#define EFI_ACPI_5_0_ERST_SUBTRACT 0x09
+#define EFI_ACPI_5_0_ERST_ADD_VALUE 0x0A
+#define EFI_ACPI_5_0_ERST_SUBTRACT_VALUE 0x0B
+#define EFI_ACPI_5_0_ERST_STALL 0x0C
+#define EFI_ACPI_5_0_ERST_STALL_WHILE_TRUE 0x0D
+#define EFI_ACPI_5_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
+#define EFI_ACPI_5_0_ERST_GOTO 0x0F
+#define EFI_ACPI_5_0_ERST_SET_SRC_ADDRESS_BASE 0x10
+#define EFI_ACPI_5_0_ERST_SET_DST_ADDRESS_BASE 0x11
+#define EFI_ACPI_5_0_ERST_MOVE_DATA 0x12
///
/// ERST Instruction Flags
///
-#define EFI_ACPI_5_0_ERST_PRESERVE_REGISTER 0x01
+#define EFI_ACPI_5_0_ERST_PRESERVE_REGISTER 0x01
///
/// ERST Serialization Instruction Entry
///
typedef struct {
- UINT8 SerializationAction;
- UINT8 Instruction;
- UINT8 Flags;
- UINT8 Reserved0;
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
- UINT64 Value;
- UINT64 Mask;
+ UINT8 SerializationAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
} EFI_ACPI_5_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
///
/// EINJ - Error Injection Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 InjectionHeaderSize;
- UINT8 InjectionFlags;
- UINT8 Reserved0[3];
- UINT32 InjectionEntryCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 InjectionHeaderSize;
+ UINT8 InjectionFlags;
+ UINT8 Reserved0[3];
+ UINT32 InjectionEntryCount;
} EFI_ACPI_5_0_ERROR_INJECTION_TABLE_HEADER;
///
/// EINJ Version (as defined in ACPI 5.0 spec.)
///
-#define EFI_ACPI_5_0_ERROR_INJECTION_TABLE_REVISION 0x01
+#define EFI_ACPI_5_0_ERROR_INJECTION_TABLE_REVISION 0x01
///
/// EINJ Error Injection Actions
///
-#define EFI_ACPI_5_0_EINJ_BEGIN_INJECTION_OPERATION 0x00
-#define EFI_ACPI_5_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
-#define EFI_ACPI_5_0_EINJ_SET_ERROR_TYPE 0x02
-#define EFI_ACPI_5_0_EINJ_GET_ERROR_TYPE 0x03
-#define EFI_ACPI_5_0_EINJ_END_OPERATION 0x04
-#define EFI_ACPI_5_0_EINJ_EXECUTE_OPERATION 0x05
-#define EFI_ACPI_5_0_EINJ_CHECK_BUSY_STATUS 0x06
-#define EFI_ACPI_5_0_EINJ_GET_COMMAND_STATUS 0x07
-#define EFI_ACPI_5_0_EINJ_TRIGGER_ERROR 0xFF
+#define EFI_ACPI_5_0_EINJ_BEGIN_INJECTION_OPERATION 0x00
+#define EFI_ACPI_5_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
+#define EFI_ACPI_5_0_EINJ_SET_ERROR_TYPE 0x02
+#define EFI_ACPI_5_0_EINJ_GET_ERROR_TYPE 0x03
+#define EFI_ACPI_5_0_EINJ_END_OPERATION 0x04
+#define EFI_ACPI_5_0_EINJ_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_5_0_EINJ_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_5_0_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_5_0_EINJ_TRIGGER_ERROR 0xFF
///
/// EINJ Action Command Status
///
-#define EFI_ACPI_5_0_EINJ_STATUS_SUCCESS 0x00
-#define EFI_ACPI_5_0_EINJ_STATUS_UNKNOWN_FAILURE 0x01
-#define EFI_ACPI_5_0_EINJ_STATUS_INVALID_ACCESS 0x02
+#define EFI_ACPI_5_0_EINJ_STATUS_SUCCESS 0x00
+#define EFI_ACPI_5_0_EINJ_STATUS_UNKNOWN_FAILURE 0x01
+#define EFI_ACPI_5_0_EINJ_STATUS_INVALID_ACCESS 0x02
///
/// EINJ Error Type Definition
///
-#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
-#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
-#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
-#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
-#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
-#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
-#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
-#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
-#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
-#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
-#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
-#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
+#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
+#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
+#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
+#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
+#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
+#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
+#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
+#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
+#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
+#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
+#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
+#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
///
/// EINJ Injection Instructions
///
-#define EFI_ACPI_5_0_EINJ_READ_REGISTER 0x00
-#define EFI_ACPI_5_0_EINJ_READ_REGISTER_VALUE 0x01
-#define EFI_ACPI_5_0_EINJ_WRITE_REGISTER 0x02
-#define EFI_ACPI_5_0_EINJ_WRITE_REGISTER_VALUE 0x03
-#define EFI_ACPI_5_0_EINJ_NOOP 0x04
+#define EFI_ACPI_5_0_EINJ_READ_REGISTER 0x00
+#define EFI_ACPI_5_0_EINJ_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_5_0_EINJ_WRITE_REGISTER 0x02
+#define EFI_ACPI_5_0_EINJ_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_5_0_EINJ_NOOP 0x04
///
/// EINJ Instruction Flags
///
-#define EFI_ACPI_5_0_EINJ_PRESERVE_REGISTER 0x01
+#define EFI_ACPI_5_0_EINJ_PRESERVE_REGISTER 0x01
///
/// EINJ Injection Instruction Entry
///
typedef struct {
- UINT8 InjectionAction;
- UINT8 Instruction;
- UINT8 Flags;
- UINT8 Reserved0;
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
- UINT64 Value;
- UINT64 Mask;
+ UINT8 InjectionAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
} EFI_ACPI_5_0_EINJ_INJECTION_INSTRUCTION_ENTRY;
///
/// EINJ Trigger Action Table
///
typedef struct {
- UINT32 HeaderSize;
- UINT32 Revision;
- UINT32 TableSize;
- UINT32 EntryCount;
+ UINT32 HeaderSize;
+ UINT32 Revision;
+ UINT32 TableSize;
+ UINT32 EntryCount;
} EFI_ACPI_5_0_EINJ_TRIGGER_ACTION_TABLE;
///
/// Platform Communications Channel Table (PCCT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Flags;
- UINT64 Reserved;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Flags;
+ UINT64 Reserved;
} EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
///
/// PCCT Version (as defined in ACPI 5.0 spec.)
///
-#define EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01
+#define EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01
///
/// PCCT Global Flags
///
-#define EFI_ACPI_5_0_PCCT_FLAGS_SCI_DOORBELL BIT0
+#define EFI_ACPI_5_0_PCCT_FLAGS_SCI_DOORBELL BIT0
//
// PCCT Subspace type
@@ -1818,25 +1819,25 @@ typedef struct {
/// PCC Subspace Structure Header
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
+ UINT8 Type;
+ UINT8 Length;
} EFI_ACPI_5_0_PCCT_SUBSPACE_HEADER;
///
/// Generic Communications Subspace Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[6];
- UINT64 BaseAddress;
- UINT64 AddressLength;
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
- UINT64 DoorbellPreserve;
- UINT64 DoorbellWrite;
- UINT32 NominalLatency;
- UINT32 MaximumPeriodicAccessRate;
- UINT16 MinimumRequestTurnaroundTime;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[6];
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
} EFI_ACPI_5_0_PCCT_SUBSPACE_GENERIC;
///
@@ -1844,18 +1845,18 @@ typedef struct {
///
typedef struct {
- UINT8 Command;
- UINT8 Reserved:7;
- UINT8 GenerateSci:1;
+ UINT8 Command;
+ UINT8 Reserved : 7;
+ UINT8 GenerateSci : 1;
} EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
typedef struct {
- UINT8 CommandComplete:1;
- UINT8 SciDoorbell:1;
- UINT8 Error:1;
- UINT8 PlatformNotification:1;
- UINT8 Reserved:4;
- UINT8 Reserved1;
+ UINT8 CommandComplete : 1;
+ UINT8 SciDoorbell : 1;
+ UINT8 Error : 1;
+ UINT8 PlatformNotification : 1;
+ UINT8 Reserved : 4;
+ UINT8 Reserved1;
} EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
typedef struct {
@@ -2097,7 +2098,7 @@ typedef struct {
/// "WAET" Windows ACPI Emulated Devices Table
///
#define EFI_ACPI_5_0_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')
-#define EFI_ACPI_5_0_WINDOWS_ACPI_ENLIGHTENMENT_TABLE_SIGNATURE EFI_ACPI_5_0_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE
+#define EFI_ACPI_5_0_WINDOWS_ACPI_ENLIGHTENMENT_TABLE_SIGNATURE EFI_ACPI_5_0_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE
///
/// "WDAT" Watchdog Action Table
diff --git a/MdePkg/Include/IndustryStandard/Acpi51.h b/MdePkg/Include/IndustryStandard/Acpi51.h
index e2877df9..d2259890 100644
--- a/MdePkg/Include/IndustryStandard/Acpi51.h
+++ b/MdePkg/Include/IndustryStandard/Acpi51.h
@@ -2,7 +2,7 @@
ACPI 5.1 definitions from the ACPI Specification Revision 5.1 Errata B January, 2016.
Copyright (c) 2014 Hewlett-Packard Development Company, L.P.
- Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.
(C) Copyright 2015 Hewlett Packard Enterprise Development LP
Copyright (c) 2020, ARM Ltd. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -22,21 +22,21 @@
/// ACPI 5.1 Generic Address Space definition
///
typedef struct {
- UINT8 AddressSpaceId;
- UINT8 RegisterBitWidth;
- UINT8 RegisterBitOffset;
- UINT8 AccessSize;
- UINT64 Address;
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
} EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE;
//
// Generic Address Space Address IDs
//
-#define EFI_ACPI_5_1_SYSTEM_MEMORY 0
-#define EFI_ACPI_5_1_SYSTEM_IO 1
-#define EFI_ACPI_5_1_PCI_CONFIGURATION_SPACE 2
-#define EFI_ACPI_5_1_EMBEDDED_CONTROLLER 3
-#define EFI_ACPI_5_1_SMBUS 4
+#define EFI_ACPI_5_1_SYSTEM_MEMORY 0
+#define EFI_ACPI_5_1_SYSTEM_IO 1
+#define EFI_ACPI_5_1_PCI_CONFIGURATION_SPACE 2
+#define EFI_ACPI_5_1_EMBEDDED_CONTROLLER 3
+#define EFI_ACPI_5_1_SMBUS 4
#define EFI_ACPI_5_1_PLATFORM_COMMUNICATION_CHANNEL 0x0A
#define EFI_ACPI_5_1_FUNCTIONAL_FIXED_HARDWARE 0x7F
@@ -57,29 +57,29 @@ typedef struct {
/// Root System Description Pointer Structure
///
typedef struct {
- UINT64 Signature;
- UINT8 Checksum;
- UINT8 OemId[6];
- UINT8 Revision;
- UINT32 RsdtAddress;
- UINT32 Length;
- UINT64 XsdtAddress;
- UINT8 ExtendedChecksum;
- UINT8 Reserved[3];
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
} EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER;
///
/// RSD_PTR Revision (as defined in ACPI 5.1 spec.)
///
-#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 5.1) says current value is 2
+#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 5.1) says current value is 2
///
/// Common table header, this prefaces all ACPI tables, including FACS, but
/// excluding the RSD PTR structure
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
+ UINT32 Signature;
+ UINT32 Length;
} EFI_ACPI_5_1_COMMON_HEADER;
//
@@ -91,7 +91,7 @@ typedef struct {
///
/// RSDT Revision (as defined in ACPI 5.1 spec.)
///
-#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
//
// Extended System Description Table
@@ -102,73 +102,73 @@ typedef struct {
///
/// XSDT Revision (as defined in ACPI 5.1 spec.)
///
-#define EFI_ACPI_5_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_5_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
///
/// Fixed ACPI Description Table Structure (FADT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 FirmwareCtrl;
- UINT32 Dsdt;
- UINT8 Reserved0;
- UINT8 PreferredPmProfile;
- UINT16 SciInt;
- UINT32 SmiCmd;
- UINT8 AcpiEnable;
- UINT8 AcpiDisable;
- UINT8 S4BiosReq;
- UINT8 PstateCnt;
- UINT32 Pm1aEvtBlk;
- UINT32 Pm1bEvtBlk;
- UINT32 Pm1aCntBlk;
- UINT32 Pm1bCntBlk;
- UINT32 Pm2CntBlk;
- UINT32 PmTmrBlk;
- UINT32 Gpe0Blk;
- UINT32 Gpe1Blk;
- UINT8 Pm1EvtLen;
- UINT8 Pm1CntLen;
- UINT8 Pm2CntLen;
- UINT8 PmTmrLen;
- UINT8 Gpe0BlkLen;
- UINT8 Gpe1BlkLen;
- UINT8 Gpe1Base;
- UINT8 CstCnt;
- UINT16 PLvl2Lat;
- UINT16 PLvl3Lat;
- UINT16 FlushSize;
- UINT16 FlushStride;
- UINT8 DutyOffset;
- UINT8 DutyWidth;
- UINT8 DayAlrm;
- UINT8 MonAlrm;
- UINT8 Century;
- UINT16 IaPcBootArch;
- UINT8 Reserved1;
- UINT32 Flags;
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE ResetReg;
- UINT8 ResetValue;
- UINT16 ArmBootArch;
- UINT8 MinorVersion;
- UINT64 XFirmwareCtrl;
- UINT64 XDsdt;
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT16 ArmBootArch;
+ UINT8 MinorVersion;
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
} EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE;
///
/// FADT Version (as defined in ACPI 5.1 spec.)
///
-#define EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x05
+#define EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x05
#define EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x01
//
@@ -188,62 +188,62 @@ typedef struct {
// Fixed ACPI Description Table Boot Architecture Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_5_1_LEGACY_DEVICES BIT0
-#define EFI_ACPI_5_1_8042 BIT1
-#define EFI_ACPI_5_1_VGA_NOT_PRESENT BIT2
-#define EFI_ACPI_5_1_MSI_NOT_SUPPORTED BIT3
-#define EFI_ACPI_5_1_PCIE_ASPM_CONTROLS BIT4
-#define EFI_ACPI_5_1_CMOS_RTC_NOT_PRESENT BIT5
+#define EFI_ACPI_5_1_LEGACY_DEVICES BIT0
+#define EFI_ACPI_5_1_8042 BIT1
+#define EFI_ACPI_5_1_VGA_NOT_PRESENT BIT2
+#define EFI_ACPI_5_1_MSI_NOT_SUPPORTED BIT3
+#define EFI_ACPI_5_1_PCIE_ASPM_CONTROLS BIT4
+#define EFI_ACPI_5_1_CMOS_RTC_NOT_PRESENT BIT5
//
// Fixed ACPI Description Table Arm Boot Architecture Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_5_1_ARM_PSCI_COMPLIANT BIT0
-#define EFI_ACPI_5_1_ARM_PSCI_USE_HVC BIT1
+#define EFI_ACPI_5_1_ARM_PSCI_COMPLIANT BIT0
+#define EFI_ACPI_5_1_ARM_PSCI_USE_HVC BIT1
//
// Fixed ACPI Description Table Fixed Feature Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_5_1_WBINVD BIT0
-#define EFI_ACPI_5_1_WBINVD_FLUSH BIT1
-#define EFI_ACPI_5_1_PROC_C1 BIT2
-#define EFI_ACPI_5_1_P_LVL2_UP BIT3
-#define EFI_ACPI_5_1_PWR_BUTTON BIT4
-#define EFI_ACPI_5_1_SLP_BUTTON BIT5
-#define EFI_ACPI_5_1_FIX_RTC BIT6
-#define EFI_ACPI_5_1_RTC_S4 BIT7
-#define EFI_ACPI_5_1_TMR_VAL_EXT BIT8
-#define EFI_ACPI_5_1_DCK_CAP BIT9
-#define EFI_ACPI_5_1_RESET_REG_SUP BIT10
-#define EFI_ACPI_5_1_SEALED_CASE BIT11
-#define EFI_ACPI_5_1_HEADLESS BIT12
-#define EFI_ACPI_5_1_CPU_SW_SLP BIT13
-#define EFI_ACPI_5_1_PCI_EXP_WAK BIT14
-#define EFI_ACPI_5_1_USE_PLATFORM_CLOCK BIT15
-#define EFI_ACPI_5_1_S4_RTC_STS_VALID BIT16
-#define EFI_ACPI_5_1_REMOTE_POWER_ON_CAPABLE BIT17
-#define EFI_ACPI_5_1_FORCE_APIC_CLUSTER_MODEL BIT18
-#define EFI_ACPI_5_1_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
-#define EFI_ACPI_5_1_HW_REDUCED_ACPI BIT20
-#define EFI_ACPI_5_1_LOW_POWER_S0_IDLE_CAPABLE BIT21
+#define EFI_ACPI_5_1_WBINVD BIT0
+#define EFI_ACPI_5_1_WBINVD_FLUSH BIT1
+#define EFI_ACPI_5_1_PROC_C1 BIT2
+#define EFI_ACPI_5_1_P_LVL2_UP BIT3
+#define EFI_ACPI_5_1_PWR_BUTTON BIT4
+#define EFI_ACPI_5_1_SLP_BUTTON BIT5
+#define EFI_ACPI_5_1_FIX_RTC BIT6
+#define EFI_ACPI_5_1_RTC_S4 BIT7
+#define EFI_ACPI_5_1_TMR_VAL_EXT BIT8
+#define EFI_ACPI_5_1_DCK_CAP BIT9
+#define EFI_ACPI_5_1_RESET_REG_SUP BIT10
+#define EFI_ACPI_5_1_SEALED_CASE BIT11
+#define EFI_ACPI_5_1_HEADLESS BIT12
+#define EFI_ACPI_5_1_CPU_SW_SLP BIT13
+#define EFI_ACPI_5_1_PCI_EXP_WAK BIT14
+#define EFI_ACPI_5_1_USE_PLATFORM_CLOCK BIT15
+#define EFI_ACPI_5_1_S4_RTC_STS_VALID BIT16
+#define EFI_ACPI_5_1_REMOTE_POWER_ON_CAPABLE BIT17
+#define EFI_ACPI_5_1_FORCE_APIC_CLUSTER_MODEL BIT18
+#define EFI_ACPI_5_1_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+#define EFI_ACPI_5_1_HW_REDUCED_ACPI BIT20
+#define EFI_ACPI_5_1_LOW_POWER_S0_IDLE_CAPABLE BIT21
///
/// Firmware ACPI Control Structure
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
- UINT32 HardwareSignature;
- UINT32 FirmwareWakingVector;
- UINT32 GlobalLock;
- UINT32 Flags;
- UINT64 XFirmwareWakingVector;
- UINT8 Version;
- UINT8 Reserved0[3];
- UINT32 OspmFlags;
- UINT8 Reserved1[24];
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved0[3];
+ UINT32 OspmFlags;
+ UINT8 Reserved1[24];
} EFI_ACPI_5_1_FIRMWARE_ACPI_CONTROL_STRUCTURE;
///
@@ -255,14 +255,14 @@ typedef struct {
/// Firmware Control Structure Feature Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_5_1_S4BIOS_F BIT0
-#define EFI_ACPI_5_1_64BIT_WAKE_SUPPORTED_F BIT1
+#define EFI_ACPI_5_1_S4BIOS_F BIT0
+#define EFI_ACPI_5_1_64BIT_WAKE_SUPPORTED_F BIT1
///
/// OSPM Enabled Firmware Control Structure Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_5_1_OSPM_64BIT_WAKE_F BIT0
+#define EFI_ACPI_5_1_OSPM_64BIT_WAKE_F BIT0
//
// Differentiated System Description Table,
@@ -271,29 +271,29 @@ typedef struct {
// no definition needed as they are common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
//
-#define EFI_ACPI_5_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
-#define EFI_ACPI_5_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_5_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_5_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
///
/// Multiple APIC Description Table header definition. The rest of the table
/// must be defined in a platform specific manner.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 LocalApicAddress;
- UINT32 Flags;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
} EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
///
/// MADT Revision (as defined in ACPI 5.1 spec.)
///
-#define EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03
+#define EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03
///
/// Multiple APIC Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_5_1_PCAT_COMPAT BIT0
+#define EFI_ACPI_5_1_PCAT_COMPAT BIT0
//
// Multiple APIC Description Table APIC structure types
@@ -324,57 +324,57 @@ typedef struct {
/// Processor Local APIC Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT8 ApicId;
- UINT32 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 ApicId;
+ UINT32 Flags;
} EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_STRUCTURE;
///
/// Local APIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_5_1_LOCAL_APIC_ENABLED BIT0
+#define EFI_ACPI_5_1_LOCAL_APIC_ENABLED BIT0
///
/// IO APIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 IoApicAddress;
- UINT32 GlobalSystemInterruptBase;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
} EFI_ACPI_5_1_IO_APIC_STRUCTURE;
///
/// Interrupt Source Override Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Bus;
- UINT8 Source;
- UINT32 GlobalSystemInterrupt;
- UINT16 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
} EFI_ACPI_5_1_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
///
/// Platform Interrupt Sources Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT8 InterruptType;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT8 IoSapicVector;
- UINT32 GlobalSystemInterrupt;
- UINT32 PlatformInterruptSourceFlags;
- UINT8 CpeiProcessorOverride;
- UINT8 Reserved[31];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
} EFI_ACPI_5_1_PLATFORM_INTERRUPT_APIC_STRUCTURE;
//
@@ -388,43 +388,43 @@ typedef struct {
/// Non-Maskable Interrupt Source Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT32 GlobalSystemInterrupt;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
} EFI_ACPI_5_1_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
///
/// Local APIC NMI Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT16 Flags;
- UINT8 LocalApicLint;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
} EFI_ACPI_5_1_LOCAL_APIC_NMI_STRUCTURE;
///
/// Local APIC Address Override Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT64 LocalApicAddress;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
} EFI_ACPI_5_1_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
///
/// IO SAPIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 GlobalSystemInterruptBase;
- UINT64 IoSapicAddress;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
} EFI_ACPI_5_1_IO_SAPIC_STRUCTURE;
///
@@ -432,155 +432,155 @@ typedef struct {
/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT8 LocalSapicId;
- UINT8 LocalSapicEid;
- UINT8 Reserved[3];
- UINT32 Flags;
- UINT32 ACPIProcessorUIDValue;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
} EFI_ACPI_5_1_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
///
/// Platform Interrupt Sources Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT8 InterruptType;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT8 IoSapicVector;
- UINT32 GlobalSystemInterrupt;
- UINT32 PlatformInterruptSourceFlags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
} EFI_ACPI_5_1_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
///
/// Platform Interrupt Source Flags.
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_5_1_CPEI_PROCESSOR_OVERRIDE BIT0
+#define EFI_ACPI_5_1_CPEI_PROCESSOR_OVERRIDE BIT0
///
/// Processor Local x2APIC Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[2];
- UINT32 X2ApicId;
- UINT32 Flags;
- UINT32 AcpiProcessorUid;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 AcpiProcessorUid;
} EFI_ACPI_5_1_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
///
/// Local x2APIC NMI Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT32 AcpiProcessorUid;
- UINT8 LocalX2ApicLint;
- UINT8 Reserved[3];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 AcpiProcessorUid;
+ UINT8 LocalX2ApicLint;
+ UINT8 Reserved[3];
} EFI_ACPI_5_1_LOCAL_X2APIC_NMI_STRUCTURE;
///
/// GIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT32 CPUInterfaceNumber;
- UINT32 AcpiProcessorUid;
- UINT32 Flags;
- UINT32 ParkingProtocolVersion;
- UINT32 PerformanceInterruptGsiv;
- UINT64 ParkedAddress;
- UINT64 PhysicalBaseAddress;
- UINT64 GICV;
- UINT64 GICH;
- UINT32 VGICMaintenanceInterrupt;
- UINT64 GICRBaseAddress;
- UINT64 MPIDR;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 CPUInterfaceNumber;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ParkingProtocolVersion;
+ UINT32 PerformanceInterruptGsiv;
+ UINT64 ParkedAddress;
+ UINT64 PhysicalBaseAddress;
+ UINT64 GICV;
+ UINT64 GICH;
+ UINT32 VGICMaintenanceInterrupt;
+ UINT64 GICRBaseAddress;
+ UINT64 MPIDR;
} EFI_ACPI_5_1_GIC_STRUCTURE;
///
/// GIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_5_1_GIC_ENABLED BIT0
-#define EFI_ACPI_5_1_PERFORMANCE_INTERRUPT_MODEL BIT1
-#define EFI_ACPI_5_1_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2
+#define EFI_ACPI_5_1_GIC_ENABLED BIT0
+#define EFI_ACPI_5_1_PERFORMANCE_INTERRUPT_MODEL BIT1
+#define EFI_ACPI_5_1_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2
///
/// GIC Distributor Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved1;
- UINT32 GicId;
- UINT64 PhysicalBaseAddress;
- UINT32 SystemVectorBase;
- UINT8 GicVersion;
- UINT8 Reserved2[3];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 SystemVectorBase;
+ UINT8 GicVersion;
+ UINT8 Reserved2[3];
} EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE;
///
/// GIC Version
///
-#define EFI_ACPI_5_1_GIC_V1 0x01
-#define EFI_ACPI_5_1_GIC_V2 0x02
-#define EFI_ACPI_5_1_GIC_V3 0x03
-#define EFI_ACPI_5_1_GIC_V4 0x04
+#define EFI_ACPI_5_1_GIC_V1 0x01
+#define EFI_ACPI_5_1_GIC_V2 0x02
+#define EFI_ACPI_5_1_GIC_V3 0x03
+#define EFI_ACPI_5_1_GIC_V4 0x04
///
/// GIC MSI Frame Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved1;
- UINT32 GicMsiFrameId;
- UINT64 PhysicalBaseAddress;
- UINT32 Flags;
- UINT16 SPICount;
- UINT16 SPIBase;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicMsiFrameId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Flags;
+ UINT16 SPICount;
+ UINT16 SPIBase;
} EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE;
///
/// GIC MSI Frame Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_5_1_SPI_COUNT_BASE_SELECT BIT0
+#define EFI_ACPI_5_1_SPI_COUNT_BASE_SELECT BIT0
///
/// GICR Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT64 DiscoveryRangeBaseAddress;
- UINT32 DiscoveryRangeLength;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 DiscoveryRangeBaseAddress;
+ UINT32 DiscoveryRangeLength;
} EFI_ACPI_5_1_GICR_STRUCTURE;
///
/// Smart Battery Description Table (SBST)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 WarningEnergyLevel;
- UINT32 LowEnergyLevel;
- UINT32 CriticalEnergyLevel;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
} EFI_ACPI_5_1_SMART_BATTERY_DESCRIPTION_TABLE;
///
/// SBST Version (as defined in ACPI 5.1 spec.)
///
-#define EFI_ACPI_5_1_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_5_1_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
///
/// Embedded Controller Boot Resources Table (ECDT)
@@ -588,11 +588,11 @@ typedef struct {
/// a fully qualified reference to the name space object.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE EcControl;
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE EcData;
- UINT32 Uid;
- UINT8 GpeBit;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
} EFI_ACPI_5_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
///
@@ -605,9 +605,9 @@ typedef struct {
/// must be defined in a platform specific manner.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Reserved1; ///< Must be set to 1
- UINT64 Reserved2;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; ///< Must be set to 1
+ UINT64 Reserved2;
} EFI_ACPI_5_1_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
///
@@ -629,83 +629,83 @@ typedef struct {
/// Processor Local APIC/SAPIC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 ProximityDomain7To0;
- UINT8 ApicId;
- UINT32 Flags;
- UINT8 LocalSapicEid;
- UINT8 ProximityDomain31To8[3];
- UINT32 ClockDomain;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT32 ClockDomain;
} EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
///
/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+#define EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
///
/// Memory Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 ProximityDomain;
- UINT16 Reserved1;
- UINT32 AddressBaseLow;
- UINT32 AddressBaseHigh;
- UINT32 LengthLow;
- UINT32 LengthHigh;
- UINT32 Reserved2;
- UINT32 Flags;
- UINT64 Reserved3;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
} EFI_ACPI_5_1_MEMORY_AFFINITY_STRUCTURE;
//
// Memory Flags. All other bits are reserved and must be 0.
//
-#define EFI_ACPI_5_1_MEMORY_ENABLED (1 << 0)
-#define EFI_ACPI_5_1_MEMORY_HOT_PLUGGABLE (1 << 1)
-#define EFI_ACPI_5_1_MEMORY_NONVOLATILE (1 << 2)
+#define EFI_ACPI_5_1_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_5_1_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_5_1_MEMORY_NONVOLATILE (1 << 2)
///
/// Processor Local x2APIC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved1[2];
- UINT32 ProximityDomain;
- UINT32 X2ApicId;
- UINT32 Flags;
- UINT32 ClockDomain;
- UINT8 Reserved2[4];
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1[2];
+ UINT32 ProximityDomain;
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+ UINT8 Reserved2[4];
} EFI_ACPI_5_1_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
///
/// GICC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 ProximityDomain;
- UINT32 AcpiProcessorUid;
- UINT32 Flags;
- UINT32 ClockDomain;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ClockDomain;
} EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE;
///
/// GICC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_5_1_GICC_ENABLED (1 << 0)
+#define EFI_ACPI_5_1_GICC_ENABLED (1 << 0)
///
/// System Locality Distance Information Table (SLIT).
/// The rest of the table is a matrix.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 NumberOfSystemLocalities;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
} EFI_ACPI_5_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
///
@@ -717,14 +717,14 @@ typedef struct {
/// Corrected Platform Error Polling Table (CPEP)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 Reserved[8];
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[8];
} EFI_ACPI_5_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
///
/// CPEP Version (as defined in ACPI 5.1 spec.)
///
-#define EFI_ACPI_5_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+#define EFI_ACPI_5_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
//
// CPEP processor structure types.
@@ -735,66 +735,66 @@ typedef struct {
/// Corrected Platform Error Polling Processor Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT32 PollingInterval;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT32 PollingInterval;
} EFI_ACPI_5_1_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
///
/// Maximum System Characteristics Table (MSCT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 OffsetProxDomInfo;
- UINT32 MaximumNumberOfProximityDomains;
- UINT32 MaximumNumberOfClockDomains;
- UINT64 MaximumPhysicalAddress;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 OffsetProxDomInfo;
+ UINT32 MaximumNumberOfProximityDomains;
+ UINT32 MaximumNumberOfClockDomains;
+ UINT64 MaximumPhysicalAddress;
} EFI_ACPI_5_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
///
/// MSCT Version (as defined in ACPI 5.1 spec.)
///
-#define EFI_ACPI_5_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+#define EFI_ACPI_5_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
///
/// Maximum Proximity Domain Information Structure Definition
///
typedef struct {
- UINT8 Revision;
- UINT8 Length;
- UINT32 ProximityDomainRangeLow;
- UINT32 ProximityDomainRangeHigh;
- UINT32 MaximumProcessorCapacity;
- UINT64 MaximumMemoryCapacity;
+ UINT8 Revision;
+ UINT8 Length;
+ UINT32 ProximityDomainRangeLow;
+ UINT32 ProximityDomainRangeHigh;
+ UINT32 MaximumProcessorCapacity;
+ UINT64 MaximumMemoryCapacity;
} EFI_ACPI_5_1_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
///
/// ACPI RAS Feature Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 PlatformCommunicationChannelIdentifier[12];
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier[12];
} EFI_ACPI_5_1_RAS_FEATURE_TABLE;
///
/// RASF Version (as defined in ACPI 5.1 spec.)
///
-#define EFI_ACPI_5_1_RAS_FEATURE_TABLE_REVISION 0x01
+#define EFI_ACPI_5_1_RAS_FEATURE_TABLE_REVISION 0x01
///
/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
///
typedef struct {
- UINT32 Signature;
- UINT16 Command;
- UINT16 Status;
- UINT16 Version;
- UINT8 RASCapabilities[16];
- UINT8 SetRASCapabilities[16];
- UINT16 NumberOfRASFParameterBlocks;
- UINT32 SetRASCapabilitiesStatus;
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT16 Version;
+ UINT8 RASCapabilities[16];
+ UINT8 SetRASCapabilities[16];
+ UINT16 NumberOfRASFParameterBlocks;
+ UINT32 SetRASCapabilitiesStatus;
} EFI_ACPI_5_1_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
///
@@ -812,52 +812,52 @@ typedef struct {
/// ACPI RASF Parameter Block structure for PATROL_SCRUB
///
typedef struct {
- UINT16 Type;
- UINT16 Version;
- UINT16 Length;
- UINT16 PatrolScrubCommand;
- UINT64 RequestedAddressRange[2];
- UINT64 ActualAddressRange[2];
- UINT16 Flags;
- UINT8 RequestedSpeed;
+ UINT16 Type;
+ UINT16 Version;
+ UINT16 Length;
+ UINT16 PatrolScrubCommand;
+ UINT64 RequestedAddressRange[2];
+ UINT64 ActualAddressRange[2];
+ UINT16 Flags;
+ UINT8 RequestedSpeed;
} EFI_ACPI_5_1_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
///
/// ACPI RASF Patrol Scrub command
///
-#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
-#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
-#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
+#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
+#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
+#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
///
/// Memory Power State Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 PlatformCommunicationChannelIdentifier;
- UINT8 Reserved[3];
-// Memory Power Node Structure
-// Memory Power State Characteristics
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier;
+ UINT8 Reserved[3];
+ // Memory Power Node Structure
+ // Memory Power State Characteristics
} EFI_ACPI_5_1_MEMORY_POWER_STATUS_TABLE;
///
/// MPST Version (as defined in ACPI 5.1 spec.)
///
-#define EFI_ACPI_5_1_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+#define EFI_ACPI_5_1_MEMORY_POWER_STATE_TABLE_REVISION 0x01
///
/// MPST Platform Communication Channel Shared Memory Region definition.
///
typedef struct {
- UINT32 Signature;
- UINT16 Command;
- UINT16 Status;
- UINT32 MemoryPowerCommandRegister;
- UINT32 MemoryPowerStatusRegister;
- UINT32 PowerStateId;
- UINT32 MemoryPowerNodeId;
- UINT64 MemoryEnergyConsumed;
- UINT64 ExpectedAveragePowerComsuned;
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT32 MemoryPowerCommandRegister;
+ UINT32 MemoryPowerStatusRegister;
+ UINT32 PowerStateId;
+ UINT32 MemoryPowerNodeId;
+ UINT64 MemoryEnergyConsumed;
+ UINT64 ExpectedAveragePowerComsuned;
} EFI_ACPI_5_1_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
///
@@ -868,186 +868,186 @@ typedef struct {
///
/// ACPI MPST Memory Power command
///
-#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
-#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
-#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
-#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
///
/// MPST Memory Power Node Table
///
typedef struct {
- UINT8 PowerStateValue;
- UINT8 PowerStateInformationIndex;
+ UINT8 PowerStateValue;
+ UINT8 PowerStateInformationIndex;
} EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE;
typedef struct {
- UINT8 Flag;
- UINT8 Reserved;
- UINT16 MemoryPowerNodeId;
- UINT32 Length;
- UINT64 AddressBase;
- UINT64 AddressLength;
- UINT32 NumberOfPowerStates;
- UINT32 NumberOfPhysicalComponents;
-//EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
-//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+ UINT8 Flag;
+ UINT8 Reserved;
+ UINT16 MemoryPowerNodeId;
+ UINT32 Length;
+ UINT64 AddressBase;
+ UINT64 AddressLength;
+ UINT32 NumberOfPowerStates;
+ UINT32 NumberOfPhysicalComponents;
+ // EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
} EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE;
-#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
-#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
-#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
typedef struct {
- UINT16 MemoryPowerNodeCount;
- UINT8 Reserved[2];
+ UINT16 MemoryPowerNodeCount;
+ UINT8 Reserved[2];
} EFI_ACPI_5_1_MPST_MEMORY_POWER_NODE_TABLE;
///
/// MPST Memory Power State Characteristics Table
///
typedef struct {
- UINT8 PowerStateStructureID;
- UINT8 Flag;
- UINT16 Reserved;
- UINT32 AveragePowerConsumedInMPS0;
- UINT32 RelativePowerSavingToMPS0;
- UINT64 ExitLatencyToMPS0;
+ UINT8 PowerStateStructureID;
+ UINT8 Flag;
+ UINT16 Reserved;
+ UINT32 AveragePowerConsumedInMPS0;
+ UINT32 RelativePowerSavingToMPS0;
+ UINT64 ExitLatencyToMPS0;
} EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
-#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
-#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
-#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
typedef struct {
- UINT16 MemoryPowerStateCharacteristicsCount;
- UINT8 Reserved[2];
+ UINT16 MemoryPowerStateCharacteristicsCount;
+ UINT8 Reserved[2];
} EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
///
/// Memory Topology Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
} EFI_ACPI_5_1_MEMORY_TOPOLOGY_TABLE;
///
/// PMTT Version (as defined in ACPI 5.1 spec.)
///
-#define EFI_ACPI_5_1_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
+#define EFI_ACPI_5_1_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
///
/// Common Memory Aggregator Device Structure.
///
typedef struct {
- UINT8 Type;
- UINT8 Reserved;
- UINT16 Length;
- UINT16 Flags;
- UINT16 Reserved1;
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16 Length;
+ UINT16 Flags;
+ UINT16 Reserved1;
} EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// Memory Aggregator Device Type
///
-#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0
-#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
-#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2
+#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0
+#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
+#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2
///
/// Socket Memory Aggregator Device Structure.
///
typedef struct {
- EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
- UINT16 SocketIdentifier;
- UINT16 Reserved;
-//EFI_ACPI_5_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];
+ EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 SocketIdentifier;
+ UINT16 Reserved;
+ // EFI_ACPI_5_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];
} EFI_ACPI_5_1_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// MemoryController Memory Aggregator Device Structure.
///
typedef struct {
- EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
- UINT32 ReadLatency;
- UINT32 WriteLatency;
- UINT32 ReadBandwidth;
- UINT32 WriteBandwidth;
- UINT16 OptimalAccessUnit;
- UINT16 OptimalAccessAlignment;
- UINT16 Reserved;
- UINT16 NumberOfProximityDomains;
-//UINT32 ProximityDomain[NumberOfProximityDomains];
-//EFI_ACPI_5_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];
+ EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT32 ReadLatency;
+ UINT32 WriteLatency;
+ UINT32 ReadBandwidth;
+ UINT32 WriteBandwidth;
+ UINT16 OptimalAccessUnit;
+ UINT16 OptimalAccessAlignment;
+ UINT16 Reserved;
+ UINT16 NumberOfProximityDomains;
+ // UINT32 ProximityDomain[NumberOfProximityDomains];
+ // EFI_ACPI_5_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];
} EFI_ACPI_5_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// DIMM Memory Aggregator Device Structure.
///
typedef struct {
- EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
- UINT16 PhysicalComponentIdentifier;
- UINT16 Reserved;
- UINT32 SizeOfDimm;
- UINT32 SmbiosHandle;
+ EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 PhysicalComponentIdentifier;
+ UINT16 Reserved;
+ UINT32 SizeOfDimm;
+ UINT32 SmbiosHandle;
} EFI_ACPI_5_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// Boot Graphics Resource Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
///
/// 2-bytes (16 bit) version ID. This value must be 1.
///
- UINT16 Version;
+ UINT16 Version;
///
/// 1-byte status field indicating current status about the table.
/// Bits[7:1] = Reserved (must be zero)
/// Bit [0] = Valid. A one indicates the boot image graphic is valid.
///
- UINT8 Status;
+ UINT8 Status;
///
/// 1-byte enumerated type field indicating format of the image.
/// 0 = Bitmap
/// 1 - 255 Reserved (for future use)
///
- UINT8 ImageType;
+ UINT8 ImageType;
///
/// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
/// of the image bitmap.
///
- UINT64 ImageAddress;
+ UINT64 ImageAddress;
///
/// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
/// (X, Y) display offset of the top left corner of the boot image.
/// The top left corner of the display is at offset (0, 0).
///
- UINT32 ImageOffsetX;
+ UINT32 ImageOffsetX;
///
/// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
/// (X, Y) display offset of the top left corner of the boot image.
/// The top left corner of the display is at offset (0, 0).
///
- UINT32 ImageOffsetY;
+ UINT32 ImageOffsetY;
} EFI_ACPI_5_1_BOOT_GRAPHICS_RESOURCE_TABLE;
///
/// BGRT Revision
///
-#define EFI_ACPI_5_1_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+#define EFI_ACPI_5_1_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
///
/// BGRT Version
///
-#define EFI_ACPI_5_1_BGRT_VERSION 0x01
+#define EFI_ACPI_5_1_BGRT_VERSION 0x01
///
/// BGRT Status
///
-#define EFI_ACPI_5_1_BGRT_STATUS_NOT_DISPLAYED 0x00
-#define EFI_ACPI_5_1_BGRT_STATUS_DISPLAYED 0x01
+#define EFI_ACPI_5_1_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_5_1_BGRT_STATUS_DISPLAYED 0x01
///
/// BGRT Image Type
@@ -1057,26 +1057,26 @@ typedef struct {
///
/// FPDT Version (as defined in ACPI 5.1 spec.)
///
-#define EFI_ACPI_5_1_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+#define EFI_ACPI_5_1_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
///
/// FPDT Performance Record Types
///
-#define EFI_ACPI_5_1_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
-#define EFI_ACPI_5_1_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
+#define EFI_ACPI_5_1_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
+#define EFI_ACPI_5_1_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
///
/// FPDT Performance Record Revision
///
-#define EFI_ACPI_5_1_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
-#define EFI_ACPI_5_1_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+#define EFI_ACPI_5_1_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
+#define EFI_ACPI_5_1_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
///
/// FPDT Runtime Performance Record Types
///
-#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
-#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
-#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
+#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
+#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
+#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
///
/// FPDT Runtime Performance Record Revision
@@ -1089,77 +1089,77 @@ typedef struct {
/// FPDT Performance Record header
///
typedef struct {
- UINT16 Type;
- UINT8 Length;
- UINT8 Revision;
+ UINT16 Type;
+ UINT8 Length;
+ UINT8 Revision;
} EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER;
///
/// FPDT Performance Table header
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
+ UINT32 Signature;
+ UINT32 Length;
} EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER;
///
/// FPDT Firmware Basic Boot Performance Pointer Record Structure
///
typedef struct {
- EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
///
/// 64-bit processor-relative physical address of the Basic Boot Performance Table.
///
- UINT64 BootPerformanceTablePointer;
+ UINT64 BootPerformanceTablePointer;
} EFI_ACPI_5_1_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
///
/// FPDT S3 Performance Table Pointer Record Structure
///
typedef struct {
- EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
///
/// 64-bit processor-relative physical address of the S3 Performance Table.
///
- UINT64 S3PerformanceTablePointer;
+ UINT64 S3PerformanceTablePointer;
} EFI_ACPI_5_1_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
///
/// FPDT Firmware Basic Boot Performance Record Structure
///
typedef struct {
- EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
///
/// Timer value logged at the beginning of firmware image execution.
/// This may not always be zero or near zero.
///
- UINT64 ResetEnd;
+ UINT64 ResetEnd;
///
/// Timer value logged just prior to loading the OS boot loader into memory.
/// For non-UEFI compatible boots, this field must be zero.
///
- UINT64 OsLoaderLoadImageStart;
+ UINT64 OsLoaderLoadImageStart;
///
/// Timer value logged just prior to launching the previously loaded OS boot loader image.
/// For non-UEFI compatible boots, the timer value logged will be just prior
/// to the INT 19h handler invocation.
///
- UINT64 OsLoaderStartImageStart;
+ UINT64 OsLoaderStartImageStart;
///
/// Timer value logged at the point when the OS loader calls the
/// ExitBootServices function for UEFI compatible firmware.
/// For non-UEFI compatible boots, this field must be zero.
///
- UINT64 ExitBootServicesEntry;
+ UINT64 ExitBootServicesEntry;
///
/// Timer value logged at the point just prior to when the OS loader gaining
/// control back from calls the ExitBootServices function for UEFI compatible firmware.
/// For non-UEFI compatible boots, this field must be zero.
///
- UINT64 ExitBootServicesExit;
+ UINT64 ExitBootServicesExit;
} EFI_ACPI_5_1_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
///
@@ -1171,7 +1171,7 @@ typedef struct {
// FPDT Firmware Basic Boot Performance Table
//
typedef struct {
- EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER Header;
//
// one or more Performance Records.
//
@@ -1186,7 +1186,7 @@ typedef struct {
// FPDT Firmware S3 Boot Performance Table
//
typedef struct {
- EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER Header;
//
// one or more Performance Records.
//
@@ -1196,203 +1196,209 @@ typedef struct {
/// FPDT Basic S3 Resume Performance Record
///
typedef struct {
- EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
///
/// A count of the number of S3 resume cycles since the last full boot sequence.
///
- UINT32 ResumeCount;
+ UINT32 ResumeCount;
///
/// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
/// OS waking vector. Only the most recent resume cycle's time is retained.
///
- UINT64 FullResume;
+ UINT64 FullResume;
///
/// Average timer value of all resume cycles logged since the last full boot
/// sequence, including the most recent resume. Note that the entire log of
/// timer values does not need to be retained in order to calculate this average.
///
- UINT64 AverageResume;
+ UINT64 AverageResume;
} EFI_ACPI_5_1_FPDT_S3_RESUME_RECORD;
///
/// FPDT Basic S3 Suspend Performance Record
///
typedef struct {
- EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
///
/// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
/// Only the most recent suspend cycle's timer value is retained.
///
- UINT64 SuspendStart;
+ UINT64 SuspendStart;
///
/// Timer value recorded at the final firmware write to SLP_TYP (or other
/// mechanism) used to trigger hardware entry to S3.
/// Only the most recent suspend cycle's timer value is retained.
///
- UINT64 SuspendEnd;
+ UINT64 SuspendEnd;
} EFI_ACPI_5_1_FPDT_S3_SUSPEND_RECORD;
///
/// Firmware Performance Record Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
} EFI_ACPI_5_1_FIRMWARE_PERFORMANCE_RECORD_TABLE;
///
/// Generic Timer Description Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 CntControlBasePhysicalAddress;
- UINT32 Reserved;
- UINT32 SecurePL1TimerGSIV;
- UINT32 SecurePL1TimerFlags;
- UINT32 NonSecurePL1TimerGSIV;
- UINT32 NonSecurePL1TimerFlags;
- UINT32 VirtualTimerGSIV;
- UINT32 VirtualTimerFlags;
- UINT32 NonSecurePL2TimerGSIV;
- UINT32 NonSecurePL2TimerFlags;
- UINT64 CntReadBasePhysicalAddress;
- UINT32 PlatformTimerCount;
- UINT32 PlatformTimerOffset;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 CntControlBasePhysicalAddress;
+ UINT32 Reserved;
+ UINT32 SecurePL1TimerGSIV;
+ UINT32 SecurePL1TimerFlags;
+ UINT32 NonSecurePL1TimerGSIV;
+ UINT32 NonSecurePL1TimerFlags;
+ UINT32 VirtualTimerGSIV;
+ UINT32 VirtualTimerFlags;
+ UINT32 NonSecurePL2TimerGSIV;
+ UINT32 NonSecurePL2TimerFlags;
+ UINT64 CntReadBasePhysicalAddress;
+ UINT32 PlatformTimerCount;
+ UINT32 PlatformTimerOffset;
} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE;
///
/// GTDT Version (as defined in ACPI 5.1 spec.)
///
-#define EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02
///
/// Timer Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
-#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
-#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2
+#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2
///
/// Platform Timer Type
///
-#define EFI_ACPI_5_1_GTDT_GT_BLOCK 0
-#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG 1
+#define EFI_ACPI_5_1_GTDT_GT_BLOCK 0
+#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG 1
///
/// GT Block Structure
///
typedef struct {
- UINT8 Type;
- UINT16 Length;
- UINT8 Reserved;
- UINT64 CntCtlBase;
- UINT32 GTBlockTimerCount;
- UINT32 GTBlockTimerOffset;
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 CntCtlBase;
+ UINT32 GTBlockTimerCount;
+ UINT32 GTBlockTimerOffset;
} EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE;
///
/// GT Block Timer Structure
///
typedef struct {
- UINT8 GTFrameNumber;
- UINT8 Reserved[3];
- UINT64 CntBaseX;
- UINT64 CntEL0BaseX;
- UINT32 GTxPhysicalTimerGSIV;
- UINT32 GTxPhysicalTimerFlags;
- UINT32 GTxVirtualTimerGSIV;
- UINT32 GTxVirtualTimerFlags;
- UINT32 GTxCommonFlags;
+ UINT8 GTFrameNumber;
+ UINT8 Reserved[3];
+ UINT64 CntBaseX;
+ UINT64 CntEL0BaseX;
+ UINT32 GTxPhysicalTimerGSIV;
+ UINT32 GTxPhysicalTimerFlags;
+ UINT32 GTxVirtualTimerGSIV;
+ UINT32 GTxVirtualTimerFlags;
+ UINT32 GTxCommonFlags;
} EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_STRUCTURE;
///
/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
-#define EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
///
/// Common Flags Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0
-#define EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1
+#define EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0
+#define EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1
///
/// SBSA Generic Watchdog Structure
///
typedef struct {
- UINT8 Type;
- UINT16 Length;
- UINT8 Reserved;
- UINT64 RefreshFramePhysicalAddress;
- UINT64 WatchdogControlFramePhysicalAddress;
- UINT32 WatchdogTimerGSIV;
- UINT32 WatchdogTimerFlags;
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 RefreshFramePhysicalAddress;
+ UINT64 WatchdogControlFramePhysicalAddress;
+ UINT32 WatchdogTimerGSIV;
+ UINT32 WatchdogTimerFlags;
} EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;
///
/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0
-#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1
-#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2
+#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2
///
/// Boot Error Record Table (BERT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 BootErrorRegionLength;
- UINT64 BootErrorRegion;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 BootErrorRegionLength;
+ UINT64 BootErrorRegion;
} EFI_ACPI_5_1_BOOT_ERROR_RECORD_TABLE_HEADER;
///
/// BERT Version (as defined in ACPI 5.1 spec.)
///
-#define EFI_ACPI_5_1_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+#define EFI_ACPI_5_1_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
///
/// Boot Error Region Block Status Definition
///
typedef struct {
- UINT32 UncorrectableErrorValid:1;
- UINT32 CorrectableErrorValid:1;
- UINT32 MultipleUncorrectableErrors:1;
- UINT32 MultipleCorrectableErrors:1;
- UINT32 ErrorDataEntryCount:10;
- UINT32 Reserved:18;
+ UINT32 UncorrectableErrorValid : 1;
+ UINT32 CorrectableErrorValid : 1;
+ UINT32 MultipleUncorrectableErrors : 1;
+ UINT32 MultipleCorrectableErrors : 1;
+ UINT32 ErrorDataEntryCount : 10;
+ UINT32 Reserved : 18;
} EFI_ACPI_5_1_ERROR_BLOCK_STATUS;
///
/// Boot Error Region Definition
///
typedef struct {
- EFI_ACPI_5_1_ERROR_BLOCK_STATUS BlockStatus;
- UINT32 RawDataOffset;
- UINT32 RawDataLength;
- UINT32 DataLength;
- UINT32 ErrorSeverity;
+ EFI_ACPI_5_1_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
} EFI_ACPI_5_1_BOOT_ERROR_REGION_STRUCTURE;
//
// Boot Error Severity types
//
-#define EFI_ACPI_5_1_ERROR_SEVERITY_CORRECTABLE 0x00
+#define EFI_ACPI_5_1_ERROR_SEVERITY_RECOVERABLE 0x00
#define EFI_ACPI_5_1_ERROR_SEVERITY_FATAL 0x01
#define EFI_ACPI_5_1_ERROR_SEVERITY_CORRECTED 0x02
#define EFI_ACPI_5_1_ERROR_SEVERITY_NONE 0x03
+//
+// The term 'Correctable' is no longer being used as an error severity of the
+// reported error since ACPI Specification Version 5.1 Errata B.
+// The below macro is considered as deprecated and should no longer be used.
+//
+#define EFI_ACPI_5_1_ERROR_SEVERITY_CORRECTABLE 0x00
///
/// Generic Error Data Entry Definition
///
typedef struct {
- UINT8 SectionType[16];
- UINT32 ErrorSeverity;
- UINT16 Revision;
- UINT8 ValidationBits;
- UINT8 Flags;
- UINT32 ErrorDataLength;
- UINT8 FruId[16];
- UINT8 FruText[20];
+ UINT8 SectionType[16];
+ UINT32 ErrorSeverity;
+ UINT16 Revision;
+ UINT8 ValidationBits;
+ UINT8 Flags;
+ UINT32 ErrorDataLength;
+ UINT8 FruId[16];
+ UINT8 FruText[20];
} EFI_ACPI_5_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
///
@@ -1404,14 +1410,14 @@ typedef struct {
/// HEST - Hardware Error Source Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 ErrorSourceCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 ErrorSourceCount;
} EFI_ACPI_5_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
///
/// HEST Version (as defined in ACPI 5.1 spec.)
///
-#define EFI_ACPI_5_1_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+#define EFI_ACPI_5_1_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
//
// Error Source structure types.
@@ -1427,403 +1433,403 @@ typedef struct {
//
// Error Source structure flags.
//
-#define EFI_ACPI_5_1_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
-#define EFI_ACPI_5_1_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
+#define EFI_ACPI_5_1_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
+#define EFI_ACPI_5_1_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
///
/// IA-32 Architecture Machine Check Exception Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT64 GlobalCapabilityInitData;
- UINT64 GlobalControlInitData;
- UINT8 NumberOfHardwareBanks;
- UINT8 Reserved1[7];
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT64 GlobalCapabilityInitData;
+ UINT64 GlobalControlInitData;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[7];
} EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
///
/// IA-32 Architecture Machine Check Bank Structure Definition
///
typedef struct {
- UINT8 BankNumber;
- UINT8 ClearStatusOnInitialization;
- UINT8 StatusDataFormat;
- UINT8 Reserved0;
- UINT32 ControlRegisterMsrAddress;
- UINT64 ControlInitData;
- UINT32 StatusRegisterMsrAddress;
- UINT32 AddressRegisterMsrAddress;
- UINT32 MiscRegisterMsrAddress;
+ UINT8 BankNumber;
+ UINT8 ClearStatusOnInitialization;
+ UINT8 StatusDataFormat;
+ UINT8 Reserved0;
+ UINT32 ControlRegisterMsrAddress;
+ UINT64 ControlInitData;
+ UINT32 StatusRegisterMsrAddress;
+ UINT32 AddressRegisterMsrAddress;
+ UINT32 MiscRegisterMsrAddress;
} EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
///
/// IA-32 Architecture Machine Check Bank Structure MCA data format
///
-#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
-#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
-#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
+#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
+#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
+#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
//
// Hardware Error Notification types. All other values are reserved
//
-#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
-#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
-#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
-#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
-#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
+#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
+#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
+#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
+#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
+#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
///
/// Hardware Error Notification Configuration Write Enable Structure Definition
///
typedef struct {
- UINT16 Type:1;
- UINT16 PollInterval:1;
- UINT16 SwitchToPollingThresholdValue:1;
- UINT16 SwitchToPollingThresholdWindow:1;
- UINT16 ErrorThresholdValue:1;
- UINT16 ErrorThresholdWindow:1;
- UINT16 Reserved:10;
+ UINT16 Type : 1;
+ UINT16 PollInterval : 1;
+ UINT16 SwitchToPollingThresholdValue : 1;
+ UINT16 SwitchToPollingThresholdWindow : 1;
+ UINT16 ErrorThresholdValue : 1;
+ UINT16 ErrorThresholdWindow : 1;
+ UINT16 Reserved : 10;
} EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
///
/// Hardware Error Notification Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
- UINT32 PollInterval;
- UINT32 Vector;
- UINT32 SwitchToPollingThresholdValue;
- UINT32 SwitchToPollingThresholdWindow;
- UINT32 ErrorThresholdValue;
- UINT32 ErrorThresholdWindow;
+ UINT8 Type;
+ UINT8 Length;
+ EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
+ UINT32 PollInterval;
+ UINT32 Vector;
+ UINT32 SwitchToPollingThresholdValue;
+ UINT32 SwitchToPollingThresholdWindow;
+ UINT32 ErrorThresholdValue;
+ UINT32 ErrorThresholdWindow;
} EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
///
/// IA-32 Architecture Corrected Machine Check Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
- UINT8 NumberOfHardwareBanks;
- UINT8 Reserved1[3];
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
} EFI_ACPI_5_1_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
///
/// IA-32 Architecture NMI Error Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 MaxRawDataLength;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
} EFI_ACPI_5_1_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
///
/// PCI Express Root Port AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
- UINT32 RootErrorCommand;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 RootErrorCommand;
} EFI_ACPI_5_1_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
///
/// PCI Express Device AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
} EFI_ACPI_5_1_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
///
/// PCI Express Bridge AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
- UINT32 SecondaryUncorrectableErrorMask;
- UINT32 SecondaryUncorrectableErrorSeverity;
- UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 SecondaryUncorrectableErrorMask;
+ UINT32 SecondaryUncorrectableErrorSeverity;
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
} EFI_ACPI_5_1_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
///
/// Generic Hardware Error Source Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT16 RelatedSourceId;
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 MaxRawDataLength;
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
- EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
- UINT32 ErrorStatusBlockLength;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
} EFI_ACPI_5_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
///
/// Generic Error Status Definition
///
typedef struct {
- EFI_ACPI_5_1_ERROR_BLOCK_STATUS BlockStatus;
- UINT32 RawDataOffset;
- UINT32 RawDataLength;
- UINT32 DataLength;
- UINT32 ErrorSeverity;
+ EFI_ACPI_5_1_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
} EFI_ACPI_5_1_GENERIC_ERROR_STATUS_STRUCTURE;
///
/// ERST - Error Record Serialization Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 SerializationHeaderSize;
- UINT8 Reserved0[4];
- UINT32 InstructionEntryCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 SerializationHeaderSize;
+ UINT8 Reserved0[4];
+ UINT32 InstructionEntryCount;
} EFI_ACPI_5_1_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
///
/// ERST Version (as defined in ACPI 5.1 spec.)
///
-#define EFI_ACPI_5_1_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+#define EFI_ACPI_5_1_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
///
/// ERST Serialization Actions
///
-#define EFI_ACPI_5_1_ERST_BEGIN_WRITE_OPERATION 0x00
-#define EFI_ACPI_5_1_ERST_BEGIN_READ_OPERATION 0x01
-#define EFI_ACPI_5_1_ERST_BEGIN_CLEAR_OPERATION 0x02
-#define EFI_ACPI_5_1_ERST_END_OPERATION 0x03
-#define EFI_ACPI_5_1_ERST_SET_RECORD_OFFSET 0x04
-#define EFI_ACPI_5_1_ERST_EXECUTE_OPERATION 0x05
-#define EFI_ACPI_5_1_ERST_CHECK_BUSY_STATUS 0x06
-#define EFI_ACPI_5_1_ERST_GET_COMMAND_STATUS 0x07
-#define EFI_ACPI_5_1_ERST_GET_RECORD_IDENTIFIER 0x08
-#define EFI_ACPI_5_1_ERST_SET_RECORD_IDENTIFIER 0x09
-#define EFI_ACPI_5_1_ERST_GET_RECORD_COUNT 0x0A
-#define EFI_ACPI_5_1_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
-#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
-#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
-#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
+#define EFI_ACPI_5_1_ERST_BEGIN_WRITE_OPERATION 0x00
+#define EFI_ACPI_5_1_ERST_BEGIN_READ_OPERATION 0x01
+#define EFI_ACPI_5_1_ERST_BEGIN_CLEAR_OPERATION 0x02
+#define EFI_ACPI_5_1_ERST_END_OPERATION 0x03
+#define EFI_ACPI_5_1_ERST_SET_RECORD_OFFSET 0x04
+#define EFI_ACPI_5_1_ERST_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_5_1_ERST_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_5_1_ERST_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_5_1_ERST_GET_RECORD_IDENTIFIER 0x08
+#define EFI_ACPI_5_1_ERST_SET_RECORD_IDENTIFIER 0x09
+#define EFI_ACPI_5_1_ERST_GET_RECORD_COUNT 0x0A
+#define EFI_ACPI_5_1_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
+#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
+#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
+#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
///
/// ERST Action Command Status
///
-#define EFI_ACPI_5_1_ERST_STATUS_SUCCESS 0x00
-#define EFI_ACPI_5_1_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
-#define EFI_ACPI_5_1_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
-#define EFI_ACPI_5_1_ERST_STATUS_FAILED 0x03
-#define EFI_ACPI_5_1_ERST_STATUS_RECORD_STORE_EMPTY 0x04
-#define EFI_ACPI_5_1_ERST_STATUS_RECORD_NOT_FOUND 0x05
+#define EFI_ACPI_5_1_ERST_STATUS_SUCCESS 0x00
+#define EFI_ACPI_5_1_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
+#define EFI_ACPI_5_1_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
+#define EFI_ACPI_5_1_ERST_STATUS_FAILED 0x03
+#define EFI_ACPI_5_1_ERST_STATUS_RECORD_STORE_EMPTY 0x04
+#define EFI_ACPI_5_1_ERST_STATUS_RECORD_NOT_FOUND 0x05
///
/// ERST Serialization Instructions
///
-#define EFI_ACPI_5_1_ERST_READ_REGISTER 0x00
-#define EFI_ACPI_5_1_ERST_READ_REGISTER_VALUE 0x01
-#define EFI_ACPI_5_1_ERST_WRITE_REGISTER 0x02
-#define EFI_ACPI_5_1_ERST_WRITE_REGISTER_VALUE 0x03
-#define EFI_ACPI_5_1_ERST_NOOP 0x04
-#define EFI_ACPI_5_1_ERST_LOAD_VAR1 0x05
-#define EFI_ACPI_5_1_ERST_LOAD_VAR2 0x06
-#define EFI_ACPI_5_1_ERST_STORE_VAR1 0x07
-#define EFI_ACPI_5_1_ERST_ADD 0x08
-#define EFI_ACPI_5_1_ERST_SUBTRACT 0x09
-#define EFI_ACPI_5_1_ERST_ADD_VALUE 0x0A
-#define EFI_ACPI_5_1_ERST_SUBTRACT_VALUE 0x0B
-#define EFI_ACPI_5_1_ERST_STALL 0x0C
-#define EFI_ACPI_5_1_ERST_STALL_WHILE_TRUE 0x0D
-#define EFI_ACPI_5_1_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
-#define EFI_ACPI_5_1_ERST_GOTO 0x0F
-#define EFI_ACPI_5_1_ERST_SET_SRC_ADDRESS_BASE 0x10
-#define EFI_ACPI_5_1_ERST_SET_DST_ADDRESS_BASE 0x11
-#define EFI_ACPI_5_1_ERST_MOVE_DATA 0x12
+#define EFI_ACPI_5_1_ERST_READ_REGISTER 0x00
+#define EFI_ACPI_5_1_ERST_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_5_1_ERST_WRITE_REGISTER 0x02
+#define EFI_ACPI_5_1_ERST_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_5_1_ERST_NOOP 0x04
+#define EFI_ACPI_5_1_ERST_LOAD_VAR1 0x05
+#define EFI_ACPI_5_1_ERST_LOAD_VAR2 0x06
+#define EFI_ACPI_5_1_ERST_STORE_VAR1 0x07
+#define EFI_ACPI_5_1_ERST_ADD 0x08
+#define EFI_ACPI_5_1_ERST_SUBTRACT 0x09
+#define EFI_ACPI_5_1_ERST_ADD_VALUE 0x0A
+#define EFI_ACPI_5_1_ERST_SUBTRACT_VALUE 0x0B
+#define EFI_ACPI_5_1_ERST_STALL 0x0C
+#define EFI_ACPI_5_1_ERST_STALL_WHILE_TRUE 0x0D
+#define EFI_ACPI_5_1_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
+#define EFI_ACPI_5_1_ERST_GOTO 0x0F
+#define EFI_ACPI_5_1_ERST_SET_SRC_ADDRESS_BASE 0x10
+#define EFI_ACPI_5_1_ERST_SET_DST_ADDRESS_BASE 0x11
+#define EFI_ACPI_5_1_ERST_MOVE_DATA 0x12
///
/// ERST Instruction Flags
///
-#define EFI_ACPI_5_1_ERST_PRESERVE_REGISTER 0x01
+#define EFI_ACPI_5_1_ERST_PRESERVE_REGISTER 0x01
///
/// ERST Serialization Instruction Entry
///
typedef struct {
- UINT8 SerializationAction;
- UINT8 Instruction;
- UINT8 Flags;
- UINT8 Reserved0;
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
- UINT64 Value;
- UINT64 Mask;
+ UINT8 SerializationAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
} EFI_ACPI_5_1_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
///
/// EINJ - Error Injection Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 InjectionHeaderSize;
- UINT8 InjectionFlags;
- UINT8 Reserved0[3];
- UINT32 InjectionEntryCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 InjectionHeaderSize;
+ UINT8 InjectionFlags;
+ UINT8 Reserved0[3];
+ UINT32 InjectionEntryCount;
} EFI_ACPI_5_1_ERROR_INJECTION_TABLE_HEADER;
///
/// EINJ Version (as defined in ACPI 5.1 spec.)
///
-#define EFI_ACPI_5_1_ERROR_INJECTION_TABLE_REVISION 0x01
+#define EFI_ACPI_5_1_ERROR_INJECTION_TABLE_REVISION 0x01
///
/// EINJ Error Injection Actions
///
-#define EFI_ACPI_5_1_EINJ_BEGIN_INJECTION_OPERATION 0x00
-#define EFI_ACPI_5_1_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
-#define EFI_ACPI_5_1_EINJ_SET_ERROR_TYPE 0x02
-#define EFI_ACPI_5_1_EINJ_GET_ERROR_TYPE 0x03
-#define EFI_ACPI_5_1_EINJ_END_OPERATION 0x04
-#define EFI_ACPI_5_1_EINJ_EXECUTE_OPERATION 0x05
-#define EFI_ACPI_5_1_EINJ_CHECK_BUSY_STATUS 0x06
-#define EFI_ACPI_5_1_EINJ_GET_COMMAND_STATUS 0x07
-#define EFI_ACPI_5_1_EINJ_TRIGGER_ERROR 0xFF
+#define EFI_ACPI_5_1_EINJ_BEGIN_INJECTION_OPERATION 0x00
+#define EFI_ACPI_5_1_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
+#define EFI_ACPI_5_1_EINJ_SET_ERROR_TYPE 0x02
+#define EFI_ACPI_5_1_EINJ_GET_ERROR_TYPE 0x03
+#define EFI_ACPI_5_1_EINJ_END_OPERATION 0x04
+#define EFI_ACPI_5_1_EINJ_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_5_1_EINJ_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_5_1_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_5_1_EINJ_TRIGGER_ERROR 0xFF
///
/// EINJ Action Command Status
///
-#define EFI_ACPI_5_1_EINJ_STATUS_SUCCESS 0x00
-#define EFI_ACPI_5_1_EINJ_STATUS_UNKNOWN_FAILURE 0x01
-#define EFI_ACPI_5_1_EINJ_STATUS_INVALID_ACCESS 0x02
+#define EFI_ACPI_5_1_EINJ_STATUS_SUCCESS 0x00
+#define EFI_ACPI_5_1_EINJ_STATUS_UNKNOWN_FAILURE 0x01
+#define EFI_ACPI_5_1_EINJ_STATUS_INVALID_ACCESS 0x02
///
/// EINJ Error Type Definition
///
-#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
-#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
-#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
-#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
-#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
-#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
-#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
-#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
-#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
-#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
-#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
-#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
+#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
+#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
+#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
+#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
+#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
+#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
+#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
+#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
+#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
+#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
+#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
+#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
///
/// EINJ Injection Instructions
///
-#define EFI_ACPI_5_1_EINJ_READ_REGISTER 0x00
-#define EFI_ACPI_5_1_EINJ_READ_REGISTER_VALUE 0x01
-#define EFI_ACPI_5_1_EINJ_WRITE_REGISTER 0x02
-#define EFI_ACPI_5_1_EINJ_WRITE_REGISTER_VALUE 0x03
-#define EFI_ACPI_5_1_EINJ_NOOP 0x04
+#define EFI_ACPI_5_1_EINJ_READ_REGISTER 0x00
+#define EFI_ACPI_5_1_EINJ_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_5_1_EINJ_WRITE_REGISTER 0x02
+#define EFI_ACPI_5_1_EINJ_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_5_1_EINJ_NOOP 0x04
///
/// EINJ Instruction Flags
///
-#define EFI_ACPI_5_1_EINJ_PRESERVE_REGISTER 0x01
+#define EFI_ACPI_5_1_EINJ_PRESERVE_REGISTER 0x01
///
/// EINJ Injection Instruction Entry
///
typedef struct {
- UINT8 InjectionAction;
- UINT8 Instruction;
- UINT8 Flags;
- UINT8 Reserved0;
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
- UINT64 Value;
- UINT64 Mask;
+ UINT8 InjectionAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
} EFI_ACPI_5_1_EINJ_INJECTION_INSTRUCTION_ENTRY;
///
/// EINJ Trigger Action Table
///
typedef struct {
- UINT32 HeaderSize;
- UINT32 Revision;
- UINT32 TableSize;
- UINT32 EntryCount;
+ UINT32 HeaderSize;
+ UINT32 Revision;
+ UINT32 TableSize;
+ UINT32 EntryCount;
} EFI_ACPI_5_1_EINJ_TRIGGER_ACTION_TABLE;
///
/// Platform Communications Channel Table (PCCT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Flags;
- UINT64 Reserved;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Flags;
+ UINT64 Reserved;
} EFI_ACPI_5_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
///
/// PCCT Version (as defined in ACPI 5.1 spec.)
///
-#define EFI_ACPI_5_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01
+#define EFI_ACPI_5_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01
///
/// PCCT Global Flags
///
-#define EFI_ACPI_5_1_PCCT_FLAGS_SCI_DOORBELL BIT0
+#define EFI_ACPI_5_1_PCCT_FLAGS_SCI_DOORBELL BIT0
//
// PCCT Subspace type
@@ -1834,25 +1840,25 @@ typedef struct {
/// PCC Subspace Structure Header
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
+ UINT8 Type;
+ UINT8 Length;
} EFI_ACPI_5_1_PCCT_SUBSPACE_HEADER;
///
/// Generic Communications Subspace Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[6];
- UINT64 BaseAddress;
- UINT64 AddressLength;
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
- UINT64 DoorbellPreserve;
- UINT64 DoorbellWrite;
- UINT32 NominalLatency;
- UINT32 MaximumPeriodicAccessRate;
- UINT16 MinimumRequestTurnaroundTime;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[6];
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
} EFI_ACPI_5_1_PCCT_SUBSPACE_GENERIC;
///
@@ -1860,18 +1866,18 @@ typedef struct {
///
typedef struct {
- UINT8 Command;
- UINT8 Reserved:7;
- UINT8 GenerateSci:1;
+ UINT8 Command;
+ UINT8 Reserved : 7;
+ UINT8 GenerateSci : 1;
} EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
typedef struct {
- UINT8 CommandComplete:1;
- UINT8 SciDoorbell:1;
- UINT8 Error:1;
- UINT8 PlatformNotification:1;
- UINT8 Reserved:4;
- UINT8 Reserved1;
+ UINT8 CommandComplete : 1;
+ UINT8 SciDoorbell : 1;
+ UINT8 Error : 1;
+ UINT8 PlatformNotification : 1;
+ UINT8 Reserved : 4;
+ UINT8 Reserved1;
} EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
typedef struct {
diff --git a/MdePkg/Include/IndustryStandard/Acpi60.h b/MdePkg/Include/IndustryStandard/Acpi60.h
index 3b05df22..c3a5a222 100644
--- a/MdePkg/Include/IndustryStandard/Acpi60.h
+++ b/MdePkg/Include/IndustryStandard/Acpi60.h
@@ -1,7 +1,7 @@
/** @file
ACPI 6.0 definitions from the ACPI Specification Revision 6.0 Errata A January, 2016.
- Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
(C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP
Copyright (c) 2020, ARM Ltd. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -21,21 +21,21 @@
/// ACPI 6.0 Generic Address Space definition
///
typedef struct {
- UINT8 AddressSpaceId;
- UINT8 RegisterBitWidth;
- UINT8 RegisterBitOffset;
- UINT8 AccessSize;
- UINT64 Address;
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
} EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE;
//
// Generic Address Space Address IDs
//
-#define EFI_ACPI_6_0_SYSTEM_MEMORY 0
-#define EFI_ACPI_6_0_SYSTEM_IO 1
-#define EFI_ACPI_6_0_PCI_CONFIGURATION_SPACE 2
-#define EFI_ACPI_6_0_EMBEDDED_CONTROLLER 3
-#define EFI_ACPI_6_0_SMBUS 4
+#define EFI_ACPI_6_0_SYSTEM_MEMORY 0
+#define EFI_ACPI_6_0_SYSTEM_IO 1
+#define EFI_ACPI_6_0_PCI_CONFIGURATION_SPACE 2
+#define EFI_ACPI_6_0_EMBEDDED_CONTROLLER 3
+#define EFI_ACPI_6_0_SMBUS 4
#define EFI_ACPI_6_0_PLATFORM_COMMUNICATION_CHANNEL 0x0A
#define EFI_ACPI_6_0_FUNCTIONAL_FIXED_HARDWARE 0x7F
@@ -56,29 +56,29 @@ typedef struct {
/// Root System Description Pointer Structure
///
typedef struct {
- UINT64 Signature;
- UINT8 Checksum;
- UINT8 OemId[6];
- UINT8 Revision;
- UINT32 RsdtAddress;
- UINT32 Length;
- UINT64 XsdtAddress;
- UINT8 ExtendedChecksum;
- UINT8 Reserved[3];
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
} EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
///
/// RSD_PTR Revision (as defined in ACPI 6.0 spec.)
///
-#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.0) says current value is 2
+#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.0) says current value is 2
///
/// Common table header, this prefaces all ACPI tables, including FACS, but
/// excluding the RSD PTR structure
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
+ UINT32 Signature;
+ UINT32 Length;
} EFI_ACPI_6_0_COMMON_HEADER;
//
@@ -90,7 +90,7 @@ typedef struct {
///
/// RSDT Revision (as defined in ACPI 6.0 spec.)
///
-#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
//
// Extended System Description Table
@@ -101,74 +101,74 @@ typedef struct {
///
/// XSDT Revision (as defined in ACPI 6.0 spec.)
///
-#define EFI_ACPI_6_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
///
/// Fixed ACPI Description Table Structure (FADT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 FirmwareCtrl;
- UINT32 Dsdt;
- UINT8 Reserved0;
- UINT8 PreferredPmProfile;
- UINT16 SciInt;
- UINT32 SmiCmd;
- UINT8 AcpiEnable;
- UINT8 AcpiDisable;
- UINT8 S4BiosReq;
- UINT8 PstateCnt;
- UINT32 Pm1aEvtBlk;
- UINT32 Pm1bEvtBlk;
- UINT32 Pm1aCntBlk;
- UINT32 Pm1bCntBlk;
- UINT32 Pm2CntBlk;
- UINT32 PmTmrBlk;
- UINT32 Gpe0Blk;
- UINT32 Gpe1Blk;
- UINT8 Pm1EvtLen;
- UINT8 Pm1CntLen;
- UINT8 Pm2CntLen;
- UINT8 PmTmrLen;
- UINT8 Gpe0BlkLen;
- UINT8 Gpe1BlkLen;
- UINT8 Gpe1Base;
- UINT8 CstCnt;
- UINT16 PLvl2Lat;
- UINT16 PLvl3Lat;
- UINT16 FlushSize;
- UINT16 FlushStride;
- UINT8 DutyOffset;
- UINT8 DutyWidth;
- UINT8 DayAlrm;
- UINT8 MonAlrm;
- UINT8 Century;
- UINT16 IaPcBootArch;
- UINT8 Reserved1;
- UINT32 Flags;
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
- UINT8 ResetValue;
- UINT16 ArmBootArch;
- UINT8 MinorVersion;
- UINT64 XFirmwareCtrl;
- UINT64 XDsdt;
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
- UINT64 HypervisorVendorIdentity;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT16 ArmBootArch;
+ UINT8 MinorVersion;
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
+ UINT64 HypervisorVendorIdentity;
} EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE;
///
/// FADT Version (as defined in ACPI 6.0 spec.)
///
-#define EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06
+#define EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06
#define EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x00
//
@@ -188,62 +188,62 @@ typedef struct {
// Fixed ACPI Description Table Boot Architecture Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_6_0_LEGACY_DEVICES BIT0
-#define EFI_ACPI_6_0_8042 BIT1
-#define EFI_ACPI_6_0_VGA_NOT_PRESENT BIT2
-#define EFI_ACPI_6_0_MSI_NOT_SUPPORTED BIT3
-#define EFI_ACPI_6_0_PCIE_ASPM_CONTROLS BIT4
-#define EFI_ACPI_6_0_CMOS_RTC_NOT_PRESENT BIT5
+#define EFI_ACPI_6_0_LEGACY_DEVICES BIT0
+#define EFI_ACPI_6_0_8042 BIT1
+#define EFI_ACPI_6_0_VGA_NOT_PRESENT BIT2
+#define EFI_ACPI_6_0_MSI_NOT_SUPPORTED BIT3
+#define EFI_ACPI_6_0_PCIE_ASPM_CONTROLS BIT4
+#define EFI_ACPI_6_0_CMOS_RTC_NOT_PRESENT BIT5
//
// Fixed ACPI Description Table Arm Boot Architecture Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_6_0_ARM_PSCI_COMPLIANT BIT0
-#define EFI_ACPI_6_0_ARM_PSCI_USE_HVC BIT1
+#define EFI_ACPI_6_0_ARM_PSCI_COMPLIANT BIT0
+#define EFI_ACPI_6_0_ARM_PSCI_USE_HVC BIT1
//
// Fixed ACPI Description Table Fixed Feature Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_6_0_WBINVD BIT0
-#define EFI_ACPI_6_0_WBINVD_FLUSH BIT1
-#define EFI_ACPI_6_0_PROC_C1 BIT2
-#define EFI_ACPI_6_0_P_LVL2_UP BIT3
-#define EFI_ACPI_6_0_PWR_BUTTON BIT4
-#define EFI_ACPI_6_0_SLP_BUTTON BIT5
-#define EFI_ACPI_6_0_FIX_RTC BIT6
-#define EFI_ACPI_6_0_RTC_S4 BIT7
-#define EFI_ACPI_6_0_TMR_VAL_EXT BIT8
-#define EFI_ACPI_6_0_DCK_CAP BIT9
-#define EFI_ACPI_6_0_RESET_REG_SUP BIT10
-#define EFI_ACPI_6_0_SEALED_CASE BIT11
-#define EFI_ACPI_6_0_HEADLESS BIT12
-#define EFI_ACPI_6_0_CPU_SW_SLP BIT13
-#define EFI_ACPI_6_0_PCI_EXP_WAK BIT14
-#define EFI_ACPI_6_0_USE_PLATFORM_CLOCK BIT15
-#define EFI_ACPI_6_0_S4_RTC_STS_VALID BIT16
-#define EFI_ACPI_6_0_REMOTE_POWER_ON_CAPABLE BIT17
-#define EFI_ACPI_6_0_FORCE_APIC_CLUSTER_MODEL BIT18
-#define EFI_ACPI_6_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
-#define EFI_ACPI_6_0_HW_REDUCED_ACPI BIT20
-#define EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE BIT21
+#define EFI_ACPI_6_0_WBINVD BIT0
+#define EFI_ACPI_6_0_WBINVD_FLUSH BIT1
+#define EFI_ACPI_6_0_PROC_C1 BIT2
+#define EFI_ACPI_6_0_P_LVL2_UP BIT3
+#define EFI_ACPI_6_0_PWR_BUTTON BIT4
+#define EFI_ACPI_6_0_SLP_BUTTON BIT5
+#define EFI_ACPI_6_0_FIX_RTC BIT6
+#define EFI_ACPI_6_0_RTC_S4 BIT7
+#define EFI_ACPI_6_0_TMR_VAL_EXT BIT8
+#define EFI_ACPI_6_0_DCK_CAP BIT9
+#define EFI_ACPI_6_0_RESET_REG_SUP BIT10
+#define EFI_ACPI_6_0_SEALED_CASE BIT11
+#define EFI_ACPI_6_0_HEADLESS BIT12
+#define EFI_ACPI_6_0_CPU_SW_SLP BIT13
+#define EFI_ACPI_6_0_PCI_EXP_WAK BIT14
+#define EFI_ACPI_6_0_USE_PLATFORM_CLOCK BIT15
+#define EFI_ACPI_6_0_S4_RTC_STS_VALID BIT16
+#define EFI_ACPI_6_0_REMOTE_POWER_ON_CAPABLE BIT17
+#define EFI_ACPI_6_0_FORCE_APIC_CLUSTER_MODEL BIT18
+#define EFI_ACPI_6_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+#define EFI_ACPI_6_0_HW_REDUCED_ACPI BIT20
+#define EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE BIT21
///
/// Firmware ACPI Control Structure
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
- UINT32 HardwareSignature;
- UINT32 FirmwareWakingVector;
- UINT32 GlobalLock;
- UINT32 Flags;
- UINT64 XFirmwareWakingVector;
- UINT8 Version;
- UINT8 Reserved0[3];
- UINT32 OspmFlags;
- UINT8 Reserved1[24];
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved0[3];
+ UINT32 OspmFlags;
+ UINT8 Reserved1[24];
} EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
///
@@ -255,14 +255,14 @@ typedef struct {
/// Firmware Control Structure Feature Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_6_0_S4BIOS_F BIT0
-#define EFI_ACPI_6_0_64BIT_WAKE_SUPPORTED_F BIT1
+#define EFI_ACPI_6_0_S4BIOS_F BIT0
+#define EFI_ACPI_6_0_64BIT_WAKE_SUPPORTED_F BIT1
///
/// OSPM Enabled Firmware Control Structure Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_6_0_OSPM_64BIT_WAKE_F BIT0
+#define EFI_ACPI_6_0_OSPM_64BIT_WAKE_F BIT0
//
// Differentiated System Description Table,
@@ -271,29 +271,29 @@ typedef struct {
// no definition needed as they are common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
//
-#define EFI_ACPI_6_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
-#define EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_6_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
///
/// Multiple APIC Description Table header definition. The rest of the table
/// must be defined in a platform specific manner.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 LocalApicAddress;
- UINT32 Flags;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
} EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
///
/// MADT Revision (as defined in ACPI 6.0 Errata A spec.)
///
-#define EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04
+#define EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04
///
/// Multiple APIC Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_6_0_PCAT_COMPAT BIT0
+#define EFI_ACPI_6_0_PCAT_COMPAT BIT0
//
// Multiple APIC Description Table APIC structure types
@@ -325,57 +325,57 @@ typedef struct {
/// Processor Local APIC Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorUid;
- UINT8 ApicId;
- UINT32 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT8 ApicId;
+ UINT32 Flags;
} EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
///
/// Local APIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_0_LOCAL_APIC_ENABLED BIT0
+#define EFI_ACPI_6_0_LOCAL_APIC_ENABLED BIT0
///
/// IO APIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 IoApicAddress;
- UINT32 GlobalSystemInterruptBase;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
} EFI_ACPI_6_0_IO_APIC_STRUCTURE;
///
/// Interrupt Source Override Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Bus;
- UINT8 Source;
- UINT32 GlobalSystemInterrupt;
- UINT16 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
} EFI_ACPI_6_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
///
/// Platform Interrupt Sources Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT8 InterruptType;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT8 IoSapicVector;
- UINT32 GlobalSystemInterrupt;
- UINT32 PlatformInterruptSourceFlags;
- UINT8 CpeiProcessorOverride;
- UINT8 Reserved[31];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
} EFI_ACPI_6_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;
//
@@ -389,43 +389,43 @@ typedef struct {
/// Non-Maskable Interrupt Source Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT32 GlobalSystemInterrupt;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
} EFI_ACPI_6_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
///
/// Local APIC NMI Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorUid;
- UINT16 Flags;
- UINT8 LocalApicLint;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
} EFI_ACPI_6_0_LOCAL_APIC_NMI_STRUCTURE;
///
/// Local APIC Address Override Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT64 LocalApicAddress;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
} EFI_ACPI_6_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
///
/// IO SAPIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 GlobalSystemInterruptBase;
- UINT64 IoSapicAddress;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
} EFI_ACPI_6_0_IO_SAPIC_STRUCTURE;
///
@@ -433,169 +433,169 @@ typedef struct {
/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT8 LocalSapicId;
- UINT8 LocalSapicEid;
- UINT8 Reserved[3];
- UINT32 Flags;
- UINT32 ACPIProcessorUIDValue;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
} EFI_ACPI_6_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
///
/// Platform Interrupt Sources Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT8 InterruptType;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT8 IoSapicVector;
- UINT32 GlobalSystemInterrupt;
- UINT32 PlatformInterruptSourceFlags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
} EFI_ACPI_6_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
///
/// Platform Interrupt Source Flags.
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_6_0_CPEI_PROCESSOR_OVERRIDE BIT0
+#define EFI_ACPI_6_0_CPEI_PROCESSOR_OVERRIDE BIT0
///
/// Processor Local x2APIC Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[2];
- UINT32 X2ApicId;
- UINT32 Flags;
- UINT32 AcpiProcessorUid;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 AcpiProcessorUid;
} EFI_ACPI_6_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
///
/// Local x2APIC NMI Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT32 AcpiProcessorUid;
- UINT8 LocalX2ApicLint;
- UINT8 Reserved[3];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 AcpiProcessorUid;
+ UINT8 LocalX2ApicLint;
+ UINT8 Reserved[3];
} EFI_ACPI_6_0_LOCAL_X2APIC_NMI_STRUCTURE;
///
/// GIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT32 CPUInterfaceNumber;
- UINT32 AcpiProcessorUid;
- UINT32 Flags;
- UINT32 ParkingProtocolVersion;
- UINT32 PerformanceInterruptGsiv;
- UINT64 ParkedAddress;
- UINT64 PhysicalBaseAddress;
- UINT64 GICV;
- UINT64 GICH;
- UINT32 VGICMaintenanceInterrupt;
- UINT64 GICRBaseAddress;
- UINT64 MPIDR;
- UINT8 ProcessorPowerEfficiencyClass;
- UINT8 Reserved2[3];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 CPUInterfaceNumber;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ParkingProtocolVersion;
+ UINT32 PerformanceInterruptGsiv;
+ UINT64 ParkedAddress;
+ UINT64 PhysicalBaseAddress;
+ UINT64 GICV;
+ UINT64 GICH;
+ UINT32 VGICMaintenanceInterrupt;
+ UINT64 GICRBaseAddress;
+ UINT64 MPIDR;
+ UINT8 ProcessorPowerEfficiencyClass;
+ UINT8 Reserved2[3];
} EFI_ACPI_6_0_GIC_STRUCTURE;
///
/// GIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_0_GIC_ENABLED BIT0
-#define EFI_ACPI_6_0_PERFORMANCE_INTERRUPT_MODEL BIT1
-#define EFI_ACPI_6_0_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2
+#define EFI_ACPI_6_0_GIC_ENABLED BIT0
+#define EFI_ACPI_6_0_PERFORMANCE_INTERRUPT_MODEL BIT1
+#define EFI_ACPI_6_0_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2
///
/// GIC Distributor Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved1;
- UINT32 GicId;
- UINT64 PhysicalBaseAddress;
- UINT32 SystemVectorBase;
- UINT8 GicVersion;
- UINT8 Reserved2[3];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 SystemVectorBase;
+ UINT8 GicVersion;
+ UINT8 Reserved2[3];
} EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE;
///
/// GIC Version
///
-#define EFI_ACPI_6_0_GIC_V1 0x01
-#define EFI_ACPI_6_0_GIC_V2 0x02
-#define EFI_ACPI_6_0_GIC_V3 0x03
-#define EFI_ACPI_6_0_GIC_V4 0x04
+#define EFI_ACPI_6_0_GIC_V1 0x01
+#define EFI_ACPI_6_0_GIC_V2 0x02
+#define EFI_ACPI_6_0_GIC_V3 0x03
+#define EFI_ACPI_6_0_GIC_V4 0x04
///
/// GIC MSI Frame Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved1;
- UINT32 GicMsiFrameId;
- UINT64 PhysicalBaseAddress;
- UINT32 Flags;
- UINT16 SPICount;
- UINT16 SPIBase;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicMsiFrameId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Flags;
+ UINT16 SPICount;
+ UINT16 SPIBase;
} EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE;
///
/// GIC MSI Frame Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_0_SPI_COUNT_BASE_SELECT BIT0
+#define EFI_ACPI_6_0_SPI_COUNT_BASE_SELECT BIT0
///
/// GICR Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT64 DiscoveryRangeBaseAddress;
- UINT32 DiscoveryRangeLength;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 DiscoveryRangeBaseAddress;
+ UINT32 DiscoveryRangeLength;
} EFI_ACPI_6_0_GICR_STRUCTURE;
///
/// GIC Interrupt Translation Service Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT32 GicItsId;
- UINT64 PhysicalBaseAddress;
- UINT32 Reserved2;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 GicItsId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Reserved2;
} EFI_ACPI_6_0_GIC_ITS_STRUCTURE;
///
/// Smart Battery Description Table (SBST)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 WarningEnergyLevel;
- UINT32 LowEnergyLevel;
- UINT32 CriticalEnergyLevel;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
} EFI_ACPI_6_0_SMART_BATTERY_DESCRIPTION_TABLE;
///
/// SBST Version (as defined in ACPI 6.0 spec.)
///
-#define EFI_ACPI_6_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
///
/// Embedded Controller Boot Resources Table (ECDT)
@@ -603,11 +603,11 @@ typedef struct {
/// a fully qualified reference to the name space object.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE EcControl;
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE EcData;
- UINT32 Uid;
- UINT8 GpeBit;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
} EFI_ACPI_6_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
///
@@ -620,9 +620,9 @@ typedef struct {
/// must be defined in a platform specific manner.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Reserved1; ///< Must be set to 1
- UINT64 Reserved2;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; ///< Must be set to 1
+ UINT64 Reserved2;
} EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
///
@@ -644,83 +644,83 @@ typedef struct {
/// Processor Local APIC/SAPIC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 ProximityDomain7To0;
- UINT8 ApicId;
- UINT32 Flags;
- UINT8 LocalSapicEid;
- UINT8 ProximityDomain31To8[3];
- UINT32 ClockDomain;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT32 ClockDomain;
} EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
///
/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+#define EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
///
/// Memory Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 ProximityDomain;
- UINT16 Reserved1;
- UINT32 AddressBaseLow;
- UINT32 AddressBaseHigh;
- UINT32 LengthLow;
- UINT32 LengthHigh;
- UINT32 Reserved2;
- UINT32 Flags;
- UINT64 Reserved3;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
} EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE;
//
// Memory Flags. All other bits are reserved and must be 0.
//
-#define EFI_ACPI_6_0_MEMORY_ENABLED (1 << 0)
-#define EFI_ACPI_6_0_MEMORY_HOT_PLUGGABLE (1 << 1)
-#define EFI_ACPI_6_0_MEMORY_NONVOLATILE (1 << 2)
+#define EFI_ACPI_6_0_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_6_0_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_6_0_MEMORY_NONVOLATILE (1 << 2)
///
/// Processor Local x2APIC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved1[2];
- UINT32 ProximityDomain;
- UINT32 X2ApicId;
- UINT32 Flags;
- UINT32 ClockDomain;
- UINT8 Reserved2[4];
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1[2];
+ UINT32 ProximityDomain;
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+ UINT8 Reserved2[4];
} EFI_ACPI_6_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
///
/// GICC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 ProximityDomain;
- UINT32 AcpiProcessorUid;
- UINT32 Flags;
- UINT32 ClockDomain;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ClockDomain;
} EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE;
///
/// GICC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_0_GICC_ENABLED (1 << 0)
+#define EFI_ACPI_6_0_GICC_ENABLED (1 << 0)
///
/// System Locality Distance Information Table (SLIT).
/// The rest of the table is a matrix.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 NumberOfSystemLocalities;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
} EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
///
@@ -732,14 +732,14 @@ typedef struct {
/// Corrected Platform Error Polling Table (CPEP)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 Reserved[8];
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[8];
} EFI_ACPI_6_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
///
/// CPEP Version (as defined in ACPI 6.0 spec.)
///
-#define EFI_ACPI_6_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+#define EFI_ACPI_6_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
//
// CPEP processor structure types.
@@ -750,66 +750,66 @@ typedef struct {
/// Corrected Platform Error Polling Processor Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT32 PollingInterval;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT32 PollingInterval;
} EFI_ACPI_6_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
///
/// Maximum System Characteristics Table (MSCT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 OffsetProxDomInfo;
- UINT32 MaximumNumberOfProximityDomains;
- UINT32 MaximumNumberOfClockDomains;
- UINT64 MaximumPhysicalAddress;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 OffsetProxDomInfo;
+ UINT32 MaximumNumberOfProximityDomains;
+ UINT32 MaximumNumberOfClockDomains;
+ UINT64 MaximumPhysicalAddress;
} EFI_ACPI_6_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
///
/// MSCT Version (as defined in ACPI 6.0 spec.)
///
-#define EFI_ACPI_6_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+#define EFI_ACPI_6_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
///
/// Maximum Proximity Domain Information Structure Definition
///
typedef struct {
- UINT8 Revision;
- UINT8 Length;
- UINT32 ProximityDomainRangeLow;
- UINT32 ProximityDomainRangeHigh;
- UINT32 MaximumProcessorCapacity;
- UINT64 MaximumMemoryCapacity;
+ UINT8 Revision;
+ UINT8 Length;
+ UINT32 ProximityDomainRangeLow;
+ UINT32 ProximityDomainRangeHigh;
+ UINT32 MaximumProcessorCapacity;
+ UINT64 MaximumMemoryCapacity;
} EFI_ACPI_6_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
///
/// ACPI RAS Feature Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 PlatformCommunicationChannelIdentifier[12];
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier[12];
} EFI_ACPI_6_0_RAS_FEATURE_TABLE;
///
/// RASF Version (as defined in ACPI 6.0 spec.)
///
-#define EFI_ACPI_6_0_RAS_FEATURE_TABLE_REVISION 0x01
+#define EFI_ACPI_6_0_RAS_FEATURE_TABLE_REVISION 0x01
///
/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
///
typedef struct {
- UINT32 Signature;
- UINT16 Command;
- UINT16 Status;
- UINT16 Version;
- UINT8 RASCapabilities[16];
- UINT8 SetRASCapabilities[16];
- UINT16 NumberOfRASFParameterBlocks;
- UINT32 SetRASCapabilitiesStatus;
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT16 Version;
+ UINT8 RASCapabilities[16];
+ UINT8 SetRASCapabilities[16];
+ UINT16 NumberOfRASFParameterBlocks;
+ UINT32 SetRASCapabilitiesStatus;
} EFI_ACPI_6_0_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
///
@@ -827,52 +827,52 @@ typedef struct {
/// ACPI RASF Parameter Block structure for PATROL_SCRUB
///
typedef struct {
- UINT16 Type;
- UINT16 Version;
- UINT16 Length;
- UINT16 PatrolScrubCommand;
- UINT64 RequestedAddressRange[2];
- UINT64 ActualAddressRange[2];
- UINT16 Flags;
- UINT8 RequestedSpeed;
+ UINT16 Type;
+ UINT16 Version;
+ UINT16 Length;
+ UINT16 PatrolScrubCommand;
+ UINT64 RequestedAddressRange[2];
+ UINT64 ActualAddressRange[2];
+ UINT16 Flags;
+ UINT8 RequestedSpeed;
} EFI_ACPI_6_0_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
///
/// ACPI RASF Patrol Scrub command
///
-#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
-#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
-#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
+#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
+#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
+#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
///
/// Memory Power State Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 PlatformCommunicationChannelIdentifier;
- UINT8 Reserved[3];
-// Memory Power Node Structure
-// Memory Power State Characteristics
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier;
+ UINT8 Reserved[3];
+ // Memory Power Node Structure
+ // Memory Power State Characteristics
} EFI_ACPI_6_0_MEMORY_POWER_STATUS_TABLE;
///
/// MPST Version (as defined in ACPI 6.0 spec.)
///
-#define EFI_ACPI_6_0_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+#define EFI_ACPI_6_0_MEMORY_POWER_STATE_TABLE_REVISION 0x01
///
/// MPST Platform Communication Channel Shared Memory Region definition.
///
typedef struct {
- UINT32 Signature;
- UINT16 Command;
- UINT16 Status;
- UINT32 MemoryPowerCommandRegister;
- UINT32 MemoryPowerStatusRegister;
- UINT32 PowerStateId;
- UINT32 MemoryPowerNodeId;
- UINT64 MemoryEnergyConsumed;
- UINT64 ExpectedAveragePowerComsuned;
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT32 MemoryPowerCommandRegister;
+ UINT32 MemoryPowerStatusRegister;
+ UINT32 PowerStateId;
+ UINT32 MemoryPowerNodeId;
+ UINT64 MemoryEnergyConsumed;
+ UINT64 ExpectedAveragePowerComsuned;
} EFI_ACPI_6_0_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
///
@@ -883,186 +883,186 @@ typedef struct {
///
/// ACPI MPST Memory Power command
///
-#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
-#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
-#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
-#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
///
/// MPST Memory Power Node Table
///
typedef struct {
- UINT8 PowerStateValue;
- UINT8 PowerStateInformationIndex;
+ UINT8 PowerStateValue;
+ UINT8 PowerStateInformationIndex;
} EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE;
typedef struct {
- UINT8 Flag;
- UINT8 Reserved;
- UINT16 MemoryPowerNodeId;
- UINT32 Length;
- UINT64 AddressBase;
- UINT64 AddressLength;
- UINT32 NumberOfPowerStates;
- UINT32 NumberOfPhysicalComponents;
-//EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
-//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+ UINT8 Flag;
+ UINT8 Reserved;
+ UINT16 MemoryPowerNodeId;
+ UINT32 Length;
+ UINT64 AddressBase;
+ UINT64 AddressLength;
+ UINT32 NumberOfPowerStates;
+ UINT32 NumberOfPhysicalComponents;
+ // EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
} EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE;
-#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
-#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
-#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
typedef struct {
- UINT16 MemoryPowerNodeCount;
- UINT8 Reserved[2];
+ UINT16 MemoryPowerNodeCount;
+ UINT8 Reserved[2];
} EFI_ACPI_6_0_MPST_MEMORY_POWER_NODE_TABLE;
///
/// MPST Memory Power State Characteristics Table
///
typedef struct {
- UINT8 PowerStateStructureID;
- UINT8 Flag;
- UINT16 Reserved;
- UINT32 AveragePowerConsumedInMPS0;
- UINT32 RelativePowerSavingToMPS0;
- UINT64 ExitLatencyToMPS0;
+ UINT8 PowerStateStructureID;
+ UINT8 Flag;
+ UINT16 Reserved;
+ UINT32 AveragePowerConsumedInMPS0;
+ UINT32 RelativePowerSavingToMPS0;
+ UINT64 ExitLatencyToMPS0;
} EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
-#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
-#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
-#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
typedef struct {
- UINT16 MemoryPowerStateCharacteristicsCount;
- UINT8 Reserved[2];
+ UINT16 MemoryPowerStateCharacteristicsCount;
+ UINT8 Reserved[2];
} EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
///
/// Memory Topology Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
} EFI_ACPI_6_0_MEMORY_TOPOLOGY_TABLE;
///
/// PMTT Version (as defined in ACPI 6.0 spec.)
///
-#define EFI_ACPI_6_0_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
+#define EFI_ACPI_6_0_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
///
/// Common Memory Aggregator Device Structure.
///
typedef struct {
- UINT8 Type;
- UINT8 Reserved;
- UINT16 Length;
- UINT16 Flags;
- UINT16 Reserved1;
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16 Length;
+ UINT16 Flags;
+ UINT16 Reserved1;
} EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// Memory Aggregator Device Type
///
-#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0
-#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
-#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2
+#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0
+#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
+#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2
///
/// Socket Memory Aggregator Device Structure.
///
typedef struct {
- EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
- UINT16 SocketIdentifier;
- UINT16 Reserved;
-//EFI_ACPI_6_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];
+ EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 SocketIdentifier;
+ UINT16 Reserved;
+ // EFI_ACPI_6_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];
} EFI_ACPI_6_0_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// MemoryController Memory Aggregator Device Structure.
///
typedef struct {
- EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
- UINT32 ReadLatency;
- UINT32 WriteLatency;
- UINT32 ReadBandwidth;
- UINT32 WriteBandwidth;
- UINT16 OptimalAccessUnit;
- UINT16 OptimalAccessAlignment;
- UINT16 Reserved;
- UINT16 NumberOfProximityDomains;
-//UINT32 ProximityDomain[NumberOfProximityDomains];
-//EFI_ACPI_6_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];
+ EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT32 ReadLatency;
+ UINT32 WriteLatency;
+ UINT32 ReadBandwidth;
+ UINT32 WriteBandwidth;
+ UINT16 OptimalAccessUnit;
+ UINT16 OptimalAccessAlignment;
+ UINT16 Reserved;
+ UINT16 NumberOfProximityDomains;
+ // UINT32 ProximityDomain[NumberOfProximityDomains];
+ // EFI_ACPI_6_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];
} EFI_ACPI_6_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// DIMM Memory Aggregator Device Structure.
///
typedef struct {
- EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
- UINT16 PhysicalComponentIdentifier;
- UINT16 Reserved;
- UINT32 SizeOfDimm;
- UINT32 SmbiosHandle;
+ EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 PhysicalComponentIdentifier;
+ UINT16 Reserved;
+ UINT32 SizeOfDimm;
+ UINT32 SmbiosHandle;
} EFI_ACPI_6_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// Boot Graphics Resource Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
///
/// 2-bytes (16 bit) version ID. This value must be 1.
///
- UINT16 Version;
+ UINT16 Version;
///
/// 1-byte status field indicating current status about the table.
/// Bits[7:1] = Reserved (must be zero)
/// Bit [0] = Valid. A one indicates the boot image graphic is valid.
///
- UINT8 Status;
+ UINT8 Status;
///
/// 1-byte enumerated type field indicating format of the image.
/// 0 = Bitmap
/// 1 - 255 Reserved (for future use)
///
- UINT8 ImageType;
+ UINT8 ImageType;
///
/// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
/// of the image bitmap.
///
- UINT64 ImageAddress;
+ UINT64 ImageAddress;
///
/// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
/// (X, Y) display offset of the top left corner of the boot image.
/// The top left corner of the display is at offset (0, 0).
///
- UINT32 ImageOffsetX;
+ UINT32 ImageOffsetX;
///
/// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
/// (X, Y) display offset of the top left corner of the boot image.
/// The top left corner of the display is at offset (0, 0).
///
- UINT32 ImageOffsetY;
+ UINT32 ImageOffsetY;
} EFI_ACPI_6_0_BOOT_GRAPHICS_RESOURCE_TABLE;
///
/// BGRT Revision
///
-#define EFI_ACPI_6_0_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+#define EFI_ACPI_6_0_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
///
/// BGRT Version
///
-#define EFI_ACPI_6_0_BGRT_VERSION 0x01
+#define EFI_ACPI_6_0_BGRT_VERSION 0x01
///
/// BGRT Status
///
-#define EFI_ACPI_6_0_BGRT_STATUS_NOT_DISPLAYED 0x00
-#define EFI_ACPI_6_0_BGRT_STATUS_DISPLAYED 0x01
+#define EFI_ACPI_6_0_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_6_0_BGRT_STATUS_DISPLAYED 0x01
///
/// BGRT Image Type
@@ -1072,26 +1072,26 @@ typedef struct {
///
/// FPDT Version (as defined in ACPI 6.0 spec.)
///
-#define EFI_ACPI_6_0_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+#define EFI_ACPI_6_0_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
///
/// FPDT Performance Record Types
///
-#define EFI_ACPI_6_0_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
-#define EFI_ACPI_6_0_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
+#define EFI_ACPI_6_0_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
+#define EFI_ACPI_6_0_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
///
/// FPDT Performance Record Revision
///
-#define EFI_ACPI_6_0_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
-#define EFI_ACPI_6_0_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+#define EFI_ACPI_6_0_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
+#define EFI_ACPI_6_0_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
///
/// FPDT Runtime Performance Record Types
///
-#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
-#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
-#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
+#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
+#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
+#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
///
/// FPDT Runtime Performance Record Revision
@@ -1104,77 +1104,77 @@ typedef struct {
/// FPDT Performance Record header
///
typedef struct {
- UINT16 Type;
- UINT8 Length;
- UINT8 Revision;
+ UINT16 Type;
+ UINT8 Length;
+ UINT8 Revision;
} EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER;
///
/// FPDT Performance Table header
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
+ UINT32 Signature;
+ UINT32 Length;
} EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER;
///
/// FPDT Firmware Basic Boot Performance Pointer Record Structure
///
typedef struct {
- EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
///
/// 64-bit processor-relative physical address of the Basic Boot Performance Table.
///
- UINT64 BootPerformanceTablePointer;
+ UINT64 BootPerformanceTablePointer;
} EFI_ACPI_6_0_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
///
/// FPDT S3 Performance Table Pointer Record Structure
///
typedef struct {
- EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
///
/// 64-bit processor-relative physical address of the S3 Performance Table.
///
- UINT64 S3PerformanceTablePointer;
+ UINT64 S3PerformanceTablePointer;
} EFI_ACPI_6_0_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
///
/// FPDT Firmware Basic Boot Performance Record Structure
///
typedef struct {
- EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
///
/// Timer value logged at the beginning of firmware image execution.
/// This may not always be zero or near zero.
///
- UINT64 ResetEnd;
+ UINT64 ResetEnd;
///
/// Timer value logged just prior to loading the OS boot loader into memory.
/// For non-UEFI compatible boots, this field must be zero.
///
- UINT64 OsLoaderLoadImageStart;
+ UINT64 OsLoaderLoadImageStart;
///
/// Timer value logged just prior to launching the previously loaded OS boot loader image.
/// For non-UEFI compatible boots, the timer value logged will be just prior
/// to the INT 19h handler invocation.
///
- UINT64 OsLoaderStartImageStart;
+ UINT64 OsLoaderStartImageStart;
///
/// Timer value logged at the point when the OS loader calls the
/// ExitBootServices function for UEFI compatible firmware.
/// For non-UEFI compatible boots, this field must be zero.
///
- UINT64 ExitBootServicesEntry;
+ UINT64 ExitBootServicesEntry;
///
/// Timer value logged at the point just prior to when the OS loader gaining
/// control back from calls the ExitBootServices function for UEFI compatible firmware.
/// For non-UEFI compatible boots, this field must be zero.
///
- UINT64 ExitBootServicesExit;
+ UINT64 ExitBootServicesExit;
} EFI_ACPI_6_0_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
///
@@ -1186,7 +1186,7 @@ typedef struct {
// FPDT Firmware Basic Boot Performance Table
//
typedef struct {
- EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER Header;
//
// one or more Performance Records.
//
@@ -1201,7 +1201,7 @@ typedef struct {
// FPDT Firmware S3 Boot Performance Table
//
typedef struct {
- EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER Header;
//
// one or more Performance Records.
//
@@ -1211,145 +1211,145 @@ typedef struct {
/// FPDT Basic S3 Resume Performance Record
///
typedef struct {
- EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
///
/// A count of the number of S3 resume cycles since the last full boot sequence.
///
- UINT32 ResumeCount;
+ UINT32 ResumeCount;
///
/// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
/// OS waking vector. Only the most recent resume cycle's time is retained.
///
- UINT64 FullResume;
+ UINT64 FullResume;
///
/// Average timer value of all resume cycles logged since the last full boot
/// sequence, including the most recent resume. Note that the entire log of
/// timer values does not need to be retained in order to calculate this average.
///
- UINT64 AverageResume;
+ UINT64 AverageResume;
} EFI_ACPI_6_0_FPDT_S3_RESUME_RECORD;
///
/// FPDT Basic S3 Suspend Performance Record
///
typedef struct {
- EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
///
/// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
/// Only the most recent suspend cycle's timer value is retained.
///
- UINT64 SuspendStart;
+ UINT64 SuspendStart;
///
/// Timer value recorded at the final firmware write to SLP_TYP (or other
/// mechanism) used to trigger hardware entry to S3.
/// Only the most recent suspend cycle's timer value is retained.
///
- UINT64 SuspendEnd;
+ UINT64 SuspendEnd;
} EFI_ACPI_6_0_FPDT_S3_SUSPEND_RECORD;
///
/// Firmware Performance Record Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
} EFI_ACPI_6_0_FIRMWARE_PERFORMANCE_RECORD_TABLE;
///
/// Generic Timer Description Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 CntControlBasePhysicalAddress;
- UINT32 Reserved;
- UINT32 SecurePL1TimerGSIV;
- UINT32 SecurePL1TimerFlags;
- UINT32 NonSecurePL1TimerGSIV;
- UINT32 NonSecurePL1TimerFlags;
- UINT32 VirtualTimerGSIV;
- UINT32 VirtualTimerFlags;
- UINT32 NonSecurePL2TimerGSIV;
- UINT32 NonSecurePL2TimerFlags;
- UINT64 CntReadBasePhysicalAddress;
- UINT32 PlatformTimerCount;
- UINT32 PlatformTimerOffset;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 CntControlBasePhysicalAddress;
+ UINT32 Reserved;
+ UINT32 SecurePL1TimerGSIV;
+ UINT32 SecurePL1TimerFlags;
+ UINT32 NonSecurePL1TimerGSIV;
+ UINT32 NonSecurePL1TimerFlags;
+ UINT32 VirtualTimerGSIV;
+ UINT32 VirtualTimerFlags;
+ UINT32 NonSecurePL2TimerGSIV;
+ UINT32 NonSecurePL2TimerFlags;
+ UINT64 CntReadBasePhysicalAddress;
+ UINT32 PlatformTimerCount;
+ UINT32 PlatformTimerOffset;
} EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE;
///
/// GTDT Version (as defined in ACPI 6.0 spec.)
///
-#define EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02
///
/// Timer Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
-#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
-#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2
+#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2
///
/// Platform Timer Type
///
-#define EFI_ACPI_6_0_GTDT_GT_BLOCK 0
-#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG 1
+#define EFI_ACPI_6_0_GTDT_GT_BLOCK 0
+#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG 1
///
/// GT Block Structure
///
typedef struct {
- UINT8 Type;
- UINT16 Length;
- UINT8 Reserved;
- UINT64 CntCtlBase;
- UINT32 GTBlockTimerCount;
- UINT32 GTBlockTimerOffset;
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 CntCtlBase;
+ UINT32 GTBlockTimerCount;
+ UINT32 GTBlockTimerOffset;
} EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE;
///
/// GT Block Timer Structure
///
typedef struct {
- UINT8 GTFrameNumber;
- UINT8 Reserved[3];
- UINT64 CntBaseX;
- UINT64 CntEL0BaseX;
- UINT32 GTxPhysicalTimerGSIV;
- UINT32 GTxPhysicalTimerFlags;
- UINT32 GTxVirtualTimerGSIV;
- UINT32 GTxVirtualTimerFlags;
- UINT32 GTxCommonFlags;
+ UINT8 GTFrameNumber;
+ UINT8 Reserved[3];
+ UINT64 CntBaseX;
+ UINT64 CntEL0BaseX;
+ UINT32 GTxPhysicalTimerGSIV;
+ UINT32 GTxPhysicalTimerFlags;
+ UINT32 GTxVirtualTimerGSIV;
+ UINT32 GTxVirtualTimerFlags;
+ UINT32 GTxCommonFlags;
} EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_STRUCTURE;
///
/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
-#define EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
///
/// Common Flags Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_0_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0
-#define EFI_ACPI_6_0_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1
+#define EFI_ACPI_6_0_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0
+#define EFI_ACPI_6_0_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1
///
/// SBSA Generic Watchdog Structure
///
typedef struct {
- UINT8 Type;
- UINT16 Length;
- UINT8 Reserved;
- UINT64 RefreshFramePhysicalAddress;
- UINT64 WatchdogControlFramePhysicalAddress;
- UINT32 WatchdogTimerGSIV;
- UINT32 WatchdogTimerFlags;
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 RefreshFramePhysicalAddress;
+ UINT64 WatchdogControlFramePhysicalAddress;
+ UINT32 WatchdogTimerGSIV;
+ UINT32 WatchdogTimerFlags;
} EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;
///
/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0
-#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1
-#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2
+#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2
//
// NVDIMM Firmware Interface Table definition.
@@ -1362,7 +1362,7 @@ typedef struct {
//
// NFIT Version (as defined in ACPI 6.0 spec.)
//
-#define EFI_ACPI_6_0_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
+#define EFI_ACPI_6_0_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
//
// Definition for NFIT Table Structure Types
@@ -1379,46 +1379,46 @@ typedef struct {
// Definition for NFIT Structure Header
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
+ UINT16 Type;
+ UINT16 Length;
} EFI_ACPI_6_0_NFIT_STRUCTURE_HEADER;
//
// Definition for System Physical Address Range Structure
//
-#define EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0
-#define EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1
-#define EFI_ACPI_6_0_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
-#define EFI_ACPI_6_0_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
-#define EFI_ACPI_6_0_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
-#define EFI_ACPI_6_0_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
-#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
-#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
-#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
-#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
+#define EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0
+#define EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1
+#define EFI_ACPI_6_0_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
+#define EFI_ACPI_6_0_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
+#define EFI_ACPI_6_0_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
+#define EFI_ACPI_6_0_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
+#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
+#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
+#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
+#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT16 SPARangeStructureIndex;
- UINT16 Flags;
- UINT32 Reserved_8;
- UINT32 ProximityDomain;
- GUID AddressRangeTypeGUID;
- UINT64 SystemPhysicalAddressRangeBase;
- UINT64 SystemPhysicalAddressRangeLength;
- UINT64 AddressRangeMemoryMappingAttribute;
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 SPARangeStructureIndex;
+ UINT16 Flags;
+ UINT32 Reserved_8;
+ UINT32 ProximityDomain;
+ GUID AddressRangeTypeGUID;
+ UINT64 SystemPhysicalAddressRangeBase;
+ UINT64 SystemPhysicalAddressRangeLength;
+ UINT64 AddressRangeMemoryMappingAttribute;
} EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;
//
// Definition for Memory Device to System Physical Address Range Mapping Structure
//
typedef struct {
- UINT32 DIMMNumber:4;
- UINT32 MemoryChannelNumber:4;
- UINT32 MemoryControllerID:4;
- UINT32 SocketID:4;
- UINT32 NodeControllerID:12;
- UINT32 Reserved_28:4;
+ UINT32 DIMMNumber : 4;
+ UINT32 MemoryChannelNumber : 4;
+ UINT32 MemoryControllerID : 4;
+ UINT32 SocketID : 4;
+ UINT32 NodeControllerID : 12;
+ UINT32 Reserved_28 : 4;
} EFI_ACPI_6_0_NFIT_DEVICE_HANDLE;
#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0
@@ -1428,155 +1428,161 @@ typedef struct {
#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF BIT4
#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5
typedef struct {
- UINT16 Type;
- UINT16 Length;
- EFI_ACPI_6_0_NFIT_DEVICE_HANDLE NFITDeviceHandle;
- UINT16 MemoryDevicePhysicalID;
- UINT16 MemoryDeviceRegionID;
- UINT16 SPARangeStructureIndex ;
- UINT16 NVDIMMControlRegionStructureIndex;
- UINT64 MemoryDeviceRegionSize;
- UINT64 RegionOffset;
- UINT64 MemoryDevicePhysicalAddressRegionBase;
- UINT16 InterleaveStructureIndex;
- UINT16 InterleaveWays;
- UINT16 MemoryDeviceStateFlags;
- UINT16 Reserved_46;
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_0_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 MemoryDevicePhysicalID;
+ UINT16 MemoryDeviceRegionID;
+ UINT16 SPARangeStructureIndex;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT64 MemoryDeviceRegionSize;
+ UINT64 RegionOffset;
+ UINT64 MemoryDevicePhysicalAddressRegionBase;
+ UINT16 InterleaveStructureIndex;
+ UINT16 InterleaveWays;
+ UINT16 MemoryDeviceStateFlags;
+ UINT16 Reserved_46;
} EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_TO_SYSTEM_ADDRESS_RANGE_MAP_STRUCTURE;
//
// Definition for Interleave Structure
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT16 InterleaveStructureIndex;
- UINT16 Reserved_6;
- UINT32 NumberOfLines;
- UINT32 LineSize;
-//UINT32 LineOffset[NumberOfLines];
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 InterleaveStructureIndex;
+ UINT16 Reserved_6;
+ UINT32 NumberOfLines;
+ UINT32 LineSize;
+ // UINT32 LineOffset[NumberOfLines];
} EFI_ACPI_6_0_NFIT_INTERLEAVE_STRUCTURE;
//
// Definition for SMBIOS Management Information Structure
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT32 Reserved_4;
-//UINT8 Data[];
+ UINT16 Type;
+ UINT16 Length;
+ UINT32 Reserved_4;
+ // UINT8 Data[];
} EFI_ACPI_6_0_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;
//
// Definition for NVDIMM Control Region Structure
//
-#define EFI_ACPI_6_0_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0
+#define EFI_ACPI_6_0_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT16 NVDIMMControlRegionStructureIndex;
- UINT16 VendorID;
- UINT16 DeviceID;
- UINT16 RevisionID;
- UINT16 SubsystemVendorID;
- UINT16 SubsystemDeviceID;
- UINT16 SubsystemRevisionID;
- UINT8 Reserved_18[6];
- UINT32 SerialNumber;
- UINT16 RegionFormatInterfaceCode;
- UINT16 NumberOfBlockControlWindows;
- UINT64 SizeOfBlockControlWindow;
- UINT64 CommandRegisterOffsetInBlockControlWindow;
- UINT64 SizeOfCommandRegisterInBlockControlWindows;
- UINT64 StatusRegisterOffsetInBlockControlWindow;
- UINT64 SizeOfStatusRegisterInBlockControlWindows;
- UINT16 NVDIMMControlRegionFlag;
- UINT8 Reserved_74[6];
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT8 Reserved_18[6];
+ UINT32 SerialNumber;
+ UINT16 RegionFormatInterfaceCode;
+ UINT16 NumberOfBlockControlWindows;
+ UINT64 SizeOfBlockControlWindow;
+ UINT64 CommandRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfCommandRegisterInBlockControlWindows;
+ UINT64 StatusRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfStatusRegisterInBlockControlWindows;
+ UINT16 NVDIMMControlRegionFlag;
+ UINT8 Reserved_74[6];
} EFI_ACPI_6_0_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;
//
// Definition for NVDIMM Block Data Window Region Structure
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT16 NVDIMMControlRegionStructureIndex;
- UINT16 NumberOfBlockDataWindows;
- UINT64 BlockDataWindowStartOffset;
- UINT64 SizeOfBlockDataWindow;
- UINT64 BlockAccessibleMemoryCapacity;
- UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 NumberOfBlockDataWindows;
+ UINT64 BlockDataWindowStartOffset;
+ UINT64 SizeOfBlockDataWindow;
+ UINT64 BlockAccessibleMemoryCapacity;
+ UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;
} EFI_ACPI_6_0_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;
//
// Definition for Flush Hint Address Structure
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
- EFI_ACPI_6_0_NFIT_DEVICE_HANDLE NFITDeviceHandle;
- UINT16 NumberOfFlushHintAddresses;
- UINT8 Reserved_10[6];
-//UINT64 FlushHintAddress[NumberOfFlushHintAddresses];
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_0_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NumberOfFlushHintAddresses;
+ UINT8 Reserved_10[6];
+ // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];
} EFI_ACPI_6_0_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;
///
/// Boot Error Record Table (BERT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 BootErrorRegionLength;
- UINT64 BootErrorRegion;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 BootErrorRegionLength;
+ UINT64 BootErrorRegion;
} EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_HEADER;
///
/// BERT Version (as defined in ACPI 6.0 spec.)
///
-#define EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+#define EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
///
/// Boot Error Region Block Status Definition
///
typedef struct {
- UINT32 UncorrectableErrorValid:1;
- UINT32 CorrectableErrorValid:1;
- UINT32 MultipleUncorrectableErrors:1;
- UINT32 MultipleCorrectableErrors:1;
- UINT32 ErrorDataEntryCount:10;
- UINT32 Reserved:18;
+ UINT32 UncorrectableErrorValid : 1;
+ UINT32 CorrectableErrorValid : 1;
+ UINT32 MultipleUncorrectableErrors : 1;
+ UINT32 MultipleCorrectableErrors : 1;
+ UINT32 ErrorDataEntryCount : 10;
+ UINT32 Reserved : 18;
} EFI_ACPI_6_0_ERROR_BLOCK_STATUS;
///
/// Boot Error Region Definition
///
typedef struct {
- EFI_ACPI_6_0_ERROR_BLOCK_STATUS BlockStatus;
- UINT32 RawDataOffset;
- UINT32 RawDataLength;
- UINT32 DataLength;
- UINT32 ErrorSeverity;
+ EFI_ACPI_6_0_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
} EFI_ACPI_6_0_BOOT_ERROR_REGION_STRUCTURE;
//
// Boot Error Severity types
//
-#define EFI_ACPI_6_0_ERROR_SEVERITY_CORRECTABLE 0x00
+#define EFI_ACPI_6_0_ERROR_SEVERITY_RECOVERABLE 0x00
#define EFI_ACPI_6_0_ERROR_SEVERITY_FATAL 0x01
#define EFI_ACPI_6_0_ERROR_SEVERITY_CORRECTED 0x02
#define EFI_ACPI_6_0_ERROR_SEVERITY_NONE 0x03
+//
+// The term 'Correctable' is no longer being used as an error severity of the
+// reported error since ACPI Specification Version 5.1 Errata B.
+// The below macro is considered as deprecated and should no longer be used.
+//
+#define EFI_ACPI_6_0_ERROR_SEVERITY_CORRECTABLE 0x00
///
/// Generic Error Data Entry Definition
///
typedef struct {
- UINT8 SectionType[16];
- UINT32 ErrorSeverity;
- UINT16 Revision;
- UINT8 ValidationBits;
- UINT8 Flags;
- UINT32 ErrorDataLength;
- UINT8 FruId[16];
- UINT8 FruText[20];
+ UINT8 SectionType[16];
+ UINT32 ErrorSeverity;
+ UINT16 Revision;
+ UINT8 ValidationBits;
+ UINT8 Flags;
+ UINT32 ErrorDataLength;
+ UINT8 FruId[16];
+ UINT8 FruText[20];
} EFI_ACPI_6_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
///
@@ -1588,14 +1594,14 @@ typedef struct {
/// HEST - Hardware Error Source Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 ErrorSourceCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 ErrorSourceCount;
} EFI_ACPI_6_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
///
/// HEST Version (as defined in ACPI 6.0 spec.)
///
-#define EFI_ACPI_6_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+#define EFI_ACPI_6_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
//
// Error Source structure types.
@@ -1611,437 +1617,437 @@ typedef struct {
//
// Error Source structure flags.
//
-#define EFI_ACPI_6_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
-#define EFI_ACPI_6_0_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
+#define EFI_ACPI_6_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
+#define EFI_ACPI_6_0_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
///
/// IA-32 Architecture Machine Check Exception Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT64 GlobalCapabilityInitData;
- UINT64 GlobalControlInitData;
- UINT8 NumberOfHardwareBanks;
- UINT8 Reserved1[7];
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT64 GlobalCapabilityInitData;
+ UINT64 GlobalControlInitData;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[7];
} EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
///
/// IA-32 Architecture Machine Check Bank Structure Definition
///
typedef struct {
- UINT8 BankNumber;
- UINT8 ClearStatusOnInitialization;
- UINT8 StatusDataFormat;
- UINT8 Reserved0;
- UINT32 ControlRegisterMsrAddress;
- UINT64 ControlInitData;
- UINT32 StatusRegisterMsrAddress;
- UINT32 AddressRegisterMsrAddress;
- UINT32 MiscRegisterMsrAddress;
+ UINT8 BankNumber;
+ UINT8 ClearStatusOnInitialization;
+ UINT8 StatusDataFormat;
+ UINT8 Reserved0;
+ UINT32 ControlRegisterMsrAddress;
+ UINT64 ControlInitData;
+ UINT32 StatusRegisterMsrAddress;
+ UINT32 AddressRegisterMsrAddress;
+ UINT32 MiscRegisterMsrAddress;
} EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
///
/// IA-32 Architecture Machine Check Bank Structure MCA data format
///
-#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
-#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
-#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
+#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
+#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
+#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
//
// Hardware Error Notification types. All other values are reserved
//
-#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
-#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
-#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
-#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
-#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
-#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05
-#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_MCE 0x06
-#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_MCE 0x06
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07
///
/// Hardware Error Notification Configuration Write Enable Structure Definition
///
typedef struct {
- UINT16 Type:1;
- UINT16 PollInterval:1;
- UINT16 SwitchToPollingThresholdValue:1;
- UINT16 SwitchToPollingThresholdWindow:1;
- UINT16 ErrorThresholdValue:1;
- UINT16 ErrorThresholdWindow:1;
- UINT16 Reserved:10;
+ UINT16 Type : 1;
+ UINT16 PollInterval : 1;
+ UINT16 SwitchToPollingThresholdValue : 1;
+ UINT16 SwitchToPollingThresholdWindow : 1;
+ UINT16 ErrorThresholdValue : 1;
+ UINT16 ErrorThresholdWindow : 1;
+ UINT16 Reserved : 10;
} EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
///
/// Hardware Error Notification Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
- UINT32 PollInterval;
- UINT32 Vector;
- UINT32 SwitchToPollingThresholdValue;
- UINT32 SwitchToPollingThresholdWindow;
- UINT32 ErrorThresholdValue;
- UINT32 ErrorThresholdWindow;
+ UINT8 Type;
+ UINT8 Length;
+ EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
+ UINT32 PollInterval;
+ UINT32 Vector;
+ UINT32 SwitchToPollingThresholdValue;
+ UINT32 SwitchToPollingThresholdWindow;
+ UINT32 ErrorThresholdValue;
+ UINT32 ErrorThresholdWindow;
} EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
///
/// IA-32 Architecture Corrected Machine Check Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
- UINT8 NumberOfHardwareBanks;
- UINT8 Reserved1[3];
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
} EFI_ACPI_6_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
///
/// IA-32 Architecture NMI Error Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 MaxRawDataLength;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
} EFI_ACPI_6_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
///
/// PCI Express Root Port AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
- UINT32 RootErrorCommand;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 RootErrorCommand;
} EFI_ACPI_6_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
///
/// PCI Express Device AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
} EFI_ACPI_6_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
///
/// PCI Express Bridge AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
- UINT32 SecondaryUncorrectableErrorMask;
- UINT32 SecondaryUncorrectableErrorSeverity;
- UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 SecondaryUncorrectableErrorMask;
+ UINT32 SecondaryUncorrectableErrorSeverity;
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
} EFI_ACPI_6_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
///
/// Generic Hardware Error Source Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT16 RelatedSourceId;
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 MaxRawDataLength;
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
- EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
- UINT32 ErrorStatusBlockLength;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
} EFI_ACPI_6_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
///
/// Generic Error Status Definition
///
typedef struct {
- EFI_ACPI_6_0_ERROR_BLOCK_STATUS BlockStatus;
- UINT32 RawDataOffset;
- UINT32 RawDataLength;
- UINT32 DataLength;
- UINT32 ErrorSeverity;
+ EFI_ACPI_6_0_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
} EFI_ACPI_6_0_GENERIC_ERROR_STATUS_STRUCTURE;
///
/// ERST - Error Record Serialization Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 SerializationHeaderSize;
- UINT8 Reserved0[4];
- UINT32 InstructionEntryCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 SerializationHeaderSize;
+ UINT8 Reserved0[4];
+ UINT32 InstructionEntryCount;
} EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
///
/// ERST Version (as defined in ACPI 6.0 spec.)
///
-#define EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
///
/// ERST Serialization Actions
///
-#define EFI_ACPI_6_0_ERST_BEGIN_WRITE_OPERATION 0x00
-#define EFI_ACPI_6_0_ERST_BEGIN_READ_OPERATION 0x01
-#define EFI_ACPI_6_0_ERST_BEGIN_CLEAR_OPERATION 0x02
-#define EFI_ACPI_6_0_ERST_END_OPERATION 0x03
-#define EFI_ACPI_6_0_ERST_SET_RECORD_OFFSET 0x04
-#define EFI_ACPI_6_0_ERST_EXECUTE_OPERATION 0x05
-#define EFI_ACPI_6_0_ERST_CHECK_BUSY_STATUS 0x06
-#define EFI_ACPI_6_0_ERST_GET_COMMAND_STATUS 0x07
-#define EFI_ACPI_6_0_ERST_GET_RECORD_IDENTIFIER 0x08
-#define EFI_ACPI_6_0_ERST_SET_RECORD_IDENTIFIER 0x09
-#define EFI_ACPI_6_0_ERST_GET_RECORD_COUNT 0x0A
-#define EFI_ACPI_6_0_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
-#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
-#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
-#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
+#define EFI_ACPI_6_0_ERST_BEGIN_WRITE_OPERATION 0x00
+#define EFI_ACPI_6_0_ERST_BEGIN_READ_OPERATION 0x01
+#define EFI_ACPI_6_0_ERST_BEGIN_CLEAR_OPERATION 0x02
+#define EFI_ACPI_6_0_ERST_END_OPERATION 0x03
+#define EFI_ACPI_6_0_ERST_SET_RECORD_OFFSET 0x04
+#define EFI_ACPI_6_0_ERST_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_0_ERST_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_0_ERST_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_0_ERST_GET_RECORD_IDENTIFIER 0x08
+#define EFI_ACPI_6_0_ERST_SET_RECORD_IDENTIFIER 0x09
+#define EFI_ACPI_6_0_ERST_GET_RECORD_COUNT 0x0A
+#define EFI_ACPI_6_0_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
+#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
+#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
+#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
///
/// ERST Action Command Status
///
-#define EFI_ACPI_6_0_ERST_STATUS_SUCCESS 0x00
-#define EFI_ACPI_6_0_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
-#define EFI_ACPI_6_0_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
-#define EFI_ACPI_6_0_ERST_STATUS_FAILED 0x03
-#define EFI_ACPI_6_0_ERST_STATUS_RECORD_STORE_EMPTY 0x04
-#define EFI_ACPI_6_0_ERST_STATUS_RECORD_NOT_FOUND 0x05
+#define EFI_ACPI_6_0_ERST_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_0_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
+#define EFI_ACPI_6_0_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
+#define EFI_ACPI_6_0_ERST_STATUS_FAILED 0x03
+#define EFI_ACPI_6_0_ERST_STATUS_RECORD_STORE_EMPTY 0x04
+#define EFI_ACPI_6_0_ERST_STATUS_RECORD_NOT_FOUND 0x05
///
/// ERST Serialization Instructions
///
-#define EFI_ACPI_6_0_ERST_READ_REGISTER 0x00
-#define EFI_ACPI_6_0_ERST_READ_REGISTER_VALUE 0x01
-#define EFI_ACPI_6_0_ERST_WRITE_REGISTER 0x02
-#define EFI_ACPI_6_0_ERST_WRITE_REGISTER_VALUE 0x03
-#define EFI_ACPI_6_0_ERST_NOOP 0x04
-#define EFI_ACPI_6_0_ERST_LOAD_VAR1 0x05
-#define EFI_ACPI_6_0_ERST_LOAD_VAR2 0x06
-#define EFI_ACPI_6_0_ERST_STORE_VAR1 0x07
-#define EFI_ACPI_6_0_ERST_ADD 0x08
-#define EFI_ACPI_6_0_ERST_SUBTRACT 0x09
-#define EFI_ACPI_6_0_ERST_ADD_VALUE 0x0A
-#define EFI_ACPI_6_0_ERST_SUBTRACT_VALUE 0x0B
-#define EFI_ACPI_6_0_ERST_STALL 0x0C
-#define EFI_ACPI_6_0_ERST_STALL_WHILE_TRUE 0x0D
-#define EFI_ACPI_6_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
-#define EFI_ACPI_6_0_ERST_GOTO 0x0F
-#define EFI_ACPI_6_0_ERST_SET_SRC_ADDRESS_BASE 0x10
-#define EFI_ACPI_6_0_ERST_SET_DST_ADDRESS_BASE 0x11
-#define EFI_ACPI_6_0_ERST_MOVE_DATA 0x12
+#define EFI_ACPI_6_0_ERST_READ_REGISTER 0x00
+#define EFI_ACPI_6_0_ERST_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_0_ERST_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_0_ERST_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_0_ERST_NOOP 0x04
+#define EFI_ACPI_6_0_ERST_LOAD_VAR1 0x05
+#define EFI_ACPI_6_0_ERST_LOAD_VAR2 0x06
+#define EFI_ACPI_6_0_ERST_STORE_VAR1 0x07
+#define EFI_ACPI_6_0_ERST_ADD 0x08
+#define EFI_ACPI_6_0_ERST_SUBTRACT 0x09
+#define EFI_ACPI_6_0_ERST_ADD_VALUE 0x0A
+#define EFI_ACPI_6_0_ERST_SUBTRACT_VALUE 0x0B
+#define EFI_ACPI_6_0_ERST_STALL 0x0C
+#define EFI_ACPI_6_0_ERST_STALL_WHILE_TRUE 0x0D
+#define EFI_ACPI_6_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
+#define EFI_ACPI_6_0_ERST_GOTO 0x0F
+#define EFI_ACPI_6_0_ERST_SET_SRC_ADDRESS_BASE 0x10
+#define EFI_ACPI_6_0_ERST_SET_DST_ADDRESS_BASE 0x11
+#define EFI_ACPI_6_0_ERST_MOVE_DATA 0x12
///
/// ERST Instruction Flags
///
-#define EFI_ACPI_6_0_ERST_PRESERVE_REGISTER 0x01
+#define EFI_ACPI_6_0_ERST_PRESERVE_REGISTER 0x01
///
/// ERST Serialization Instruction Entry
///
typedef struct {
- UINT8 SerializationAction;
- UINT8 Instruction;
- UINT8 Flags;
- UINT8 Reserved0;
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
- UINT64 Value;
- UINT64 Mask;
+ UINT8 SerializationAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
} EFI_ACPI_6_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
///
/// EINJ - Error Injection Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 InjectionHeaderSize;
- UINT8 InjectionFlags;
- UINT8 Reserved0[3];
- UINT32 InjectionEntryCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 InjectionHeaderSize;
+ UINT8 InjectionFlags;
+ UINT8 Reserved0[3];
+ UINT32 InjectionEntryCount;
} EFI_ACPI_6_0_ERROR_INJECTION_TABLE_HEADER;
///
/// EINJ Version (as defined in ACPI 6.0 spec.)
///
-#define EFI_ACPI_6_0_ERROR_INJECTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_0_ERROR_INJECTION_TABLE_REVISION 0x01
///
/// EINJ Error Injection Actions
///
-#define EFI_ACPI_6_0_EINJ_BEGIN_INJECTION_OPERATION 0x00
-#define EFI_ACPI_6_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
-#define EFI_ACPI_6_0_EINJ_SET_ERROR_TYPE 0x02
-#define EFI_ACPI_6_0_EINJ_GET_ERROR_TYPE 0x03
-#define EFI_ACPI_6_0_EINJ_END_OPERATION 0x04
-#define EFI_ACPI_6_0_EINJ_EXECUTE_OPERATION 0x05
-#define EFI_ACPI_6_0_EINJ_CHECK_BUSY_STATUS 0x06
-#define EFI_ACPI_6_0_EINJ_GET_COMMAND_STATUS 0x07
-#define EFI_ACPI_6_0_EINJ_TRIGGER_ERROR 0xFF
+#define EFI_ACPI_6_0_EINJ_BEGIN_INJECTION_OPERATION 0x00
+#define EFI_ACPI_6_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
+#define EFI_ACPI_6_0_EINJ_SET_ERROR_TYPE 0x02
+#define EFI_ACPI_6_0_EINJ_GET_ERROR_TYPE 0x03
+#define EFI_ACPI_6_0_EINJ_END_OPERATION 0x04
+#define EFI_ACPI_6_0_EINJ_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_0_EINJ_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_0_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_0_EINJ_TRIGGER_ERROR 0xFF
///
/// EINJ Action Command Status
///
-#define EFI_ACPI_6_0_EINJ_STATUS_SUCCESS 0x00
-#define EFI_ACPI_6_0_EINJ_STATUS_UNKNOWN_FAILURE 0x01
-#define EFI_ACPI_6_0_EINJ_STATUS_INVALID_ACCESS 0x02
+#define EFI_ACPI_6_0_EINJ_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_0_EINJ_STATUS_UNKNOWN_FAILURE 0x01
+#define EFI_ACPI_6_0_EINJ_STATUS_INVALID_ACCESS 0x02
///
/// EINJ Error Type Definition
///
-#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
-#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
-#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
-#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
-#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
-#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
-#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
-#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
-#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
-#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
-#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
-#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
+#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
+#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
+#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
+#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
+#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
+#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
+#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
+#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
+#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
+#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
+#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
+#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
///
/// EINJ Injection Instructions
///
-#define EFI_ACPI_6_0_EINJ_READ_REGISTER 0x00
-#define EFI_ACPI_6_0_EINJ_READ_REGISTER_VALUE 0x01
-#define EFI_ACPI_6_0_EINJ_WRITE_REGISTER 0x02
-#define EFI_ACPI_6_0_EINJ_WRITE_REGISTER_VALUE 0x03
-#define EFI_ACPI_6_0_EINJ_NOOP 0x04
+#define EFI_ACPI_6_0_EINJ_READ_REGISTER 0x00
+#define EFI_ACPI_6_0_EINJ_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_0_EINJ_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_0_EINJ_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_0_EINJ_NOOP 0x04
///
/// EINJ Instruction Flags
///
-#define EFI_ACPI_6_0_EINJ_PRESERVE_REGISTER 0x01
+#define EFI_ACPI_6_0_EINJ_PRESERVE_REGISTER 0x01
///
/// EINJ Injection Instruction Entry
///
typedef struct {
- UINT8 InjectionAction;
- UINT8 Instruction;
- UINT8 Flags;
- UINT8 Reserved0;
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
- UINT64 Value;
- UINT64 Mask;
+ UINT8 InjectionAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
} EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY;
///
/// EINJ Trigger Action Table
///
typedef struct {
- UINT32 HeaderSize;
- UINT32 Revision;
- UINT32 TableSize;
- UINT32 EntryCount;
+ UINT32 HeaderSize;
+ UINT32 Revision;
+ UINT32 TableSize;
+ UINT32 EntryCount;
} EFI_ACPI_6_0_EINJ_TRIGGER_ACTION_TABLE;
///
/// Platform Communications Channel Table (PCCT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Flags;
- UINT64 Reserved;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Flags;
+ UINT64 Reserved;
} EFI_ACPI_6_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
///
/// PCCT Version (as defined in ACPI 6.0 spec.)
///
-#define EFI_ACPI_6_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01
+#define EFI_ACPI_6_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01
///
/// PCCT Global Flags
///
-#define EFI_ACPI_6_0_PCCT_FLAGS_SCI_DOORBELL BIT0
+#define EFI_ACPI_6_0_PCCT_FLAGS_SCI_DOORBELL BIT0
//
// PCCT Subspace type
//
-#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_GENERIC 0x00
-#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01
-#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_GENERIC 0x00
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02
///
/// PCC Subspace Structure Header
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
+ UINT8 Type;
+ UINT8 Length;
} EFI_ACPI_6_0_PCCT_SUBSPACE_HEADER;
///
/// Generic Communications Subspace Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[6];
- UINT64 BaseAddress;
- UINT64 AddressLength;
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
- UINT64 DoorbellPreserve;
- UINT64 DoorbellWrite;
- UINT32 NominalLatency;
- UINT32 MaximumPeriodicAccessRate;
- UINT16 MinimumRequestTurnaroundTime;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[6];
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
} EFI_ACPI_6_0_PCCT_SUBSPACE_GENERIC;
///
@@ -2049,18 +2055,18 @@ typedef struct {
///
typedef struct {
- UINT8 Command;
- UINT8 Reserved:7;
- UINT8 GenerateSci:1;
+ UINT8 Command;
+ UINT8 Reserved : 7;
+ UINT8 GenerateSci : 1;
} EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
typedef struct {
- UINT8 CommandComplete:1;
- UINT8 SciDoorbell:1;
- UINT8 Error:1;
- UINT8 PlatformNotification:1;
- UINT8 Reserved:4;
- UINT8 Reserved1;
+ UINT8 CommandComplete : 1;
+ UINT8 SciDoorbell : 1;
+ UINT8 Error : 1;
+ UINT8 PlatformNotification : 1;
+ UINT8 Reserved : 4;
+ UINT8 Reserved1;
} EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
typedef struct {
@@ -2069,48 +2075,48 @@ typedef struct {
EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;
} EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
-#define EFI_ACPI_6_0_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_POLARITY BIT0
-#define EFI_ACPI_6_0_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_MODE BIT1
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_POLARITY BIT0
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_MODE BIT1
///
/// Type 1 HW-Reduced Communications Subspace Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 DoorbellInterrupt;
- UINT8 DoorbellInterruptFlags;
- UINT8 Reserved;
- UINT64 BaseAddress;
- UINT64 AddressLength;
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
- UINT64 DoorbellPreserve;
- UINT64 DoorbellWrite;
- UINT32 NominalLatency;
- UINT32 MaximumPeriodicAccessRate;
- UINT16 MinimumRequestTurnaroundTime;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 DoorbellInterrupt;
+ UINT8 DoorbellInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
} EFI_ACPI_6_0_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
///
/// Type 2 HW-Reduced Communications Subspace Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 DoorbellInterrupt;
- UINT8 DoorbellInterruptFlags;
- UINT8 Reserved;
- UINT64 BaseAddress;
- UINT64 AddressLength;
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
- UINT64 DoorbellPreserve;
- UINT64 DoorbellWrite;
- UINT32 NominalLatency;
- UINT32 MaximumPeriodicAccessRate;
- UINT16 MinimumRequestTurnaroundTime;
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellAckRegister;
- UINT64 DoorbellAckPreserve;
- UINT64 DoorbellAckWrite;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 DoorbellInterrupt;
+ UINT8 DoorbellInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellAckRegister;
+ UINT64 DoorbellAckPreserve;
+ UINT64 DoorbellAckWrite;
} EFI_ACPI_6_0_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
//
diff --git a/MdePkg/Include/IndustryStandard/Acpi61.h b/MdePkg/Include/IndustryStandard/Acpi61.h
index 31ba4e72..94cfe8b0 100644
--- a/MdePkg/Include/IndustryStandard/Acpi61.h
+++ b/MdePkg/Include/IndustryStandard/Acpi61.h
@@ -1,7 +1,7 @@
/** @file
ACPI 6.1 definitions from the ACPI Specification Revision 6.1 January, 2016.
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.
(C) Copyright 2016 Hewlett Packard Enterprise Development LP
Copyright (c) 2020, ARM Ltd. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -21,21 +21,21 @@
/// ACPI 6.1 Generic Address Space definition
///
typedef struct {
- UINT8 AddressSpaceId;
- UINT8 RegisterBitWidth;
- UINT8 RegisterBitOffset;
- UINT8 AccessSize;
- UINT64 Address;
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
} EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE;
//
// Generic Address Space Address IDs
//
-#define EFI_ACPI_6_1_SYSTEM_MEMORY 0
-#define EFI_ACPI_6_1_SYSTEM_IO 1
-#define EFI_ACPI_6_1_PCI_CONFIGURATION_SPACE 2
-#define EFI_ACPI_6_1_EMBEDDED_CONTROLLER 3
-#define EFI_ACPI_6_1_SMBUS 4
+#define EFI_ACPI_6_1_SYSTEM_MEMORY 0
+#define EFI_ACPI_6_1_SYSTEM_IO 1
+#define EFI_ACPI_6_1_PCI_CONFIGURATION_SPACE 2
+#define EFI_ACPI_6_1_EMBEDDED_CONTROLLER 3
+#define EFI_ACPI_6_1_SMBUS 4
#define EFI_ACPI_6_1_PLATFORM_COMMUNICATION_CHANNEL 0x0A
#define EFI_ACPI_6_1_FUNCTIONAL_FIXED_HARDWARE 0x7F
@@ -56,29 +56,29 @@ typedef struct {
/// Root System Description Pointer Structure
///
typedef struct {
- UINT64 Signature;
- UINT8 Checksum;
- UINT8 OemId[6];
- UINT8 Revision;
- UINT32 RsdtAddress;
- UINT32 Length;
- UINT64 XsdtAddress;
- UINT8 ExtendedChecksum;
- UINT8 Reserved[3];
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
} EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER;
///
/// RSD_PTR Revision (as defined in ACPI 6.1 spec.)
///
-#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.1) says current value is 2
+#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.1) says current value is 2
///
/// Common table header, this prefaces all ACPI tables, including FACS, but
/// excluding the RSD PTR structure
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
+ UINT32 Signature;
+ UINT32 Length;
} EFI_ACPI_6_1_COMMON_HEADER;
//
@@ -90,7 +90,7 @@ typedef struct {
///
/// RSDT Revision (as defined in ACPI 6.1 spec.)
///
-#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
//
// Extended System Description Table
@@ -101,74 +101,74 @@ typedef struct {
///
/// XSDT Revision (as defined in ACPI 6.1 spec.)
///
-#define EFI_ACPI_6_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
///
/// Fixed ACPI Description Table Structure (FADT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 FirmwareCtrl;
- UINT32 Dsdt;
- UINT8 Reserved0;
- UINT8 PreferredPmProfile;
- UINT16 SciInt;
- UINT32 SmiCmd;
- UINT8 AcpiEnable;
- UINT8 AcpiDisable;
- UINT8 S4BiosReq;
- UINT8 PstateCnt;
- UINT32 Pm1aEvtBlk;
- UINT32 Pm1bEvtBlk;
- UINT32 Pm1aCntBlk;
- UINT32 Pm1bCntBlk;
- UINT32 Pm2CntBlk;
- UINT32 PmTmrBlk;
- UINT32 Gpe0Blk;
- UINT32 Gpe1Blk;
- UINT8 Pm1EvtLen;
- UINT8 Pm1CntLen;
- UINT8 Pm2CntLen;
- UINT8 PmTmrLen;
- UINT8 Gpe0BlkLen;
- UINT8 Gpe1BlkLen;
- UINT8 Gpe1Base;
- UINT8 CstCnt;
- UINT16 PLvl2Lat;
- UINT16 PLvl3Lat;
- UINT16 FlushSize;
- UINT16 FlushStride;
- UINT8 DutyOffset;
- UINT8 DutyWidth;
- UINT8 DayAlrm;
- UINT8 MonAlrm;
- UINT8 Century;
- UINT16 IaPcBootArch;
- UINT8 Reserved1;
- UINT32 Flags;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResetReg;
- UINT8 ResetValue;
- UINT16 ArmBootArch;
- UINT8 MinorVersion;
- UINT64 XFirmwareCtrl;
- UINT64 XDsdt;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
- UINT64 HypervisorVendorIdentity;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT16 ArmBootArch;
+ UINT8 MinorVersion;
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
+ UINT64 HypervisorVendorIdentity;
} EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE;
///
/// FADT Version (as defined in ACPI 6.1 spec.)
///
-#define EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06
+#define EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06
#define EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x01
//
@@ -188,62 +188,62 @@ typedef struct {
// Fixed ACPI Description Table Boot Architecture Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_6_1_LEGACY_DEVICES BIT0
-#define EFI_ACPI_6_1_8042 BIT1
-#define EFI_ACPI_6_1_VGA_NOT_PRESENT BIT2
-#define EFI_ACPI_6_1_MSI_NOT_SUPPORTED BIT3
-#define EFI_ACPI_6_1_PCIE_ASPM_CONTROLS BIT4
-#define EFI_ACPI_6_1_CMOS_RTC_NOT_PRESENT BIT5
+#define EFI_ACPI_6_1_LEGACY_DEVICES BIT0
+#define EFI_ACPI_6_1_8042 BIT1
+#define EFI_ACPI_6_1_VGA_NOT_PRESENT BIT2
+#define EFI_ACPI_6_1_MSI_NOT_SUPPORTED BIT3
+#define EFI_ACPI_6_1_PCIE_ASPM_CONTROLS BIT4
+#define EFI_ACPI_6_1_CMOS_RTC_NOT_PRESENT BIT5
//
// Fixed ACPI Description Table Arm Boot Architecture Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_6_1_ARM_PSCI_COMPLIANT BIT0
-#define EFI_ACPI_6_1_ARM_PSCI_USE_HVC BIT1
+#define EFI_ACPI_6_1_ARM_PSCI_COMPLIANT BIT0
+#define EFI_ACPI_6_1_ARM_PSCI_USE_HVC BIT1
//
// Fixed ACPI Description Table Fixed Feature Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_6_1_WBINVD BIT0
-#define EFI_ACPI_6_1_WBINVD_FLUSH BIT1
-#define EFI_ACPI_6_1_PROC_C1 BIT2
-#define EFI_ACPI_6_1_P_LVL2_UP BIT3
-#define EFI_ACPI_6_1_PWR_BUTTON BIT4
-#define EFI_ACPI_6_1_SLP_BUTTON BIT5
-#define EFI_ACPI_6_1_FIX_RTC BIT6
-#define EFI_ACPI_6_1_RTC_S4 BIT7
-#define EFI_ACPI_6_1_TMR_VAL_EXT BIT8
-#define EFI_ACPI_6_1_DCK_CAP BIT9
-#define EFI_ACPI_6_1_RESET_REG_SUP BIT10
-#define EFI_ACPI_6_1_SEALED_CASE BIT11
-#define EFI_ACPI_6_1_HEADLESS BIT12
-#define EFI_ACPI_6_1_CPU_SW_SLP BIT13
-#define EFI_ACPI_6_1_PCI_EXP_WAK BIT14
-#define EFI_ACPI_6_1_USE_PLATFORM_CLOCK BIT15
-#define EFI_ACPI_6_1_S4_RTC_STS_VALID BIT16
-#define EFI_ACPI_6_1_REMOTE_POWER_ON_CAPABLE BIT17
-#define EFI_ACPI_6_1_FORCE_APIC_CLUSTER_MODEL BIT18
-#define EFI_ACPI_6_1_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
-#define EFI_ACPI_6_1_HW_REDUCED_ACPI BIT20
-#define EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE BIT21
+#define EFI_ACPI_6_1_WBINVD BIT0
+#define EFI_ACPI_6_1_WBINVD_FLUSH BIT1
+#define EFI_ACPI_6_1_PROC_C1 BIT2
+#define EFI_ACPI_6_1_P_LVL2_UP BIT3
+#define EFI_ACPI_6_1_PWR_BUTTON BIT4
+#define EFI_ACPI_6_1_SLP_BUTTON BIT5
+#define EFI_ACPI_6_1_FIX_RTC BIT6
+#define EFI_ACPI_6_1_RTC_S4 BIT7
+#define EFI_ACPI_6_1_TMR_VAL_EXT BIT8
+#define EFI_ACPI_6_1_DCK_CAP BIT9
+#define EFI_ACPI_6_1_RESET_REG_SUP BIT10
+#define EFI_ACPI_6_1_SEALED_CASE BIT11
+#define EFI_ACPI_6_1_HEADLESS BIT12
+#define EFI_ACPI_6_1_CPU_SW_SLP BIT13
+#define EFI_ACPI_6_1_PCI_EXP_WAK BIT14
+#define EFI_ACPI_6_1_USE_PLATFORM_CLOCK BIT15
+#define EFI_ACPI_6_1_S4_RTC_STS_VALID BIT16
+#define EFI_ACPI_6_1_REMOTE_POWER_ON_CAPABLE BIT17
+#define EFI_ACPI_6_1_FORCE_APIC_CLUSTER_MODEL BIT18
+#define EFI_ACPI_6_1_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+#define EFI_ACPI_6_1_HW_REDUCED_ACPI BIT20
+#define EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE BIT21
///
/// Firmware ACPI Control Structure
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
- UINT32 HardwareSignature;
- UINT32 FirmwareWakingVector;
- UINT32 GlobalLock;
- UINT32 Flags;
- UINT64 XFirmwareWakingVector;
- UINT8 Version;
- UINT8 Reserved0[3];
- UINT32 OspmFlags;
- UINT8 Reserved1[24];
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved0[3];
+ UINT32 OspmFlags;
+ UINT8 Reserved1[24];
} EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE;
///
@@ -255,14 +255,14 @@ typedef struct {
/// Firmware Control Structure Feature Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_6_1_S4BIOS_F BIT0
-#define EFI_ACPI_6_1_64BIT_WAKE_SUPPORTED_F BIT1
+#define EFI_ACPI_6_1_S4BIOS_F BIT0
+#define EFI_ACPI_6_1_64BIT_WAKE_SUPPORTED_F BIT1
///
/// OSPM Enabled Firmware Control Structure Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_6_1_OSPM_64BIT_WAKE_F BIT0
+#define EFI_ACPI_6_1_OSPM_64BIT_WAKE_F BIT0
//
// Differentiated System Description Table,
@@ -271,29 +271,29 @@ typedef struct {
// no definition needed as they are common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
//
-#define EFI_ACPI_6_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
-#define EFI_ACPI_6_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_6_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_6_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
///
/// Multiple APIC Description Table header definition. The rest of the table
/// must be defined in a platform specific manner.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 LocalApicAddress;
- UINT32 Flags;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
///
/// MADT Revision (as defined in ACPI 6.1 spec.)
///
-#define EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04
+#define EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04
///
/// Multiple APIC Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_6_1_PCAT_COMPAT BIT0
+#define EFI_ACPI_6_1_PCAT_COMPAT BIT0
//
// Multiple APIC Description Table APIC structure types
@@ -325,57 +325,57 @@ typedef struct {
/// Processor Local APIC Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorUid;
- UINT8 ApicId;
- UINT32 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT8 ApicId;
+ UINT32 Flags;
} EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_STRUCTURE;
///
/// Local APIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_1_LOCAL_APIC_ENABLED BIT0
+#define EFI_ACPI_6_1_LOCAL_APIC_ENABLED BIT0
///
/// IO APIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 IoApicAddress;
- UINT32 GlobalSystemInterruptBase;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
} EFI_ACPI_6_1_IO_APIC_STRUCTURE;
///
/// Interrupt Source Override Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Bus;
- UINT8 Source;
- UINT32 GlobalSystemInterrupt;
- UINT16 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
} EFI_ACPI_6_1_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
///
/// Platform Interrupt Sources Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT8 InterruptType;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT8 IoSapicVector;
- UINT32 GlobalSystemInterrupt;
- UINT32 PlatformInterruptSourceFlags;
- UINT8 CpeiProcessorOverride;
- UINT8 Reserved[31];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
} EFI_ACPI_6_1_PLATFORM_INTERRUPT_APIC_STRUCTURE;
//
@@ -389,43 +389,43 @@ typedef struct {
/// Non-Maskable Interrupt Source Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT32 GlobalSystemInterrupt;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
} EFI_ACPI_6_1_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
///
/// Local APIC NMI Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorUid;
- UINT16 Flags;
- UINT8 LocalApicLint;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
} EFI_ACPI_6_1_LOCAL_APIC_NMI_STRUCTURE;
///
/// Local APIC Address Override Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT64 LocalApicAddress;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
} EFI_ACPI_6_1_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
///
/// IO SAPIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 GlobalSystemInterruptBase;
- UINT64 IoSapicAddress;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
} EFI_ACPI_6_1_IO_SAPIC_STRUCTURE;
///
@@ -433,169 +433,169 @@ typedef struct {
/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT8 LocalSapicId;
- UINT8 LocalSapicEid;
- UINT8 Reserved[3];
- UINT32 Flags;
- UINT32 ACPIProcessorUIDValue;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
} EFI_ACPI_6_1_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
///
/// Platform Interrupt Sources Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT8 InterruptType;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT8 IoSapicVector;
- UINT32 GlobalSystemInterrupt;
- UINT32 PlatformInterruptSourceFlags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
} EFI_ACPI_6_1_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
///
/// Platform Interrupt Source Flags.
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_6_1_CPEI_PROCESSOR_OVERRIDE BIT0
+#define EFI_ACPI_6_1_CPEI_PROCESSOR_OVERRIDE BIT0
///
/// Processor Local x2APIC Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[2];
- UINT32 X2ApicId;
- UINT32 Flags;
- UINT32 AcpiProcessorUid;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 AcpiProcessorUid;
} EFI_ACPI_6_1_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
///
/// Local x2APIC NMI Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT32 AcpiProcessorUid;
- UINT8 LocalX2ApicLint;
- UINT8 Reserved[3];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 AcpiProcessorUid;
+ UINT8 LocalX2ApicLint;
+ UINT8 Reserved[3];
} EFI_ACPI_6_1_LOCAL_X2APIC_NMI_STRUCTURE;
///
/// GIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT32 CPUInterfaceNumber;
- UINT32 AcpiProcessorUid;
- UINT32 Flags;
- UINT32 ParkingProtocolVersion;
- UINT32 PerformanceInterruptGsiv;
- UINT64 ParkedAddress;
- UINT64 PhysicalBaseAddress;
- UINT64 GICV;
- UINT64 GICH;
- UINT32 VGICMaintenanceInterrupt;
- UINT64 GICRBaseAddress;
- UINT64 MPIDR;
- UINT8 ProcessorPowerEfficiencyClass;
- UINT8 Reserved2[3];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 CPUInterfaceNumber;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ParkingProtocolVersion;
+ UINT32 PerformanceInterruptGsiv;
+ UINT64 ParkedAddress;
+ UINT64 PhysicalBaseAddress;
+ UINT64 GICV;
+ UINT64 GICH;
+ UINT32 VGICMaintenanceInterrupt;
+ UINT64 GICRBaseAddress;
+ UINT64 MPIDR;
+ UINT8 ProcessorPowerEfficiencyClass;
+ UINT8 Reserved2[3];
} EFI_ACPI_6_1_GIC_STRUCTURE;
///
/// GIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_1_GIC_ENABLED BIT0
-#define EFI_ACPI_6_1_PERFORMANCE_INTERRUPT_MODEL BIT1
-#define EFI_ACPI_6_1_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2
+#define EFI_ACPI_6_1_GIC_ENABLED BIT0
+#define EFI_ACPI_6_1_PERFORMANCE_INTERRUPT_MODEL BIT1
+#define EFI_ACPI_6_1_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2
///
/// GIC Distributor Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved1;
- UINT32 GicId;
- UINT64 PhysicalBaseAddress;
- UINT32 SystemVectorBase;
- UINT8 GicVersion;
- UINT8 Reserved2[3];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 SystemVectorBase;
+ UINT8 GicVersion;
+ UINT8 Reserved2[3];
} EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE;
///
/// GIC Version
///
-#define EFI_ACPI_6_1_GIC_V1 0x01
-#define EFI_ACPI_6_1_GIC_V2 0x02
-#define EFI_ACPI_6_1_GIC_V3 0x03
-#define EFI_ACPI_6_1_GIC_V4 0x04
+#define EFI_ACPI_6_1_GIC_V1 0x01
+#define EFI_ACPI_6_1_GIC_V2 0x02
+#define EFI_ACPI_6_1_GIC_V3 0x03
+#define EFI_ACPI_6_1_GIC_V4 0x04
///
/// GIC MSI Frame Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved1;
- UINT32 GicMsiFrameId;
- UINT64 PhysicalBaseAddress;
- UINT32 Flags;
- UINT16 SPICount;
- UINT16 SPIBase;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicMsiFrameId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Flags;
+ UINT16 SPICount;
+ UINT16 SPIBase;
} EFI_ACPI_6_1_GIC_MSI_FRAME_STRUCTURE;
///
/// GIC MSI Frame Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_1_SPI_COUNT_BASE_SELECT BIT0
+#define EFI_ACPI_6_1_SPI_COUNT_BASE_SELECT BIT0
///
/// GICR Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT64 DiscoveryRangeBaseAddress;
- UINT32 DiscoveryRangeLength;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 DiscoveryRangeBaseAddress;
+ UINT32 DiscoveryRangeLength;
} EFI_ACPI_6_1_GICR_STRUCTURE;
///
/// GIC Interrupt Translation Service Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT32 GicItsId;
- UINT64 PhysicalBaseAddress;
- UINT32 Reserved2;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 GicItsId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Reserved2;
} EFI_ACPI_6_1_GIC_ITS_STRUCTURE;
///
/// Smart Battery Description Table (SBST)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 WarningEnergyLevel;
- UINT32 LowEnergyLevel;
- UINT32 CriticalEnergyLevel;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
} EFI_ACPI_6_1_SMART_BATTERY_DESCRIPTION_TABLE;
///
/// SBST Version (as defined in ACPI 6.1 spec.)
///
-#define EFI_ACPI_6_1_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_1_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
///
/// Embedded Controller Boot Resources Table (ECDT)
@@ -603,11 +603,11 @@ typedef struct {
/// a fully qualified reference to the name space object.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE EcControl;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE EcData;
- UINT32 Uid;
- UINT8 GpeBit;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
} EFI_ACPI_6_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
///
@@ -620,9 +620,9 @@ typedef struct {
/// must be defined in a platform specific manner.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Reserved1; ///< Must be set to 1
- UINT64 Reserved2;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; ///< Must be set to 1
+ UINT64 Reserved2;
} EFI_ACPI_6_1_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
///
@@ -644,83 +644,83 @@ typedef struct {
/// Processor Local APIC/SAPIC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 ProximityDomain7To0;
- UINT8 ApicId;
- UINT32 Flags;
- UINT8 LocalSapicEid;
- UINT8 ProximityDomain31To8[3];
- UINT32 ClockDomain;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT32 ClockDomain;
} EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
///
/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+#define EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
///
/// Memory Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 ProximityDomain;
- UINT16 Reserved1;
- UINT32 AddressBaseLow;
- UINT32 AddressBaseHigh;
- UINT32 LengthLow;
- UINT32 LengthHigh;
- UINT32 Reserved2;
- UINT32 Flags;
- UINT64 Reserved3;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
} EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE;
//
// Memory Flags. All other bits are reserved and must be 0.
//
-#define EFI_ACPI_6_1_MEMORY_ENABLED (1 << 0)
-#define EFI_ACPI_6_1_MEMORY_HOT_PLUGGABLE (1 << 1)
-#define EFI_ACPI_6_1_MEMORY_NONVOLATILE (1 << 2)
+#define EFI_ACPI_6_1_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_6_1_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_6_1_MEMORY_NONVOLATILE (1 << 2)
///
/// Processor Local x2APIC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved1[2];
- UINT32 ProximityDomain;
- UINT32 X2ApicId;
- UINT32 Flags;
- UINT32 ClockDomain;
- UINT8 Reserved2[4];
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1[2];
+ UINT32 ProximityDomain;
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+ UINT8 Reserved2[4];
} EFI_ACPI_6_1_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
///
/// GICC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 ProximityDomain;
- UINT32 AcpiProcessorUid;
- UINT32 Flags;
- UINT32 ClockDomain;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ClockDomain;
} EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE;
///
/// GICC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_1_GICC_ENABLED (1 << 0)
+#define EFI_ACPI_6_1_GICC_ENABLED (1 << 0)
///
/// System Locality Distance Information Table (SLIT).
/// The rest of the table is a matrix.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 NumberOfSystemLocalities;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
} EFI_ACPI_6_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
///
@@ -732,14 +732,14 @@ typedef struct {
/// Corrected Platform Error Polling Table (CPEP)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 Reserved[8];
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[8];
} EFI_ACPI_6_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
///
/// CPEP Version (as defined in ACPI 6.1 spec.)
///
-#define EFI_ACPI_6_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+#define EFI_ACPI_6_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
//
// CPEP processor structure types.
@@ -750,66 +750,66 @@ typedef struct {
/// Corrected Platform Error Polling Processor Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT32 PollingInterval;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT32 PollingInterval;
} EFI_ACPI_6_1_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
///
/// Maximum System Characteristics Table (MSCT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 OffsetProxDomInfo;
- UINT32 MaximumNumberOfProximityDomains;
- UINT32 MaximumNumberOfClockDomains;
- UINT64 MaximumPhysicalAddress;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 OffsetProxDomInfo;
+ UINT32 MaximumNumberOfProximityDomains;
+ UINT32 MaximumNumberOfClockDomains;
+ UINT64 MaximumPhysicalAddress;
} EFI_ACPI_6_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
///
/// MSCT Version (as defined in ACPI 6.1 spec.)
///
-#define EFI_ACPI_6_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+#define EFI_ACPI_6_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
///
/// Maximum Proximity Domain Information Structure Definition
///
typedef struct {
- UINT8 Revision;
- UINT8 Length;
- UINT32 ProximityDomainRangeLow;
- UINT32 ProximityDomainRangeHigh;
- UINT32 MaximumProcessorCapacity;
- UINT64 MaximumMemoryCapacity;
+ UINT8 Revision;
+ UINT8 Length;
+ UINT32 ProximityDomainRangeLow;
+ UINT32 ProximityDomainRangeHigh;
+ UINT32 MaximumProcessorCapacity;
+ UINT64 MaximumMemoryCapacity;
} EFI_ACPI_6_1_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
///
/// ACPI RAS Feature Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 PlatformCommunicationChannelIdentifier[12];
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier[12];
} EFI_ACPI_6_1_RAS_FEATURE_TABLE;
///
/// RASF Version (as defined in ACPI 6.1 spec.)
///
-#define EFI_ACPI_6_1_RAS_FEATURE_TABLE_REVISION 0x01
+#define EFI_ACPI_6_1_RAS_FEATURE_TABLE_REVISION 0x01
///
/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
///
typedef struct {
- UINT32 Signature;
- UINT16 Command;
- UINT16 Status;
- UINT16 Version;
- UINT8 RASCapabilities[16];
- UINT8 SetRASCapabilities[16];
- UINT16 NumberOfRASFParameterBlocks;
- UINT32 SetRASCapabilitiesStatus;
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT16 Version;
+ UINT8 RASCapabilities[16];
+ UINT8 SetRASCapabilities[16];
+ UINT16 NumberOfRASFParameterBlocks;
+ UINT32 SetRASCapabilitiesStatus;
} EFI_ACPI_6_1_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
///
@@ -827,52 +827,52 @@ typedef struct {
/// ACPI RASF Parameter Block structure for PATROL_SCRUB
///
typedef struct {
- UINT16 Type;
- UINT16 Version;
- UINT16 Length;
- UINT16 PatrolScrubCommand;
- UINT64 RequestedAddressRange[2];
- UINT64 ActualAddressRange[2];
- UINT16 Flags;
- UINT8 RequestedSpeed;
+ UINT16 Type;
+ UINT16 Version;
+ UINT16 Length;
+ UINT16 PatrolScrubCommand;
+ UINT64 RequestedAddressRange[2];
+ UINT64 ActualAddressRange[2];
+ UINT16 Flags;
+ UINT8 RequestedSpeed;
} EFI_ACPI_6_1_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
///
/// ACPI RASF Patrol Scrub command
///
-#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
-#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
-#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
+#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
+#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
+#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
///
/// Memory Power State Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 PlatformCommunicationChannelIdentifier;
- UINT8 Reserved[3];
-// Memory Power Node Structure
-// Memory Power State Characteristics
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier;
+ UINT8 Reserved[3];
+ // Memory Power Node Structure
+ // Memory Power State Characteristics
} EFI_ACPI_6_1_MEMORY_POWER_STATUS_TABLE;
///
/// MPST Version (as defined in ACPI 6.1 spec.)
///
-#define EFI_ACPI_6_1_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+#define EFI_ACPI_6_1_MEMORY_POWER_STATE_TABLE_REVISION 0x01
///
/// MPST Platform Communication Channel Shared Memory Region definition.
///
typedef struct {
- UINT32 Signature;
- UINT16 Command;
- UINT16 Status;
- UINT32 MemoryPowerCommandRegister;
- UINT32 MemoryPowerStatusRegister;
- UINT32 PowerStateId;
- UINT32 MemoryPowerNodeId;
- UINT64 MemoryEnergyConsumed;
- UINT64 ExpectedAveragePowerComsuned;
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT32 MemoryPowerCommandRegister;
+ UINT32 MemoryPowerStatusRegister;
+ UINT32 PowerStateId;
+ UINT32 MemoryPowerNodeId;
+ UINT64 MemoryEnergyConsumed;
+ UINT64 ExpectedAveragePowerComsuned;
} EFI_ACPI_6_1_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
///
@@ -883,186 +883,186 @@ typedef struct {
///
/// ACPI MPST Memory Power command
///
-#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
-#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
-#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
-#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
///
/// MPST Memory Power Node Table
///
typedef struct {
- UINT8 PowerStateValue;
- UINT8 PowerStateInformationIndex;
+ UINT8 PowerStateValue;
+ UINT8 PowerStateInformationIndex;
} EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE;
typedef struct {
- UINT8 Flag;
- UINT8 Reserved;
- UINT16 MemoryPowerNodeId;
- UINT32 Length;
- UINT64 AddressBase;
- UINT64 AddressLength;
- UINT32 NumberOfPowerStates;
- UINT32 NumberOfPhysicalComponents;
-//EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
-//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+ UINT8 Flag;
+ UINT8 Reserved;
+ UINT16 MemoryPowerNodeId;
+ UINT32 Length;
+ UINT64 AddressBase;
+ UINT64 AddressLength;
+ UINT32 NumberOfPowerStates;
+ UINT32 NumberOfPhysicalComponents;
+ // EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
} EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE;
-#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
-#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
-#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
typedef struct {
- UINT16 MemoryPowerNodeCount;
- UINT8 Reserved[2];
+ UINT16 MemoryPowerNodeCount;
+ UINT8 Reserved[2];
} EFI_ACPI_6_1_MPST_MEMORY_POWER_NODE_TABLE;
///
/// MPST Memory Power State Characteristics Table
///
typedef struct {
- UINT8 PowerStateStructureID;
- UINT8 Flag;
- UINT16 Reserved;
- UINT32 AveragePowerConsumedInMPS0;
- UINT32 RelativePowerSavingToMPS0;
- UINT64 ExitLatencyToMPS0;
+ UINT8 PowerStateStructureID;
+ UINT8 Flag;
+ UINT16 Reserved;
+ UINT32 AveragePowerConsumedInMPS0;
+ UINT32 RelativePowerSavingToMPS0;
+ UINT64 ExitLatencyToMPS0;
} EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
-#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
-#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
-#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
typedef struct {
- UINT16 MemoryPowerStateCharacteristicsCount;
- UINT8 Reserved[2];
+ UINT16 MemoryPowerStateCharacteristicsCount;
+ UINT8 Reserved[2];
} EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
///
/// Memory Topology Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
} EFI_ACPI_6_1_MEMORY_TOPOLOGY_TABLE;
///
/// PMTT Version (as defined in ACPI 6.1 spec.)
///
-#define EFI_ACPI_6_1_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
+#define EFI_ACPI_6_1_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
///
/// Common Memory Aggregator Device Structure.
///
typedef struct {
- UINT8 Type;
- UINT8 Reserved;
- UINT16 Length;
- UINT16 Flags;
- UINT16 Reserved1;
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16 Length;
+ UINT16 Flags;
+ UINT16 Reserved1;
} EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// Memory Aggregator Device Type
///
-#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0
-#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
-#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2
+#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0
+#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
+#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2
///
/// Socket Memory Aggregator Device Structure.
///
typedef struct {
- EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
- UINT16 SocketIdentifier;
- UINT16 Reserved;
-//EFI_ACPI_6_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];
+ EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 SocketIdentifier;
+ UINT16 Reserved;
+ // EFI_ACPI_6_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];
} EFI_ACPI_6_1_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// MemoryController Memory Aggregator Device Structure.
///
typedef struct {
- EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
- UINT32 ReadLatency;
- UINT32 WriteLatency;
- UINT32 ReadBandwidth;
- UINT32 WriteBandwidth;
- UINT16 OptimalAccessUnit;
- UINT16 OptimalAccessAlignment;
- UINT16 Reserved;
- UINT16 NumberOfProximityDomains;
-//UINT32 ProximityDomain[NumberOfProximityDomains];
-//EFI_ACPI_6_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];
+ EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT32 ReadLatency;
+ UINT32 WriteLatency;
+ UINT32 ReadBandwidth;
+ UINT32 WriteBandwidth;
+ UINT16 OptimalAccessUnit;
+ UINT16 OptimalAccessAlignment;
+ UINT16 Reserved;
+ UINT16 NumberOfProximityDomains;
+ // UINT32 ProximityDomain[NumberOfProximityDomains];
+ // EFI_ACPI_6_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];
} EFI_ACPI_6_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// DIMM Memory Aggregator Device Structure.
///
typedef struct {
- EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
- UINT16 PhysicalComponentIdentifier;
- UINT16 Reserved;
- UINT32 SizeOfDimm;
- UINT32 SmbiosHandle;
+ EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 PhysicalComponentIdentifier;
+ UINT16 Reserved;
+ UINT32 SizeOfDimm;
+ UINT32 SmbiosHandle;
} EFI_ACPI_6_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// Boot Graphics Resource Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
///
/// 2-bytes (16 bit) version ID. This value must be 1.
///
- UINT16 Version;
+ UINT16 Version;
///
/// 1-byte status field indicating current status about the table.
/// Bits[7:1] = Reserved (must be zero)
/// Bit [0] = Valid. A one indicates the boot image graphic is valid.
///
- UINT8 Status;
+ UINT8 Status;
///
/// 1-byte enumerated type field indicating format of the image.
/// 0 = Bitmap
/// 1 - 255 Reserved (for future use)
///
- UINT8 ImageType;
+ UINT8 ImageType;
///
/// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
/// of the image bitmap.
///
- UINT64 ImageAddress;
+ UINT64 ImageAddress;
///
/// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
/// (X, Y) display offset of the top left corner of the boot image.
/// The top left corner of the display is at offset (0, 0).
///
- UINT32 ImageOffsetX;
+ UINT32 ImageOffsetX;
///
/// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
/// (X, Y) display offset of the top left corner of the boot image.
/// The top left corner of the display is at offset (0, 0).
///
- UINT32 ImageOffsetY;
+ UINT32 ImageOffsetY;
} EFI_ACPI_6_1_BOOT_GRAPHICS_RESOURCE_TABLE;
///
/// BGRT Revision
///
-#define EFI_ACPI_6_1_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+#define EFI_ACPI_6_1_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
///
/// BGRT Version
///
-#define EFI_ACPI_6_1_BGRT_VERSION 0x01
+#define EFI_ACPI_6_1_BGRT_VERSION 0x01
///
/// BGRT Status
///
-#define EFI_ACPI_6_1_BGRT_STATUS_NOT_DISPLAYED 0x00
-#define EFI_ACPI_6_1_BGRT_STATUS_DISPLAYED 0x01
+#define EFI_ACPI_6_1_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_6_1_BGRT_STATUS_DISPLAYED 0x01
///
/// BGRT Image Type
@@ -1072,26 +1072,26 @@ typedef struct {
///
/// FPDT Version (as defined in ACPI 6.1 spec.)
///
-#define EFI_ACPI_6_1_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+#define EFI_ACPI_6_1_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
///
/// FPDT Performance Record Types
///
-#define EFI_ACPI_6_1_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
-#define EFI_ACPI_6_1_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
+#define EFI_ACPI_6_1_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
+#define EFI_ACPI_6_1_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
///
/// FPDT Performance Record Revision
///
-#define EFI_ACPI_6_1_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
-#define EFI_ACPI_6_1_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+#define EFI_ACPI_6_1_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
+#define EFI_ACPI_6_1_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
///
/// FPDT Runtime Performance Record Types
///
-#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
-#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
-#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
+#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
+#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
+#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
///
/// FPDT Runtime Performance Record Revision
@@ -1104,77 +1104,77 @@ typedef struct {
/// FPDT Performance Record header
///
typedef struct {
- UINT16 Type;
- UINT8 Length;
- UINT8 Revision;
+ UINT16 Type;
+ UINT8 Length;
+ UINT8 Revision;
} EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER;
///
/// FPDT Performance Table header
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
+ UINT32 Signature;
+ UINT32 Length;
} EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER;
///
/// FPDT Firmware Basic Boot Performance Pointer Record Structure
///
typedef struct {
- EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
///
/// 64-bit processor-relative physical address of the Basic Boot Performance Table.
///
- UINT64 BootPerformanceTablePointer;
+ UINT64 BootPerformanceTablePointer;
} EFI_ACPI_6_1_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
///
/// FPDT S3 Performance Table Pointer Record Structure
///
typedef struct {
- EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
///
/// 64-bit processor-relative physical address of the S3 Performance Table.
///
- UINT64 S3PerformanceTablePointer;
+ UINT64 S3PerformanceTablePointer;
} EFI_ACPI_6_1_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
///
/// FPDT Firmware Basic Boot Performance Record Structure
///
typedef struct {
- EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
///
/// Timer value logged at the beginning of firmware image execution.
/// This may not always be zero or near zero.
///
- UINT64 ResetEnd;
+ UINT64 ResetEnd;
///
/// Timer value logged just prior to loading the OS boot loader into memory.
/// For non-UEFI compatible boots, this field must be zero.
///
- UINT64 OsLoaderLoadImageStart;
+ UINT64 OsLoaderLoadImageStart;
///
/// Timer value logged just prior to launching the previously loaded OS boot loader image.
/// For non-UEFI compatible boots, the timer value logged will be just prior
/// to the INT 19h handler invocation.
///
- UINT64 OsLoaderStartImageStart;
+ UINT64 OsLoaderStartImageStart;
///
/// Timer value logged at the point when the OS loader calls the
/// ExitBootServices function for UEFI compatible firmware.
/// For non-UEFI compatible boots, this field must be zero.
///
- UINT64 ExitBootServicesEntry;
+ UINT64 ExitBootServicesEntry;
///
/// Timer value logged at the point just prior to when the OS loader gaining
/// control back from calls the ExitBootServices function for UEFI compatible firmware.
/// For non-UEFI compatible boots, this field must be zero.
///
- UINT64 ExitBootServicesExit;
+ UINT64 ExitBootServicesExit;
} EFI_ACPI_6_1_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
///
@@ -1186,7 +1186,7 @@ typedef struct {
// FPDT Firmware Basic Boot Performance Table
//
typedef struct {
- EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER Header;
//
// one or more Performance Records.
//
@@ -1201,7 +1201,7 @@ typedef struct {
// FPDT Firmware S3 Boot Performance Table
//
typedef struct {
- EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER Header;
//
// one or more Performance Records.
//
@@ -1211,145 +1211,145 @@ typedef struct {
/// FPDT Basic S3 Resume Performance Record
///
typedef struct {
- EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
///
/// A count of the number of S3 resume cycles since the last full boot sequence.
///
- UINT32 ResumeCount;
+ UINT32 ResumeCount;
///
/// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
/// OS waking vector. Only the most recent resume cycle's time is retained.
///
- UINT64 FullResume;
+ UINT64 FullResume;
///
/// Average timer value of all resume cycles logged since the last full boot
/// sequence, including the most recent resume. Note that the entire log of
/// timer values does not need to be retained in order to calculate this average.
///
- UINT64 AverageResume;
+ UINT64 AverageResume;
} EFI_ACPI_6_1_FPDT_S3_RESUME_RECORD;
///
/// FPDT Basic S3 Suspend Performance Record
///
typedef struct {
- EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
///
/// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
/// Only the most recent suspend cycle's timer value is retained.
///
- UINT64 SuspendStart;
+ UINT64 SuspendStart;
///
/// Timer value recorded at the final firmware write to SLP_TYP (or other
/// mechanism) used to trigger hardware entry to S3.
/// Only the most recent suspend cycle's timer value is retained.
///
- UINT64 SuspendEnd;
+ UINT64 SuspendEnd;
} EFI_ACPI_6_1_FPDT_S3_SUSPEND_RECORD;
///
/// Firmware Performance Record Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
} EFI_ACPI_6_1_FIRMWARE_PERFORMANCE_RECORD_TABLE;
///
/// Generic Timer Description Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 CntControlBasePhysicalAddress;
- UINT32 Reserved;
- UINT32 SecurePL1TimerGSIV;
- UINT32 SecurePL1TimerFlags;
- UINT32 NonSecurePL1TimerGSIV;
- UINT32 NonSecurePL1TimerFlags;
- UINT32 VirtualTimerGSIV;
- UINT32 VirtualTimerFlags;
- UINT32 NonSecurePL2TimerGSIV;
- UINT32 NonSecurePL2TimerFlags;
- UINT64 CntReadBasePhysicalAddress;
- UINT32 PlatformTimerCount;
- UINT32 PlatformTimerOffset;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 CntControlBasePhysicalAddress;
+ UINT32 Reserved;
+ UINT32 SecurePL1TimerGSIV;
+ UINT32 SecurePL1TimerFlags;
+ UINT32 NonSecurePL1TimerGSIV;
+ UINT32 NonSecurePL1TimerFlags;
+ UINT32 VirtualTimerGSIV;
+ UINT32 VirtualTimerFlags;
+ UINT32 NonSecurePL2TimerGSIV;
+ UINT32 NonSecurePL2TimerFlags;
+ UINT64 CntReadBasePhysicalAddress;
+ UINT32 PlatformTimerCount;
+ UINT32 PlatformTimerOffset;
} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE;
///
/// GTDT Version (as defined in ACPI 6.1 spec.)
///
-#define EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02
///
/// Timer Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
-#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
-#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2
+#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2
///
/// Platform Timer Type
///
-#define EFI_ACPI_6_1_GTDT_GT_BLOCK 0
-#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG 1
+#define EFI_ACPI_6_1_GTDT_GT_BLOCK 0
+#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG 1
///
/// GT Block Structure
///
typedef struct {
- UINT8 Type;
- UINT16 Length;
- UINT8 Reserved;
- UINT64 CntCtlBase;
- UINT32 GTBlockTimerCount;
- UINT32 GTBlockTimerOffset;
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 CntCtlBase;
+ UINT32 GTBlockTimerCount;
+ UINT32 GTBlockTimerOffset;
} EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE;
///
/// GT Block Timer Structure
///
typedef struct {
- UINT8 GTFrameNumber;
- UINT8 Reserved[3];
- UINT64 CntBaseX;
- UINT64 CntEL0BaseX;
- UINT32 GTxPhysicalTimerGSIV;
- UINT32 GTxPhysicalTimerFlags;
- UINT32 GTxVirtualTimerGSIV;
- UINT32 GTxVirtualTimerFlags;
- UINT32 GTxCommonFlags;
+ UINT8 GTFrameNumber;
+ UINT8 Reserved[3];
+ UINT64 CntBaseX;
+ UINT64 CntEL0BaseX;
+ UINT32 GTxPhysicalTimerGSIV;
+ UINT32 GTxPhysicalTimerFlags;
+ UINT32 GTxVirtualTimerGSIV;
+ UINT32 GTxVirtualTimerFlags;
+ UINT32 GTxCommonFlags;
} EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE;
///
/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
-#define EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
///
/// Common Flags Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0
-#define EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1
+#define EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0
+#define EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1
///
/// SBSA Generic Watchdog Structure
///
typedef struct {
- UINT8 Type;
- UINT16 Length;
- UINT8 Reserved;
- UINT64 RefreshFramePhysicalAddress;
- UINT64 WatchdogControlFramePhysicalAddress;
- UINT32 WatchdogTimerGSIV;
- UINT32 WatchdogTimerFlags;
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 RefreshFramePhysicalAddress;
+ UINT64 WatchdogControlFramePhysicalAddress;
+ UINT32 WatchdogTimerGSIV;
+ UINT32 WatchdogTimerFlags;
} EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;
///
/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0
-#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1
-#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2
+#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2
//
// NVDIMM Firmware Interface Table definition.
@@ -1362,63 +1362,63 @@ typedef struct {
//
// NFIT Version (as defined in ACPI 6.1 spec.)
//
-#define EFI_ACPI_6_1_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
+#define EFI_ACPI_6_1_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
//
// Definition for NFIT Table Structure Types
//
-#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0
-#define EFI_ACPI_6_1_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1
-#define EFI_ACPI_6_1_NFIT_INTERLEAVE_STRUCTURE_TYPE 2
-#define EFI_ACPI_6_1_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3
-#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4
-#define EFI_ACPI_6_1_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5
-#define EFI_ACPI_6_1_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6
+#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0
+#define EFI_ACPI_6_1_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1
+#define EFI_ACPI_6_1_NFIT_INTERLEAVE_STRUCTURE_TYPE 2
+#define EFI_ACPI_6_1_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3
+#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4
+#define EFI_ACPI_6_1_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5
+#define EFI_ACPI_6_1_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6
//
// Definition for NFIT Structure Header
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
+ UINT16 Type;
+ UINT16 Length;
} EFI_ACPI_6_1_NFIT_STRUCTURE_HEADER;
//
// Definition for System Physical Address Range Structure
//
-#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0
-#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1
-#define EFI_ACPI_6_1_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
-#define EFI_ACPI_6_1_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
-#define EFI_ACPI_6_1_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
-#define EFI_ACPI_6_1_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
-#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
-#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
-#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
-#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
+#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0
+#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1
+#define EFI_ACPI_6_1_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
+#define EFI_ACPI_6_1_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
+#define EFI_ACPI_6_1_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
+#define EFI_ACPI_6_1_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
+#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
+#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
+#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
+#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT16 SPARangeStructureIndex;
- UINT16 Flags;
- UINT32 Reserved_8;
- UINT32 ProximityDomain;
- GUID AddressRangeTypeGUID;
- UINT64 SystemPhysicalAddressRangeBase;
- UINT64 SystemPhysicalAddressRangeLength;
- UINT64 AddressRangeMemoryMappingAttribute;
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 SPARangeStructureIndex;
+ UINT16 Flags;
+ UINT32 Reserved_8;
+ UINT32 ProximityDomain;
+ GUID AddressRangeTypeGUID;
+ UINT64 SystemPhysicalAddressRangeBase;
+ UINT64 SystemPhysicalAddressRangeLength;
+ UINT64 AddressRangeMemoryMappingAttribute;
} EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;
//
// Definition for Memory Device to System Physical Address Range Mapping Structure
//
typedef struct {
- UINT32 DIMMNumber:4;
- UINT32 MemoryChannelNumber:4;
- UINT32 MemoryControllerID:4;
- UINT32 SocketID:4;
- UINT32 NodeControllerID:12;
- UINT32 Reserved_28:4;
+ UINT32 DIMMNumber : 4;
+ UINT32 MemoryChannelNumber : 4;
+ UINT32 MemoryControllerID : 4;
+ UINT32 SocketID : 4;
+ UINT32 NodeControllerID : 12;
+ UINT32 Reserved_28 : 4;
} EFI_ACPI_6_1_NFIT_DEVICE_HANDLE;
#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0
@@ -1429,161 +1429,167 @@ typedef struct {
#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5
#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6
typedef struct {
- UINT16 Type;
- UINT16 Length;
- EFI_ACPI_6_1_NFIT_DEVICE_HANDLE NFITDeviceHandle;
- UINT16 NVDIMMPhysicalID;
- UINT16 NVDIMMRegionID;
- UINT16 SPARangeStructureIndex ;
- UINT16 NVDIMMControlRegionStructureIndex;
- UINT64 NVDIMMRegionSize;
- UINT64 RegionOffset;
- UINT64 NVDIMMPhysicalAddressRegionBase;
- UINT16 InterleaveStructureIndex;
- UINT16 InterleaveWays;
- UINT16 NVDIMMStateFlags;
- UINT16 Reserved_46;
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_1_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NVDIMMPhysicalID;
+ UINT16 NVDIMMRegionID;
+ UINT16 SPARangeStructureIndex;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT64 NVDIMMRegionSize;
+ UINT64 RegionOffset;
+ UINT64 NVDIMMPhysicalAddressRegionBase;
+ UINT16 InterleaveStructureIndex;
+ UINT16 InterleaveWays;
+ UINT16 NVDIMMStateFlags;
+ UINT16 Reserved_46;
} EFI_ACPI_6_1_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;
//
// Definition for Interleave Structure
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT16 InterleaveStructureIndex;
- UINT16 Reserved_6;
- UINT32 NumberOfLines;
- UINT32 LineSize;
-//UINT32 LineOffset[NumberOfLines];
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 InterleaveStructureIndex;
+ UINT16 Reserved_6;
+ UINT32 NumberOfLines;
+ UINT32 LineSize;
+ // UINT32 LineOffset[NumberOfLines];
} EFI_ACPI_6_1_NFIT_INTERLEAVE_STRUCTURE;
//
// Definition for SMBIOS Management Information Structure
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT32 Reserved_4;
-//UINT8 Data[];
+ UINT16 Type;
+ UINT16 Length;
+ UINT32 Reserved_4;
+ // UINT8 Data[];
} EFI_ACPI_6_1_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;
//
// Definition for NVDIMM Control Region Structure
//
-#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0
+#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0
-#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0
+#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT16 NVDIMMControlRegionStructureIndex;
- UINT16 VendorID;
- UINT16 DeviceID;
- UINT16 RevisionID;
- UINT16 SubsystemVendorID;
- UINT16 SubsystemDeviceID;
- UINT16 SubsystemRevisionID;
- UINT8 ValidFields;
- UINT8 ManufacturingLocation;
- UINT16 ManufacturingDate;
- UINT8 Reserved_22[2];
- UINT32 SerialNumber;
- UINT16 RegionFormatInterfaceCode;
- UINT16 NumberOfBlockControlWindows;
- UINT64 SizeOfBlockControlWindow;
- UINT64 CommandRegisterOffsetInBlockControlWindow;
- UINT64 SizeOfCommandRegisterInBlockControlWindows;
- UINT64 StatusRegisterOffsetInBlockControlWindow;
- UINT64 SizeOfStatusRegisterInBlockControlWindows;
- UINT16 NVDIMMControlRegionFlag;
- UINT8 Reserved_74[6];
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT8 ValidFields;
+ UINT8 ManufacturingLocation;
+ UINT16 ManufacturingDate;
+ UINT8 Reserved_22[2];
+ UINT32 SerialNumber;
+ UINT16 RegionFormatInterfaceCode;
+ UINT16 NumberOfBlockControlWindows;
+ UINT64 SizeOfBlockControlWindow;
+ UINT64 CommandRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfCommandRegisterInBlockControlWindows;
+ UINT64 StatusRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfStatusRegisterInBlockControlWindows;
+ UINT16 NVDIMMControlRegionFlag;
+ UINT8 Reserved_74[6];
} EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;
//
// Definition for NVDIMM Block Data Window Region Structure
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT16 NVDIMMControlRegionStructureIndex;
- UINT16 NumberOfBlockDataWindows;
- UINT64 BlockDataWindowStartOffset;
- UINT64 SizeOfBlockDataWindow;
- UINT64 BlockAccessibleMemoryCapacity;
- UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 NumberOfBlockDataWindows;
+ UINT64 BlockDataWindowStartOffset;
+ UINT64 SizeOfBlockDataWindow;
+ UINT64 BlockAccessibleMemoryCapacity;
+ UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;
} EFI_ACPI_6_1_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;
//
// Definition for Flush Hint Address Structure
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
- EFI_ACPI_6_1_NFIT_DEVICE_HANDLE NFITDeviceHandle;
- UINT16 NumberOfFlushHintAddresses;
- UINT8 Reserved_10[6];
-//UINT64 FlushHintAddress[NumberOfFlushHintAddresses];
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_1_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NumberOfFlushHintAddresses;
+ UINT8 Reserved_10[6];
+ // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];
} EFI_ACPI_6_1_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;
///
/// Boot Error Record Table (BERT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 BootErrorRegionLength;
- UINT64 BootErrorRegion;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 BootErrorRegionLength;
+ UINT64 BootErrorRegion;
} EFI_ACPI_6_1_BOOT_ERROR_RECORD_TABLE_HEADER;
///
/// BERT Version (as defined in ACPI 6.1 spec.)
///
-#define EFI_ACPI_6_1_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+#define EFI_ACPI_6_1_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
///
/// Boot Error Region Block Status Definition
///
typedef struct {
- UINT32 UncorrectableErrorValid:1;
- UINT32 CorrectableErrorValid:1;
- UINT32 MultipleUncorrectableErrors:1;
- UINT32 MultipleCorrectableErrors:1;
- UINT32 ErrorDataEntryCount:10;
- UINT32 Reserved:18;
+ UINT32 UncorrectableErrorValid : 1;
+ UINT32 CorrectableErrorValid : 1;
+ UINT32 MultipleUncorrectableErrors : 1;
+ UINT32 MultipleCorrectableErrors : 1;
+ UINT32 ErrorDataEntryCount : 10;
+ UINT32 Reserved : 18;
} EFI_ACPI_6_1_ERROR_BLOCK_STATUS;
///
/// Boot Error Region Definition
///
typedef struct {
- EFI_ACPI_6_1_ERROR_BLOCK_STATUS BlockStatus;
- UINT32 RawDataOffset;
- UINT32 RawDataLength;
- UINT32 DataLength;
- UINT32 ErrorSeverity;
+ EFI_ACPI_6_1_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
} EFI_ACPI_6_1_BOOT_ERROR_REGION_STRUCTURE;
//
// Boot Error Severity types
//
-#define EFI_ACPI_6_1_ERROR_SEVERITY_CORRECTABLE 0x00
+#define EFI_ACPI_6_1_ERROR_SEVERITY_RECOVERABLE 0x00
#define EFI_ACPI_6_1_ERROR_SEVERITY_FATAL 0x01
#define EFI_ACPI_6_1_ERROR_SEVERITY_CORRECTED 0x02
#define EFI_ACPI_6_1_ERROR_SEVERITY_NONE 0x03
+//
+// The term 'Correctable' is no longer being used as an error severity of the
+// reported error since ACPI Specification Version 5.1 Errata B.
+// The below macro is considered as deprecated and should no longer be used.
+//
+#define EFI_ACPI_6_1_ERROR_SEVERITY_CORRECTABLE 0x00
///
/// Generic Error Data Entry Definition
///
typedef struct {
- UINT8 SectionType[16];
- UINT32 ErrorSeverity;
- UINT16 Revision;
- UINT8 ValidationBits;
- UINT8 Flags;
- UINT32 ErrorDataLength;
- UINT8 FruId[16];
- UINT8 FruText[20];
- UINT8 Timestamp[8];
+ UINT8 SectionType[16];
+ UINT32 ErrorSeverity;
+ UINT16 Revision;
+ UINT8 ValidationBits;
+ UINT8 Flags;
+ UINT32 ErrorDataLength;
+ UINT8 FruId[16];
+ UINT8 FruText[20];
+ UINT8 Timestamp[8];
} EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
///
@@ -1595,14 +1601,14 @@ typedef struct {
/// HEST - Hardware Error Source Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 ErrorSourceCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 ErrorSourceCount;
} EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
///
/// HEST Version (as defined in ACPI 6.1 spec.)
///
-#define EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+#define EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
//
// Error Source structure types.
@@ -1619,461 +1625,461 @@ typedef struct {
//
// Error Source structure flags.
//
-#define EFI_ACPI_6_1_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
-#define EFI_ACPI_6_1_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
+#define EFI_ACPI_6_1_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
+#define EFI_ACPI_6_1_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
///
/// IA-32 Architecture Machine Check Exception Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT64 GlobalCapabilityInitData;
- UINT64 GlobalControlInitData;
- UINT8 NumberOfHardwareBanks;
- UINT8 Reserved1[7];
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT64 GlobalCapabilityInitData;
+ UINT64 GlobalControlInitData;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[7];
} EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
///
/// IA-32 Architecture Machine Check Bank Structure Definition
///
typedef struct {
- UINT8 BankNumber;
- UINT8 ClearStatusOnInitialization;
- UINT8 StatusDataFormat;
- UINT8 Reserved0;
- UINT32 ControlRegisterMsrAddress;
- UINT64 ControlInitData;
- UINT32 StatusRegisterMsrAddress;
- UINT32 AddressRegisterMsrAddress;
- UINT32 MiscRegisterMsrAddress;
+ UINT8 BankNumber;
+ UINT8 ClearStatusOnInitialization;
+ UINT8 StatusDataFormat;
+ UINT8 Reserved0;
+ UINT32 ControlRegisterMsrAddress;
+ UINT64 ControlInitData;
+ UINT32 StatusRegisterMsrAddress;
+ UINT32 AddressRegisterMsrAddress;
+ UINT32 MiscRegisterMsrAddress;
} EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
///
/// IA-32 Architecture Machine Check Bank Structure MCA data format
///
-#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
-#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
-#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
+#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
+#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
+#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
//
// Hardware Error Notification types. All other values are reserved
//
-#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
-#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
-#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
-#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
-#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
-#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05
-#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_MCE 0x06
-#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07
-#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08
-#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09
-#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_MCE 0x06
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A
///
/// Hardware Error Notification Configuration Write Enable Structure Definition
///
typedef struct {
- UINT16 Type:1;
- UINT16 PollInterval:1;
- UINT16 SwitchToPollingThresholdValue:1;
- UINT16 SwitchToPollingThresholdWindow:1;
- UINT16 ErrorThresholdValue:1;
- UINT16 ErrorThresholdWindow:1;
- UINT16 Reserved:10;
+ UINT16 Type : 1;
+ UINT16 PollInterval : 1;
+ UINT16 SwitchToPollingThresholdValue : 1;
+ UINT16 SwitchToPollingThresholdWindow : 1;
+ UINT16 ErrorThresholdValue : 1;
+ UINT16 ErrorThresholdWindow : 1;
+ UINT16 Reserved : 10;
} EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
///
/// Hardware Error Notification Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
- UINT32 PollInterval;
- UINT32 Vector;
- UINT32 SwitchToPollingThresholdValue;
- UINT32 SwitchToPollingThresholdWindow;
- UINT32 ErrorThresholdValue;
- UINT32 ErrorThresholdWindow;
+ UINT8 Type;
+ UINT8 Length;
+ EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
+ UINT32 PollInterval;
+ UINT32 Vector;
+ UINT32 SwitchToPollingThresholdValue;
+ UINT32 SwitchToPollingThresholdWindow;
+ UINT32 ErrorThresholdValue;
+ UINT32 ErrorThresholdWindow;
} EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
///
/// IA-32 Architecture Corrected Machine Check Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
- UINT8 NumberOfHardwareBanks;
- UINT8 Reserved1[3];
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
} EFI_ACPI_6_1_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
///
/// IA-32 Architecture NMI Error Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 MaxRawDataLength;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
} EFI_ACPI_6_1_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
///
/// PCI Express Root Port AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
- UINT32 RootErrorCommand;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 RootErrorCommand;
} EFI_ACPI_6_1_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
///
/// PCI Express Device AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
} EFI_ACPI_6_1_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
///
/// PCI Express Bridge AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
- UINT32 SecondaryUncorrectableErrorMask;
- UINT32 SecondaryUncorrectableErrorSeverity;
- UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 SecondaryUncorrectableErrorMask;
+ UINT32 SecondaryUncorrectableErrorSeverity;
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
} EFI_ACPI_6_1_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
///
/// Generic Hardware Error Source Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT16 RelatedSourceId;
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 MaxRawDataLength;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
- EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
- UINT32 ErrorStatusBlockLength;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
} EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
///
/// Generic Hardware Error Source Version 2 Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT16 RelatedSourceId;
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 MaxRawDataLength;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
- EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
- UINT32 ErrorStatusBlockLength;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;
- UINT64 ReadAckPreserve;
- UINT64 ReadAckWrite;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;
+ UINT64 ReadAckPreserve;
+ UINT64 ReadAckWrite;
} EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;
///
/// Generic Error Status Definition
///
typedef struct {
- EFI_ACPI_6_1_ERROR_BLOCK_STATUS BlockStatus;
- UINT32 RawDataOffset;
- UINT32 RawDataLength;
- UINT32 DataLength;
- UINT32 ErrorSeverity;
+ EFI_ACPI_6_1_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
} EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE;
///
/// ERST - Error Record Serialization Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 SerializationHeaderSize;
- UINT8 Reserved0[4];
- UINT32 InstructionEntryCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 SerializationHeaderSize;
+ UINT8 Reserved0[4];
+ UINT32 InstructionEntryCount;
} EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
///
/// ERST Version (as defined in ACPI 6.1 spec.)
///
-#define EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
///
/// ERST Serialization Actions
///
-#define EFI_ACPI_6_1_ERST_BEGIN_WRITE_OPERATION 0x00
-#define EFI_ACPI_6_1_ERST_BEGIN_READ_OPERATION 0x01
-#define EFI_ACPI_6_1_ERST_BEGIN_CLEAR_OPERATION 0x02
-#define EFI_ACPI_6_1_ERST_END_OPERATION 0x03
-#define EFI_ACPI_6_1_ERST_SET_RECORD_OFFSET 0x04
-#define EFI_ACPI_6_1_ERST_EXECUTE_OPERATION 0x05
-#define EFI_ACPI_6_1_ERST_CHECK_BUSY_STATUS 0x06
-#define EFI_ACPI_6_1_ERST_GET_COMMAND_STATUS 0x07
-#define EFI_ACPI_6_1_ERST_GET_RECORD_IDENTIFIER 0x08
-#define EFI_ACPI_6_1_ERST_SET_RECORD_IDENTIFIER 0x09
-#define EFI_ACPI_6_1_ERST_GET_RECORD_COUNT 0x0A
-#define EFI_ACPI_6_1_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
-#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
-#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
-#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
-#define EFI_ACPI_6_1_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10
+#define EFI_ACPI_6_1_ERST_BEGIN_WRITE_OPERATION 0x00
+#define EFI_ACPI_6_1_ERST_BEGIN_READ_OPERATION 0x01
+#define EFI_ACPI_6_1_ERST_BEGIN_CLEAR_OPERATION 0x02
+#define EFI_ACPI_6_1_ERST_END_OPERATION 0x03
+#define EFI_ACPI_6_1_ERST_SET_RECORD_OFFSET 0x04
+#define EFI_ACPI_6_1_ERST_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_1_ERST_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_1_ERST_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_1_ERST_GET_RECORD_IDENTIFIER 0x08
+#define EFI_ACPI_6_1_ERST_SET_RECORD_IDENTIFIER 0x09
+#define EFI_ACPI_6_1_ERST_GET_RECORD_COUNT 0x0A
+#define EFI_ACPI_6_1_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
+#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
+#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
+#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
+#define EFI_ACPI_6_1_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10
///
/// ERST Action Command Status
///
-#define EFI_ACPI_6_1_ERST_STATUS_SUCCESS 0x00
-#define EFI_ACPI_6_1_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
-#define EFI_ACPI_6_1_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
-#define EFI_ACPI_6_1_ERST_STATUS_FAILED 0x03
-#define EFI_ACPI_6_1_ERST_STATUS_RECORD_STORE_EMPTY 0x04
-#define EFI_ACPI_6_1_ERST_STATUS_RECORD_NOT_FOUND 0x05
+#define EFI_ACPI_6_1_ERST_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_1_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
+#define EFI_ACPI_6_1_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
+#define EFI_ACPI_6_1_ERST_STATUS_FAILED 0x03
+#define EFI_ACPI_6_1_ERST_STATUS_RECORD_STORE_EMPTY 0x04
+#define EFI_ACPI_6_1_ERST_STATUS_RECORD_NOT_FOUND 0x05
///
/// ERST Serialization Instructions
///
-#define EFI_ACPI_6_1_ERST_READ_REGISTER 0x00
-#define EFI_ACPI_6_1_ERST_READ_REGISTER_VALUE 0x01
-#define EFI_ACPI_6_1_ERST_WRITE_REGISTER 0x02
-#define EFI_ACPI_6_1_ERST_WRITE_REGISTER_VALUE 0x03
-#define EFI_ACPI_6_1_ERST_NOOP 0x04
-#define EFI_ACPI_6_1_ERST_LOAD_VAR1 0x05
-#define EFI_ACPI_6_1_ERST_LOAD_VAR2 0x06
-#define EFI_ACPI_6_1_ERST_STORE_VAR1 0x07
-#define EFI_ACPI_6_1_ERST_ADD 0x08
-#define EFI_ACPI_6_1_ERST_SUBTRACT 0x09
-#define EFI_ACPI_6_1_ERST_ADD_VALUE 0x0A
-#define EFI_ACPI_6_1_ERST_SUBTRACT_VALUE 0x0B
-#define EFI_ACPI_6_1_ERST_STALL 0x0C
-#define EFI_ACPI_6_1_ERST_STALL_WHILE_TRUE 0x0D
-#define EFI_ACPI_6_1_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
-#define EFI_ACPI_6_1_ERST_GOTO 0x0F
-#define EFI_ACPI_6_1_ERST_SET_SRC_ADDRESS_BASE 0x10
-#define EFI_ACPI_6_1_ERST_SET_DST_ADDRESS_BASE 0x11
-#define EFI_ACPI_6_1_ERST_MOVE_DATA 0x12
+#define EFI_ACPI_6_1_ERST_READ_REGISTER 0x00
+#define EFI_ACPI_6_1_ERST_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_1_ERST_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_1_ERST_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_1_ERST_NOOP 0x04
+#define EFI_ACPI_6_1_ERST_LOAD_VAR1 0x05
+#define EFI_ACPI_6_1_ERST_LOAD_VAR2 0x06
+#define EFI_ACPI_6_1_ERST_STORE_VAR1 0x07
+#define EFI_ACPI_6_1_ERST_ADD 0x08
+#define EFI_ACPI_6_1_ERST_SUBTRACT 0x09
+#define EFI_ACPI_6_1_ERST_ADD_VALUE 0x0A
+#define EFI_ACPI_6_1_ERST_SUBTRACT_VALUE 0x0B
+#define EFI_ACPI_6_1_ERST_STALL 0x0C
+#define EFI_ACPI_6_1_ERST_STALL_WHILE_TRUE 0x0D
+#define EFI_ACPI_6_1_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
+#define EFI_ACPI_6_1_ERST_GOTO 0x0F
+#define EFI_ACPI_6_1_ERST_SET_SRC_ADDRESS_BASE 0x10
+#define EFI_ACPI_6_1_ERST_SET_DST_ADDRESS_BASE 0x11
+#define EFI_ACPI_6_1_ERST_MOVE_DATA 0x12
///
/// ERST Instruction Flags
///
-#define EFI_ACPI_6_1_ERST_PRESERVE_REGISTER 0x01
+#define EFI_ACPI_6_1_ERST_PRESERVE_REGISTER 0x01
///
/// ERST Serialization Instruction Entry
///
typedef struct {
- UINT8 SerializationAction;
- UINT8 Instruction;
- UINT8 Flags;
- UINT8 Reserved0;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
- UINT64 Value;
- UINT64 Mask;
+ UINT8 SerializationAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
} EFI_ACPI_6_1_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
///
/// EINJ - Error Injection Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 InjectionHeaderSize;
- UINT8 InjectionFlags;
- UINT8 Reserved0[3];
- UINT32 InjectionEntryCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 InjectionHeaderSize;
+ UINT8 InjectionFlags;
+ UINT8 Reserved0[3];
+ UINT32 InjectionEntryCount;
} EFI_ACPI_6_1_ERROR_INJECTION_TABLE_HEADER;
///
/// EINJ Version (as defined in ACPI 6.1 spec.)
///
-#define EFI_ACPI_6_1_ERROR_INJECTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_1_ERROR_INJECTION_TABLE_REVISION 0x01
///
/// EINJ Error Injection Actions
///
-#define EFI_ACPI_6_1_EINJ_BEGIN_INJECTION_OPERATION 0x00
-#define EFI_ACPI_6_1_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
-#define EFI_ACPI_6_1_EINJ_SET_ERROR_TYPE 0x02
-#define EFI_ACPI_6_1_EINJ_GET_ERROR_TYPE 0x03
-#define EFI_ACPI_6_1_EINJ_END_OPERATION 0x04
-#define EFI_ACPI_6_1_EINJ_EXECUTE_OPERATION 0x05
-#define EFI_ACPI_6_1_EINJ_CHECK_BUSY_STATUS 0x06
-#define EFI_ACPI_6_1_EINJ_GET_COMMAND_STATUS 0x07
-#define EFI_ACPI_6_1_EINJ_TRIGGER_ERROR 0xFF
+#define EFI_ACPI_6_1_EINJ_BEGIN_INJECTION_OPERATION 0x00
+#define EFI_ACPI_6_1_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
+#define EFI_ACPI_6_1_EINJ_SET_ERROR_TYPE 0x02
+#define EFI_ACPI_6_1_EINJ_GET_ERROR_TYPE 0x03
+#define EFI_ACPI_6_1_EINJ_END_OPERATION 0x04
+#define EFI_ACPI_6_1_EINJ_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_1_EINJ_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_1_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_1_EINJ_TRIGGER_ERROR 0xFF
///
/// EINJ Action Command Status
///
-#define EFI_ACPI_6_1_EINJ_STATUS_SUCCESS 0x00
-#define EFI_ACPI_6_1_EINJ_STATUS_UNKNOWN_FAILURE 0x01
-#define EFI_ACPI_6_1_EINJ_STATUS_INVALID_ACCESS 0x02
+#define EFI_ACPI_6_1_EINJ_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_1_EINJ_STATUS_UNKNOWN_FAILURE 0x01
+#define EFI_ACPI_6_1_EINJ_STATUS_INVALID_ACCESS 0x02
///
/// EINJ Error Type Definition
///
-#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
-#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
-#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
-#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
-#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
-#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
-#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
-#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
-#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
-#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
-#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
-#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
+#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
+#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
+#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
+#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
+#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
+#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
+#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
+#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
+#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
+#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
+#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
+#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
///
/// EINJ Injection Instructions
///
-#define EFI_ACPI_6_1_EINJ_READ_REGISTER 0x00
-#define EFI_ACPI_6_1_EINJ_READ_REGISTER_VALUE 0x01
-#define EFI_ACPI_6_1_EINJ_WRITE_REGISTER 0x02
-#define EFI_ACPI_6_1_EINJ_WRITE_REGISTER_VALUE 0x03
-#define EFI_ACPI_6_1_EINJ_NOOP 0x04
+#define EFI_ACPI_6_1_EINJ_READ_REGISTER 0x00
+#define EFI_ACPI_6_1_EINJ_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_1_EINJ_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_1_EINJ_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_1_EINJ_NOOP 0x04
///
/// EINJ Instruction Flags
///
-#define EFI_ACPI_6_1_EINJ_PRESERVE_REGISTER 0x01
+#define EFI_ACPI_6_1_EINJ_PRESERVE_REGISTER 0x01
///
/// EINJ Injection Instruction Entry
///
typedef struct {
- UINT8 InjectionAction;
- UINT8 Instruction;
- UINT8 Flags;
- UINT8 Reserved0;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
- UINT64 Value;
- UINT64 Mask;
+ UINT8 InjectionAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
} EFI_ACPI_6_1_EINJ_INJECTION_INSTRUCTION_ENTRY;
///
/// EINJ Trigger Action Table
///
typedef struct {
- UINT32 HeaderSize;
- UINT32 Revision;
- UINT32 TableSize;
- UINT32 EntryCount;
+ UINT32 HeaderSize;
+ UINT32 Revision;
+ UINT32 TableSize;
+ UINT32 EntryCount;
} EFI_ACPI_6_1_EINJ_TRIGGER_ACTION_TABLE;
///
/// Platform Communications Channel Table (PCCT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Flags;
- UINT64 Reserved;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Flags;
+ UINT64 Reserved;
} EFI_ACPI_6_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
///
/// PCCT Version (as defined in ACPI 6.1 spec.)
///
-#define EFI_ACPI_6_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01
+#define EFI_ACPI_6_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01
///
/// PCCT Global Flags
///
-#define EFI_ACPI_6_1_PCCT_FLAGS_SCI_DOORBELL BIT0
+#define EFI_ACPI_6_1_PCCT_FLAGS_SCI_DOORBELL BIT0
//
// PCCT Subspace type
//
-#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_GENERIC 0x00
-#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01
-#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_GENERIC 0x00
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02
///
/// PCC Subspace Structure Header
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
+ UINT8 Type;
+ UINT8 Length;
} EFI_ACPI_6_1_PCCT_SUBSPACE_HEADER;
///
/// Generic Communications Subspace Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[6];
- UINT64 BaseAddress;
- UINT64 AddressLength;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
- UINT64 DoorbellPreserve;
- UINT64 DoorbellWrite;
- UINT32 NominalLatency;
- UINT32 MaximumPeriodicAccessRate;
- UINT16 MinimumRequestTurnaroundTime;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[6];
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
} EFI_ACPI_6_1_PCCT_SUBSPACE_GENERIC;
///
@@ -2081,18 +2087,18 @@ typedef struct {
///
typedef struct {
- UINT8 Command;
- UINT8 Reserved:7;
- UINT8 GenerateSci:1;
+ UINT8 Command;
+ UINT8 Reserved : 7;
+ UINT8 GenerateSci : 1;
} EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
typedef struct {
- UINT8 CommandComplete:1;
- UINT8 SciDoorbell:1;
- UINT8 Error:1;
- UINT8 PlatformNotification:1;
- UINT8 Reserved:4;
- UINT8 Reserved1;
+ UINT8 CommandComplete : 1;
+ UINT8 SciDoorbell : 1;
+ UINT8 Error : 1;
+ UINT8 PlatformNotification : 1;
+ UINT8 Reserved : 4;
+ UINT8 Reserved1;
} EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
typedef struct {
@@ -2101,48 +2107,48 @@ typedef struct {
EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;
} EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
-#define EFI_ACPI_6_1_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_POLARITY BIT0
-#define EFI_ACPI_6_1_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_MODE BIT1
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_POLARITY BIT0
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_MODE BIT1
///
/// Type 1 HW-Reduced Communications Subspace Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 DoorbellInterrupt;
- UINT8 DoorbellInterruptFlags;
- UINT8 Reserved;
- UINT64 BaseAddress;
- UINT64 AddressLength;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
- UINT64 DoorbellPreserve;
- UINT64 DoorbellWrite;
- UINT32 NominalLatency;
- UINT32 MaximumPeriodicAccessRate;
- UINT16 MinimumRequestTurnaroundTime;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 DoorbellInterrupt;
+ UINT8 DoorbellInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
} EFI_ACPI_6_1_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
///
/// Type 2 HW-Reduced Communications Subspace Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 DoorbellInterrupt;
- UINT8 DoorbellInterruptFlags;
- UINT8 Reserved;
- UINT64 BaseAddress;
- UINT64 AddressLength;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
- UINT64 DoorbellPreserve;
- UINT64 DoorbellWrite;
- UINT32 NominalLatency;
- UINT32 MaximumPeriodicAccessRate;
- UINT16 MinimumRequestTurnaroundTime;
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellAckRegister;
- UINT64 DoorbellAckPreserve;
- UINT64 DoorbellAckWrite;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 DoorbellInterrupt;
+ UINT8 DoorbellInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellAckRegister;
+ UINT64 DoorbellAckPreserve;
+ UINT64 DoorbellAckWrite;
} EFI_ACPI_6_1_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
//
diff --git a/MdePkg/Include/IndustryStandard/Acpi62.h b/MdePkg/Include/IndustryStandard/Acpi62.h
index 319586d6..c174e6d4 100644
--- a/MdePkg/Include/IndustryStandard/Acpi62.h
+++ b/MdePkg/Include/IndustryStandard/Acpi62.h
@@ -1,7 +1,7 @@
/** @file
ACPI 6.2 definitions from the ACPI Specification Revision 6.2 May, 2017.
- Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
Copyright (c) 2020, ARM Ltd. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -14,20 +14,20 @@
//
// Large Item Descriptor Name
//
-#define ACPI_LARGE_PIN_FUNCTION_DESCRIPTOR_NAME 0x0D
-#define ACPI_LARGE_PIN_CONFIGURATION_DESCRIPTOR_NAME 0x0F
-#define ACPI_LARGE_PIN_GROUP_DESCRIPTOR_NAME 0x10
-#define ACPI_LARGE_PIN_GROUP_FUNCTION_DESCRIPTOR_NAME 0x11
-#define ACPI_LARGE_PIN_GROUP_CONFIGURATION_DESCRIPTOR_NAME 0x12
+#define ACPI_LARGE_PIN_FUNCTION_DESCRIPTOR_NAME 0x0D
+#define ACPI_LARGE_PIN_CONFIGURATION_DESCRIPTOR_NAME 0x0F
+#define ACPI_LARGE_PIN_GROUP_DESCRIPTOR_NAME 0x10
+#define ACPI_LARGE_PIN_GROUP_FUNCTION_DESCRIPTOR_NAME 0x11
+#define ACPI_LARGE_PIN_GROUP_CONFIGURATION_DESCRIPTOR_NAME 0x12
//
// Large Item Descriptor Value
//
-#define ACPI_PIN_FUNCTION_DESCRIPTOR 0x8D
-#define ACPI_PIN_CONFIGURATION_DESCRIPTOR 0x8F
-#define ACPI_PIN_GROUP_DESCRIPTOR 0x90
-#define ACPI_PIN_GROUP_FUNCTION_DESCRIPTOR 0x91
-#define ACPI_PIN_GROUP_CONFIGURATION_DESCRIPTOR 0x92
+#define ACPI_PIN_FUNCTION_DESCRIPTOR 0x8D
+#define ACPI_PIN_CONFIGURATION_DESCRIPTOR 0x8F
+#define ACPI_PIN_GROUP_DESCRIPTOR 0x90
+#define ACPI_PIN_GROUP_FUNCTION_DESCRIPTOR 0x91
+#define ACPI_PIN_GROUP_CONFIGURATION_DESCRIPTOR 0x92
#pragma pack(1)
@@ -118,21 +118,21 @@ typedef PACKED struct {
/// ACPI 6.2 Generic Address Space definition
///
typedef struct {
- UINT8 AddressSpaceId;
- UINT8 RegisterBitWidth;
- UINT8 RegisterBitOffset;
- UINT8 AccessSize;
- UINT64 Address;
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
} EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE;
//
// Generic Address Space Address IDs
//
-#define EFI_ACPI_6_2_SYSTEM_MEMORY 0
-#define EFI_ACPI_6_2_SYSTEM_IO 1
-#define EFI_ACPI_6_2_PCI_CONFIGURATION_SPACE 2
-#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER 3
-#define EFI_ACPI_6_2_SMBUS 4
+#define EFI_ACPI_6_2_SYSTEM_MEMORY 0
+#define EFI_ACPI_6_2_SYSTEM_IO 1
+#define EFI_ACPI_6_2_PCI_CONFIGURATION_SPACE 2
+#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER 3
+#define EFI_ACPI_6_2_SMBUS 4
#define EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL 0x0A
#define EFI_ACPI_6_2_FUNCTIONAL_FIXED_HARDWARE 0x7F
@@ -153,29 +153,29 @@ typedef struct {
/// Root System Description Pointer Structure
///
typedef struct {
- UINT64 Signature;
- UINT8 Checksum;
- UINT8 OemId[6];
- UINT8 Revision;
- UINT32 RsdtAddress;
- UINT32 Length;
- UINT64 XsdtAddress;
- UINT8 ExtendedChecksum;
- UINT8 Reserved[3];
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
} EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER;
///
/// RSD_PTR Revision (as defined in ACPI 6.2 spec.)
///
-#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.2) says current value is 2
+#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.2) says current value is 2
///
/// Common table header, this prefaces all ACPI tables, including FACS, but
/// excluding the RSD PTR structure
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
+ UINT32 Signature;
+ UINT32 Length;
} EFI_ACPI_6_2_COMMON_HEADER;
//
@@ -187,7 +187,7 @@ typedef struct {
///
/// RSDT Revision (as defined in ACPI 6.2 spec.)
///
-#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
//
// Extended System Description Table
@@ -198,74 +198,74 @@ typedef struct {
///
/// XSDT Revision (as defined in ACPI 6.2 spec.)
///
-#define EFI_ACPI_6_2_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_2_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
///
/// Fixed ACPI Description Table Structure (FADT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 FirmwareCtrl;
- UINT32 Dsdt;
- UINT8 Reserved0;
- UINT8 PreferredPmProfile;
- UINT16 SciInt;
- UINT32 SmiCmd;
- UINT8 AcpiEnable;
- UINT8 AcpiDisable;
- UINT8 S4BiosReq;
- UINT8 PstateCnt;
- UINT32 Pm1aEvtBlk;
- UINT32 Pm1bEvtBlk;
- UINT32 Pm1aCntBlk;
- UINT32 Pm1bCntBlk;
- UINT32 Pm2CntBlk;
- UINT32 PmTmrBlk;
- UINT32 Gpe0Blk;
- UINT32 Gpe1Blk;
- UINT8 Pm1EvtLen;
- UINT8 Pm1CntLen;
- UINT8 Pm2CntLen;
- UINT8 PmTmrLen;
- UINT8 Gpe0BlkLen;
- UINT8 Gpe1BlkLen;
- UINT8 Gpe1Base;
- UINT8 CstCnt;
- UINT16 PLvl2Lat;
- UINT16 PLvl3Lat;
- UINT16 FlushSize;
- UINT16 FlushStride;
- UINT8 DutyOffset;
- UINT8 DutyWidth;
- UINT8 DayAlrm;
- UINT8 MonAlrm;
- UINT8 Century;
- UINT16 IaPcBootArch;
- UINT8 Reserved1;
- UINT32 Flags;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ResetReg;
- UINT8 ResetValue;
- UINT16 ArmBootArch;
- UINT8 MinorVersion;
- UINT64 XFirmwareCtrl;
- UINT64 XDsdt;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
- UINT64 HypervisorVendorIdentity;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT16 ArmBootArch;
+ UINT8 MinorVersion;
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
+ UINT64 HypervisorVendorIdentity;
} EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE;
///
/// FADT Version (as defined in ACPI 6.2 spec.)
///
-#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06
+#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06
#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x02
//
@@ -285,62 +285,62 @@ typedef struct {
// Fixed ACPI Description Table Boot Architecture Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_6_2_LEGACY_DEVICES BIT0
-#define EFI_ACPI_6_2_8042 BIT1
-#define EFI_ACPI_6_2_VGA_NOT_PRESENT BIT2
-#define EFI_ACPI_6_2_MSI_NOT_SUPPORTED BIT3
-#define EFI_ACPI_6_2_PCIE_ASPM_CONTROLS BIT4
-#define EFI_ACPI_6_2_CMOS_RTC_NOT_PRESENT BIT5
+#define EFI_ACPI_6_2_LEGACY_DEVICES BIT0
+#define EFI_ACPI_6_2_8042 BIT1
+#define EFI_ACPI_6_2_VGA_NOT_PRESENT BIT2
+#define EFI_ACPI_6_2_MSI_NOT_SUPPORTED BIT3
+#define EFI_ACPI_6_2_PCIE_ASPM_CONTROLS BIT4
+#define EFI_ACPI_6_2_CMOS_RTC_NOT_PRESENT BIT5
//
// Fixed ACPI Description Table Arm Boot Architecture Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_6_2_ARM_PSCI_COMPLIANT BIT0
-#define EFI_ACPI_6_2_ARM_PSCI_USE_HVC BIT1
+#define EFI_ACPI_6_2_ARM_PSCI_COMPLIANT BIT0
+#define EFI_ACPI_6_2_ARM_PSCI_USE_HVC BIT1
//
// Fixed ACPI Description Table Fixed Feature Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_6_2_WBINVD BIT0
-#define EFI_ACPI_6_2_WBINVD_FLUSH BIT1
-#define EFI_ACPI_6_2_PROC_C1 BIT2
-#define EFI_ACPI_6_2_P_LVL2_UP BIT3
-#define EFI_ACPI_6_2_PWR_BUTTON BIT4
-#define EFI_ACPI_6_2_SLP_BUTTON BIT5
-#define EFI_ACPI_6_2_FIX_RTC BIT6
-#define EFI_ACPI_6_2_RTC_S4 BIT7
-#define EFI_ACPI_6_2_TMR_VAL_EXT BIT8
-#define EFI_ACPI_6_2_DCK_CAP BIT9
-#define EFI_ACPI_6_2_RESET_REG_SUP BIT10
-#define EFI_ACPI_6_2_SEALED_CASE BIT11
-#define EFI_ACPI_6_2_HEADLESS BIT12
-#define EFI_ACPI_6_2_CPU_SW_SLP BIT13
-#define EFI_ACPI_6_2_PCI_EXP_WAK BIT14
-#define EFI_ACPI_6_2_USE_PLATFORM_CLOCK BIT15
-#define EFI_ACPI_6_2_S4_RTC_STS_VALID BIT16
-#define EFI_ACPI_6_2_REMOTE_POWER_ON_CAPABLE BIT17
-#define EFI_ACPI_6_2_FORCE_APIC_CLUSTER_MODEL BIT18
-#define EFI_ACPI_6_2_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
-#define EFI_ACPI_6_2_HW_REDUCED_ACPI BIT20
-#define EFI_ACPI_6_2_LOW_POWER_S0_IDLE_CAPABLE BIT21
+#define EFI_ACPI_6_2_WBINVD BIT0
+#define EFI_ACPI_6_2_WBINVD_FLUSH BIT1
+#define EFI_ACPI_6_2_PROC_C1 BIT2
+#define EFI_ACPI_6_2_P_LVL2_UP BIT3
+#define EFI_ACPI_6_2_PWR_BUTTON BIT4
+#define EFI_ACPI_6_2_SLP_BUTTON BIT5
+#define EFI_ACPI_6_2_FIX_RTC BIT6
+#define EFI_ACPI_6_2_RTC_S4 BIT7
+#define EFI_ACPI_6_2_TMR_VAL_EXT BIT8
+#define EFI_ACPI_6_2_DCK_CAP BIT9
+#define EFI_ACPI_6_2_RESET_REG_SUP BIT10
+#define EFI_ACPI_6_2_SEALED_CASE BIT11
+#define EFI_ACPI_6_2_HEADLESS BIT12
+#define EFI_ACPI_6_2_CPU_SW_SLP BIT13
+#define EFI_ACPI_6_2_PCI_EXP_WAK BIT14
+#define EFI_ACPI_6_2_USE_PLATFORM_CLOCK BIT15
+#define EFI_ACPI_6_2_S4_RTC_STS_VALID BIT16
+#define EFI_ACPI_6_2_REMOTE_POWER_ON_CAPABLE BIT17
+#define EFI_ACPI_6_2_FORCE_APIC_CLUSTER_MODEL BIT18
+#define EFI_ACPI_6_2_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+#define EFI_ACPI_6_2_HW_REDUCED_ACPI BIT20
+#define EFI_ACPI_6_2_LOW_POWER_S0_IDLE_CAPABLE BIT21
///
/// Firmware ACPI Control Structure
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
- UINT32 HardwareSignature;
- UINT32 FirmwareWakingVector;
- UINT32 GlobalLock;
- UINT32 Flags;
- UINT64 XFirmwareWakingVector;
- UINT8 Version;
- UINT8 Reserved0[3];
- UINT32 OspmFlags;
- UINT8 Reserved1[24];
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved0[3];
+ UINT32 OspmFlags;
+ UINT8 Reserved1[24];
} EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE;
///
@@ -352,14 +352,14 @@ typedef struct {
/// Firmware Control Structure Feature Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_6_2_S4BIOS_F BIT0
-#define EFI_ACPI_6_2_64BIT_WAKE_SUPPORTED_F BIT1
+#define EFI_ACPI_6_2_S4BIOS_F BIT0
+#define EFI_ACPI_6_2_64BIT_WAKE_SUPPORTED_F BIT1
///
/// OSPM Enabled Firmware Control Structure Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_6_2_OSPM_64BIT_WAKE_F BIT0
+#define EFI_ACPI_6_2_OSPM_64BIT_WAKE_F BIT0
//
// Differentiated System Description Table,
@@ -368,29 +368,29 @@ typedef struct {
// no definition needed as they are common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
//
-#define EFI_ACPI_6_2_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
-#define EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_6_2_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
///
/// Multiple APIC Description Table header definition. The rest of the table
/// must be defined in a platform specific manner.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 LocalApicAddress;
- UINT32 Flags;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
///
/// MADT Revision (as defined in ACPI 6.2 spec.)
///
-#define EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04
+#define EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04
///
/// Multiple APIC Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_6_2_PCAT_COMPAT BIT0
+#define EFI_ACPI_6_2_PCAT_COMPAT BIT0
//
// Multiple APIC Description Table APIC structure types
@@ -422,57 +422,57 @@ typedef struct {
/// Processor Local APIC Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorUid;
- UINT8 ApicId;
- UINT32 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT8 ApicId;
+ UINT32 Flags;
} EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_STRUCTURE;
///
/// Local APIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_2_LOCAL_APIC_ENABLED BIT0
+#define EFI_ACPI_6_2_LOCAL_APIC_ENABLED BIT0
///
/// IO APIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 IoApicAddress;
- UINT32 GlobalSystemInterruptBase;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
} EFI_ACPI_6_2_IO_APIC_STRUCTURE;
///
/// Interrupt Source Override Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Bus;
- UINT8 Source;
- UINT32 GlobalSystemInterrupt;
- UINT16 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
} EFI_ACPI_6_2_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
///
/// Platform Interrupt Sources Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT8 InterruptType;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT8 IoSapicVector;
- UINT32 GlobalSystemInterrupt;
- UINT32 PlatformInterruptSourceFlags;
- UINT8 CpeiProcessorOverride;
- UINT8 Reserved[31];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
} EFI_ACPI_6_2_PLATFORM_INTERRUPT_APIC_STRUCTURE;
//
@@ -486,43 +486,43 @@ typedef struct {
/// Non-Maskable Interrupt Source Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT32 GlobalSystemInterrupt;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
} EFI_ACPI_6_2_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
///
/// Local APIC NMI Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorUid;
- UINT16 Flags;
- UINT8 LocalApicLint;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
} EFI_ACPI_6_2_LOCAL_APIC_NMI_STRUCTURE;
///
/// Local APIC Address Override Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT64 LocalApicAddress;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
} EFI_ACPI_6_2_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
///
/// IO SAPIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 GlobalSystemInterruptBase;
- UINT64 IoSapicAddress;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
} EFI_ACPI_6_2_IO_SAPIC_STRUCTURE;
///
@@ -530,169 +530,169 @@ typedef struct {
/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT8 LocalSapicId;
- UINT8 LocalSapicEid;
- UINT8 Reserved[3];
- UINT32 Flags;
- UINT32 ACPIProcessorUIDValue;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
} EFI_ACPI_6_2_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
///
/// Platform Interrupt Sources Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT8 InterruptType;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT8 IoSapicVector;
- UINT32 GlobalSystemInterrupt;
- UINT32 PlatformInterruptSourceFlags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
} EFI_ACPI_6_2_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
///
/// Platform Interrupt Source Flags.
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_6_2_CPEI_PROCESSOR_OVERRIDE BIT0
+#define EFI_ACPI_6_2_CPEI_PROCESSOR_OVERRIDE BIT0
///
/// Processor Local x2APIC Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[2];
- UINT32 X2ApicId;
- UINT32 Flags;
- UINT32 AcpiProcessorUid;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 AcpiProcessorUid;
} EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
///
/// Local x2APIC NMI Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT32 AcpiProcessorUid;
- UINT8 LocalX2ApicLint;
- UINT8 Reserved[3];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 AcpiProcessorUid;
+ UINT8 LocalX2ApicLint;
+ UINT8 Reserved[3];
} EFI_ACPI_6_2_LOCAL_X2APIC_NMI_STRUCTURE;
///
/// GIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT32 CPUInterfaceNumber;
- UINT32 AcpiProcessorUid;
- UINT32 Flags;
- UINT32 ParkingProtocolVersion;
- UINT32 PerformanceInterruptGsiv;
- UINT64 ParkedAddress;
- UINT64 PhysicalBaseAddress;
- UINT64 GICV;
- UINT64 GICH;
- UINT32 VGICMaintenanceInterrupt;
- UINT64 GICRBaseAddress;
- UINT64 MPIDR;
- UINT8 ProcessorPowerEfficiencyClass;
- UINT8 Reserved2[3];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 CPUInterfaceNumber;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ParkingProtocolVersion;
+ UINT32 PerformanceInterruptGsiv;
+ UINT64 ParkedAddress;
+ UINT64 PhysicalBaseAddress;
+ UINT64 GICV;
+ UINT64 GICH;
+ UINT32 VGICMaintenanceInterrupt;
+ UINT64 GICRBaseAddress;
+ UINT64 MPIDR;
+ UINT8 ProcessorPowerEfficiencyClass;
+ UINT8 Reserved2[3];
} EFI_ACPI_6_2_GIC_STRUCTURE;
///
/// GIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_2_GIC_ENABLED BIT0
-#define EFI_ACPI_6_2_PERFORMANCE_INTERRUPT_MODEL BIT1
-#define EFI_ACPI_6_2_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2
+#define EFI_ACPI_6_2_GIC_ENABLED BIT0
+#define EFI_ACPI_6_2_PERFORMANCE_INTERRUPT_MODEL BIT1
+#define EFI_ACPI_6_2_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2
///
/// GIC Distributor Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved1;
- UINT32 GicId;
- UINT64 PhysicalBaseAddress;
- UINT32 SystemVectorBase;
- UINT8 GicVersion;
- UINT8 Reserved2[3];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 SystemVectorBase;
+ UINT8 GicVersion;
+ UINT8 Reserved2[3];
} EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE;
///
/// GIC Version
///
-#define EFI_ACPI_6_2_GIC_V1 0x01
-#define EFI_ACPI_6_2_GIC_V2 0x02
-#define EFI_ACPI_6_2_GIC_V3 0x03
-#define EFI_ACPI_6_2_GIC_V4 0x04
+#define EFI_ACPI_6_2_GIC_V1 0x01
+#define EFI_ACPI_6_2_GIC_V2 0x02
+#define EFI_ACPI_6_2_GIC_V3 0x03
+#define EFI_ACPI_6_2_GIC_V4 0x04
///
/// GIC MSI Frame Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved1;
- UINT32 GicMsiFrameId;
- UINT64 PhysicalBaseAddress;
- UINT32 Flags;
- UINT16 SPICount;
- UINT16 SPIBase;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicMsiFrameId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Flags;
+ UINT16 SPICount;
+ UINT16 SPIBase;
} EFI_ACPI_6_2_GIC_MSI_FRAME_STRUCTURE;
///
/// GIC MSI Frame Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_2_SPI_COUNT_BASE_SELECT BIT0
+#define EFI_ACPI_6_2_SPI_COUNT_BASE_SELECT BIT0
///
/// GICR Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT64 DiscoveryRangeBaseAddress;
- UINT32 DiscoveryRangeLength;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 DiscoveryRangeBaseAddress;
+ UINT32 DiscoveryRangeLength;
} EFI_ACPI_6_2_GICR_STRUCTURE;
///
/// GIC Interrupt Translation Service Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT32 GicItsId;
- UINT64 PhysicalBaseAddress;
- UINT32 Reserved2;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 GicItsId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Reserved2;
} EFI_ACPI_6_2_GIC_ITS_STRUCTURE;
///
/// Smart Battery Description Table (SBST)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 WarningEnergyLevel;
- UINT32 LowEnergyLevel;
- UINT32 CriticalEnergyLevel;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
} EFI_ACPI_6_2_SMART_BATTERY_DESCRIPTION_TABLE;
///
/// SBST Version (as defined in ACPI 6.2 spec.)
///
-#define EFI_ACPI_6_2_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_2_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
///
/// Embedded Controller Boot Resources Table (ECDT)
@@ -700,11 +700,11 @@ typedef struct {
/// a fully qualified reference to the name space object.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE EcControl;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE EcData;
- UINT32 Uid;
- UINT8 GpeBit;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
} EFI_ACPI_6_2_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
///
@@ -717,9 +717,9 @@ typedef struct {
/// must be defined in a platform specific manner.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Reserved1; ///< Must be set to 1
- UINT64 Reserved2;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; ///< Must be set to 1
+ UINT64 Reserved2;
} EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
///
@@ -742,85 +742,85 @@ typedef struct {
/// Processor Local APIC/SAPIC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 ProximityDomain7To0;
- UINT8 ApicId;
- UINT32 Flags;
- UINT8 LocalSapicEid;
- UINT8 ProximityDomain31To8[3];
- UINT32 ClockDomain;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT32 ClockDomain;
} EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
///
/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
///
/// Memory Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 ProximityDomain;
- UINT16 Reserved1;
- UINT32 AddressBaseLow;
- UINT32 AddressBaseHigh;
- UINT32 LengthLow;
- UINT32 LengthHigh;
- UINT32 Reserved2;
- UINT32 Flags;
- UINT64 Reserved3;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
} EFI_ACPI_6_2_MEMORY_AFFINITY_STRUCTURE;
//
// Memory Flags. All other bits are reserved and must be 0.
//
-#define EFI_ACPI_6_2_MEMORY_ENABLED (1 << 0)
-#define EFI_ACPI_6_2_MEMORY_HOT_PLUGGABLE (1 << 1)
-#define EFI_ACPI_6_2_MEMORY_NONVOLATILE (1 << 2)
+#define EFI_ACPI_6_2_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_6_2_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_6_2_MEMORY_NONVOLATILE (1 << 2)
///
/// Processor Local x2APIC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved1[2];
- UINT32 ProximityDomain;
- UINT32 X2ApicId;
- UINT32 Flags;
- UINT32 ClockDomain;
- UINT8 Reserved2[4];
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1[2];
+ UINT32 ProximityDomain;
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+ UINT8 Reserved2[4];
} EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
///
/// GICC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 ProximityDomain;
- UINT32 AcpiProcessorUid;
- UINT32 Flags;
- UINT32 ClockDomain;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ClockDomain;
} EFI_ACPI_6_2_GICC_AFFINITY_STRUCTURE;
///
/// GICC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_2_GICC_ENABLED (1 << 0)
+#define EFI_ACPI_6_2_GICC_ENABLED (1 << 0)
///
/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 ProximityDomain;
- UINT8 Reserved[2];
- UINT32 ItsId;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT8 Reserved[2];
+ UINT32 ItsId;
} EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE;
///
@@ -828,8 +828,8 @@ typedef struct {
/// The rest of the table is a matrix.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 NumberOfSystemLocalities;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
} EFI_ACPI_6_2_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
///
@@ -841,14 +841,14 @@ typedef struct {
/// Corrected Platform Error Polling Table (CPEP)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 Reserved[8];
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[8];
} EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
///
/// CPEP Version (as defined in ACPI 6.2 spec.)
///
-#define EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+#define EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
//
// CPEP processor structure types.
@@ -859,66 +859,66 @@ typedef struct {
/// Corrected Platform Error Polling Processor Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT32 PollingInterval;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT32 PollingInterval;
} EFI_ACPI_6_2_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
///
/// Maximum System Characteristics Table (MSCT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 OffsetProxDomInfo;
- UINT32 MaximumNumberOfProximityDomains;
- UINT32 MaximumNumberOfClockDomains;
- UINT64 MaximumPhysicalAddress;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 OffsetProxDomInfo;
+ UINT32 MaximumNumberOfProximityDomains;
+ UINT32 MaximumNumberOfClockDomains;
+ UINT64 MaximumPhysicalAddress;
} EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
///
/// MSCT Version (as defined in ACPI 6.2 spec.)
///
-#define EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+#define EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
///
/// Maximum Proximity Domain Information Structure Definition
///
typedef struct {
- UINT8 Revision;
- UINT8 Length;
- UINT32 ProximityDomainRangeLow;
- UINT32 ProximityDomainRangeHigh;
- UINT32 MaximumProcessorCapacity;
- UINT64 MaximumMemoryCapacity;
+ UINT8 Revision;
+ UINT8 Length;
+ UINT32 ProximityDomainRangeLow;
+ UINT32 ProximityDomainRangeHigh;
+ UINT32 MaximumProcessorCapacity;
+ UINT64 MaximumMemoryCapacity;
} EFI_ACPI_6_2_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
///
/// ACPI RAS Feature Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 PlatformCommunicationChannelIdentifier[12];
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier[12];
} EFI_ACPI_6_2_RAS_FEATURE_TABLE;
///
/// RASF Version (as defined in ACPI 6.2 spec.)
///
-#define EFI_ACPI_6_2_RAS_FEATURE_TABLE_REVISION 0x01
+#define EFI_ACPI_6_2_RAS_FEATURE_TABLE_REVISION 0x01
///
/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
///
typedef struct {
- UINT32 Signature;
- UINT16 Command;
- UINT16 Status;
- UINT16 Version;
- UINT8 RASCapabilities[16];
- UINT8 SetRASCapabilities[16];
- UINT16 NumberOfRASFParameterBlocks;
- UINT32 SetRASCapabilitiesStatus;
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT16 Version;
+ UINT8 RASCapabilities[16];
+ UINT8 SetRASCapabilities[16];
+ UINT16 NumberOfRASFParameterBlocks;
+ UINT32 SetRASCapabilitiesStatus;
} EFI_ACPI_6_2_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
///
@@ -929,62 +929,62 @@ typedef struct {
///
/// ACPI RASF Platform RAS Capabilities
///
-#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0
-#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1
-#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2
-#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3
-#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4
///
/// ACPI RASF Parameter Block structure for PATROL_SCRUB
///
typedef struct {
- UINT16 Type;
- UINT16 Version;
- UINT16 Length;
- UINT16 PatrolScrubCommand;
- UINT64 RequestedAddressRange[2];
- UINT64 ActualAddressRange[2];
- UINT16 Flags;
- UINT8 RequestedSpeed;
+ UINT16 Type;
+ UINT16 Version;
+ UINT16 Length;
+ UINT16 PatrolScrubCommand;
+ UINT64 RequestedAddressRange[2];
+ UINT64 ActualAddressRange[2];
+ UINT16 Flags;
+ UINT8 RequestedSpeed;
} EFI_ACPI_6_2_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
///
/// ACPI RASF Patrol Scrub command
///
-#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
-#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
-#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
+#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
+#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
+#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
///
/// Memory Power State Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 PlatformCommunicationChannelIdentifier;
- UINT8 Reserved[3];
-// Memory Power Node Structure
-// Memory Power State Characteristics
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier;
+ UINT8 Reserved[3];
+ // Memory Power Node Structure
+ // Memory Power State Characteristics
} EFI_ACPI_6_2_MEMORY_POWER_STATUS_TABLE;
///
/// MPST Version (as defined in ACPI 6.2 spec.)
///
-#define EFI_ACPI_6_2_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+#define EFI_ACPI_6_2_MEMORY_POWER_STATE_TABLE_REVISION 0x01
///
/// MPST Platform Communication Channel Shared Memory Region definition.
///
typedef struct {
- UINT32 Signature;
- UINT16 Command;
- UINT16 Status;
- UINT32 MemoryPowerCommandRegister;
- UINT32 MemoryPowerStatusRegister;
- UINT32 PowerStateId;
- UINT32 MemoryPowerNodeId;
- UINT64 MemoryEnergyConsumed;
- UINT64 ExpectedAveragePowerComsuned;
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT32 MemoryPowerCommandRegister;
+ UINT32 MemoryPowerStatusRegister;
+ UINT32 PowerStateId;
+ UINT32 MemoryPowerNodeId;
+ UINT64 MemoryEnergyConsumed;
+ UINT64 ExpectedAveragePowerComsuned;
} EFI_ACPI_6_2_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
///
@@ -995,186 +995,186 @@ typedef struct {
///
/// ACPI MPST Memory Power command
///
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
///
/// MPST Memory Power Node Table
///
typedef struct {
- UINT8 PowerStateValue;
- UINT8 PowerStateInformationIndex;
+ UINT8 PowerStateValue;
+ UINT8 PowerStateInformationIndex;
} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE;
typedef struct {
- UINT8 Flag;
- UINT8 Reserved;
- UINT16 MemoryPowerNodeId;
- UINT32 Length;
- UINT64 AddressBase;
- UINT64 AddressLength;
- UINT32 NumberOfPowerStates;
- UINT32 NumberOfPhysicalComponents;
-//EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
-//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+ UINT8 Flag;
+ UINT8 Reserved;
+ UINT16 MemoryPowerNodeId;
+ UINT32 Length;
+ UINT64 AddressBase;
+ UINT64 AddressLength;
+ UINT32 NumberOfPowerStates;
+ UINT32 NumberOfPhysicalComponents;
+ // EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
} EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE;
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
typedef struct {
- UINT16 MemoryPowerNodeCount;
- UINT8 Reserved[2];
+ UINT16 MemoryPowerNodeCount;
+ UINT8 Reserved[2];
} EFI_ACPI_6_2_MPST_MEMORY_POWER_NODE_TABLE;
///
/// MPST Memory Power State Characteristics Table
///
typedef struct {
- UINT8 PowerStateStructureID;
- UINT8 Flag;
- UINT16 Reserved;
- UINT32 AveragePowerConsumedInMPS0;
- UINT32 RelativePowerSavingToMPS0;
- UINT64 ExitLatencyToMPS0;
+ UINT8 PowerStateStructureID;
+ UINT8 Flag;
+ UINT16 Reserved;
+ UINT32 AveragePowerConsumedInMPS0;
+ UINT32 RelativePowerSavingToMPS0;
+ UINT64 ExitLatencyToMPS0;
} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
typedef struct {
- UINT16 MemoryPowerStateCharacteristicsCount;
- UINT8 Reserved[2];
+ UINT16 MemoryPowerStateCharacteristicsCount;
+ UINT8 Reserved[2];
} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
///
/// Memory Topology Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
} EFI_ACPI_6_2_MEMORY_TOPOLOGY_TABLE;
///
/// PMTT Version (as defined in ACPI 6.2 spec.)
///
-#define EFI_ACPI_6_2_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
+#define EFI_ACPI_6_2_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
///
/// Common Memory Aggregator Device Structure.
///
typedef struct {
- UINT8 Type;
- UINT8 Reserved;
- UINT16 Length;
- UINT16 Flags;
- UINT16 Reserved1;
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16 Length;
+ UINT16 Flags;
+ UINT16 Reserved1;
} EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// Memory Aggregator Device Type
///
-#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0
-#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
-#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2
+#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0
+#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
+#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2
///
/// Socket Memory Aggregator Device Structure.
///
typedef struct {
- EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
- UINT16 SocketIdentifier;
- UINT16 Reserved;
-//EFI_ACPI_6_2_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];
+ EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 SocketIdentifier;
+ UINT16 Reserved;
+ // EFI_ACPI_6_2_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];
} EFI_ACPI_6_2_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// MemoryController Memory Aggregator Device Structure.
///
typedef struct {
- EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
- UINT32 ReadLatency;
- UINT32 WriteLatency;
- UINT32 ReadBandwidth;
- UINT32 WriteBandwidth;
- UINT16 OptimalAccessUnit;
- UINT16 OptimalAccessAlignment;
- UINT16 Reserved;
- UINT16 NumberOfProximityDomains;
-//UINT32 ProximityDomain[NumberOfProximityDomains];
-//EFI_ACPI_6_2_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];
+ EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT32 ReadLatency;
+ UINT32 WriteLatency;
+ UINT32 ReadBandwidth;
+ UINT32 WriteBandwidth;
+ UINT16 OptimalAccessUnit;
+ UINT16 OptimalAccessAlignment;
+ UINT16 Reserved;
+ UINT16 NumberOfProximityDomains;
+ // UINT32 ProximityDomain[NumberOfProximityDomains];
+ // EFI_ACPI_6_2_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];
} EFI_ACPI_6_2_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// DIMM Memory Aggregator Device Structure.
///
typedef struct {
- EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
- UINT16 PhysicalComponentIdentifier;
- UINT16 Reserved;
- UINT32 SizeOfDimm;
- UINT32 SmbiosHandle;
+ EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 PhysicalComponentIdentifier;
+ UINT16 Reserved;
+ UINT32 SizeOfDimm;
+ UINT32 SmbiosHandle;
} EFI_ACPI_6_2_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// Boot Graphics Resource Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
///
/// 2-bytes (16 bit) version ID. This value must be 1.
///
- UINT16 Version;
+ UINT16 Version;
///
/// 1-byte status field indicating current status about the table.
/// Bits[7:1] = Reserved (must be zero)
/// Bit [0] = Valid. A one indicates the boot image graphic is valid.
///
- UINT8 Status;
+ UINT8 Status;
///
/// 1-byte enumerated type field indicating format of the image.
/// 0 = Bitmap
/// 1 - 255 Reserved (for future use)
///
- UINT8 ImageType;
+ UINT8 ImageType;
///
/// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
/// of the image bitmap.
///
- UINT64 ImageAddress;
+ UINT64 ImageAddress;
///
/// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
/// (X, Y) display offset of the top left corner of the boot image.
/// The top left corner of the display is at offset (0, 0).
///
- UINT32 ImageOffsetX;
+ UINT32 ImageOffsetX;
///
/// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
/// (X, Y) display offset of the top left corner of the boot image.
/// The top left corner of the display is at offset (0, 0).
///
- UINT32 ImageOffsetY;
+ UINT32 ImageOffsetY;
} EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE;
///
/// BGRT Revision
///
-#define EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+#define EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
///
/// BGRT Version
///
-#define EFI_ACPI_6_2_BGRT_VERSION 0x01
+#define EFI_ACPI_6_2_BGRT_VERSION 0x01
///
/// BGRT Status
///
-#define EFI_ACPI_6_2_BGRT_STATUS_NOT_DISPLAYED 0x00
-#define EFI_ACPI_6_2_BGRT_STATUS_DISPLAYED 0x01
+#define EFI_ACPI_6_2_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_6_2_BGRT_STATUS_DISPLAYED 0x01
///
/// BGRT Image Type
@@ -1184,26 +1184,26 @@ typedef struct {
///
/// FPDT Version (as defined in ACPI 6.2 spec.)
///
-#define EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+#define EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
///
/// FPDT Performance Record Types
///
-#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
-#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
+#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
+#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
///
/// FPDT Performance Record Revision
///
-#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
-#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
+#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
///
/// FPDT Runtime Performance Record Types
///
-#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
-#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
-#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
///
/// FPDT Runtime Performance Record Revision
@@ -1216,77 +1216,77 @@ typedef struct {
/// FPDT Performance Record header
///
typedef struct {
- UINT16 Type;
- UINT8 Length;
- UINT8 Revision;
+ UINT16 Type;
+ UINT8 Length;
+ UINT8 Revision;
} EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER;
///
/// FPDT Performance Table header
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
+ UINT32 Signature;
+ UINT32 Length;
} EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER;
///
/// FPDT Firmware Basic Boot Performance Pointer Record Structure
///
typedef struct {
- EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
///
/// 64-bit processor-relative physical address of the Basic Boot Performance Table.
///
- UINT64 BootPerformanceTablePointer;
+ UINT64 BootPerformanceTablePointer;
} EFI_ACPI_6_2_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
///
/// FPDT S3 Performance Table Pointer Record Structure
///
typedef struct {
- EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
///
/// 64-bit processor-relative physical address of the S3 Performance Table.
///
- UINT64 S3PerformanceTablePointer;
+ UINT64 S3PerformanceTablePointer;
} EFI_ACPI_6_2_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
///
/// FPDT Firmware Basic Boot Performance Record Structure
///
typedef struct {
- EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
///
/// Timer value logged at the beginning of firmware image execution.
/// This may not always be zero or near zero.
///
- UINT64 ResetEnd;
+ UINT64 ResetEnd;
///
/// Timer value logged just prior to loading the OS boot loader into memory.
/// For non-UEFI compatible boots, this field must be zero.
///
- UINT64 OsLoaderLoadImageStart;
+ UINT64 OsLoaderLoadImageStart;
///
/// Timer value logged just prior to launching the previously loaded OS boot loader image.
/// For non-UEFI compatible boots, the timer value logged will be just prior
/// to the INT 19h handler invocation.
///
- UINT64 OsLoaderStartImageStart;
+ UINT64 OsLoaderStartImageStart;
///
/// Timer value logged at the point when the OS loader calls the
/// ExitBootServices function for UEFI compatible firmware.
/// For non-UEFI compatible boots, this field must be zero.
///
- UINT64 ExitBootServicesEntry;
+ UINT64 ExitBootServicesEntry;
///
/// Timer value logged at the point just prior to when the OS loader gaining
/// control back from calls the ExitBootServices function for UEFI compatible firmware.
/// For non-UEFI compatible boots, this field must be zero.
///
- UINT64 ExitBootServicesExit;
+ UINT64 ExitBootServicesExit;
} EFI_ACPI_6_2_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
///
@@ -1298,7 +1298,7 @@ typedef struct {
// FPDT Firmware Basic Boot Performance Table
//
typedef struct {
- EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER Header;
//
// one or more Performance Records.
//
@@ -1313,7 +1313,7 @@ typedef struct {
// FPDT Firmware S3 Boot Performance Table
//
typedef struct {
- EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER Header;
//
// one or more Performance Records.
//
@@ -1323,145 +1323,145 @@ typedef struct {
/// FPDT Basic S3 Resume Performance Record
///
typedef struct {
- EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;
///
/// A count of the number of S3 resume cycles since the last full boot sequence.
///
- UINT32 ResumeCount;
+ UINT32 ResumeCount;
///
/// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
/// OS waking vector. Only the most recent resume cycle's time is retained.
///
- UINT64 FullResume;
+ UINT64 FullResume;
///
/// Average timer value of all resume cycles logged since the last full boot
/// sequence, including the most recent resume. Note that the entire log of
/// timer values does not need to be retained in order to calculate this average.
///
- UINT64 AverageResume;
+ UINT64 AverageResume;
} EFI_ACPI_6_2_FPDT_S3_RESUME_RECORD;
///
/// FPDT Basic S3 Suspend Performance Record
///
typedef struct {
- EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;
///
/// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
/// Only the most recent suspend cycle's timer value is retained.
///
- UINT64 SuspendStart;
+ UINT64 SuspendStart;
///
/// Timer value recorded at the final firmware write to SLP_TYP (or other
/// mechanism) used to trigger hardware entry to S3.
/// Only the most recent suspend cycle's timer value is retained.
///
- UINT64 SuspendEnd;
+ UINT64 SuspendEnd;
} EFI_ACPI_6_2_FPDT_S3_SUSPEND_RECORD;
///
/// Firmware Performance Record Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
} EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_RECORD_TABLE;
///
/// Generic Timer Description Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 CntControlBasePhysicalAddress;
- UINT32 Reserved;
- UINT32 SecurePL1TimerGSIV;
- UINT32 SecurePL1TimerFlags;
- UINT32 NonSecurePL1TimerGSIV;
- UINT32 NonSecurePL1TimerFlags;
- UINT32 VirtualTimerGSIV;
- UINT32 VirtualTimerFlags;
- UINT32 NonSecurePL2TimerGSIV;
- UINT32 NonSecurePL2TimerFlags;
- UINT64 CntReadBasePhysicalAddress;
- UINT32 PlatformTimerCount;
- UINT32 PlatformTimerOffset;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 CntControlBasePhysicalAddress;
+ UINT32 Reserved;
+ UINT32 SecurePL1TimerGSIV;
+ UINT32 SecurePL1TimerFlags;
+ UINT32 NonSecurePL1TimerGSIV;
+ UINT32 NonSecurePL1TimerFlags;
+ UINT32 VirtualTimerGSIV;
+ UINT32 VirtualTimerFlags;
+ UINT32 NonSecurePL2TimerGSIV;
+ UINT32 NonSecurePL2TimerFlags;
+ UINT64 CntReadBasePhysicalAddress;
+ UINT32 PlatformTimerCount;
+ UINT32 PlatformTimerOffset;
} EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE;
///
/// GTDT Version (as defined in ACPI 6.2 spec.)
///
-#define EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02
///
/// Timer Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
-#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
-#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2
+#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2
///
/// Platform Timer Type
///
-#define EFI_ACPI_6_2_GTDT_GT_BLOCK 0
-#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG 1
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK 0
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG 1
///
/// GT Block Structure
///
typedef struct {
- UINT8 Type;
- UINT16 Length;
- UINT8 Reserved;
- UINT64 CntCtlBase;
- UINT32 GTBlockTimerCount;
- UINT32 GTBlockTimerOffset;
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 CntCtlBase;
+ UINT32 GTBlockTimerCount;
+ UINT32 GTBlockTimerOffset;
} EFI_ACPI_6_2_GTDT_GT_BLOCK_STRUCTURE;
///
/// GT Block Timer Structure
///
typedef struct {
- UINT8 GTFrameNumber;
- UINT8 Reserved[3];
- UINT64 CntBaseX;
- UINT64 CntEL0BaseX;
- UINT32 GTxPhysicalTimerGSIV;
- UINT32 GTxPhysicalTimerFlags;
- UINT32 GTxVirtualTimerGSIV;
- UINT32 GTxVirtualTimerFlags;
- UINT32 GTxCommonFlags;
+ UINT8 GTFrameNumber;
+ UINT8 Reserved[3];
+ UINT64 CntBaseX;
+ UINT64 CntEL0BaseX;
+ UINT32 GTxPhysicalTimerGSIV;
+ UINT32 GTxPhysicalTimerFlags;
+ UINT32 GTxVirtualTimerGSIV;
+ UINT32 GTxVirtualTimerFlags;
+ UINT32 GTxCommonFlags;
} EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_STRUCTURE;
///
/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
-#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
///
/// Common Flags Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0
-#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1
///
/// SBSA Generic Watchdog Structure
///
typedef struct {
- UINT8 Type;
- UINT16 Length;
- UINT8 Reserved;
- UINT64 RefreshFramePhysicalAddress;
- UINT64 WatchdogControlFramePhysicalAddress;
- UINT32 WatchdogTimerGSIV;
- UINT32 WatchdogTimerFlags;
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 RefreshFramePhysicalAddress;
+ UINT64 WatchdogControlFramePhysicalAddress;
+ UINT32 WatchdogTimerGSIV;
+ UINT32 WatchdogTimerFlags;
} EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;
///
/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0
-#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1
-#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2
//
// NVDIMM Firmware Interface Table definition.
@@ -1474,63 +1474,64 @@ typedef struct {
//
// NFIT Version (as defined in ACPI 6.2 spec.)
//
-#define EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
+#define EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
//
// Definition for NFIT Table Structure Types
//
-#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0
-#define EFI_ACPI_6_2_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1
-#define EFI_ACPI_6_2_NFIT_INTERLEAVE_STRUCTURE_TYPE 2
-#define EFI_ACPI_6_2_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3
-#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4
-#define EFI_ACPI_6_2_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5
-#define EFI_ACPI_6_2_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6
+#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0
+#define EFI_ACPI_6_2_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1
+#define EFI_ACPI_6_2_NFIT_INTERLEAVE_STRUCTURE_TYPE 2
+#define EFI_ACPI_6_2_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3
+#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4
+#define EFI_ACPI_6_2_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5
+#define EFI_ACPI_6_2_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6
+#define EFI_ACPI_6_2_NFIT_PLATFORM_CAPABILITIES_STRUCTURE_TYPE 7
//
// Definition for NFIT Structure Header
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
+ UINT16 Type;
+ UINT16 Length;
} EFI_ACPI_6_2_NFIT_STRUCTURE_HEADER;
//
// Definition for System Physical Address Range Structure
//
-#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0
-#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1
-#define EFI_ACPI_6_2_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
-#define EFI_ACPI_6_2_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
-#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
-#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
-#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
-#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
-#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
-#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
+#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0
+#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1
+#define EFI_ACPI_6_2_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
+#define EFI_ACPI_6_2_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
+#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
+#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT16 SPARangeStructureIndex;
- UINT16 Flags;
- UINT32 Reserved_8;
- UINT32 ProximityDomain;
- GUID AddressRangeTypeGUID;
- UINT64 SystemPhysicalAddressRangeBase;
- UINT64 SystemPhysicalAddressRangeLength;
- UINT64 AddressRangeMemoryMappingAttribute;
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 SPARangeStructureIndex;
+ UINT16 Flags;
+ UINT32 Reserved_8;
+ UINT32 ProximityDomain;
+ GUID AddressRangeTypeGUID;
+ UINT64 SystemPhysicalAddressRangeBase;
+ UINT64 SystemPhysicalAddressRangeLength;
+ UINT64 AddressRangeMemoryMappingAttribute;
} EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;
//
// Definition for Memory Device to System Physical Address Range Mapping Structure
//
typedef struct {
- UINT32 DIMMNumber:4;
- UINT32 MemoryChannelNumber:4;
- UINT32 MemoryControllerID:4;
- UINT32 SocketID:4;
- UINT32 NodeControllerID:12;
- UINT32 Reserved_28:4;
+ UINT32 DIMMNumber : 4;
+ UINT32 MemoryChannelNumber : 4;
+ UINT32 MemoryControllerID : 4;
+ UINT32 SocketID : 4;
+ UINT32 NodeControllerID : 12;
+ UINT32 Reserved_28 : 4;
} EFI_ACPI_6_2_NFIT_DEVICE_HANDLE;
#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0
@@ -1541,221 +1542,243 @@ typedef struct {
#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5
#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6
typedef struct {
- UINT16 Type;
- UINT16 Length;
- EFI_ACPI_6_2_NFIT_DEVICE_HANDLE NFITDeviceHandle;
- UINT16 NVDIMMPhysicalID;
- UINT16 NVDIMMRegionID;
- UINT16 SPARangeStructureIndex ;
- UINT16 NVDIMMControlRegionStructureIndex;
- UINT64 NVDIMMRegionSize;
- UINT64 RegionOffset;
- UINT64 NVDIMMPhysicalAddressRegionBase;
- UINT16 InterleaveStructureIndex;
- UINT16 InterleaveWays;
- UINT16 NVDIMMStateFlags;
- UINT16 Reserved_46;
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_2_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NVDIMMPhysicalID;
+ UINT16 NVDIMMRegionID;
+ UINT16 SPARangeStructureIndex;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT64 NVDIMMRegionSize;
+ UINT64 RegionOffset;
+ UINT64 NVDIMMPhysicalAddressRegionBase;
+ UINT16 InterleaveStructureIndex;
+ UINT16 InterleaveWays;
+ UINT16 NVDIMMStateFlags;
+ UINT16 Reserved_46;
} EFI_ACPI_6_2_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;
//
// Definition for Interleave Structure
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT16 InterleaveStructureIndex;
- UINT16 Reserved_6;
- UINT32 NumberOfLines;
- UINT32 LineSize;
-//UINT32 LineOffset[NumberOfLines];
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 InterleaveStructureIndex;
+ UINT16 Reserved_6;
+ UINT32 NumberOfLines;
+ UINT32 LineSize;
+ // UINT32 LineOffset[NumberOfLines];
} EFI_ACPI_6_2_NFIT_INTERLEAVE_STRUCTURE;
//
// Definition for SMBIOS Management Information Structure
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT32 Reserved_4;
-//UINT8 Data[];
+ UINT16 Type;
+ UINT16 Length;
+ UINT32 Reserved_4;
+ // UINT8 Data[];
} EFI_ACPI_6_2_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;
//
// Definition for NVDIMM Control Region Structure
//
-#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0
+#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0
-#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0
+#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT16 NVDIMMControlRegionStructureIndex;
- UINT16 VendorID;
- UINT16 DeviceID;
- UINT16 RevisionID;
- UINT16 SubsystemVendorID;
- UINT16 SubsystemDeviceID;
- UINT16 SubsystemRevisionID;
- UINT8 ValidFields;
- UINT8 ManufacturingLocation;
- UINT16 ManufacturingDate;
- UINT8 Reserved_22[2];
- UINT32 SerialNumber;
- UINT16 RegionFormatInterfaceCode;
- UINT16 NumberOfBlockControlWindows;
- UINT64 SizeOfBlockControlWindow;
- UINT64 CommandRegisterOffsetInBlockControlWindow;
- UINT64 SizeOfCommandRegisterInBlockControlWindows;
- UINT64 StatusRegisterOffsetInBlockControlWindow;
- UINT64 SizeOfStatusRegisterInBlockControlWindows;
- UINT16 NVDIMMControlRegionFlag;
- UINT8 Reserved_74[6];
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT8 ValidFields;
+ UINT8 ManufacturingLocation;
+ UINT16 ManufacturingDate;
+ UINT8 Reserved_22[2];
+ UINT32 SerialNumber;
+ UINT16 RegionFormatInterfaceCode;
+ UINT16 NumberOfBlockControlWindows;
+ UINT64 SizeOfBlockControlWindow;
+ UINT64 CommandRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfCommandRegisterInBlockControlWindows;
+ UINT64 StatusRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfStatusRegisterInBlockControlWindows;
+ UINT16 NVDIMMControlRegionFlag;
+ UINT8 Reserved_74[6];
} EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;
//
// Definition for NVDIMM Block Data Window Region Structure
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT16 NVDIMMControlRegionStructureIndex;
- UINT16 NumberOfBlockDataWindows;
- UINT64 BlockDataWindowStartOffset;
- UINT64 SizeOfBlockDataWindow;
- UINT64 BlockAccessibleMemoryCapacity;
- UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 NumberOfBlockDataWindows;
+ UINT64 BlockDataWindowStartOffset;
+ UINT64 SizeOfBlockDataWindow;
+ UINT64 BlockAccessibleMemoryCapacity;
+ UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;
} EFI_ACPI_6_2_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;
//
// Definition for Flush Hint Address Structure
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
- EFI_ACPI_6_2_NFIT_DEVICE_HANDLE NFITDeviceHandle;
- UINT16 NumberOfFlushHintAddresses;
- UINT8 Reserved_10[6];
-//UINT64 FlushHintAddress[NumberOfFlushHintAddresses];
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_2_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NumberOfFlushHintAddresses;
+ UINT8 Reserved_10[6];
+ // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];
} EFI_ACPI_6_2_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;
+//
+// Definition for Platform Capabilities Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT8 HighestValidCapability;
+ UINT8 Reserved_5[3];
+ UINT32 Capabilities;
+ UINT8 Reserved_12[4];
+} EFI_ACPI_6_2_NFIT_PLATFORM_CAPABILITIES_STRUCTURE;
+
+#define EFI_ACPI_6_2_NFIT_PLATFORM_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT0
+#define EFI_ACPI_6_2_NFIT_PLATFORM_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT1
+#define EFI_ACPI_6_2_NFIT_PLATFORM_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT2
+
///
/// Secure DEVices Table (SDEV)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
} EFI_ACPI_6_2_SECURE_DEVICES_TABLE_HEADER;
///
/// SDEV Revision (as defined in ACPI 6.2 spec.)
///
-#define EFI_ACPI_6_2_SECURE_DEVICES_TABLE_REVISION 0x01
+#define EFI_ACPI_6_2_SECURE_DEVICES_TABLE_REVISION 0x01
///
/// Secure Device types
///
-#define EFI_ACPI_6_2_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01
-#define EFI_ACPI_6_2_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00
+#define EFI_ACPI_6_2_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01
+#define EFI_ACPI_6_2_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00
///
/// Secure Device flags
///
-#define EFI_ACPI_6_2_SDEV_FLAG_ALLOW_HANDOFF BIT0
+#define EFI_ACPI_6_2_SDEV_FLAG_ALLOW_HANDOFF BIT0
///
/// SDEV Structure Header
///
typedef struct {
- UINT8 Type;
- UINT8 Flags;
- UINT16 Length;
+ UINT8 Type;
+ UINT8 Flags;
+ UINT16 Length;
} EFI_ACPI_6_2_SDEV_STRUCTURE_HEADER;
///
/// PCIe Endpoint Device based Secure Device Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Flags;
- UINT16 Length;
- UINT16 PciSegmentNumber;
- UINT16 StartBusNumber;
- UINT16 PciPathOffset;
- UINT16 PciPathLength;
- UINT16 VendorSpecificDataOffset;
- UINT16 VendorSpecificDataLength;
+ UINT8 Type;
+ UINT8 Flags;
+ UINT16 Length;
+ UINT16 PciSegmentNumber;
+ UINT16 StartBusNumber;
+ UINT16 PciPathOffset;
+ UINT16 PciPathLength;
+ UINT16 VendorSpecificDataOffset;
+ UINT16 VendorSpecificDataLength;
} EFI_ACPI_6_2_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE;
///
/// ACPI_NAMESPACE_DEVICE based Secure Device Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Flags;
- UINT16 Length;
- UINT16 DeviceIdentifierOffset;
- UINT16 DeviceIdentifierLength;
- UINT16 VendorSpecificDataOffset;
- UINT16 VendorSpecificDataLength;
+ UINT8 Type;
+ UINT8 Flags;
+ UINT16 Length;
+ UINT16 DeviceIdentifierOffset;
+ UINT16 DeviceIdentifierLength;
+ UINT16 VendorSpecificDataOffset;
+ UINT16 VendorSpecificDataLength;
} EFI_ACPI_6_2_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE;
///
/// Boot Error Record Table (BERT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 BootErrorRegionLength;
- UINT64 BootErrorRegion;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 BootErrorRegionLength;
+ UINT64 BootErrorRegion;
} EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_HEADER;
///
/// BERT Version (as defined in ACPI 6.2 spec.)
///
-#define EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+#define EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
///
/// Boot Error Region Block Status Definition
///
typedef struct {
- UINT32 UncorrectableErrorValid:1;
- UINT32 CorrectableErrorValid:1;
- UINT32 MultipleUncorrectableErrors:1;
- UINT32 MultipleCorrectableErrors:1;
- UINT32 ErrorDataEntryCount:10;
- UINT32 Reserved:18;
+ UINT32 UncorrectableErrorValid : 1;
+ UINT32 CorrectableErrorValid : 1;
+ UINT32 MultipleUncorrectableErrors : 1;
+ UINT32 MultipleCorrectableErrors : 1;
+ UINT32 ErrorDataEntryCount : 10;
+ UINT32 Reserved : 18;
} EFI_ACPI_6_2_ERROR_BLOCK_STATUS;
///
/// Boot Error Region Definition
///
typedef struct {
- EFI_ACPI_6_2_ERROR_BLOCK_STATUS BlockStatus;
- UINT32 RawDataOffset;
- UINT32 RawDataLength;
- UINT32 DataLength;
- UINT32 ErrorSeverity;
+ EFI_ACPI_6_2_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
} EFI_ACPI_6_2_BOOT_ERROR_REGION_STRUCTURE;
//
// Boot Error Severity types
//
-#define EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTABLE 0x00
+#define EFI_ACPI_6_2_ERROR_SEVERITY_RECOVERABLE 0x00
#define EFI_ACPI_6_2_ERROR_SEVERITY_FATAL 0x01
#define EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTED 0x02
#define EFI_ACPI_6_2_ERROR_SEVERITY_NONE 0x03
+//
+// The term 'Correctable' is no longer being used as an error severity of the
+// reported error since ACPI Specification Version 5.1 Errata B.
+// The below macro is considered as deprecated and should no longer be used.
+//
+#define EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTABLE 0x00
///
/// Generic Error Data Entry Definition
///
typedef struct {
- UINT8 SectionType[16];
- UINT32 ErrorSeverity;
- UINT16 Revision;
- UINT8 ValidationBits;
- UINT8 Flags;
- UINT32 ErrorDataLength;
- UINT8 FruId[16];
- UINT8 FruText[20];
- UINT8 Timestamp[8];
+ UINT8 SectionType[16];
+ UINT32 ErrorSeverity;
+ UINT16 Revision;
+ UINT8 ValidationBits;
+ UINT8 Flags;
+ UINT32 ErrorDataLength;
+ UINT8 FruId[16];
+ UINT8 FruText[20];
+ UINT8 Timestamp[8];
} EFI_ACPI_6_2_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
///
@@ -1767,14 +1790,14 @@ typedef struct {
/// HEST - Hardware Error Source Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 ErrorSourceCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 ErrorSourceCount;
} EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
///
/// HEST Version (as defined in ACPI 6.2 spec.)
///
-#define EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+#define EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
//
// Error Source structure types.
@@ -1792,237 +1815,237 @@ typedef struct {
//
// Error Source structure flags.
//
-#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
-#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
-#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)
+#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
+#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
+#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)
///
/// IA-32 Architecture Machine Check Exception Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT64 GlobalCapabilityInitData;
- UINT64 GlobalControlInitData;
- UINT8 NumberOfHardwareBanks;
- UINT8 Reserved1[7];
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT64 GlobalCapabilityInitData;
+ UINT64 GlobalControlInitData;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[7];
} EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
///
/// IA-32 Architecture Machine Check Bank Structure Definition
///
typedef struct {
- UINT8 BankNumber;
- UINT8 ClearStatusOnInitialization;
- UINT8 StatusDataFormat;
- UINT8 Reserved0;
- UINT32 ControlRegisterMsrAddress;
- UINT64 ControlInitData;
- UINT32 StatusRegisterMsrAddress;
- UINT32 AddressRegisterMsrAddress;
- UINT32 MiscRegisterMsrAddress;
+ UINT8 BankNumber;
+ UINT8 ClearStatusOnInitialization;
+ UINT8 StatusDataFormat;
+ UINT8 Reserved0;
+ UINT32 ControlRegisterMsrAddress;
+ UINT64 ControlInitData;
+ UINT32 StatusRegisterMsrAddress;
+ UINT32 AddressRegisterMsrAddress;
+ UINT32 MiscRegisterMsrAddress;
} EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
///
/// IA-32 Architecture Machine Check Bank Structure MCA data format
///
-#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
-#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
-#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
//
// Hardware Error Notification types. All other values are reserved
//
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_MCE 0x06
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_MCE 0x06
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B
///
/// Hardware Error Notification Configuration Write Enable Structure Definition
///
typedef struct {
- UINT16 Type:1;
- UINT16 PollInterval:1;
- UINT16 SwitchToPollingThresholdValue:1;
- UINT16 SwitchToPollingThresholdWindow:1;
- UINT16 ErrorThresholdValue:1;
- UINT16 ErrorThresholdWindow:1;
- UINT16 Reserved:10;
+ UINT16 Type : 1;
+ UINT16 PollInterval : 1;
+ UINT16 SwitchToPollingThresholdValue : 1;
+ UINT16 SwitchToPollingThresholdWindow : 1;
+ UINT16 ErrorThresholdValue : 1;
+ UINT16 ErrorThresholdWindow : 1;
+ UINT16 Reserved : 10;
} EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
///
/// Hardware Error Notification Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
- UINT32 PollInterval;
- UINT32 Vector;
- UINT32 SwitchToPollingThresholdValue;
- UINT32 SwitchToPollingThresholdWindow;
- UINT32 ErrorThresholdValue;
- UINT32 ErrorThresholdWindow;
+ UINT8 Type;
+ UINT8 Length;
+ EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
+ UINT32 PollInterval;
+ UINT32 Vector;
+ UINT32 SwitchToPollingThresholdValue;
+ UINT32 SwitchToPollingThresholdWindow;
+ UINT32 ErrorThresholdValue;
+ UINT32 ErrorThresholdWindow;
} EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
///
/// IA-32 Architecture Corrected Machine Check Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
- UINT8 NumberOfHardwareBanks;
- UINT8 Reserved1[3];
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
} EFI_ACPI_6_2_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
///
/// IA-32 Architecture NMI Error Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 MaxRawDataLength;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
} EFI_ACPI_6_2_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
///
/// PCI Express Root Port AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
- UINT32 RootErrorCommand;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 RootErrorCommand;
} EFI_ACPI_6_2_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
///
/// PCI Express Device AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
} EFI_ACPI_6_2_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
///
/// PCI Express Bridge AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
- UINT32 SecondaryUncorrectableErrorMask;
- UINT32 SecondaryUncorrectableErrorSeverity;
- UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 SecondaryUncorrectableErrorMask;
+ UINT32 SecondaryUncorrectableErrorSeverity;
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
} EFI_ACPI_6_2_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
///
/// Generic Hardware Error Source Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT16 RelatedSourceId;
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 MaxRawDataLength;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
- EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
- UINT32 ErrorStatusBlockLength;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
} EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
///
/// Generic Hardware Error Source Version 2 Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT16 RelatedSourceId;
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 MaxRawDataLength;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
- EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
- UINT32 ErrorStatusBlockLength;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;
- UINT64 ReadAckPreserve;
- UINT64 ReadAckWrite;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;
+ UINT64 ReadAckPreserve;
+ UINT64 ReadAckWrite;
} EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;
///
/// Generic Error Status Definition
///
typedef struct {
- EFI_ACPI_6_2_ERROR_BLOCK_STATUS BlockStatus;
- UINT32 RawDataOffset;
- UINT32 RawDataLength;
- UINT32 DataLength;
- UINT32 ErrorSeverity;
+ EFI_ACPI_6_2_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
} EFI_ACPI_6_2_GENERIC_ERROR_STATUS_STRUCTURE;
///
@@ -2039,301 +2062,301 @@ typedef struct {
EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
UINT8 NumberOfHardwareBanks;
UINT8 Reserved1[3];
-} EFI_ACPI_6_2_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;;
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;
///
/// HMAT - Heterogeneous Memory Attribute Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 Reserved[4];
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[4];
} EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;
///
/// HMAT Revision (as defined in ACPI 6.2 spec.)
///
-#define EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x01
+#define EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x01
///
/// HMAT types
///
-#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SUBSYSTEM_ADDRESS_RANGE 0x00
-#define EFI_ACPI_6_2_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01
-#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02
+#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SUBSYSTEM_ADDRESS_RANGE 0x00
+#define EFI_ACPI_6_2_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01
+#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02
///
/// HMAT Structure Header
///
typedef struct {
- UINT16 Type;
- UINT8 Reserved[2];
- UINT32 Length;
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
} EFI_ACPI_6_2_HMAT_STRUCTURE_HEADER;
///
/// Memory Subsystem Address Range Structure flags
///
typedef struct {
- UINT16 ProcessorProximityDomainValid:1;
- UINT16 MemoryProximityDomainValid:1;
- UINT16 ReservationHint:1;
- UINT16 Reserved:13;
+ UINT16 ProcessorProximityDomainValid : 1;
+ UINT16 MemoryProximityDomainValid : 1;
+ UINT16 ReservationHint : 1;
+ UINT16 Reserved : 13;
} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE_FLAGS;
///
/// Memory Subsystem Address Range Structure
///
typedef struct {
- UINT16 Type;
- UINT8 Reserved[2];
- UINT32 Length;
- EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE_FLAGS Flags;
- UINT8 Reserved1[2];
- UINT32 ProcessorProximityDomain;
- UINT32 MemoryProximityDomain;
- UINT8 Reserved2[4];
- UINT64 SystemPhysicalAddressRangeBase;
- UINT64 SystemPhysicalAddressRangeLength;
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE_FLAGS Flags;
+ UINT8 Reserved1[2];
+ UINT32 ProcessorProximityDomain;
+ UINT32 MemoryProximityDomain;
+ UINT8 Reserved2[4];
+ UINT64 SystemPhysicalAddressRangeBase;
+ UINT64 SystemPhysicalAddressRangeLength;
} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE;
///
/// System Locality Latency and Bandwidth Information Structure flags
///
typedef struct {
- UINT8 MemoryHierarchy:5;
- UINT8 Reserved:3;
+ UINT8 MemoryHierarchy : 5;
+ UINT8 Reserved : 3;
} EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS;
///
/// System Locality Latency and Bandwidth Information Structure
///
typedef struct {
- UINT16 Type;
- UINT8 Reserved[2];
- UINT32 Length;
- EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;
- UINT8 DataType;
- UINT8 Reserved1[2];
- UINT32 NumberOfInitiatorProximityDomains;
- UINT32 NumberOfTargetProximityDomains;
- UINT8 Reserved2[4];
- UINT64 EntryBaseUnit;
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;
+ UINT8 DataType;
+ UINT8 Reserved1[2];
+ UINT32 NumberOfInitiatorProximityDomains;
+ UINT32 NumberOfTargetProximityDomains;
+ UINT8 Reserved2[4];
+ UINT64 EntryBaseUnit;
} EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO;
///
/// Memory Side Cache Information Structure cache attributes
///
typedef struct {
- UINT32 TotalCacheLevels:4;
- UINT32 CacheLevel:4;
- UINT32 CacheAssociativity:4;
- UINT32 WritePolicy:4;
- UINT32 CacheLineSize:16;
+ UINT32 TotalCacheLevels : 4;
+ UINT32 CacheLevel : 4;
+ UINT32 CacheAssociativity : 4;
+ UINT32 WritePolicy : 4;
+ UINT32 CacheLineSize : 16;
} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES;
///
/// Memory Side Cache Information Structure
///
typedef struct {
- UINT16 Type;
- UINT8 Reserved[2];
- UINT32 Length;
- UINT32 MemoryProximityDomain;
- UINT8 Reserved1[4];
- UINT64 MemorySideCacheSize;
- EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;
- UINT8 Reserved2[2];
- UINT16 NumberOfSmbiosHandles;
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ UINT32 MemoryProximityDomain;
+ UINT8 Reserved1[4];
+ UINT64 MemorySideCacheSize;
+ EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;
+ UINT8 Reserved2[2];
+ UINT16 NumberOfSmbiosHandles;
} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO;
///
/// ERST - Error Record Serialization Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 SerializationHeaderSize;
- UINT8 Reserved0[4];
- UINT32 InstructionEntryCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 SerializationHeaderSize;
+ UINT8 Reserved0[4];
+ UINT32 InstructionEntryCount;
} EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
///
/// ERST Version (as defined in ACPI 6.2 spec.)
///
-#define EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
///
/// ERST Serialization Actions
///
-#define EFI_ACPI_6_2_ERST_BEGIN_WRITE_OPERATION 0x00
-#define EFI_ACPI_6_2_ERST_BEGIN_READ_OPERATION 0x01
-#define EFI_ACPI_6_2_ERST_BEGIN_CLEAR_OPERATION 0x02
-#define EFI_ACPI_6_2_ERST_END_OPERATION 0x03
-#define EFI_ACPI_6_2_ERST_SET_RECORD_OFFSET 0x04
-#define EFI_ACPI_6_2_ERST_EXECUTE_OPERATION 0x05
-#define EFI_ACPI_6_2_ERST_CHECK_BUSY_STATUS 0x06
-#define EFI_ACPI_6_2_ERST_GET_COMMAND_STATUS 0x07
-#define EFI_ACPI_6_2_ERST_GET_RECORD_IDENTIFIER 0x08
-#define EFI_ACPI_6_2_ERST_SET_RECORD_IDENTIFIER 0x09
-#define EFI_ACPI_6_2_ERST_GET_RECORD_COUNT 0x0A
-#define EFI_ACPI_6_2_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
-#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
-#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
-#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
-#define EFI_ACPI_6_2_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10
+#define EFI_ACPI_6_2_ERST_BEGIN_WRITE_OPERATION 0x00
+#define EFI_ACPI_6_2_ERST_BEGIN_READ_OPERATION 0x01
+#define EFI_ACPI_6_2_ERST_BEGIN_CLEAR_OPERATION 0x02
+#define EFI_ACPI_6_2_ERST_END_OPERATION 0x03
+#define EFI_ACPI_6_2_ERST_SET_RECORD_OFFSET 0x04
+#define EFI_ACPI_6_2_ERST_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_2_ERST_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_2_ERST_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_2_ERST_GET_RECORD_IDENTIFIER 0x08
+#define EFI_ACPI_6_2_ERST_SET_RECORD_IDENTIFIER 0x09
+#define EFI_ACPI_6_2_ERST_GET_RECORD_COUNT 0x0A
+#define EFI_ACPI_6_2_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
+#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
+#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
+#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
+#define EFI_ACPI_6_2_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10
///
/// ERST Action Command Status
///
-#define EFI_ACPI_6_2_ERST_STATUS_SUCCESS 0x00
-#define EFI_ACPI_6_2_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
-#define EFI_ACPI_6_2_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
-#define EFI_ACPI_6_2_ERST_STATUS_FAILED 0x03
-#define EFI_ACPI_6_2_ERST_STATUS_RECORD_STORE_EMPTY 0x04
-#define EFI_ACPI_6_2_ERST_STATUS_RECORD_NOT_FOUND 0x05
+#define EFI_ACPI_6_2_ERST_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_2_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
+#define EFI_ACPI_6_2_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
+#define EFI_ACPI_6_2_ERST_STATUS_FAILED 0x03
+#define EFI_ACPI_6_2_ERST_STATUS_RECORD_STORE_EMPTY 0x04
+#define EFI_ACPI_6_2_ERST_STATUS_RECORD_NOT_FOUND 0x05
///
/// ERST Serialization Instructions
///
-#define EFI_ACPI_6_2_ERST_READ_REGISTER 0x00
-#define EFI_ACPI_6_2_ERST_READ_REGISTER_VALUE 0x01
-#define EFI_ACPI_6_2_ERST_WRITE_REGISTER 0x02
-#define EFI_ACPI_6_2_ERST_WRITE_REGISTER_VALUE 0x03
-#define EFI_ACPI_6_2_ERST_NOOP 0x04
-#define EFI_ACPI_6_2_ERST_LOAD_VAR1 0x05
-#define EFI_ACPI_6_2_ERST_LOAD_VAR2 0x06
-#define EFI_ACPI_6_2_ERST_STORE_VAR1 0x07
-#define EFI_ACPI_6_2_ERST_ADD 0x08
-#define EFI_ACPI_6_2_ERST_SUBTRACT 0x09
-#define EFI_ACPI_6_2_ERST_ADD_VALUE 0x0A
-#define EFI_ACPI_6_2_ERST_SUBTRACT_VALUE 0x0B
-#define EFI_ACPI_6_2_ERST_STALL 0x0C
-#define EFI_ACPI_6_2_ERST_STALL_WHILE_TRUE 0x0D
-#define EFI_ACPI_6_2_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
-#define EFI_ACPI_6_2_ERST_GOTO 0x0F
-#define EFI_ACPI_6_2_ERST_SET_SRC_ADDRESS_BASE 0x10
-#define EFI_ACPI_6_2_ERST_SET_DST_ADDRESS_BASE 0x11
-#define EFI_ACPI_6_2_ERST_MOVE_DATA 0x12
+#define EFI_ACPI_6_2_ERST_READ_REGISTER 0x00
+#define EFI_ACPI_6_2_ERST_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_2_ERST_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_2_ERST_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_2_ERST_NOOP 0x04
+#define EFI_ACPI_6_2_ERST_LOAD_VAR1 0x05
+#define EFI_ACPI_6_2_ERST_LOAD_VAR2 0x06
+#define EFI_ACPI_6_2_ERST_STORE_VAR1 0x07
+#define EFI_ACPI_6_2_ERST_ADD 0x08
+#define EFI_ACPI_6_2_ERST_SUBTRACT 0x09
+#define EFI_ACPI_6_2_ERST_ADD_VALUE 0x0A
+#define EFI_ACPI_6_2_ERST_SUBTRACT_VALUE 0x0B
+#define EFI_ACPI_6_2_ERST_STALL 0x0C
+#define EFI_ACPI_6_2_ERST_STALL_WHILE_TRUE 0x0D
+#define EFI_ACPI_6_2_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
+#define EFI_ACPI_6_2_ERST_GOTO 0x0F
+#define EFI_ACPI_6_2_ERST_SET_SRC_ADDRESS_BASE 0x10
+#define EFI_ACPI_6_2_ERST_SET_DST_ADDRESS_BASE 0x11
+#define EFI_ACPI_6_2_ERST_MOVE_DATA 0x12
///
/// ERST Instruction Flags
///
-#define EFI_ACPI_6_2_ERST_PRESERVE_REGISTER 0x01
+#define EFI_ACPI_6_2_ERST_PRESERVE_REGISTER 0x01
///
/// ERST Serialization Instruction Entry
///
typedef struct {
- UINT8 SerializationAction;
- UINT8 Instruction;
- UINT8 Flags;
- UINT8 Reserved0;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
- UINT64 Value;
- UINT64 Mask;
+ UINT8 SerializationAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
} EFI_ACPI_6_2_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
///
/// EINJ - Error Injection Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 InjectionHeaderSize;
- UINT8 InjectionFlags;
- UINT8 Reserved0[3];
- UINT32 InjectionEntryCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 InjectionHeaderSize;
+ UINT8 InjectionFlags;
+ UINT8 Reserved0[3];
+ UINT32 InjectionEntryCount;
} EFI_ACPI_6_2_ERROR_INJECTION_TABLE_HEADER;
///
/// EINJ Version (as defined in ACPI 6.2 spec.)
///
-#define EFI_ACPI_6_2_ERROR_INJECTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_2_ERROR_INJECTION_TABLE_REVISION 0x01
///
/// EINJ Error Injection Actions
///
-#define EFI_ACPI_6_2_EINJ_BEGIN_INJECTION_OPERATION 0x00
-#define EFI_ACPI_6_2_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
-#define EFI_ACPI_6_2_EINJ_SET_ERROR_TYPE 0x02
-#define EFI_ACPI_6_2_EINJ_GET_ERROR_TYPE 0x03
-#define EFI_ACPI_6_2_EINJ_END_OPERATION 0x04
-#define EFI_ACPI_6_2_EINJ_EXECUTE_OPERATION 0x05
-#define EFI_ACPI_6_2_EINJ_CHECK_BUSY_STATUS 0x06
-#define EFI_ACPI_6_2_EINJ_GET_COMMAND_STATUS 0x07
-#define EFI_ACPI_6_2_EINJ_TRIGGER_ERROR 0xFF
+#define EFI_ACPI_6_2_EINJ_BEGIN_INJECTION_OPERATION 0x00
+#define EFI_ACPI_6_2_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
+#define EFI_ACPI_6_2_EINJ_SET_ERROR_TYPE 0x02
+#define EFI_ACPI_6_2_EINJ_GET_ERROR_TYPE 0x03
+#define EFI_ACPI_6_2_EINJ_END_OPERATION 0x04
+#define EFI_ACPI_6_2_EINJ_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_2_EINJ_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_2_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_2_EINJ_TRIGGER_ERROR 0xFF
///
/// EINJ Action Command Status
///
-#define EFI_ACPI_6_2_EINJ_STATUS_SUCCESS 0x00
-#define EFI_ACPI_6_2_EINJ_STATUS_UNKNOWN_FAILURE 0x01
-#define EFI_ACPI_6_2_EINJ_STATUS_INVALID_ACCESS 0x02
+#define EFI_ACPI_6_2_EINJ_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_2_EINJ_STATUS_UNKNOWN_FAILURE 0x01
+#define EFI_ACPI_6_2_EINJ_STATUS_INVALID_ACCESS 0x02
///
/// EINJ Error Type Definition
///
-#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
-#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
-#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
-#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
-#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
-#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
-#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
-#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
-#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
-#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
-#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
-#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
+#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
+#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
+#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
+#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
+#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
+#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
+#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
+#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
+#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
+#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
+#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
+#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
///
/// EINJ Injection Instructions
///
-#define EFI_ACPI_6_2_EINJ_READ_REGISTER 0x00
-#define EFI_ACPI_6_2_EINJ_READ_REGISTER_VALUE 0x01
-#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER 0x02
-#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER_VALUE 0x03
-#define EFI_ACPI_6_2_EINJ_NOOP 0x04
+#define EFI_ACPI_6_2_EINJ_READ_REGISTER 0x00
+#define EFI_ACPI_6_2_EINJ_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_2_EINJ_NOOP 0x04
///
/// EINJ Instruction Flags
///
-#define EFI_ACPI_6_2_EINJ_PRESERVE_REGISTER 0x01
+#define EFI_ACPI_6_2_EINJ_PRESERVE_REGISTER 0x01
///
/// EINJ Injection Instruction Entry
///
typedef struct {
- UINT8 InjectionAction;
- UINT8 Instruction;
- UINT8 Flags;
- UINT8 Reserved0;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
- UINT64 Value;
- UINT64 Mask;
+ UINT8 InjectionAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
} EFI_ACPI_6_2_EINJ_INJECTION_INSTRUCTION_ENTRY;
///
/// EINJ Trigger Action Table
///
typedef struct {
- UINT32 HeaderSize;
- UINT32 Revision;
- UINT32 TableSize;
- UINT32 EntryCount;
+ UINT32 HeaderSize;
+ UINT32 Revision;
+ UINT32 TableSize;
+ UINT32 EntryCount;
} EFI_ACPI_6_2_EINJ_TRIGGER_ACTION_TABLE;
///
/// Platform Communications Channel Table (PCCT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Flags;
- UINT64 Reserved;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Flags;
+ UINT64 Reserved;
} EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
///
/// PCCT Version (as defined in ACPI 6.2 spec.)
///
-#define EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02
+#define EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02
///
/// PCCT Global Flags
@@ -2343,35 +2366,35 @@ typedef struct {
//
// PCCT Subspace type
//
-#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_GENERIC 0x00
-#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01
-#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02
-#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03
-#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_GENERIC 0x00
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04
///
/// PCC Subspace Structure Header
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
+ UINT8 Type;
+ UINT8 Length;
} EFI_ACPI_6_2_PCCT_SUBSPACE_HEADER;
///
/// Generic Communications Subspace Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[6];
- UINT64 BaseAddress;
- UINT64 AddressLength;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
- UINT64 DoorbellPreserve;
- UINT64 DoorbellWrite;
- UINT32 NominalLatency;
- UINT32 MaximumPeriodicAccessRate;
- UINT16 MinimumRequestTurnaroundTime;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[6];
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
} EFI_ACPI_6_2_PCCT_SUBSPACE_GENERIC;
///
@@ -2379,18 +2402,18 @@ typedef struct {
///
typedef struct {
- UINT8 Command;
- UINT8 Reserved:7;
- UINT8 NotifyOnCompletion:1;
+ UINT8 Command;
+ UINT8 Reserved : 7;
+ UINT8 NotifyOnCompletion : 1;
} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
typedef struct {
- UINT8 CommandComplete:1;
- UINT8 PlatformInterrupt:1;
- UINT8 Error:1;
- UINT8 PlatformNotification:1;
- UINT8 Reserved:4;
- UINT8 Reserved1;
+ UINT8 CommandComplete : 1;
+ UINT8 PlatformInterrupt : 1;
+ UINT8 Error : 1;
+ UINT8 PlatformNotification : 1;
+ UINT8 Reserved : 4;
+ UINT8 Reserved1;
} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
typedef struct {
@@ -2399,78 +2422,78 @@ typedef struct {
EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;
} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
-#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0
-#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1
///
/// Type 1 HW-Reduced Communications Subspace Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 PlatformInterrupt;
- UINT8 PlatformInterruptFlags;
- UINT8 Reserved;
- UINT64 BaseAddress;
- UINT64 AddressLength;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
- UINT64 DoorbellPreserve;
- UINT64 DoorbellWrite;
- UINT32 NominalLatency;
- UINT32 MaximumPeriodicAccessRate;
- UINT16 MinimumRequestTurnaroundTime;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
} EFI_ACPI_6_2_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
///
/// Type 2 HW-Reduced Communications Subspace Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 PlatformInterrupt;
- UINT8 PlatformInterruptFlags;
- UINT8 Reserved;
- UINT64 BaseAddress;
- UINT64 AddressLength;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
- UINT64 DoorbellPreserve;
- UINT64 DoorbellWrite;
- UINT32 NominalLatency;
- UINT32 MaximumPeriodicAccessRate;
- UINT16 MinimumRequestTurnaroundTime;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
- UINT64 PlatformInterruptAckPreserve;
- UINT64 PlatformInterruptAckWrite;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
+ UINT64 PlatformInterruptAckPreserve;
+ UINT64 PlatformInterruptAckWrite;
} EFI_ACPI_6_2_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
///
/// Type 3 Extended PCC Subspace Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 PlatformInterrupt;
- UINT8 PlatformInterruptFlags;
- UINT8 Reserved;
- UINT64 BaseAddress;
- UINT32 AddressLength;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
- UINT64 DoorbellPreserve;
- UINT64 DoorbellWrite;
- UINT32 NominalLatency;
- UINT32 MaximumPeriodicAccessRate;
- UINT32 MinimumRequestTurnaroundTime;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
- UINT64 PlatformInterruptAckPreserve;
- UINT64 PlatformInterruptAckSet;
- UINT8 Reserved1[8];
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;
- UINT64 CommandCompleteCheckMask;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;
- UINT64 CommandCompleteUpdatePreserve;
- UINT64 CommandCompleteUpdateSet;
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;
- UINT64 ErrorStatusMask;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT32 AddressLength;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT32 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
+ UINT64 PlatformInterruptAckPreserve;
+ UINT64 PlatformInterruptAckSet;
+ UINT8 Reserved1[8];
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;
+ UINT64 CommandCompleteCheckMask;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;
+ UINT64 CommandCompleteUpdatePreserve;
+ UINT64 CommandCompleteUpdateSet;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;
+ UINT64 ErrorStatusMask;
} EFI_ACPI_6_2_PCCT_SUBSPACE_3_EXTENDED_PCC;
///
@@ -2478,45 +2501,45 @@ typedef struct {
///
typedef EFI_ACPI_6_2_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_2_PCCT_SUBSPACE_4_EXTENDED_PCC;
-#define EFI_ACPI_6_2_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0
+#define EFI_ACPI_6_2_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0
typedef struct {
- UINT32 Signature;
- UINT32 Flags;
- UINT32 Length;
- UINT32 Command;
+ UINT32 Signature;
+ UINT32 Flags;
+ UINT32 Length;
+ UINT32 Command;
} EFI_ACPI_6_2_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER;
///
/// Platform Debug Trigger Table (PDTT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 TriggerCount;
- UINT8 Reserved[3];
- UINT32 TriggerIdentifierArrayOffset;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 TriggerCount;
+ UINT8 Reserved[3];
+ UINT32 TriggerIdentifierArrayOffset;
} EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER;
///
/// PDTT Revision (as defined in ACPI 6.2 spec.)
///
-#define EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00
+#define EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00
///
/// PDTT Platform Communication Channel Identifier Structure
///
typedef struct {
- UINT16 SubChannelIdentifer:8;
- UINT16 Runtime:1;
- UINT16 WaitForCompletion:1;
- UINT16 Reserved:6;
+ UINT16 SubChannelIdentifer : 8;
+ UINT16 Runtime : 1;
+ UINT16 WaitForCompletion : 1;
+ UINT16 Reserved : 6;
} EFI_ACPI_6_2_PDTT_PCC_IDENTIFIER;
///
/// PCC Commands Codes used by Platform Debug Trigger Table
///
-#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00
-#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01
+#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00
+#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01
///
/// PPTT Platform Communication Channel
@@ -2527,123 +2550,123 @@ typedef EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6_2_PDTT_
/// Processor Properties Topology Table (PPTT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
} EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;
///
/// PPTT Revision (as defined in ACPI 6.2 spec.)
///
-#define EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x01
+#define EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x01
///
/// PPTT types
///
-#define EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR 0x00
-#define EFI_ACPI_6_2_PPTT_TYPE_CACHE 0x01
-#define EFI_ACPI_6_2_PPTT_TYPE_ID 0x02
+#define EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR 0x00
+#define EFI_ACPI_6_2_PPTT_TYPE_CACHE 0x01
+#define EFI_ACPI_6_2_PPTT_TYPE_ID 0x02
///
/// PPTT Structure Header
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[2];
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
} EFI_ACPI_6_2_PPTT_STRUCTURE_HEADER;
///
/// For PPTT struct processor flags
///
-#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID 0x0
-#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID 0x1
+#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID 0x0
+#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID 0x1
///
/// Processor hierarchy node structure flags
///
typedef struct {
- UINT32 PhysicalPackage:1;
- UINT32 AcpiProcessorIdValid:1;
- UINT32 Reserved:30;
+ UINT32 PhysicalPackage : 1;
+ UINT32 AcpiProcessorIdValid : 1;
+ UINT32 Reserved : 30;
} EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS;
///
/// Processor hierarchy node structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[2];
- EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;
- UINT32 Parent;
- UINT32 AcpiProcessorId;
- UINT32 NumberOfPrivateResources;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;
+ UINT32 Parent;
+ UINT32 AcpiProcessorId;
+ UINT32 NumberOfPrivateResources;
} EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR;
///
/// Cache Type Structure flags
///
typedef struct {
- UINT32 SizePropertyValid:1;
- UINT32 NumberOfSetsValid:1;
- UINT32 AssociativityValid:1;
- UINT32 AllocationTypeValid:1;
- UINT32 CacheTypeValid:1;
- UINT32 WritePolicyValid:1;
- UINT32 LineSizeValid:1;
- UINT32 Reserved:25;
+ UINT32 SizePropertyValid : 1;
+ UINT32 NumberOfSetsValid : 1;
+ UINT32 AssociativityValid : 1;
+ UINT32 AllocationTypeValid : 1;
+ UINT32 CacheTypeValid : 1;
+ UINT32 WritePolicyValid : 1;
+ UINT32 LineSizeValid : 1;
+ UINT32 Reserved : 25;
} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_FLAGS;
///
/// For cache attributes
///
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1
///
/// Cache Type Structure cache attributes
///
typedef struct {
- UINT8 AllocationType:2;
- UINT8 CacheType:2;
- UINT8 WritePolicy:1;
- UINT8 Reserved:3;
+ UINT8 AllocationType : 2;
+ UINT8 CacheType : 2;
+ UINT8 WritePolicy : 1;
+ UINT8 Reserved : 3;
} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES;
///
/// Cache Type Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[2];
- EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_FLAGS Flags;
- UINT32 NextLevelOfCache;
- UINT32 Size;
- UINT32 NumberOfSets;
- UINT8 Associativity;
- EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;
- UINT16 LineSize;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_FLAGS Flags;
+ UINT32 NextLevelOfCache;
+ UINT32 Size;
+ UINT32 NumberOfSets;
+ UINT8 Associativity;
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;
+ UINT16 LineSize;
} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE;
///
/// ID structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[2];
- UINT32 VendorId;
- UINT64 Level1Id;
- UINT64 Level2Id;
- UINT16 MajorRev;
- UINT16 MinorRev;
- UINT16 SpinRev;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 VendorId;
+ UINT64 Level1Id;
+ UINT64 Level2Id;
+ UINT16 MajorRev;
+ UINT16 MinorRev;
+ UINT16 SpinRev;
} EFI_ACPI_6_2_PPTT_STRUCTURE_ID;
//
diff --git a/MdePkg/Include/IndustryStandard/Acpi63.h b/MdePkg/Include/IndustryStandard/Acpi63.h
index 431daac1..75f6ccbc 100644
--- a/MdePkg/Include/IndustryStandard/Acpi63.h
+++ b/MdePkg/Include/IndustryStandard/Acpi63.h
@@ -1,7 +1,7 @@
/** @file
ACPI 6.3 definitions from the ACPI Specification Revision 6.3 Jan, 2019.
- Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
Copyright (c) 2019 - 2020, ARM Ltd. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -21,11 +21,11 @@
/// ACPI 6.3 Generic Address Space definition
///
typedef struct {
- UINT8 AddressSpaceId;
- UINT8 RegisterBitWidth;
- UINT8 RegisterBitOffset;
- UINT8 AccessSize;
- UINT64 Address;
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
} EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE;
//
@@ -61,29 +61,29 @@ typedef struct {
/// Root System Description Pointer Structure
///
typedef struct {
- UINT64 Signature;
- UINT8 Checksum;
- UINT8 OemId[6];
- UINT8 Revision;
- UINT32 RsdtAddress;
- UINT32 Length;
- UINT64 XsdtAddress;
- UINT8 ExtendedChecksum;
- UINT8 Reserved[3];
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
} EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER;
///
/// RSD_PTR Revision (as defined in ACPI 6.3 spec.)
///
-#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.3) says current value is 2
+#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.3) says current value is 2
///
/// Common table header, this prefaces all ACPI tables, including FACS, but
/// excluding the RSD PTR structure
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
+ UINT32 Signature;
+ UINT32 Length;
} EFI_ACPI_6_3_COMMON_HEADER;
//
@@ -95,7 +95,7 @@ typedef struct {
///
/// RSDT Revision (as defined in ACPI 6.3 spec.)
///
-#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
//
// Extended System Description Table
@@ -106,74 +106,74 @@ typedef struct {
///
/// XSDT Revision (as defined in ACPI 6.3 spec.)
///
-#define EFI_ACPI_6_3_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_3_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
///
/// Fixed ACPI Description Table Structure (FADT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 FirmwareCtrl;
- UINT32 Dsdt;
- UINT8 Reserved0;
- UINT8 PreferredPmProfile;
- UINT16 SciInt;
- UINT32 SmiCmd;
- UINT8 AcpiEnable;
- UINT8 AcpiDisable;
- UINT8 S4BiosReq;
- UINT8 PstateCnt;
- UINT32 Pm1aEvtBlk;
- UINT32 Pm1bEvtBlk;
- UINT32 Pm1aCntBlk;
- UINT32 Pm1bCntBlk;
- UINT32 Pm2CntBlk;
- UINT32 PmTmrBlk;
- UINT32 Gpe0Blk;
- UINT32 Gpe1Blk;
- UINT8 Pm1EvtLen;
- UINT8 Pm1CntLen;
- UINT8 Pm2CntLen;
- UINT8 PmTmrLen;
- UINT8 Gpe0BlkLen;
- UINT8 Gpe1BlkLen;
- UINT8 Gpe1Base;
- UINT8 CstCnt;
- UINT16 PLvl2Lat;
- UINT16 PLvl3Lat;
- UINT16 FlushSize;
- UINT16 FlushStride;
- UINT8 DutyOffset;
- UINT8 DutyWidth;
- UINT8 DayAlrm;
- UINT8 MonAlrm;
- UINT8 Century;
- UINT16 IaPcBootArch;
- UINT8 Reserved1;
- UINT32 Flags;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ResetReg;
- UINT8 ResetValue;
- UINT16 ArmBootArch;
- UINT8 MinorVersion;
- UINT64 XFirmwareCtrl;
- UINT64 XDsdt;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
- UINT64 HypervisorVendorIdentity;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT16 ArmBootArch;
+ UINT8 MinorVersion;
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
+ UINT64 HypervisorVendorIdentity;
} EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE;
///
/// FADT Version (as defined in ACPI 6.3 spec.)
///
-#define EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06
+#define EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06
#define EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x03
//
@@ -193,62 +193,62 @@ typedef struct {
// Fixed ACPI Description Table Boot Architecture Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_6_3_LEGACY_DEVICES BIT0
-#define EFI_ACPI_6_3_8042 BIT1
-#define EFI_ACPI_6_3_VGA_NOT_PRESENT BIT2
-#define EFI_ACPI_6_3_MSI_NOT_SUPPORTED BIT3
-#define EFI_ACPI_6_3_PCIE_ASPM_CONTROLS BIT4
-#define EFI_ACPI_6_3_CMOS_RTC_NOT_PRESENT BIT5
+#define EFI_ACPI_6_3_LEGACY_DEVICES BIT0
+#define EFI_ACPI_6_3_8042 BIT1
+#define EFI_ACPI_6_3_VGA_NOT_PRESENT BIT2
+#define EFI_ACPI_6_3_MSI_NOT_SUPPORTED BIT3
+#define EFI_ACPI_6_3_PCIE_ASPM_CONTROLS BIT4
+#define EFI_ACPI_6_3_CMOS_RTC_NOT_PRESENT BIT5
//
// Fixed ACPI Description Table Arm Boot Architecture Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_6_3_ARM_PSCI_COMPLIANT BIT0
-#define EFI_ACPI_6_3_ARM_PSCI_USE_HVC BIT1
+#define EFI_ACPI_6_3_ARM_PSCI_COMPLIANT BIT0
+#define EFI_ACPI_6_3_ARM_PSCI_USE_HVC BIT1
//
// Fixed ACPI Description Table Fixed Feature Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_6_3_WBINVD BIT0
-#define EFI_ACPI_6_3_WBINVD_FLUSH BIT1
-#define EFI_ACPI_6_3_PROC_C1 BIT2
-#define EFI_ACPI_6_3_P_LVL2_UP BIT3
-#define EFI_ACPI_6_3_PWR_BUTTON BIT4
-#define EFI_ACPI_6_3_SLP_BUTTON BIT5
-#define EFI_ACPI_6_3_FIX_RTC BIT6
-#define EFI_ACPI_6_3_RTC_S4 BIT7
-#define EFI_ACPI_6_3_TMR_VAL_EXT BIT8
-#define EFI_ACPI_6_3_DCK_CAP BIT9
-#define EFI_ACPI_6_3_RESET_REG_SUP BIT10
-#define EFI_ACPI_6_3_SEALED_CASE BIT11
-#define EFI_ACPI_6_3_HEADLESS BIT12
-#define EFI_ACPI_6_3_CPU_SW_SLP BIT13
-#define EFI_ACPI_6_3_PCI_EXP_WAK BIT14
-#define EFI_ACPI_6_3_USE_PLATFORM_CLOCK BIT15
-#define EFI_ACPI_6_3_S4_RTC_STS_VALID BIT16
-#define EFI_ACPI_6_3_REMOTE_POWER_ON_CAPABLE BIT17
-#define EFI_ACPI_6_3_FORCE_APIC_CLUSTER_MODEL BIT18
-#define EFI_ACPI_6_3_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
-#define EFI_ACPI_6_3_HW_REDUCED_ACPI BIT20
-#define EFI_ACPI_6_3_LOW_POWER_S0_IDLE_CAPABLE BIT21
+#define EFI_ACPI_6_3_WBINVD BIT0
+#define EFI_ACPI_6_3_WBINVD_FLUSH BIT1
+#define EFI_ACPI_6_3_PROC_C1 BIT2
+#define EFI_ACPI_6_3_P_LVL2_UP BIT3
+#define EFI_ACPI_6_3_PWR_BUTTON BIT4
+#define EFI_ACPI_6_3_SLP_BUTTON BIT5
+#define EFI_ACPI_6_3_FIX_RTC BIT6
+#define EFI_ACPI_6_3_RTC_S4 BIT7
+#define EFI_ACPI_6_3_TMR_VAL_EXT BIT8
+#define EFI_ACPI_6_3_DCK_CAP BIT9
+#define EFI_ACPI_6_3_RESET_REG_SUP BIT10
+#define EFI_ACPI_6_3_SEALED_CASE BIT11
+#define EFI_ACPI_6_3_HEADLESS BIT12
+#define EFI_ACPI_6_3_CPU_SW_SLP BIT13
+#define EFI_ACPI_6_3_PCI_EXP_WAK BIT14
+#define EFI_ACPI_6_3_USE_PLATFORM_CLOCK BIT15
+#define EFI_ACPI_6_3_S4_RTC_STS_VALID BIT16
+#define EFI_ACPI_6_3_REMOTE_POWER_ON_CAPABLE BIT17
+#define EFI_ACPI_6_3_FORCE_APIC_CLUSTER_MODEL BIT18
+#define EFI_ACPI_6_3_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+#define EFI_ACPI_6_3_HW_REDUCED_ACPI BIT20
+#define EFI_ACPI_6_3_LOW_POWER_S0_IDLE_CAPABLE BIT21
///
/// Firmware ACPI Control Structure
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
- UINT32 HardwareSignature;
- UINT32 FirmwareWakingVector;
- UINT32 GlobalLock;
- UINT32 Flags;
- UINT64 XFirmwareWakingVector;
- UINT8 Version;
- UINT8 Reserved0[3];
- UINT32 OspmFlags;
- UINT8 Reserved1[24];
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved0[3];
+ UINT32 OspmFlags;
+ UINT8 Reserved1[24];
} EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE;
///
@@ -260,14 +260,14 @@ typedef struct {
/// Firmware Control Structure Feature Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_6_3_S4BIOS_F BIT0
-#define EFI_ACPI_6_3_64BIT_WAKE_SUPPORTED_F BIT1
+#define EFI_ACPI_6_3_S4BIOS_F BIT0
+#define EFI_ACPI_6_3_64BIT_WAKE_SUPPORTED_F BIT1
///
/// OSPM Enabled Firmware Control Structure Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_6_3_OSPM_64BIT_WAKE_F BIT0
+#define EFI_ACPI_6_3_OSPM_64BIT_WAKE_F BIT0
//
// Differentiated System Description Table,
@@ -276,29 +276,29 @@ typedef struct {
// no definition needed as they are common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
//
-#define EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
-#define EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
///
/// Multiple APIC Description Table header definition. The rest of the table
/// must be defined in a platform specific manner.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 LocalApicAddress;
- UINT32 Flags;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
} EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
///
/// MADT Revision (as defined in ACPI 6.3 spec.)
///
-#define EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x05
+#define EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x05
///
/// Multiple APIC Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_6_3_PCAT_COMPAT BIT0
+#define EFI_ACPI_6_3_PCAT_COMPAT BIT0
//
// Multiple APIC Description Table APIC structure types
@@ -330,11 +330,11 @@ typedef struct {
/// Processor Local APIC Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorUid;
- UINT8 ApicId;
- UINT32 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT8 ApicId;
+ UINT32 Flags;
} EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE;
///
@@ -347,41 +347,41 @@ typedef struct {
/// IO APIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 IoApicAddress;
- UINT32 GlobalSystemInterruptBase;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
} EFI_ACPI_6_3_IO_APIC_STRUCTURE;
///
/// Interrupt Source Override Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Bus;
- UINT8 Source;
- UINT32 GlobalSystemInterrupt;
- UINT16 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
} EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
///
/// Platform Interrupt Sources Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT8 InterruptType;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT8 IoSapicVector;
- UINT32 GlobalSystemInterrupt;
- UINT32 PlatformInterruptSourceFlags;
- UINT8 CpeiProcessorOverride;
- UINT8 Reserved[31];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
} EFI_ACPI_6_3_PLATFORM_INTERRUPT_APIC_STRUCTURE;
//
@@ -395,43 +395,43 @@ typedef struct {
/// Non-Maskable Interrupt Source Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT32 GlobalSystemInterrupt;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
} EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
///
/// Local APIC NMI Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorUid;
- UINT16 Flags;
- UINT8 LocalApicLint;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
} EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE;
///
/// Local APIC Address Override Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT64 LocalApicAddress;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
} EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
///
/// IO SAPIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 GlobalSystemInterruptBase;
- UINT64 IoSapicAddress;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
} EFI_ACPI_6_3_IO_SAPIC_STRUCTURE;
///
@@ -439,170 +439,170 @@ typedef struct {
/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT8 LocalSapicId;
- UINT8 LocalSapicEid;
- UINT8 Reserved[3];
- UINT32 Flags;
- UINT32 ACPIProcessorUIDValue;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
} EFI_ACPI_6_3_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
///
/// Platform Interrupt Sources Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT8 InterruptType;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT8 IoSapicVector;
- UINT32 GlobalSystemInterrupt;
- UINT32 PlatformInterruptSourceFlags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
} EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
///
/// Platform Interrupt Source Flags.
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_6_3_CPEI_PROCESSOR_OVERRIDE BIT0
+#define EFI_ACPI_6_3_CPEI_PROCESSOR_OVERRIDE BIT0
///
/// Processor Local x2APIC Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[2];
- UINT32 X2ApicId;
- UINT32 Flags;
- UINT32 AcpiProcessorUid;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 AcpiProcessorUid;
} EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
///
/// Local x2APIC NMI Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT32 AcpiProcessorUid;
- UINT8 LocalX2ApicLint;
- UINT8 Reserved[3];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 AcpiProcessorUid;
+ UINT8 LocalX2ApicLint;
+ UINT8 Reserved[3];
} EFI_ACPI_6_3_LOCAL_X2APIC_NMI_STRUCTURE;
///
/// GIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT32 CPUInterfaceNumber;
- UINT32 AcpiProcessorUid;
- UINT32 Flags;
- UINT32 ParkingProtocolVersion;
- UINT32 PerformanceInterruptGsiv;
- UINT64 ParkedAddress;
- UINT64 PhysicalBaseAddress;
- UINT64 GICV;
- UINT64 GICH;
- UINT32 VGICMaintenanceInterrupt;
- UINT64 GICRBaseAddress;
- UINT64 MPIDR;
- UINT8 ProcessorPowerEfficiencyClass;
- UINT8 Reserved2;
- UINT16 SpeOverflowInterrupt;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 CPUInterfaceNumber;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ParkingProtocolVersion;
+ UINT32 PerformanceInterruptGsiv;
+ UINT64 ParkedAddress;
+ UINT64 PhysicalBaseAddress;
+ UINT64 GICV;
+ UINT64 GICH;
+ UINT32 VGICMaintenanceInterrupt;
+ UINT64 GICRBaseAddress;
+ UINT64 MPIDR;
+ UINT8 ProcessorPowerEfficiencyClass;
+ UINT8 Reserved2;
+ UINT16 SpeOverflowInterrupt;
} EFI_ACPI_6_3_GIC_STRUCTURE;
///
/// GIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_3_GIC_ENABLED BIT0
-#define EFI_ACPI_6_3_PERFORMANCE_INTERRUPT_MODEL BIT1
-#define EFI_ACPI_6_3_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2
+#define EFI_ACPI_6_3_GIC_ENABLED BIT0
+#define EFI_ACPI_6_3_PERFORMANCE_INTERRUPT_MODEL BIT1
+#define EFI_ACPI_6_3_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2
///
/// GIC Distributor Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved1;
- UINT32 GicId;
- UINT64 PhysicalBaseAddress;
- UINT32 SystemVectorBase;
- UINT8 GicVersion;
- UINT8 Reserved2[3];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 SystemVectorBase;
+ UINT8 GicVersion;
+ UINT8 Reserved2[3];
} EFI_ACPI_6_3_GIC_DISTRIBUTOR_STRUCTURE;
///
/// GIC Version
///
-#define EFI_ACPI_6_3_GIC_V1 0x01
-#define EFI_ACPI_6_3_GIC_V2 0x02
-#define EFI_ACPI_6_3_GIC_V3 0x03
-#define EFI_ACPI_6_3_GIC_V4 0x04
+#define EFI_ACPI_6_3_GIC_V1 0x01
+#define EFI_ACPI_6_3_GIC_V2 0x02
+#define EFI_ACPI_6_3_GIC_V3 0x03
+#define EFI_ACPI_6_3_GIC_V4 0x04
///
/// GIC MSI Frame Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved1;
- UINT32 GicMsiFrameId;
- UINT64 PhysicalBaseAddress;
- UINT32 Flags;
- UINT16 SPICount;
- UINT16 SPIBase;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicMsiFrameId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Flags;
+ UINT16 SPICount;
+ UINT16 SPIBase;
} EFI_ACPI_6_3_GIC_MSI_FRAME_STRUCTURE;
///
/// GIC MSI Frame Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_3_SPI_COUNT_BASE_SELECT BIT0
+#define EFI_ACPI_6_3_SPI_COUNT_BASE_SELECT BIT0
///
/// GICR Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT64 DiscoveryRangeBaseAddress;
- UINT32 DiscoveryRangeLength;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 DiscoveryRangeBaseAddress;
+ UINT32 DiscoveryRangeLength;
} EFI_ACPI_6_3_GICR_STRUCTURE;
///
/// GIC Interrupt Translation Service Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT32 GicItsId;
- UINT64 PhysicalBaseAddress;
- UINT32 Reserved2;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 GicItsId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Reserved2;
} EFI_ACPI_6_3_GIC_ITS_STRUCTURE;
///
/// Smart Battery Description Table (SBST)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 WarningEnergyLevel;
- UINT32 LowEnergyLevel;
- UINT32 CriticalEnergyLevel;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
} EFI_ACPI_6_3_SMART_BATTERY_DESCRIPTION_TABLE;
///
/// SBST Version (as defined in ACPI 6.3 spec.)
///
-#define EFI_ACPI_6_3_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_3_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
///
/// Embedded Controller Boot Resources Table (ECDT)
@@ -610,11 +610,11 @@ typedef struct {
/// a fully qualified reference to the name space object.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE EcControl;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE EcData;
- UINT32 Uid;
- UINT8 GpeBit;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
} EFI_ACPI_6_3_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
///
@@ -627,9 +627,9 @@ typedef struct {
/// must be defined in a platform specific manner.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Reserved1; ///< Must be set to 1
- UINT64 Reserved2;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; ///< Must be set to 1
+ UINT64 Reserved2;
} EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
///
@@ -653,85 +653,85 @@ typedef struct {
/// Processor Local APIC/SAPIC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 ProximityDomain7To0;
- UINT8 ApicId;
- UINT32 Flags;
- UINT8 LocalSapicEid;
- UINT8 ProximityDomain31To8[3];
- UINT32 ClockDomain;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT32 ClockDomain;
} EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
///
/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+#define EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
///
/// Memory Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 ProximityDomain;
- UINT16 Reserved1;
- UINT32 AddressBaseLow;
- UINT32 AddressBaseHigh;
- UINT32 LengthLow;
- UINT32 LengthHigh;
- UINT32 Reserved2;
- UINT32 Flags;
- UINT64 Reserved3;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
} EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE;
//
// Memory Flags. All other bits are reserved and must be 0.
//
-#define EFI_ACPI_6_3_MEMORY_ENABLED (1 << 0)
-#define EFI_ACPI_6_3_MEMORY_HOT_PLUGGABLE (1 << 1)
-#define EFI_ACPI_6_3_MEMORY_NONVOLATILE (1 << 2)
+#define EFI_ACPI_6_3_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_6_3_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_6_3_MEMORY_NONVOLATILE (1 << 2)
///
/// Processor Local x2APIC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved1[2];
- UINT32 ProximityDomain;
- UINT32 X2ApicId;
- UINT32 Flags;
- UINT32 ClockDomain;
- UINT8 Reserved2[4];
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1[2];
+ UINT32 ProximityDomain;
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+ UINT8 Reserved2[4];
} EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
///
/// GICC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 ProximityDomain;
- UINT32 AcpiProcessorUid;
- UINT32 Flags;
- UINT32 ClockDomain;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ClockDomain;
} EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE;
///
/// GICC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_3_GICC_ENABLED (1 << 0)
+#define EFI_ACPI_6_3_GICC_ENABLED (1 << 0)
///
/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 ProximityDomain;
- UINT8 Reserved[2];
- UINT32 ItsId;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT8 Reserved[2];
+ UINT32 ItsId;
} EFI_ACPI_6_3_GIC_ITS_AFFINITY_STRUCTURE;
//
@@ -739,59 +739,59 @@ typedef struct {
// All other values between 0x02 an 0xFF are reserved and
// will be ignored by OSPM.
//
-#define EFI_ACPI_6_3_ACPI_DEVICE_HANDLE 0x00
-#define EFI_ACPI_6_3_PCI_DEVICE_HANDLE 0x01
+#define EFI_ACPI_6_3_ACPI_DEVICE_HANDLE 0x00
+#define EFI_ACPI_6_3_PCI_DEVICE_HANDLE 0x01
///
/// Device Handle - ACPI
///
typedef struct {
- UINT64 AcpiHid;
- UINT32 AcpiUid;
- UINT8 Reserved[4];
+ UINT64 AcpiHid;
+ UINT32 AcpiUid;
+ UINT8 Reserved[4];
} EFI_ACPI_6_3_DEVICE_HANDLE_ACPI;
///
/// Device Handle - PCI
///
typedef struct {
- UINT16 PciSegment;
- UINT16 PciBdfNumber;
- UINT8 Reserved[12];
+ UINT16 PciSegment;
+ UINT16 PciBdfNumber;
+ UINT8 Reserved[12];
} EFI_ACPI_6_3_DEVICE_HANDLE_PCI;
///
/// Generic Initiator Affinity Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved1;
- UINT8 DeviceHandleType;
- UINT32 ProximityDomain;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1;
+ UINT8 DeviceHandleType;
+ UINT32 ProximityDomain;
union {
- EFI_ACPI_6_3_DEVICE_HANDLE_ACPI Acpi;
- EFI_ACPI_6_3_DEVICE_HANDLE_PCI Pci;
+ EFI_ACPI_6_3_DEVICE_HANDLE_ACPI Acpi;
+ EFI_ACPI_6_3_DEVICE_HANDLE_PCI Pci;
} DeviceHandle;
- UINT32 Flags;
- UINT8 Reserved2[4];
+ UINT32 Flags;
+ UINT8 Reserved2[4];
} EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY_STRUCTURE;
///
/// Generic Initiator Affinity Structure Flags. All other bits are reserved
/// and must be 0.
///
-#define EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ENABLED (1 << 0)
+#define EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ENABLED (1 << 0)
///
/// System Locality Distance Information Table (SLIT).
/// The rest of the table is a matrix.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 NumberOfSystemLocalities;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
} EFI_ACPI_6_3_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
///
@@ -803,14 +803,14 @@ typedef struct {
/// Corrected Platform Error Polling Table (CPEP)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 Reserved[8];
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[8];
} EFI_ACPI_6_3_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
///
/// CPEP Version (as defined in ACPI 6.3 spec.)
///
-#define EFI_ACPI_6_3_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+#define EFI_ACPI_6_3_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
//
// CPEP processor structure types.
@@ -821,66 +821,66 @@ typedef struct {
/// Corrected Platform Error Polling Processor Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT32 PollingInterval;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT32 PollingInterval;
} EFI_ACPI_6_3_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
///
/// Maximum System Characteristics Table (MSCT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 OffsetProxDomInfo;
- UINT32 MaximumNumberOfProximityDomains;
- UINT32 MaximumNumberOfClockDomains;
- UINT64 MaximumPhysicalAddress;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 OffsetProxDomInfo;
+ UINT32 MaximumNumberOfProximityDomains;
+ UINT32 MaximumNumberOfClockDomains;
+ UINT64 MaximumPhysicalAddress;
} EFI_ACPI_6_3_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
///
/// MSCT Version (as defined in ACPI 6.3 spec.)
///
-#define EFI_ACPI_6_3_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+#define EFI_ACPI_6_3_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
///
/// Maximum Proximity Domain Information Structure Definition
///
typedef struct {
- UINT8 Revision;
- UINT8 Length;
- UINT32 ProximityDomainRangeLow;
- UINT32 ProximityDomainRangeHigh;
- UINT32 MaximumProcessorCapacity;
- UINT64 MaximumMemoryCapacity;
+ UINT8 Revision;
+ UINT8 Length;
+ UINT32 ProximityDomainRangeLow;
+ UINT32 ProximityDomainRangeHigh;
+ UINT32 MaximumProcessorCapacity;
+ UINT64 MaximumMemoryCapacity;
} EFI_ACPI_6_3_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
///
/// ACPI RAS Feature Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 PlatformCommunicationChannelIdentifier[12];
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier[12];
} EFI_ACPI_6_3_RAS_FEATURE_TABLE;
///
/// RASF Version (as defined in ACPI 6.3 spec.)
///
-#define EFI_ACPI_6_3_RAS_FEATURE_TABLE_REVISION 0x01
+#define EFI_ACPI_6_3_RAS_FEATURE_TABLE_REVISION 0x01
///
/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
///
typedef struct {
- UINT32 Signature;
- UINT16 Command;
- UINT16 Status;
- UINT16 Version;
- UINT8 RASCapabilities[16];
- UINT8 SetRASCapabilities[16];
- UINT16 NumberOfRASFParameterBlocks;
- UINT32 SetRASCapabilitiesStatus;
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT16 Version;
+ UINT8 RASCapabilities[16];
+ UINT8 SetRASCapabilities[16];
+ UINT16 NumberOfRASFParameterBlocks;
+ UINT32 SetRASCapabilitiesStatus;
} EFI_ACPI_6_3_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
///
@@ -891,62 +891,62 @@ typedef struct {
///
/// ACPI RASF Platform RAS Capabilities
///
-#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0
-#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1
-#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2
-#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3
-#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4
///
/// ACPI RASF Parameter Block structure for PATROL_SCRUB
///
typedef struct {
- UINT16 Type;
- UINT16 Version;
- UINT16 Length;
- UINT16 PatrolScrubCommand;
- UINT64 RequestedAddressRange[2];
- UINT64 ActualAddressRange[2];
- UINT16 Flags;
- UINT8 RequestedSpeed;
+ UINT16 Type;
+ UINT16 Version;
+ UINT16 Length;
+ UINT16 PatrolScrubCommand;
+ UINT64 RequestedAddressRange[2];
+ UINT64 ActualAddressRange[2];
+ UINT16 Flags;
+ UINT8 RequestedSpeed;
} EFI_ACPI_6_3_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
///
/// ACPI RASF Patrol Scrub command
///
-#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
-#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
-#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
+#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
+#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
+#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
///
/// Memory Power State Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 PlatformCommunicationChannelIdentifier;
- UINT8 Reserved[3];
-// Memory Power Node Structure
-// Memory Power State Characteristics
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier;
+ UINT8 Reserved[3];
+ // Memory Power Node Structure
+ // Memory Power State Characteristics
} EFI_ACPI_6_3_MEMORY_POWER_STATUS_TABLE;
///
/// MPST Version (as defined in ACPI 6.3 spec.)
///
-#define EFI_ACPI_6_3_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+#define EFI_ACPI_6_3_MEMORY_POWER_STATE_TABLE_REVISION 0x01
///
/// MPST Platform Communication Channel Shared Memory Region definition.
///
typedef struct {
- UINT32 Signature;
- UINT16 Command;
- UINT16 Status;
- UINT32 MemoryPowerCommandRegister;
- UINT32 MemoryPowerStatusRegister;
- UINT32 PowerStateId;
- UINT32 MemoryPowerNodeId;
- UINT64 MemoryEnergyConsumed;
- UINT64 ExpectedAveragePowerComsuned;
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT32 MemoryPowerCommandRegister;
+ UINT32 MemoryPowerStatusRegister;
+ UINT32 PowerStateId;
+ UINT32 MemoryPowerNodeId;
+ UINT64 MemoryEnergyConsumed;
+ UINT64 ExpectedAveragePowerComsuned;
} EFI_ACPI_6_3_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
///
@@ -957,186 +957,186 @@ typedef struct {
///
/// ACPI MPST Memory Power command
///
-#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
-#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
-#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
-#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
///
/// MPST Memory Power Node Table
///
typedef struct {
- UINT8 PowerStateValue;
- UINT8 PowerStateInformationIndex;
+ UINT8 PowerStateValue;
+ UINT8 PowerStateInformationIndex;
} EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE;
typedef struct {
- UINT8 Flag;
- UINT8 Reserved;
- UINT16 MemoryPowerNodeId;
- UINT32 Length;
- UINT64 AddressBase;
- UINT64 AddressLength;
- UINT32 NumberOfPowerStates;
- UINT32 NumberOfPhysicalComponents;
-//EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
-//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+ UINT8 Flag;
+ UINT8 Reserved;
+ UINT16 MemoryPowerNodeId;
+ UINT32 Length;
+ UINT64 AddressBase;
+ UINT64 AddressLength;
+ UINT32 NumberOfPowerStates;
+ UINT32 NumberOfPhysicalComponents;
+ // EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
} EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE;
-#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
-#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
-#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
typedef struct {
- UINT16 MemoryPowerNodeCount;
- UINT8 Reserved[2];
+ UINT16 MemoryPowerNodeCount;
+ UINT8 Reserved[2];
} EFI_ACPI_6_3_MPST_MEMORY_POWER_NODE_TABLE;
///
/// MPST Memory Power State Characteristics Table
///
typedef struct {
- UINT8 PowerStateStructureID;
- UINT8 Flag;
- UINT16 Reserved;
- UINT32 AveragePowerConsumedInMPS0;
- UINT32 RelativePowerSavingToMPS0;
- UINT64 ExitLatencyToMPS0;
+ UINT8 PowerStateStructureID;
+ UINT8 Flag;
+ UINT16 Reserved;
+ UINT32 AveragePowerConsumedInMPS0;
+ UINT32 RelativePowerSavingToMPS0;
+ UINT64 ExitLatencyToMPS0;
} EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
-#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
-#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
-#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
typedef struct {
- UINT16 MemoryPowerStateCharacteristicsCount;
- UINT8 Reserved[2];
+ UINT16 MemoryPowerStateCharacteristicsCount;
+ UINT8 Reserved[2];
} EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
///
/// Memory Topology Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
} EFI_ACPI_6_3_MEMORY_TOPOLOGY_TABLE;
///
/// PMTT Version (as defined in ACPI 6.3 spec.)
///
-#define EFI_ACPI_6_3_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
+#define EFI_ACPI_6_3_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
///
/// Common Memory Aggregator Device Structure.
///
typedef struct {
- UINT8 Type;
- UINT8 Reserved;
- UINT16 Length;
- UINT16 Flags;
- UINT16 Reserved1;
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16 Length;
+ UINT16 Flags;
+ UINT16 Reserved1;
} EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// Memory Aggregator Device Type
///
-#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0
-#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
-#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2
+#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0
+#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
+#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2
///
/// Socket Memory Aggregator Device Structure.
///
typedef struct {
- EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
- UINT16 SocketIdentifier;
- UINT16 Reserved;
-//EFI_ACPI_6_3_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];
+ EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 SocketIdentifier;
+ UINT16 Reserved;
+ // EFI_ACPI_6_3_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];
} EFI_ACPI_6_3_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// MemoryController Memory Aggregator Device Structure.
///
typedef struct {
- EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
- UINT32 ReadLatency;
- UINT32 WriteLatency;
- UINT32 ReadBandwidth;
- UINT32 WriteBandwidth;
- UINT16 OptimalAccessUnit;
- UINT16 OptimalAccessAlignment;
- UINT16 Reserved;
- UINT16 NumberOfProximityDomains;
-//UINT32 ProximityDomain[NumberOfProximityDomains];
-//EFI_ACPI_6_3_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];
+ EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT32 ReadLatency;
+ UINT32 WriteLatency;
+ UINT32 ReadBandwidth;
+ UINT32 WriteBandwidth;
+ UINT16 OptimalAccessUnit;
+ UINT16 OptimalAccessAlignment;
+ UINT16 Reserved;
+ UINT16 NumberOfProximityDomains;
+ // UINT32 ProximityDomain[NumberOfProximityDomains];
+ // EFI_ACPI_6_3_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];
} EFI_ACPI_6_3_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// DIMM Memory Aggregator Device Structure.
///
typedef struct {
- EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
- UINT16 PhysicalComponentIdentifier;
- UINT16 Reserved;
- UINT32 SizeOfDimm;
- UINT32 SmbiosHandle;
+ EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 PhysicalComponentIdentifier;
+ UINT16 Reserved;
+ UINT32 SizeOfDimm;
+ UINT32 SmbiosHandle;
} EFI_ACPI_6_3_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
///
/// Boot Graphics Resource Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
///
/// 2-bytes (16 bit) version ID. This value must be 1.
///
- UINT16 Version;
+ UINT16 Version;
///
/// 1-byte status field indicating current status about the table.
/// Bits[7:1] = Reserved (must be zero)
/// Bit [0] = Valid. A one indicates the boot image graphic is valid.
///
- UINT8 Status;
+ UINT8 Status;
///
/// 1-byte enumerated type field indicating format of the image.
/// 0 = Bitmap
/// 1 - 255 Reserved (for future use)
///
- UINT8 ImageType;
+ UINT8 ImageType;
///
/// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
/// of the image bitmap.
///
- UINT64 ImageAddress;
+ UINT64 ImageAddress;
///
/// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
/// (X, Y) display offset of the top left corner of the boot image.
/// The top left corner of the display is at offset (0, 0).
///
- UINT32 ImageOffsetX;
+ UINT32 ImageOffsetX;
///
/// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
/// (X, Y) display offset of the top left corner of the boot image.
/// The top left corner of the display is at offset (0, 0).
///
- UINT32 ImageOffsetY;
+ UINT32 ImageOffsetY;
} EFI_ACPI_6_3_BOOT_GRAPHICS_RESOURCE_TABLE;
///
/// BGRT Revision
///
-#define EFI_ACPI_6_3_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+#define EFI_ACPI_6_3_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
///
/// BGRT Version
///
-#define EFI_ACPI_6_3_BGRT_VERSION 0x01
+#define EFI_ACPI_6_3_BGRT_VERSION 0x01
///
/// BGRT Status
///
-#define EFI_ACPI_6_3_BGRT_STATUS_NOT_DISPLAYED 0x00
-#define EFI_ACPI_6_3_BGRT_STATUS_DISPLAYED 0x01
+#define EFI_ACPI_6_3_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_6_3_BGRT_STATUS_DISPLAYED 0x01
///
/// BGRT Image Type
@@ -1146,26 +1146,26 @@ typedef struct {
///
/// FPDT Version (as defined in ACPI 6.3 spec.)
///
-#define EFI_ACPI_6_3_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+#define EFI_ACPI_6_3_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
///
/// FPDT Performance Record Types
///
-#define EFI_ACPI_6_3_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
-#define EFI_ACPI_6_3_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
+#define EFI_ACPI_6_3_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
+#define EFI_ACPI_6_3_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
///
/// FPDT Performance Record Revision
///
-#define EFI_ACPI_6_3_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
-#define EFI_ACPI_6_3_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+#define EFI_ACPI_6_3_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
+#define EFI_ACPI_6_3_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
///
/// FPDT Runtime Performance Record Types
///
-#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
-#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
-#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
///
/// FPDT Runtime Performance Record Revision
@@ -1178,77 +1178,77 @@ typedef struct {
/// FPDT Performance Record header
///
typedef struct {
- UINT16 Type;
- UINT8 Length;
- UINT8 Revision;
+ UINT16 Type;
+ UINT8 Length;
+ UINT8 Revision;
} EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER;
///
/// FPDT Performance Table header
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
+ UINT32 Signature;
+ UINT32 Length;
} EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER;
///
/// FPDT Firmware Basic Boot Performance Pointer Record Structure
///
typedef struct {
- EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
///
/// 64-bit processor-relative physical address of the Basic Boot Performance Table.
///
- UINT64 BootPerformanceTablePointer;
+ UINT64 BootPerformanceTablePointer;
} EFI_ACPI_6_3_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
///
/// FPDT S3 Performance Table Pointer Record Structure
///
typedef struct {
- EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
///
/// 64-bit processor-relative physical address of the S3 Performance Table.
///
- UINT64 S3PerformanceTablePointer;
+ UINT64 S3PerformanceTablePointer;
} EFI_ACPI_6_3_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
///
/// FPDT Firmware Basic Boot Performance Record Structure
///
typedef struct {
- EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
///
/// Timer value logged at the beginning of firmware image execution.
/// This may not always be zero or near zero.
///
- UINT64 ResetEnd;
+ UINT64 ResetEnd;
///
/// Timer value logged just prior to loading the OS boot loader into memory.
/// For non-UEFI compatible boots, this field must be zero.
///
- UINT64 OsLoaderLoadImageStart;
+ UINT64 OsLoaderLoadImageStart;
///
/// Timer value logged just prior to launching the previously loaded OS boot loader image.
/// For non-UEFI compatible boots, the timer value logged will be just prior
/// to the INT 19h handler invocation.
///
- UINT64 OsLoaderStartImageStart;
+ UINT64 OsLoaderStartImageStart;
///
/// Timer value logged at the point when the OS loader calls the
/// ExitBootServices function for UEFI compatible firmware.
/// For non-UEFI compatible boots, this field must be zero.
///
- UINT64 ExitBootServicesEntry;
+ UINT64 ExitBootServicesEntry;
///
/// Timer value logged at the point just prior towhen the OS loader gaining
/// control back from calls the ExitBootServices function for UEFI compatible firmware.
/// For non-UEFI compatible boots, this field must be zero.
///
- UINT64 ExitBootServicesExit;
+ UINT64 ExitBootServicesExit;
} EFI_ACPI_6_3_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
///
@@ -1260,7 +1260,7 @@ typedef struct {
// FPDT Firmware Basic Boot Performance Table
//
typedef struct {
- EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER Header;
//
// one or more Performance Records.
//
@@ -1275,7 +1275,7 @@ typedef struct {
// FPDT Firmware S3 Boot Performance Table
//
typedef struct {
- EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER Header;
//
// one or more Performance Records.
//
@@ -1285,147 +1285,147 @@ typedef struct {
/// FPDT Basic S3 Resume Performance Record
///
typedef struct {
- EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;
///
/// A count of the number of S3 resume cycles since the last full boot sequence.
///
- UINT32 ResumeCount;
+ UINT32 ResumeCount;
///
/// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
/// OS waking vector. Only the most recent resume cycle's time is retained.
///
- UINT64 FullResume;
+ UINT64 FullResume;
///
/// Average timer value of all resume cycles logged since the last full boot
/// sequence, including the most recent resume. Note that the entire log of
/// timer values does not need to be retained in order to calculate this average.
///
- UINT64 AverageResume;
+ UINT64 AverageResume;
} EFI_ACPI_6_3_FPDT_S3_RESUME_RECORD;
///
/// FPDT Basic S3 Suspend Performance Record
///
typedef struct {
- EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;
///
/// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
/// Only the most recent suspend cycle's timer value is retained.
///
- UINT64 SuspendStart;
+ UINT64 SuspendStart;
///
/// Timer value recorded at the final firmware write to SLP_TYP (or other
/// mechanism) used to trigger hardware entry to S3.
/// Only the most recent suspend cycle's timer value is retained.
///
- UINT64 SuspendEnd;
+ UINT64 SuspendEnd;
} EFI_ACPI_6_3_FPDT_S3_SUSPEND_RECORD;
///
/// Firmware Performance Record Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
} EFI_ACPI_6_3_FIRMWARE_PERFORMANCE_RECORD_TABLE;
///
/// Generic Timer Description Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 CntControlBasePhysicalAddress;
- UINT32 Reserved;
- UINT32 SecurePL1TimerGSIV;
- UINT32 SecurePL1TimerFlags;
- UINT32 NonSecurePL1TimerGSIV;
- UINT32 NonSecurePL1TimerFlags;
- UINT32 VirtualTimerGSIV;
- UINT32 VirtualTimerFlags;
- UINT32 NonSecurePL2TimerGSIV;
- UINT32 NonSecurePL2TimerFlags;
- UINT64 CntReadBasePhysicalAddress;
- UINT32 PlatformTimerCount;
- UINT32 PlatformTimerOffset;
- UINT32 VirtualPL2TimerGSIV;
- UINT32 VirtualPL2TimerFlags;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 CntControlBasePhysicalAddress;
+ UINT32 Reserved;
+ UINT32 SecurePL1TimerGSIV;
+ UINT32 SecurePL1TimerFlags;
+ UINT32 NonSecurePL1TimerGSIV;
+ UINT32 NonSecurePL1TimerFlags;
+ UINT32 VirtualTimerGSIV;
+ UINT32 VirtualTimerFlags;
+ UINT32 NonSecurePL2TimerGSIV;
+ UINT32 NonSecurePL2TimerFlags;
+ UINT64 CntReadBasePhysicalAddress;
+ UINT32 PlatformTimerCount;
+ UINT32 PlatformTimerOffset;
+ UINT32 VirtualPL2TimerGSIV;
+ UINT32 VirtualPL2TimerFlags;
} EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE;
///
/// GTDT Version (as defined in ACPI 6.3 spec.)
///
-#define EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x03
+#define EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x03
///
/// Timer Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
-#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
-#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2
+#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2
///
/// Platform Timer Type
///
-#define EFI_ACPI_6_3_GTDT_GT_BLOCK 0
-#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG 1
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK 0
+#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG 1
///
/// GT Block Structure
///
typedef struct {
- UINT8 Type;
- UINT16 Length;
- UINT8 Reserved;
- UINT64 CntCtlBase;
- UINT32 GTBlockTimerCount;
- UINT32 GTBlockTimerOffset;
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 CntCtlBase;
+ UINT32 GTBlockTimerCount;
+ UINT32 GTBlockTimerOffset;
} EFI_ACPI_6_3_GTDT_GT_BLOCK_STRUCTURE;
///
/// GT Block Timer Structure
///
typedef struct {
- UINT8 GTFrameNumber;
- UINT8 Reserved[3];
- UINT64 CntBaseX;
- UINT64 CntEL0BaseX;
- UINT32 GTxPhysicalTimerGSIV;
- UINT32 GTxPhysicalTimerFlags;
- UINT32 GTxVirtualTimerGSIV;
- UINT32 GTxVirtualTimerFlags;
- UINT32 GTxCommonFlags;
+ UINT8 GTFrameNumber;
+ UINT8 Reserved[3];
+ UINT64 CntBaseX;
+ UINT64 CntEL0BaseX;
+ UINT32 GTxPhysicalTimerGSIV;
+ UINT32 GTxPhysicalTimerFlags;
+ UINT32 GTxVirtualTimerGSIV;
+ UINT32 GTxVirtualTimerFlags;
+ UINT32 GTxCommonFlags;
} EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_STRUCTURE;
///
/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
-#define EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
///
/// Common Flags Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0
-#define EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1
///
/// SBSA Generic Watchdog Structure
///
typedef struct {
- UINT8 Type;
- UINT16 Length;
- UINT8 Reserved;
- UINT64 RefreshFramePhysicalAddress;
- UINT64 WatchdogControlFramePhysicalAddress;
- UINT32 WatchdogTimerGSIV;
- UINT32 WatchdogTimerFlags;
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 RefreshFramePhysicalAddress;
+ UINT64 WatchdogControlFramePhysicalAddress;
+ UINT32 WatchdogTimerGSIV;
+ UINT32 WatchdogTimerFlags;
} EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;
///
/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0
-#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1
-#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2
+#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2
//
// NVDIMM Firmware Interface Table definition.
@@ -1438,63 +1438,64 @@ typedef struct {
//
// NFIT Version (as defined in ACPI 6.3 spec.)
//
-#define EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
+#define EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
//
// Definition for NFIT Table Structure Types
//
-#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0
-#define EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1
-#define EFI_ACPI_6_3_NFIT_INTERLEAVE_STRUCTURE_TYPE 2
-#define EFI_ACPI_6_3_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3
-#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4
-#define EFI_ACPI_6_3_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5
-#define EFI_ACPI_6_3_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6
+#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0
+#define EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1
+#define EFI_ACPI_6_3_NFIT_INTERLEAVE_STRUCTURE_TYPE 2
+#define EFI_ACPI_6_3_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3
+#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4
+#define EFI_ACPI_6_3_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5
+#define EFI_ACPI_6_3_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6
+#define EFI_ACPI_6_3_NFIT_PLATFORM_CAPABILITIES_STRUCTURE_TYPE 7
//
// Definition for NFIT Structure Header
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
+ UINT16 Type;
+ UINT16 Length;
} EFI_ACPI_6_3_NFIT_STRUCTURE_HEADER;
//
// Definition for System Physical Address Range Structure
//
-#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0
-#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1
-#define EFI_ACPI_6_3_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
-#define EFI_ACPI_6_3_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
-#define EFI_ACPI_6_3_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
-#define EFI_ACPI_6_3_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
-#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
-#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
-#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
-#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
+#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0
+#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1
+#define EFI_ACPI_6_3_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
+#define EFI_ACPI_6_3_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
+#define EFI_ACPI_6_3_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
+#define EFI_ACPI_6_3_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
+#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
+#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
+#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
+#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT16 SPARangeStructureIndex;
- UINT16 Flags;
- UINT32 Reserved_8;
- UINT32 ProximityDomain;
- GUID AddressRangeTypeGUID;
- UINT64 SystemPhysicalAddressRangeBase;
- UINT64 SystemPhysicalAddressRangeLength;
- UINT64 AddressRangeMemoryMappingAttribute;
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 SPARangeStructureIndex;
+ UINT16 Flags;
+ UINT32 Reserved_8;
+ UINT32 ProximityDomain;
+ GUID AddressRangeTypeGUID;
+ UINT64 SystemPhysicalAddressRangeBase;
+ UINT64 SystemPhysicalAddressRangeLength;
+ UINT64 AddressRangeMemoryMappingAttribute;
} EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;
//
// Definition for Memory Device to System Physical Address Range Mapping Structure
//
typedef struct {
- UINT32 DIMMNumber:4;
- UINT32 MemoryChannelNumber:4;
- UINT32 MemoryControllerID:4;
- UINT32 SocketID:4;
- UINT32 NodeControllerID:12;
- UINT32 Reserved_28:4;
+ UINT32 DIMMNumber : 4;
+ UINT32 MemoryChannelNumber : 4;
+ UINT32 MemoryControllerID : 4;
+ UINT32 SocketID : 4;
+ UINT32 NodeControllerID : 12;
+ UINT32 Reserved_28 : 4;
} EFI_ACPI_6_3_NFIT_DEVICE_HANDLE;
#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0
@@ -1505,221 +1506,243 @@ typedef struct {
#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5
#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6
typedef struct {
- UINT16 Type;
- UINT16 Length;
- EFI_ACPI_6_3_NFIT_DEVICE_HANDLE NFITDeviceHandle;
- UINT16 NVDIMMPhysicalID;
- UINT16 NVDIMMRegionID;
- UINT16 SPARangeStructureIndex ;
- UINT16 NVDIMMControlRegionStructureIndex;
- UINT64 NVDIMMRegionSize;
- UINT64 RegionOffset;
- UINT64 NVDIMMPhysicalAddressRegionBase;
- UINT16 InterleaveStructureIndex;
- UINT16 InterleaveWays;
- UINT16 NVDIMMStateFlags;
- UINT16 Reserved_46;
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_3_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NVDIMMPhysicalID;
+ UINT16 NVDIMMRegionID;
+ UINT16 SPARangeStructureIndex;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT64 NVDIMMRegionSize;
+ UINT64 RegionOffset;
+ UINT64 NVDIMMPhysicalAddressRegionBase;
+ UINT16 InterleaveStructureIndex;
+ UINT16 InterleaveWays;
+ UINT16 NVDIMMStateFlags;
+ UINT16 Reserved_46;
} EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;
//
// Definition for Interleave Structure
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT16 InterleaveStructureIndex;
- UINT16 Reserved_6;
- UINT32 NumberOfLines;
- UINT32 LineSize;
-//UINT32 LineOffset[NumberOfLines];
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 InterleaveStructureIndex;
+ UINT16 Reserved_6;
+ UINT32 NumberOfLines;
+ UINT32 LineSize;
+ // UINT32 LineOffset[NumberOfLines];
} EFI_ACPI_6_3_NFIT_INTERLEAVE_STRUCTURE;
//
// Definition for SMBIOS Management Information Structure
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT32 Reserved_4;
-//UINT8 Data[];
+ UINT16 Type;
+ UINT16 Length;
+ UINT32 Reserved_4;
+ // UINT8 Data[];
} EFI_ACPI_6_3_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;
//
// Definition for NVDIMM Control Region Structure
//
-#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0
+#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0
-#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0
+#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT16 NVDIMMControlRegionStructureIndex;
- UINT16 VendorID;
- UINT16 DeviceID;
- UINT16 RevisionID;
- UINT16 SubsystemVendorID;
- UINT16 SubsystemDeviceID;
- UINT16 SubsystemRevisionID;
- UINT8 ValidFields;
- UINT8 ManufacturingLocation;
- UINT16 ManufacturingDate;
- UINT8 Reserved_22[2];
- UINT32 SerialNumber;
- UINT16 RegionFormatInterfaceCode;
- UINT16 NumberOfBlockControlWindows;
- UINT64 SizeOfBlockControlWindow;
- UINT64 CommandRegisterOffsetInBlockControlWindow;
- UINT64 SizeOfCommandRegisterInBlockControlWindows;
- UINT64 StatusRegisterOffsetInBlockControlWindow;
- UINT64 SizeOfStatusRegisterInBlockControlWindows;
- UINT16 NVDIMMControlRegionFlag;
- UINT8 Reserved_74[6];
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT8 ValidFields;
+ UINT8 ManufacturingLocation;
+ UINT16 ManufacturingDate;
+ UINT8 Reserved_22[2];
+ UINT32 SerialNumber;
+ UINT16 RegionFormatInterfaceCode;
+ UINT16 NumberOfBlockControlWindows;
+ UINT64 SizeOfBlockControlWindow;
+ UINT64 CommandRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfCommandRegisterInBlockControlWindows;
+ UINT64 StatusRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfStatusRegisterInBlockControlWindows;
+ UINT16 NVDIMMControlRegionFlag;
+ UINT8 Reserved_74[6];
} EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;
//
// Definition for NVDIMM Block Data Window Region Structure
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT16 NVDIMMControlRegionStructureIndex;
- UINT16 NumberOfBlockDataWindows;
- UINT64 BlockDataWindowStartOffset;
- UINT64 SizeOfBlockDataWindow;
- UINT64 BlockAccessibleMemoryCapacity;
- UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 NumberOfBlockDataWindows;
+ UINT64 BlockDataWindowStartOffset;
+ UINT64 SizeOfBlockDataWindow;
+ UINT64 BlockAccessibleMemoryCapacity;
+ UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;
} EFI_ACPI_6_3_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;
//
// Definition for Flush Hint Address Structure
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
- EFI_ACPI_6_3_NFIT_DEVICE_HANDLE NFITDeviceHandle;
- UINT16 NumberOfFlushHintAddresses;
- UINT8 Reserved_10[6];
-//UINT64 FlushHintAddress[NumberOfFlushHintAddresses];
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_3_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NumberOfFlushHintAddresses;
+ UINT8 Reserved_10[6];
+ // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];
} EFI_ACPI_6_3_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;
+//
+// Definition for Platform Capabilities Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT8 HighestValidCapability;
+ UINT8 Reserved_5[3];
+ UINT32 Capabilities;
+ UINT8 Reserved_12[4];
+} EFI_ACPI_6_3_NFIT_PLATFORM_CAPABILITIES_STRUCTURE;
+
+#define EFI_ACPI_6_3_NFIT_PLATFORM_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT0
+#define EFI_ACPI_6_3_NFIT_PLATFORM_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT1
+#define EFI_ACPI_6_3_NFIT_PLATFORM_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT2
+
///
/// Secure DEVices Table (SDEV)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
} EFI_ACPI_6_3_SECURE_DEVICES_TABLE_HEADER;
///
/// SDEV Revision (as defined in ACPI 6.3 spec.)
///
-#define EFI_ACPI_6_3_SECURE_DEVICES_TABLE_REVISION 0x01
+#define EFI_ACPI_6_3_SECURE_DEVICES_TABLE_REVISION 0x01
///
/// Secure Devcice types
///
-#define EFI_ACPI_6_3_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01
-#define EFI_ACPI_6_3_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00
+#define EFI_ACPI_6_3_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01
+#define EFI_ACPI_6_3_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00
///
/// Secure Devcice flags
///
-#define EFI_ACPI_6_3_SDEV_FLAG_ALLOW_HANDOFF BIT0
+#define EFI_ACPI_6_3_SDEV_FLAG_ALLOW_HANDOFF BIT0
///
/// SDEV Structure Header
///
typedef struct {
- UINT8 Type;
- UINT8 Flags;
- UINT16 Length;
+ UINT8 Type;
+ UINT8 Flags;
+ UINT16 Length;
} EFI_ACPI_6_3_SDEV_STRUCTURE_HEADER;
///
/// PCIe Endpoint Device based Secure Device Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Flags;
- UINT16 Length;
- UINT16 PciSegmentNumber;
- UINT16 StartBusNumber;
- UINT16 PciPathOffset;
- UINT16 PciPathLength;
- UINT16 VendorSpecificDataOffset;
- UINT16 VendorSpecificDataLength;
+ UINT8 Type;
+ UINT8 Flags;
+ UINT16 Length;
+ UINT16 PciSegmentNumber;
+ UINT16 StartBusNumber;
+ UINT16 PciPathOffset;
+ UINT16 PciPathLength;
+ UINT16 VendorSpecificDataOffset;
+ UINT16 VendorSpecificDataLength;
} EFI_ACPI_6_3_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE;
///
/// ACPI_NAMESPACE_DEVICE based Secure Device Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Flags;
- UINT16 Length;
- UINT16 DeviceIdentifierOffset;
- UINT16 DeviceIdentifierLength;
- UINT16 VendorSpecificDataOffset;
- UINT16 VendorSpecificDataLength;
+ UINT8 Type;
+ UINT8 Flags;
+ UINT16 Length;
+ UINT16 DeviceIdentifierOffset;
+ UINT16 DeviceIdentifierLength;
+ UINT16 VendorSpecificDataOffset;
+ UINT16 VendorSpecificDataLength;
} EFI_ACPI_6_3_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE;
///
/// Boot Error Record Table (BERT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 BootErrorRegionLength;
- UINT64 BootErrorRegion;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 BootErrorRegionLength;
+ UINT64 BootErrorRegion;
} EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_HEADER;
///
/// BERT Version (as defined in ACPI 6.3 spec.)
///
-#define EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+#define EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
///
/// Boot Error Region Block Status Definition
///
typedef struct {
- UINT32 UncorrectableErrorValid:1;
- UINT32 CorrectableErrorValid:1;
- UINT32 MultipleUncorrectableErrors:1;
- UINT32 MultipleCorrectableErrors:1;
- UINT32 ErrorDataEntryCount:10;
- UINT32 Reserved:18;
+ UINT32 UncorrectableErrorValid : 1;
+ UINT32 CorrectableErrorValid : 1;
+ UINT32 MultipleUncorrectableErrors : 1;
+ UINT32 MultipleCorrectableErrors : 1;
+ UINT32 ErrorDataEntryCount : 10;
+ UINT32 Reserved : 18;
} EFI_ACPI_6_3_ERROR_BLOCK_STATUS;
///
/// Boot Error Region Definition
///
typedef struct {
- EFI_ACPI_6_3_ERROR_BLOCK_STATUS BlockStatus;
- UINT32 RawDataOffset;
- UINT32 RawDataLength;
- UINT32 DataLength;
- UINT32 ErrorSeverity;
+ EFI_ACPI_6_3_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
} EFI_ACPI_6_3_BOOT_ERROR_REGION_STRUCTURE;
//
// Boot Error Severity types
//
-#define EFI_ACPI_6_3_ERROR_SEVERITY_CORRECTABLE 0x00
+#define EFI_ACPI_6_3_ERROR_SEVERITY_RECOVERABLE 0x00
#define EFI_ACPI_6_3_ERROR_SEVERITY_FATAL 0x01
#define EFI_ACPI_6_3_ERROR_SEVERITY_CORRECTED 0x02
#define EFI_ACPI_6_3_ERROR_SEVERITY_NONE 0x03
+//
+// The term 'Correctable' is no longer being used as an error severity of the
+// reported error since ACPI Specification Version 5.1 Errata B.
+// The below macro is considered as deprecated and should no longer be used.
+//
+#define EFI_ACPI_6_3_ERROR_SEVERITY_CORRECTABLE 0x00
///
/// Generic Error Data Entry Definition
///
typedef struct {
- UINT8 SectionType[16];
- UINT32 ErrorSeverity;
- UINT16 Revision;
- UINT8 ValidationBits;
- UINT8 Flags;
- UINT32 ErrorDataLength;
- UINT8 FruId[16];
- UINT8 FruText[20];
- UINT8 Timestamp[8];
+ UINT8 SectionType[16];
+ UINT32 ErrorSeverity;
+ UINT16 Revision;
+ UINT8 ValidationBits;
+ UINT8 Flags;
+ UINT32 ErrorDataLength;
+ UINT8 FruId[16];
+ UINT8 FruText[20];
+ UINT8 Timestamp[8];
} EFI_ACPI_6_3_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
///
@@ -1731,14 +1754,14 @@ typedef struct {
/// HEST - Hardware Error Source Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 ErrorSourceCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 ErrorSourceCount;
} EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
///
/// HEST Version (as defined in ACPI 6.3 spec.)
///
-#define EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+#define EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
//
// Error Source structure types.
@@ -1756,237 +1779,237 @@ typedef struct {
//
// Error Source structure flags.
//
-#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
-#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
-#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)
+#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
+#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
+#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)
///
/// IA-32 Architecture Machine Check Exception Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT64 GlobalCapabilityInitData;
- UINT64 GlobalControlInitData;
- UINT8 NumberOfHardwareBanks;
- UINT8 Reserved1[7];
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT64 GlobalCapabilityInitData;
+ UINT64 GlobalControlInitData;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[7];
} EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
///
/// IA-32 Architecture Machine Check Bank Structure Definition
///
typedef struct {
- UINT8 BankNumber;
- UINT8 ClearStatusOnInitialization;
- UINT8 StatusDataFormat;
- UINT8 Reserved0;
- UINT32 ControlRegisterMsrAddress;
- UINT64 ControlInitData;
- UINT32 StatusRegisterMsrAddress;
- UINT32 AddressRegisterMsrAddress;
- UINT32 MiscRegisterMsrAddress;
+ UINT8 BankNumber;
+ UINT8 ClearStatusOnInitialization;
+ UINT8 StatusDataFormat;
+ UINT8 Reserved0;
+ UINT32 ControlRegisterMsrAddress;
+ UINT64 ControlInitData;
+ UINT32 StatusRegisterMsrAddress;
+ UINT32 AddressRegisterMsrAddress;
+ UINT32 MiscRegisterMsrAddress;
} EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
///
/// IA-32 Architecture Machine Check Bank Structure MCA data format
///
-#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
-#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
-#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
//
// Hardware Error Notification types. All other values are reserved
//
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_MCE 0x06
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_MCE 0x06
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B
///
/// Hardware Error Notification Configuration Write Enable Structure Definition
///
typedef struct {
- UINT16 Type:1;
- UINT16 PollInterval:1;
- UINT16 SwitchToPollingThresholdValue:1;
- UINT16 SwitchToPollingThresholdWindow:1;
- UINT16 ErrorThresholdValue:1;
- UINT16 ErrorThresholdWindow:1;
- UINT16 Reserved:10;
+ UINT16 Type : 1;
+ UINT16 PollInterval : 1;
+ UINT16 SwitchToPollingThresholdValue : 1;
+ UINT16 SwitchToPollingThresholdWindow : 1;
+ UINT16 ErrorThresholdValue : 1;
+ UINT16 ErrorThresholdWindow : 1;
+ UINT16 Reserved : 10;
} EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
///
/// Hardware Error Notification Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
- UINT32 PollInterval;
- UINT32 Vector;
- UINT32 SwitchToPollingThresholdValue;
- UINT32 SwitchToPollingThresholdWindow;
- UINT32 ErrorThresholdValue;
- UINT32 ErrorThresholdWindow;
+ UINT8 Type;
+ UINT8 Length;
+ EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
+ UINT32 PollInterval;
+ UINT32 Vector;
+ UINT32 SwitchToPollingThresholdValue;
+ UINT32 SwitchToPollingThresholdWindow;
+ UINT32 ErrorThresholdValue;
+ UINT32 ErrorThresholdWindow;
} EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
///
/// IA-32 Architecture Corrected Machine Check Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
- UINT8 NumberOfHardwareBanks;
- UINT8 Reserved1[3];
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
} EFI_ACPI_6_3_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
///
/// IA-32 Architecture NMI Error Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 MaxRawDataLength;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
} EFI_ACPI_6_3_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
///
/// PCI Express Root Port AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
- UINT32 RootErrorCommand;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 RootErrorCommand;
} EFI_ACPI_6_3_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
///
/// PCI Express Device AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
} EFI_ACPI_6_3_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
///
/// PCI Express Bridge AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
- UINT32 SecondaryUncorrectableErrorMask;
- UINT32 SecondaryUncorrectableErrorSeverity;
- UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 SecondaryUncorrectableErrorMask;
+ UINT32 SecondaryUncorrectableErrorSeverity;
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
} EFI_ACPI_6_3_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
///
/// Generic Hardware Error Source Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT16 RelatedSourceId;
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 MaxRawDataLength;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
- EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
- UINT32 ErrorStatusBlockLength;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
} EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
///
/// Generic Hardware Error Source Version 2 Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT16 RelatedSourceId;
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 MaxRawDataLength;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
- EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
- UINT32 ErrorStatusBlockLength;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;
- UINT64 ReadAckPreserve;
- UINT64 ReadAckWrite;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;
+ UINT64 ReadAckPreserve;
+ UINT64 ReadAckWrite;
} EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;
///
/// Generic Error Status Definition
///
typedef struct {
- EFI_ACPI_6_3_ERROR_BLOCK_STATUS BlockStatus;
- UINT32 RawDataOffset;
- UINT32 RawDataLength;
- UINT32 DataLength;
- UINT32 ErrorSeverity;
+ EFI_ACPI_6_3_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
} EFI_ACPI_6_3_GENERIC_ERROR_STATUS_STRUCTURE;
///
@@ -2003,297 +2026,297 @@ typedef struct {
EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
UINT8 NumberOfHardwareBanks;
UINT8 Reserved1[3];
-} EFI_ACPI_6_3_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;;
+} EFI_ACPI_6_3_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;
///
/// HMAT - Heterogeneous Memory Attribute Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 Reserved[4];
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[4];
} EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;
///
/// HMAT Revision (as defined in ACPI 6.3 spec.)
///
-#define EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x02
+#define EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x02
///
/// HMAT types
///
-#define EFI_ACPI_6_3_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES 0x00
-#define EFI_ACPI_6_3_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01
-#define EFI_ACPI_6_3_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02
+#define EFI_ACPI_6_3_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES 0x00
+#define EFI_ACPI_6_3_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01
+#define EFI_ACPI_6_3_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02
///
/// HMAT Structure Header
///
typedef struct {
- UINT16 Type;
- UINT8 Reserved[2];
- UINT32 Length;
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
} EFI_ACPI_6_3_HMAT_STRUCTURE_HEADER;
///
/// Memory Proximity Domain Attributes Structure flags
///
typedef struct {
- UINT16 InitiatorProximityDomainValid:1;
- UINT16 Reserved:15;
+ UINT16 InitiatorProximityDomainValid : 1;
+ UINT16 Reserved : 15;
} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS;
///
/// Memory Proximity Domain Attributes Structure
///
typedef struct {
- UINT16 Type;
- UINT8 Reserved[2];
- UINT32 Length;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS Flags;
- UINT8 Reserved1[2];
- UINT32 InitiatorProximityDomain;
- UINT32 MemoryProximityDomain;
- UINT8 Reserved2[20];
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS Flags;
+ UINT8 Reserved1[2];
+ UINT32 InitiatorProximityDomain;
+ UINT32 MemoryProximityDomain;
+ UINT8 Reserved2[20];
} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES;
///
/// System Locality Latency and Bandwidth Information Structure flags
///
typedef struct {
- UINT8 MemoryHierarchy:4;
- UINT8 Reserved:4;
+ UINT8 MemoryHierarchy : 4;
+ UINT8 Reserved : 4;
} EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS;
///
/// System Locality Latency and Bandwidth Information Structure
///
typedef struct {
- UINT16 Type;
- UINT8 Reserved[2];
- UINT32 Length;
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;
- UINT8 DataType;
- UINT8 Reserved1[2];
- UINT32 NumberOfInitiatorProximityDomains;
- UINT32 NumberOfTargetProximityDomains;
- UINT8 Reserved2[4];
- UINT64 EntryBaseUnit;
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;
+ UINT8 DataType;
+ UINT8 Reserved1[2];
+ UINT32 NumberOfInitiatorProximityDomains;
+ UINT32 NumberOfTargetProximityDomains;
+ UINT8 Reserved2[4];
+ UINT64 EntryBaseUnit;
} EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO;
///
/// Memory Side Cache Information Structure cache attributes
///
typedef struct {
- UINT32 TotalCacheLevels:4;
- UINT32 CacheLevel:4;
- UINT32 CacheAssociativity:4;
- UINT32 WritePolicy:4;
- UINT32 CacheLineSize:16;
+ UINT32 TotalCacheLevels : 4;
+ UINT32 CacheLevel : 4;
+ UINT32 CacheAssociativity : 4;
+ UINT32 WritePolicy : 4;
+ UINT32 CacheLineSize : 16;
} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES;
///
/// Memory Side Cache Information Structure
///
typedef struct {
- UINT16 Type;
- UINT8 Reserved[2];
- UINT32 Length;
- UINT32 MemoryProximityDomain;
- UINT8 Reserved1[4];
- UINT64 MemorySideCacheSize;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;
- UINT8 Reserved2[2];
- UINT16 NumberOfSmbiosHandles;
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ UINT32 MemoryProximityDomain;
+ UINT8 Reserved1[4];
+ UINT64 MemorySideCacheSize;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;
+ UINT8 Reserved2[2];
+ UINT16 NumberOfSmbiosHandles;
} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO;
///
/// ERST - Error Record Serialization Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 SerializationHeaderSize;
- UINT8 Reserved0[4];
- UINT32 InstructionEntryCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 SerializationHeaderSize;
+ UINT8 Reserved0[4];
+ UINT32 InstructionEntryCount;
} EFI_ACPI_6_3_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
///
/// ERST Version (as defined in ACPI 6.3 spec.)
///
-#define EFI_ACPI_6_3_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_3_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
///
/// ERST Serialization Actions
///
-#define EFI_ACPI_6_3_ERST_BEGIN_WRITE_OPERATION 0x00
-#define EFI_ACPI_6_3_ERST_BEGIN_READ_OPERATION 0x01
-#define EFI_ACPI_6_3_ERST_BEGIN_CLEAR_OPERATION 0x02
-#define EFI_ACPI_6_3_ERST_END_OPERATION 0x03
-#define EFI_ACPI_6_3_ERST_SET_RECORD_OFFSET 0x04
-#define EFI_ACPI_6_3_ERST_EXECUTE_OPERATION 0x05
-#define EFI_ACPI_6_3_ERST_CHECK_BUSY_STATUS 0x06
-#define EFI_ACPI_6_3_ERST_GET_COMMAND_STATUS 0x07
-#define EFI_ACPI_6_3_ERST_GET_RECORD_IDENTIFIER 0x08
-#define EFI_ACPI_6_3_ERST_SET_RECORD_IDENTIFIER 0x09
-#define EFI_ACPI_6_3_ERST_GET_RECORD_COUNT 0x0A
-#define EFI_ACPI_6_3_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
-#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
-#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
-#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
-#define EFI_ACPI_6_3_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10
+#define EFI_ACPI_6_3_ERST_BEGIN_WRITE_OPERATION 0x00
+#define EFI_ACPI_6_3_ERST_BEGIN_READ_OPERATION 0x01
+#define EFI_ACPI_6_3_ERST_BEGIN_CLEAR_OPERATION 0x02
+#define EFI_ACPI_6_3_ERST_END_OPERATION 0x03
+#define EFI_ACPI_6_3_ERST_SET_RECORD_OFFSET 0x04
+#define EFI_ACPI_6_3_ERST_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_3_ERST_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_3_ERST_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_3_ERST_GET_RECORD_IDENTIFIER 0x08
+#define EFI_ACPI_6_3_ERST_SET_RECORD_IDENTIFIER 0x09
+#define EFI_ACPI_6_3_ERST_GET_RECORD_COUNT 0x0A
+#define EFI_ACPI_6_3_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
+#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
+#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
+#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
+#define EFI_ACPI_6_3_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10
///
/// ERST Action Command Status
///
-#define EFI_ACPI_6_3_ERST_STATUS_SUCCESS 0x00
-#define EFI_ACPI_6_3_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
-#define EFI_ACPI_6_3_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
-#define EFI_ACPI_6_3_ERST_STATUS_FAILED 0x03
-#define EFI_ACPI_6_3_ERST_STATUS_RECORD_STORE_EMPTY 0x04
-#define EFI_ACPI_6_3_ERST_STATUS_RECORD_NOT_FOUND 0x05
+#define EFI_ACPI_6_3_ERST_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_3_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
+#define EFI_ACPI_6_3_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
+#define EFI_ACPI_6_3_ERST_STATUS_FAILED 0x03
+#define EFI_ACPI_6_3_ERST_STATUS_RECORD_STORE_EMPTY 0x04
+#define EFI_ACPI_6_3_ERST_STATUS_RECORD_NOT_FOUND 0x05
///
/// ERST Serialization Instructions
///
-#define EFI_ACPI_6_3_ERST_READ_REGISTER 0x00
-#define EFI_ACPI_6_3_ERST_READ_REGISTER_VALUE 0x01
-#define EFI_ACPI_6_3_ERST_WRITE_REGISTER 0x02
-#define EFI_ACPI_6_3_ERST_WRITE_REGISTER_VALUE 0x03
-#define EFI_ACPI_6_3_ERST_NOOP 0x04
-#define EFI_ACPI_6_3_ERST_LOAD_VAR1 0x05
-#define EFI_ACPI_6_3_ERST_LOAD_VAR2 0x06
-#define EFI_ACPI_6_3_ERST_STORE_VAR1 0x07
-#define EFI_ACPI_6_3_ERST_ADD 0x08
-#define EFI_ACPI_6_3_ERST_SUBTRACT 0x09
-#define EFI_ACPI_6_3_ERST_ADD_VALUE 0x0A
-#define EFI_ACPI_6_3_ERST_SUBTRACT_VALUE 0x0B
-#define EFI_ACPI_6_3_ERST_STALL 0x0C
-#define EFI_ACPI_6_3_ERST_STALL_WHILE_TRUE 0x0D
-#define EFI_ACPI_6_3_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
-#define EFI_ACPI_6_3_ERST_GOTO 0x0F
-#define EFI_ACPI_6_3_ERST_SET_SRC_ADDRESS_BASE 0x10
-#define EFI_ACPI_6_3_ERST_SET_DST_ADDRESS_BASE 0x11
-#define EFI_ACPI_6_3_ERST_MOVE_DATA 0x12
+#define EFI_ACPI_6_3_ERST_READ_REGISTER 0x00
+#define EFI_ACPI_6_3_ERST_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_3_ERST_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_3_ERST_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_3_ERST_NOOP 0x04
+#define EFI_ACPI_6_3_ERST_LOAD_VAR1 0x05
+#define EFI_ACPI_6_3_ERST_LOAD_VAR2 0x06
+#define EFI_ACPI_6_3_ERST_STORE_VAR1 0x07
+#define EFI_ACPI_6_3_ERST_ADD 0x08
+#define EFI_ACPI_6_3_ERST_SUBTRACT 0x09
+#define EFI_ACPI_6_3_ERST_ADD_VALUE 0x0A
+#define EFI_ACPI_6_3_ERST_SUBTRACT_VALUE 0x0B
+#define EFI_ACPI_6_3_ERST_STALL 0x0C
+#define EFI_ACPI_6_3_ERST_STALL_WHILE_TRUE 0x0D
+#define EFI_ACPI_6_3_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
+#define EFI_ACPI_6_3_ERST_GOTO 0x0F
+#define EFI_ACPI_6_3_ERST_SET_SRC_ADDRESS_BASE 0x10
+#define EFI_ACPI_6_3_ERST_SET_DST_ADDRESS_BASE 0x11
+#define EFI_ACPI_6_3_ERST_MOVE_DATA 0x12
///
/// ERST Instruction Flags
///
-#define EFI_ACPI_6_3_ERST_PRESERVE_REGISTER 0x01
+#define EFI_ACPI_6_3_ERST_PRESERVE_REGISTER 0x01
///
/// ERST Serialization Instruction Entry
///
typedef struct {
- UINT8 SerializationAction;
- UINT8 Instruction;
- UINT8 Flags;
- UINT8 Reserved0;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
- UINT64 Value;
- UINT64 Mask;
+ UINT8 SerializationAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
} EFI_ACPI_6_3_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
///
/// EINJ - Error Injection Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 InjectionHeaderSize;
- UINT8 InjectionFlags;
- UINT8 Reserved0[3];
- UINT32 InjectionEntryCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 InjectionHeaderSize;
+ UINT8 InjectionFlags;
+ UINT8 Reserved0[3];
+ UINT32 InjectionEntryCount;
} EFI_ACPI_6_3_ERROR_INJECTION_TABLE_HEADER;
///
/// EINJ Version (as defined in ACPI 6.3 spec.)
///
-#define EFI_ACPI_6_3_ERROR_INJECTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_3_ERROR_INJECTION_TABLE_REVISION 0x01
///
/// EINJ Error Injection Actions
///
-#define EFI_ACPI_6_3_EINJ_BEGIN_INJECTION_OPERATION 0x00
-#define EFI_ACPI_6_3_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
-#define EFI_ACPI_6_3_EINJ_SET_ERROR_TYPE 0x02
-#define EFI_ACPI_6_3_EINJ_GET_ERROR_TYPE 0x03
-#define EFI_ACPI_6_3_EINJ_END_OPERATION 0x04
-#define EFI_ACPI_6_3_EINJ_EXECUTE_OPERATION 0x05
-#define EFI_ACPI_6_3_EINJ_CHECK_BUSY_STATUS 0x06
-#define EFI_ACPI_6_3_EINJ_GET_COMMAND_STATUS 0x07
-#define EFI_ACPI_6_3_EINJ_TRIGGER_ERROR 0xFF
+#define EFI_ACPI_6_3_EINJ_BEGIN_INJECTION_OPERATION 0x00
+#define EFI_ACPI_6_3_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
+#define EFI_ACPI_6_3_EINJ_SET_ERROR_TYPE 0x02
+#define EFI_ACPI_6_3_EINJ_GET_ERROR_TYPE 0x03
+#define EFI_ACPI_6_3_EINJ_END_OPERATION 0x04
+#define EFI_ACPI_6_3_EINJ_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_3_EINJ_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_3_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_3_EINJ_TRIGGER_ERROR 0xFF
///
/// EINJ Action Command Status
///
-#define EFI_ACPI_6_3_EINJ_STATUS_SUCCESS 0x00
-#define EFI_ACPI_6_3_EINJ_STATUS_UNKNOWN_FAILURE 0x01
-#define EFI_ACPI_6_3_EINJ_STATUS_INVALID_ACCESS 0x02
+#define EFI_ACPI_6_3_EINJ_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_3_EINJ_STATUS_UNKNOWN_FAILURE 0x01
+#define EFI_ACPI_6_3_EINJ_STATUS_INVALID_ACCESS 0x02
///
/// EINJ Error Type Definition
///
-#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
-#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
-#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
-#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
-#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
-#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
-#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
-#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
-#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
-#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
-#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
-#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
+#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
+#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
+#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
+#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
+#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
+#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
+#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
+#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
+#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
+#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
+#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
+#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
///
/// EINJ Injection Instructions
///
-#define EFI_ACPI_6_3_EINJ_READ_REGISTER 0x00
-#define EFI_ACPI_6_3_EINJ_READ_REGISTER_VALUE 0x01
-#define EFI_ACPI_6_3_EINJ_WRITE_REGISTER 0x02
-#define EFI_ACPI_6_3_EINJ_WRITE_REGISTER_VALUE 0x03
-#define EFI_ACPI_6_3_EINJ_NOOP 0x04
+#define EFI_ACPI_6_3_EINJ_READ_REGISTER 0x00
+#define EFI_ACPI_6_3_EINJ_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_3_EINJ_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_3_EINJ_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_3_EINJ_NOOP 0x04
///
/// EINJ Instruction Flags
///
-#define EFI_ACPI_6_3_EINJ_PRESERVE_REGISTER 0x01
+#define EFI_ACPI_6_3_EINJ_PRESERVE_REGISTER 0x01
///
/// EINJ Injection Instruction Entry
///
typedef struct {
- UINT8 InjectionAction;
- UINT8 Instruction;
- UINT8 Flags;
- UINT8 Reserved0;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
- UINT64 Value;
- UINT64 Mask;
+ UINT8 InjectionAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
} EFI_ACPI_6_3_EINJ_INJECTION_INSTRUCTION_ENTRY;
///
/// EINJ Trigger Action Table
///
typedef struct {
- UINT32 HeaderSize;
- UINT32 Revision;
- UINT32 TableSize;
- UINT32 EntryCount;
+ UINT32 HeaderSize;
+ UINT32 Revision;
+ UINT32 TableSize;
+ UINT32 EntryCount;
} EFI_ACPI_6_3_EINJ_TRIGGER_ACTION_TABLE;
///
/// Platform Communications Channel Table (PCCT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Flags;
- UINT64 Reserved;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Flags;
+ UINT64 Reserved;
} EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
///
/// PCCT Version (as defined in ACPI 6.3 spec.)
///
-#define EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02
+#define EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02
///
/// PCCT Global Flags
@@ -2303,35 +2326,35 @@ typedef struct {
//
// PCCT Subspace type
//
-#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_GENERIC 0x00
-#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01
-#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02
-#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03
-#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_GENERIC 0x00
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04
///
/// PCC Subspace Structure Header
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
+ UINT8 Type;
+ UINT8 Length;
} EFI_ACPI_6_3_PCCT_SUBSPACE_HEADER;
///
/// Generic Communications Subspace Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[6];
- UINT64 BaseAddress;
- UINT64 AddressLength;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
- UINT64 DoorbellPreserve;
- UINT64 DoorbellWrite;
- UINT32 NominalLatency;
- UINT32 MaximumPeriodicAccessRate;
- UINT16 MinimumRequestTurnaroundTime;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[6];
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
} EFI_ACPI_6_3_PCCT_SUBSPACE_GENERIC;
///
@@ -2339,18 +2362,18 @@ typedef struct {
///
typedef struct {
- UINT8 Command;
- UINT8 Reserved:7;
- UINT8 NotifyOnCompletion:1;
+ UINT8 Command;
+ UINT8 Reserved : 7;
+ UINT8 NotifyOnCompletion : 1;
} EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
typedef struct {
- UINT8 CommandComplete:1;
- UINT8 PlatformInterrupt:1;
- UINT8 Error:1;
- UINT8 PlatformNotification:1;
- UINT8 Reserved:4;
- UINT8 Reserved1;
+ UINT8 CommandComplete : 1;
+ UINT8 PlatformInterrupt : 1;
+ UINT8 Error : 1;
+ UINT8 PlatformNotification : 1;
+ UINT8 Reserved : 4;
+ UINT8 Reserved1;
} EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
typedef struct {
@@ -2359,78 +2382,78 @@ typedef struct {
EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;
} EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
-#define EFI_ACPI_6_3_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0
-#define EFI_ACPI_6_3_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1
///
/// Type 1 HW-Reduced Communications Subspace Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 PlatformInterrupt;
- UINT8 PlatformInterruptFlags;
- UINT8 Reserved;
- UINT64 BaseAddress;
- UINT64 AddressLength;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
- UINT64 DoorbellPreserve;
- UINT64 DoorbellWrite;
- UINT32 NominalLatency;
- UINT32 MaximumPeriodicAccessRate;
- UINT16 MinimumRequestTurnaroundTime;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
} EFI_ACPI_6_3_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
///
/// Type 2 HW-Reduced Communications Subspace Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 PlatformInterrupt;
- UINT8 PlatformInterruptFlags;
- UINT8 Reserved;
- UINT64 BaseAddress;
- UINT64 AddressLength;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
- UINT64 DoorbellPreserve;
- UINT64 DoorbellWrite;
- UINT32 NominalLatency;
- UINT32 MaximumPeriodicAccessRate;
- UINT16 MinimumRequestTurnaroundTime;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
- UINT64 PlatformInterruptAckPreserve;
- UINT64 PlatformInterruptAckWrite;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
+ UINT64 PlatformInterruptAckPreserve;
+ UINT64 PlatformInterruptAckWrite;
} EFI_ACPI_6_3_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
///
/// Type 3 Extended PCC Subspace Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 PlatformInterrupt;
- UINT8 PlatformInterruptFlags;
- UINT8 Reserved;
- UINT64 BaseAddress;
- UINT32 AddressLength;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
- UINT64 DoorbellPreserve;
- UINT64 DoorbellWrite;
- UINT32 NominalLatency;
- UINT32 MaximumPeriodicAccessRate;
- UINT32 MinimumRequestTurnaroundTime;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
- UINT64 PlatformInterruptAckPreserve;
- UINT64 PlatformInterruptAckSet;
- UINT8 Reserved1[8];
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;
- UINT64 CommandCompleteCheckMask;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;
- UINT64 CommandCompleteUpdatePreserve;
- UINT64 CommandCompleteUpdateSet;
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;
- UINT64 ErrorStatusMask;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT32 AddressLength;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT32 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
+ UINT64 PlatformInterruptAckPreserve;
+ UINT64 PlatformInterruptAckSet;
+ UINT8 Reserved1[8];
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;
+ UINT64 CommandCompleteCheckMask;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;
+ UINT64 CommandCompleteUpdatePreserve;
+ UINT64 CommandCompleteUpdateSet;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;
+ UINT64 ErrorStatusMask;
} EFI_ACPI_6_3_PCCT_SUBSPACE_3_EXTENDED_PCC;
///
@@ -2438,46 +2461,46 @@ typedef struct {
///
typedef EFI_ACPI_6_3_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_3_PCCT_SUBSPACE_4_EXTENDED_PCC;
-#define EFI_ACPI_6_3_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0
+#define EFI_ACPI_6_3_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0
typedef struct {
- UINT32 Signature;
- UINT32 Flags;
- UINT32 Length;
- UINT32 Command;
+ UINT32 Signature;
+ UINT32 Flags;
+ UINT32 Length;
+ UINT32 Command;
} EFI_ACPI_6_3_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER;
///
/// Platform Debug Trigger Table (PDTT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 TriggerCount;
- UINT8 Reserved[3];
- UINT32 TriggerIdentifierArrayOffset;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 TriggerCount;
+ UINT8 Reserved[3];
+ UINT32 TriggerIdentifierArrayOffset;
} EFI_ACPI_6_3_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER;
///
/// PDTT Revision (as defined in ACPI 6.3 spec.)
///
-#define EFI_ACPI_6_3_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00
+#define EFI_ACPI_6_3_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00
///
/// PDTT Platform Communication Channel Identifier Structure
///
typedef struct {
- UINT16 SubChannelIdentifer:8;
- UINT16 Runtime:1;
- UINT16 WaitForCompletion:1;
- UINT16 TriggerOrder:1;
- UINT16 Reserved:5;
+ UINT16 SubChannelIdentifer : 8;
+ UINT16 Runtime : 1;
+ UINT16 WaitForCompletion : 1;
+ UINT16 TriggerOrder : 1;
+ UINT16 Reserved : 5;
} EFI_ACPI_6_3_PDTT_PCC_IDENTIFIER;
///
/// PCC Commands Codes used by Platform Debug Trigger Table
///
-#define EFI_ACPI_6_3_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00
-#define EFI_ACPI_6_3_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01
+#define EFI_ACPI_6_3_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00
+#define EFI_ACPI_6_3_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01
///
/// PPTT Platform Communication Channel
@@ -2488,28 +2511,28 @@ typedef EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6_3_PDTT_
/// Processor Properties Topology Table (PPTT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;
///
/// PPTT Revision (as defined in ACPI 6.3 spec.)
///
-#define EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x02
+#define EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x02
///
/// PPTT types
///
-#define EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR 0x00
-#define EFI_ACPI_6_3_PPTT_TYPE_CACHE 0x01
-#define EFI_ACPI_6_3_PPTT_TYPE_ID 0x02
+#define EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR 0x00
+#define EFI_ACPI_6_3_PPTT_TYPE_CACHE 0x01
+#define EFI_ACPI_6_3_PPTT_TYPE_ID 0x02
///
/// PPTT Structure Header
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[2];
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
} EFI_ACPI_6_3_PPTT_STRUCTURE_HEADER;
///
@@ -2530,110 +2553,110 @@ typedef struct {
/// Processor hierarchy node structure flags
///
typedef struct {
- UINT32 PhysicalPackage:1;
- UINT32 AcpiProcessorIdValid:1;
- UINT32 ProcessorIsAThread:1;
- UINT32 NodeIsALeaf:1;
- UINT32 IdenticalImplementation:1;
- UINT32 Reserved:27;
+ UINT32 PhysicalPackage : 1;
+ UINT32 AcpiProcessorIdValid : 1;
+ UINT32 ProcessorIsAThread : 1;
+ UINT32 NodeIsALeaf : 1;
+ UINT32 IdenticalImplementation : 1;
+ UINT32 Reserved : 27;
} EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS;
///
/// Processor hierarchy node structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[2];
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;
- UINT32 Parent;
- UINT32 AcpiProcessorId;
- UINT32 NumberOfPrivateResources;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;
+ UINT32 Parent;
+ UINT32 AcpiProcessorId;
+ UINT32 NumberOfPrivateResources;
} EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR;
///
/// For PPTT struct cache flags
///
-#define EFI_ACPI_6_3_PPTT_CACHE_SIZE_INVALID 0x0
-#define EFI_ACPI_6_3_PPTT_CACHE_SIZE_VALID 0x1
-#define EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_INVALID 0x0
-#define EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_VALID 0x1
-#define EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_INVALID 0x0
-#define EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_VALID 0x1
-#define EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_INVALID 0x0
-#define EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_VALID 0x1
-#define EFI_ACPI_6_3_PPTT_CACHE_TYPE_INVALID 0x0
-#define EFI_ACPI_6_3_PPTT_CACHE_TYPE_VALID 0x1
-#define EFI_ACPI_6_3_PPTT_WRITE_POLICY_INVALID 0x0
-#define EFI_ACPI_6_3_PPTT_WRITE_POLICY_VALID 0x1
-#define EFI_ACPI_6_3_PPTT_LINE_SIZE_INVALID 0x0
-#define EFI_ACPI_6_3_PPTT_LINE_SIZE_VALID 0x1
+#define EFI_ACPI_6_3_PPTT_CACHE_SIZE_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_CACHE_SIZE_VALID 0x1
+#define EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_VALID 0x1
+#define EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_VALID 0x1
+#define EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_VALID 0x1
+#define EFI_ACPI_6_3_PPTT_CACHE_TYPE_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_CACHE_TYPE_VALID 0x1
+#define EFI_ACPI_6_3_PPTT_WRITE_POLICY_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_WRITE_POLICY_VALID 0x1
+#define EFI_ACPI_6_3_PPTT_LINE_SIZE_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_LINE_SIZE_VALID 0x1
///
/// Cache Type Structure flags
///
typedef struct {
- UINT32 SizePropertyValid:1;
- UINT32 NumberOfSetsValid:1;
- UINT32 AssociativityValid:1;
- UINT32 AllocationTypeValid:1;
- UINT32 CacheTypeValid:1;
- UINT32 WritePolicyValid:1;
- UINT32 LineSizeValid:1;
- UINT32 Reserved:25;
+ UINT32 SizePropertyValid : 1;
+ UINT32 NumberOfSetsValid : 1;
+ UINT32 AssociativityValid : 1;
+ UINT32 AllocationTypeValid : 1;
+ UINT32 CacheTypeValid : 1;
+ UINT32 WritePolicyValid : 1;
+ UINT32 LineSizeValid : 1;
+ UINT32 Reserved : 25;
} EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_FLAGS;
///
/// For cache attributes
///
-#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0
-#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1
-#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2
-#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0
-#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1
-#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2
-#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0
-#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1
///
/// Cache Type Structure cache attributes
///
typedef struct {
- UINT8 AllocationType:2;
- UINT8 CacheType:2;
- UINT8 WritePolicy:1;
- UINT8 Reserved:3;
+ UINT8 AllocationType : 2;
+ UINT8 CacheType : 2;
+ UINT8 WritePolicy : 1;
+ UINT8 Reserved : 3;
} EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_ATTRIBUTES;
///
/// Cache Type Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[2];
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_FLAGS Flags;
- UINT32 NextLevelOfCache;
- UINT32 Size;
- UINT32 NumberOfSets;
- UINT8 Associativity;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;
- UINT16 LineSize;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_FLAGS Flags;
+ UINT32 NextLevelOfCache;
+ UINT32 Size;
+ UINT32 NumberOfSets;
+ UINT8 Associativity;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;
+ UINT16 LineSize;
} EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE;
///
/// ID structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[2];
- UINT32 VendorId;
- UINT64 Level1Id;
- UINT64 Level2Id;
- UINT16 MajorRev;
- UINT16 MinorRev;
- UINT16 SpinRev;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 VendorId;
+ UINT64 Level1Id;
+ UINT64 Level2Id;
+ UINT16 MajorRev;
+ UINT16 MinorRev;
+ UINT16 SpinRev;
} EFI_ACPI_6_3_PPTT_STRUCTURE_ID;
//
diff --git a/MdePkg/Include/IndustryStandard/Acpi64.h b/MdePkg/Include/IndustryStandard/Acpi64.h
index 706e795d..16ea03e9 100644
--- a/MdePkg/Include/IndustryStandard/Acpi64.h
+++ b/MdePkg/Include/IndustryStandard/Acpi64.h
@@ -1,7 +1,7 @@
/** @file
ACPI 6.4 definitions from the ACPI Specification Revision 6.4 Jan, 2021.
- Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
Copyright (c) 2019 - 2021, ARM Ltd. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -21,11 +21,11 @@
/// ACPI 6.4 Generic Address Space definition
///
typedef struct {
- UINT8 AddressSpaceId;
- UINT8 RegisterBitWidth;
- UINT8 RegisterBitOffset;
- UINT8 AccessSize;
- UINT64 Address;
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
} EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE;
//
@@ -61,29 +61,29 @@ typedef struct {
/// Root System Description Pointer Structure
///
typedef struct {
- UINT64 Signature;
- UINT8 Checksum;
- UINT8 OemId[6];
- UINT8 Revision;
- UINT32 RsdtAddress;
- UINT32 Length;
- UINT64 XsdtAddress;
- UINT8 ExtendedChecksum;
- UINT8 Reserved[3];
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
} EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_POINTER;
///
/// RSD_PTR Revision (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.4) says current value is 2
+#define EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.4) says current value is 2
///
/// Common table header, this prefaces all ACPI tables, including FACS, but
/// excluding the RSD PTR structure
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
+ UINT32 Signature;
+ UINT32 Length;
} EFI_ACPI_6_4_COMMON_HEADER;
//
@@ -95,7 +95,7 @@ typedef struct {
///
/// RSDT Revision (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
//
// Extended System Description Table
@@ -106,74 +106,74 @@ typedef struct {
///
/// XSDT Revision (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_4_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
///
/// Fixed ACPI Description Table Structure (FADT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 FirmwareCtrl;
- UINT32 Dsdt;
- UINT8 Reserved0;
- UINT8 PreferredPmProfile;
- UINT16 SciInt;
- UINT32 SmiCmd;
- UINT8 AcpiEnable;
- UINT8 AcpiDisable;
- UINT8 S4BiosReq;
- UINT8 PstateCnt;
- UINT32 Pm1aEvtBlk;
- UINT32 Pm1bEvtBlk;
- UINT32 Pm1aCntBlk;
- UINT32 Pm1bCntBlk;
- UINT32 Pm2CntBlk;
- UINT32 PmTmrBlk;
- UINT32 Gpe0Blk;
- UINT32 Gpe1Blk;
- UINT8 Pm1EvtLen;
- UINT8 Pm1CntLen;
- UINT8 Pm2CntLen;
- UINT8 PmTmrLen;
- UINT8 Gpe0BlkLen;
- UINT8 Gpe1BlkLen;
- UINT8 Gpe1Base;
- UINT8 CstCnt;
- UINT16 PLvl2Lat;
- UINT16 PLvl3Lat;
- UINT16 FlushSize;
- UINT16 FlushStride;
- UINT8 DutyOffset;
- UINT8 DutyWidth;
- UINT8 DayAlrm;
- UINT8 MonAlrm;
- UINT8 Century;
- UINT16 IaPcBootArch;
- UINT8 Reserved1;
- UINT32 Flags;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ResetReg;
- UINT8 ResetValue;
- UINT16 ArmBootArch;
- UINT8 MinorVersion;
- UINT64 XFirmwareCtrl;
- UINT64 XDsdt;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
- UINT64 HypervisorVendorIdentity;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT16 ArmBootArch;
+ UINT8 MinorVersion;
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
+ UINT64 HypervisorVendorIdentity;
} EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE;
///
/// FADT Version (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06
+#define EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06
#define EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x04
//
@@ -193,62 +193,62 @@ typedef struct {
// Fixed ACPI Description Table Boot Architecture Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_6_4_LEGACY_DEVICES BIT0
-#define EFI_ACPI_6_4_8042 BIT1
-#define EFI_ACPI_6_4_VGA_NOT_PRESENT BIT2
-#define EFI_ACPI_6_4_MSI_NOT_SUPPORTED BIT3
-#define EFI_ACPI_6_4_PCIE_ASPM_CONTROLS BIT4
-#define EFI_ACPI_6_4_CMOS_RTC_NOT_PRESENT BIT5
+#define EFI_ACPI_6_4_LEGACY_DEVICES BIT0
+#define EFI_ACPI_6_4_8042 BIT1
+#define EFI_ACPI_6_4_VGA_NOT_PRESENT BIT2
+#define EFI_ACPI_6_4_MSI_NOT_SUPPORTED BIT3
+#define EFI_ACPI_6_4_PCIE_ASPM_CONTROLS BIT4
+#define EFI_ACPI_6_4_CMOS_RTC_NOT_PRESENT BIT5
//
// Fixed ACPI Description Table Arm Boot Architecture Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_6_4_ARM_PSCI_COMPLIANT BIT0
-#define EFI_ACPI_6_4_ARM_PSCI_USE_HVC BIT1
+#define EFI_ACPI_6_4_ARM_PSCI_COMPLIANT BIT0
+#define EFI_ACPI_6_4_ARM_PSCI_USE_HVC BIT1
//
// Fixed ACPI Description Table Fixed Feature Flags
// All other bits are reserved and must be set to 0.
//
-#define EFI_ACPI_6_4_WBINVD BIT0
-#define EFI_ACPI_6_4_WBINVD_FLUSH BIT1
-#define EFI_ACPI_6_4_PROC_C1 BIT2
-#define EFI_ACPI_6_4_P_LVL2_UP BIT3
-#define EFI_ACPI_6_4_PWR_BUTTON BIT4
-#define EFI_ACPI_6_4_SLP_BUTTON BIT5
-#define EFI_ACPI_6_4_FIX_RTC BIT6
-#define EFI_ACPI_6_4_RTC_S4 BIT7
-#define EFI_ACPI_6_4_TMR_VAL_EXT BIT8
-#define EFI_ACPI_6_4_DCK_CAP BIT9
-#define EFI_ACPI_6_4_RESET_REG_SUP BIT10
-#define EFI_ACPI_6_4_SEALED_CASE BIT11
-#define EFI_ACPI_6_4_HEADLESS BIT12
-#define EFI_ACPI_6_4_CPU_SW_SLP BIT13
-#define EFI_ACPI_6_4_PCI_EXP_WAK BIT14
-#define EFI_ACPI_6_4_USE_PLATFORM_CLOCK BIT15
-#define EFI_ACPI_6_4_S4_RTC_STS_VALID BIT16
-#define EFI_ACPI_6_4_REMOTE_POWER_ON_CAPABLE BIT17
-#define EFI_ACPI_6_4_FORCE_APIC_CLUSTER_MODEL BIT18
-#define EFI_ACPI_6_4_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
-#define EFI_ACPI_6_4_HW_REDUCED_ACPI BIT20
-#define EFI_ACPI_6_4_LOW_POWER_S0_IDLE_CAPABLE BIT21
+#define EFI_ACPI_6_4_WBINVD BIT0
+#define EFI_ACPI_6_4_WBINVD_FLUSH BIT1
+#define EFI_ACPI_6_4_PROC_C1 BIT2
+#define EFI_ACPI_6_4_P_LVL2_UP BIT3
+#define EFI_ACPI_6_4_PWR_BUTTON BIT4
+#define EFI_ACPI_6_4_SLP_BUTTON BIT5
+#define EFI_ACPI_6_4_FIX_RTC BIT6
+#define EFI_ACPI_6_4_RTC_S4 BIT7
+#define EFI_ACPI_6_4_TMR_VAL_EXT BIT8
+#define EFI_ACPI_6_4_DCK_CAP BIT9
+#define EFI_ACPI_6_4_RESET_REG_SUP BIT10
+#define EFI_ACPI_6_4_SEALED_CASE BIT11
+#define EFI_ACPI_6_4_HEADLESS BIT12
+#define EFI_ACPI_6_4_CPU_SW_SLP BIT13
+#define EFI_ACPI_6_4_PCI_EXP_WAK BIT14
+#define EFI_ACPI_6_4_USE_PLATFORM_CLOCK BIT15
+#define EFI_ACPI_6_4_S4_RTC_STS_VALID BIT16
+#define EFI_ACPI_6_4_REMOTE_POWER_ON_CAPABLE BIT17
+#define EFI_ACPI_6_4_FORCE_APIC_CLUSTER_MODEL BIT18
+#define EFI_ACPI_6_4_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+#define EFI_ACPI_6_4_HW_REDUCED_ACPI BIT20
+#define EFI_ACPI_6_4_LOW_POWER_S0_IDLE_CAPABLE BIT21
///
/// Firmware ACPI Control Structure
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
- UINT32 HardwareSignature;
- UINT32 FirmwareWakingVector;
- UINT32 GlobalLock;
- UINT32 Flags;
- UINT64 XFirmwareWakingVector;
- UINT8 Version;
- UINT8 Reserved0[3];
- UINT32 OspmFlags;
- UINT8 Reserved1[24];
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved0[3];
+ UINT32 OspmFlags;
+ UINT8 Reserved1[24];
} EFI_ACPI_6_4_FIRMWARE_ACPI_CONTROL_STRUCTURE;
///
@@ -260,14 +260,14 @@ typedef struct {
/// Firmware Control Structure Feature Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_6_4_S4BIOS_F BIT0
-#define EFI_ACPI_6_4_64BIT_WAKE_SUPPORTED_F BIT1
+#define EFI_ACPI_6_4_S4BIOS_F BIT0
+#define EFI_ACPI_6_4_64BIT_WAKE_SUPPORTED_F BIT1
///
/// OSPM Enabled Firmware Control Structure Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_6_4_OSPM_64BIT_WAKE_F BIT0
+#define EFI_ACPI_6_4_OSPM_64BIT_WAKE_F BIT0
//
// Differentiated System Description Table,
@@ -276,29 +276,29 @@ typedef struct {
// no definition needed as they are common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
//
-#define EFI_ACPI_6_4_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
-#define EFI_ACPI_6_4_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_6_4_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_6_4_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
///
/// Multiple APIC Description Table header definition. The rest of the table
/// must be defined in a platform specific manner.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 LocalApicAddress;
- UINT32 Flags;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
///
/// MADT Revision (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x05
+#define EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x05
///
/// Multiple APIC Flags
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_6_4_PCAT_COMPAT BIT0
+#define EFI_ACPI_6_4_PCAT_COMPAT BIT0
//
// Multiple APIC Description Table APIC structure types
@@ -331,11 +331,11 @@ typedef struct {
/// Processor Local APIC Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorUid;
- UINT8 ApicId;
- UINT32 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT8 ApicId;
+ UINT32 Flags;
} EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC_STRUCTURE;
///
@@ -348,41 +348,41 @@ typedef struct {
/// IO APIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 IoApicAddress;
- UINT32 GlobalSystemInterruptBase;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
} EFI_ACPI_6_4_IO_APIC_STRUCTURE;
///
/// Interrupt Source Override Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Bus;
- UINT8 Source;
- UINT32 GlobalSystemInterrupt;
- UINT16 Flags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
} EFI_ACPI_6_4_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
///
/// Platform Interrupt Sources Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT8 InterruptType;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT8 IoSapicVector;
- UINT32 GlobalSystemInterrupt;
- UINT32 PlatformInterruptSourceFlags;
- UINT8 CpeiProcessorOverride;
- UINT8 Reserved[31];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
} EFI_ACPI_6_4_PLATFORM_INTERRUPT_APIC_STRUCTURE;
//
@@ -396,43 +396,43 @@ typedef struct {
/// Non-Maskable Interrupt Source Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT32 GlobalSystemInterrupt;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
} EFI_ACPI_6_4_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
///
/// Local APIC NMI Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorUid;
- UINT16 Flags;
- UINT8 LocalApicLint;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
} EFI_ACPI_6_4_LOCAL_APIC_NMI_STRUCTURE;
///
/// Local APIC Address Override Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT64 LocalApicAddress;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
} EFI_ACPI_6_4_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
///
/// IO SAPIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 IoApicId;
- UINT8 Reserved;
- UINT32 GlobalSystemInterruptBase;
- UINT64 IoSapicAddress;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
} EFI_ACPI_6_4_IO_SAPIC_STRUCTURE;
///
@@ -440,196 +440,196 @@ typedef struct {
/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 AcpiProcessorId;
- UINT8 LocalSapicId;
- UINT8 LocalSapicEid;
- UINT8 Reserved[3];
- UINT32 Flags;
- UINT32 ACPIProcessorUIDValue;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
} EFI_ACPI_6_4_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
///
/// Platform Interrupt Sources Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT8 InterruptType;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT8 IoSapicVector;
- UINT32 GlobalSystemInterrupt;
- UINT32 PlatformInterruptSourceFlags;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
} EFI_ACPI_6_4_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
///
/// Platform Interrupt Source Flags.
/// All other bits are reserved and must be set to 0.
///
-#define EFI_ACPI_6_4_CPEI_PROCESSOR_OVERRIDE BIT0
+#define EFI_ACPI_6_4_CPEI_PROCESSOR_OVERRIDE BIT0
///
/// Processor Local x2APIC Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[2];
- UINT32 X2ApicId;
- UINT32 Flags;
- UINT32 AcpiProcessorUid;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 AcpiProcessorUid;
} EFI_ACPI_6_4_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
///
/// Local x2APIC NMI Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Flags;
- UINT32 AcpiProcessorUid;
- UINT8 LocalX2ApicLint;
- UINT8 Reserved[3];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 AcpiProcessorUid;
+ UINT8 LocalX2ApicLint;
+ UINT8 Reserved[3];
} EFI_ACPI_6_4_LOCAL_X2APIC_NMI_STRUCTURE;
///
/// GIC Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT32 CPUInterfaceNumber;
- UINT32 AcpiProcessorUid;
- UINT32 Flags;
- UINT32 ParkingProtocolVersion;
- UINT32 PerformanceInterruptGsiv;
- UINT64 ParkedAddress;
- UINT64 PhysicalBaseAddress;
- UINT64 GICV;
- UINT64 GICH;
- UINT32 VGICMaintenanceInterrupt;
- UINT64 GICRBaseAddress;
- UINT64 MPIDR;
- UINT8 ProcessorPowerEfficiencyClass;
- UINT8 Reserved2;
- UINT16 SpeOverflowInterrupt;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 CPUInterfaceNumber;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ParkingProtocolVersion;
+ UINT32 PerformanceInterruptGsiv;
+ UINT64 ParkedAddress;
+ UINT64 PhysicalBaseAddress;
+ UINT64 GICV;
+ UINT64 GICH;
+ UINT32 VGICMaintenanceInterrupt;
+ UINT64 GICRBaseAddress;
+ UINT64 MPIDR;
+ UINT8 ProcessorPowerEfficiencyClass;
+ UINT8 Reserved2;
+ UINT16 SpeOverflowInterrupt;
} EFI_ACPI_6_4_GIC_STRUCTURE;
///
/// GIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_4_GIC_ENABLED BIT0
-#define EFI_ACPI_6_4_PERFORMANCE_INTERRUPT_MODEL BIT1
-#define EFI_ACPI_6_4_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2
+#define EFI_ACPI_6_4_GIC_ENABLED BIT0
+#define EFI_ACPI_6_4_PERFORMANCE_INTERRUPT_MODEL BIT1
+#define EFI_ACPI_6_4_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2
///
/// GIC Distributor Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved1;
- UINT32 GicId;
- UINT64 PhysicalBaseAddress;
- UINT32 SystemVectorBase;
- UINT8 GicVersion;
- UINT8 Reserved2[3];
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 SystemVectorBase;
+ UINT8 GicVersion;
+ UINT8 Reserved2[3];
} EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE;
///
/// GIC Version
///
-#define EFI_ACPI_6_4_GIC_V1 0x01
-#define EFI_ACPI_6_4_GIC_V2 0x02
-#define EFI_ACPI_6_4_GIC_V3 0x03
-#define EFI_ACPI_6_4_GIC_V4 0x04
+#define EFI_ACPI_6_4_GIC_V1 0x01
+#define EFI_ACPI_6_4_GIC_V2 0x02
+#define EFI_ACPI_6_4_GIC_V3 0x03
+#define EFI_ACPI_6_4_GIC_V4 0x04
///
/// GIC MSI Frame Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved1;
- UINT32 GicMsiFrameId;
- UINT64 PhysicalBaseAddress;
- UINT32 Flags;
- UINT16 SPICount;
- UINT16 SPIBase;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicMsiFrameId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Flags;
+ UINT16 SPICount;
+ UINT16 SPIBase;
} EFI_ACPI_6_4_GIC_MSI_FRAME_STRUCTURE;
///
/// GIC MSI Frame Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_4_SPI_COUNT_BASE_SELECT BIT0
+#define EFI_ACPI_6_4_SPI_COUNT_BASE_SELECT BIT0
///
/// GICR Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT64 DiscoveryRangeBaseAddress;
- UINT32 DiscoveryRangeLength;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 DiscoveryRangeBaseAddress;
+ UINT32 DiscoveryRangeLength;
} EFI_ACPI_6_4_GICR_STRUCTURE;
///
/// GIC Interrupt Translation Service Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved;
- UINT32 GicItsId;
- UINT64 PhysicalBaseAddress;
- UINT32 Reserved2;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 GicItsId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Reserved2;
} EFI_ACPI_6_4_GIC_ITS_STRUCTURE;
///
/// Multiprocessor Wakeup Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 MailBoxVersion;
- UINT32 Reserved;
- UINT64 MailBoxAddress;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 MailBoxVersion;
+ UINT32 Reserved;
+ UINT64 MailBoxAddress;
} EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_STRUCTURE;
///
/// Multiprocessor Wakeup Mailbox Structure
///
typedef struct {
- UINT16 Command;
- UINT16 Reserved;
- UINT32 AcpiId;
- UINT64 WakeupVector;
- UINT8 ReservedForOs[2032];
- UINT8 ReservedForFirmware[2048];
+ UINT16 Command;
+ UINT16 Reserved;
+ UINT32 AcpiId;
+ UINT64 WakeupVector;
+ UINT8 ReservedForOs[2032];
+ UINT8 ReservedForFirmware[2048];
} EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_MAILBOX_STRUCTURE;
-#define EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_NOOP 0x0000
-#define EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_WAKEUP 0x0001
+#define EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_NOOP 0x0000
+#define EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_WAKEUP 0x0001
///
/// Smart Battery Description Table (SBST)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 WarningEnergyLevel;
- UINT32 LowEnergyLevel;
- UINT32 CriticalEnergyLevel;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
} EFI_ACPI_6_4_SMART_BATTERY_DESCRIPTION_TABLE;
///
/// SBST Version (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_4_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
///
/// Embedded Controller Boot Resources Table (ECDT)
@@ -637,11 +637,11 @@ typedef struct {
/// a fully qualified reference to the name space object.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE EcControl;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE EcData;
- UINT32 Uid;
- UINT8 GpeBit;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
} EFI_ACPI_6_4_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
///
@@ -654,9 +654,9 @@ typedef struct {
/// must be defined in a platform specific manner.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Reserved1; ///< Must be set to 1
- UINT64 Reserved2;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; ///< Must be set to 1
+ UINT64 Reserved2;
} EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
///
@@ -680,85 +680,85 @@ typedef struct {
/// Processor Local APIC/SAPIC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 ProximityDomain7To0;
- UINT8 ApicId;
- UINT32 Flags;
- UINT8 LocalSapicEid;
- UINT8 ProximityDomain31To8[3];
- UINT32 ClockDomain;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT32 ClockDomain;
} EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
///
/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+#define EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
///
/// Memory Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 ProximityDomain;
- UINT16 Reserved1;
- UINT32 AddressBaseLow;
- UINT32 AddressBaseHigh;
- UINT32 LengthLow;
- UINT32 LengthHigh;
- UINT32 Reserved2;
- UINT32 Flags;
- UINT64 Reserved3;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
} EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE;
//
// Memory Flags. All other bits are reserved and must be 0.
//
-#define EFI_ACPI_6_4_MEMORY_ENABLED (1 << 0)
-#define EFI_ACPI_6_4_MEMORY_HOT_PLUGGABLE (1 << 1)
-#define EFI_ACPI_6_4_MEMORY_NONVOLATILE (1 << 2)
+#define EFI_ACPI_6_4_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_6_4_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_6_4_MEMORY_NONVOLATILE (1 << 2)
///
/// Processor Local x2APIC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved1[2];
- UINT32 ProximityDomain;
- UINT32 X2ApicId;
- UINT32 Flags;
- UINT32 ClockDomain;
- UINT8 Reserved2[4];
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1[2];
+ UINT32 ProximityDomain;
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+ UINT8 Reserved2[4];
} EFI_ACPI_6_4_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
///
/// GICC Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 ProximityDomain;
- UINT32 AcpiProcessorUid;
- UINT32 Flags;
- UINT32 ClockDomain;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ClockDomain;
} EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE;
///
/// GICC Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_4_GICC_ENABLED (1 << 0)
+#define EFI_ACPI_6_4_GICC_ENABLED (1 << 0)
///
/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 ProximityDomain;
- UINT8 Reserved[2];
- UINT32 ItsId;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT8 Reserved[2];
+ UINT32 ItsId;
} EFI_ACPI_6_4_GIC_ITS_AFFINITY_STRUCTURE;
//
@@ -766,47 +766,47 @@ typedef struct {
// All other values between 0x02 an 0xFF are reserved and
// will be ignored by OSPM.
//
-#define EFI_ACPI_6_4_ACPI_DEVICE_HANDLE 0x00
-#define EFI_ACPI_6_4_PCI_DEVICE_HANDLE 0x01
+#define EFI_ACPI_6_4_ACPI_DEVICE_HANDLE 0x00
+#define EFI_ACPI_6_4_PCI_DEVICE_HANDLE 0x01
///
/// Device Handle - ACPI
///
typedef struct {
- UINT64 AcpiHid;
- UINT32 AcpiUid;
- UINT8 Reserved[4];
+ UINT64 AcpiHid;
+ UINT32 AcpiUid;
+ UINT8 Reserved[4];
} EFI_ACPI_6_4_DEVICE_HANDLE_ACPI;
///
/// Device Handle - PCI
///
typedef struct {
- UINT16 PciSegment;
- UINT16 PciBdfNumber;
- UINT8 Reserved[12];
+ UINT16 PciSegment;
+ UINT16 PciBdfNumber;
+ UINT8 Reserved[12];
} EFI_ACPI_6_4_DEVICE_HANDLE_PCI;
///
/// Device Handle
///
typedef union {
- EFI_ACPI_6_4_DEVICE_HANDLE_ACPI Acpi;
- EFI_ACPI_6_4_DEVICE_HANDLE_PCI Pci;
+ EFI_ACPI_6_4_DEVICE_HANDLE_ACPI Acpi;
+ EFI_ACPI_6_4_DEVICE_HANDLE_PCI Pci;
} EFI_ACPI_6_4_DEVICE_HANDLE;
///
/// Generic Initiator Affinity Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved1;
- UINT8 DeviceHandleType;
- UINT32 ProximityDomain;
- EFI_ACPI_6_4_DEVICE_HANDLE DeviceHandle;
- UINT32 Flags;
- UINT8 Reserved2[4];
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1;
+ UINT8 DeviceHandleType;
+ UINT32 ProximityDomain;
+ EFI_ACPI_6_4_DEVICE_HANDLE DeviceHandle;
+ UINT32 Flags;
+ UINT8 Reserved2[4];
} EFI_ACPI_6_4_GENERIC_INITIATOR_AFFINITY_STRUCTURE;
///
@@ -821,8 +821,8 @@ typedef struct {
/// The rest of the table is a matrix.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 NumberOfSystemLocalities;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
} EFI_ACPI_6_4_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
///
@@ -834,14 +834,14 @@ typedef struct {
/// Corrected Platform Error Polling Table (CPEP)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 Reserved[8];
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[8];
} EFI_ACPI_6_4_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
///
/// CPEP Version (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+#define EFI_ACPI_6_4_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
//
// CPEP processor structure types.
@@ -852,66 +852,66 @@ typedef struct {
/// Corrected Platform Error Polling Processor Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 ProcessorId;
- UINT8 ProcessorEid;
- UINT32 PollingInterval;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT32 PollingInterval;
} EFI_ACPI_6_4_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
///
/// Maximum System Characteristics Table (MSCT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 OffsetProxDomInfo;
- UINT32 MaximumNumberOfProximityDomains;
- UINT32 MaximumNumberOfClockDomains;
- UINT64 MaximumPhysicalAddress;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 OffsetProxDomInfo;
+ UINT32 MaximumNumberOfProximityDomains;
+ UINT32 MaximumNumberOfClockDomains;
+ UINT64 MaximumPhysicalAddress;
} EFI_ACPI_6_4_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
///
/// MSCT Version (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+#define EFI_ACPI_6_4_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
///
/// Maximum Proximity Domain Information Structure Definition
///
typedef struct {
- UINT8 Revision;
- UINT8 Length;
- UINT32 ProximityDomainRangeLow;
- UINT32 ProximityDomainRangeHigh;
- UINT32 MaximumProcessorCapacity;
- UINT64 MaximumMemoryCapacity;
+ UINT8 Revision;
+ UINT8 Length;
+ UINT32 ProximityDomainRangeLow;
+ UINT32 ProximityDomainRangeHigh;
+ UINT32 MaximumProcessorCapacity;
+ UINT64 MaximumMemoryCapacity;
} EFI_ACPI_6_4_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
///
/// ACPI RAS Feature Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 PlatformCommunicationChannelIdentifier[12];
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier[12];
} EFI_ACPI_6_4_RAS_FEATURE_TABLE;
///
/// RASF Version (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_RAS_FEATURE_TABLE_REVISION 0x01
+#define EFI_ACPI_6_4_RAS_FEATURE_TABLE_REVISION 0x01
///
/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
///
typedef struct {
- UINT32 Signature;
- UINT16 Command;
- UINT16 Status;
- UINT16 Version;
- UINT8 RASCapabilities[16];
- UINT8 SetRASCapabilities[16];
- UINT16 NumberOfRASFParameterBlocks;
- UINT32 SetRASCapabilitiesStatus;
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT16 Version;
+ UINT8 RASCapabilities[16];
+ UINT8 SetRASCapabilities[16];
+ UINT16 NumberOfRASFParameterBlocks;
+ UINT32 SetRASCapabilitiesStatus;
} EFI_ACPI_6_4_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
///
@@ -922,62 +922,62 @@ typedef struct {
///
/// ACPI RASF Platform RAS Capabilities
///
-#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0
-#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1
-#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2
-#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3
-#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4
+#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0
+#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1
+#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2
+#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3
+#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4
///
/// ACPI RASF Parameter Block structure for PATROL_SCRUB
///
typedef struct {
- UINT16 Type;
- UINT16 Version;
- UINT16 Length;
- UINT16 PatrolScrubCommand;
- UINT64 RequestedAddressRange[2];
- UINT64 ActualAddressRange[2];
- UINT16 Flags;
- UINT8 RequestedSpeed;
+ UINT16 Type;
+ UINT16 Version;
+ UINT16 Length;
+ UINT16 PatrolScrubCommand;
+ UINT64 RequestedAddressRange[2];
+ UINT64 ActualAddressRange[2];
+ UINT16 Flags;
+ UINT8 RequestedSpeed;
} EFI_ACPI_6_4_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
///
/// ACPI RASF Patrol Scrub command
///
-#define EFI_ACPI_6_4_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
-#define EFI_ACPI_6_4_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
-#define EFI_ACPI_6_4_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
+#define EFI_ACPI_6_4_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
+#define EFI_ACPI_6_4_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
+#define EFI_ACPI_6_4_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
///
/// Memory Power State Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 PlatformCommunicationChannelIdentifier;
- UINT8 Reserved[3];
-// Memory Power Node Structure
-// Memory Power State Characteristics
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier;
+ UINT8 Reserved[3];
+ // Memory Power Node Structure
+ // Memory Power State Characteristics
} EFI_ACPI_6_4_MEMORY_POWER_STATUS_TABLE;
///
/// MPST Version (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+#define EFI_ACPI_6_4_MEMORY_POWER_STATE_TABLE_REVISION 0x01
///
/// MPST Platform Communication Channel Shared Memory Region definition.
///
typedef struct {
- UINT32 Signature;
- UINT16 Command;
- UINT16 Status;
- UINT32 MemoryPowerCommandRegister;
- UINT32 MemoryPowerStatusRegister;
- UINT32 PowerStateId;
- UINT32 MemoryPowerNodeId;
- UINT64 MemoryEnergyConsumed;
- UINT64 ExpectedAveragePowerComsuned;
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT32 MemoryPowerCommandRegister;
+ UINT32 MemoryPowerStatusRegister;
+ UINT32 PowerStateId;
+ UINT32 MemoryPowerNodeId;
+ UINT64 MemoryEnergyConsumed;
+ UINT64 ExpectedAveragePowerComsuned;
} EFI_ACPI_6_4_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
///
@@ -988,145 +988,145 @@ typedef struct {
///
/// ACPI MPST Memory Power command
///
-#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
-#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
-#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
-#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
///
/// MPST Memory Power Node Table
///
typedef struct {
- UINT8 PowerStateValue;
- UINT8 PowerStateInformationIndex;
+ UINT8 PowerStateValue;
+ UINT8 PowerStateInformationIndex;
} EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE;
typedef struct {
- UINT8 Flag;
- UINT8 Reserved;
- UINT16 MemoryPowerNodeId;
- UINT32 Length;
- UINT64 AddressBase;
- UINT64 AddressLength;
- UINT32 NumberOfPowerStates;
- UINT32 NumberOfPhysicalComponents;
-//EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
-//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+ UINT8 Flag;
+ UINT8 Reserved;
+ UINT16 MemoryPowerNodeId;
+ UINT32 Length;
+ UINT64 AddressBase;
+ UINT64 AddressLength;
+ UINT32 NumberOfPowerStates;
+ UINT32 NumberOfPhysicalComponents;
+ // EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
} EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE;
-#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
-#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
-#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
typedef struct {
- UINT16 MemoryPowerNodeCount;
- UINT8 Reserved[2];
+ UINT16 MemoryPowerNodeCount;
+ UINT8 Reserved[2];
} EFI_ACPI_6_4_MPST_MEMORY_POWER_NODE_TABLE;
///
/// MPST Memory Power State Characteristics Table
///
typedef struct {
- UINT8 PowerStateStructureID;
- UINT8 Flag;
- UINT16 Reserved;
- UINT32 AveragePowerConsumedInMPS0;
- UINT32 RelativePowerSavingToMPS0;
- UINT64 ExitLatencyToMPS0;
+ UINT8 PowerStateStructureID;
+ UINT8 Flag;
+ UINT16 Reserved;
+ UINT32 AveragePowerConsumedInMPS0;
+ UINT32 RelativePowerSavingToMPS0;
+ UINT64 ExitLatencyToMPS0;
} EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
-#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
-#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
-#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
typedef struct {
- UINT16 MemoryPowerStateCharacteristicsCount;
- UINT8 Reserved[2];
+ UINT16 MemoryPowerStateCharacteristicsCount;
+ UINT8 Reserved[2];
} EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
///
/// Platform Memory Topology Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 NumberOfMemoryDevices;
-//EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[NumberOfMemoryDevices];
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 NumberOfMemoryDevices;
+ // EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[NumberOfMemoryDevices];
} EFI_ACPI_6_4_PLATFORM_MEMORY_TOPOLOGY_TABLE;
///
/// PMTT Version (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_MEMORY_TOPOLOGY_TABLE_REVISION 0x02
+#define EFI_ACPI_6_4_MEMORY_TOPOLOGY_TABLE_REVISION 0x02
///
/// Common Memory Device.
///
typedef struct {
- UINT8 Type;
- UINT8 Reserved;
- UINT16 Length;
- UINT16 Flags;
- UINT16 Reserved1;
- UINT32 NumberOfMemoryDevices;
-//UINT8 TypeSpecificData[];
-//EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[NumberOfMemoryDevices];
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16 Length;
+ UINT16 Flags;
+ UINT16 Reserved1;
+ UINT32 NumberOfMemoryDevices;
+ // UINT8 TypeSpecificData[];
+ // EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[NumberOfMemoryDevices];
} EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE;
///
/// Memory Device Type.
///
-#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_SOCKET 0x0
-#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
-#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_DIMM 0x2
-#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_VENDOR_SPECIFIC_TYPE 0xFF
+#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_SOCKET 0x0
+#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
+#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_DIMM 0x2
+#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_VENDOR_SPECIFIC_TYPE 0xFF
///
/// Socket Type Data.
///
typedef struct {
- EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;
- UINT16 SocketIdentifier;
- UINT16 Reserved;
-//EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];
+ EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;
+ UINT16 SocketIdentifier;
+ UINT16 Reserved;
+ // EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];
} EFI_ACPI_6_4_PMTT_SOCKET_TYPE_DATA;
///
/// Memory Controller Type Data.
///
typedef struct {
- EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;
- UINT16 MemoryControllerIdentifier;
- UINT16 Reserved;
-//EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];
+ EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;
+ UINT16 MemoryControllerIdentifier;
+ UINT16 Reserved;
+ // EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];
} EFI_ACPI_6_4_PMTT_MEMORY_CONTROLLER_TYPE_DATA;
///
/// DIMM Type Specific Data.
///
typedef struct {
- EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;
- UINT32 SmbiosHandle;
+ EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;
+ UINT32 SmbiosHandle;
} EFI_ACPI_6_4_PMTT_DIMM_TYPE_SPECIFIC_DATA;
///
/// Vendor Specific Type Data.
///
typedef struct {
- EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;
- UINT8 TypeUuid[16];
-//EFI_ACPI_6_4_PMTT_VENDOR_SPECIFIC_TYPE_DATA VendorSpecificData[];
-//EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];
+ EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;
+ UINT8 TypeUuid[16];
+ // EFI_ACPI_6_4_PMTT_VENDOR_SPECIFIC_TYPE_DATA VendorSpecificData[];
+ // EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];
} EFI_ACPI_6_4_PMTT_VENDOR_SPECIFIC_TYPE_DATA;
///
/// Boot Graphics Resource Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
///
/// 2-bytes (16 bit) version ID. This value must be 1.
///
- UINT16 Version;
+ UINT16 Version;
///
/// 1-byte status field indicating current status about the table.
/// Bits[7:3] = Reserved (must be zero)
@@ -1139,47 +1139,47 @@ typedef struct {
/// Bit [0] = Displayed. A one indicates the boot image graphic is
/// displayed.
///
- UINT8 Status;
+ UINT8 Status;
///
/// 1-byte enumerated type field indicating format of the image.
/// 0 = Bitmap
/// 1 - 255 Reserved (for future use)
///
- UINT8 ImageType;
+ UINT8 ImageType;
///
/// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
/// of the image bitmap.
///
- UINT64 ImageAddress;
+ UINT64 ImageAddress;
///
/// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
/// (X, Y) display offset of the top left corner of the boot image.
/// The top left corner of the display is at offset (0, 0).
///
- UINT32 ImageOffsetX;
+ UINT32 ImageOffsetX;
///
/// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
/// (X, Y) display offset of the top left corner of the boot image.
/// The top left corner of the display is at offset (0, 0).
///
- UINT32 ImageOffsetY;
+ UINT32 ImageOffsetY;
} EFI_ACPI_6_4_BOOT_GRAPHICS_RESOURCE_TABLE;
///
/// BGRT Revision
///
-#define EFI_ACPI_6_4_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+#define EFI_ACPI_6_4_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
///
/// BGRT Version
///
-#define EFI_ACPI_6_4_BGRT_VERSION 0x01
+#define EFI_ACPI_6_4_BGRT_VERSION 0x01
///
/// BGRT Status
///
-#define EFI_ACPI_6_4_BGRT_STATUS_NOT_DISPLAYED 0x00
-#define EFI_ACPI_6_4_BGRT_STATUS_DISPLAYED 0x01
+#define EFI_ACPI_6_4_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_6_4_BGRT_STATUS_DISPLAYED 0x01
///
/// BGRT Image Type
@@ -1189,26 +1189,26 @@ typedef struct {
///
/// FPDT Version (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+#define EFI_ACPI_6_4_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
///
/// FPDT Performance Record Types
///
-#define EFI_ACPI_6_4_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
-#define EFI_ACPI_6_4_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
+#define EFI_ACPI_6_4_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
+#define EFI_ACPI_6_4_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
///
/// FPDT Performance Record Revision
///
-#define EFI_ACPI_6_4_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
-#define EFI_ACPI_6_4_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+#define EFI_ACPI_6_4_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
+#define EFI_ACPI_6_4_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
///
/// FPDT Runtime Performance Record Types
///
-#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
-#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
-#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
+#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
+#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
+#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
///
/// FPDT Runtime Performance Record Revision
@@ -1221,77 +1221,77 @@ typedef struct {
/// FPDT Performance Record header
///
typedef struct {
- UINT16 Type;
- UINT8 Length;
- UINT8 Revision;
+ UINT16 Type;
+ UINT8 Length;
+ UINT8 Revision;
} EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER;
///
/// FPDT Performance Table header
///
typedef struct {
- UINT32 Signature;
- UINT32 Length;
+ UINT32 Signature;
+ UINT32 Length;
} EFI_ACPI_6_4_FPDT_PERFORMANCE_TABLE_HEADER;
///
/// FPDT Firmware Basic Boot Performance Pointer Record Structure
///
typedef struct {
- EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
///
/// 64-bit processor-relative physical address of the Basic Boot Performance Table.
///
- UINT64 BootPerformanceTablePointer;
+ UINT64 BootPerformanceTablePointer;
} EFI_ACPI_6_4_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
///
/// FPDT S3 Performance Table Pointer Record Structure
///
typedef struct {
- EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
///
/// 64-bit processor-relative physical address of the S3 Performance Table.
///
- UINT64 S3PerformanceTablePointer;
+ UINT64 S3PerformanceTablePointer;
} EFI_ACPI_6_4_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
///
/// FPDT Firmware Basic Boot Performance Record Structure
///
typedef struct {
- EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;
- UINT32 Reserved;
+ EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
///
/// Timer value logged at the beginning of firmware image execution.
/// This may not always be zero or near zero.
///
- UINT64 ResetEnd;
+ UINT64 ResetEnd;
///
/// Timer value logged just prior to loading the OS boot loader into memory.
/// For non-UEFI compatible boots, this field must be zero.
///
- UINT64 OsLoaderLoadImageStart;
+ UINT64 OsLoaderLoadImageStart;
///
/// Timer value logged just prior to launching the previously loaded OS boot loader image.
/// For non-UEFI compatible boots, the timer value logged will be just prior
/// to the INT 19h handler invocation.
///
- UINT64 OsLoaderStartImageStart;
+ UINT64 OsLoaderStartImageStart;
///
/// Timer value logged at the point when the OS loader calls the
/// ExitBootServices function for UEFI compatible firmware.
/// For non-UEFI compatible boots, this field must be zero.
///
- UINT64 ExitBootServicesEntry;
+ UINT64 ExitBootServicesEntry;
///
/// Timer value logged at the point just prior towhen the OS loader gaining
/// control back from calls the ExitBootServices function for UEFI compatible firmware.
/// For non-UEFI compatible boots, this field must be zero.
///
- UINT64 ExitBootServicesExit;
+ UINT64 ExitBootServicesExit;
} EFI_ACPI_6_4_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
///
@@ -1303,7 +1303,7 @@ typedef struct {
// FPDT Firmware Basic Boot Performance Table
//
typedef struct {
- EFI_ACPI_6_4_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ EFI_ACPI_6_4_FPDT_PERFORMANCE_TABLE_HEADER Header;
//
// one or more Performance Records.
//
@@ -1318,7 +1318,7 @@ typedef struct {
// FPDT Firmware S3 Boot Performance Table
//
typedef struct {
- EFI_ACPI_6_4_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ EFI_ACPI_6_4_FPDT_PERFORMANCE_TABLE_HEADER Header;
//
// one or more Performance Records.
//
@@ -1328,147 +1328,147 @@ typedef struct {
/// FPDT Basic S3 Resume Performance Record
///
typedef struct {
- EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;
///
/// A count of the number of S3 resume cycles since the last full boot sequence.
///
- UINT32 ResumeCount;
+ UINT32 ResumeCount;
///
/// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
/// OS waking vector. Only the most recent resume cycle's time is retained.
///
- UINT64 FullResume;
+ UINT64 FullResume;
///
/// Average timer value of all resume cycles logged since the last full boot
/// sequence, including the most recent resume. Note that the entire log of
/// timer values does not need to be retained in order to calculate this average.
///
- UINT64 AverageResume;
+ UINT64 AverageResume;
} EFI_ACPI_6_4_FPDT_S3_RESUME_RECORD;
///
/// FPDT Basic S3 Suspend Performance Record
///
typedef struct {
- EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;
///
/// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
/// Only the most recent suspend cycle's timer value is retained.
///
- UINT64 SuspendStart;
+ UINT64 SuspendStart;
///
/// Timer value recorded at the final firmware write to SLP_TYP (or other
/// mechanism) used to trigger hardware entry to S3.
/// Only the most recent suspend cycle's timer value is retained.
///
- UINT64 SuspendEnd;
+ UINT64 SuspendEnd;
} EFI_ACPI_6_4_FPDT_S3_SUSPEND_RECORD;
///
/// Firmware Performance Record Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
} EFI_ACPI_6_4_FIRMWARE_PERFORMANCE_RECORD_TABLE;
///
/// Generic Timer Description Table definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 CntControlBasePhysicalAddress;
- UINT32 Reserved;
- UINT32 SecurePL1TimerGSIV;
- UINT32 SecurePL1TimerFlags;
- UINT32 NonSecurePL1TimerGSIV;
- UINT32 NonSecurePL1TimerFlags;
- UINT32 VirtualTimerGSIV;
- UINT32 VirtualTimerFlags;
- UINT32 NonSecurePL2TimerGSIV;
- UINT32 NonSecurePL2TimerFlags;
- UINT64 CntReadBasePhysicalAddress;
- UINT32 PlatformTimerCount;
- UINT32 PlatformTimerOffset;
- UINT32 VirtualPL2TimerGSIV;
- UINT32 VirtualPL2TimerFlags;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 CntControlBasePhysicalAddress;
+ UINT32 Reserved;
+ UINT32 SecurePL1TimerGSIV;
+ UINT32 SecurePL1TimerFlags;
+ UINT32 NonSecurePL1TimerGSIV;
+ UINT32 NonSecurePL1TimerFlags;
+ UINT32 VirtualTimerGSIV;
+ UINT32 VirtualTimerFlags;
+ UINT32 NonSecurePL2TimerGSIV;
+ UINT32 NonSecurePL2TimerFlags;
+ UINT64 CntReadBasePhysicalAddress;
+ UINT32 PlatformTimerCount;
+ UINT32 PlatformTimerOffset;
+ UINT32 VirtualPL2TimerGSIV;
+ UINT32 VirtualPL2TimerFlags;
} EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE;
///
/// GTDT Version (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x03
+#define EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x03
///
/// Timer Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_4_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
-#define EFI_ACPI_6_4_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
-#define EFI_ACPI_6_4_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2
+#define EFI_ACPI_6_4_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_4_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_4_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2
///
/// Platform Timer Type
///
-#define EFI_ACPI_6_4_GTDT_GT_BLOCK 0
-#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG 1
+#define EFI_ACPI_6_4_GTDT_GT_BLOCK 0
+#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG 1
///
/// GT Block Structure
///
typedef struct {
- UINT8 Type;
- UINT16 Length;
- UINT8 Reserved;
- UINT64 CntCtlBase;
- UINT32 GTBlockTimerCount;
- UINT32 GTBlockTimerOffset;
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 CntCtlBase;
+ UINT32 GTBlockTimerCount;
+ UINT32 GTBlockTimerOffset;
} EFI_ACPI_6_4_GTDT_GT_BLOCK_STRUCTURE;
///
/// GT Block Timer Structure
///
typedef struct {
- UINT8 GTFrameNumber;
- UINT8 Reserved[3];
- UINT64 CntBaseX;
- UINT64 CntEL0BaseX;
- UINT32 GTxPhysicalTimerGSIV;
- UINT32 GTxPhysicalTimerFlags;
- UINT32 GTxVirtualTimerGSIV;
- UINT32 GTxVirtualTimerFlags;
- UINT32 GTxCommonFlags;
+ UINT8 GTFrameNumber;
+ UINT8 Reserved[3];
+ UINT64 CntBaseX;
+ UINT64 CntEL0BaseX;
+ UINT32 GTxPhysicalTimerGSIV;
+ UINT32 GTxPhysicalTimerFlags;
+ UINT32 GTxVirtualTimerGSIV;
+ UINT32 GTxVirtualTimerFlags;
+ UINT32 GTxCommonFlags;
} EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_STRUCTURE;
///
/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
-#define EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
///
/// Common Flags Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_4_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0
-#define EFI_ACPI_6_4_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1
+#define EFI_ACPI_6_4_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0
+#define EFI_ACPI_6_4_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1
///
/// Arm Generic Watchdog Structure
///
typedef struct {
- UINT8 Type;
- UINT16 Length;
- UINT8 Reserved;
- UINT64 RefreshFramePhysicalAddress;
- UINT64 WatchdogControlFramePhysicalAddress;
- UINT32 WatchdogTimerGSIV;
- UINT32 WatchdogTimerFlags;
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 RefreshFramePhysicalAddress;
+ UINT64 WatchdogControlFramePhysicalAddress;
+ UINT32 WatchdogTimerGSIV;
+ UINT32 WatchdogTimerFlags;
} EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_STRUCTURE;
///
/// Arm Generic Watchdog Timer Flags. All other bits are reserved and must be 0.
///
-#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0
-#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1
-#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2
+#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2
//
// NVDIMM Firmware Interface Table definition.
@@ -1481,67 +1481,68 @@ typedef struct {
//
// NFIT Version (as defined in ACPI 6.4 spec.)
//
-#define EFI_ACPI_6_4_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
+#define EFI_ACPI_6_4_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
//
// Definition for NFIT Table Structure Types
//
-#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0
-#define EFI_ACPI_6_4_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1
-#define EFI_ACPI_6_4_NFIT_INTERLEAVE_STRUCTURE_TYPE 2
-#define EFI_ACPI_6_4_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3
-#define EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4
-#define EFI_ACPI_6_4_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5
-#define EFI_ACPI_6_4_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6
+#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0
+#define EFI_ACPI_6_4_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1
+#define EFI_ACPI_6_4_NFIT_INTERLEAVE_STRUCTURE_TYPE 2
+#define EFI_ACPI_6_4_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3
+#define EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4
+#define EFI_ACPI_6_4_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5
+#define EFI_ACPI_6_4_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6
+#define EFI_ACPI_6_4_NFIT_PLATFORM_CAPABILITIES_STRUCTURE_TYPE 7
//
// Definition for NFIT Structure Header
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
+ UINT16 Type;
+ UINT16 Length;
} EFI_ACPI_6_4_NFIT_STRUCTURE_HEADER;
//
// Definition for System Physical Address Range Structure
//
-#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0
-#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1
-#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_SPA_LOCATION_COOKIE_VALID BIT2
+#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0
+#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1
+#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_SPA_LOCATION_COOKIE_VALID BIT2
-#define EFI_ACPI_6_4_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
-#define EFI_ACPI_6_4_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
-#define EFI_ACPI_6_4_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
-#define EFI_ACPI_6_4_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
-#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
-#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
-#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
-#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
+#define EFI_ACPI_6_4_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
+#define EFI_ACPI_6_4_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
+#define EFI_ACPI_6_4_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
+#define EFI_ACPI_6_4_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
+#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
+#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
+#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
+#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT16 SPARangeStructureIndex;
- UINT16 Flags;
- UINT32 Reserved_8;
- UINT32 ProximityDomain;
- GUID AddressRangeTypeGUID;
- UINT64 SystemPhysicalAddressRangeBase;
- UINT64 SystemPhysicalAddressRangeLength;
- UINT64 AddressRangeMemoryMappingAttribute;
- UINT64 SPALocationCookie;
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 SPARangeStructureIndex;
+ UINT16 Flags;
+ UINT32 Reserved_8;
+ UINT32 ProximityDomain;
+ GUID AddressRangeTypeGUID;
+ UINT64 SystemPhysicalAddressRangeBase;
+ UINT64 SystemPhysicalAddressRangeLength;
+ UINT64 AddressRangeMemoryMappingAttribute;
+ UINT64 SPALocationCookie;
} EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;
//
// Definition for Memory Device to System Physical Address Range Mapping Structure
//
typedef struct {
- UINT32 DIMMNumber:4;
- UINT32 MemoryChannelNumber:4;
- UINT32 MemoryControllerID:4;
- UINT32 SocketID:4;
- UINT32 NodeControllerID:12;
- UINT32 Reserved_28:4;
+ UINT32 DIMMNumber : 4;
+ UINT32 MemoryChannelNumber : 4;
+ UINT32 MemoryControllerID : 4;
+ UINT32 SocketID : 4;
+ UINT32 NodeControllerID : 12;
+ UINT32 Reserved_28 : 4;
} EFI_ACPI_6_4_NFIT_DEVICE_HANDLE;
#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0
@@ -1553,254 +1554,276 @@ typedef struct {
#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6
typedef struct {
- UINT16 Type;
- UINT16 Length;
- EFI_ACPI_6_4_NFIT_DEVICE_HANDLE NFITDeviceHandle;
- UINT16 NVDIMMPhysicalID;
- UINT16 NVDIMMRegionID;
- UINT16 SPARangeStructureIndex ;
- UINT16 NVDIMMControlRegionStructureIndex;
- UINT64 NVDIMMRegionSize;
- UINT64 RegionOffset;
- UINT64 NVDIMMPhysicalAddressRegionBase;
- UINT16 InterleaveStructureIndex;
- UINT16 InterleaveWays;
- UINT16 NVDIMMStateFlags;
- UINT16 Reserved_46;
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_4_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NVDIMMPhysicalID;
+ UINT16 NVDIMMRegionID;
+ UINT16 SPARangeStructureIndex;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT64 NVDIMMRegionSize;
+ UINT64 RegionOffset;
+ UINT64 NVDIMMPhysicalAddressRegionBase;
+ UINT16 InterleaveStructureIndex;
+ UINT16 InterleaveWays;
+ UINT16 NVDIMMStateFlags;
+ UINT16 Reserved_46;
} EFI_ACPI_6_4_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;
//
// Definition for Interleave Structure
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT16 InterleaveStructureIndex;
- UINT16 Reserved_6;
- UINT32 NumberOfLines;
- UINT32 LineSize;
-//UINT32 LineOffset[NumberOfLines];
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 InterleaveStructureIndex;
+ UINT16 Reserved_6;
+ UINT32 NumberOfLines;
+ UINT32 LineSize;
+ // UINT32 LineOffset[NumberOfLines];
} EFI_ACPI_6_4_NFIT_INTERLEAVE_STRUCTURE;
//
// Definition for SMBIOS Management Information Structure
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT32 Reserved_4;
-//UINT8 Data[];
+ UINT16 Type;
+ UINT16 Length;
+ UINT32 Reserved_4;
+ // UINT8 Data[];
} EFI_ACPI_6_4_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;
//
// Definition for NVDIMM Control Region Structure
//
-#define EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0
+#define EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0
-#define EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0
+#define EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT16 NVDIMMControlRegionStructureIndex;
- UINT16 VendorID;
- UINT16 DeviceID;
- UINT16 RevisionID;
- UINT16 SubsystemVendorID;
- UINT16 SubsystemDeviceID;
- UINT16 SubsystemRevisionID;
- UINT8 ValidFields;
- UINT8 ManufacturingLocation;
- UINT16 ManufacturingDate;
- UINT8 Reserved_22[2];
- UINT32 SerialNumber;
- UINT16 RegionFormatInterfaceCode;
- UINT16 NumberOfBlockControlWindows;
- UINT64 SizeOfBlockControlWindow;
- UINT64 CommandRegisterOffsetInBlockControlWindow;
- UINT64 SizeOfCommandRegisterInBlockControlWindows;
- UINT64 StatusRegisterOffsetInBlockControlWindow;
- UINT64 SizeOfStatusRegisterInBlockControlWindows;
- UINT16 NVDIMMControlRegionFlag;
- UINT8 Reserved_74[6];
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT8 ValidFields;
+ UINT8 ManufacturingLocation;
+ UINT16 ManufacturingDate;
+ UINT8 Reserved_22[2];
+ UINT32 SerialNumber;
+ UINT16 RegionFormatInterfaceCode;
+ UINT16 NumberOfBlockControlWindows;
+ UINT64 SizeOfBlockControlWindow;
+ UINT64 CommandRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfCommandRegisterInBlockControlWindows;
+ UINT64 StatusRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfStatusRegisterInBlockControlWindows;
+ UINT16 NVDIMMControlRegionFlag;
+ UINT8 Reserved_74[6];
} EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;
//
// Definition for NVDIMM Block Data Window Region Structure
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
- UINT16 NVDIMMControlRegionStructureIndex;
- UINT16 NumberOfBlockDataWindows;
- UINT64 BlockDataWindowStartOffset;
- UINT64 SizeOfBlockDataWindow;
- UINT64 BlockAccessibleMemoryCapacity;
- UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 NumberOfBlockDataWindows;
+ UINT64 BlockDataWindowStartOffset;
+ UINT64 SizeOfBlockDataWindow;
+ UINT64 BlockAccessibleMemoryCapacity;
+ UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;
} EFI_ACPI_6_4_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;
//
// Definition for Flush Hint Address Structure
//
typedef struct {
- UINT16 Type;
- UINT16 Length;
- EFI_ACPI_6_4_NFIT_DEVICE_HANDLE NFITDeviceHandle;
- UINT16 NumberOfFlushHintAddresses;
- UINT8 Reserved_10[6];
-//UINT64 FlushHintAddress[NumberOfFlushHintAddresses];
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_4_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NumberOfFlushHintAddresses;
+ UINT8 Reserved_10[6];
+ // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];
} EFI_ACPI_6_4_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;
+//
+// Definition for Platform Capabilities Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT8 HighestValidCapability;
+ UINT8 Reserved_5[3];
+ UINT32 Capabilities;
+ UINT8 Reserved_12[4];
+} EFI_ACPI_6_4_NFIT_PLATFORM_CAPABILITIES_STRUCTURE;
+
+#define EFI_ACPI_6_4_NFIT_PLATFORM_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT0
+#define EFI_ACPI_6_4_NFIT_PLATFORM_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT1
+#define EFI_ACPI_6_4_NFIT_PLATFORM_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT2
+
///
/// Secure DEVices Table (SDEV)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
} EFI_ACPI_6_4_SECURE_DEVICES_TABLE_HEADER;
///
/// SDEV Revision (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_SECURE_DEVICES_TABLE_REVISION 0x01
+#define EFI_ACPI_6_4_SECURE_DEVICES_TABLE_REVISION 0x01
///
/// Secure Device types
///
-#define EFI_ACPI_6_4_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00
-#define EFI_ACPI_6_4_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01
+#define EFI_ACPI_6_4_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00
+#define EFI_ACPI_6_4_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01
///
/// Secure Device flags
///
-#define EFI_ACPI_6_4_SDEV_FLAG_ALLOW_HANDOFF BIT0
-#define EFI_ACPI_6_4_SDEV_FLAG_SECURE_ACCESS_COMPONENTS_PRESENT BIT1
+#define EFI_ACPI_6_4_SDEV_FLAG_ALLOW_HANDOFF BIT0
+#define EFI_ACPI_6_4_SDEV_FLAG_SECURE_ACCESS_COMPONENTS_PRESENT BIT1
///
/// SDEV Structure Header
///
typedef struct {
- UINT8 Type;
- UINT8 Flags;
- UINT16 Length;
+ UINT8 Type;
+ UINT8 Flags;
+ UINT16 Length;
} EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER;
///
/// ACPI_NAMESPACE_DEVICE based Secure Device Structure
///
typedef struct {
- EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;
- UINT16 DeviceIdentifierOffset;
- UINT16 DeviceIdentifierLength;
- UINT16 VendorSpecificDataOffset;
- UINT16 VendorSpecificDataLength;
- UINT16 SecureAccessComponentsOffset;
- UINT16 SecureAccessComponentsLength;
+ EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;
+ UINT16 DeviceIdentifierOffset;
+ UINT16 DeviceIdentifierLength;
+ UINT16 VendorSpecificDataOffset;
+ UINT16 VendorSpecificDataLength;
+ UINT16 SecureAccessComponentsOffset;
+ UINT16 SecureAccessComponentsLength;
} EFI_ACPI_6_4_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE;
///
/// Secure Access Component Types
///
-#define EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_TYPE_IDENTIFICATION 0x00
-#define EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_TYPE_MEMORY 0x01
+#define EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_TYPE_IDENTIFICATION 0x00
+#define EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_TYPE_MEMORY 0x01
///
/// Identification Based Secure Access Component
///
typedef struct {
- EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;
- UINT16 HardwareIdentifierOffset;
- UINT16 HardwareIdentifierLength;
- UINT16 SubsystemIdentifierOffset;
- UINT16 SubsystemIdentifierLength;
- UINT16 HardwareRevision;
- UINT8 HardwareRevisionPresent;
- UINT8 ClassCodePresent;
- UINT8 PciCompatibleBaseClass;
- UINT8 PciCompatibleSubClass;
- UINT8 PciCompatibleProgrammingInterface;
+ EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;
+ UINT16 HardwareIdentifierOffset;
+ UINT16 HardwareIdentifierLength;
+ UINT16 SubsystemIdentifierOffset;
+ UINT16 SubsystemIdentifierLength;
+ UINT16 HardwareRevision;
+ UINT8 HardwareRevisionPresent;
+ UINT8 ClassCodePresent;
+ UINT8 PciCompatibleBaseClass;
+ UINT8 PciCompatibleSubClass;
+ UINT8 PciCompatibleProgrammingInterface;
} EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_IDENTIFICATION_STRUCTURE;
///
/// Memory-based Secure Access Component
///
typedef struct {
- EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;
- UINT32 Reserved;
- UINT64 MemoryAddressBase;
- UINT64 MemoryLength;
+ EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;
+ UINT32 Reserved;
+ UINT64 MemoryAddressBase;
+ UINT64 MemoryLength;
} EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_MEMORY_STRUCTURE;
///
/// PCIe Endpoint Device based Secure Device Structure
///
typedef struct {
- EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;
- UINT16 PciSegmentNumber;
- UINT16 StartBusNumber;
- UINT16 PciPathOffset;
- UINT16 PciPathLength;
- UINT16 VendorSpecificDataOffset;
- UINT16 VendorSpecificDataLength;
+ EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;
+ UINT16 PciSegmentNumber;
+ UINT16 StartBusNumber;
+ UINT16 PciPathOffset;
+ UINT16 PciPathLength;
+ UINT16 VendorSpecificDataOffset;
+ UINT16 VendorSpecificDataLength;
} EFI_ACPI_6_4_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE;
///
/// Boot Error Record Table (BERT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 BootErrorRegionLength;
- UINT64 BootErrorRegion;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 BootErrorRegionLength;
+ UINT64 BootErrorRegion;
} EFI_ACPI_6_4_BOOT_ERROR_RECORD_TABLE_HEADER;
///
/// BERT Version (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+#define EFI_ACPI_6_4_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
///
/// Boot Error Region Block Status Definition
///
typedef struct {
- UINT32 UncorrectableErrorValid:1;
- UINT32 CorrectableErrorValid:1;
- UINT32 MultipleUncorrectableErrors:1;
- UINT32 MultipleCorrectableErrors:1;
- UINT32 ErrorDataEntryCount:10;
- UINT32 Reserved:18;
+ UINT32 UncorrectableErrorValid : 1;
+ UINT32 CorrectableErrorValid : 1;
+ UINT32 MultipleUncorrectableErrors : 1;
+ UINT32 MultipleCorrectableErrors : 1;
+ UINT32 ErrorDataEntryCount : 10;
+ UINT32 Reserved : 18;
} EFI_ACPI_6_4_ERROR_BLOCK_STATUS;
///
/// Boot Error Region Definition
///
typedef struct {
- EFI_ACPI_6_4_ERROR_BLOCK_STATUS BlockStatus;
- UINT32 RawDataOffset;
- UINT32 RawDataLength;
- UINT32 DataLength;
- UINT32 ErrorSeverity;
+ EFI_ACPI_6_4_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
} EFI_ACPI_6_4_BOOT_ERROR_REGION_STRUCTURE;
//
// Boot Error Severity types
//
-#define EFI_ACPI_6_4_ERROR_SEVERITY_CORRECTABLE 0x00
+#define EFI_ACPI_6_4_ERROR_SEVERITY_RECOVERABLE 0x00
#define EFI_ACPI_6_4_ERROR_SEVERITY_FATAL 0x01
#define EFI_ACPI_6_4_ERROR_SEVERITY_CORRECTED 0x02
#define EFI_ACPI_6_4_ERROR_SEVERITY_NONE 0x03
+//
+// The term 'Correctable' is no longer being used as an error severity of the
+// reported error since ACPI Specification Version 5.1 Errata B.
+// The below macro is considered as deprecated and should no longer be used.
+//
+#define EFI_ACPI_6_4_ERROR_SEVERITY_CORRECTABLE 0x00
///
/// Generic Error Data Entry Definition
///
typedef struct {
- UINT8 SectionType[16];
- UINT32 ErrorSeverity;
- UINT16 Revision;
- UINT8 ValidationBits;
- UINT8 Flags;
- UINT32 ErrorDataLength;
- UINT8 FruId[16];
- UINT8 FruText[20];
- UINT8 Timestamp[8];
+ UINT8 SectionType[16];
+ UINT32 ErrorSeverity;
+ UINT16 Revision;
+ UINT8 ValidationBits;
+ UINT8 Flags;
+ UINT32 ErrorDataLength;
+ UINT8 FruId[16];
+ UINT8 FruText[20];
+ UINT8 Timestamp[8];
} EFI_ACPI_6_4_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
///
@@ -1812,14 +1835,14 @@ typedef struct {
/// HEST - Hardware Error Source Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 ErrorSourceCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 ErrorSourceCount;
} EFI_ACPI_6_4_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
///
/// HEST Version (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+#define EFI_ACPI_6_4_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
//
// Error Source structure types.
@@ -1837,237 +1860,237 @@ typedef struct {
//
// Error Source structure flags.
//
-#define EFI_ACPI_6_4_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
-#define EFI_ACPI_6_4_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
-#define EFI_ACPI_6_4_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)
+#define EFI_ACPI_6_4_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
+#define EFI_ACPI_6_4_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
+#define EFI_ACPI_6_4_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)
///
/// IA-32 Architecture Machine Check Exception Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT64 GlobalCapabilityInitData;
- UINT64 GlobalControlInitData;
- UINT8 NumberOfHardwareBanks;
- UINT8 Reserved1[7];
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT64 GlobalCapabilityInitData;
+ UINT64 GlobalControlInitData;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[7];
} EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
///
/// IA-32 Architecture Machine Check Bank Structure Definition
///
typedef struct {
- UINT8 BankNumber;
- UINT8 ClearStatusOnInitialization;
- UINT8 StatusDataFormat;
- UINT8 Reserved0;
- UINT32 ControlRegisterMsrAddress;
- UINT64 ControlInitData;
- UINT32 StatusRegisterMsrAddress;
- UINT32 AddressRegisterMsrAddress;
- UINT32 MiscRegisterMsrAddress;
+ UINT8 BankNumber;
+ UINT8 ClearStatusOnInitialization;
+ UINT8 StatusDataFormat;
+ UINT8 Reserved0;
+ UINT32 ControlRegisterMsrAddress;
+ UINT64 ControlInitData;
+ UINT32 StatusRegisterMsrAddress;
+ UINT32 AddressRegisterMsrAddress;
+ UINT32 MiscRegisterMsrAddress;
} EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
///
/// IA-32 Architecture Machine Check Bank Structure MCA data format
///
-#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
-#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
-#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
+#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
+#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
+#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
//
// Hardware Error Notification types. All other values are reserved
//
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_MCE 0x06
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_MCE 0x06
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B
///
/// Hardware Error Notification Configuration Write Enable Structure Definition
///
typedef struct {
- UINT16 Type:1;
- UINT16 PollInterval:1;
- UINT16 SwitchToPollingThresholdValue:1;
- UINT16 SwitchToPollingThresholdWindow:1;
- UINT16 ErrorThresholdValue:1;
- UINT16 ErrorThresholdWindow:1;
- UINT16 Reserved:10;
+ UINT16 Type : 1;
+ UINT16 PollInterval : 1;
+ UINT16 SwitchToPollingThresholdValue : 1;
+ UINT16 SwitchToPollingThresholdWindow : 1;
+ UINT16 ErrorThresholdValue : 1;
+ UINT16 ErrorThresholdWindow : 1;
+ UINT16 Reserved : 10;
} EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
///
/// Hardware Error Notification Structure Definition
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
- UINT32 PollInterval;
- UINT32 Vector;
- UINT32 SwitchToPollingThresholdValue;
- UINT32 SwitchToPollingThresholdWindow;
- UINT32 ErrorThresholdValue;
- UINT32 ErrorThresholdWindow;
+ UINT8 Type;
+ UINT8 Length;
+ EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
+ UINT32 PollInterval;
+ UINT32 Vector;
+ UINT32 SwitchToPollingThresholdValue;
+ UINT32 SwitchToPollingThresholdWindow;
+ UINT32 ErrorThresholdValue;
+ UINT32 ErrorThresholdWindow;
} EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
///
/// IA-32 Architecture Corrected Machine Check Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
- UINT8 NumberOfHardwareBanks;
- UINT8 Reserved1[3];
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
} EFI_ACPI_6_4_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
///
/// IA-32 Architecture NMI Error Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 MaxRawDataLength;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
} EFI_ACPI_6_4_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
///
/// PCI Express Root Port AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
- UINT32 RootErrorCommand;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 RootErrorCommand;
} EFI_ACPI_6_4_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
///
/// PCI Express Device AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
} EFI_ACPI_6_4_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
///
/// PCI Express Bridge AER Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT8 Reserved0[2];
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 Bus;
- UINT16 Device;
- UINT16 Function;
- UINT16 DeviceControl;
- UINT8 Reserved1[2];
- UINT32 UncorrectableErrorMask;
- UINT32 UncorrectableErrorSeverity;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
- UINT32 SecondaryUncorrectableErrorMask;
- UINT32 SecondaryUncorrectableErrorSeverity;
- UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 SecondaryUncorrectableErrorMask;
+ UINT32 SecondaryUncorrectableErrorSeverity;
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
} EFI_ACPI_6_4_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
///
/// Generic Hardware Error Source Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT16 RelatedSourceId;
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 MaxRawDataLength;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
- EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
- UINT32 ErrorStatusBlockLength;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
} EFI_ACPI_6_4_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
///
/// Generic Hardware Error Source Version 2 Structure Definition
///
typedef struct {
- UINT16 Type;
- UINT16 SourceId;
- UINT16 RelatedSourceId;
- UINT8 Flags;
- UINT8 Enabled;
- UINT32 NumberOfRecordsToPreAllocate;
- UINT32 MaxSectionsPerRecord;
- UINT32 MaxRawDataLength;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
- EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
- UINT32 ErrorStatusBlockLength;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;
- UINT64 ReadAckPreserve;
- UINT64 ReadAckWrite;
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;
+ UINT64 ReadAckPreserve;
+ UINT64 ReadAckWrite;
} EFI_ACPI_6_4_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;
///
/// Generic Error Status Definition
///
typedef struct {
- EFI_ACPI_6_4_ERROR_BLOCK_STATUS BlockStatus;
- UINT32 RawDataOffset;
- UINT32 RawDataLength;
- UINT32 DataLength;
- UINT32 ErrorSeverity;
+ EFI_ACPI_6_4_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
} EFI_ACPI_6_4_GENERIC_ERROR_STATUS_STRUCTURE;
///
@@ -2084,299 +2107,299 @@ typedef struct {
EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
UINT8 NumberOfHardwareBanks;
UINT8 Reserved1[3];
-} EFI_ACPI_6_4_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;;
+} EFI_ACPI_6_4_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;
///
/// HMAT - Heterogeneous Memory Attribute Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 Reserved[4];
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[4];
} EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;
///
/// HMAT Revision (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x02
+#define EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x02
///
/// HMAT types
///
-#define EFI_ACPI_6_4_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES 0x00
-#define EFI_ACPI_6_4_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01
-#define EFI_ACPI_6_4_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02
+#define EFI_ACPI_6_4_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES 0x00
+#define EFI_ACPI_6_4_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01
+#define EFI_ACPI_6_4_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02
///
/// HMAT Structure Header
///
typedef struct {
- UINT16 Type;
- UINT8 Reserved[2];
- UINT32 Length;
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
} EFI_ACPI_6_4_HMAT_STRUCTURE_HEADER;
///
/// Memory Proximity Domain Attributes Structure flags
///
typedef struct {
- UINT16 InitiatorProximityDomainValid:1;
- UINT16 Reserved:15;
+ UINT16 InitiatorProximityDomainValid : 1;
+ UINT16 Reserved : 15;
} EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS;
///
/// Memory Proximity Domain Attributes Structure
///
typedef struct {
- UINT16 Type;
- UINT8 Reserved[2];
- UINT32 Length;
- EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS Flags;
- UINT8 Reserved1[2];
- UINT32 InitiatorProximityDomain;
- UINT32 MemoryProximityDomain;
- UINT8 Reserved2[20];
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS Flags;
+ UINT8 Reserved1[2];
+ UINT32 InitiatorProximityDomain;
+ UINT32 MemoryProximityDomain;
+ UINT8 Reserved2[20];
} EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES;
///
/// System Locality Latency and Bandwidth Information Structure flags
///
typedef struct {
- UINT8 MemoryHierarchy:4;
- UINT8 AccessAttributes:2;
- UINT8 Reserved:2;
+ UINT8 MemoryHierarchy : 4;
+ UINT8 AccessAttributes : 2;
+ UINT8 Reserved : 2;
} EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS;
///
/// System Locality Latency and Bandwidth Information Structure
///
typedef struct {
- UINT16 Type;
- UINT8 Reserved[2];
- UINT32 Length;
- EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;
- UINT8 DataType;
- UINT8 MinTransferSize;
- UINT8 Reserved1;
- UINT32 NumberOfInitiatorProximityDomains;
- UINT32 NumberOfTargetProximityDomains;
- UINT8 Reserved2[4];
- UINT64 EntryBaseUnit;
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;
+ UINT8 DataType;
+ UINT8 MinTransferSize;
+ UINT8 Reserved1;
+ UINT32 NumberOfInitiatorProximityDomains;
+ UINT32 NumberOfTargetProximityDomains;
+ UINT8 Reserved2[4];
+ UINT64 EntryBaseUnit;
} EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO;
///
/// Memory Side Cache Information Structure cache attributes
///
typedef struct {
- UINT32 TotalCacheLevels:4;
- UINT32 CacheLevel:4;
- UINT32 CacheAssociativity:4;
- UINT32 WritePolicy:4;
- UINT32 CacheLineSize:16;
+ UINT32 TotalCacheLevels : 4;
+ UINT32 CacheLevel : 4;
+ UINT32 CacheAssociativity : 4;
+ UINT32 WritePolicy : 4;
+ UINT32 CacheLineSize : 16;
} EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES;
///
/// Memory Side Cache Information Structure
///
typedef struct {
- UINT16 Type;
- UINT8 Reserved[2];
- UINT32 Length;
- UINT32 MemoryProximityDomain;
- UINT8 Reserved1[4];
- UINT64 MemorySideCacheSize;
- EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;
- UINT8 Reserved2[2];
- UINT16 NumberOfSmbiosHandles;
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ UINT32 MemoryProximityDomain;
+ UINT8 Reserved1[4];
+ UINT64 MemorySideCacheSize;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;
+ UINT8 Reserved2[2];
+ UINT16 NumberOfSmbiosHandles;
} EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO;
///
/// ERST - Error Record Serialization Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 SerializationHeaderSize;
- UINT8 Reserved0[4];
- UINT32 InstructionEntryCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 SerializationHeaderSize;
+ UINT8 Reserved0[4];
+ UINT32 InstructionEntryCount;
} EFI_ACPI_6_4_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
///
/// ERST Version (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_4_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
///
/// ERST Serialization Actions
///
-#define EFI_ACPI_6_4_ERST_BEGIN_WRITE_OPERATION 0x00
-#define EFI_ACPI_6_4_ERST_BEGIN_READ_OPERATION 0x01
-#define EFI_ACPI_6_4_ERST_BEGIN_CLEAR_OPERATION 0x02
-#define EFI_ACPI_6_4_ERST_END_OPERATION 0x03
-#define EFI_ACPI_6_4_ERST_SET_RECORD_OFFSET 0x04
-#define EFI_ACPI_6_4_ERST_EXECUTE_OPERATION 0x05
-#define EFI_ACPI_6_4_ERST_CHECK_BUSY_STATUS 0x06
-#define EFI_ACPI_6_4_ERST_GET_COMMAND_STATUS 0x07
-#define EFI_ACPI_6_4_ERST_GET_RECORD_IDENTIFIER 0x08
-#define EFI_ACPI_6_4_ERST_SET_RECORD_IDENTIFIER 0x09
-#define EFI_ACPI_6_4_ERST_GET_RECORD_COUNT 0x0A
-#define EFI_ACPI_6_4_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
-#define EFI_ACPI_6_4_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
-#define EFI_ACPI_6_4_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
-#define EFI_ACPI_6_4_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
-#define EFI_ACPI_6_4_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10
+#define EFI_ACPI_6_4_ERST_BEGIN_WRITE_OPERATION 0x00
+#define EFI_ACPI_6_4_ERST_BEGIN_READ_OPERATION 0x01
+#define EFI_ACPI_6_4_ERST_BEGIN_CLEAR_OPERATION 0x02
+#define EFI_ACPI_6_4_ERST_END_OPERATION 0x03
+#define EFI_ACPI_6_4_ERST_SET_RECORD_OFFSET 0x04
+#define EFI_ACPI_6_4_ERST_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_4_ERST_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_4_ERST_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_4_ERST_GET_RECORD_IDENTIFIER 0x08
+#define EFI_ACPI_6_4_ERST_SET_RECORD_IDENTIFIER 0x09
+#define EFI_ACPI_6_4_ERST_GET_RECORD_COUNT 0x0A
+#define EFI_ACPI_6_4_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
+#define EFI_ACPI_6_4_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
+#define EFI_ACPI_6_4_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
+#define EFI_ACPI_6_4_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
+#define EFI_ACPI_6_4_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10
///
/// ERST Action Command Status
///
-#define EFI_ACPI_6_4_ERST_STATUS_SUCCESS 0x00
-#define EFI_ACPI_6_4_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
-#define EFI_ACPI_6_4_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
-#define EFI_ACPI_6_4_ERST_STATUS_FAILED 0x03
-#define EFI_ACPI_6_4_ERST_STATUS_RECORD_STORE_EMPTY 0x04
-#define EFI_ACPI_6_4_ERST_STATUS_RECORD_NOT_FOUND 0x05
+#define EFI_ACPI_6_4_ERST_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_4_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
+#define EFI_ACPI_6_4_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
+#define EFI_ACPI_6_4_ERST_STATUS_FAILED 0x03
+#define EFI_ACPI_6_4_ERST_STATUS_RECORD_STORE_EMPTY 0x04
+#define EFI_ACPI_6_4_ERST_STATUS_RECORD_NOT_FOUND 0x05
///
/// ERST Serialization Instructions
///
-#define EFI_ACPI_6_4_ERST_READ_REGISTER 0x00
-#define EFI_ACPI_6_4_ERST_READ_REGISTER_VALUE 0x01
-#define EFI_ACPI_6_4_ERST_WRITE_REGISTER 0x02
-#define EFI_ACPI_6_4_ERST_WRITE_REGISTER_VALUE 0x03
-#define EFI_ACPI_6_4_ERST_NOOP 0x04
-#define EFI_ACPI_6_4_ERST_LOAD_VAR1 0x05
-#define EFI_ACPI_6_4_ERST_LOAD_VAR2 0x06
-#define EFI_ACPI_6_4_ERST_STORE_VAR1 0x07
-#define EFI_ACPI_6_4_ERST_ADD 0x08
-#define EFI_ACPI_6_4_ERST_SUBTRACT 0x09
-#define EFI_ACPI_6_4_ERST_ADD_VALUE 0x0A
-#define EFI_ACPI_6_4_ERST_SUBTRACT_VALUE 0x0B
-#define EFI_ACPI_6_4_ERST_STALL 0x0C
-#define EFI_ACPI_6_4_ERST_STALL_WHILE_TRUE 0x0D
-#define EFI_ACPI_6_4_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
-#define EFI_ACPI_6_4_ERST_GOTO 0x0F
-#define EFI_ACPI_6_4_ERST_SET_SRC_ADDRESS_BASE 0x10
-#define EFI_ACPI_6_4_ERST_SET_DST_ADDRESS_BASE 0x11
-#define EFI_ACPI_6_4_ERST_MOVE_DATA 0x12
+#define EFI_ACPI_6_4_ERST_READ_REGISTER 0x00
+#define EFI_ACPI_6_4_ERST_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_4_ERST_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_4_ERST_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_4_ERST_NOOP 0x04
+#define EFI_ACPI_6_4_ERST_LOAD_VAR1 0x05
+#define EFI_ACPI_6_4_ERST_LOAD_VAR2 0x06
+#define EFI_ACPI_6_4_ERST_STORE_VAR1 0x07
+#define EFI_ACPI_6_4_ERST_ADD 0x08
+#define EFI_ACPI_6_4_ERST_SUBTRACT 0x09
+#define EFI_ACPI_6_4_ERST_ADD_VALUE 0x0A
+#define EFI_ACPI_6_4_ERST_SUBTRACT_VALUE 0x0B
+#define EFI_ACPI_6_4_ERST_STALL 0x0C
+#define EFI_ACPI_6_4_ERST_STALL_WHILE_TRUE 0x0D
+#define EFI_ACPI_6_4_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
+#define EFI_ACPI_6_4_ERST_GOTO 0x0F
+#define EFI_ACPI_6_4_ERST_SET_SRC_ADDRESS_BASE 0x10
+#define EFI_ACPI_6_4_ERST_SET_DST_ADDRESS_BASE 0x11
+#define EFI_ACPI_6_4_ERST_MOVE_DATA 0x12
///
/// ERST Instruction Flags
///
-#define EFI_ACPI_6_4_ERST_PRESERVE_REGISTER 0x01
+#define EFI_ACPI_6_4_ERST_PRESERVE_REGISTER 0x01
///
/// ERST Serialization Instruction Entry
///
typedef struct {
- UINT8 SerializationAction;
- UINT8 Instruction;
- UINT8 Flags;
- UINT8 Reserved0;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
- UINT64 Value;
- UINT64 Mask;
+ UINT8 SerializationAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
} EFI_ACPI_6_4_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
///
/// EINJ - Error Injection Table
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 InjectionHeaderSize;
- UINT8 InjectionFlags;
- UINT8 Reserved0[3];
- UINT32 InjectionEntryCount;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 InjectionHeaderSize;
+ UINT8 InjectionFlags;
+ UINT8 Reserved0[3];
+ UINT32 InjectionEntryCount;
} EFI_ACPI_6_4_ERROR_INJECTION_TABLE_HEADER;
///
/// EINJ Version (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_ERROR_INJECTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_4_ERROR_INJECTION_TABLE_REVISION 0x01
///
/// EINJ Error Injection Actions
///
-#define EFI_ACPI_6_4_EINJ_BEGIN_INJECTION_OPERATION 0x00
-#define EFI_ACPI_6_4_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
-#define EFI_ACPI_6_4_EINJ_SET_ERROR_TYPE 0x02
-#define EFI_ACPI_6_4_EINJ_GET_ERROR_TYPE 0x03
-#define EFI_ACPI_6_4_EINJ_END_OPERATION 0x04
-#define EFI_ACPI_6_4_EINJ_EXECUTE_OPERATION 0x05
-#define EFI_ACPI_6_4_EINJ_CHECK_BUSY_STATUS 0x06
-#define EFI_ACPI_6_4_EINJ_GET_COMMAND_STATUS 0x07
-#define EFI_ACPI_6_4_EINJ_TRIGGER_ERROR 0xFF
+#define EFI_ACPI_6_4_EINJ_BEGIN_INJECTION_OPERATION 0x00
+#define EFI_ACPI_6_4_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
+#define EFI_ACPI_6_4_EINJ_SET_ERROR_TYPE 0x02
+#define EFI_ACPI_6_4_EINJ_GET_ERROR_TYPE 0x03
+#define EFI_ACPI_6_4_EINJ_END_OPERATION 0x04
+#define EFI_ACPI_6_4_EINJ_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_4_EINJ_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_4_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_4_EINJ_TRIGGER_ERROR 0xFF
///
/// EINJ Action Command Status
///
-#define EFI_ACPI_6_4_EINJ_STATUS_SUCCESS 0x00
-#define EFI_ACPI_6_4_EINJ_STATUS_UNKNOWN_FAILURE 0x01
-#define EFI_ACPI_6_4_EINJ_STATUS_INVALID_ACCESS 0x02
+#define EFI_ACPI_6_4_EINJ_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_4_EINJ_STATUS_UNKNOWN_FAILURE 0x01
+#define EFI_ACPI_6_4_EINJ_STATUS_INVALID_ACCESS 0x02
///
/// EINJ Error Type Definition
///
-#define EFI_ACPI_6_4_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
-#define EFI_ACPI_6_4_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
-#define EFI_ACPI_6_4_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
-#define EFI_ACPI_6_4_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
-#define EFI_ACPI_6_4_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
-#define EFI_ACPI_6_4_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
-#define EFI_ACPI_6_4_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
-#define EFI_ACPI_6_4_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
-#define EFI_ACPI_6_4_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
-#define EFI_ACPI_6_4_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
-#define EFI_ACPI_6_4_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
-#define EFI_ACPI_6_4_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
+#define EFI_ACPI_6_4_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
+#define EFI_ACPI_6_4_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
+#define EFI_ACPI_6_4_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
+#define EFI_ACPI_6_4_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
+#define EFI_ACPI_6_4_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
+#define EFI_ACPI_6_4_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
+#define EFI_ACPI_6_4_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
+#define EFI_ACPI_6_4_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
+#define EFI_ACPI_6_4_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
+#define EFI_ACPI_6_4_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
+#define EFI_ACPI_6_4_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
+#define EFI_ACPI_6_4_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
///
/// EINJ Injection Instructions
///
-#define EFI_ACPI_6_4_EINJ_READ_REGISTER 0x00
-#define EFI_ACPI_6_4_EINJ_READ_REGISTER_VALUE 0x01
-#define EFI_ACPI_6_4_EINJ_WRITE_REGISTER 0x02
-#define EFI_ACPI_6_4_EINJ_WRITE_REGISTER_VALUE 0x03
-#define EFI_ACPI_6_4_EINJ_NOOP 0x04
+#define EFI_ACPI_6_4_EINJ_READ_REGISTER 0x00
+#define EFI_ACPI_6_4_EINJ_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_4_EINJ_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_4_EINJ_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_4_EINJ_NOOP 0x04
///
/// EINJ Instruction Flags
///
-#define EFI_ACPI_6_4_EINJ_PRESERVE_REGISTER 0x01
+#define EFI_ACPI_6_4_EINJ_PRESERVE_REGISTER 0x01
///
/// EINJ Injection Instruction Entry
///
typedef struct {
- UINT8 InjectionAction;
- UINT8 Instruction;
- UINT8 Flags;
- UINT8 Reserved0;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
- UINT64 Value;
- UINT64 Mask;
+ UINT8 InjectionAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
} EFI_ACPI_6_4_EINJ_INJECTION_INSTRUCTION_ENTRY;
///
/// EINJ Trigger Action Table
///
typedef struct {
- UINT32 HeaderSize;
- UINT32 Revision;
- UINT32 TableSize;
- UINT32 EntryCount;
+ UINT32 HeaderSize;
+ UINT32 Revision;
+ UINT32 TableSize;
+ UINT32 EntryCount;
} EFI_ACPI_6_4_EINJ_TRIGGER_ACTION_TABLE;
///
/// Platform Communications Channel Table (PCCT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 Flags;
- UINT64 Reserved;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Flags;
+ UINT64 Reserved;
} EFI_ACPI_6_4_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
///
/// PCCT Version (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02
+#define EFI_ACPI_6_4_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02
///
/// PCCT Global Flags
@@ -2386,36 +2409,36 @@ typedef struct {
//
// PCCT Subspace type
//
-#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_GENERIC 0x00
-#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01
-#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02
-#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03
-#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04
-#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_5_HW_REGISTERS_COMMUNICATIONS 0x05
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_GENERIC 0x00
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_5_HW_REGISTERS_COMMUNICATIONS 0x05
///
/// PCC Subspace Structure Header
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
+ UINT8 Type;
+ UINT8 Length;
} EFI_ACPI_6_4_PCCT_SUBSPACE_HEADER;
///
/// Generic Communications Subspace Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[6];
- UINT64 BaseAddress;
- UINT64 AddressLength;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
- UINT64 DoorbellPreserve;
- UINT64 DoorbellWrite;
- UINT32 NominalLatency;
- UINT32 MaximumPeriodicAccessRate;
- UINT16 MinimumRequestTurnaroundTime;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[6];
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
} EFI_ACPI_6_4_PCCT_SUBSPACE_GENERIC;
///
@@ -2423,18 +2446,18 @@ typedef struct {
///
typedef struct {
- UINT8 Command;
- UINT8 Reserved:7;
- UINT8 NotifyOnCompletion:1;
+ UINT8 Command;
+ UINT8 Reserved : 7;
+ UINT8 NotifyOnCompletion : 1;
} EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
typedef struct {
- UINT8 CommandComplete:1;
- UINT8 PlatformInterrupt:1;
- UINT8 Error:1;
- UINT8 PlatformNotification:1;
- UINT8 Reserved:4;
- UINT8 Reserved1;
+ UINT8 CommandComplete : 1;
+ UINT8 PlatformInterrupt : 1;
+ UINT8 Error : 1;
+ UINT8 PlatformNotification : 1;
+ UINT8 Reserved : 4;
+ UINT8 Reserved1;
} EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
typedef struct {
@@ -2443,78 +2466,78 @@ typedef struct {
EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;
} EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
-#define EFI_ACPI_6_4_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0
-#define EFI_ACPI_6_4_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1
///
/// Type 1 HW-Reduced Communications Subspace Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 PlatformInterrupt;
- UINT8 PlatformInterruptFlags;
- UINT8 Reserved;
- UINT64 BaseAddress;
- UINT64 AddressLength;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
- UINT64 DoorbellPreserve;
- UINT64 DoorbellWrite;
- UINT32 NominalLatency;
- UINT32 MaximumPeriodicAccessRate;
- UINT16 MinimumRequestTurnaroundTime;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
} EFI_ACPI_6_4_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
///
/// Type 2 HW-Reduced Communications Subspace Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 PlatformInterrupt;
- UINT8 PlatformInterruptFlags;
- UINT8 Reserved;
- UINT64 BaseAddress;
- UINT64 AddressLength;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
- UINT64 DoorbellPreserve;
- UINT64 DoorbellWrite;
- UINT32 NominalLatency;
- UINT32 MaximumPeriodicAccessRate;
- UINT16 MinimumRequestTurnaroundTime;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
- UINT64 PlatformInterruptAckPreserve;
- UINT64 PlatformInterruptAckWrite;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
+ UINT64 PlatformInterruptAckPreserve;
+ UINT64 PlatformInterruptAckWrite;
} EFI_ACPI_6_4_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
///
/// Type 3 Extended PCC Subspace Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT32 PlatformInterrupt;
- UINT8 PlatformInterruptFlags;
- UINT8 Reserved;
- UINT64 BaseAddress;
- UINT32 AddressLength;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
- UINT64 DoorbellPreserve;
- UINT64 DoorbellWrite;
- UINT32 NominalLatency;
- UINT32 MaximumPeriodicAccessRate;
- UINT32 MinimumRequestTurnaroundTime;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
- UINT64 PlatformInterruptAckPreserve;
- UINT64 PlatformInterruptAckSet;
- UINT8 Reserved1[8];
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;
- UINT64 CommandCompleteCheckMask;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;
- UINT64 CommandCompleteUpdatePreserve;
- UINT64 CommandCompleteUpdateSet;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;
- UINT64 ErrorStatusMask;
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT32 AddressLength;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT32 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
+ UINT64 PlatformInterruptAckPreserve;
+ UINT64 PlatformInterruptAckSet;
+ UINT8 Reserved1[8];
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;
+ UINT64 CommandCompleteCheckMask;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;
+ UINT64 CommandCompleteUpdatePreserve;
+ UINT64 CommandCompleteUpdateSet;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;
+ UINT64 ErrorStatusMask;
} EFI_ACPI_6_4_PCCT_SUBSPACE_3_EXTENDED_PCC;
///
@@ -2522,74 +2545,74 @@ typedef struct {
///
typedef EFI_ACPI_6_4_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_4_PCCT_SUBSPACE_4_EXTENDED_PCC;
-#define EFI_ACPI_6_4_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0
+#define EFI_ACPI_6_4_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0
typedef struct {
- UINT32 Signature;
- UINT32 Flags;
- UINT32 Length;
- UINT32 Command;
+ UINT32 Signature;
+ UINT32 Flags;
+ UINT32 Length;
+ UINT32 Command;
} EFI_ACPI_6_4_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER;
///
/// Type 5 HW Registers based Communications Subspace Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Version;
- UINT64 BaseAddress;
- UINT64 SharedMemoryRangeLength;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
- UINT64 DoorbellPreserve;
- UINT64 DoorbellWrite;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;
- UINT64 CommandCompleteCheckMask;
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;
- UINT64 ErrorStatusMask;
- UINT32 NominalLatency;
- UINT32 MinimumRequestTurnaroundTime;
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Version;
+ UINT64 BaseAddress;
+ UINT64 SharedMemoryRangeLength;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;
+ UINT64 CommandCompleteCheckMask;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;
+ UINT64 ErrorStatusMask;
+ UINT32 NominalLatency;
+ UINT32 MinimumRequestTurnaroundTime;
} EFI_ACPI_6_4_PCCT_SUBSPACE_5_HW_REGISTERS_COMMUNICATIONS;
///
/// Reduced PCC Subspace Shared Memory Region
///
typedef struct {
- UINT32 Signature;
-//UINT8 CommunicationSubspace[];
+ UINT32 Signature;
+ // UINT8 CommunicationSubspace[];
} EFI_6_4_PCCT_REDUCED_PCC_SUBSPACE_SHARED_MEMORY_REGION;
///
/// Platform Debug Trigger Table (PDTT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT8 TriggerCount;
- UINT8 Reserved[3];
- UINT32 TriggerIdentifierArrayOffset;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 TriggerCount;
+ UINT8 Reserved[3];
+ UINT32 TriggerIdentifierArrayOffset;
} EFI_ACPI_6_4_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER;
///
/// PDTT Revision (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00
+#define EFI_ACPI_6_4_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00
///
/// PDTT Platform Communication Channel Identifier Structure
///
typedef struct {
- UINT16 SubChannelIdentifer:8;
- UINT16 Runtime:1;
- UINT16 WaitForCompletion:1;
- UINT16 TriggerOrder:1;
- UINT16 Reserved:5;
+ UINT16 SubChannelIdentifer : 8;
+ UINT16 Runtime : 1;
+ UINT16 WaitForCompletion : 1;
+ UINT16 TriggerOrder : 1;
+ UINT16 Reserved : 5;
} EFI_ACPI_6_4_PDTT_PCC_IDENTIFIER;
///
/// PCC Commands Codes used by Platform Debug Trigger Table
///
-#define EFI_ACPI_6_4_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00
-#define EFI_ACPI_6_4_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01
+#define EFI_ACPI_6_4_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00
+#define EFI_ACPI_6_4_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01
///
/// PDTT Platform Communication Channel
@@ -2600,28 +2623,27 @@ typedef EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6_4_PDTT_
/// Processor Properties Topology Table (PPTT)
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;
///
/// PPTT Revision (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x03
+#define EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x03
///
/// PPTT types
///
-#define EFI_ACPI_6_4_PPTT_TYPE_PROCESSOR 0x00
-#define EFI_ACPI_6_4_PPTT_TYPE_CACHE 0x01
-#define EFI_ACPI_6_4_PPTT_TYPE_ID 0x02
+#define EFI_ACPI_6_4_PPTT_TYPE_PROCESSOR 0x00
+#define EFI_ACPI_6_4_PPTT_TYPE_CACHE 0x01
///
/// PPTT Structure Header
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[2];
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
} EFI_ACPI_6_4_PPTT_STRUCTURE_HEADER;
///
@@ -2642,132 +2664,119 @@ typedef struct {
/// Processor hierarchy node structure flags
///
typedef struct {
- UINT32 PhysicalPackage:1;
- UINT32 AcpiProcessorIdValid:1;
- UINT32 ProcessorIsAThread:1;
- UINT32 NodeIsALeaf:1;
- UINT32 IdenticalImplementation:1;
- UINT32 Reserved:27;
+ UINT32 PhysicalPackage : 1;
+ UINT32 AcpiProcessorIdValid : 1;
+ UINT32 ProcessorIsAThread : 1;
+ UINT32 NodeIsALeaf : 1;
+ UINT32 IdenticalImplementation : 1;
+ UINT32 Reserved : 27;
} EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_FLAGS;
///
/// Processor hierarchy node structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[2];
- EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;
- UINT32 Parent;
- UINT32 AcpiProcessorId;
- UINT32 NumberOfPrivateResources;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;
+ UINT32 Parent;
+ UINT32 AcpiProcessorId;
+ UINT32 NumberOfPrivateResources;
} EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR;
///
/// For PPTT struct cache flags
///
-#define EFI_ACPI_6_4_PPTT_CACHE_SIZE_INVALID 0x0
-#define EFI_ACPI_6_4_PPTT_CACHE_SIZE_VALID 0x1
-#define EFI_ACPI_6_4_PPTT_NUMBER_OF_SETS_INVALID 0x0
-#define EFI_ACPI_6_4_PPTT_NUMBER_OF_SETS_VALID 0x1
-#define EFI_ACPI_6_4_PPTT_ASSOCIATIVITY_INVALID 0x0
-#define EFI_ACPI_6_4_PPTT_ASSOCIATIVITY_VALID 0x1
-#define EFI_ACPI_6_4_PPTT_ALLOCATION_TYPE_INVALID 0x0
-#define EFI_ACPI_6_4_PPTT_ALLOCATION_TYPE_VALID 0x1
-#define EFI_ACPI_6_4_PPTT_CACHE_TYPE_INVALID 0x0
-#define EFI_ACPI_6_4_PPTT_CACHE_TYPE_VALID 0x1
-#define EFI_ACPI_6_4_PPTT_WRITE_POLICY_INVALID 0x0
-#define EFI_ACPI_6_4_PPTT_WRITE_POLICY_VALID 0x1
-#define EFI_ACPI_6_4_PPTT_LINE_SIZE_INVALID 0x0
-#define EFI_ACPI_6_4_PPTT_LINE_SIZE_VALID 0x1
+#define EFI_ACPI_6_4_PPTT_CACHE_SIZE_INVALID 0x0
+#define EFI_ACPI_6_4_PPTT_CACHE_SIZE_VALID 0x1
+#define EFI_ACPI_6_4_PPTT_NUMBER_OF_SETS_INVALID 0x0
+#define EFI_ACPI_6_4_PPTT_NUMBER_OF_SETS_VALID 0x1
+#define EFI_ACPI_6_4_PPTT_ASSOCIATIVITY_INVALID 0x0
+#define EFI_ACPI_6_4_PPTT_ASSOCIATIVITY_VALID 0x1
+#define EFI_ACPI_6_4_PPTT_ALLOCATION_TYPE_INVALID 0x0
+#define EFI_ACPI_6_4_PPTT_ALLOCATION_TYPE_VALID 0x1
+#define EFI_ACPI_6_4_PPTT_CACHE_TYPE_INVALID 0x0
+#define EFI_ACPI_6_4_PPTT_CACHE_TYPE_VALID 0x1
+#define EFI_ACPI_6_4_PPTT_WRITE_POLICY_INVALID 0x0
+#define EFI_ACPI_6_4_PPTT_WRITE_POLICY_VALID 0x1
+#define EFI_ACPI_6_4_PPTT_LINE_SIZE_INVALID 0x0
+#define EFI_ACPI_6_4_PPTT_LINE_SIZE_VALID 0x1
+#define EFI_ACPI_6_4_PPTT_CACHE_ID_INVALID 0x0
+#define EFI_ACPI_6_4_PPTT_CACHE_ID_VALID 0x1
///
/// Cache Type Structure flags
///
typedef struct {
- UINT32 SizePropertyValid:1;
- UINT32 NumberOfSetsValid:1;
- UINT32 AssociativityValid:1;
- UINT32 AllocationTypeValid:1;
- UINT32 CacheTypeValid:1;
- UINT32 WritePolicyValid:1;
- UINT32 LineSizeValid:1;
- UINT32 CacheIdValid:1;
- UINT32 Reserved:24;
+ UINT32 SizePropertyValid : 1;
+ UINT32 NumberOfSetsValid : 1;
+ UINT32 AssociativityValid : 1;
+ UINT32 AllocationTypeValid : 1;
+ UINT32 CacheTypeValid : 1;
+ UINT32 WritePolicyValid : 1;
+ UINT32 LineSizeValid : 1;
+ UINT32 CacheIdValid : 1;
+ UINT32 Reserved : 24;
} EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_FLAGS;
///
/// For cache attributes
///
-#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0
-#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1
-#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2
-#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0
-#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1
-#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2
-#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0
-#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1
///
/// Cache Type Structure cache attributes
///
typedef struct {
- UINT8 AllocationType:2;
- UINT8 CacheType:2;
- UINT8 WritePolicy:1;
- UINT8 Reserved:3;
+ UINT8 AllocationType : 2;
+ UINT8 CacheType : 2;
+ UINT8 WritePolicy : 1;
+ UINT8 Reserved : 3;
} EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_ATTRIBUTES;
///
/// Cache Type Structure
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[2];
- EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_FLAGS Flags;
- UINT32 NextLevelOfCache;
- UINT32 Size;
- UINT32 NumberOfSets;
- UINT8 Associativity;
- EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;
- UINT16 LineSize;
- UINT32 CacheId;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_FLAGS Flags;
+ UINT32 NextLevelOfCache;
+ UINT32 Size;
+ UINT32 NumberOfSets;
+ UINT8 Associativity;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;
+ UINT16 LineSize;
+ UINT32 CacheId;
} EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE;
-///
-/// ID structure
-///
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved[2];
- UINT32 VendorId;
- UINT64 Level1Id;
- UINT64 Level2Id;
- UINT16 MajorRev;
- UINT16 MinorRev;
- UINT16 SpinRev;
-} EFI_ACPI_6_4_PPTT_STRUCTURE_ID;
-
///
/// Platform Health Assessment Table (PHAT) Format
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
-//UINT8 PlatformTelemetryRecords[];
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ // UINT8 PlatformTelemetryRecords[];
} EFI_ACPI_6_4_PLATFORM_HEALTH_ASSESSMENT_TABLE;
-#define EFI_ACPI_6_4_PLATFORM_HEALTH_ASSESSMENT_TABLE_REVISION 0x01
+#define EFI_ACPI_6_4_PLATFORM_HEALTH_ASSESSMENT_TABLE_REVISION 0x01
///
/// PHAT Record Format
///
typedef struct {
- UINT16 PlatformHealthAssessmentRecordType;
- UINT16 RecordLength;
- UINT8 Revision;
-//UINT8 Data[];
+ UINT16 PlatformHealthAssessmentRecordType;
+ UINT16 RecordLength;
+ UINT8 Revision;
+ // UINT8 Data[];
} EFI_ACPI_6_4_PHAT_RECORD;
///
@@ -2780,38 +2789,38 @@ typedef struct {
/// PHAT Version Element
///
typedef struct {
- GUID ComponentId;
- UINT64 VersionValue;
- UINT32 ProducerId;
+ GUID ComponentId;
+ UINT64 VersionValue;
+ UINT32 ProducerId;
} EFI_ACPI_6_4_PHAT_VERSION_ELEMENT;
///
/// PHAT Firmware Version Data Record
///
typedef struct {
- UINT16 PlatformRecordType;
- UINT16 RecordLength;
- UINT8 Revision;
- UINT8 Reserved[3];
- UINT32 RecordCount;
-//UINT8 PhatVersionElement[];
+ UINT16 PlatformRecordType;
+ UINT16 RecordLength;
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ UINT32 RecordCount;
+ // UINT8 PhatVersionElement[];
} EFI_ACPI_6_4_PHAT_FIRMWARE_VERISON_DATA_RECORD;
-#define EFI_ACPI_6_4_PHAT_FIRMWARE_VERSION_DATA_RECORD_REVISION 0x01
+#define EFI_ACPI_6_4_PHAT_FIRMWARE_VERSION_DATA_RECORD_REVISION 0x01
///
/// Firmware Health Data Record Structure
///
typedef struct {
- UINT16 PlatformRecordType;
- UINT16 RecordLength;
- UINT8 Revision;
- UINT16 Reserved;
- UINT8 AmHealthy;
- GUID DeviceSignature;
- UINT32 DeviceSpecificDataOffset;
-//UINT8 DevicePath[];
-//UINT8 DeviceSpecificData[];
+ UINT16 PlatformRecordType;
+ UINT16 RecordLength;
+ UINT8 Revision;
+ UINT16 Reserved;
+ UINT8 AmHealthy;
+ GUID DeviceSignature;
+ UINT32 DeviceSpecificDataOffset;
+ // UINT8 DevicePath[];
+ // UINT8 DeviceSpecificData[];
} EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_STRUCTURE;
#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_REVISION 0x01
@@ -2819,10 +2828,10 @@ typedef struct {
///
/// Firmware Health Data Record device health state
///
-#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_ERRORS_FOUND 0x00
-#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_NO_ERRORS_FOUND 0x01
-#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_UNKNOWN 0x02
-#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_ADVISORY 0x03
+#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_ERRORS_FOUND 0x00
+#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_NO_ERRORS_FOUND 0x01
+#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_UNKNOWN 0x02
+#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_ADVISORY 0x03
//
// Known table signatures
@@ -2838,6 +2847,11 @@ typedef struct {
///
#define EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
+///
+/// "APMT" Arm Performance Monitoring Unit Table
+///
+#define EFI_ACPI_6_4_ARM_PERFORMANCE_MONITORING_UNIT_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'M', 'T')
+
///
/// "BERT" Boot Error Record Table
///
@@ -3071,7 +3085,7 @@ typedef struct {
///
/// "PHAT" Platform Health Assessment Table
///
-#define EFI_ACPI_6_4_PLATFORM_HEALTH_ASSESSMENT_TABLE_SIGNATURE SIGNATURE_32('P', 'H', 'A', 'T')
+#define EFI_ACPI_6_4_PLATFORM_HEALTH_ASSESSMENT_TABLE_SIGNATURE SIGNATURE_32('P', 'H', 'A', 'T')
///
/// "SDEI" Software Delegated Exceptions Interface Table
diff --git a/MdePkg/Include/IndustryStandard/Acpi65.h b/MdePkg/Include/IndustryStandard/Acpi65.h
new file mode 100644
index 00000000..d3805353
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/Acpi65.h
@@ -0,0 +1,3259 @@
+/** @file
+ ACPI 6.5 definitions from the ACPI Specification Revision 6.5 Aug, 2022.
+
+ Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2019 - 2023, ARM Ltd. All rights reserved.
+ Copyright (c) 2023, Loongson Technology Corporation Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef ACPI_6_5_H_
+#define ACPI_6_5_H_
+
+#include
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 6.5 Generic Address Space definition
+///
+typedef struct {
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
+} EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_6_5_SYSTEM_MEMORY 0x00
+#define EFI_ACPI_6_5_SYSTEM_IO 0x01
+#define EFI_ACPI_6_5_PCI_CONFIGURATION_SPACE 0x02
+#define EFI_ACPI_6_5_EMBEDDED_CONTROLLER 0x03
+#define EFI_ACPI_6_5_SMBUS 0x04
+#define EFI_ACPI_6_5_SYSTEM_CMOS 0x05
+#define EFI_ACPI_6_5_PCI_BAR_TARGET 0x06
+#define EFI_ACPI_6_5_IPMI 0x07
+#define EFI_ACPI_6_5_GENERAL_PURPOSE_IO 0x08
+#define EFI_ACPI_6_5_GENERIC_SERIAL_BUS 0x09
+#define EFI_ACPI_6_5_PLATFORM_COMMUNICATION_CHANNEL 0x0A
+#define EFI_ACPI_6_5_PLATFORM_RUNTIME_MECHANISM 0x0B
+#define EFI_ACPI_6_5_FUNCTIONAL_FIXED_HARDWARE 0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_6_5_UNDEFINED 0
+#define EFI_ACPI_6_5_BYTE 1
+#define EFI_ACPI_6_5_WORD 2
+#define EFI_ACPI_6_5_DWORD 3
+#define EFI_ACPI_6_5_QWORD 4
+
+//
+// ACPI 6.5 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
+} EFI_ACPI_6_5_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.5) says current value is 2
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_6_5_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT16 ArmBootArch;
+ UINT8 MinorVersion;
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
+ UINT64 HypervisorVendorIdentity;
+} EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06
+#define EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x05
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_6_5_PM_PROFILE_UNSPECIFIED 0
+#define EFI_ACPI_6_5_PM_PROFILE_DESKTOP 1
+#define EFI_ACPI_6_5_PM_PROFILE_MOBILE 2
+#define EFI_ACPI_6_5_PM_PROFILE_WORKSTATION 3
+#define EFI_ACPI_6_5_PM_PROFILE_ENTERPRISE_SERVER 4
+#define EFI_ACPI_6_5_PM_PROFILE_SOHO_SERVER 5
+#define EFI_ACPI_6_5_PM_PROFILE_APPLIANCE_PC 6
+#define EFI_ACPI_6_5_PM_PROFILE_PERFORMANCE_SERVER 7
+#define EFI_ACPI_6_5_PM_PROFILE_TABLET 8
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_5_LEGACY_DEVICES BIT0
+#define EFI_ACPI_6_5_8042 BIT1
+#define EFI_ACPI_6_5_VGA_NOT_PRESENT BIT2
+#define EFI_ACPI_6_5_MSI_NOT_SUPPORTED BIT3
+#define EFI_ACPI_6_5_PCIE_ASPM_CONTROLS BIT4
+#define EFI_ACPI_6_5_CMOS_RTC_NOT_PRESENT BIT5
+
+//
+// Fixed ACPI Description Table Arm Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_5_ARM_PSCI_COMPLIANT BIT0
+#define EFI_ACPI_6_5_ARM_PSCI_USE_HVC BIT1
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_5_WBINVD BIT0
+#define EFI_ACPI_6_5_WBINVD_FLUSH BIT1
+#define EFI_ACPI_6_5_PROC_C1 BIT2
+#define EFI_ACPI_6_5_P_LVL2_UP BIT3
+#define EFI_ACPI_6_5_PWR_BUTTON BIT4
+#define EFI_ACPI_6_5_SLP_BUTTON BIT5
+#define EFI_ACPI_6_5_FIX_RTC BIT6
+#define EFI_ACPI_6_5_RTC_S4 BIT7
+#define EFI_ACPI_6_5_TMR_VAL_EXT BIT8
+#define EFI_ACPI_6_5_DCK_CAP BIT9
+#define EFI_ACPI_6_5_RESET_REG_SUP BIT10
+#define EFI_ACPI_6_5_SEALED_CASE BIT11
+#define EFI_ACPI_6_5_HEADLESS BIT12
+#define EFI_ACPI_6_5_CPU_SW_SLP BIT13
+#define EFI_ACPI_6_5_PCI_EXP_WAK BIT14
+#define EFI_ACPI_6_5_USE_PLATFORM_CLOCK BIT15
+#define EFI_ACPI_6_5_S4_RTC_STS_VALID BIT16
+#define EFI_ACPI_6_5_REMOTE_POWER_ON_CAPABLE BIT17
+#define EFI_ACPI_6_5_FORCE_APIC_CLUSTER_MODEL BIT18
+#define EFI_ACPI_6_5_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+#define EFI_ACPI_6_5_HW_REDUCED_ACPI BIT20
+#define EFI_ACPI_6_5_LOW_POWER_S0_IDLE_CAPABLE BIT21
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved0[3];
+ UINT32 OspmFlags;
+ UINT8 Reserved1[24];
+} EFI_ACPI_6_5_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_5_S4BIOS_F BIT0
+#define EFI_ACPI_6_5_64BIT_WAKE_SUPPORTED_F BIT1
+
+///
+/// OSPM Enabled Firmware Control Structure Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_5_OSPM_64BIT_WAKE_F BIT0
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
+//
+#define EFI_ACPI_6_5_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_6_5_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Multiple APIC Description Table header definition. The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
+} EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x06
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_5_PCAT_COMPAT BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x18 and 0x7F are reserved and
+// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.
+//
+#define EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC 0x00
+#define EFI_ACPI_6_5_IO_APIC 0x01
+#define EFI_ACPI_6_5_INTERRUPT_SOURCE_OVERRIDE 0x02
+#define EFI_ACPI_6_5_NON_MASKABLE_INTERRUPT_SOURCE 0x03
+#define EFI_ACPI_6_5_LOCAL_APIC_NMI 0x04
+#define EFI_ACPI_6_5_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
+#define EFI_ACPI_6_5_IO_SAPIC 0x06
+#define EFI_ACPI_6_5_LOCAL_SAPIC 0x07
+#define EFI_ACPI_6_5_PLATFORM_INTERRUPT_SOURCES 0x08
+#define EFI_ACPI_6_5_PROCESSOR_LOCAL_X2APIC 0x09
+#define EFI_ACPI_6_5_LOCAL_X2APIC_NMI 0x0A
+#define EFI_ACPI_6_5_GIC 0x0B
+#define EFI_ACPI_6_5_GICD 0x0C
+#define EFI_ACPI_6_5_GIC_MSI_FRAME 0x0D
+#define EFI_ACPI_6_5_GICR 0x0E
+#define EFI_ACPI_6_5_GIC_ITS 0x0F
+#define EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP 0x10
+#define EFI_ACPI_6_5_CORE_PIC 0x11
+#define EFI_ACPI_6_5_LIO_PIC 0x12
+#define EFI_ACPI_6_5_HT_PIC 0x13
+#define EFI_ACPI_6_5_EIO_PIC 0x14
+#define EFI_ACPI_6_5_MSI_PIC 0x15
+#define EFI_ACPI_6_5_BIO_PIC 0x16
+#define EFI_ACPI_6_5_LPC_PIC 0x17
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT8 ApicId;
+ UINT32 Flags;
+} EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_5_LOCAL_APIC_ENABLED BIT0
+#define EFI_ACPI_6_5_LOCAL_APIC_ONLINE_CAPABLE BIT1
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
+} EFI_ACPI_6_5_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
+} EFI_ACPI_6_5_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
+} EFI_ACPI_6_5_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_5_POLARITY (3 << 0)
+#define EFI_ACPI_6_5_TRIGGER_MODE (3 << 2)
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
+} EFI_ACPI_6_5_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
+} EFI_ACPI_6_5_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
+} EFI_ACPI_6_5_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
+} EFI_ACPI_6_5_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
+} EFI_ACPI_6_5_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+} EFI_ACPI_6_5_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Platform Interrupt Source Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_5_CPEI_PROCESSOR_OVERRIDE BIT0
+
+///
+/// Processor Local x2APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 AcpiProcessorUid;
+} EFI_ACPI_6_5_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
+
+///
+/// Local x2APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 AcpiProcessorUid;
+ UINT8 LocalX2ApicLint;
+ UINT8 Reserved[3];
+} EFI_ACPI_6_5_LOCAL_X2APIC_NMI_STRUCTURE;
+
+///
+/// GIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 CPUInterfaceNumber;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ParkingProtocolVersion;
+ UINT32 PerformanceInterruptGsiv;
+ UINT64 ParkedAddress;
+ UINT64 PhysicalBaseAddress;
+ UINT64 GICV;
+ UINT64 GICH;
+ UINT32 VGICMaintenanceInterrupt;
+ UINT64 GICRBaseAddress;
+ UINT64 MPIDR;
+ UINT8 ProcessorPowerEfficiencyClass;
+ UINT8 Reserved2;
+ UINT16 SpeOverflowInterrupt;
+ UINT16 TrbeInterrupt;
+} EFI_ACPI_6_5_GIC_STRUCTURE;
+
+///
+/// GIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_5_GIC_ENABLED BIT0
+#define EFI_ACPI_6_5_PERFORMANCE_INTERRUPT_MODEL BIT1
+#define EFI_ACPI_6_5_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2
+#define EFI_ACPI_6_5_GIC_ONLINE_CAPABLE BIT3
+
+///
+/// GIC Distributor Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 SystemVectorBase;
+ UINT8 GicVersion;
+ UINT8 Reserved2[3];
+} EFI_ACPI_6_5_GIC_DISTRIBUTOR_STRUCTURE;
+
+///
+/// GIC Version
+///
+#define EFI_ACPI_6_5_GIC_V1 0x01
+#define EFI_ACPI_6_5_GIC_V2 0x02
+#define EFI_ACPI_6_5_GIC_V3 0x03
+#define EFI_ACPI_6_5_GIC_V4 0x04
+
+///
+/// GIC MSI Frame Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicMsiFrameId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Flags;
+ UINT16 SPICount;
+ UINT16 SPIBase;
+} EFI_ACPI_6_5_GIC_MSI_FRAME_STRUCTURE;
+
+///
+/// GIC MSI Frame Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_5_SPI_COUNT_BASE_SELECT BIT0
+
+///
+/// GICR Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 DiscoveryRangeBaseAddress;
+ UINT32 DiscoveryRangeLength;
+} EFI_ACPI_6_5_GICR_STRUCTURE;
+
+///
+/// GIC Interrupt Translation Service Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 GicItsId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Reserved2;
+} EFI_ACPI_6_5_GIC_ITS_STRUCTURE;
+
+///
+/// Multiprocessor Wakeup Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 MailBoxVersion;
+ UINT32 Reserved;
+ UINT64 MailBoxAddress;
+} EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP_STRUCTURE;
+
+///
+/// Multiprocessor Wakeup Mailbox Structure
+///
+typedef struct {
+ UINT16 Command;
+ UINT16 Reserved;
+ UINT32 AcpiId;
+ UINT64 WakeupVector;
+ UINT8 ReservedForOs[2032];
+ UINT8 ReservedForFirmware[2048];
+} EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP_MAILBOX_STRUCTURE;
+
+#define EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_NOOP 0x0000
+#define EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_WAKEUP 0x0001
+
+///
+/// Core Programmable Interrupt Controller
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Version;
+ UINT32 ProcessorId;
+ UINT32 CoreId;
+ UINT32 Flags;
+} EFI_ACPI_6_5_CORE_PIC_STRUCTURE;
+
+///
+/// Legacy I/O Programmable Interrupt Controller
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Version;
+ UINT64 Address;
+ UINT16 Size;
+ UINT8 Cascade[2];
+ UINT32 CascadeMap[2];
+} EFI_ACPI_6_5_LIO_PIC_STRUCTURE;
+
+///
+/// HyperTransport Programmable Interrupt Controller
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Version;
+ UINT64 Address;
+ UINT16 Size;
+ UINT8 Cascade[8];
+} EFI_ACPI_6_5_HT_PIC_STRUCTURE;
+
+///
+/// Extend I/O Programmable Interrupt Controller
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Version;
+ UINT8 Cascade;
+ UINT8 Node;
+ UINT64 NodeMap;
+} EFI_ACPI_6_5_EIO_PIC_STRUCTURE;
+
+///
+/// MSI Programmable Interrupt Controller
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Version;
+ UINT64 MsgAddress;
+ UINT32 Start;
+ UINT32 Count;
+} EFI_ACPI_6_5_MSI_PIC_STRUCTURE;
+
+///
+/// Bridge I/O Programmable Interrupt Controller
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Version;
+ UINT64 Address;
+ UINT16 Size;
+ UINT16 Id;
+ UINT16 GsiBase;
+} EFI_ACPI_6_5_BIO_PIC_STRUCTURE;
+
+///
+/// Low Pin Count Programmable Interrupt Controller
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Version;
+ UINT64 Address;
+ UINT16 Size;
+ UINT8 Cascade;
+} EFI_ACPI_6_5_LPC_PIC_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
+} EFI_ACPI_6_5_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
+} EFI_ACPI_6_5_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
+
+///
+/// System Resource Affinity Table (SRAT). The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; ///< Must be set to 1
+ UINT64 Reserved2;
+} EFI_ACPI_6_5_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+///
+/// SRAT Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03
+
+//
+// SRAT structure types.
+// All other values between 0x06 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00
+#define EFI_ACPI_6_5_MEMORY_AFFINITY 0x01
+#define EFI_ACPI_6_5_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02
+#define EFI_ACPI_6_5_GICC_AFFINITY 0x03
+#define EFI_ACPI_6_5_GIC_ITS_AFFINITY 0x04
+#define EFI_ACPI_6_5_GENERIC_INITIATOR_AFFINITY 0x05
+
+///
+/// Processor Local APIC/SAPIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT32 ClockDomain;
+} EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+///
+/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+///
+/// Memory Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
+} EFI_ACPI_6_5_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_6_5_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_6_5_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_6_5_MEMORY_NONVOLATILE (1 << 2)
+
+///
+/// Processor Local x2APIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1[2];
+ UINT32 ProximityDomain;
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+ UINT8 Reserved2[4];
+} EFI_ACPI_6_5_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+} EFI_ACPI_6_5_GICC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_5_GICC_ENABLED (1 << 0)
+
+///
+/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT8 Reserved[2];
+ UINT32 ItsId;
+} EFI_ACPI_6_5_GIC_ITS_AFFINITY_STRUCTURE;
+
+//
+// Generic Initiator Affinity Structure Device Handle Types
+// All other values between 0x02 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_6_5_ACPI_DEVICE_HANDLE 0x00
+#define EFI_ACPI_6_5_PCI_DEVICE_HANDLE 0x01
+
+///
+/// Device Handle - ACPI
+///
+typedef struct {
+ UINT64 AcpiHid;
+ UINT32 AcpiUid;
+ UINT8 Reserved[4];
+} EFI_ACPI_6_5_DEVICE_HANDLE_ACPI;
+
+///
+/// Device Handle - PCI
+///
+typedef struct {
+ UINT16 PciSegment;
+ UINT16 PciBdfNumber;
+ UINT8 Reserved[12];
+} EFI_ACPI_6_5_DEVICE_HANDLE_PCI;
+
+///
+/// Device Handle
+///
+typedef union {
+ EFI_ACPI_6_5_DEVICE_HANDLE_ACPI Acpi;
+ EFI_ACPI_6_5_DEVICE_HANDLE_PCI Pci;
+} EFI_ACPI_6_5_DEVICE_HANDLE;
+
+///
+/// Generic Initiator Affinity Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1;
+ UINT8 DeviceHandleType;
+ UINT32 ProximityDomain;
+ EFI_ACPI_6_5_DEVICE_HANDLE DeviceHandle;
+ UINT32 Flags;
+ UINT8 Reserved2[4];
+} EFI_ACPI_6_5_GENERIC_INITIATOR_AFFINITY_STRUCTURE;
+
+///
+/// Generic Initiator Affinity Structure Flags. All other bits are reserved
+/// and must be 0.
+///
+#define EFI_ACPI_6_5_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ENABLED BIT0
+#define EFI_ACPI_6_5_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ARCHITECTURAL_TRANSACTIONS BIT1
+
+///
+/// System Locality Distance Information Table (SLIT).
+/// The rest of the table is a matrix.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
+} EFI_ACPI_6_5_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+///
+/// SLIT Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01
+
+///
+/// Corrected Platform Error Polling Table (CPEP)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[8];
+} EFI_ACPI_6_5_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
+
+///
+/// CPEP Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+
+//
+// CPEP processor structure types.
+//
+#define EFI_ACPI_6_5_CPEP_PROCESSOR_APIC_SAPIC 0x00
+
+///
+/// Corrected Platform Error Polling Processor Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT32 PollingInterval;
+} EFI_ACPI_6_5_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
+
+///
+/// Maximum System Characteristics Table (MSCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 OffsetProxDomInfo;
+ UINT32 MaximumNumberOfProximityDomains;
+ UINT32 MaximumNumberOfClockDomains;
+ UINT64 MaximumPhysicalAddress;
+} EFI_ACPI_6_5_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
+
+///
+/// MSCT Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+
+///
+/// Maximum Proximity Domain Information Structure Definition
+///
+typedef struct {
+ UINT8 Revision;
+ UINT8 Length;
+ UINT32 ProximityDomainRangeLow;
+ UINT32 ProximityDomainRangeHigh;
+ UINT32 MaximumProcessorCapacity;
+ UINT64 MaximumMemoryCapacity;
+} EFI_ACPI_6_5_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
+
+///
+/// ACPI RAS Feature Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier[12];
+} EFI_ACPI_6_5_RAS_FEATURE_TABLE;
+
+///
+/// RASF Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_RAS_FEATURE_TABLE_REVISION 0x01
+
+///
+/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT16 Version;
+ UINT8 RASCapabilities[16];
+ UINT8 SetRASCapabilities[16];
+ UINT16 NumberOfRASFParameterBlocks;
+ UINT32 SetRASCapabilitiesStatus;
+} EFI_ACPI_6_5_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI RASF PCC command code
+///
+#define EFI_ACPI_6_5_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01
+
+///
+/// ACPI RASF Platform RAS Capabilities
+///
+#define EFI_ACPI_6_5_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0
+#define EFI_ACPI_6_5_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1
+#define EFI_ACPI_6_5_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2
+#define EFI_ACPI_6_5_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3
+#define EFI_ACPI_6_5_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4
+
+///
+/// ACPI RASF Parameter Block structure for PATROL_SCRUB
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 Version;
+ UINT16 Length;
+ UINT16 PatrolScrubCommand;
+ UINT64 RequestedAddressRange[2];
+ UINT64 ActualAddressRange[2];
+ UINT16 Flags;
+ UINT8 RequestedSpeed;
+} EFI_ACPI_6_5_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
+
+///
+/// ACPI RASF Patrol Scrub command
+///
+#define EFI_ACPI_6_5_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
+#define EFI_ACPI_6_5_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
+#define EFI_ACPI_6_5_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
+
+///
+/// Memory Power State Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier;
+ UINT8 Reserved[3];
+ // Memory Power Node Structure
+ // Memory Power State Characteristics
+} EFI_ACPI_6_5_MEMORY_POWER_STATUS_TABLE;
+
+///
+/// MPST Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+
+///
+/// MPST Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT32 MemoryPowerCommandRegister;
+ UINT32 MemoryPowerStatusRegister;
+ UINT32 PowerStateId;
+ UINT32 MemoryPowerNodeId;
+ UINT64 MemoryEnergyConsumed;
+ UINT64 ExpectedAveragePowerComsuned;
+} EFI_ACPI_6_5_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI MPST PCC command code
+///
+#define EFI_ACPI_6_5_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03
+
+///
+/// ACPI MPST Memory Power command
+///
+#define EFI_ACPI_6_5_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
+#define EFI_ACPI_6_5_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
+#define EFI_ACPI_6_5_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
+#define EFI_ACPI_6_5_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
+
+///
+/// MPST Memory Power Node Table
+///
+typedef struct {
+ UINT8 PowerStateValue;
+ UINT8 PowerStateInformationIndex;
+} EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE;
+
+typedef struct {
+ UINT8 Flag;
+ UINT8 Reserved;
+ UINT16 MemoryPowerNodeId;
+ UINT32 Length;
+ UINT64 AddressBase;
+ UINT64 AddressLength;
+ UINT32 NumberOfPowerStates;
+ UINT32 NumberOfPhysicalComponents;
+ // EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+} EFI_ACPI_6_5_MPST_MEMORY_POWER_STRUCTURE;
+
+#define EFI_ACPI_6_5_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
+#define EFI_ACPI_6_5_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
+#define EFI_ACPI_6_5_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
+
+typedef struct {
+ UINT16 MemoryPowerNodeCount;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_5_MPST_MEMORY_POWER_NODE_TABLE;
+
+///
+/// MPST Memory Power State Characteristics Table
+///
+typedef struct {
+ UINT8 PowerStateStructureID;
+ UINT8 Flag;
+ UINT16 Reserved;
+ UINT32 AveragePowerConsumedInMPS0;
+ UINT32 RelativePowerSavingToMPS0;
+ UINT64 ExitLatencyToMPS0;
+} EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
+
+#define EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
+#define EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
+#define EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
+
+typedef struct {
+ UINT16 MemoryPowerStateCharacteristicsCount;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
+
+///
+/// Platform Memory Topology Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 NumberOfMemoryDevices;
+ // EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[NumberOfMemoryDevices];
+} EFI_ACPI_6_5_PLATFORM_MEMORY_TOPOLOGY_TABLE;
+
+///
+/// PMTT Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_MEMORY_TOPOLOGY_TABLE_REVISION 0x02
+
+///
+/// Common Memory Device.
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16 Length;
+ UINT16 Flags;
+ UINT16 Reserved1;
+ UINT32 NumberOfMemoryDevices;
+ // UINT8 TypeSpecificData[];
+ // EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[NumberOfMemoryDevices];
+} EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE;
+
+///
+/// Memory Device Type.
+///
+#define EFI_ACPI_6_5_PMTT_MEMORY_DEVICE_TYPE_SOCKET 0x0
+#define EFI_ACPI_6_5_PMTT_MEMORY_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
+#define EFI_ACPI_6_5_PMTT_MEMORY_DEVICE_TYPE_DIMM 0x2
+#define EFI_ACPI_6_5_PMTT_MEMORY_DEVICE_TYPE_VENDOR_SPECIFIC_TYPE 0xFF
+
+///
+/// Socket Type Data.
+///
+typedef struct {
+ EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;
+ UINT16 SocketIdentifier;
+ UINT16 Reserved;
+ // EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];
+} EFI_ACPI_6_5_PMTT_SOCKET_TYPE_DATA;
+
+///
+/// Memory Controller Type Data.
+///
+typedef struct {
+ EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;
+ UINT16 MemoryControllerIdentifier;
+ UINT16 Reserved;
+ // EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];
+} EFI_ACPI_6_5_PMTT_MEMORY_CONTROLLER_TYPE_DATA;
+
+///
+/// DIMM Type Specific Data.
+///
+typedef struct {
+ EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;
+ UINT32 SmbiosHandle;
+} EFI_ACPI_6_5_PMTT_DIMM_TYPE_SPECIFIC_DATA;
+
+///
+/// Vendor Specific Type Data.
+///
+typedef struct {
+ EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;
+ UINT8 TypeUuid[16];
+ // EFI_ACPI_6_5_PMTT_VENDOR_SPECIFIC_TYPE_DATA VendorSpecificData[];
+ // EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];
+} EFI_ACPI_6_5_PMTT_VENDOR_SPECIFIC_TYPE_DATA;
+
+///
+/// Boot Graphics Resource Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ ///
+ /// 2-bytes (16 bit) version ID. This value must be 1.
+ ///
+ UINT16 Version;
+ ///
+ /// 1-byte status field indicating current status about the table.
+ /// Bits[7:3] = Reserved (must be zero)
+ /// Bits[2:1] = Orientation Offset. These bits describe the clockwise
+ /// degree offset from the image's default orientation.
+ /// [00] = 0, no offset
+ /// [01] = 90
+ /// [10] = 180
+ /// [11] = 270
+ /// Bit [0] = Displayed. A one indicates the boot image graphic is
+ /// displayed.
+ ///
+ UINT8 Status;
+ ///
+ /// 1-byte enumerated type field indicating format of the image.
+ /// 0 = Bitmap
+ /// 1 - 255 Reserved (for future use)
+ ///
+ UINT8 ImageType;
+ ///
+ /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
+ /// of the image bitmap.
+ ///
+ UINT64 ImageAddress;
+ ///
+ /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
+ /// (X, Y) display offset of the top left corner of the boot image.
+ /// The top left corner of the display is at offset (0, 0).
+ ///
+ UINT32 ImageOffsetX;
+ ///
+ /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
+ /// (X, Y) display offset of the top left corner of the boot image.
+ /// The top left corner of the display is at offset (0, 0).
+ ///
+ UINT32 ImageOffsetY;
+} EFI_ACPI_6_5_BOOT_GRAPHICS_RESOURCE_TABLE;
+
+///
+/// BGRT Revision
+///
+#define EFI_ACPI_6_5_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+
+///
+/// BGRT Version
+///
+#define EFI_ACPI_6_5_BGRT_VERSION 0x01
+
+///
+/// BGRT Status
+///
+#define EFI_ACPI_6_5_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_6_5_BGRT_STATUS_DISPLAYED 0x01
+
+///
+/// BGRT Image Type
+///
+#define EFI_ACPI_6_5_BGRT_IMAGE_TYPE_BMP 0x00
+
+///
+/// FPDT Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+
+///
+/// FPDT Performance Record Types
+///
+#define EFI_ACPI_6_5_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
+#define EFI_ACPI_6_5_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
+
+///
+/// FPDT Performance Record Revision
+///
+#define EFI_ACPI_6_5_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
+#define EFI_ACPI_6_5_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+
+///
+/// FPDT Runtime Performance Record Types
+///
+#define EFI_ACPI_6_5_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
+#define EFI_ACPI_6_5_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
+#define EFI_ACPI_6_5_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
+
+///
+/// FPDT Runtime Performance Record Revision
+///
+#define EFI_ACPI_6_5_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01
+#define EFI_ACPI_6_5_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01
+#define EFI_ACPI_6_5_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02
+
+///
+/// FPDT Performance Record header
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Length;
+ UINT8 Revision;
+} EFI_ACPI_6_5_FPDT_PERFORMANCE_RECORD_HEADER;
+
+///
+/// FPDT Performance Table header
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_6_5_FPDT_PERFORMANCE_TABLE_HEADER;
+
+///
+/// FPDT Firmware Basic Boot Performance Pointer Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_5_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// 64-bit processor-relative physical address of the Basic Boot Performance Table.
+ ///
+ UINT64 BootPerformanceTablePointer;
+} EFI_ACPI_6_5_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT S3 Performance Table Pointer Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_5_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// 64-bit processor-relative physical address of the S3 Performance Table.
+ ///
+ UINT64 S3PerformanceTablePointer;
+} EFI_ACPI_6_5_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_5_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// Timer value logged at the beginning of firmware image execution.
+ /// This may not always be zero or near zero.
+ ///
+ UINT64 ResetEnd;
+ ///
+ /// Timer value logged just prior to loading the OS boot loader into memory.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 OsLoaderLoadImageStart;
+ ///
+ /// Timer value logged just prior to launching the previously loaded OS boot loader image.
+ /// For non-UEFI compatible boots, the timer value logged will be just prior
+ /// to the INT 19h handler invocation.
+ ///
+ UINT64 OsLoaderStartImageStart;
+ ///
+ /// Timer value logged at the point when the OS loader calls the
+ /// ExitBootServices function for UEFI compatible firmware.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 ExitBootServicesEntry;
+ ///
+ /// Timer value logged at the point just prior towhen the OS loader gaining
+ /// control back from calls the ExitBootServices function for UEFI compatible firmware.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 ExitBootServicesExit;
+} EFI_ACPI_6_5_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Table signature
+///
+#define EFI_ACPI_6_5_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T')
+
+//
+// FPDT Firmware Basic Boot Performance Table
+//
+typedef struct {
+ EFI_ACPI_6_5_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ //
+ // one or more Performance Records.
+ //
+} EFI_ACPI_6_5_FPDT_FIRMWARE_BASIC_BOOT_TABLE;
+
+///
+/// FPDT "S3PT" S3 Performance Table
+///
+#define EFI_ACPI_6_5_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T')
+
+//
+// FPDT Firmware S3 Boot Performance Table
+//
+typedef struct {
+ EFI_ACPI_6_5_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ //
+ // one or more Performance Records.
+ //
+} EFI_ACPI_6_5_FPDT_FIRMWARE_S3_BOOT_TABLE;
+
+///
+/// FPDT Basic S3 Resume Performance Record
+///
+typedef struct {
+ EFI_ACPI_6_5_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ ///
+ /// A count of the number of S3 resume cycles since the last full boot sequence.
+ ///
+ UINT32 ResumeCount;
+ ///
+ /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
+ /// OS waking vector. Only the most recent resume cycle's time is retained.
+ ///
+ UINT64 FullResume;
+ ///
+ /// Average timer value of all resume cycles logged since the last full boot
+ /// sequence, including the most recent resume. Note that the entire log of
+ /// timer values does not need to be retained in order to calculate this average.
+ ///
+ UINT64 AverageResume;
+} EFI_ACPI_6_5_FPDT_S3_RESUME_RECORD;
+
+///
+/// FPDT Basic S3 Suspend Performance Record
+///
+typedef struct {
+ EFI_ACPI_6_5_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ ///
+ /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
+ /// Only the most recent suspend cycle's timer value is retained.
+ ///
+ UINT64 SuspendStart;
+ ///
+ /// Timer value recorded at the final firmware write to SLP_TYP (or other
+ /// mechanism) used to trigger hardware entry to S3.
+ /// Only the most recent suspend cycle's timer value is retained.
+ ///
+ UINT64 SuspendEnd;
+} EFI_ACPI_6_5_FPDT_S3_SUSPEND_RECORD;
+
+///
+/// Firmware Performance Record Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_5_FIRMWARE_PERFORMANCE_RECORD_TABLE;
+
+///
+/// Generic Timer Description Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 CntControlBasePhysicalAddress;
+ UINT32 Reserved;
+ UINT32 SecurePL1TimerGSIV;
+ UINT32 SecurePL1TimerFlags;
+ UINT32 NonSecurePL1TimerGSIV;
+ UINT32 NonSecurePL1TimerFlags;
+ UINT32 VirtualTimerGSIV;
+ UINT32 VirtualTimerFlags;
+ UINT32 NonSecurePL2TimerGSIV;
+ UINT32 NonSecurePL2TimerFlags;
+ UINT64 CntReadBasePhysicalAddress;
+ UINT32 PlatformTimerCount;
+ UINT32 PlatformTimerOffset;
+ UINT32 VirtualPL2TimerGSIV;
+ UINT32 VirtualPL2TimerFlags;
+} EFI_ACPI_6_5_GENERIC_TIMER_DESCRIPTION_TABLE;
+
+///
+/// GTDT Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x03
+
+///
+/// Timer Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_5_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_5_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_5_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2
+
+///
+/// Platform Timer Type
+///
+#define EFI_ACPI_6_5_GTDT_GT_BLOCK 0
+#define EFI_ACPI_6_5_GTDT_ARM_GENERIC_WATCHDOG 1
+
+///
+/// GT Block Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 CntCtlBase;
+ UINT32 GTBlockTimerCount;
+ UINT32 GTBlockTimerOffset;
+} EFI_ACPI_6_5_GTDT_GT_BLOCK_STRUCTURE;
+
+///
+/// GT Block Timer Structure
+///
+typedef struct {
+ UINT8 GTFrameNumber;
+ UINT8 Reserved[3];
+ UINT64 CntBaseX;
+ UINT64 CntEL0BaseX;
+ UINT32 GTxPhysicalTimerGSIV;
+ UINT32 GTxPhysicalTimerFlags;
+ UINT32 GTxVirtualTimerGSIV;
+ UINT32 GTxVirtualTimerFlags;
+ UINT32 GTxCommonFlags;
+} EFI_ACPI_6_5_GTDT_GT_BLOCK_TIMER_STRUCTURE;
+
+///
+/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_5_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_5_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+
+///
+/// Common Flags Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_5_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0
+#define EFI_ACPI_6_5_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1
+
+///
+/// Arm Generic Watchdog Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 RefreshFramePhysicalAddress;
+ UINT64 WatchdogControlFramePhysicalAddress;
+ UINT32 WatchdogTimerGSIV;
+ UINT32 WatchdogTimerFlags;
+} EFI_ACPI_6_5_GTDT_ARM_GENERIC_WATCHDOG_STRUCTURE;
+
+///
+/// Arm Generic Watchdog Timer Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_5_GTDT_ARM_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_5_GTDT_ARM_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_5_GTDT_ARM_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2
+
+//
+// NVDIMM Firmware Interface Table definition.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
+} EFI_ACPI_6_5_NVDIMM_FIRMWARE_INTERFACE_TABLE;
+
+//
+// NFIT Version (as defined in ACPI 6.5 spec.)
+//
+#define EFI_ACPI_6_5_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
+
+//
+// Definition for NFIT Table Structure Types
+//
+#define EFI_ACPI_6_5_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0
+#define EFI_ACPI_6_5_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1
+#define EFI_ACPI_6_5_NFIT_INTERLEAVE_STRUCTURE_TYPE 2
+#define EFI_ACPI_6_5_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3
+#define EFI_ACPI_6_5_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4
+#define EFI_ACPI_6_5_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5
+#define EFI_ACPI_6_5_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6
+#define EFI_ACPI_6_5_NFIT_PLATFORM_CAPABILITIES_STRUCTURE_TYPE 7
+
+//
+// Definition for NFIT Structure Header
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+} EFI_ACPI_6_5_NFIT_STRUCTURE_HEADER;
+
+//
+// Definition for System Physical Address Range Structure
+//
+#define EFI_ACPI_6_5_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0
+#define EFI_ACPI_6_5_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1
+#define EFI_ACPI_6_5_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_SPA_LOCATION_COOKIE_VALID BIT2
+
+#define EFI_ACPI_6_5_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
+#define EFI_ACPI_6_5_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
+#define EFI_ACPI_6_5_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
+#define EFI_ACPI_6_5_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
+#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x6.5B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
+#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
+#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
+#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
+
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 SPARangeStructureIndex;
+ UINT16 Flags;
+ UINT32 Reserved_8;
+ UINT32 ProximityDomain;
+ GUID AddressRangeTypeGUID;
+ UINT64 SystemPhysicalAddressRangeBase;
+ UINT64 SystemPhysicalAddressRangeLength;
+ UINT64 AddressRangeMemoryMappingAttribute;
+ UINT64 SPALocationCookie;
+} EFI_ACPI_6_5_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;
+
+//
+// Definition for Memory Device to System Physical Address Range Mapping Structure
+//
+typedef struct {
+ UINT32 DIMMNumber : 4;
+ UINT32 MemoryChannelNumber : 4;
+ UINT32 MemoryControllerID : 4;
+ UINT32 SocketID : 4;
+ UINT32 NodeControllerID : 12;
+ UINT32 Reserved_28 : 4;
+} EFI_ACPI_6_5_NFIT_DEVICE_HANDLE;
+
+#define EFI_ACPI_6_5_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0
+#define EFI_ACPI_6_5_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL BIT1
+#define EFI_ACPI_6_5_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL BIT2
+#define EFI_ACPI_6_5_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF BIT3
+#define EFI_ACPI_6_5_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF BIT4
+#define EFI_ACPI_6_5_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5
+#define EFI_ACPI_6_5_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6
+
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_5_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NVDIMMPhysicalID;
+ UINT16 NVDIMMRegionID;
+ UINT16 SPARangeStructureIndex;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT64 NVDIMMRegionSize;
+ UINT64 RegionOffset;
+ UINT64 NVDIMMPhysicalAddressRegionBase;
+ UINT16 InterleaveStructureIndex;
+ UINT16 InterleaveWays;
+ UINT16 NVDIMMStateFlags;
+ UINT16 Reserved_46;
+} EFI_ACPI_6_5_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;
+
+//
+// Definition for Interleave Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 InterleaveStructureIndex;
+ UINT16 Reserved_6;
+ UINT32 NumberOfLines;
+ UINT32 LineSize;
+ // UINT32 LineOffset[NumberOfLines];
+} EFI_ACPI_6_5_NFIT_INTERLEAVE_STRUCTURE;
+
+//
+// Definition for SMBIOS Management Information Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT32 Reserved_4;
+ // UINT8 Data[];
+} EFI_ACPI_6_5_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;
+
+//
+// Definition for NVDIMM Control Region Structure
+//
+#define EFI_ACPI_6_5_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0
+
+#define EFI_ACPI_6_5_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0
+
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT8 ValidFields;
+ UINT8 ManufacturingLocation;
+ UINT16 ManufacturingDate;
+ UINT8 Reserved_22[2];
+ UINT32 SerialNumber;
+ UINT16 RegionFormatInterfaceCode;
+ UINT16 NumberOfBlockControlWindows;
+ UINT64 SizeOfBlockControlWindow;
+ UINT64 CommandRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfCommandRegisterInBlockControlWindows;
+ UINT64 StatusRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfStatusRegisterInBlockControlWindows;
+ UINT16 NVDIMMControlRegionFlag;
+ UINT8 Reserved_74[6];
+} EFI_ACPI_6_5_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;
+
+//
+// Definition for NVDIMM Block Data Window Region Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 NumberOfBlockDataWindows;
+ UINT64 BlockDataWindowStartOffset;
+ UINT64 SizeOfBlockDataWindow;
+ UINT64 BlockAccessibleMemoryCapacity;
+ UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;
+} EFI_ACPI_6_5_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;
+
+//
+// Definition for Flush Hint Address Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_5_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NumberOfFlushHintAddresses;
+ UINT8 Reserved_10[6];
+ // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];
+} EFI_ACPI_6_5_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;
+
+//
+// Definition for Platform Capabilities Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT8 HighestValidCapability;
+ UINT8 Reserved_5[3];
+ UINT32 Capabilities;
+ UINT8 Reserved_12[4];
+} EFI_ACPI_6_5_NFIT_PLATFORM_CAPABILITIES_STRUCTURE;
+
+#define EFI_ACPI_6_5_NFIT_PLATFORM_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT0
+#define EFI_ACPI_6_5_NFIT_PLATFORM_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT1
+#define EFI_ACPI_6_5_NFIT_PLATFORM_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT2
+
+///
+/// Secure DEVices Table (SDEV)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_5_SECURE_DEVICES_TABLE_HEADER;
+
+///
+/// SDEV Revision (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_SECURE_DEVICES_TABLE_REVISION 0x01
+
+///
+/// Secure Device types
+///
+#define EFI_ACPI_6_5_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00
+#define EFI_ACPI_6_5_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01
+
+///
+/// Secure Device flags
+///
+#define EFI_ACPI_6_5_SDEV_FLAG_ALLOW_HANDOFF BIT0
+#define EFI_ACPI_6_5_SDEV_FLAG_SECURE_ACCESS_COMPONENTS_PRESENT BIT1
+
+///
+/// SDEV Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Flags;
+ UINT16 Length;
+} EFI_ACPI_6_5_SDEV_STRUCTURE_HEADER;
+
+///
+/// ACPI_NAMESPACE_DEVICE based Secure Device Structure
+///
+typedef struct {
+ EFI_ACPI_6_5_SDEV_STRUCTURE_HEADER Header;
+ UINT16 DeviceIdentifierOffset;
+ UINT16 DeviceIdentifierLength;
+ UINT16 VendorSpecificDataOffset;
+ UINT16 VendorSpecificDataLength;
+ UINT16 SecureAccessComponentsOffset;
+ UINT16 SecureAccessComponentsLength;
+} EFI_ACPI_6_5_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE;
+
+///
+/// Secure Access Component Types
+///
+#define EFI_ACPI_6_5_SDEV_SECURE_ACCESS_COMPONENT_TYPE_IDENTIFICATION 0x00
+#define EFI_ACPI_6_5_SDEV_SECURE_ACCESS_COMPONENT_TYPE_MEMORY 0x01
+
+///
+/// Identification Based Secure Access Component
+///
+typedef struct {
+ EFI_ACPI_6_5_SDEV_STRUCTURE_HEADER Header;
+ UINT16 HardwareIdentifierOffset;
+ UINT16 HardwareIdentifierLength;
+ UINT16 SubsystemIdentifierOffset;
+ UINT16 SubsystemIdentifierLength;
+ UINT16 HardwareRevision;
+ UINT8 HardwareRevisionPresent;
+ UINT8 ClassCodePresent;
+ UINT8 PciCompatibleBaseClass;
+ UINT8 PciCompatibleSubClass;
+ UINT8 PciCompatibleProgrammingInterface;
+} EFI_ACPI_6_5_SDEV_SECURE_ACCESS_COMPONENT_IDENTIFICATION_STRUCTURE;
+
+///
+/// Memory-based Secure Access Component
+///
+typedef struct {
+ EFI_ACPI_6_5_SDEV_STRUCTURE_HEADER Header;
+ UINT32 Reserved;
+ UINT64 MemoryAddressBase;
+ UINT64 MemoryLength;
+} EFI_ACPI_6_5_SDEV_SECURE_ACCESS_COMPONENT_MEMORY_STRUCTURE;
+
+///
+/// PCIe Endpoint Device based Secure Device Structure
+///
+typedef struct {
+ EFI_ACPI_6_5_SDEV_STRUCTURE_HEADER Header;
+ UINT16 PciSegmentNumber;
+ UINT16 StartBusNumber;
+ UINT16 PciPathOffset;
+ UINT16 PciPathLength;
+ UINT16 VendorSpecificDataOffset;
+ UINT16 VendorSpecificDataLength;
+} EFI_ACPI_6_5_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE;
+
+///
+/// Boot Error Record Table (BERT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 BootErrorRegionLength;
+ UINT64 BootErrorRegion;
+} EFI_ACPI_6_5_BOOT_ERROR_RECORD_TABLE_HEADER;
+
+///
+/// BERT Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+
+///
+/// Boot Error Region Block Status Definition
+///
+typedef struct {
+ UINT32 UncorrectableErrorValid : 1;
+ UINT32 CorrectableErrorValid : 1;
+ UINT32 MultipleUncorrectableErrors : 1;
+ UINT32 MultipleCorrectableErrors : 1;
+ UINT32 ErrorDataEntryCount : 10;
+ UINT32 Reserved : 18;
+} EFI_ACPI_6_5_ERROR_BLOCK_STATUS;
+
+///
+/// Boot Error Region Definition
+///
+typedef struct {
+ EFI_ACPI_6_5_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_6_5_BOOT_ERROR_REGION_STRUCTURE;
+
+//
+// Boot Error Severity types
+//
+#define EFI_ACPI_6_5_ERROR_SEVERITY_RECOVERABLE 0x00
+#define EFI_ACPI_6_5_ERROR_SEVERITY_FATAL 0x01
+#define EFI_ACPI_6_5_ERROR_SEVERITY_CORRECTED 0x02
+#define EFI_ACPI_6_5_ERROR_SEVERITY_NONE 0x03
+//
+// The term 'Correctable' is no longer being used as an error severity of the
+// reported error since ACPI Specification Version 5.1 Errata B.
+// The below macro is considered as deprecated and should no longer be used.
+//
+#define EFI_ACPI_6_5_ERROR_SEVERITY_CORRECTABLE 0x00
+
+///
+/// Generic Error Data Entry Definition
+///
+typedef struct {
+ UINT8 SectionType[16];
+ UINT32 ErrorSeverity;
+ UINT16 Revision;
+ UINT8 ValidationBits;
+ UINT8 Flags;
+ UINT32 ErrorDataLength;
+ UINT8 FruId[16];
+ UINT8 FruText[20];
+ UINT8 Timestamp[8];
+} EFI_ACPI_6_5_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
+
+///
+/// Generic Error Data Entry Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0300
+
+///
+/// HEST - Hardware Error Source Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 ErrorSourceCount;
+} EFI_ACPI_6_5_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
+
+///
+/// HEST Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+
+//
+// Error Source structure types.
+//
+#define EFI_ACPI_6_5_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00
+#define EFI_ACPI_6_5_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01
+#define EFI_ACPI_6_5_IA32_ARCHITECTURE_NMI_ERROR 0x02
+#define EFI_ACPI_6_5_PCI_EXPRESS_ROOT_PORT_AER 0x06
+#define EFI_ACPI_6_5_PCI_EXPRESS_DEVICE_AER 0x07
+#define EFI_ACPI_6_5_PCI_EXPRESS_BRIDGE_AER 0x08
+#define EFI_ACPI_6_5_GENERIC_HARDWARE_ERROR 0x09
+#define EFI_ACPI_6_5_GENERIC_HARDWARE_ERROR_VERSION_2 0x0A
+#define EFI_ACPI_6_5_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK 0x0B
+
+//
+// Error Source structure flags.
+//
+#define EFI_ACPI_6_5_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
+#define EFI_ACPI_6_5_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
+#define EFI_ACPI_6_5_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)
+
+///
+/// IA-32 Architecture Machine Check Exception Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT64 GlobalCapabilityInitData;
+ UINT64 GlobalControlInitData;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[7];
+} EFI_ACPI_6_5_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure Definition
+///
+typedef struct {
+ UINT8 BankNumber;
+ UINT8 ClearStatusOnInitialization;
+ UINT8 StatusDataFormat;
+ UINT8 Reserved0;
+ UINT32 ControlRegisterMsrAddress;
+ UINT64 ControlInitData;
+ UINT32 StatusRegisterMsrAddress;
+ UINT32 AddressRegisterMsrAddress;
+ UINT32 MiscRegisterMsrAddress;
+} EFI_ACPI_6_5_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure MCA data format
+///
+#define EFI_ACPI_6_5_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
+#define EFI_ACPI_6_5_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
+#define EFI_ACPI_6_5_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
+
+//
+// Hardware Error Notification types. All other values are reserved
+//
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_MCE 0x06
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B
+
+///
+/// Hardware Error Notification Configuration Write Enable Structure Definition
+///
+typedef struct {
+ UINT16 Type : 1;
+ UINT16 PollInterval : 1;
+ UINT16 SwitchToPollingThresholdValue : 1;
+ UINT16 SwitchToPollingThresholdWindow : 1;
+ UINT16 ErrorThresholdValue : 1;
+ UINT16 ErrorThresholdWindow : 1;
+ UINT16 Reserved : 10;
+} EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
+
+///
+/// Hardware Error Notification Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
+ UINT32 PollInterval;
+ UINT32 Vector;
+ UINT32 SwitchToPollingThresholdValue;
+ UINT32 SwitchToPollingThresholdWindow;
+ UINT32 ErrorThresholdValue;
+ UINT32 ErrorThresholdWindow;
+} EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
+
+///
+/// IA-32 Architecture Corrected Machine Check Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
+} EFI_ACPI_6_5_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// IA-32 Architecture NMI Error Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+} EFI_ACPI_6_5_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
+
+///
+/// PCI Express Root Port AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 RootErrorCommand;
+} EFI_ACPI_6_5_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
+
+///
+/// PCI Express Device AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_5_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
+
+///
+/// PCI Express Bridge AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 SecondaryUncorrectableErrorMask;
+ UINT32 SecondaryUncorrectableErrorSeverity;
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_5_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+} EFI_ACPI_6_5_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Version 2 Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;
+ UINT64 ReadAckPreserve;
+ UINT64 ReadAckWrite;
+} EFI_ACPI_6_5_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;
+
+///
+/// Generic Error Status Definition
+///
+typedef struct {
+ EFI_ACPI_6_5_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_6_5_GENERIC_ERROR_STATUS_STRUCTURE;
+
+///
+/// IA-32 Architecture Deferred Machine Check Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
+} EFI_ACPI_6_5_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// HMAT - Heterogeneous Memory Attribute Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[4];
+} EFI_ACPI_6_5_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;
+
+///
+/// HMAT Revision (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x02
+
+///
+/// HMAT types
+///
+#define EFI_ACPI_6_5_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES 0x00
+#define EFI_ACPI_6_5_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01
+#define EFI_ACPI_6_5_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02
+
+///
+/// HMAT Structure Header
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+} EFI_ACPI_6_5_HMAT_STRUCTURE_HEADER;
+
+///
+/// Memory Proximity Domain Attributes Structure flags
+///
+typedef struct {
+ UINT16 InitiatorProximityDomainValid : 1;
+ UINT16 Reserved : 15;
+} EFI_ACPI_6_5_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS;
+
+///
+/// Memory Proximity Domain Attributes Structure
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ EFI_ACPI_6_5_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS Flags;
+ UINT8 Reserved1[2];
+ UINT32 InitiatorProximityDomain;
+ UINT32 MemoryProximityDomain;
+ UINT8 Reserved2[20];
+} EFI_ACPI_6_5_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES;
+
+///
+/// System Locality Latency and Bandwidth Information Structure flags
+///
+typedef struct {
+ UINT8 MemoryHierarchy : 4;
+ UINT8 AccessAttributes : 2;
+ UINT8 Reserved : 2;
+} EFI_ACPI_6_5_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS;
+
+///
+/// System Locality Latency and Bandwidth Information Structure
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ EFI_ACPI_6_5_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;
+ UINT8 DataType;
+ UINT8 MinTransferSize;
+ UINT8 Reserved1;
+ UINT32 NumberOfInitiatorProximityDomains;
+ UINT32 NumberOfTargetProximityDomains;
+ UINT8 Reserved2[4];
+ UINT64 EntryBaseUnit;
+} EFI_ACPI_6_5_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO;
+
+///
+/// Memory Side Cache Information Structure cache attributes
+///
+typedef struct {
+ UINT32 TotalCacheLevels : 4;
+ UINT32 CacheLevel : 4;
+ UINT32 CacheAssociativity : 4;
+ UINT32 WritePolicy : 4;
+ UINT32 CacheLineSize : 16;
+} EFI_ACPI_6_5_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES;
+
+///
+/// Memory Side Cache Information Structure
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ UINT32 MemoryProximityDomain;
+ UINT8 Reserved1[4];
+ UINT64 MemorySideCacheSize;
+ EFI_ACPI_6_5_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;
+ UINT8 Reserved2[2];
+ UINT16 NumberOfSmbiosHandles;
+} EFI_ACPI_6_5_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO;
+
+///
+/// ERST - Error Record Serialization Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 SerializationHeaderSize;
+ UINT8 Reserved0[4];
+ UINT32 InstructionEntryCount;
+} EFI_ACPI_6_5_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
+
+///
+/// ERST Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+
+///
+/// ERST Serialization Actions
+///
+#define EFI_ACPI_6_5_ERST_BEGIN_WRITE_OPERATION 0x00
+#define EFI_ACPI_6_5_ERST_BEGIN_READ_OPERATION 0x01
+#define EFI_ACPI_6_5_ERST_BEGIN_CLEAR_OPERATION 0x02
+#define EFI_ACPI_6_5_ERST_END_OPERATION 0x03
+#define EFI_ACPI_6_5_ERST_SET_RECORD_OFFSET 0x04
+#define EFI_ACPI_6_5_ERST_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_5_ERST_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_5_ERST_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_5_ERST_GET_RECORD_IDENTIFIER 0x08
+#define EFI_ACPI_6_5_ERST_SET_RECORD_IDENTIFIER 0x09
+#define EFI_ACPI_6_5_ERST_GET_RECORD_COUNT 0x0A
+#define EFI_ACPI_6_5_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
+#define EFI_ACPI_6_5_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
+#define EFI_ACPI_6_5_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
+#define EFI_ACPI_6_5_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
+#define EFI_ACPI_6_5_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10
+
+///
+/// ERST Action Command Status
+///
+#define EFI_ACPI_6_5_ERST_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_5_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
+#define EFI_ACPI_6_5_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
+#define EFI_ACPI_6_5_ERST_STATUS_FAILED 0x03
+#define EFI_ACPI_6_5_ERST_STATUS_RECORD_STORE_EMPTY 0x04
+#define EFI_ACPI_6_5_ERST_STATUS_RECORD_NOT_FOUND 0x05
+
+///
+/// ERST Serialization Instructions
+///
+#define EFI_ACPI_6_5_ERST_READ_REGISTER 0x00
+#define EFI_ACPI_6_5_ERST_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_5_ERST_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_5_ERST_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_5_ERST_NOOP 0x04
+#define EFI_ACPI_6_5_ERST_LOAD_VAR1 0x05
+#define EFI_ACPI_6_5_ERST_LOAD_VAR2 0x06
+#define EFI_ACPI_6_5_ERST_STORE_VAR1 0x07
+#define EFI_ACPI_6_5_ERST_ADD 0x08
+#define EFI_ACPI_6_5_ERST_SUBTRACT 0x09
+#define EFI_ACPI_6_5_ERST_ADD_VALUE 0x0A
+#define EFI_ACPI_6_5_ERST_SUBTRACT_VALUE 0x0B
+#define EFI_ACPI_6_5_ERST_STALL 0x0C
+#define EFI_ACPI_6_5_ERST_STALL_WHILE_TRUE 0x0D
+#define EFI_ACPI_6_5_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
+#define EFI_ACPI_6_5_ERST_GOTO 0x0F
+#define EFI_ACPI_6_5_ERST_SET_SRC_ADDRESS_BASE 0x10
+#define EFI_ACPI_6_5_ERST_SET_DST_ADDRESS_BASE 0x11
+#define EFI_ACPI_6_5_ERST_MOVE_DATA 0x12
+
+///
+/// ERST Instruction Flags
+///
+#define EFI_ACPI_6_5_ERST_PRESERVE_REGISTER 0x01
+
+///
+/// ERST Serialization Instruction Entry
+///
+typedef struct {
+ UINT8 SerializationAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_6_5_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ - Error Injection Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 InjectionHeaderSize;
+ UINT8 InjectionFlags;
+ UINT8 Reserved0[3];
+ UINT32 InjectionEntryCount;
+} EFI_ACPI_6_5_ERROR_INJECTION_TABLE_HEADER;
+
+///
+/// EINJ Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_ERROR_INJECTION_TABLE_REVISION 0x01
+
+///
+/// EINJ Error Injection Actions
+///
+#define EFI_ACPI_6_5_EINJ_BEGIN_INJECTION_OPERATION 0x00
+#define EFI_ACPI_6_5_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
+#define EFI_ACPI_6_5_EINJ_SET_ERROR_TYPE 0x02
+#define EFI_ACPI_6_5_EINJ_GET_ERROR_TYPE 0x03
+#define EFI_ACPI_6_5_EINJ_END_OPERATION 0x04
+#define EFI_ACPI_6_5_EINJ_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_5_EINJ_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_5_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_5_EINJ_TRIGGER_ERROR 0xFF
+
+///
+/// EINJ Action Command Status
+///
+#define EFI_ACPI_6_5_EINJ_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_5_EINJ_STATUS_UNKNOWN_FAILURE 0x01
+#define EFI_ACPI_6_5_EINJ_STATUS_INVALID_ACCESS 0x02
+
+///
+/// EINJ Error Type Definition
+///
+#define EFI_ACPI_6_5_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
+#define EFI_ACPI_6_5_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
+#define EFI_ACPI_6_5_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
+#define EFI_ACPI_6_5_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
+#define EFI_ACPI_6_5_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
+#define EFI_ACPI_6_5_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
+#define EFI_ACPI_6_5_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
+#define EFI_ACPI_6_5_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
+#define EFI_ACPI_6_5_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
+#define EFI_ACPI_6_5_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
+#define EFI_ACPI_6_5_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
+#define EFI_ACPI_6_5_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
+
+///
+/// EINJ Injection Instructions
+///
+#define EFI_ACPI_6_5_EINJ_READ_REGISTER 0x00
+#define EFI_ACPI_6_5_EINJ_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_5_EINJ_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_5_EINJ_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_5_EINJ_NOOP 0x04
+
+///
+/// EINJ Instruction Flags
+///
+#define EFI_ACPI_6_5_EINJ_PRESERVE_REGISTER 0x01
+
+///
+/// EINJ Injection Instruction Entry
+///
+typedef struct {
+ UINT8 InjectionAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_6_5_EINJ_INJECTION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ Trigger Action Table
+///
+typedef struct {
+ UINT32 HeaderSize;
+ UINT32 Revision;
+ UINT32 TableSize;
+ UINT32 EntryCount;
+} EFI_ACPI_6_5_EINJ_TRIGGER_ACTION_TABLE;
+
+///
+/// Platform Communications Channel Table (PCCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Flags;
+ UINT64 Reserved;
+} EFI_ACPI_6_5_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
+
+///
+/// PCCT Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02
+
+///
+/// PCCT Global Flags
+///
+#define EFI_ACPI_6_5_PCCT_FLAGS_PLATFORM_INTERRUPT BIT0
+
+//
+// PCCT Subspace type
+//
+#define EFI_ACPI_6_5_PCCT_SUBSPACE_TYPE_GENERIC 0x00
+#define EFI_ACPI_6_5_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01
+#define EFI_ACPI_6_5_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02
+#define EFI_ACPI_6_5_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03
+#define EFI_ACPI_6_5_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04
+#define EFI_ACPI_6_5_PCCT_SUBSPACE_TYPE_5_HW_REGISTERS_COMMUNICATIONS 0x05
+
+///
+/// PCC Subspace Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+} EFI_ACPI_6_5_PCCT_SUBSPACE_HEADER;
+
+///
+/// Generic Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[6];
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_5_PCCT_SUBSPACE_GENERIC;
+
+///
+/// Generic Communications Channel Shared Memory Region
+///
+
+typedef struct {
+ UINT8 Command;
+ UINT8 Reserved : 7;
+ UINT8 NotifyOnCompletion : 1;
+} EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
+
+typedef struct {
+ UINT8 CommandComplete : 1;
+ UINT8 PlatformInterrupt : 1;
+ UINT8 Error : 1;
+ UINT8 PlatformNotification : 1;
+ UINT8 Reserved : 4;
+ UINT8 Reserved1;
+} EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
+
+typedef struct {
+ UINT32 Signature;
+ EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command;
+ EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;
+} EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
+
+#define EFI_ACPI_6_5_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0
+#define EFI_ACPI_6_5_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1
+
+///
+/// Type 1 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_5_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 2 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
+ UINT64 PlatformInterruptAckPreserve;
+ UINT64 PlatformInterruptAckWrite;
+} EFI_ACPI_6_5_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 3 Extended PCC Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT32 AddressLength;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT32 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
+ UINT64 PlatformInterruptAckPreserve;
+ UINT64 PlatformInterruptAckSet;
+ UINT8 Reserved1[8];
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;
+ UINT64 CommandCompleteCheckMask;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;
+ UINT64 CommandCompleteUpdatePreserve;
+ UINT64 CommandCompleteUpdateSet;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;
+ UINT64 ErrorStatusMask;
+} EFI_ACPI_6_5_PCCT_SUBSPACE_3_EXTENDED_PCC;
+
+///
+/// Type 4 Extended PCC Subspace Structure
+///
+typedef EFI_ACPI_6_5_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_5_PCCT_SUBSPACE_4_EXTENDED_PCC;
+
+#define EFI_ACPI_6_5_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0
+
+typedef struct {
+ UINT32 Signature;
+ UINT32 Flags;
+ UINT32 Length;
+ UINT32 Command;
+} EFI_ACPI_6_5_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER;
+
+///
+/// Type 5 HW Registers based Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Version;
+ UINT64 BaseAddress;
+ UINT64 SharedMemoryRangeLength;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;
+ UINT64 CommandCompleteCheckMask;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;
+ UINT64 ErrorStatusMask;
+ UINT32 NominalLatency;
+ UINT32 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_5_PCCT_SUBSPACE_5_HW_REGISTERS_COMMUNICATIONS;
+
+///
+/// Reduced PCC Subspace Shared Memory Region
+///
+typedef struct {
+ UINT32 Signature;
+ // UINT8 CommunicationSubspace[];
+} EFI_6_5_PCCT_REDUCED_PCC_SUBSPACE_SHARED_MEMORY_REGION;
+
+///
+/// Platform Debug Trigger Table (PDTT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 TriggerCount;
+ UINT8 Reserved[3];
+ UINT32 TriggerIdentifierArrayOffset;
+} EFI_ACPI_6_5_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER;
+
+///
+/// PDTT Revision (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00
+
+///
+/// PDTT Platform Communication Channel Identifier Structure
+///
+typedef struct {
+ UINT16 SubChannelIdentifer : 8;
+ UINT16 Runtime : 1;
+ UINT16 WaitForCompletion : 1;
+ UINT16 TriggerOrder : 1;
+ UINT16 Reserved : 5;
+} EFI_ACPI_6_5_PDTT_PCC_IDENTIFIER;
+
+///
+/// PCC Commands Codes used by Platform Debug Trigger Table
+///
+#define EFI_ACPI_6_5_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00
+#define EFI_ACPI_6_5_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01
+
+///
+/// PDTT Platform Communication Channel
+///
+typedef EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6_5_PDTT_PCC;
+
+///
+/// Processor Properties Topology Table (PPTT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_5_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;
+
+///
+/// PPTT Revision (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x03
+
+///
+/// PPTT types
+///
+#define EFI_ACPI_6_5_PPTT_TYPE_PROCESSOR 0x00
+#define EFI_ACPI_6_5_PPTT_TYPE_CACHE 0x01
+
+///
+/// PPTT Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_5_PPTT_STRUCTURE_HEADER;
+
+///
+/// For PPTT struct processor flags
+///
+#define EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL 0x0
+#define EFI_ACPI_6_5_PPTT_PACKAGE_PHYSICAL 0x1
+#define EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID 0x0
+#define EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID 0x1
+#define EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD 0x0
+#define EFI_ACPI_6_5_PPTT_PROCESSOR_IS_THREAD 0x1
+#define EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF 0x0
+#define EFI_ACPI_6_5_PPTT_NODE_IS_LEAF 0x1
+#define EFI_ACPI_6_5_PPTT_IMPLEMENTATION_NOT_IDENTICAL 0x0
+#define EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL 0x1
+
+///
+/// Processor hierarchy node structure flags
+///
+typedef struct {
+ UINT32 PhysicalPackage : 1;
+ UINT32 AcpiProcessorIdValid : 1;
+ UINT32 ProcessorIsAThread : 1;
+ UINT32 NodeIsALeaf : 1;
+ UINT32 IdenticalImplementation : 1;
+ UINT32 Reserved : 27;
+} EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS;
+
+///
+/// Processor hierarchy node structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;
+ UINT32 Parent;
+ UINT32 AcpiProcessorId;
+ UINT32 NumberOfPrivateResources;
+} EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR;
+
+///
+/// For PPTT struct cache flags
+///
+#define EFI_ACPI_6_5_PPTT_CACHE_SIZE_INVALID 0x0
+#define EFI_ACPI_6_5_PPTT_CACHE_SIZE_VALID 0x1
+#define EFI_ACPI_6_5_PPTT_NUMBER_OF_SETS_INVALID 0x0
+#define EFI_ACPI_6_5_PPTT_NUMBER_OF_SETS_VALID 0x1
+#define EFI_ACPI_6_5_PPTT_ASSOCIATIVITY_INVALID 0x0
+#define EFI_ACPI_6_5_PPTT_ASSOCIATIVITY_VALID 0x1
+#define EFI_ACPI_6_5_PPTT_ALLOCATION_TYPE_INVALID 0x0
+#define EFI_ACPI_6_5_PPTT_ALLOCATION_TYPE_VALID 0x1
+#define EFI_ACPI_6_5_PPTT_CACHE_TYPE_INVALID 0x0
+#define EFI_ACPI_6_5_PPTT_CACHE_TYPE_VALID 0x1
+#define EFI_ACPI_6_5_PPTT_WRITE_POLICY_INVALID 0x0
+#define EFI_ACPI_6_5_PPTT_WRITE_POLICY_VALID 0x1
+#define EFI_ACPI_6_5_PPTT_LINE_SIZE_INVALID 0x0
+#define EFI_ACPI_6_5_PPTT_LINE_SIZE_VALID 0x1
+#define EFI_ACPI_6_5_PPTT_CACHE_ID_INVALID 0x0
+#define EFI_ACPI_6_5_PPTT_CACHE_ID_VALID 0x1
+
+///
+/// Cache Type Structure flags
+///
+typedef struct {
+ UINT32 SizePropertyValid : 1;
+ UINT32 NumberOfSetsValid : 1;
+ UINT32 AssociativityValid : 1;
+ UINT32 AllocationTypeValid : 1;
+ UINT32 CacheTypeValid : 1;
+ UINT32 WritePolicyValid : 1;
+ UINT32 LineSizeValid : 1;
+ UINT32 CacheIdValid : 1;
+ UINT32 Reserved : 24;
+} EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE_FLAGS;
+
+///
+/// For cache attributes
+///
+#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0
+#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1
+#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2
+#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0
+#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1
+#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2
+#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0
+#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1
+
+///
+/// Cache Type Structure cache attributes
+///
+typedef struct {
+ UINT8 AllocationType : 2;
+ UINT8 CacheType : 2;
+ UINT8 WritePolicy : 1;
+ UINT8 Reserved : 3;
+} EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE_ATTRIBUTES;
+
+///
+/// Cache Type Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE_FLAGS Flags;
+ UINT32 NextLevelOfCache;
+ UINT32 Size;
+ UINT32 NumberOfSets;
+ UINT8 Associativity;
+ EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;
+ UINT16 LineSize;
+ UINT32 CacheId;
+} EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE;
+
+///
+/// Platform Health Assessment Table (PHAT) Format
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ // UINT8 PlatformTelemetryRecords[];
+} EFI_ACPI_6_5_PLATFORM_HEALTH_ASSESSMENT_TABLE;
+
+#define EFI_ACPI_6_5_PLATFORM_HEALTH_ASSESSMENT_TABLE_REVISION 0x01
+
+///
+/// PHAT Record Format
+///
+typedef struct {
+ UINT16 PlatformHealthAssessmentRecordType;
+ UINT16 RecordLength;
+ UINT8 Revision;
+ // UINT8 Data[];
+} EFI_ACPI_6_5_PHAT_RECORD;
+
+///
+/// PHAT Record Type Format
+///
+#define EFI_ACPI_6_5_PHAT_RECORD_TYPE_FIRMWARE_VERSION_DATA_RECORD 0x0000
+#define EFI_ACPI_6_5_PHAT_RECORD_TYPE_FIRMWARE_HEALTH_DATA_RECORD 0x0001
+
+///
+/// PHAT Version Element
+///
+typedef struct {
+ GUID ComponentId;
+ UINT64 VersionValue;
+ UINT32 ProducerId;
+} EFI_ACPI_6_5_PHAT_VERSION_ELEMENT;
+
+///
+/// PHAT Firmware Version Data Record
+///
+typedef struct {
+ UINT16 PlatformRecordType;
+ UINT16 RecordLength;
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ UINT32 RecordCount;
+ // UINT8 PhatVersionElement[];
+} EFI_ACPI_6_5_PHAT_FIRMWARE_VERISON_DATA_RECORD;
+
+#define EFI_ACPI_6_5_PHAT_FIRMWARE_VERSION_DATA_RECORD_REVISION 0x01
+
+///
+/// Firmware Health Data Record Structure
+///
+typedef struct {
+ UINT16 PlatformRecordType;
+ UINT16 RecordLength;
+ UINT8 Revision;
+ UINT16 Reserved;
+ UINT8 AmHealthy;
+ GUID DeviceSignature;
+ UINT32 DeviceSpecificDataOffset;
+ // UINT8 DevicePath[];
+ // UINT8 DeviceSpecificData[];
+} EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_STRUCTURE;
+
+#define EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_REVISION 0x01
+
+///
+/// Firmware Health Data Record device health state
+///
+#define EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_ERRORS_FOUND 0x00
+#define EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_NO_ERRORS_FOUND 0x01
+#define EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_UNKNOWN 0x02
+#define EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_ADVISORY 0x03
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_6_5_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "APMT" Arm Performance Monitoring Unit Table
+///
+#define EFI_ACPI_6_5_ARM_PERFORMANCE_MONITORING_UNIT_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'M', 'T')
+
+///
+/// "BERT" Boot Error Record Table
+///
+#define EFI_ACPI_6_5_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T')
+
+///
+/// "BGRT" Boot Graphics Resource Table
+///
+#define EFI_ACPI_6_5_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T')
+
+///
+/// "CDIT" Component Distance Information Table
+///
+#define EFI_ACPI_6_5_COMPONENT_DISTANCE_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('C', 'D', 'I', 'T')
+
+///
+/// "CPEP" Corrected Platform Error Polling Table
+///
+#define EFI_ACPI_6_5_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')
+
+///
+/// "CRAT" Component Resource Attribute Table
+///
+#define EFI_ACPI_6_5_COMPONENT_RESOURCE_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('C', 'R', 'A', 'T')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_6_5_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_6_5_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "EINJ" Error Injection Table
+///
+#define EFI_ACPI_6_5_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J')
+
+///
+/// "ERST" Error Record Serialization Table
+///
+#define EFI_ACPI_6_5_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_6_5_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "FPDT" Firmware Performance Data Table
+///
+#define EFI_ACPI_6_5_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T')
+
+///
+/// "GTDT" Generic Timer Description Table
+///
+#define EFI_ACPI_6_5_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T')
+
+///
+/// "HEST" Hardware Error Source Table
+///
+#define EFI_ACPI_6_5_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T')
+
+///
+/// "HMAT" Heterogeneous Memory Attribute Table
+///
+#define EFI_ACPI_6_5_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('H', 'M', 'A', 'T')
+
+///
+/// "MPST" Memory Power State Table
+///
+#define EFI_ACPI_6_5_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T')
+
+///
+/// "MSCT" Maximum System Characteristics Table
+///
+#define EFI_ACPI_6_5_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T')
+
+///
+/// "NFIT" NVDIMM Firmware Interface Table
+///
+#define EFI_ACPI_6_5_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('N', 'F', 'I', 'T')
+
+///
+/// "PDTT" Platform Debug Trigger Table
+///
+#define EFI_ACPI_6_5_PLATFORM_DEBUG_TRIGGER_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'D', 'T', 'T')
+
+///
+/// "PMTT" Platform Memory Topology Table
+///
+#define EFI_ACPI_6_5_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T')
+
+///
+/// "PPTT" Processor Properties Topology Table
+///
+#define EFI_ACPI_6_5_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'P', 'T', 'T')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_6_5_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RASF" ACPI RAS Feature Table
+///
+#define EFI_ACPI_6_5_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_6_5_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_6_5_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SDEV" Secure DEVices Table
+///
+#define EFI_ACPI_6_5_SECURE_DEVICES_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'V')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_6_5_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SRAT" System Resource Affinity Table
+///
+#define EFI_ACPI_6_5_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_6_5_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_6_5_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_6_5_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "CSRT" MS Core System Resource Table
+///
+#define EFI_ACPI_6_5_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T')
+
+///
+/// "DBG2" MS Debug Port 2 Spec
+///
+#define EFI_ACPI_6_5_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2')
+
+///
+/// "DBGP" MS Debug Port Spec
+///
+#define EFI_ACPI_6_5_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "DMAR" DMA Remapping Table
+///
+#define EFI_ACPI_6_5_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R')
+
+///
+/// "DRTM" Dynamic Root of Trust for Measurement Table
+///
+#define EFI_ACPI_6_5_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_6_5_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "HPET" IA-PC High Precision Event Timer Table
+///
+#define EFI_ACPI_6_5_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')
+
+///
+/// "iBFT" iSCSI Boot Firmware Table
+///
+#define EFI_ACPI_6_5_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')
+
+///
+/// "IORT" I/O Remapping Table
+///
+#define EFI_ACPI_6_5_IO_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('I', 'O', 'R', 'T')
+
+///
+/// "IVRS" I/O Virtualization Reporting Structure
+///
+#define EFI_ACPI_6_5_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S')
+
+///
+/// "LPIT" Low Power Idle Table
+///
+#define EFI_ACPI_6_5_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_6_5_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')
+
+///
+/// "MCHI" Management Controller Host Interface Table
+///
+#define EFI_ACPI_6_5_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')
+
+///
+/// "MSDM" MS Data Management Table
+///
+#define EFI_ACPI_6_5_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')
+
+///
+/// "PCCT" Platform Communications Channel Table
+///
+#define EFI_ACPI_6_5_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')
+
+///
+/// "PHAT" Platform Health Assessment Table
+///
+#define EFI_ACPI_6_5_PLATFORM_HEALTH_ASSESSMENT_TABLE_SIGNATURE SIGNATURE_32('P', 'H', 'A', 'T')
+
+///
+/// "SDEI" Software Delegated Exceptions Interface Table
+///
+#define EFI_ACPI_6_5_SOFTWARE_DELEGATED_EXCEPTIONS_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'I')
+
+///
+/// "SLIC" MS Software Licensing Table Specification
+///
+#define EFI_ACPI_6_5_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')
+
+///
+/// "SPCR" Serial Port Concole Redirection Table
+///
+#define EFI_ACPI_6_5_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_6_5_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "STAO" _STA Override Table
+///
+#define EFI_ACPI_6_5_STA_OVERRIDE_TABLE_SIGNATURE SIGNATURE_32('S', 'T', 'A', 'O')
+
+///
+/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+///
+#define EFI_ACPI_6_5_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')
+
+///
+/// "TPM2" Trusted Computing Platform 1 Table
+///
+#define EFI_ACPI_6_5_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2')
+
+///
+/// "UEFI" UEFI ACPI Data Table
+///
+#define EFI_ACPI_6_5_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I')
+
+///
+/// "WAET" Windows ACPI Emulated Devices Table
+///
+#define EFI_ACPI_6_5_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')
+
+///
+/// "WDAT" Watchdog Action Table
+///
+#define EFI_ACPI_6_5_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')
+
+///
+/// "WDRT" Watchdog Resource Table
+///
+#define EFI_ACPI_6_5_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')
+
+///
+/// "WPBT" MS Platform Binary Table
+///
+#define EFI_ACPI_6_5_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T')
+
+///
+/// "WSMT" Windows SMM Security Mitigation Table
+///
+#define EFI_ACPI_6_5_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE SIGNATURE_32('W', 'S', 'M', 'T')
+
+///
+/// "XENV" Xen Project Table
+///
+#define EFI_ACPI_6_5_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V')
+
+#pragma pack()
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/AcpiAml.h b/MdePkg/Include/IndustryStandard/AcpiAml.h
index 7aae14b3..79e30b7b 100644
--- a/MdePkg/Include/IndustryStandard/AcpiAml.h
+++ b/MdePkg/Include/IndustryStandard/AcpiAml.h
@@ -17,168 +17,168 @@
//
// Primary OpCode
//
-#define AML_ZERO_OP 0x00
-#define AML_ONE_OP 0x01
-#define AML_ALIAS_OP 0x06
-#define AML_NAME_OP 0x08
-#define AML_BYTE_PREFIX 0x0a
-#define AML_WORD_PREFIX 0x0b
-#define AML_DWORD_PREFIX 0x0c
-#define AML_STRING_PREFIX 0x0d
-#define AML_QWORD_PREFIX 0x0e
-#define AML_SCOPE_OP 0x10
-#define AML_BUFFER_OP 0x11
-#define AML_PACKAGE_OP 0x12
-#define AML_VAR_PACKAGE_OP 0x13
-#define AML_METHOD_OP 0x14
-#define AML_EXTERNAL_OP 0x15
-#define AML_DUAL_NAME_PREFIX 0x2e
-#define AML_MULTI_NAME_PREFIX 0x2f
-#define AML_NAME_CHAR_A 0x41
-#define AML_NAME_CHAR_B 0x42
-#define AML_NAME_CHAR_C 0x43
-#define AML_NAME_CHAR_D 0x44
-#define AML_NAME_CHAR_E 0x45
-#define AML_NAME_CHAR_F 0x46
-#define AML_NAME_CHAR_G 0x47
-#define AML_NAME_CHAR_H 0x48
-#define AML_NAME_CHAR_I 0x49
-#define AML_NAME_CHAR_J 0x4a
-#define AML_NAME_CHAR_K 0x4b
-#define AML_NAME_CHAR_L 0x4c
-#define AML_NAME_CHAR_M 0x4d
-#define AML_NAME_CHAR_N 0x4e
-#define AML_NAME_CHAR_O 0x4f
-#define AML_NAME_CHAR_P 0x50
-#define AML_NAME_CHAR_Q 0x51
-#define AML_NAME_CHAR_R 0x52
-#define AML_NAME_CHAR_S 0x53
-#define AML_NAME_CHAR_T 0x54
-#define AML_NAME_CHAR_U 0x55
-#define AML_NAME_CHAR_V 0x56
-#define AML_NAME_CHAR_W 0x57
-#define AML_NAME_CHAR_X 0x58
-#define AML_NAME_CHAR_Y 0x59
-#define AML_NAME_CHAR_Z 0x5a
-#define AML_ROOT_CHAR 0x5c
-#define AML_PARENT_PREFIX_CHAR 0x5e
-#define AML_NAME_CHAR__ 0x5f
-#define AML_LOCAL0 0x60
-#define AML_LOCAL1 0x61
-#define AML_LOCAL2 0x62
-#define AML_LOCAL3 0x63
-#define AML_LOCAL4 0x64
-#define AML_LOCAL5 0x65
-#define AML_LOCAL6 0x66
-#define AML_LOCAL7 0x67
-#define AML_ARG0 0x68
-#define AML_ARG1 0x69
-#define AML_ARG2 0x6a
-#define AML_ARG3 0x6b
-#define AML_ARG4 0x6c
-#define AML_ARG5 0x6d
-#define AML_ARG6 0x6e
-#define AML_STORE_OP 0x70
-#define AML_REF_OF_OP 0x71
-#define AML_ADD_OP 0x72
-#define AML_CONCAT_OP 0x73
-#define AML_SUBTRACT_OP 0x74
-#define AML_INCREMENT_OP 0x75
-#define AML_DECREMENT_OP 0x76
-#define AML_MULTIPLY_OP 0x77
-#define AML_DIVIDE_OP 0x78
-#define AML_SHIFT_LEFT_OP 0x79
-#define AML_SHIFT_RIGHT_OP 0x7a
-#define AML_AND_OP 0x7b
-#define AML_NAND_OP 0x7c
-#define AML_OR_OP 0x7d
-#define AML_NOR_OP 0x7e
-#define AML_XOR_OP 0x7f
-#define AML_NOT_OP 0x80
-#define AML_FIND_SET_LEFT_BIT_OP 0x81
-#define AML_FIND_SET_RIGHT_BIT_OP 0x82
-#define AML_DEREF_OF_OP 0x83
-#define AML_CONCAT_RES_OP 0x84
-#define AML_MOD_OP 0x85
-#define AML_NOTIFY_OP 0x86
-#define AML_SIZE_OF_OP 0x87
-#define AML_INDEX_OP 0x88
-#define AML_MATCH_OP 0x89
-#define AML_CREATE_DWORD_FIELD_OP 0x8a
-#define AML_CREATE_WORD_FIELD_OP 0x8b
-#define AML_CREATE_BYTE_FIELD_OP 0x8c
-#define AML_CREATE_BIT_FIELD_OP 0x8d
-#define AML_OBJECT_TYPE_OP 0x8e
-#define AML_CREATE_QWORD_FIELD_OP 0x8f
-#define AML_LAND_OP 0x90
-#define AML_LOR_OP 0x91
-#define AML_LNOT_OP 0x92
-#define AML_LEQUAL_OP 0x93
-#define AML_LGREATER_OP 0x94
-#define AML_LLESS_OP 0x95
-#define AML_TO_BUFFER_OP 0x96
-#define AML_TO_DEC_STRING_OP 0x97
-#define AML_TO_HEX_STRING_OP 0x98
-#define AML_TO_INTEGER_OP 0x99
-#define AML_TO_STRING_OP 0x9c
-#define AML_COPY_OBJECT_OP 0x9d
-#define AML_MID_OP 0x9e
-#define AML_CONTINUE_OP 0x9f
-#define AML_IF_OP 0xa0
-#define AML_ELSE_OP 0xa1
-#define AML_WHILE_OP 0xa2
-#define AML_NOOP_OP 0xa3
-#define AML_RETURN_OP 0xa4
-#define AML_BREAK_OP 0xa5
-#define AML_BREAK_POINT_OP 0xcc
-#define AML_ONES_OP 0xff
+#define AML_ZERO_OP 0x00
+#define AML_ONE_OP 0x01
+#define AML_ALIAS_OP 0x06
+#define AML_NAME_OP 0x08
+#define AML_BYTE_PREFIX 0x0a
+#define AML_WORD_PREFIX 0x0b
+#define AML_DWORD_PREFIX 0x0c
+#define AML_STRING_PREFIX 0x0d
+#define AML_QWORD_PREFIX 0x0e
+#define AML_SCOPE_OP 0x10
+#define AML_BUFFER_OP 0x11
+#define AML_PACKAGE_OP 0x12
+#define AML_VAR_PACKAGE_OP 0x13
+#define AML_METHOD_OP 0x14
+#define AML_EXTERNAL_OP 0x15
+#define AML_DUAL_NAME_PREFIX 0x2e
+#define AML_MULTI_NAME_PREFIX 0x2f
+#define AML_NAME_CHAR_A 0x41
+#define AML_NAME_CHAR_B 0x42
+#define AML_NAME_CHAR_C 0x43
+#define AML_NAME_CHAR_D 0x44
+#define AML_NAME_CHAR_E 0x45
+#define AML_NAME_CHAR_F 0x46
+#define AML_NAME_CHAR_G 0x47
+#define AML_NAME_CHAR_H 0x48
+#define AML_NAME_CHAR_I 0x49
+#define AML_NAME_CHAR_J 0x4a
+#define AML_NAME_CHAR_K 0x4b
+#define AML_NAME_CHAR_L 0x4c
+#define AML_NAME_CHAR_M 0x4d
+#define AML_NAME_CHAR_N 0x4e
+#define AML_NAME_CHAR_O 0x4f
+#define AML_NAME_CHAR_P 0x50
+#define AML_NAME_CHAR_Q 0x51
+#define AML_NAME_CHAR_R 0x52
+#define AML_NAME_CHAR_S 0x53
+#define AML_NAME_CHAR_T 0x54
+#define AML_NAME_CHAR_U 0x55
+#define AML_NAME_CHAR_V 0x56
+#define AML_NAME_CHAR_W 0x57
+#define AML_NAME_CHAR_X 0x58
+#define AML_NAME_CHAR_Y 0x59
+#define AML_NAME_CHAR_Z 0x5a
+#define AML_ROOT_CHAR 0x5c
+#define AML_PARENT_PREFIX_CHAR 0x5e
+#define AML_NAME_CHAR__ 0x5f
+#define AML_LOCAL0 0x60
+#define AML_LOCAL1 0x61
+#define AML_LOCAL2 0x62
+#define AML_LOCAL3 0x63
+#define AML_LOCAL4 0x64
+#define AML_LOCAL5 0x65
+#define AML_LOCAL6 0x66
+#define AML_LOCAL7 0x67
+#define AML_ARG0 0x68
+#define AML_ARG1 0x69
+#define AML_ARG2 0x6a
+#define AML_ARG3 0x6b
+#define AML_ARG4 0x6c
+#define AML_ARG5 0x6d
+#define AML_ARG6 0x6e
+#define AML_STORE_OP 0x70
+#define AML_REF_OF_OP 0x71
+#define AML_ADD_OP 0x72
+#define AML_CONCAT_OP 0x73
+#define AML_SUBTRACT_OP 0x74
+#define AML_INCREMENT_OP 0x75
+#define AML_DECREMENT_OP 0x76
+#define AML_MULTIPLY_OP 0x77
+#define AML_DIVIDE_OP 0x78
+#define AML_SHIFT_LEFT_OP 0x79
+#define AML_SHIFT_RIGHT_OP 0x7a
+#define AML_AND_OP 0x7b
+#define AML_NAND_OP 0x7c
+#define AML_OR_OP 0x7d
+#define AML_NOR_OP 0x7e
+#define AML_XOR_OP 0x7f
+#define AML_NOT_OP 0x80
+#define AML_FIND_SET_LEFT_BIT_OP 0x81
+#define AML_FIND_SET_RIGHT_BIT_OP 0x82
+#define AML_DEREF_OF_OP 0x83
+#define AML_CONCAT_RES_OP 0x84
+#define AML_MOD_OP 0x85
+#define AML_NOTIFY_OP 0x86
+#define AML_SIZE_OF_OP 0x87
+#define AML_INDEX_OP 0x88
+#define AML_MATCH_OP 0x89
+#define AML_CREATE_DWORD_FIELD_OP 0x8a
+#define AML_CREATE_WORD_FIELD_OP 0x8b
+#define AML_CREATE_BYTE_FIELD_OP 0x8c
+#define AML_CREATE_BIT_FIELD_OP 0x8d
+#define AML_OBJECT_TYPE_OP 0x8e
+#define AML_CREATE_QWORD_FIELD_OP 0x8f
+#define AML_LAND_OP 0x90
+#define AML_LOR_OP 0x91
+#define AML_LNOT_OP 0x92
+#define AML_LEQUAL_OP 0x93
+#define AML_LGREATER_OP 0x94
+#define AML_LLESS_OP 0x95
+#define AML_TO_BUFFER_OP 0x96
+#define AML_TO_DEC_STRING_OP 0x97
+#define AML_TO_HEX_STRING_OP 0x98
+#define AML_TO_INTEGER_OP 0x99
+#define AML_TO_STRING_OP 0x9c
+#define AML_COPY_OBJECT_OP 0x9d
+#define AML_MID_OP 0x9e
+#define AML_CONTINUE_OP 0x9f
+#define AML_IF_OP 0xa0
+#define AML_ELSE_OP 0xa1
+#define AML_WHILE_OP 0xa2
+#define AML_NOOP_OP 0xa3
+#define AML_RETURN_OP 0xa4
+#define AML_BREAK_OP 0xa5
+#define AML_BREAK_POINT_OP 0xcc
+#define AML_ONES_OP 0xff
//
// Extended OpCode
//
-#define AML_EXT_OP 0x5b
+#define AML_EXT_OP 0x5b
-#define AML_EXT_MUTEX_OP 0x01
-#define AML_EXT_EVENT_OP 0x02
-#define AML_EXT_COND_REF_OF_OP 0x12
-#define AML_EXT_CREATE_FIELD_OP 0x13
-#define AML_EXT_LOAD_TABLE_OP 0x1f
-#define AML_EXT_LOAD_OP 0x20
-#define AML_EXT_STALL_OP 0x21
-#define AML_EXT_SLEEP_OP 0x22
-#define AML_EXT_ACQUIRE_OP 0x23
-#define AML_EXT_SIGNAL_OP 0x24
-#define AML_EXT_WAIT_OP 0x25
-#define AML_EXT_RESET_OP 0x26
-#define AML_EXT_RELEASE_OP 0x27
-#define AML_EXT_FROM_BCD_OP 0x28
-#define AML_EXT_TO_BCD_OP 0x29
-#define AML_EXT_UNLOAD_OP 0x2a
-#define AML_EXT_REVISION_OP 0x30
-#define AML_EXT_DEBUG_OP 0x31
-#define AML_EXT_FATAL_OP 0x32
-#define AML_EXT_TIMER_OP 0x33
-#define AML_EXT_REGION_OP 0x80
-#define AML_EXT_FIELD_OP 0x81
-#define AML_EXT_DEVICE_OP 0x82
-#define AML_EXT_PROCESSOR_OP 0x83
-#define AML_EXT_POWER_RES_OP 0x84
-#define AML_EXT_THERMAL_ZONE_OP 0x85
-#define AML_EXT_INDEX_FIELD_OP 0x86
-#define AML_EXT_BANK_FIELD_OP 0x87
-#define AML_EXT_DATA_REGION_OP 0x88
+#define AML_EXT_MUTEX_OP 0x01
+#define AML_EXT_EVENT_OP 0x02
+#define AML_EXT_COND_REF_OF_OP 0x12
+#define AML_EXT_CREATE_FIELD_OP 0x13
+#define AML_EXT_LOAD_TABLE_OP 0x1f
+#define AML_EXT_LOAD_OP 0x20
+#define AML_EXT_STALL_OP 0x21
+#define AML_EXT_SLEEP_OP 0x22
+#define AML_EXT_ACQUIRE_OP 0x23
+#define AML_EXT_SIGNAL_OP 0x24
+#define AML_EXT_WAIT_OP 0x25
+#define AML_EXT_RESET_OP 0x26
+#define AML_EXT_RELEASE_OP 0x27
+#define AML_EXT_FROM_BCD_OP 0x28
+#define AML_EXT_TO_BCD_OP 0x29
+#define AML_EXT_UNLOAD_OP 0x2a
+#define AML_EXT_REVISION_OP 0x30
+#define AML_EXT_DEBUG_OP 0x31
+#define AML_EXT_FATAL_OP 0x32
+#define AML_EXT_TIMER_OP 0x33
+#define AML_EXT_REGION_OP 0x80
+#define AML_EXT_FIELD_OP 0x81
+#define AML_EXT_DEVICE_OP 0x82
+#define AML_EXT_PROCESSOR_OP 0x83
+#define AML_EXT_POWER_RES_OP 0x84
+#define AML_EXT_THERMAL_ZONE_OP 0x85
+#define AML_EXT_INDEX_FIELD_OP 0x86
+#define AML_EXT_BANK_FIELD_OP 0x87
+#define AML_EXT_DATA_REGION_OP 0x88
//
// FieldElement OpCode
//
-#define AML_FIELD_RESERVED_OP 0x00
-#define AML_FIELD_ACCESS_OP 0x01
-#define AML_FIELD_CONNECTION_OP 0x02
-#define AML_FIELD_EXT_ACCESS_OP 0x03
+#define AML_FIELD_RESERVED_OP 0x00
+#define AML_FIELD_ACCESS_OP 0x01
+#define AML_FIELD_CONNECTION_OP 0x02
+#define AML_FIELD_EXT_ACCESS_OP 0x03
//
// AML Name segment definitions
//
-#define AML_NAME_SEG_SIZE 4
+#define AML_NAME_SEG_SIZE 4
#endif
diff --git a/MdePkg/Include/IndustryStandard/Atapi.h b/MdePkg/Include/IndustryStandard/Atapi.h
index a886f59e..7f11302b 100644
--- a/MdePkg/Include/IndustryStandard/Atapi.h
+++ b/MdePkg/Include/IndustryStandard/Atapi.h
@@ -19,55 +19,55 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
/// ATA_IDENTIFY_DATA, which currently conforms to ATA-8.)
///
typedef struct {
- UINT16 config; ///< General Configuration.
- UINT16 cylinders; ///< Number of Cylinders.
- UINT16 reserved_2;
- UINT16 heads; ///< Number of logical heads.
- UINT16 vendor_data1;
- UINT16 vendor_data2;
- UINT16 sectors_per_track;
- UINT16 vendor_specific_7_9[3];
- CHAR8 SerialNo[20]; ///< ASCII
- UINT16 vendor_specific_20_21[2];
- UINT16 ecc_bytes_available;
- CHAR8 FirmwareVer[8]; ///< ASCII
- CHAR8 ModelName[40]; ///< ASCII
- UINT16 multi_sector_cmd_max_sct_cnt;
- UINT16 reserved_48;
- UINT16 capabilities;
- UINT16 reserved_50;
- UINT16 pio_cycle_timing;
- UINT16 reserved_52;
- UINT16 field_validity;
- UINT16 current_cylinders;
- UINT16 current_heads;
- UINT16 current_sectors;
- UINT16 CurrentCapacityLsb;
- UINT16 CurrentCapacityMsb;
- UINT16 reserved_59;
- UINT16 user_addressable_sectors_lo;
- UINT16 user_addressable_sectors_hi;
- UINT16 reserved_62;
- UINT16 multi_word_dma_mode;
- UINT16 advanced_pio_modes;
- UINT16 min_multi_word_dma_cycle_time;
- UINT16 rec_multi_word_dma_cycle_time;
- UINT16 min_pio_cycle_time_without_flow_control;
- UINT16 min_pio_cycle_time_with_flow_control;
- UINT16 reserved_69_79[11];
- UINT16 major_version_no;
- UINT16 minor_version_no;
- UINT16 command_set_supported_82; ///< word 82
- UINT16 command_set_supported_83; ///< word 83
- UINT16 command_set_feature_extn; ///< word 84
- UINT16 command_set_feature_enb_85; ///< word 85
- UINT16 command_set_feature_enb_86; ///< word 86
- UINT16 command_set_feature_default; ///< word 87
- UINT16 ultra_dma_mode; ///< word 88
- UINT16 reserved_89_127[39];
- UINT16 security_status;
- UINT16 vendor_data_129_159[31];
- UINT16 reserved_160_255[96];
+ UINT16 config; ///< General Configuration.
+ UINT16 cylinders; ///< Number of Cylinders.
+ UINT16 reserved_2;
+ UINT16 heads; ///< Number of logical heads.
+ UINT16 vendor_data1;
+ UINT16 vendor_data2;
+ UINT16 sectors_per_track;
+ UINT16 vendor_specific_7_9[3];
+ CHAR8 SerialNo[20]; ///< ASCII
+ UINT16 vendor_specific_20_21[2];
+ UINT16 ecc_bytes_available;
+ CHAR8 FirmwareVer[8]; ///< ASCII
+ CHAR8 ModelName[40]; ///< ASCII
+ UINT16 multi_sector_cmd_max_sct_cnt;
+ UINT16 reserved_48;
+ UINT16 capabilities;
+ UINT16 reserved_50;
+ UINT16 pio_cycle_timing;
+ UINT16 reserved_52;
+ UINT16 field_validity;
+ UINT16 current_cylinders;
+ UINT16 current_heads;
+ UINT16 current_sectors;
+ UINT16 CurrentCapacityLsb;
+ UINT16 CurrentCapacityMsb;
+ UINT16 reserved_59;
+ UINT16 user_addressable_sectors_lo;
+ UINT16 user_addressable_sectors_hi;
+ UINT16 reserved_62;
+ UINT16 multi_word_dma_mode;
+ UINT16 advanced_pio_modes;
+ UINT16 min_multi_word_dma_cycle_time;
+ UINT16 rec_multi_word_dma_cycle_time;
+ UINT16 min_pio_cycle_time_without_flow_control;
+ UINT16 min_pio_cycle_time_with_flow_control;
+ UINT16 reserved_69_79[11];
+ UINT16 major_version_no;
+ UINT16 minor_version_no;
+ UINT16 command_set_supported_82; ///< word 82
+ UINT16 command_set_supported_83; ///< word 83
+ UINT16 command_set_feature_extn; ///< word 84
+ UINT16 command_set_feature_enb_85; ///< word 85
+ UINT16 command_set_feature_enb_86; ///< word 86
+ UINT16 command_set_feature_default; ///< word 87
+ UINT16 ultra_dma_mode; ///< word 88
+ UINT16 reserved_89_127[39];
+ UINT16 security_status;
+ UINT16 vendor_data_129_159[31];
+ UINT16 reserved_160_255[96];
} ATA5_IDENTIFY_DATA;
///
@@ -76,107 +76,107 @@ typedef struct {
/// completion of the ATA IDENTIFY_DEVICE command.
///
typedef struct {
- UINT16 config; ///< General Configuration.
- UINT16 obsolete_1;
- UINT16 specific_config; ///< Specific Configuration.
- UINT16 obsolete_3;
- UINT16 retired_4_5[2];
- UINT16 obsolete_6;
- UINT16 cfa_reserved_7_8[2];
- UINT16 retired_9;
- CHAR8 SerialNo[20]; ///< word 10~19
- UINT16 retired_20_21[2];
- UINT16 obsolete_22;
- CHAR8 FirmwareVer[8]; ///< word 23~26
- CHAR8 ModelName[40]; ///< word 27~46
- UINT16 multi_sector_cmd_max_sct_cnt;
- UINT16 trusted_computing_support;
- UINT16 capabilities_49;
- UINT16 capabilities_50;
- UINT16 obsolete_51_52[2];
- UINT16 field_validity;
- UINT16 obsolete_54_58[5];
- UINT16 multi_sector_setting;
- UINT16 user_addressable_sectors_lo;
- UINT16 user_addressable_sectors_hi;
- UINT16 obsolete_62;
- UINT16 multi_word_dma_mode;
- UINT16 advanced_pio_modes;
- UINT16 min_multi_word_dma_cycle_time;
- UINT16 rec_multi_word_dma_cycle_time;
- UINT16 min_pio_cycle_time_without_flow_control;
- UINT16 min_pio_cycle_time_with_flow_control;
- UINT16 additional_supported; ///< word 69
- UINT16 reserved_70;
- UINT16 reserved_71_74[4]; ///< Reserved for IDENTIFY PACKET DEVICE cmd.
- UINT16 queue_depth;
- UINT16 serial_ata_capabilities;
- UINT16 reserved_77; ///< Reserved for Serial ATA
- UINT16 serial_ata_features_supported;
- UINT16 serial_ata_features_enabled;
- UINT16 major_version_no;
- UINT16 minor_version_no;
- UINT16 command_set_supported_82; ///< word 82
- UINT16 command_set_supported_83; ///< word 83
- UINT16 command_set_feature_extn; ///< word 84
- UINT16 command_set_feature_enb_85; ///< word 85
- UINT16 command_set_feature_enb_86; ///< word 86
- UINT16 command_set_feature_default; ///< word 87
- UINT16 ultra_dma_mode; ///< word 88
- UINT16 time_for_security_erase_unit;
- UINT16 time_for_enhanced_security_erase_unit;
- UINT16 advanced_power_management_level;
- UINT16 master_password_identifier;
- UINT16 hardware_configuration_test_result;
- UINT16 obsolete_94;
- UINT16 stream_minimum_request_size;
- UINT16 streaming_transfer_time_for_dma;
- UINT16 streaming_access_latency_for_dma_and_pio;
- UINT16 streaming_performance_granularity[2]; ///< word 98~99
- UINT16 maximum_lba_for_48bit_addressing[4]; ///< word 100~103
- UINT16 streaming_transfer_time_for_pio;
- UINT16 max_no_of_512byte_blocks_per_data_set_cmd;
- UINT16 phy_logic_sector_support; ///< word 106
- UINT16 interseek_delay_for_iso7779;
- UINT16 world_wide_name[4]; ///< word 108~111
- UINT16 reserved_for_128bit_wwn_112_115[4];
- UINT16 reserved_for_technical_report;
- UINT16 logic_sector_size_lo; ///< word 117
- UINT16 logic_sector_size_hi; ///< word 118
- UINT16 features_and_command_sets_supported_ext; ///< word 119
- UINT16 features_and_command_sets_enabled_ext; ///< word 120
- UINT16 reserved_121_126[6];
- UINT16 obsolete_127;
- UINT16 security_status; ///< word 128
- UINT16 vendor_specific_129_159[31];
- UINT16 cfa_power_mode; ///< word 160
- UINT16 reserved_for_compactflash_161_167[7];
- UINT16 device_nominal_form_factor;
- UINT16 is_data_set_cmd_supported;
- CHAR8 additional_product_identifier[8];
- UINT16 reserved_174_175[2];
- CHAR8 media_serial_number[60]; ///< word 176~205
- UINT16 sct_command_transport; ///< word 206
- UINT16 reserved_207_208[2];
- UINT16 alignment_logic_in_phy_blocks; ///< word 209
- UINT16 write_read_verify_sector_count_mode3[2]; ///< word 210~211
- UINT16 verify_sector_count_mode2[2];
- UINT16 nv_cache_capabilities;
- UINT16 nv_cache_size_in_logical_block_lsw; ///< word 215
- UINT16 nv_cache_size_in_logical_block_msw; ///< word 216
- UINT16 nominal_media_rotation_rate;
- UINT16 reserved_218;
- UINT16 nv_cache_options; ///< word 219
- UINT16 write_read_verify_mode; ///< word 220
- UINT16 reserved_221;
- UINT16 transport_major_revision_number;
- UINT16 transport_minor_revision_number;
- UINT16 reserved_224_229[6];
- UINT64 extended_no_of_addressable_sectors;
- UINT16 min_number_per_download_microcode_mode3; ///< word 234
- UINT16 max_number_per_download_microcode_mode3; ///< word 235
- UINT16 reserved_236_254[19];
- UINT16 integrity_word;
+ UINT16 config; ///< General Configuration.
+ UINT16 obsolete_1;
+ UINT16 specific_config; ///< Specific Configuration.
+ UINT16 obsolete_3;
+ UINT16 retired_4_5[2];
+ UINT16 obsolete_6;
+ UINT16 cfa_reserved_7_8[2];
+ UINT16 retired_9;
+ CHAR8 SerialNo[20]; ///< word 10~19
+ UINT16 retired_20_21[2];
+ UINT16 obsolete_22;
+ CHAR8 FirmwareVer[8]; ///< word 23~26
+ CHAR8 ModelName[40]; ///< word 27~46
+ UINT16 multi_sector_cmd_max_sct_cnt;
+ UINT16 trusted_computing_support;
+ UINT16 capabilities_49;
+ UINT16 capabilities_50;
+ UINT16 obsolete_51_52[2];
+ UINT16 field_validity;
+ UINT16 obsolete_54_58[5];
+ UINT16 multi_sector_setting;
+ UINT16 user_addressable_sectors_lo;
+ UINT16 user_addressable_sectors_hi;
+ UINT16 obsolete_62;
+ UINT16 multi_word_dma_mode;
+ UINT16 advanced_pio_modes;
+ UINT16 min_multi_word_dma_cycle_time;
+ UINT16 rec_multi_word_dma_cycle_time;
+ UINT16 min_pio_cycle_time_without_flow_control;
+ UINT16 min_pio_cycle_time_with_flow_control;
+ UINT16 additional_supported; ///< word 69
+ UINT16 reserved_70;
+ UINT16 reserved_71_74[4]; ///< Reserved for IDENTIFY PACKET DEVICE cmd.
+ UINT16 queue_depth;
+ UINT16 serial_ata_capabilities;
+ UINT16 reserved_77; ///< Reserved for Serial ATA
+ UINT16 serial_ata_features_supported;
+ UINT16 serial_ata_features_enabled;
+ UINT16 major_version_no;
+ UINT16 minor_version_no;
+ UINT16 command_set_supported_82; ///< word 82
+ UINT16 command_set_supported_83; ///< word 83
+ UINT16 command_set_feature_extn; ///< word 84
+ UINT16 command_set_feature_enb_85; ///< word 85
+ UINT16 command_set_feature_enb_86; ///< word 86
+ UINT16 command_set_feature_default; ///< word 87
+ UINT16 ultra_dma_mode; ///< word 88
+ UINT16 time_for_security_erase_unit;
+ UINT16 time_for_enhanced_security_erase_unit;
+ UINT16 advanced_power_management_level;
+ UINT16 master_password_identifier;
+ UINT16 hardware_configuration_test_result;
+ UINT16 obsolete_94;
+ UINT16 stream_minimum_request_size;
+ UINT16 streaming_transfer_time_for_dma;
+ UINT16 streaming_access_latency_for_dma_and_pio;
+ UINT16 streaming_performance_granularity[2]; ///< word 98~99
+ UINT16 maximum_lba_for_48bit_addressing[4]; ///< word 100~103
+ UINT16 streaming_transfer_time_for_pio;
+ UINT16 max_no_of_512byte_blocks_per_data_set_cmd;
+ UINT16 phy_logic_sector_support; ///< word 106
+ UINT16 interseek_delay_for_iso7779;
+ UINT16 world_wide_name[4]; ///< word 108~111
+ UINT16 reserved_for_128bit_wwn_112_115[4];
+ UINT16 reserved_for_technical_report;
+ UINT16 logic_sector_size_lo; ///< word 117
+ UINT16 logic_sector_size_hi; ///< word 118
+ UINT16 features_and_command_sets_supported_ext; ///< word 119
+ UINT16 features_and_command_sets_enabled_ext; ///< word 120
+ UINT16 reserved_121_126[6];
+ UINT16 obsolete_127;
+ UINT16 security_status; ///< word 128
+ UINT16 vendor_specific_129_159[31];
+ UINT16 cfa_power_mode; ///< word 160
+ UINT16 reserved_for_compactflash_161_167[7];
+ UINT16 device_nominal_form_factor;
+ UINT16 is_data_set_cmd_supported;
+ CHAR8 additional_product_identifier[8];
+ UINT16 reserved_174_175[2];
+ CHAR8 media_serial_number[60]; ///< word 176~205
+ UINT16 sct_command_transport; ///< word 206
+ UINT16 reserved_207_208[2];
+ UINT16 alignment_logic_in_phy_blocks; ///< word 209
+ UINT16 write_read_verify_sector_count_mode3[2]; ///< word 210~211
+ UINT16 verify_sector_count_mode2[2];
+ UINT16 nv_cache_capabilities;
+ UINT16 nv_cache_size_in_logical_block_lsw; ///< word 215
+ UINT16 nv_cache_size_in_logical_block_msw; ///< word 216
+ UINT16 nominal_media_rotation_rate;
+ UINT16 reserved_218;
+ UINT16 nv_cache_options; ///< word 219
+ UINT16 write_read_verify_mode; ///< word 220
+ UINT16 reserved_221;
+ UINT16 transport_major_revision_number;
+ UINT16 transport_minor_revision_number;
+ UINT16 reserved_224_229[6];
+ UINT64 extended_no_of_addressable_sectors;
+ UINT16 min_number_per_download_microcode_mode3; ///< word 234
+ UINT16 max_number_per_download_microcode_mode3; ///< word 235
+ UINT16 reserved_236_254[19];
+ UINT16 integrity_word;
} ATA_IDENTIFY_DATA;
///
@@ -185,135 +185,134 @@ typedef struct {
/// completion of the ATA IDENTIFY_PACKET_DEVICE command.
///
typedef struct {
- UINT16 config; ///< General Configuration.
- UINT16 reserved_1;
- UINT16 specific_config; ///< Specific Configuration.
- UINT16 reserved_3_9[7];
- CHAR8 SerialNo[20]; ///< word 10~19
- UINT16 reserved_20_22[3];
- CHAR8 FirmwareVer[8]; ///< word 23~26
- CHAR8 ModelName[40]; ///< word 27~46
- UINT16 reserved_47_48[2];
- UINT16 capabilities_49;
- UINT16 capabilities_50;
- UINT16 obsolete_51;
- UINT16 reserved_52;
- UINT16 field_validity; ///< word 53
- UINT16 reserved_54_61[8];
- UINT16 dma_dir;
- UINT16 multi_word_dma_mode; ///< word 63
- UINT16 advanced_pio_modes; ///< word 64
- UINT16 min_multi_word_dma_cycle_time;
- UINT16 rec_multi_word_dma_cycle_time;
- UINT16 min_pio_cycle_time_without_flow_control;
- UINT16 min_pio_cycle_time_with_flow_control;
- UINT16 reserved_69_70[2];
- UINT16 obsolete_71_72[2];
- UINT16 reserved_73_74[2];
- UINT16 obsolete_75;
- UINT16 serial_ata_capabilities;
- UINT16 reserved_77; ///< Reserved for Serial ATA
- UINT16 serial_ata_features_supported;
- UINT16 serial_ata_features_enabled;
- UINT16 major_version_no; ///< word 80
- UINT16 minor_version_no; ///< word 81
- UINT16 cmd_set_support_82;
- UINT16 cmd_set_support_83;
- UINT16 cmd_feature_support;
- UINT16 cmd_feature_enable_85;
- UINT16 cmd_feature_enable_86;
- UINT16 cmd_feature_default;
- UINT16 ultra_dma_select;
- UINT16 time_required_for_sec_erase; ///< word 89
- UINT16 time_required_for_enhanced_sec_erase; ///< word 90
- UINT16 advanced_power_management_level;
- UINT16 master_pwd_revison_code;
- UINT16 hardware_reset_result; ///< word 93
- UINT16 obsolete_94;
- UINT16 reserved_95_107[13];
- UINT16 world_wide_name[4]; ///< word 108~111
- UINT16 reserved_for_128bit_wwn_112_115[4];
- UINT16 reserved_116_118[3];
- UINT16 command_and_feature_sets_supported; ///< word 119
- UINT16 command_and_feature_sets_supported_enabled;
- UINT16 reserved_121_124[4];
- UINT16 atapi_byte_count_0_behavior; ///< word 125
- UINT16 obsolete_126_127[2];
- UINT16 security_status;
- UINT16 reserved_129_159[31];
- UINT16 cfa_reserved_160_175[16];
- UINT16 reserved_176_221[46];
- UINT16 transport_major_version;
- UINT16 transport_minor_version;
- UINT16 reserved_224_254[31];
- UINT16 integrity_word;
+ UINT16 config; ///< General Configuration.
+ UINT16 reserved_1;
+ UINT16 specific_config; ///< Specific Configuration.
+ UINT16 reserved_3_9[7];
+ CHAR8 SerialNo[20]; ///< word 10~19
+ UINT16 reserved_20_22[3];
+ CHAR8 FirmwareVer[8]; ///< word 23~26
+ CHAR8 ModelName[40]; ///< word 27~46
+ UINT16 reserved_47_48[2];
+ UINT16 capabilities_49;
+ UINT16 capabilities_50;
+ UINT16 obsolete_51;
+ UINT16 reserved_52;
+ UINT16 field_validity; ///< word 53
+ UINT16 reserved_54_61[8];
+ UINT16 dma_dir;
+ UINT16 multi_word_dma_mode; ///< word 63
+ UINT16 advanced_pio_modes; ///< word 64
+ UINT16 min_multi_word_dma_cycle_time;
+ UINT16 rec_multi_word_dma_cycle_time;
+ UINT16 min_pio_cycle_time_without_flow_control;
+ UINT16 min_pio_cycle_time_with_flow_control;
+ UINT16 reserved_69_70[2];
+ UINT16 obsolete_71_72[2];
+ UINT16 reserved_73_74[2];
+ UINT16 obsolete_75;
+ UINT16 serial_ata_capabilities;
+ UINT16 reserved_77; ///< Reserved for Serial ATA
+ UINT16 serial_ata_features_supported;
+ UINT16 serial_ata_features_enabled;
+ UINT16 major_version_no; ///< word 80
+ UINT16 minor_version_no; ///< word 81
+ UINT16 cmd_set_support_82;
+ UINT16 cmd_set_support_83;
+ UINT16 cmd_feature_support;
+ UINT16 cmd_feature_enable_85;
+ UINT16 cmd_feature_enable_86;
+ UINT16 cmd_feature_default;
+ UINT16 ultra_dma_select;
+ UINT16 time_required_for_sec_erase; ///< word 89
+ UINT16 time_required_for_enhanced_sec_erase; ///< word 90
+ UINT16 advanced_power_management_level;
+ UINT16 master_pwd_revison_code;
+ UINT16 hardware_reset_result; ///< word 93
+ UINT16 obsolete_94;
+ UINT16 reserved_95_107[13];
+ UINT16 world_wide_name[4]; ///< word 108~111
+ UINT16 reserved_for_128bit_wwn_112_115[4];
+ UINT16 reserved_116_118[3];
+ UINT16 command_and_feature_sets_supported; ///< word 119
+ UINT16 command_and_feature_sets_supported_enabled;
+ UINT16 reserved_121_124[4];
+ UINT16 atapi_byte_count_0_behavior; ///< word 125
+ UINT16 obsolete_126_127[2];
+ UINT16 security_status;
+ UINT16 reserved_129_159[31];
+ UINT16 cfa_reserved_160_175[16];
+ UINT16 reserved_176_221[46];
+ UINT16 transport_major_version;
+ UINT16 transport_minor_version;
+ UINT16 reserved_224_254[31];
+ UINT16 integrity_word;
} ATAPI_IDENTIFY_DATA;
-
///
/// Standard Quiry Data format, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
- UINT8 peripheral_type;
- UINT8 RMB;
- UINT8 version;
- UINT8 response_data_format;
- UINT8 addnl_length; ///< n - 4, Numbers of bytes following this one.
- UINT8 reserved_5;
- UINT8 reserved_6;
- UINT8 reserved_7;
- UINT8 vendor_info[8];
- UINT8 product_id[16];
- UINT8 product_revision_level[4];
- UINT8 vendor_specific_36_55[55 - 36 + 1];
- UINT8 reserved_56_95[95 - 56 + 1];
+ UINT8 peripheral_type;
+ UINT8 RMB;
+ UINT8 version;
+ UINT8 response_data_format;
+ UINT8 addnl_length; ///< n - 4, Numbers of bytes following this one.
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 reserved_7;
+ UINT8 vendor_info[8];
+ UINT8 product_id[16];
+ UINT8 product_revision_level[4];
+ UINT8 vendor_specific_36_55[55 - 36 + 1];
+ UINT8 reserved_56_95[95 - 56 + 1];
///
/// Vendor-specific parameters fields. The sizeof (ATAPI_INQUIRY_DATA) is 254
/// since allocation_length is one byte in ATAPI_INQUIRY_CMD.
///
- UINT8 vendor_specific_96_253[253 - 96 + 1];
+ UINT8 vendor_specific_96_253[253 - 96 + 1];
} ATAPI_INQUIRY_DATA;
///
/// Request Sense Standard Data, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
- UINT8 error_code : 7;
- UINT8 valid : 1;
- UINT8 reserved_1;
- UINT8 sense_key : 4;
- UINT8 reserved_2 : 1;
- UINT8 Vendor_specifc_1 : 3;
- UINT8 vendor_specific_3;
- UINT8 vendor_specific_4;
- UINT8 vendor_specific_5;
- UINT8 vendor_specific_6;
- UINT8 addnl_sense_length; ///< n - 7
- UINT8 vendor_specific_8;
- UINT8 vendor_specific_9;
- UINT8 vendor_specific_10;
- UINT8 vendor_specific_11;
- UINT8 addnl_sense_code; ///< mandatory
- UINT8 addnl_sense_code_qualifier; ///< mandatory
- UINT8 field_replaceable_unit_code; ///< optional
- UINT8 sense_key_specific_15 : 7;
- UINT8 SKSV : 1;
- UINT8 sense_key_specific_16;
- UINT8 sense_key_specific_17;
+ UINT8 error_code : 7;
+ UINT8 valid : 1;
+ UINT8 reserved_1;
+ UINT8 sense_key : 4;
+ UINT8 reserved_2 : 1;
+ UINT8 Vendor_specifc_1 : 3;
+ UINT8 vendor_specific_3;
+ UINT8 vendor_specific_4;
+ UINT8 vendor_specific_5;
+ UINT8 vendor_specific_6;
+ UINT8 addnl_sense_length; ///< n - 7
+ UINT8 vendor_specific_8;
+ UINT8 vendor_specific_9;
+ UINT8 vendor_specific_10;
+ UINT8 vendor_specific_11;
+ UINT8 addnl_sense_code; ///< mandatory
+ UINT8 addnl_sense_code_qualifier; ///< mandatory
+ UINT8 field_replaceable_unit_code; ///< optional
+ UINT8 sense_key_specific_15 : 7;
+ UINT8 SKSV : 1;
+ UINT8 sense_key_specific_16;
+ UINT8 sense_key_specific_17;
} ATAPI_REQUEST_SENSE_DATA;
///
/// READ CAPACITY Data, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
- UINT8 LastLba3;
- UINT8 LastLba2;
- UINT8 LastLba1;
- UINT8 LastLba0;
- UINT8 BlockSize3;
- UINT8 BlockSize2;
- UINT8 BlockSize1;
- UINT8 BlockSize0;
+ UINT8 LastLba3;
+ UINT8 LastLba2;
+ UINT8 LastLba1;
+ UINT8 LastLba0;
+ UINT8 BlockSize3;
+ UINT8 BlockSize2;
+ UINT8 BlockSize1;
+ UINT8 BlockSize0;
} ATAPI_READ_CAPACITY_DATA;
///
@@ -321,133 +320,133 @@ typedef struct {
/// defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
- UINT8 reserved_0;
- UINT8 reserved_1;
- UINT8 reserved_2;
- UINT8 Capacity_Length;
- UINT8 LastLba3;
- UINT8 LastLba2;
- UINT8 LastLba1;
- UINT8 LastLba0;
- UINT8 DesCode : 2;
- UINT8 reserved_9 : 6;
- UINT8 BlockSize2;
- UINT8 BlockSize1;
- UINT8 BlockSize0;
+ UINT8 reserved_0;
+ UINT8 reserved_1;
+ UINT8 reserved_2;
+ UINT8 Capacity_Length;
+ UINT8 LastLba3;
+ UINT8 LastLba2;
+ UINT8 LastLba1;
+ UINT8 LastLba0;
+ UINT8 DesCode : 2;
+ UINT8 reserved_9 : 6;
+ UINT8 BlockSize2;
+ UINT8 BlockSize1;
+ UINT8 BlockSize0;
} ATAPI_READ_FORMAT_CAPACITY_DATA;
///
/// Test Unit Ready Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
- UINT8 opcode;
- UINT8 reserved_1;
- UINT8 reserved_2;
- UINT8 reserved_3;
- UINT8 reserved_4;
- UINT8 reserved_5;
- UINT8 reserved_6;
- UINT8 reserved_7;
- UINT8 reserved_8;
- UINT8 reserved_9;
- UINT8 reserved_10;
- UINT8 reserved_11;
+ UINT8 opcode;
+ UINT8 reserved_1;
+ UINT8 reserved_2;
+ UINT8 reserved_3;
+ UINT8 reserved_4;
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 reserved_7;
+ UINT8 reserved_8;
+ UINT8 reserved_9;
+ UINT8 reserved_10;
+ UINT8 reserved_11;
} ATAPI_TEST_UNIT_READY_CMD;
///
/// INQUIRY Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
- UINT8 opcode;
- UINT8 reserved_1 : 5;
- UINT8 lun : 3;
- UINT8 page_code; ///< defined in SFF8090i, V6
- UINT8 reserved_3;
- UINT8 allocation_length;
- UINT8 reserved_5;
- UINT8 reserved_6;
- UINT8 reserved_7;
- UINT8 reserved_8;
- UINT8 reserved_9;
- UINT8 reserved_10;
- UINT8 reserved_11;
+ UINT8 opcode;
+ UINT8 reserved_1 : 5;
+ UINT8 lun : 3;
+ UINT8 page_code; ///< defined in SFF8090i, V6
+ UINT8 reserved_3;
+ UINT8 allocation_length;
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 reserved_7;
+ UINT8 reserved_8;
+ UINT8 reserved_9;
+ UINT8 reserved_10;
+ UINT8 reserved_11;
} ATAPI_INQUIRY_CMD;
///
/// REQUEST SENSE Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
- UINT8 opcode;
- UINT8 reserved_1 : 5;
- UINT8 lun : 3;
- UINT8 reserved_2;
- UINT8 reserved_3;
- UINT8 allocation_length;
- UINT8 reserved_5;
- UINT8 reserved_6;
- UINT8 reserved_7;
- UINT8 reserved_8;
- UINT8 reserved_9;
- UINT8 reserved_10;
- UINT8 reserved_11;
+ UINT8 opcode;
+ UINT8 reserved_1 : 5;
+ UINT8 lun : 3;
+ UINT8 reserved_2;
+ UINT8 reserved_3;
+ UINT8 allocation_length;
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 reserved_7;
+ UINT8 reserved_8;
+ UINT8 reserved_9;
+ UINT8 reserved_10;
+ UINT8 reserved_11;
} ATAPI_REQUEST_SENSE_CMD;
///
/// READ (10) Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
- UINT8 opcode;
- UINT8 reserved_1 : 5;
- UINT8 lun : 3;
- UINT8 Lba0;
- UINT8 Lba1;
- UINT8 Lba2;
- UINT8 Lba3;
- UINT8 reserved_6;
- UINT8 TranLen0;
- UINT8 TranLen1;
- UINT8 reserved_9;
- UINT8 reserved_10;
- UINT8 reserved_11;
+ UINT8 opcode;
+ UINT8 reserved_1 : 5;
+ UINT8 lun : 3;
+ UINT8 Lba0;
+ UINT8 Lba1;
+ UINT8 Lba2;
+ UINT8 Lba3;
+ UINT8 reserved_6;
+ UINT8 TranLen0;
+ UINT8 TranLen1;
+ UINT8 reserved_9;
+ UINT8 reserved_10;
+ UINT8 reserved_11;
} ATAPI_READ10_CMD;
///
/// READ Format Capacity Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
- UINT8 opcode;
- UINT8 reserved_1 : 5;
- UINT8 lun : 3;
- UINT8 reserved_2;
- UINT8 reserved_3;
- UINT8 reserved_4;
- UINT8 reserved_5;
- UINT8 reserved_6;
- UINT8 allocation_length_hi;
- UINT8 allocation_length_lo;
- UINT8 reserved_9;
- UINT8 reserved_10;
- UINT8 reserved_11;
+ UINT8 opcode;
+ UINT8 reserved_1 : 5;
+ UINT8 lun : 3;
+ UINT8 reserved_2;
+ UINT8 reserved_3;
+ UINT8 reserved_4;
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 allocation_length_hi;
+ UINT8 allocation_length_lo;
+ UINT8 reserved_9;
+ UINT8 reserved_10;
+ UINT8 reserved_11;
} ATAPI_READ_FORMAT_CAP_CMD;
///
/// MODE SENSE Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
- UINT8 opcode;
- UINT8 reserved_1 : 5;
- UINT8 lun : 3;
- UINT8 page_code : 6;
- UINT8 page_control : 2;
- UINT8 reserved_3;
- UINT8 reserved_4;
- UINT8 reserved_5;
- UINT8 reserved_6;
- UINT8 parameter_list_length_hi;
- UINT8 parameter_list_length_lo;
- UINT8 reserved_9;
- UINT8 reserved_10;
- UINT8 reserved_11;
+ UINT8 opcode;
+ UINT8 reserved_1 : 5;
+ UINT8 lun : 3;
+ UINT8 page_code : 6;
+ UINT8 page_control : 2;
+ UINT8 reserved_3;
+ UINT8 reserved_4;
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 parameter_list_length_hi;
+ UINT8 parameter_list_length_lo;
+ UINT8 reserved_9;
+ UINT8 reserved_10;
+ UINT8 reserved_11;
} ATAPI_MODE_SENSE_CMD;
///
@@ -455,83 +454,82 @@ typedef struct {
/// We add it here for the convenience of ATA/ATAPI module writers.
///
typedef union {
- UINT16 Data16[6];
- ATAPI_TEST_UNIT_READY_CMD TestUnitReady;
- ATAPI_READ10_CMD Read10;
- ATAPI_REQUEST_SENSE_CMD RequestSence;
- ATAPI_INQUIRY_CMD Inquiry;
- ATAPI_MODE_SENSE_CMD ModeSense;
- ATAPI_READ_FORMAT_CAP_CMD ReadFormatCapacity;
+ UINT16 Data16[6];
+ ATAPI_TEST_UNIT_READY_CMD TestUnitReady;
+ ATAPI_READ10_CMD Read10;
+ ATAPI_REQUEST_SENSE_CMD RequestSence;
+ ATAPI_INQUIRY_CMD Inquiry;
+ ATAPI_MODE_SENSE_CMD ModeSense;
+ ATAPI_READ_FORMAT_CAP_CMD ReadFormatCapacity;
} ATAPI_PACKET_COMMAND;
#pragma pack()
-
-#define ATAPI_MAX_DMA_EXT_CMD_SECTORS 0x10000
-#define ATAPI_MAX_DMA_CMD_SECTORS 0x100
+#define ATAPI_MAX_DMA_EXT_CMD_SECTORS 0x10000
+#define ATAPI_MAX_DMA_CMD_SECTORS 0x100
// ATA/ATAPI Signature equates
-#define ATA_SIGNATURE 0x0101 ///< defined in ACS-3
-#define ATAPI_SIGNATURE 0xeb14 ///< defined in ACS-3
-#define ATAPI_SIGNATURE_32 0xeb140101 ///< defined in ACS-3
+#define ATA_SIGNATURE 0x0101 ///< defined in ACS-3
+#define ATAPI_SIGNATURE 0xeb14 ///< defined in ACS-3
+#define ATAPI_SIGNATURE_32 0xeb140101 ///< defined in ACS-3
// Spin Up Configuration definitions
-#define ATA_SPINUP_CFG_REQUIRED_IDD_INCOMPLETE 0x37c8 ///< defined in ACS-3
-#define ATA_SPINUP_CFG_REQUIRED_IDD_COMPLETE 0x738c ///< defined in ACS-3
-#define ATA_SPINUP_CFG_NOT_REQUIRED_IDD_INCOMPLETE 0x8c73 ///< defined in ACS-3
-#define ATA_SPINUP_CFG_NOT_REQUIRED_IDD_COMPLETE 0xc837 ///< defined in ACS-3
+#define ATA_SPINUP_CFG_REQUIRED_IDD_INCOMPLETE 0x37c8 ///< defined in ACS-3
+#define ATA_SPINUP_CFG_REQUIRED_IDD_COMPLETE 0x738c ///< defined in ACS-3
+#define ATA_SPINUP_CFG_NOT_REQUIRED_IDD_INCOMPLETE 0x8c73 ///< defined in ACS-3
+#define ATA_SPINUP_CFG_NOT_REQUIRED_IDD_COMPLETE 0xc837 ///< defined in ACS-3
//
// ATA Packet Command Code
//
-#define ATA_CMD_FORMAT_UNIT 0x04 ///< defined in ATAPI Removable Rewritable Media Devices
-#define ATA_CMD_SOFT_RESET 0x08 ///< defined from ATA-3
-#define ATA_CMD_PACKET 0xA0 ///< defined from ATA-3
-#define ATA_CMD_IDENTIFY_DEVICE 0xA1 ///< defined from ATA-3
-#define ATA_CMD_SERVICE 0xA2 ///< defined from ATA-3
-#define ATA_CMD_TEST_UNIT_READY 0x00 ///< defined from ATA-1
-#define ATA_CMD_REQUEST_SENSE 0x03 ///< defined from ATA-4
-#define ATA_CMD_INQUIRY 0x12 ///< defined in ATAPI Removable Rewritable Media Devices
-#define ATA_CMD_READ_FORMAT_CAPACITY 0x23 ///< defined in ATAPI Removable Rewritable Media Devices
-#define ATA_CMD_READ_CAPACITY 0x25 ///< defined in ATAPI Removable Rewritable Media Devices
-#define ATA_CMD_READ_10 0x28 ///< defined in ATAPI Removable Rewritable Media Devices
-#define ATA_CMD_WRITE_10 0x2A ///< defined in ATAPI Removable Rewritable Media Devices
-#define ATA_CMD_ATAPI_SEEK 0x2B ///< defined in ATAPI Removable Rewritable Media Devices
-#define ATA_CMD_WRITE_AND_VERIFY 0x2E ///< defined in ATAPI Removable Rewritable Media Devices
-#define ATA_CMD_VERIFY 0x2F ///< defined in ATAPI Removable Rewritable Media Devices
-#define ATA_CMD_READ_12 0xA8 ///< defined in ATAPI Removable Rewritable Media Devices
-#define ATA_CMD_WRITE_12 0xAA ///< defined in ATAPI Removable Rewritable Media Devices
-#define ATA_CMD_START_STOP_UNIT 0x1B ///< defined in ATAPI Removable Rewritable Media Devices
-#define ATA_CMD_PREVENT_ALLOW_MEDIA_REMOVAL 0x1E ///< defined in ATAPI Removable Rewritable Media Devices
-#define ATA_CMD_MODE_SELECT 0x55 ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_FORMAT_UNIT 0x04 ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_SOFT_RESET 0x08 ///< defined from ATA-3
+#define ATA_CMD_PACKET 0xA0 ///< defined from ATA-3
+#define ATA_CMD_IDENTIFY_DEVICE 0xA1 ///< defined from ATA-3
+#define ATA_CMD_SERVICE 0xA2 ///< defined from ATA-3
+#define ATA_CMD_TEST_UNIT_READY 0x00 ///< defined from ATA-1
+#define ATA_CMD_REQUEST_SENSE 0x03 ///< defined from ATA-4
+#define ATA_CMD_INQUIRY 0x12 ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_READ_FORMAT_CAPACITY 0x23 ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_READ_CAPACITY 0x25 ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_READ_10 0x28 ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_WRITE_10 0x2A ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_ATAPI_SEEK 0x2B ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_WRITE_AND_VERIFY 0x2E ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_VERIFY 0x2F ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_READ_12 0xA8 ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_WRITE_12 0xAA ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_START_STOP_UNIT 0x1B ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_PREVENT_ALLOW_MEDIA_REMOVAL 0x1E ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_MODE_SELECT 0x55 ///< defined in ATAPI Removable Rewritable Media Devices
-#define ATA_CMD_MODE_SENSE 0x5A ///< defined in ATAPI Removable Rewritable Media Devices
- #define ATA_PAGE_CODE_READ_WRITE_ERROR 0x01 ///< defined in ATAPI Removable Rewritable Media Devices
- #define ATA_PAGE_CODE_CACHING_PAGE 0x08 ///< defined in ATAPI Removable Rewritable Media Devices
- #define ATA_PAGE_CODE_REMOVABLE_BLOCK_CAPABILITIES 0x1B ///< defined in ATAPI Removable Rewritable Media Devices
- #define ATA_PAGE_CODE_TIMER_PROTECT_PAGE 0x1C ///< defined in ATAPI Removable Rewritable Media Devices
- #define ATA_PAGE_CODE_RETURN_ALL_PAGES 0x3F ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_MODE_SENSE 0x5A ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_PAGE_CODE_READ_WRITE_ERROR 0x01 ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_PAGE_CODE_CACHING_PAGE 0x08 ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_PAGE_CODE_REMOVABLE_BLOCK_CAPABILITIES 0x1B ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_PAGE_CODE_TIMER_PROTECT_PAGE 0x1C ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_PAGE_CODE_RETURN_ALL_PAGES 0x3F ///< defined in ATAPI Removable Rewritable Media Devices
-#define ATA_CMD_GET_CONFIGURATION 0x46 ///< defined in ATAPI Multimedia Devices
- #define ATA_GCCD_RT_FIELD_VALUE_ALL 0x00 ///< defined in ATAPI Multimedia Devices
- #define ATA_GCCD_RT_FIELD_VALUE_CURRENT 0x01 ///< defined in ATAPI Multimedia Devices
- #define ATA_GCCD_RT_FIELD_VALUE_SINGLE 0x02 ///< defined in ATAPI Multimedia Devices
- #define ATA_GCCD_RT_FIELD_VALUE_RESERVED 0x03 ///< defined in ATAPI Multimedia Devices
+#define ATA_CMD_GET_CONFIGURATION 0x46 ///< defined in ATAPI Multimedia Devices
+#define ATA_GCCD_RT_FIELD_VALUE_ALL 0x00 ///< defined in ATAPI Multimedia Devices
+#define ATA_GCCD_RT_FIELD_VALUE_CURRENT 0x01 ///< defined in ATAPI Multimedia Devices
+#define ATA_GCCD_RT_FIELD_VALUE_SINGLE 0x02 ///< defined in ATAPI Multimedia Devices
+#define ATA_GCCD_RT_FIELD_VALUE_RESERVED 0x03 ///< defined in ATAPI Multimedia Devices
- #define ATA_FEATURE_LIST_PROFILE_LIST 0x0000 ///< defined in ATAPI Multimedia Devices
- #define ATA_FEATURE_LIST_CORE 0x0001 ///< defined in ATAPI Multimedia Devices
- #define ATA_FEATURE_LIST_MORPHING 0x0002 ///< defined in ATAPI Multimedia Devices
- #define ATA_FEATURE_LIST_REMOVEABLE_MEDIUM 0x0003 ///< defined in ATAPI Multimedia Devices
- #define ATA_FEATURE_LIST_WRITE_PROTECT 0x0004 ///< defined in ATAPI Multimedia Devices
+#define ATA_FEATURE_LIST_PROFILE_LIST 0x0000 ///< defined in ATAPI Multimedia Devices
+#define ATA_FEATURE_LIST_CORE 0x0001 ///< defined in ATAPI Multimedia Devices
+#define ATA_FEATURE_LIST_MORPHING 0x0002 ///< defined in ATAPI Multimedia Devices
+#define ATA_FEATURE_LIST_REMOVEABLE_MEDIUM 0x0003 ///< defined in ATAPI Multimedia Devices
+#define ATA_FEATURE_LIST_WRITE_PROTECT 0x0004 ///< defined in ATAPI Multimedia Devices
///
/// Start/Stop and Eject Operations
///
///@{
-#define ATA_CMD_SUBOP_STOP_DISC 0x00 ///< Stop the Disc
-#define ATA_CMD_SUBOP_START_DISC 0x01 ///< Start the Disc and acquire the format type
-#define ATA_CMD_SUBOP_EJECT_DISC 0x02 ///< Eject the Disc if possible
-#define ATA_CMD_SUBOP_CLOSE_TRAY 0x03 ///< Load the Disc (Close Tray)
+#define ATA_CMD_SUBOP_STOP_DISC 0x00 ///< Stop the Disc
+#define ATA_CMD_SUBOP_START_DISC 0x01 ///< Start the Disc and acquire the format type
+#define ATA_CMD_SUBOP_EJECT_DISC 0x02 ///< Eject the Disc if possible
+#define ATA_CMD_SUBOP_CLOSE_TRAY 0x03 ///< Load the Disc (Close Tray)
///@}
//
@@ -541,234 +539,234 @@ typedef union {
//
// Class 1: PIO Data-In Commands
//
-#define ATA_CMD_IDENTIFY_DRIVE 0xec ///< defined from ATA-3
-#define ATA_CMD_READ_BUFFER 0xe4 ///< defined from ATA-1
-#define ATA_CMD_READ_SECTORS 0x20 ///< defined from ATA-1
-#define ATA_CMD_READ_SECTORS_WITH_RETRY 0x21 ///< defined from ATA-1, obsoleted from ATA-5
-#define ATA_CMD_READ_LONG 0x22 ///< defined from ATA-1, obsoleted from ATA-5
-#define ATA_CMD_READ_LONG_WITH_RETRY 0x23 ///< defined from ATA-1, obsoleted from ATA-5
-#define ATA_CMD_READ_SECTORS_EXT 0x24 ///< defined from ATA-6
-#define ATA_CMD_READ_MULTIPLE 0xc4 ///< defined in ACS-3
-#define ATA_CMD_READ_MULTIPLE_EXT 0x29 ///< defined in ACS-3
-#define ATA_CMD_READ_LOG_EXT 0x2f ///< defined in ACS-3
+#define ATA_CMD_IDENTIFY_DRIVE 0xec ///< defined from ATA-3
+#define ATA_CMD_READ_BUFFER 0xe4 ///< defined from ATA-1
+#define ATA_CMD_READ_SECTORS 0x20 ///< defined from ATA-1
+#define ATA_CMD_READ_SECTORS_WITH_RETRY 0x21 ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_READ_LONG 0x22 ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_READ_LONG_WITH_RETRY 0x23 ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_READ_SECTORS_EXT 0x24 ///< defined from ATA-6
+#define ATA_CMD_READ_MULTIPLE 0xc4 ///< defined in ACS-3
+#define ATA_CMD_READ_MULTIPLE_EXT 0x29 ///< defined in ACS-3
+#define ATA_CMD_READ_LOG_EXT 0x2f ///< defined in ACS-3
//
// Class 2: PIO Data-Out Commands
//
-#define ATA_CMD_FORMAT_TRACK 0x50 ///< defined from ATA-1, obsoleted from ATA-4
-#define ATA_CMD_WRITE_BUFFER 0xe8 ///< defined from ATA-1
-#define ATA_CMD_WRITE_SECTORS 0x30 ///< defined from ATA-1
-#define ATA_CMD_WRITE_SECTORS_WITH_RETRY 0x31 ///< defined from ATA-1, obsoleted from ATA-5
-#define ATA_CMD_WRITE_LONG 0x32 ///< defined from ATA-1, obsoleted from ATA-5
-#define ATA_CMD_WRITE_LONG_WITH_RETRY 0x33 ///< defined from ATA-1, obsoleted from ATA-5
-#define ATA_CMD_WRITE_VERIFY 0x3c ///< defined from ATA-1, obsoleted from ATA-5
-#define ATA_CMD_WRITE_SECTORS_EXT 0x34 ///< defined from ATA-6
-#define ATA_CMD_WRITE_MULTIPLE 0xc5 ///< defined in ACS-3
-#define ATA_CMD_WRITE_MULTIPLE_EXT 0x39 ///< defined in ACS-3
+#define ATA_CMD_FORMAT_TRACK 0x50 ///< defined from ATA-1, obsoleted from ATA-4
+#define ATA_CMD_WRITE_BUFFER 0xe8 ///< defined from ATA-1
+#define ATA_CMD_WRITE_SECTORS 0x30 ///< defined from ATA-1
+#define ATA_CMD_WRITE_SECTORS_WITH_RETRY 0x31 ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_WRITE_LONG 0x32 ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_WRITE_LONG_WITH_RETRY 0x33 ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_WRITE_VERIFY 0x3c ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_WRITE_SECTORS_EXT 0x34 ///< defined from ATA-6
+#define ATA_CMD_WRITE_MULTIPLE 0xc5 ///< defined in ACS-3
+#define ATA_CMD_WRITE_MULTIPLE_EXT 0x39 ///< defined in ACS-3
//
// Class 3 No Data Command
//
-#define ATA_CMD_ACK_MEDIA_CHANGE 0xdb ///< defined from ATA-1, obsoleted from ATA-5
-#define ATA_CMD_BOOT_POST_BOOT 0xdc ///< defined from ATA-1, obsoleted from ATA-3
-#define ATA_CMD_BOOT_PRE_BOOT 0xdd ///< defined from ATA-1, obsoleted from ATA-3
-#define ATA_CMD_CHECK_POWER_MODE 0x98 ///< defined from ATA-1, obsoleted from ATA-4
-#define ATA_CMD_CHECK_POWER_MODE_ALIAS 0xe5 ///< defined from ATA-1
-#define ATA_CMD_DOOR_LOCK 0xde ///< defined from ATA-1
-#define ATA_CMD_DOOR_UNLOCK 0xdf ///< defined from ATA-1
-#define ATA_CMD_EXEC_DRIVE_DIAG 0x90 ///< defined from ATA-1
-#define ATA_CMD_IDLE_ALIAS 0x97 ///< defined from ATA-1, obsoleted from ATA-4
-#define ATA_CMD_IDLE 0xe3 ///< defined from ATA-1
-#define ATA_CMD_IDLE_IMMEDIATE 0x95 ///< defined from ATA-1, obsoleted from ATA-4
-#define ATA_CMD_IDLE_IMMEDIATE_ALIAS 0xe1 ///< defined from ATA-1
-#define ATA_CMD_INIT_DRIVE_PARAM 0x91 ///< defined from ATA-1, obsoleted from ATA-6
-#define ATA_CMD_RECALIBRATE 0x10 ///< defined from ATA-1, obsoleted from ATA-4
-#define ATA_CMD_READ_DRIVE_STATE 0xe9 ///< defined from ATA-1, obsoleted from ATA-3
-#define ATA_CMD_SET_MULTIPLE_MODE 0xC6 ///< defined from ATA-2
-#define ATA_CMD_READ_VERIFY 0x40 ///< defined from ATA-1
-#define ATA_CMD_READ_VERIFY_WITH_RETRY 0x41 ///< defined from ATA-1, obsoleted from ATA-5
-#define ATA_CMD_SEEK 0x70 ///< defined from ATA-1
-#define ATA_CMD_SET_FEATURES 0xef ///< defined from ATA-1
-#define ATA_CMD_STANDBY 0x96 ///< defined from ATA-1, obsoleted from ATA-4
-#define ATA_CMD_STANDBY_ALIAS 0xe2 ///< defined from ATA-1
-#define ATA_CMD_STANDBY_IMMEDIATE 0x94 ///< defined from ATA-1, obsoleted from ATA-4
-#define ATA_CMD_STANDBY_IMMEDIATE_ALIAS 0xe0 ///< defined from ATA-1
-#define ATA_CMD_SLEEP 0xe6 ///< defined in ACS-3
-#define ATA_CMD_READ_NATIVE_MAX_ADDRESS 0xf8 ///< defined in ATA-6
-#define ATA_CMD_READ_NATIVE_MAX_ADDRESS_EXT 0x27 ///< defined in ATA-6
+#define ATA_CMD_ACK_MEDIA_CHANGE 0xdb ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_BOOT_POST_BOOT 0xdc ///< defined from ATA-1, obsoleted from ATA-3
+#define ATA_CMD_BOOT_PRE_BOOT 0xdd ///< defined from ATA-1, obsoleted from ATA-3
+#define ATA_CMD_CHECK_POWER_MODE 0x98 ///< defined from ATA-1, obsoleted from ATA-4
+#define ATA_CMD_CHECK_POWER_MODE_ALIAS 0xe5 ///< defined from ATA-1
+#define ATA_CMD_DOOR_LOCK 0xde ///< defined from ATA-1
+#define ATA_CMD_DOOR_UNLOCK 0xdf ///< defined from ATA-1
+#define ATA_CMD_EXEC_DRIVE_DIAG 0x90 ///< defined from ATA-1
+#define ATA_CMD_IDLE_ALIAS 0x97 ///< defined from ATA-1, obsoleted from ATA-4
+#define ATA_CMD_IDLE 0xe3 ///< defined from ATA-1
+#define ATA_CMD_IDLE_IMMEDIATE 0x95 ///< defined from ATA-1, obsoleted from ATA-4
+#define ATA_CMD_IDLE_IMMEDIATE_ALIAS 0xe1 ///< defined from ATA-1
+#define ATA_CMD_INIT_DRIVE_PARAM 0x91 ///< defined from ATA-1, obsoleted from ATA-6
+#define ATA_CMD_RECALIBRATE 0x10 ///< defined from ATA-1, obsoleted from ATA-4
+#define ATA_CMD_READ_DRIVE_STATE 0xe9 ///< defined from ATA-1, obsoleted from ATA-3
+#define ATA_CMD_SET_MULTIPLE_MODE 0xC6 ///< defined from ATA-2
+#define ATA_CMD_READ_VERIFY 0x40 ///< defined from ATA-1
+#define ATA_CMD_READ_VERIFY_WITH_RETRY 0x41 ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_SEEK 0x70 ///< defined from ATA-1
+#define ATA_CMD_SET_FEATURES 0xef ///< defined from ATA-1
+#define ATA_CMD_STANDBY 0x96 ///< defined from ATA-1, obsoleted from ATA-4
+#define ATA_CMD_STANDBY_ALIAS 0xe2 ///< defined from ATA-1
+#define ATA_CMD_STANDBY_IMMEDIATE 0x94 ///< defined from ATA-1, obsoleted from ATA-4
+#define ATA_CMD_STANDBY_IMMEDIATE_ALIAS 0xe0 ///< defined from ATA-1
+#define ATA_CMD_SLEEP 0xe6 ///< defined in ACS-3
+#define ATA_CMD_READ_NATIVE_MAX_ADDRESS 0xf8 ///< defined in ATA-6
+#define ATA_CMD_READ_NATIVE_MAX_ADDRESS_EXT 0x27 ///< defined in ATA-6
//
// Set Features Sub Command
//
-#define ATA_SUB_CMD_ENABLE_VOLATILE_WRITE_CACHE 0x02 ///< defined in ACS-3
-#define ATA_SUB_CMD_SET_TRANSFER_MODE 0x03 ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_APM 0x05 ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_PUIS 0x06 ///< defined in ACS-3
-#define ATA_SUB_CMD_PUIS_SET_DEVICE_SPINUP 0x07 ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_WRITE_READ_VERIFY 0x0b ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_SATA_FEATURE 0x10 ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_MEDIA_STATUS_NOTIFICATION 0x31 ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_FREE_FALL_CONTROL 0x41 ///< defined in ACS-3
-#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_ENABLE 0x42 ///< defined in ACS-3
-#define ATA_SUB_CMD_SET_MAX_HOST_INTERFACE_SECTOR_TIMES 0x43 ///< defined in ACS-3
-#define ATA_SUB_CMD_EXTENDED_POWER_CONDITIONS 0x4a ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_READ_LOOK_AHEAD 0x55 ///< defined in ACS-3
-#define ATA_SUB_CMD_EN_DIS_DSN_FEATURE 0x63 ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_REVERT_TO_POWER_ON_DEFAULTS 0x66 ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_VOLATILE_WRITE_CACHE 0x82 ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_APM 0x85 ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_PUIS 0x86 ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_WRITE_READ_VERIFY 0x8b ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_SATA_FEATURE 0x90 ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_MEDIA_STATUS_NOTIFICATION 0x95 ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_READ_LOOK_AHEAD 0xaa ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_FREE_FALL_CONTROL 0xc1 ///< defined in ACS-3
-#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_DISABLE 0xc2 ///< defined in ACS-3
-#define ATA_SUB_CMD_EN_DIS_SENSE_DATA_REPORTING 0xc3 ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_REVERT_TO_POWER_ON_DEFAULTS 0xcc ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_VOLATILE_WRITE_CACHE 0x02 ///< defined in ACS-3
+#define ATA_SUB_CMD_SET_TRANSFER_MODE 0x03 ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_APM 0x05 ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_PUIS 0x06 ///< defined in ACS-3
+#define ATA_SUB_CMD_PUIS_SET_DEVICE_SPINUP 0x07 ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_WRITE_READ_VERIFY 0x0b ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_SATA_FEATURE 0x10 ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_MEDIA_STATUS_NOTIFICATION 0x31 ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_FREE_FALL_CONTROL 0x41 ///< defined in ACS-3
+#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_ENABLE 0x42 ///< defined in ACS-3
+#define ATA_SUB_CMD_SET_MAX_HOST_INTERFACE_SECTOR_TIMES 0x43 ///< defined in ACS-3
+#define ATA_SUB_CMD_EXTENDED_POWER_CONDITIONS 0x4a ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_READ_LOOK_AHEAD 0x55 ///< defined in ACS-3
+#define ATA_SUB_CMD_EN_DIS_DSN_FEATURE 0x63 ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_REVERT_TO_POWER_ON_DEFAULTS 0x66 ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_VOLATILE_WRITE_CACHE 0x82 ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_APM 0x85 ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_PUIS 0x86 ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_WRITE_READ_VERIFY 0x8b ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_SATA_FEATURE 0x90 ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_MEDIA_STATUS_NOTIFICATION 0x95 ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_READ_LOOK_AHEAD 0xaa ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_FREE_FALL_CONTROL 0xc1 ///< defined in ACS-3
+#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_DISABLE 0xc2 ///< defined in ACS-3
+#define ATA_SUB_CMD_EN_DIS_SENSE_DATA_REPORTING 0xc3 ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_REVERT_TO_POWER_ON_DEFAULTS 0xcc ///< defined in ACS-3
//
// S.M.A.R.T
//
-#define ATA_CMD_SMART 0xb0 ///< defined from ATA-3
-#define ATA_CONSTANT_C2 0xc2 ///< reserved
-#define ATA_CONSTANT_4F 0x4f ///< reserved
+#define ATA_CMD_SMART 0xb0 ///< defined from ATA-3
+#define ATA_CONSTANT_C2 0xc2 ///< reserved
+#define ATA_CONSTANT_4F 0x4f ///< reserved
-#define ATA_SMART_READ_DATA 0xd0 ///< defined in ACS-3
+#define ATA_SMART_READ_DATA 0xd0 ///< defined in ACS-3
-#define ATA_SMART_AUTOSAVE 0xd2 ///< defined in ACS-3
- #define ATA_AUTOSAVE_DISABLE_ATTR 0x00
- #define ATA_AUTOSAVE_ENABLE_ATTR 0xf1
+#define ATA_SMART_AUTOSAVE 0xd2 ///< defined in ACS-3
+#define ATA_AUTOSAVE_DISABLE_ATTR 0x00
+#define ATA_AUTOSAVE_ENABLE_ATTR 0xf1
-#define ATA_SMART_EXECUTE_OFFLINE_IMMEDIATE 0xd4 ///< defined in ACS-3
- #define ATA_EXECUTE_SMART_OFFLINE_ROUTINE 0x00 ///< defined in ACS-3
- #define ATA_EXECUTE_SMART_OFFLINE_SHORT_SELFTEST 0x01 ///< defined in ACS-3
- #define ATA_EXECUTE_SMART_OFFLINE_EXTENDED_SELFTEST 0x02 ///< defined in ACS-3
- #define ATA_EXECUTE_SMART_OFFLINE_CONVEYANCE_SELFTEST 0x03 ///< defined in ACS-3
- #define ATA_EXECUTE_SMART_OFFLINE_SELECTIVE_SELFTEST 0x04 ///< defined in ACS-3
- #define ATA_SMART_ABORT_SELF_TEST_SUBROUTINE 0x7f ///< defined in ACS-3
- #define ATA_EXECUTE_SMART_CAPTIVE_SHORT_SELFTEST 0x81 ///< defined in ACS-3
- #define ATA_EXECUTE_SMART_CAPTIVE_EXTENDED_SELFTEST 0x82 ///< defined in ACS-3
- #define ATA_EXECUTE_SMART_CAPTIVE_CONVEYANCE_SELFTEST 0x83 ///< defined in ACS-3
- #define ATA_EXECUTE_SMART_CAPTIVE_SELECTIVE_SELFTEST 0x84 ///< defined in ACS-3
+#define ATA_SMART_EXECUTE_OFFLINE_IMMEDIATE 0xd4 ///< defined in ACS-3
+#define ATA_EXECUTE_SMART_OFFLINE_ROUTINE 0x00 ///< defined in ACS-3
+#define ATA_EXECUTE_SMART_OFFLINE_SHORT_SELFTEST 0x01 ///< defined in ACS-3
+#define ATA_EXECUTE_SMART_OFFLINE_EXTENDED_SELFTEST 0x02 ///< defined in ACS-3
+#define ATA_EXECUTE_SMART_OFFLINE_CONVEYANCE_SELFTEST 0x03 ///< defined in ACS-3
+#define ATA_EXECUTE_SMART_OFFLINE_SELECTIVE_SELFTEST 0x04 ///< defined in ACS-3
+#define ATA_SMART_ABORT_SELF_TEST_SUBROUTINE 0x7f ///< defined in ACS-3
+#define ATA_EXECUTE_SMART_CAPTIVE_SHORT_SELFTEST 0x81 ///< defined in ACS-3
+#define ATA_EXECUTE_SMART_CAPTIVE_EXTENDED_SELFTEST 0x82 ///< defined in ACS-3
+#define ATA_EXECUTE_SMART_CAPTIVE_CONVEYANCE_SELFTEST 0x83 ///< defined in ACS-3
+#define ATA_EXECUTE_SMART_CAPTIVE_SELECTIVE_SELFTEST 0x84 ///< defined in ACS-3
-#define ATA_SMART_READLOG 0xd5 ///< defined in ACS-3
-#define ATA_SMART_WRITELOG 0xd6 ///< defined in ACS-3
-#define ATA_SMART_ENABLE_OPERATION 0xd8 ///< reserved
-#define ATA_SMART_DISABLE_OPERATION 0xd9 ///< defined in ACS-3
-#define ATA_SMART_RETURN_STATUS 0xda ///< defined from ATA-3
+#define ATA_SMART_READLOG 0xd5 ///< defined in ACS-3
+#define ATA_SMART_WRITELOG 0xd6 ///< defined in ACS-3
+#define ATA_SMART_ENABLE_OPERATION 0xd8 ///< reserved
+#define ATA_SMART_DISABLE_OPERATION 0xd9 ///< defined in ACS-3
+#define ATA_SMART_RETURN_STATUS 0xda ///< defined from ATA-3
-#define ATA_SMART_THRESHOLD_NOT_EXCEEDED_VALUE 0xc24f ///< defined in ACS-3
-#define ATA_SMART_THRESHOLD_EXCEEDED_VALUE 0x2cf4 ///< defined in ACS-3
+#define ATA_SMART_THRESHOLD_NOT_EXCEEDED_VALUE 0xc24f ///< defined in ACS-3
+#define ATA_SMART_THRESHOLD_EXCEEDED_VALUE 0x2cf4 ///< defined in ACS-3
// SMART Log Definitions
-#define ATA_SMART_LOG_DIRECTORY 0x00 ///< defined in ACS-3
-#define ATA_SMART_SUM_SMART_ERROR_LOG 0x01 ///< defined in ACS-3
-#define ATA_SMART_COMP_SMART_ERROR_LOG 0x02 ///< defined in ACS-3
-#define ATA_SMART_EXT_COMP_SMART_ERROR_LOG 0x03 ///< defined in ACS-3
-#define ATA_SMART_SMART_SELFTEST_LOG 0x06 ///< defined in ACS-3
-#define ATA_SMART_EXT_SMART_SELFTEST_LOG 0x07 ///< defined in ACS-3
-#define ATA_SMART_SELECTIVE_SELFTEST_LOG 0x09 ///< defined in ACS-3
-#define ATA_SMART_HOST_VENDOR_SPECIFIC 0x80 ///< defined in ACS-3
-#define ATA_SMART_DEVICE_VENDOR_SPECIFIC 0xa0 ///< defined in ACS-3
+#define ATA_SMART_LOG_DIRECTORY 0x00 ///< defined in ACS-3
+#define ATA_SMART_SUM_SMART_ERROR_LOG 0x01 ///< defined in ACS-3
+#define ATA_SMART_COMP_SMART_ERROR_LOG 0x02 ///< defined in ACS-3
+#define ATA_SMART_EXT_COMP_SMART_ERROR_LOG 0x03 ///< defined in ACS-3
+#define ATA_SMART_SMART_SELFTEST_LOG 0x06 ///< defined in ACS-3
+#define ATA_SMART_EXT_SMART_SELFTEST_LOG 0x07 ///< defined in ACS-3
+#define ATA_SMART_SELECTIVE_SELFTEST_LOG 0x09 ///< defined in ACS-3
+#define ATA_SMART_HOST_VENDOR_SPECIFIC 0x80 ///< defined in ACS-3
+#define ATA_SMART_DEVICE_VENDOR_SPECIFIC 0xa0 ///< defined in ACS-3
//
// Class 4: DMA Command
//
-#define ATA_CMD_READ_DMA 0xc8 ///< defined from ATA-1
-#define ATA_CMD_READ_DMA_WITH_RETRY 0xc9 ///< defined from ATA-1, obsoleted from ATA-5
-#define ATA_CMD_READ_DMA_EXT 0x25 ///< defined from ATA-6
-#define ATA_CMD_WRITE_DMA 0xca ///< defined from ATA-1
-#define ATA_CMD_WRITE_DMA_WITH_RETRY 0xcb ///< defined from ATA-1, obsoleted from ATA-
-#define ATA_CMD_WRITE_DMA_EXT 0x35 ///< defined from ATA-6
+#define ATA_CMD_READ_DMA 0xc8 ///< defined from ATA-1
+#define ATA_CMD_READ_DMA_WITH_RETRY 0xc9 ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_READ_DMA_EXT 0x25 ///< defined from ATA-6
+#define ATA_CMD_WRITE_DMA 0xca ///< defined from ATA-1
+#define ATA_CMD_WRITE_DMA_WITH_RETRY 0xcb ///< defined from ATA-1, obsoleted from ATA-
+#define ATA_CMD_WRITE_DMA_EXT 0x35 ///< defined from ATA-6
//
// ATA Security commands
//
-#define ATA_CMD_SECURITY_SET_PASSWORD 0xf1 ///< defined in ACS-3
-#define ATA_CMD_SECURITY_UNLOCK 0xf2 ///< defined in ACS-3
-#define ATA_CMD_SECURITY_ERASE_PREPARE 0xf3 ///< defined in ACS-3
-#define ATA_CMD_SECURITY_ERASE_UNIT 0xf4 ///< defined in ACS-3
-#define ATA_CMD_SECURITY_FREEZE_LOCK 0xf5 ///< defined in ACS-3
-#define ATA_CMD_SECURITY_DISABLE_PASSWORD 0xf6 ///< defined in ACS-3
+#define ATA_CMD_SECURITY_SET_PASSWORD 0xf1 ///< defined in ACS-3
+#define ATA_CMD_SECURITY_UNLOCK 0xf2 ///< defined in ACS-3
+#define ATA_CMD_SECURITY_ERASE_PREPARE 0xf3 ///< defined in ACS-3
+#define ATA_CMD_SECURITY_ERASE_UNIT 0xf4 ///< defined in ACS-3
+#define ATA_CMD_SECURITY_FREEZE_LOCK 0xf5 ///< defined in ACS-3
+#define ATA_CMD_SECURITY_DISABLE_PASSWORD 0xf6 ///< defined in ACS-3
-#define ATA_SECURITY_BUFFER_LENGTH 512 ///< defined in ACS-3
+#define ATA_SECURITY_BUFFER_LENGTH 512 ///< defined in ACS-3
//
// ATA Device Config Overlay
//
-#define ATA_CMD_DEV_CONFIG_OVERLAY 0xb1 ///< defined from ATA-6
- #define ATA_CMD_DEV_CONFIG_RESTORE_FEATURE 0xc0 ///< defined from ATA-6
- #define ATA_CMD_DEV_CONFIG_FREEZELOCK_FEATURE 0xc1 ///< defined from ATA-6
- #define ATA_CMD_DEV_CONFIG_IDENTIFY_FEATURE 0xc2 ///< defined from ATA-6
- #define ATA_CMD_DEV_CONFIG_SET_FEATURE 0xc3 ///< defined from ATA-6
+#define ATA_CMD_DEV_CONFIG_OVERLAY 0xb1 ///< defined from ATA-6
+#define ATA_CMD_DEV_CONFIG_RESTORE_FEATURE 0xc0 ///< defined from ATA-6
+#define ATA_CMD_DEV_CONFIG_FREEZELOCK_FEATURE 0xc1 ///< defined from ATA-6
+#define ATA_CMD_DEV_CONFIG_IDENTIFY_FEATURE 0xc2 ///< defined from ATA-6
+#define ATA_CMD_DEV_CONFIG_SET_FEATURE 0xc3 ///< defined from ATA-6
//
// ATA Trusted Computing Feature Set Commands
//
-#define ATA_CMD_TRUSTED_NON_DATA 0x5b ///< defined in ACS-3
-#define ATA_CMD_TRUSTED_RECEIVE 0x5c ///< defined in ACS-3
-#define ATA_CMD_TRUSTED_RECEIVE_DMA 0x5d ///< defined in ACS-3
-#define ATA_CMD_TRUSTED_SEND 0x5e ///< defined in ACS-3
-#define ATA_CMD_TRUSTED_SEND_DMA 0x5f ///< defined in ACS-3
+#define ATA_CMD_TRUSTED_NON_DATA 0x5b ///< defined in ACS-3
+#define ATA_CMD_TRUSTED_RECEIVE 0x5c ///< defined in ACS-3
+#define ATA_CMD_TRUSTED_RECEIVE_DMA 0x5d ///< defined in ACS-3
+#define ATA_CMD_TRUSTED_SEND 0x5e ///< defined in ACS-3
+#define ATA_CMD_TRUSTED_SEND_DMA 0x5f ///< defined in ACS-3
//
// ATA Trusted Receive Fields
//
-#define ATA_TR_RETURN_SECURITY_PROTOCOL_INFORMATION 0x00 ///< defined in ACS-3
-#define ATA_TR_SECURITY_PROTOCOL_JEDEC_RESERVED 0xec ///< defined in ACS-3
-#define ATA_TR_SECURITY_PROTOCOL_SDCARD_RESERVED 0xed ///< defined in ACS-3
-#define ATA_TR_SECURITY_PROTOCOL_IEEE1667_RESERVED 0xee ///< defined in ACS-3
+#define ATA_TR_RETURN_SECURITY_PROTOCOL_INFORMATION 0x00 ///< defined in ACS-3
+#define ATA_TR_SECURITY_PROTOCOL_JEDEC_RESERVED 0xec ///< defined in ACS-3
+#define ATA_TR_SECURITY_PROTOCOL_SDCARD_RESERVED 0xed ///< defined in ACS-3
+#define ATA_TR_SECURITY_PROTOCOL_IEEE1667_RESERVED 0xee ///< defined in ACS-3
//
// Equates used for Acoustic Flags
//
-#define ATA_ACOUSTIC_LEVEL_BYPASS 0xff ///< defined from ATA-6
-#define ATA_ACOUSTIC_LEVEL_MAXIMUM_PERFORMANCE 0xfe ///< defined from ATA-6
-#define ATA_ACOUSTIC_LEVEL_QUIET 0x80 ///< defined from ATA-6
+#define ATA_ACOUSTIC_LEVEL_BYPASS 0xff ///< defined from ATA-6
+#define ATA_ACOUSTIC_LEVEL_MAXIMUM_PERFORMANCE 0xfe ///< defined from ATA-6
+#define ATA_ACOUSTIC_LEVEL_QUIET 0x80 ///< defined from ATA-6
//
// Equates used for DiPM Support
//
-#define ATA_CMD_DIPM_SUB 0x03 // defined in ACS-3 : Count value in SetFeature identification : 03h Device-initiated interface power state transitions
- #define ATA_DIPM_ENABLE 0x10 // defined in ACS-3
- #define ATA_DIPM_DISABLE 0x90 // defined in ACS-3
+#define ATA_CMD_DIPM_SUB 0x03 // defined in ACS-3 : Count value in SetFeature identification : 03h Device-initiated interface power state transitions
+#define ATA_DIPM_ENABLE 0x10 // defined in ACS-3
+#define ATA_DIPM_DISABLE 0x90 // defined in ACS-3
//
// Equates used for DevSleep Support
//
-#define ATA_CMD_DEVSLEEP_SUB 0x09 // defined in SATA 3.2 Gold Spec : Count value in SetFeature identification : 09h Device Sleep
- #define ATA_DEVSLEEP_ENABLE 0x10 // defined in SATA 3.2 Gold Spec
- #define ATA_DEVSLEEP_DISABLE 0x90 // defined in SATA 3.2 Gold Spec
+#define ATA_CMD_DEVSLEEP_SUB 0x09 // defined in SATA 3.2 Gold Spec : Count value in SetFeature identification : 09h Device Sleep
+#define ATA_DEVSLEEP_ENABLE 0x10 // defined in SATA 3.2 Gold Spec
+#define ATA_DEVSLEEP_DISABLE 0x90 // defined in SATA 3.2 Gold Spec
-#define ATA_DEVSLP_EXIT_TIMEOUT 20 // MDAT - 20 ms
-#define ATA_DEVSLP_MINIMUM_DETECTION_TIME 10 // DMDT - 10 us
-#define ATA_DEVSLP_MINIMUM_ASSERTION_TIME 10 // DETO - 10 ms
+#define ATA_DEVSLP_EXIT_TIMEOUT 20 // MDAT - 20 ms
+#define ATA_DEVSLP_MINIMUM_DETECTION_TIME 10 // DMDT - 10 us
+#define ATA_DEVSLP_MINIMUM_ASSERTION_TIME 10 // DETO - 10 ms
//
// Set MAX Commands
//
-#define ATA_CMD_SET_MAX_ADDRESS_EXT 0x37 ///< defined from ATA-6
-#define ATA_CMD_SET_MAX_ADDRESS 0xf9 ///< defined from ATA-6
- #define ATA_SET_MAX_SET_PASSWORD 0x01 ///< defined from ATA-6
- #define ATA_SET_MAX_LOCK 0x02 ///< defined from ATA-6
- #define ATA_SET_MAX_UNLOCK 0x03 ///< defined from ATA-6
- #define ATA_SET_MAX_FREEZE_LOCK 0x04 ///< defined from ATA-6
+#define ATA_CMD_SET_MAX_ADDRESS_EXT 0x37 ///< defined from ATA-6
+#define ATA_CMD_SET_MAX_ADDRESS 0xf9 ///< defined from ATA-6
+#define ATA_SET_MAX_SET_PASSWORD 0x01 ///< defined from ATA-6
+#define ATA_SET_MAX_LOCK 0x02 ///< defined from ATA-6
+#define ATA_SET_MAX_UNLOCK 0x03 ///< defined from ATA-6
+#define ATA_SET_MAX_FREEZE_LOCK 0x04 ///< defined from ATA-6
///
/// Default content of device control register, disable INT,
/// Bit3 is set to 1 according ATA-1
///
-#define ATA_DEFAULT_CTL (0x0a)
+#define ATA_DEFAULT_CTL (0x0a)
///
/// Default context of Device/Head Register,
/// Bit7 and Bit5 are set to 1 for back-compatibilities.
///
-#define ATA_DEFAULT_CMD (0xa0)
+#define ATA_DEFAULT_CMD (0xa0)
-#define ATAPI_MAX_BYTE_COUNT (0xfffe)
+#define ATAPI_MAX_BYTE_COUNT (0xfffe)
-#define ATA_REQUEST_SENSE_ERROR (0x70) ///< defined in SFF-8070i
+#define ATA_REQUEST_SENSE_ERROR (0x70) ///< defined in SFF-8070i
//
// Sense Key, Additional Sense Codes and Additional Sense Code Qualifier
@@ -776,76 +774,76 @@ typedef union {
//
// Sense Key
//
-#define ATA_SK_NO_SENSE (0x0)
-#define ATA_SK_RECOVERY_ERROR (0x1)
-#define ATA_SK_NOT_READY (0x2)
-#define ATA_SK_MEDIUM_ERROR (0x3)
-#define ATA_SK_HARDWARE_ERROR (0x4)
-#define ATA_SK_ILLEGAL_REQUEST (0x5)
-#define ATA_SK_UNIT_ATTENTION (0x6)
-#define ATA_SK_DATA_PROTECT (0x7)
-#define ATA_SK_BLANK_CHECK (0x8)
-#define ATA_SK_VENDOR_SPECIFIC (0x9)
-#define ATA_SK_RESERVED_A (0xA)
-#define ATA_SK_ABORT (0xB)
-#define ATA_SK_RESERVED_C (0xC)
-#define ATA_SK_OVERFLOW (0xD)
-#define ATA_SK_MISCOMPARE (0xE)
-#define ATA_SK_RESERVED_F (0xF)
+#define ATA_SK_NO_SENSE (0x0)
+#define ATA_SK_RECOVERY_ERROR (0x1)
+#define ATA_SK_NOT_READY (0x2)
+#define ATA_SK_MEDIUM_ERROR (0x3)
+#define ATA_SK_HARDWARE_ERROR (0x4)
+#define ATA_SK_ILLEGAL_REQUEST (0x5)
+#define ATA_SK_UNIT_ATTENTION (0x6)
+#define ATA_SK_DATA_PROTECT (0x7)
+#define ATA_SK_BLANK_CHECK (0x8)
+#define ATA_SK_VENDOR_SPECIFIC (0x9)
+#define ATA_SK_RESERVED_A (0xA)
+#define ATA_SK_ABORT (0xB)
+#define ATA_SK_RESERVED_C (0xC)
+#define ATA_SK_OVERFLOW (0xD)
+#define ATA_SK_MISCOMPARE (0xE)
+#define ATA_SK_RESERVED_F (0xF)
//
// Additional Sense Codes
//
-#define ATA_ASC_NOT_READY (0x04)
-#define ATA_ASC_MEDIA_ERR1 (0x10)
-#define ATA_ASC_MEDIA_ERR2 (0x11)
-#define ATA_ASC_MEDIA_ERR3 (0x14)
-#define ATA_ASC_MEDIA_ERR4 (0x30)
-#define ATA_ASC_MEDIA_UPSIDE_DOWN (0x06)
-#define ATA_ASC_INVALID_CMD (0x20)
-#define ATA_ASC_LBA_OUT_OF_RANGE (0x21)
-#define ATA_ASC_INVALID_FIELD (0x24)
-#define ATA_ASC_WRITE_PROTECTED (0x27)
-#define ATA_ASC_MEDIA_CHANGE (0x28)
-#define ATA_ASC_RESET (0x29) ///< Power On Reset or Bus Reset occurred.
-#define ATA_ASC_ILLEGAL_FIELD (0x26)
-#define ATA_ASC_NO_MEDIA (0x3A)
-#define ATA_ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
+#define ATA_ASC_NOT_READY (0x04)
+#define ATA_ASC_MEDIA_ERR1 (0x10)
+#define ATA_ASC_MEDIA_ERR2 (0x11)
+#define ATA_ASC_MEDIA_ERR3 (0x14)
+#define ATA_ASC_MEDIA_ERR4 (0x30)
+#define ATA_ASC_MEDIA_UPSIDE_DOWN (0x06)
+#define ATA_ASC_INVALID_CMD (0x20)
+#define ATA_ASC_LBA_OUT_OF_RANGE (0x21)
+#define ATA_ASC_INVALID_FIELD (0x24)
+#define ATA_ASC_WRITE_PROTECTED (0x27)
+#define ATA_ASC_MEDIA_CHANGE (0x28)
+#define ATA_ASC_RESET (0x29) ///< Power On Reset or Bus Reset occurred.
+#define ATA_ASC_ILLEGAL_FIELD (0x26)
+#define ATA_ASC_NO_MEDIA (0x3A)
+#define ATA_ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
//
// Additional Sense Code Qualifier
//
-#define ATA_ASCQ_IN_PROGRESS (0x01)
+#define ATA_ASCQ_IN_PROGRESS (0x01)
//
// Error Register
//
-#define ATA_ERRREG_BBK BIT7 ///< Bad block detected defined from ATA-1, obsoleted from ATA-2
-#define ATA_ERRREG_UNC BIT6 ///< Uncorrectable Data defined from ATA-1, obsoleted from ATA-4
-#define ATA_ERRREG_MC BIT5 ///< Media Change defined from ATA-1, obsoleted from ATA-4
-#define ATA_ERRREG_IDNF BIT4 ///< ID Not Found defined from ATA-1, obsoleted from ATA-4
-#define ATA_ERRREG_MCR BIT3 ///< Media Change Requested defined from ATA-1, obsoleted from ATA-4
-#define ATA_ERRREG_ABRT BIT2 ///< Aborted Command defined from ATA-1
-#define ATA_ERRREG_TK0NF BIT1 ///< Track 0 Not Found defined from ATA-1, obsoleted from ATA-4
-#define ATA_ERRREG_AMNF BIT0 ///< Address Mark Not Found defined from ATA-1, obsoleted from ATA-4
+#define ATA_ERRREG_BBK BIT7 ///< Bad block detected defined from ATA-1, obsoleted from ATA-2
+#define ATA_ERRREG_UNC BIT6 ///< Uncorrectable Data defined from ATA-1, obsoleted from ATA-4
+#define ATA_ERRREG_MC BIT5 ///< Media Change defined from ATA-1, obsoleted from ATA-4
+#define ATA_ERRREG_IDNF BIT4 ///< ID Not Found defined from ATA-1, obsoleted from ATA-4
+#define ATA_ERRREG_MCR BIT3 ///< Media Change Requested defined from ATA-1, obsoleted from ATA-4
+#define ATA_ERRREG_ABRT BIT2 ///< Aborted Command defined from ATA-1
+#define ATA_ERRREG_TK0NF BIT1 ///< Track 0 Not Found defined from ATA-1, obsoleted from ATA-4
+#define ATA_ERRREG_AMNF BIT0 ///< Address Mark Not Found defined from ATA-1, obsoleted from ATA-4
//
// Status Register
//
-#define ATA_STSREG_BSY BIT7 ///< Controller Busy defined from ATA-1
-#define ATA_STSREG_DRDY BIT6 ///< Drive Ready defined from ATA-1
-#define ATA_STSREG_DWF BIT5 ///< Drive Write Fault defined from ATA-1, obsoleted from ATA-4
-#define ATA_STSREG_DF BIT5 ///< Drive Fault defined from ATA-6
-#define ATA_STSREG_DSC BIT4 ///< Disk Seek Complete defined from ATA-1, obsoleted from ATA-4
-#define ATA_STSREG_DRQ BIT3 ///< Data Request defined from ATA-1
-#define ATA_STSREG_CORR BIT2 ///< Corrected Data defined from ATA-1, obsoleted from ATA-4
-#define ATA_STSREG_IDX BIT1 ///< Index defined from ATA-1, obsoleted from ATA-4
-#define ATA_STSREG_ERR BIT0 ///< Error defined from ATA-1
+#define ATA_STSREG_BSY BIT7 ///< Controller Busy defined from ATA-1
+#define ATA_STSREG_DRDY BIT6 ///< Drive Ready defined from ATA-1
+#define ATA_STSREG_DWF BIT5 ///< Drive Write Fault defined from ATA-1, obsoleted from ATA-4
+#define ATA_STSREG_DF BIT5 ///< Drive Fault defined from ATA-6
+#define ATA_STSREG_DSC BIT4 ///< Disk Seek Complete defined from ATA-1, obsoleted from ATA-4
+#define ATA_STSREG_DRQ BIT3 ///< Data Request defined from ATA-1
+#define ATA_STSREG_CORR BIT2 ///< Corrected Data defined from ATA-1, obsoleted from ATA-4
+#define ATA_STSREG_IDX BIT1 ///< Index defined from ATA-1, obsoleted from ATA-4
+#define ATA_STSREG_ERR BIT0 ///< Error defined from ATA-1
//
// Device Control Register
//
-#define ATA_CTLREG_SRST BIT2 ///< Software Reset.
-#define ATA_CTLREG_IEN_L BIT1 ///< Interrupt Enable #.
+#define ATA_CTLREG_SRST BIT2 ///< Software Reset.
+#define ATA_CTLREG_IEN_L BIT1 ///< Interrupt Enable #.
#endif
diff --git a/MdePkg/Include/IndustryStandard/Bluetooth.h b/MdePkg/Include/IndustryStandard/Bluetooth.h
index 96940129..c22dbff9 100644
--- a/MdePkg/Include/IndustryStandard/Bluetooth.h
+++ b/MdePkg/Include/IndustryStandard/Bluetooth.h
@@ -19,17 +19,17 @@ typedef struct {
///
/// 48bit Bluetooth device address.
///
- UINT8 Address[6];
+ UINT8 Address[6];
} BLUETOOTH_ADDRESS;
///
/// BLUETOOTH_CLASS_OF_DEVICE. See Bluetooth specification for detail.
///
typedef struct {
- UINT8 FormatType:2;
- UINT8 MinorDeviceClass: 6;
- UINT16 MajorDeviceClass: 5;
- UINT16 MajorServiceClass:11;
+ UINT8 FormatType : 2;
+ UINT8 MinorDeviceClass : 6;
+ UINT16 MajorDeviceClass : 5;
+ UINT16 MajorServiceClass : 11;
} BLUETOOTH_CLASS_OF_DEVICE;
///
@@ -39,18 +39,18 @@ typedef struct {
///
/// 48-bit Bluetooth device address
///
- UINT8 Address[6];
+ UINT8 Address[6];
///
/// 0x00 - Public Device Address
/// 0x01 - Random Device Address
///
- UINT8 Type;
+ UINT8 Type;
} BLUETOOTH_LE_ADDRESS;
#pragma pack()
-#define BLUETOOTH_HCI_COMMAND_LOCAL_READABLE_NAME_MAX_SIZE 248
+#define BLUETOOTH_HCI_COMMAND_LOCAL_READABLE_NAME_MAX_SIZE 248
-#define BLUETOOTH_HCI_LINK_KEY_SIZE 16
+#define BLUETOOTH_HCI_LINK_KEY_SIZE 16
#endif
diff --git a/MdePkg/Include/IndustryStandard/Bmp.h b/MdePkg/Include/IndustryStandard/Bmp.h
index 36f71940..5d66483d 100644
--- a/MdePkg/Include/IndustryStandard/Bmp.h
+++ b/MdePkg/Include/IndustryStandard/Bmp.h
@@ -12,29 +12,29 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#pragma pack(1)
typedef struct {
- UINT8 Blue;
- UINT8 Green;
- UINT8 Red;
- UINT8 Reserved;
+ UINT8 Blue;
+ UINT8 Green;
+ UINT8 Red;
+ UINT8 Reserved;
} BMP_COLOR_MAP;
typedef struct {
- CHAR8 CharB;
- CHAR8 CharM;
- UINT32 Size;
- UINT16 Reserved[2];
- UINT32 ImageOffset;
- UINT32 HeaderSize;
- UINT32 PixelWidth;
- UINT32 PixelHeight;
- UINT16 Planes; ///< Must be 1
- UINT16 BitPerPixel; ///< 1, 4, 8, or 24
- UINT32 CompressionType;
- UINT32 ImageSize; ///< Compressed image size in bytes
- UINT32 XPixelsPerMeter;
- UINT32 YPixelsPerMeter;
- UINT32 NumberOfColors;
- UINT32 ImportantColors;
+ CHAR8 CharB;
+ CHAR8 CharM;
+ UINT32 Size;
+ UINT16 Reserved[2];
+ UINT32 ImageOffset;
+ UINT32 HeaderSize;
+ UINT32 PixelWidth;
+ UINT32 PixelHeight;
+ UINT16 Planes; ///< Must be 1
+ UINT16 BitPerPixel; ///< 1, 4, 8, or 24
+ UINT32 CompressionType;
+ UINT32 ImageSize; ///< Compressed image size in bytes
+ UINT32 XPixelsPerMeter;
+ UINT32 YPixelsPerMeter;
+ UINT32 NumberOfColors;
+ UINT32 ImportantColors;
} BMP_IMAGE_HEADER;
#pragma pack()
diff --git a/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h b/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h
index a36df39b..8a04bfae 100644
--- a/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h
+++ b/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h
@@ -2,18 +2,19 @@
DMA Remapping Reporting (DMAR) ACPI table definition from Intel(R)
Virtualization Technology for Directed I/O (VT-D) Architecture Specification.
- Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
- Intel(R) Virtualization Technology for Directed I/O (VT-D) Architecture
- Specification v3.2, Dated October 2020.
+ Specification v4.0, Dated June 2022.
https://software.intel.com/content/dam/develop/external/us/en/documents/vt-directed-io-spec.pdf
@par Glossary:
- HPET - High Precision Event Timer
- NUMA - Non-uniform Memory Access
**/
+
#ifndef _DMA_REMAPPING_REPORTING_TABLE_H_
#define _DMA_REMAPPING_REPORTING_TABLE_H_
@@ -24,7 +25,7 @@
///
/// DMA-Remapping Reporting Structure definitions from section 8.1
///@{
-#define EFI_ACPI_DMAR_REVISION 0x01
+#define EFI_ACPI_DMAR_REVISION 0x01
#define EFI_ACPI_DMAR_FLAGS_INTR_REMAP BIT0
#define EFI_ACPI_DMAR_FLAGS_X2APIC_OPT_OUT BIT1
@@ -34,12 +35,13 @@
///
/// Remapping Structure Types definitions from section 8.2
///@{
-#define EFI_ACPI_DMAR_TYPE_DRHD 0x00
-#define EFI_ACPI_DMAR_TYPE_RMRR 0x01
-#define EFI_ACPI_DMAR_TYPE_ATSR 0x02
-#define EFI_ACPI_DMAR_TYPE_RHSA 0x03
-#define EFI_ACPI_DMAR_TYPE_ANDD 0x04
-#define EFI_ACPI_DMAR_TYPE_SATC 0x05
+#define EFI_ACPI_DMAR_TYPE_DRHD 0x00
+#define EFI_ACPI_DMAR_TYPE_RMRR 0x01
+#define EFI_ACPI_DMAR_TYPE_ATSR 0x02
+#define EFI_ACPI_DMAR_TYPE_RHSA 0x03
+#define EFI_ACPI_DMAR_TYPE_ANDD 0x04
+#define EFI_ACPI_DMAR_TYPE_SATC 0x05
+#define EFI_ACPI_DMAR_TYPE_SIDP 0x06
///@}
///
@@ -55,38 +57,45 @@
#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_IOAPIC 0x03
#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_MSI_CAPABLE_HPET 0x04
#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_ACPI_NAMESPACE_DEVICE 0x05
+
+#define EFI_ACPI_DEVICE_SCOPE_REQ_WO_PASID_NESTED_NOTALLOWED BIT0
+#define EFI_ACPI_DEVICE_SCOPE_REQ_WO_PASID_PWSNP_NOTALLOWED BIT1
+#define EFI_ACPI_DEVICE_SCOPE_REQ_WO_PASID_PGSNP_NOTALLOWED BIT2
+#define EFI_ACPI_DEVICE_SCOPE_REQ_WO_PASID_ATC_HARDENED BIT3
+#define EFI_ACPI_DEVICE_SCOPE_REQ_WO_PASID_ATC_REQUIRED BIT4
///@}
///
/// Root Port ATS Capability Reporting Structure definitions from section 8.5
///
-#define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS BIT0
+#define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS BIT0
///
/// Definition for DMA Remapping Structure Header
///
typedef struct {
- UINT16 Type;
- UINT16 Length;
+ UINT16 Type;
+ UINT16 Length;
} EFI_ACPI_DMAR_STRUCTURE_HEADER;
///
/// Definition for DMA-Remapping PCI Path
///
typedef struct {
- UINT8 Device;
- UINT8 Function;
+ UINT8 Device;
+ UINT8 Function;
} EFI_ACPI_DMAR_PCI_PATH;
///
/// Device Scope Structure is defined in section 8.3.1
///
typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Reserved2;
- UINT8 EnumerationId;
- UINT8 StartBusNumber;
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Flags;
+ UINT8 Reserved;
+ UINT8 EnumerationId;
+ UINT8 StartBusNumber;
} EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER;
/**
@@ -96,7 +105,8 @@ typedef struct {
for each PCI segment in the platform.
**/
typedef struct {
- EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
+
/**
- Bit[0]: INCLUDE_PCI_ALL
- If Set, this remapping hardware unit has under its scope all
@@ -108,16 +118,23 @@ typedef struct {
through the DeviceScope field.
- Bits[7:1] Reserved.
**/
- UINT8 Flags;
- UINT8 Reserved;
+ UINT8 Flags;
+
+ /**
+ - Bits[3:0]: Indicates the size of the remapping hardware register set for
+ this remapping unit. If the value in this field is N, the size
+ of the register set is 2^N 4 KB pages
+ - Bits[7:4]: Reserved.
+ **/
+ UINT8 Size;
///
/// The PCI Segment associated with this unit.
///
- UINT16 SegmentNumber;
+ UINT16 SegmentNumber;
///
/// Base address of remapping hardware register-set for this unit.
///
- UINT64 RegisterBaseAddress;
+ UINT64 RegisterBaseAddress;
} EFI_ACPI_DMAR_DRHD_HEADER;
/**
@@ -127,24 +144,25 @@ typedef struct {
reserved memory region.
**/
typedef struct {
- EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
- UINT8 Reserved[2];
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
+ UINT8 Reserved[2];
///
/// PCI Segment Number associated with devices identified through
/// the Device Scope field.
///
- UINT16 SegmentNumber;
+ UINT16 SegmentNumber;
///
/// Base address of 4KB-aligned reserved memory region
///
- UINT64 ReservedMemoryRegionBaseAddress;
+ UINT64 ReservedMemoryRegionBaseAddress;
+
/**
Last address of the reserved memory region. Value in this field must be
greater than the value in Reserved Memory Region Base Address field.
The reserved memory region size (Limit - Base + 1) must be an integer
multiple of 4KB.
**/
- UINT64 ReservedMemoryRegionLimitAddress;
+ UINT64 ReservedMemoryRegionLimitAddress;
} EFI_ACPI_DMAR_RMRR_HEADER;
/**
@@ -158,7 +176,8 @@ typedef struct {
ATS transactions.
**/
typedef struct {
- EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
+
/**
- Bit[0]: ALL_PORTS:
- If Set, indicates all PCI Express Root Ports in the specified
@@ -167,12 +186,12 @@ typedef struct {
Root Ports identified through the Device Scope field.
- Bits[7:1] Reserved.
**/
- UINT8 Flags;
- UINT8 Reserved;
+ UINT8 Flags;
+ UINT8 Reserved;
///
/// The PCI Segment associated with this ATSR structure
///
- UINT16 SegmentNumber;
+ UINT16 SegmentNumber;
} EFI_ACPI_DMAR_ATSR_HEADER;
/**
@@ -183,18 +202,18 @@ typedef struct {
reported through DRHD structure.
**/
typedef struct {
- EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
- UINT8 Reserved[4];
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
+ UINT8 Reserved[4];
///
/// Register Base Address of this Remap hardware unit reported in the
/// corresponding DRHD structure.
///
- UINT64 RegisterBaseAddress;
+ UINT64 RegisterBaseAddress;
///
/// Proximity Domain to which the Remap hardware unit identified by the
/// Register Base Address field belongs.
///
- UINT32 ProximityDomain;
+ UINT32 ProximityDomain;
} EFI_ACPI_DMAR_RHSA_HEADER;
/**
@@ -204,8 +223,9 @@ typedef struct {
with Device-Scope entries of type ACPI_NAMESPACE_DEVICE.
**/
typedef struct {
- EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
- UINT8 Reserved[3];
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
+ UINT8 Reserved[3];
+
/**
Each ACPI device enumerated through an ANDD structure must have a unique
value for this field. To report an ACPI device with ACPI Device Number
@@ -214,7 +234,7 @@ typedef struct {
The Start Bus Number and Path fields in the Device-Scope together
provides the 16-bit source-id allocated by platform for the ACPI device.
**/
- UINT8 AcpiDeviceNumber;
+ UINT8 AcpiDeviceNumber;
} EFI_ACPI_DMAR_ANDD_HEADER;
/**
@@ -222,7 +242,8 @@ typedef struct {
defined in section 8.8.
**/
typedef struct {
- EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
+
/**
- Bit[0]: ATC_REQUIRED:
- If Set, indicates that every SoC integrated device enumerated
@@ -233,16 +254,30 @@ typedef struct {
performance or functionality).
- Bits[7:1] Reserved.
**/
- UINT8 Flags;
- UINT8 Reserved;
+ UINT8 Flags;
+ UINT8 Reserved;
///
/// The PCI Segment associated with this SATC structure. All SoC integrated
/// devices within a PCI segment with same value for Flags field must be
/// enumerated in the same SATC structure.
///
- UINT16 SegmentNumber;
+ UINT16 SegmentNumber;
} EFI_ACPI_DMAR_SATC_HEADER;
+/**
+ SoC Integrated Device Property (SIDP) Reporting Structure is defined in
+ section 8.9.
+**/
+typedef struct {
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
+
+ UINT16 Reserved;
+ ///
+ /// The PCI Segment associated with this SIDP structure.
+ ///
+ UINT16 SegmentNumber;
+} EFI_ACPI_DMAR_SIDP_HEADER;
+
/**
DMA Remapping Reporting Structure Header as defined in section 8.1
This header will be followed by list of Remapping Structures listed below
@@ -252,12 +287,14 @@ typedef struct {
- Remapping Hardware Static Affinity (RHSA)
- ACPI Name-space Device Declaration (ANDD)
- SoC Integrated Address Translation Cache reporting (SATC)
+ - SoC Integrated Device Property reporting (SIDP)
These structure types must by reported in numerical order.
i.e., All remapping structures of type 0 (DRHD) enumerated before remapping
structures of type 1 (RMRR), and so forth.
**/
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+
/**
This field indicates the maximum DMA physical addressability supported by
this platform. The system address map reported by the BIOS indicates what
@@ -267,7 +304,8 @@ typedef struct {
For example, for a platform supporting 40 bits of physical addressability,
the value of 100111b is reported in this field.
**/
- UINT8 HostAddressWidth;
+ UINT8 HostAddressWidth;
+
/**
- Bit[0]: INTR_REMAP - If Clear, the platform does not support interrupt
remapping. If Set, the platform supports interrupt remapping.
@@ -282,8 +320,8 @@ typedef struct {
such as on ExitBootServices().
- Bits[7:3] Reserved.
**/
- UINT8 Flags;
- UINT8 Reserved[10];
+ UINT8 Flags;
+ UINT8 Reserved[10];
} EFI_ACPI_DMAR_HEADER;
#pragma pack()
diff --git a/MdePkg/Include/IndustryStandard/ElTorito.h b/MdePkg/Include/IndustryStandard/ElTorito.h
index e9b870f7..b6a8b1a5 100644
--- a/MdePkg/Include/IndustryStandard/ElTorito.h
+++ b/MdePkg/Include/IndustryStandard/ElTorito.h
@@ -16,9 +16,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// CDROM_VOLUME_DESCRIPTOR.Types, defined in ISO 9660
//
-#define CDVOL_TYPE_STANDARD 0x0
-#define CDVOL_TYPE_CODED 0x1
-#define CDVOL_TYPE_END 0xFF
+#define CDVOL_TYPE_STANDARD 0x0
+#define CDVOL_TYPE_CODED 0x1
+#define CDVOL_TYPE_END 0xFF
///
/// CDROM_VOLUME_DESCRIPTOR.Id
@@ -28,7 +28,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
///
/// CDROM_VOLUME_DESCRIPTOR.SystemId
///
-#define CDVOL_ELTORITO_ID "EL TORITO SPECIFICATION"
+#define CDVOL_ELTORITO_ID "EL TORITO SPECIFICATION"
//
// Indicator types
@@ -42,12 +42,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// ELTORITO_CATALOG.Boot.MediaTypes
//
-#define ELTORITO_NO_EMULATION 0x00
-#define ELTORITO_12_DISKETTE 0x01
-#define ELTORITO_14_DISKETTE 0x02
-#define ELTORITO_28_DISKETTE 0x03
-#define ELTORITO_HARD_DISK 0x04
-
+#define ELTORITO_NO_EMULATION 0x00
+#define ELTORITO_12_DISKETTE 0x01
+#define ELTORITO_14_DISKETTE 0x02
+#define ELTORITO_28_DISKETTE 0x03
+#define ELTORITO_HARD_DISK 0x04
#pragma pack(1)
@@ -56,38 +55,37 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
///
typedef union {
struct {
- UINT8 Type;
- CHAR8 Id[5]; ///< "CD001"
- CHAR8 Reserved[82];
+ UINT8 Type;
+ CHAR8 Id[5]; ///< "CD001"
+ CHAR8 Reserved[82];
} Unknown;
///
/// Boot Record Volume Descriptor, defined in "El Torito" Specification.
///
struct {
- UINT8 Type; ///< Must be 0
- CHAR8 Id[5]; ///< "CD001"
- UINT8 Version; ///< Must be 1
- CHAR8 SystemId[32]; ///< "EL TORITO SPECIFICATION"
- CHAR8 Unused[32]; ///< Must be 0
- UINT8 EltCatalog[4]; ///< Absolute pointer to first sector of Boot Catalog
- CHAR8 Unused2[13]; ///< Must be 0
+ UINT8 Type; ///< Must be 0
+ CHAR8 Id[5]; ///< "CD001"
+ UINT8 Version; ///< Must be 1
+ CHAR8 SystemId[32]; ///< "EL TORITO SPECIFICATION"
+ CHAR8 Unused[32]; ///< Must be 0
+ UINT8 EltCatalog[4]; ///< Absolute pointer to first sector of Boot Catalog
+ CHAR8 Unused2[13]; ///< Must be 0
} BootRecordVolume;
///
/// Primary Volume Descriptor, defined in ISO 9660.
///
struct {
- UINT8 Type;
- CHAR8 Id[5]; ///< "CD001"
- UINT8 Version;
- UINT8 Unused; ///< Must be 0
- CHAR8 SystemId[32];
- CHAR8 VolumeId[32];
- UINT8 Unused2[8]; ///< Must be 0
- UINT32 VolSpaceSize[2]; ///< the number of Logical Blocks
+ UINT8 Type;
+ CHAR8 Id[5]; ///< "CD001"
+ UINT8 Version;
+ UINT8 Unused; ///< Must be 0
+ CHAR8 SystemId[32];
+ CHAR8 VolumeId[32];
+ UINT8 Unused2[8]; ///< Must be 0
+ UINT32 VolSpaceSize[2]; ///< the number of Logical Blocks
} PrimaryVolume;
-
} CDROM_VOLUME_DESCRIPTOR;
///
@@ -95,45 +93,44 @@ typedef union {
///
typedef union {
struct {
- CHAR8 Reserved[0x20];
+ CHAR8 Reserved[0x20];
} Unknown;
///
/// Catalog validation entry (Catalog header)
///
struct {
- UINT8 Indicator; ///< Must be 01
- UINT8 PlatformId;
- UINT16 Reserved;
- CHAR8 ManufacId[24];
- UINT16 Checksum;
- UINT16 Id55AA;
+ UINT8 Indicator; ///< Must be 01
+ UINT8 PlatformId;
+ UINT16 Reserved;
+ CHAR8 ManufacId[24];
+ UINT16 Checksum;
+ UINT16 Id55AA;
} Catalog;
///
/// Initial/Default Entry or Section Entry
///
struct {
- UINT8 Indicator; ///< 88 = Bootable, 00 = Not Bootable
- UINT8 MediaType : 4;
- UINT8 Reserved1 : 4; ///< Must be 0
- UINT16 LoadSegment;
- UINT8 SystemType;
- UINT8 Reserved2; ///< Must be 0
- UINT16 SectorCount;
- UINT32 Lba;
+ UINT8 Indicator; ///< 88 = Bootable, 00 = Not Bootable
+ UINT8 MediaType : 4;
+ UINT8 Reserved1 : 4; ///< Must be 0
+ UINT16 LoadSegment;
+ UINT8 SystemType;
+ UINT8 Reserved2; ///< Must be 0
+ UINT16 SectorCount;
+ UINT32 Lba;
} Boot;
///
/// Section Header Entry
///
struct {
- UINT8 Indicator; ///< 90 - Header, more header follw, 91 - Final Header
- UINT8 PlatformId;
- UINT16 SectionEntries; ///< Number of section entries following this header
- CHAR8 Id[28];
+ UINT8 Indicator; ///< 90 - Header, more header follw, 91 - Final Header
+ UINT8 PlatformId;
+ UINT16 SectionEntries; ///< Number of section entries following this header
+ CHAR8 Id[28];
} Section;
-
} ELTORITO_CATALOG;
#pragma pack()
diff --git a/MdePkg/Include/IndustryStandard/Emmc.h b/MdePkg/Include/IndustryStandard/Emmc.h
index 0987f6c4..a2ff5b73 100644
--- a/MdePkg/Include/IndustryStandard/Emmc.h
+++ b/MdePkg/Include/IndustryStandard/Emmc.h
@@ -14,276 +14,276 @@
//
// EMMC command index
//
-#define EMMC_GO_IDLE_STATE 0
-#define EMMC_SEND_OP_COND 1
-#define EMMC_ALL_SEND_CID 2
-#define EMMC_SET_RELATIVE_ADDR 3
-#define EMMC_SET_DSR 4
-#define EMMC_SLEEP_AWAKE 5
-#define EMMC_SWITCH 6
-#define EMMC_SELECT_DESELECT_CARD 7
-#define EMMC_SEND_EXT_CSD 8
-#define EMMC_SEND_CSD 9
-#define EMMC_SEND_CID 10
-#define EMMC_STOP_TRANSMISSION 12
-#define EMMC_SEND_STATUS 13
-#define EMMC_BUSTEST_R 14
-#define EMMC_GO_INACTIVE_STATE 15
-#define EMMC_SET_BLOCKLEN 16
-#define EMMC_READ_SINGLE_BLOCK 17
-#define EMMC_READ_MULTIPLE_BLOCK 18
-#define EMMC_BUSTEST_W 19
-#define EMMC_SEND_TUNING_BLOCK 21
-#define EMMC_SET_BLOCK_COUNT 23
-#define EMMC_WRITE_BLOCK 24
-#define EMMC_WRITE_MULTIPLE_BLOCK 25
-#define EMMC_PROGRAM_CID 26
-#define EMMC_PROGRAM_CSD 27
-#define EMMC_SET_WRITE_PROT 28
-#define EMMC_CLR_WRITE_PROT 29
-#define EMMC_SEND_WRITE_PROT 30
-#define EMMC_SEND_WRITE_PROT_TYPE 31
-#define EMMC_ERASE_GROUP_START 35
-#define EMMC_ERASE_GROUP_END 36
-#define EMMC_ERASE 38
-#define EMMC_FAST_IO 39
-#define EMMC_GO_IRQ_STATE 40
-#define EMMC_LOCK_UNLOCK 42
-#define EMMC_SET_TIME 49
-#define EMMC_PROTOCOL_RD 53
-#define EMMC_PROTOCOL_WR 54
-#define EMMC_APP_CMD 55
-#define EMMC_GEN_CMD 56
+#define EMMC_GO_IDLE_STATE 0
+#define EMMC_SEND_OP_COND 1
+#define EMMC_ALL_SEND_CID 2
+#define EMMC_SET_RELATIVE_ADDR 3
+#define EMMC_SET_DSR 4
+#define EMMC_SLEEP_AWAKE 5
+#define EMMC_SWITCH 6
+#define EMMC_SELECT_DESELECT_CARD 7
+#define EMMC_SEND_EXT_CSD 8
+#define EMMC_SEND_CSD 9
+#define EMMC_SEND_CID 10
+#define EMMC_STOP_TRANSMISSION 12
+#define EMMC_SEND_STATUS 13
+#define EMMC_BUSTEST_R 14
+#define EMMC_GO_INACTIVE_STATE 15
+#define EMMC_SET_BLOCKLEN 16
+#define EMMC_READ_SINGLE_BLOCK 17
+#define EMMC_READ_MULTIPLE_BLOCK 18
+#define EMMC_BUSTEST_W 19
+#define EMMC_SEND_TUNING_BLOCK 21
+#define EMMC_SET_BLOCK_COUNT 23
+#define EMMC_WRITE_BLOCK 24
+#define EMMC_WRITE_MULTIPLE_BLOCK 25
+#define EMMC_PROGRAM_CID 26
+#define EMMC_PROGRAM_CSD 27
+#define EMMC_SET_WRITE_PROT 28
+#define EMMC_CLR_WRITE_PROT 29
+#define EMMC_SEND_WRITE_PROT 30
+#define EMMC_SEND_WRITE_PROT_TYPE 31
+#define EMMC_ERASE_GROUP_START 35
+#define EMMC_ERASE_GROUP_END 36
+#define EMMC_ERASE 38
+#define EMMC_FAST_IO 39
+#define EMMC_GO_IRQ_STATE 40
+#define EMMC_LOCK_UNLOCK 42
+#define EMMC_SET_TIME 49
+#define EMMC_PROTOCOL_RD 53
+#define EMMC_PROTOCOL_WR 54
+#define EMMC_APP_CMD 55
+#define EMMC_GEN_CMD 56
typedef enum {
- EmmcPartitionUserData = 0,
- EmmcPartitionBoot1 = 1,
- EmmcPartitionBoot2 = 2,
- EmmcPartitionRPMB = 3,
- EmmcPartitionGP1 = 4,
- EmmcPartitionGP2 = 5,
- EmmcPartitionGP3 = 6,
- EmmcPartitionGP4 = 7,
+ EmmcPartitionUserData = 0,
+ EmmcPartitionBoot1 = 1,
+ EmmcPartitionBoot2 = 2,
+ EmmcPartitionRPMB = 3,
+ EmmcPartitionGP1 = 4,
+ EmmcPartitionGP2 = 5,
+ EmmcPartitionGP3 = 6,
+ EmmcPartitionGP4 = 7,
EmmcPartitionUnknown
} EMMC_PARTITION_TYPE;
#pragma pack(1)
typedef struct {
- UINT8 NotUsed:1; // Not used [0:0]
- UINT8 Crc:7; // CRC [7:1]
- UINT8 ManufacturingDate; // Manufacturing date [15:8]
- UINT8 ProductSerialNumber[4]; // Product serial number [47:16]
- UINT8 ProductRevision; // Product revision [55:48]
- UINT8 ProductName[6]; // Product name [103:56]
- UINT8 OemId; // OEM/Application ID [111:104]
- UINT8 DeviceType:2; // Device/BGA [113:112]
- UINT8 Reserved:6; // Reserved [119:114]
- UINT8 ManufacturerId; // Manufacturer ID [127:120]
+ UINT8 NotUsed : 1; // Not used [0:0]
+ UINT8 Crc : 7; // CRC [7:1]
+ UINT8 ManufacturingDate; // Manufacturing date [15:8]
+ UINT8 ProductSerialNumber[4]; // Product serial number [47:16]
+ UINT8 ProductRevision; // Product revision [55:48]
+ UINT8 ProductName[6]; // Product name [103:56]
+ UINT8 OemId; // OEM/Application ID [111:104]
+ UINT8 DeviceType : 2; // Device/BGA [113:112]
+ UINT8 Reserved : 6; // Reserved [119:114]
+ UINT8 ManufacturerId; // Manufacturer ID [127:120]
} EMMC_CID;
typedef struct {
- UINT32 NotUsed:1; // Not used [0:0]
- UINT32 Crc:7; // CRC [7:1]
- UINT32 Ecc:2; // ECC code [9:8]
- UINT32 FileFormat:2; // File format [11:10]
- UINT32 TmpWriteProtect:1; // Temporary write protection [12:12]
- UINT32 PermWriteProtect:1; // Permanent write protection [13:13]
- UINT32 Copy:1; // Copy flag (OTP) [14:14]
- UINT32 FileFormatGrp:1; // File format group [15:15]
- UINT32 ContentProtApp:1; // Content protection application [16:16]
- UINT32 Reserved:4; // Reserved [20:17]
- UINT32 WriteBlPartial:1; // Partial blocks for write allowed [21:21]
- UINT32 WriteBlLen:4; // Max. write data block length [25:22]
- UINT32 R2WFactor:3; // Write speed factor [28:26]
- UINT32 DefaultEcc:2; // Manufacturer default ECC [30:29]
- UINT32 WpGrpEnable:1; // Write protect group enable [31:31]
+ UINT32 NotUsed : 1; // Not used [0:0]
+ UINT32 Crc : 7; // CRC [7:1]
+ UINT32 Ecc : 2; // ECC code [9:8]
+ UINT32 FileFormat : 2; // File format [11:10]
+ UINT32 TmpWriteProtect : 1; // Temporary write protection [12:12]
+ UINT32 PermWriteProtect : 1; // Permanent write protection [13:13]
+ UINT32 Copy : 1; // Copy flag (OTP) [14:14]
+ UINT32 FileFormatGrp : 1; // File format group [15:15]
+ UINT32 ContentProtApp : 1; // Content protection application [16:16]
+ UINT32 Reserved : 4; // Reserved [20:17]
+ UINT32 WriteBlPartial : 1; // Partial blocks for write allowed [21:21]
+ UINT32 WriteBlLen : 4; // Max. write data block length [25:22]
+ UINT32 R2WFactor : 3; // Write speed factor [28:26]
+ UINT32 DefaultEcc : 2; // Manufacturer default ECC [30:29]
+ UINT32 WpGrpEnable : 1; // Write protect group enable [31:31]
- UINT32 WpGrpSize:5; // Write protect group size [36:32]
- UINT32 EraseGrpMult:5; // Erase group size multiplier [41:37]
- UINT32 EraseGrpSize:5; // Erase group size [46:42]
- UINT32 CSizeMult:3; // Device size multiplier [49:47]
- UINT32 VddWCurrMax:3; // Max. write current @ VDD max [52:50]
- UINT32 VddWCurrMin:3; // Max. write current @ VDD min [55:53]
- UINT32 VddRCurrMax:3; // Max. read current @ VDD max [58:56]
- UINT32 VddRCurrMin:3; // Max. read current @ VDD min [61:59]
- UINT32 CSizeLow:2; // Device size low two bits [63:62]
+ UINT32 WpGrpSize : 5; // Write protect group size [36:32]
+ UINT32 EraseGrpMult : 5; // Erase group size multiplier [41:37]
+ UINT32 EraseGrpSize : 5; // Erase group size [46:42]
+ UINT32 CSizeMult : 3; // Device size multiplier [49:47]
+ UINT32 VddWCurrMax : 3; // Max. write current @ VDD max [52:50]
+ UINT32 VddWCurrMin : 3; // Max. write current @ VDD min [55:53]
+ UINT32 VddRCurrMax : 3; // Max. read current @ VDD max [58:56]
+ UINT32 VddRCurrMin : 3; // Max. read current @ VDD min [61:59]
+ UINT32 CSizeLow : 2; // Device size low two bits [63:62]
- UINT32 CSizeHigh:10; // Device size high eight bits [73:64]
- UINT32 Reserved1:2; // Reserved [75:74]
- UINT32 DsrImp:1; // DSR implemented [76:76]
- UINT32 ReadBlkMisalign:1; // Read block misalignment [77:77]
- UINT32 WriteBlkMisalign:1; // Write block misalignment [78:78]
- UINT32 ReadBlPartial:1; // Partial blocks for read allowed [79:79]
- UINT32 ReadBlLen:4; // Max. read data block length [83:80]
- UINT32 Ccc:12; // Device command classes [95:84]
+ UINT32 CSizeHigh : 10; // Device size high eight bits [73:64]
+ UINT32 Reserved1 : 2; // Reserved [75:74]
+ UINT32 DsrImp : 1; // DSR implemented [76:76]
+ UINT32 ReadBlkMisalign : 1; // Read block misalignment [77:77]
+ UINT32 WriteBlkMisalign : 1; // Write block misalignment [78:78]
+ UINT32 ReadBlPartial : 1; // Partial blocks for read allowed [79:79]
+ UINT32 ReadBlLen : 4; // Max. read data block length [83:80]
+ UINT32 Ccc : 12; // Device command classes [95:84]
- UINT32 TranSpeed:8; // Max. bus clock frequency [103:96]
- UINT32 Nsac:8; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
- UINT32 Taac:8; // Data read access-time 1 [119:112]
- UINT32 Reserved2:2; // Reserved [121:120]
- UINT32 SpecVers:4; // System specification version [125:122]
- UINT32 CsdStructure:2; // CSD structure [127:126]
+ UINT32 TranSpeed : 8; // Max. bus clock frequency [103:96]
+ UINT32 Nsac : 8; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
+ UINT32 Taac : 8; // Data read access-time 1 [119:112]
+ UINT32 Reserved2 : 2; // Reserved [121:120]
+ UINT32 SpecVers : 4; // System specification version [125:122]
+ UINT32 CsdStructure : 2; // CSD structure [127:126]
} EMMC_CSD;
typedef struct {
//
// Modes Segment
//
- UINT8 Reserved[16]; // Reserved [15:0]
- UINT8 SecureRemovalType; // Secure Removal Type R/W & R [16]
- UINT8 ProductStateAwarenessEnablement; // Product state awareness enablement R/W/E & R [17]
- UINT8 MaxPreLoadingDataSize[4]; // Max pre loading data size R [21:18]
- UINT8 PreLoadingDataSize[4]; // Pre loading data size R/W/EP [25:22]
- UINT8 FfuStatus; // FFU status R [26]
- UINT8 Reserved1[2]; // Reserved [28:27]
- UINT8 ModeOperationCodes; // Mode operation codes W/EP [29]
- UINT8 ModeConfig; // Mode config R/W/EP [30]
- UINT8 Reserved2; // Reserved [31]
- UINT8 FlushCache; // Flushing of the cache W/EP [32]
- UINT8 CacheCtrl; // Control to turn the Cache ON/OFF R/W/EP [33]
- UINT8 PowerOffNotification; // Power Off Notification R/W/EP [34]
- UINT8 PackedFailureIndex; // Packed command failure index R [35]
- UINT8 PackedCommandStatus; // Packed command status R [36]
- UINT8 ContextConf[15]; // Context configuration R/W/EP [51:37]
- UINT8 ExtPartitionsAttribute[2]; // Extended Partitions Attribute R/W [53:52]
- UINT8 ExceptionEventsStatus[2]; // Exception events status R [55:54]
- UINT8 ExceptionEventsCtrl[2]; // Exception events control R/W/EP [57:56]
- UINT8 DyncapNeeded; // Number of addressed group to be Released R [58]
- UINT8 Class6Ctrl; // Class 6 commands control R/W/EP [59]
- UINT8 IniTimeoutEmu; // 1st initialization after disabling sector size emulation R [60]
- UINT8 DataSectorSize; // Sector size R [61]
- UINT8 UseNativeSector; // Sector size emulation R/W [62]
- UINT8 NativeSectorSize; // Native sector size R [63]
- UINT8 VendorSpecificField[64]; // Vendor Specific Fields [127:64]
- UINT8 Reserved3[2]; // Reserved [129:128]
- UINT8 ProgramCidCsdDdrSupport; // Program CID/CSD in DDR mode support R [130]
- UINT8 PeriodicWakeup; // Periodic Wake-up R/W/E [131]
- UINT8 TcaseSupport; // Package Case Temperature is controlled W/EP [132]
- UINT8 ProductionStateAwareness; // Production state awareness R/W/E [133]
- UINT8 SecBadBlkMgmnt; // Bad Block Management mode R/W [134]
- UINT8 Reserved4; // Reserved [135]
- UINT8 EnhStartAddr[4]; // Enhanced User Data Start Address R/W [139:136]
- UINT8 EnhSizeMult[3]; // Enhanced User Data Area Size R/W [142:140]
- UINT8 GpSizeMult[12]; // General Purpose Partition Size R/W [154:143]
- UINT8 PartitionSettingCompleted; // Partitioning Setting R/W [155]
- UINT8 PartitionsAttribute; // Partitions attribute R/W [156]
- UINT8 MaxEnhSizeMult[3]; // Max Enhanced Area Size R [159:157]
- UINT8 PartitioningSupport; // Partitioning Support R [160]
- UINT8 HpiMgmt; // HPI management R/W/EP [161]
- UINT8 RstFunction; // H/W reset function R/W [162]
- UINT8 BkopsEn; // Enable background operations handshake R/W [163]
- UINT8 BkopsStart; // Manually start background operations W/EP [164]
- UINT8 SanitizeStart; // Start Sanitize operation W/EP [165]
- UINT8 WrRelParam; // Write reliability parameter register R [166]
- UINT8 WrRelSet; // Write reliability setting register R/W [167]
- UINT8 RpmbSizeMult; // RPMB Size R [168]
- UINT8 FwConfig; // FW configuration R/W [169]
- UINT8 Reserved5; // Reserved [170]
- UINT8 UserWp; // User area write protection register R/W,R/W/CP&R/W/EP [171]
- UINT8 Reserved6; // Reserved [172]
- UINT8 BootWp; // Boot area write protection register R/W&R/W/CP[173]
- UINT8 BootWpStatus; // Boot write protection status registers R [174]
- UINT8 EraseGroupDef; // High-density erase group definition R/W/EP [175]
- UINT8 Reserved7; // Reserved [176]
- UINT8 BootBusConditions; // Boot bus Conditions R/W/E [177]
- UINT8 BootConfigProt; // Boot config protection R/W&R/W/CP[178]
- UINT8 PartitionConfig; // Partition configuration R/W/E&R/W/EP[179]
- UINT8 Reserved8; // Reserved [180]
- UINT8 ErasedMemCont; // Erased memory content R [181]
- UINT8 Reserved9; // Reserved [182]
- UINT8 BusWidth; // Bus width mode W/EP [183]
- UINT8 Reserved10; // Reserved [184]
- UINT8 HsTiming; // High-speed interface timing R/W/EP [185]
- UINT8 Reserved11; // Reserved [186]
- UINT8 PowerClass; // Power class R/W/EP [187]
- UINT8 Reserved12; // Reserved [188]
- UINT8 CmdSetRev; // Command set revision R [189]
- UINT8 Reserved13; // Reserved [190]
- UINT8 CmdSet; // Command set R/W/EP [191]
+ UINT8 Reserved[16]; // Reserved [15:0]
+ UINT8 SecureRemovalType; // Secure Removal Type R/W & R [16]
+ UINT8 ProductStateAwarenessEnablement; // Product state awareness enablement R/W/E & R [17]
+ UINT8 MaxPreLoadingDataSize[4]; // Max pre loading data size R [21:18]
+ UINT8 PreLoadingDataSize[4]; // Pre loading data size R/W/EP [25:22]
+ UINT8 FfuStatus; // FFU status R [26]
+ UINT8 Reserved1[2]; // Reserved [28:27]
+ UINT8 ModeOperationCodes; // Mode operation codes W/EP [29]
+ UINT8 ModeConfig; // Mode config R/W/EP [30]
+ UINT8 Reserved2; // Reserved [31]
+ UINT8 FlushCache; // Flushing of the cache W/EP [32]
+ UINT8 CacheCtrl; // Control to turn the Cache ON/OFF R/W/EP [33]
+ UINT8 PowerOffNotification; // Power Off Notification R/W/EP [34]
+ UINT8 PackedFailureIndex; // Packed command failure index R [35]
+ UINT8 PackedCommandStatus; // Packed command status R [36]
+ UINT8 ContextConf[15]; // Context configuration R/W/EP [51:37]
+ UINT8 ExtPartitionsAttribute[2]; // Extended Partitions Attribute R/W [53:52]
+ UINT8 ExceptionEventsStatus[2]; // Exception events status R [55:54]
+ UINT8 ExceptionEventsCtrl[2]; // Exception events control R/W/EP [57:56]
+ UINT8 DyncapNeeded; // Number of addressed group to be Released R [58]
+ UINT8 Class6Ctrl; // Class 6 commands control R/W/EP [59]
+ UINT8 IniTimeoutEmu; // 1st initialization after disabling sector size emulation R [60]
+ UINT8 DataSectorSize; // Sector size R [61]
+ UINT8 UseNativeSector; // Sector size emulation R/W [62]
+ UINT8 NativeSectorSize; // Native sector size R [63]
+ UINT8 VendorSpecificField[64]; // Vendor Specific Fields [127:64]
+ UINT8 Reserved3[2]; // Reserved [129:128]
+ UINT8 ProgramCidCsdDdrSupport; // Program CID/CSD in DDR mode support R [130]
+ UINT8 PeriodicWakeup; // Periodic Wake-up R/W/E [131]
+ UINT8 TcaseSupport; // Package Case Temperature is controlled W/EP [132]
+ UINT8 ProductionStateAwareness; // Production state awareness R/W/E [133]
+ UINT8 SecBadBlkMgmnt; // Bad Block Management mode R/W [134]
+ UINT8 Reserved4; // Reserved [135]
+ UINT8 EnhStartAddr[4]; // Enhanced User Data Start Address R/W [139:136]
+ UINT8 EnhSizeMult[3]; // Enhanced User Data Area Size R/W [142:140]
+ UINT8 GpSizeMult[12]; // General Purpose Partition Size R/W [154:143]
+ UINT8 PartitionSettingCompleted; // Partitioning Setting R/W [155]
+ UINT8 PartitionsAttribute; // Partitions attribute R/W [156]
+ UINT8 MaxEnhSizeMult[3]; // Max Enhanced Area Size R [159:157]
+ UINT8 PartitioningSupport; // Partitioning Support R [160]
+ UINT8 HpiMgmt; // HPI management R/W/EP [161]
+ UINT8 RstFunction; // H/W reset function R/W [162]
+ UINT8 BkopsEn; // Enable background operations handshake R/W [163]
+ UINT8 BkopsStart; // Manually start background operations W/EP [164]
+ UINT8 SanitizeStart; // Start Sanitize operation W/EP [165]
+ UINT8 WrRelParam; // Write reliability parameter register R [166]
+ UINT8 WrRelSet; // Write reliability setting register R/W [167]
+ UINT8 RpmbSizeMult; // RPMB Size R [168]
+ UINT8 FwConfig; // FW configuration R/W [169]
+ UINT8 Reserved5; // Reserved [170]
+ UINT8 UserWp; // User area write protection register R/W,R/W/CP&R/W/EP [171]
+ UINT8 Reserved6; // Reserved [172]
+ UINT8 BootWp; // Boot area write protection register R/W&R/W/CP[173]
+ UINT8 BootWpStatus; // Boot write protection status registers R [174]
+ UINT8 EraseGroupDef; // High-density erase group definition R/W/EP [175]
+ UINT8 Reserved7; // Reserved [176]
+ UINT8 BootBusConditions; // Boot bus Conditions R/W/E [177]
+ UINT8 BootConfigProt; // Boot config protection R/W&R/W/CP[178]
+ UINT8 PartitionConfig; // Partition configuration R/W/E&R/W/EP[179]
+ UINT8 Reserved8; // Reserved [180]
+ UINT8 ErasedMemCont; // Erased memory content R [181]
+ UINT8 Reserved9; // Reserved [182]
+ UINT8 BusWidth; // Bus width mode W/EP [183]
+ UINT8 Reserved10; // Reserved [184]
+ UINT8 HsTiming; // High-speed interface timing R/W/EP [185]
+ UINT8 Reserved11; // Reserved [186]
+ UINT8 PowerClass; // Power class R/W/EP [187]
+ UINT8 Reserved12; // Reserved [188]
+ UINT8 CmdSetRev; // Command set revision R [189]
+ UINT8 Reserved13; // Reserved [190]
+ UINT8 CmdSet; // Command set R/W/EP [191]
//
// Properties Segment
//
- UINT8 ExtCsdRev; // Extended CSD revision [192]
- UINT8 Reserved14; // Reserved [193]
- UINT8 CsdStructure; // CSD STRUCTURE [194]
- UINT8 Reserved15; // Reserved [195]
- UINT8 DeviceType; // Device type [196]
- UINT8 DriverStrength; // I/O Driver Strength [197]
- UINT8 OutOfInterruptTime; // Out-of-interrupt busy timing[198]
- UINT8 PartitionSwitchTime; // Partition switching timing [199]
- UINT8 PwrCl52M195V; // Power class for 52MHz at 1.95V [200]
- UINT8 PwrCl26M195V; // Power class for 26MHz at 1.95V [201]
- UINT8 PwrCl52M360V; // Power class for 52MHz at 3.6V [202]
- UINT8 PwrCl26M360V; // Power class for 26MHz at 3.6V [203]
- UINT8 Reserved16; // Reserved [204]
- UINT8 MinPerfR4B26M; // Minimum Read Performance for 4bit at 26MHz [205]
- UINT8 MinPerfW4B26M; // Minimum Write Performance for 4bit at 26MHz [206]
- UINT8 MinPerfR8B26M4B52M; // Minimum Read Performance for 8bit at 26MHz, for 4bit at 52MHz [207]
- UINT8 MinPerfW8B26M4B52M; // Minimum Write Performance for 8bit at 26MHz, for 4bit at 52MHz [208]
- UINT8 MinPerfR8B52M; // Minimum Read Performance for 8bit at 52MHz [209]
- UINT8 MinPerfW8B52M; // Minimum Write Performance for 8bit at 52MHz [210]
- UINT8 Reserved17; // Reserved [211]
- UINT8 SecCount[4]; // Sector Count [215:212]
- UINT8 SleepNotificationTime; // Sleep Notification Timeout [216]
- UINT8 SATimeout; // Sleep/awake timeout [217]
- UINT8 ProductionStateAwarenessTimeout; // Production state awareness timeout [218]
- UINT8 SCVccq; // Sleep current (VCCQ) [219]
- UINT8 SCVcc; // Sleep current (VCC) [220]
- UINT8 HcWpGrpSize; // High-capacity write protect group size [221]
- UINT8 RelWrSecC; // Reliable write sector count [222]
- UINT8 EraseTimeoutMult; // High-capacity erase timeout [223]
- UINT8 HcEraseGrpSize; // High-capacity erase unit size [224]
- UINT8 AccSize; // Access size [225]
- UINT8 BootSizeMult; // Boot partition size [226]
- UINT8 Reserved18; // Reserved [227]
- UINT8 BootInfo; // Boot information [228]
- UINT8 SecTrimMult; // Secure TRIM Multiplier [229]
- UINT8 SecEraseMult; // Secure Erase Multiplier [230]
- UINT8 SecFeatureSupport; // Secure Feature support [231]
- UINT8 TrimMult; // TRIM Multiplier [232]
- UINT8 Reserved19; // Reserved [233]
- UINT8 MinPerfDdrR8b52M; // Minimum Read Performance for 8bit at 52MHz in DDR mode [234]
- UINT8 MinPerfDdrW8b52M; // Minimum Write Performance for 8bit at 52MHz in DDR mode [235]
- UINT8 PwrCl200M130V; // Power class for 200MHz, at VCCQ=1.3V, VCC = 3.6V [236]
- UINT8 PwrCl200M195V; // Power class for 200MHz at VCCQ=1.95V, VCC = 3.6V [237]
- UINT8 PwrClDdr52M195V; // Power class for 52MHz, DDR at VCC= 1.95V [238]
- UINT8 PwrClDdr52M360V; // Power class for 52MHz, DDR at VCC= 3.6V [239]
- UINT8 Reserved20; // Reserved [240]
- UINT8 IniTimeoutAp; // 1st initialization time after partitioning [241]
- UINT8 CorrectlyPrgSectorsNum[4]; // Number of correctly programmed sectors [245:242]
- UINT8 BkopsStatus; // Background operations status [246]
- UINT8 PowerOffLongTime; // Power off notification(long) timeout [247]
- UINT8 GenericCmd6Time; // Generic CMD6 timeout [248]
- UINT8 CacheSize[4]; // Cache size [252:249]
- UINT8 PwrClDdr200M360V; // Power class for 200MHz, DDR at VCC= 3.6V [253]
- UINT8 FirmwareVersion[8]; // Firmware version [261:254]
- UINT8 DeviceVersion[2]; // Device version [263:262]
- UINT8 OptimalTrimUnitSize; // Optimal trim unit size[264]
- UINT8 OptimalWriteSize; // Optimal write size [265]
- UINT8 OptimalReadSize; // Optimal read size [266]
- UINT8 PreEolInfo; // Pre EOL information [267]
- UINT8 DeviceLifeTimeEstTypA; // Device life time estimation type A [268]
- UINT8 DeviceLifeTimeEstTypB; // Device life time estimation type B [269]
- UINT8 VendorProprietaryHealthReport[32]; // Vendor proprietary health report [301:270]
- UINT8 NumOfFwSectorsProgrammed[4]; // Number of FW sectors correctly programmed [305:302]
- UINT8 Reserved21[181]; // Reserved [486:306]
- UINT8 FfuArg[4]; // FFU Argument [490:487]
- UINT8 OperationCodeTimeout; // Operation codes timeout [491]
- UINT8 FfuFeatures; // FFU features [492]
- UINT8 SupportedModes; // Supported modes [493]
- UINT8 ExtSupport; // Extended partitions attribute support [494]
- UINT8 LargeUnitSizeM1; // Large Unit size [495]
- UINT8 ContextCapabilities; // Context management capabilities [496]
- UINT8 TagResSize; // Tag Resources Size [497]
- UINT8 TagUnitSize; // Tag Unit Size [498]
- UINT8 DataTagSupport; // Data Tag Support [499]
- UINT8 MaxPackedWrites; // Max packed write commands [500]
- UINT8 MaxPackedReads; // Max packed read commands[501]
- UINT8 BkOpsSupport; // Background operations support [502]
- UINT8 HpiFeatures; // HPI features [503]
- UINT8 SupportedCmdSet; // Supported Command Sets [504]
- UINT8 ExtSecurityErr; // Extended Security Commands Error [505]
- UINT8 Reserved22[6]; // Reserved [511:506]
+ UINT8 ExtCsdRev; // Extended CSD revision [192]
+ UINT8 Reserved14; // Reserved [193]
+ UINT8 CsdStructure; // CSD STRUCTURE [194]
+ UINT8 Reserved15; // Reserved [195]
+ UINT8 DeviceType; // Device type [196]
+ UINT8 DriverStrength; // I/O Driver Strength [197]
+ UINT8 OutOfInterruptTime; // Out-of-interrupt busy timing[198]
+ UINT8 PartitionSwitchTime; // Partition switching timing [199]
+ UINT8 PwrCl52M195V; // Power class for 52MHz at 1.95V [200]
+ UINT8 PwrCl26M195V; // Power class for 26MHz at 1.95V [201]
+ UINT8 PwrCl52M360V; // Power class for 52MHz at 3.6V [202]
+ UINT8 PwrCl26M360V; // Power class for 26MHz at 3.6V [203]
+ UINT8 Reserved16; // Reserved [204]
+ UINT8 MinPerfR4B26M; // Minimum Read Performance for 4bit at 26MHz [205]
+ UINT8 MinPerfW4B26M; // Minimum Write Performance for 4bit at 26MHz [206]
+ UINT8 MinPerfR8B26M4B52M; // Minimum Read Performance for 8bit at 26MHz, for 4bit at 52MHz [207]
+ UINT8 MinPerfW8B26M4B52M; // Minimum Write Performance for 8bit at 26MHz, for 4bit at 52MHz [208]
+ UINT8 MinPerfR8B52M; // Minimum Read Performance for 8bit at 52MHz [209]
+ UINT8 MinPerfW8B52M; // Minimum Write Performance for 8bit at 52MHz [210]
+ UINT8 Reserved17; // Reserved [211]
+ UINT8 SecCount[4]; // Sector Count [215:212]
+ UINT8 SleepNotificationTime; // Sleep Notification Timeout [216]
+ UINT8 SATimeout; // Sleep/awake timeout [217]
+ UINT8 ProductionStateAwarenessTimeout; // Production state awareness timeout [218]
+ UINT8 SCVccq; // Sleep current (VCCQ) [219]
+ UINT8 SCVcc; // Sleep current (VCC) [220]
+ UINT8 HcWpGrpSize; // High-capacity write protect group size [221]
+ UINT8 RelWrSecC; // Reliable write sector count [222]
+ UINT8 EraseTimeoutMult; // High-capacity erase timeout [223]
+ UINT8 HcEraseGrpSize; // High-capacity erase unit size [224]
+ UINT8 AccSize; // Access size [225]
+ UINT8 BootSizeMult; // Boot partition size [226]
+ UINT8 Reserved18; // Reserved [227]
+ UINT8 BootInfo; // Boot information [228]
+ UINT8 SecTrimMult; // Secure TRIM Multiplier [229]
+ UINT8 SecEraseMult; // Secure Erase Multiplier [230]
+ UINT8 SecFeatureSupport; // Secure Feature support [231]
+ UINT8 TrimMult; // TRIM Multiplier [232]
+ UINT8 Reserved19; // Reserved [233]
+ UINT8 MinPerfDdrR8b52M; // Minimum Read Performance for 8bit at 52MHz in DDR mode [234]
+ UINT8 MinPerfDdrW8b52M; // Minimum Write Performance for 8bit at 52MHz in DDR mode [235]
+ UINT8 PwrCl200M130V; // Power class for 200MHz, at VCCQ=1.3V, VCC = 3.6V [236]
+ UINT8 PwrCl200M195V; // Power class for 200MHz at VCCQ=1.95V, VCC = 3.6V [237]
+ UINT8 PwrClDdr52M195V; // Power class for 52MHz, DDR at VCC= 1.95V [238]
+ UINT8 PwrClDdr52M360V; // Power class for 52MHz, DDR at VCC= 3.6V [239]
+ UINT8 Reserved20; // Reserved [240]
+ UINT8 IniTimeoutAp; // 1st initialization time after partitioning [241]
+ UINT8 CorrectlyPrgSectorsNum[4]; // Number of correctly programmed sectors [245:242]
+ UINT8 BkopsStatus; // Background operations status [246]
+ UINT8 PowerOffLongTime; // Power off notification(long) timeout [247]
+ UINT8 GenericCmd6Time; // Generic CMD6 timeout [248]
+ UINT8 CacheSize[4]; // Cache size [252:249]
+ UINT8 PwrClDdr200M360V; // Power class for 200MHz, DDR at VCC= 3.6V [253]
+ UINT8 FirmwareVersion[8]; // Firmware version [261:254]
+ UINT8 DeviceVersion[2]; // Device version [263:262]
+ UINT8 OptimalTrimUnitSize; // Optimal trim unit size[264]
+ UINT8 OptimalWriteSize; // Optimal write size [265]
+ UINT8 OptimalReadSize; // Optimal read size [266]
+ UINT8 PreEolInfo; // Pre EOL information [267]
+ UINT8 DeviceLifeTimeEstTypA; // Device life time estimation type A [268]
+ UINT8 DeviceLifeTimeEstTypB; // Device life time estimation type B [269]
+ UINT8 VendorProprietaryHealthReport[32]; // Vendor proprietary health report [301:270]
+ UINT8 NumOfFwSectorsProgrammed[4]; // Number of FW sectors correctly programmed [305:302]
+ UINT8 Reserved21[181]; // Reserved [486:306]
+ UINT8 FfuArg[4]; // FFU Argument [490:487]
+ UINT8 OperationCodeTimeout; // Operation codes timeout [491]
+ UINT8 FfuFeatures; // FFU features [492]
+ UINT8 SupportedModes; // Supported modes [493]
+ UINT8 ExtSupport; // Extended partitions attribute support [494]
+ UINT8 LargeUnitSizeM1; // Large Unit size [495]
+ UINT8 ContextCapabilities; // Context management capabilities [496]
+ UINT8 TagResSize; // Tag Resources Size [497]
+ UINT8 TagUnitSize; // Tag Unit Size [498]
+ UINT8 DataTagSupport; // Data Tag Support [499]
+ UINT8 MaxPackedWrites; // Max packed write commands [500]
+ UINT8 MaxPackedReads; // Max packed read commands[501]
+ UINT8 BkOpsSupport; // Background operations support [502]
+ UINT8 HpiFeatures; // HPI features [503]
+ UINT8 SupportedCmdSet; // Supported Command Sets [504]
+ UINT8 ExtSecurityErr; // Extended Security Commands Error [505]
+ UINT8 Reserved22[6]; // Reserved [511:506]
} EMMC_EXT_CSD;
#pragma pack()
diff --git a/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h b/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h
index d2bc6d57..9d16104f 100644
--- a/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h
+++ b/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h
@@ -21,27 +21,26 @@
///
typedef union {
struct {
- UINT32 Revision : 8;
- UINT32 NumberOfTimers : 5;
- UINT32 CounterSize : 1;
- UINT32 Reserved : 1;
- UINT32 LegacyRoute : 1;
- UINT32 VendorId : 16;
+ UINT32 Revision : 8;
+ UINT32 NumberOfTimers : 5;
+ UINT32 CounterSize : 1;
+ UINT32 Reserved : 1;
+ UINT32 LegacyRoute : 1;
+ UINT32 VendorId : 16;
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_BLOCK_ID;
-
///
/// High Precision Event Timer Table header definition.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT32 EventTimerBlockId;
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddressLower32Bit;
- UINT8 HpetNumber;
- UINT16 MainCounterMinimumClockTickInPeriodicMode;
- UINT8 PageProtectionAndOemAttribute;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 EventTimerBlockId;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddressLower32Bit;
+ UINT8 HpetNumber;
+ UINT16 MainCounterMinimumClockTickInPeriodicMode;
+ UINT8 PageProtectionAndOemAttribute;
} EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER;
///
@@ -53,9 +52,9 @@ typedef struct {
// Page protection setting
// Values 3 through 15 are reserved for use by the specification
//
-#define EFI_ACPI_NO_PAGE_PROTECTION 0
-#define EFI_ACPI_4KB_PAGE_PROTECTION 1
-#define EFI_ACPI_64KB_PAGE_PROTECTION 2
+#define EFI_ACPI_NO_PAGE_PROTECTION 0
+#define EFI_ACPI_4KB_PAGE_PROTECTION 1
+#define EFI_ACPI_64KB_PAGE_PROTECTION 2
#pragma pack()
diff --git a/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h b/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h
index 8de0cbf6..627c01df 100644
--- a/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h
+++ b/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h
@@ -12,6 +12,7 @@
- GAS - Generic Address Structure
- LPI - Low Power Idle
**/
+
#ifndef _LOW_POWER_IDLE_TABLE_H_
#define _LOW_POWER_IDLE_TABLE_H_
@@ -22,53 +23,57 @@
///
/// LPI Structure Types
///
-#define ACPI_LPI_STRUCTURE_TYPE_NATIVE_CSTATE 0x00
+#define ACPI_LPI_STRUCTURE_TYPE_NATIVE_CSTATE 0x00
///
/// Low Power Idle (LPI) State Flags
///
typedef union {
struct {
- UINT32 Disabled : 1; ///< If set, LPI state is not used
+ UINT32 Disabled : 1; ///< If set, LPI state is not used
+
/**
If set, Residency counter is not available for this LPI state and
Residency Counter Frequency is invalid
**/
- UINT32 CounterUnavailable : 1;
- UINT32 Reserved : 30; ///< Reserved for future use. Must be zero
+ UINT32 CounterUnavailable : 1;
+ UINT32 Reserved : 30; ///< Reserved for future use. Must be zero
} Bits;
- UINT32 Data32;
+ UINT32 Data32;
} ACPI_LPI_STATE_FLAGS;
///
/// Low Power Idle (LPI) structure with Native C-state instruction entry trigger descriptor
///
typedef struct {
- UINT32 Type; ///< LPI State descriptor Type 0
- UINT32 Length; ///< Length of LPI state Descriptor Structure
+ UINT32 Type; ///< LPI State descriptor Type 0
+ UINT32 Length; ///< Length of LPI state Descriptor Structure
///
/// Unique LPI state identifier: zero based, monotonically increasing identifier
///
- UINT16 UniqueId;
- UINT8 Reserved[2]; ///< Must be Zero
- ACPI_LPI_STATE_FLAGS Flags; ///< LPI state flags
+ UINT16 UniqueId;
+ UINT8 Reserved[2]; ///< Must be Zero
+ ACPI_LPI_STATE_FLAGS Flags; ///< LPI state flags
+
/**
The LPI entry trigger, matching an existing _CST.Register object, represented as a
Generic Address Structure. All processors must request this state or deeper to trigger.
**/
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE EntryTrigger;
- UINT32 Residency; ///< Minimum residency or break-even in uSec
- UINT32 Latency; ///< Worst case exit latency in uSec
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE EntryTrigger;
+ UINT32 Residency; ///< Minimum residency or break-even in uSec
+ UINT32 Latency; ///< Worst case exit latency in uSec
+
/**
[optional] Residency counter, represented as a Generic Address Structure.
If not present, Flags[1] bit should be set.
**/
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResidencyCounter;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResidencyCounter;
+
/**
[optional] Residency counter frequency in cycles per second. Value 0 indicates that
counter runs at TSC frequency. Valid only if Residency Counter is present.
**/
- UINT64 ResidencyCounterFrequency;
+ UINT64 ResidencyCounterFrequency;
} ACPI_LPI_NATIVE_CSTATE_DESCRIPTOR;
#pragma pack()
diff --git a/MdePkg/Include/IndustryStandard/Mbr.h b/MdePkg/Include/IndustryStandard/Mbr.h
index 2d8c1f1e..8ceef53c 100644
--- a/MdePkg/Include/IndustryStandard/Mbr.h
+++ b/MdePkg/Include/IndustryStandard/Mbr.h
@@ -9,44 +9,44 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _MBR_H_
#define _MBR_H_
-#define MBR_SIGNATURE 0xaa55
+#define MBR_SIGNATURE 0xaa55
#define EXTENDED_DOS_PARTITION 0x05
#define EXTENDED_WINDOWS_PARTITION 0x0F
-#define MAX_MBR_PARTITIONS 4
+#define MAX_MBR_PARTITIONS 4
-#define PMBR_GPT_PARTITION 0xEE
-#define EFI_PARTITION 0xEF
+#define PMBR_GPT_PARTITION 0xEE
+#define EFI_PARTITION 0xEF
-#define MBR_SIZE 512
+#define MBR_SIZE 512
#pragma pack(1)
///
/// MBR Partition Entry
///
typedef struct {
- UINT8 BootIndicator;
- UINT8 StartHead;
- UINT8 StartSector;
- UINT8 StartTrack;
- UINT8 OSIndicator;
- UINT8 EndHead;
- UINT8 EndSector;
- UINT8 EndTrack;
- UINT8 StartingLBA[4];
- UINT8 SizeInLBA[4];
+ UINT8 BootIndicator;
+ UINT8 StartHead;
+ UINT8 StartSector;
+ UINT8 StartTrack;
+ UINT8 OSIndicator;
+ UINT8 EndHead;
+ UINT8 EndSector;
+ UINT8 EndTrack;
+ UINT8 StartingLBA[4];
+ UINT8 SizeInLBA[4];
} MBR_PARTITION_RECORD;
///
/// MBR Partition Table
///
typedef struct {
- UINT8 BootStrapCode[440];
- UINT8 UniqueMbrSignature[4];
- UINT8 Unknown[2];
- MBR_PARTITION_RECORD Partition[MAX_MBR_PARTITIONS];
- UINT16 Signature;
+ UINT8 BootStrapCode[440];
+ UINT8 UniqueMbrSignature[4];
+ UINT8 Unknown[2];
+ MBR_PARTITION_RECORD Partition[MAX_MBR_PARTITIONS];
+ UINT16 Signature;
} MASTER_BOOT_RECORD;
#pragma pack()
diff --git a/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h b/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h
index 4bc163e1..d47bf848 100644
--- a/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h
+++ b/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h
@@ -23,11 +23,11 @@
/// a number of base address allocation structures.
///
typedef struct {
- UINT64 BaseAddress;
- UINT16 PciSegmentGroupNumber;
- UINT8 StartBusNumber;
- UINT8 EndBusNumber;
- UINT32 Reserved;
+ UINT64 BaseAddress;
+ UINT16 PciSegmentGroupNumber;
+ UINT8 StartBusNumber;
+ UINT8 EndBusNumber;
+ UINT32 Reserved;
} EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE;
///
@@ -35,8 +35,8 @@ typedef struct {
/// must be defined in a platform specific manner.
///
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 Reserved;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 Reserved;
} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER;
///
diff --git a/MdePkg/Include/IndustryStandard/Nvme.h b/MdePkg/Include/IndustryStandard/Nvme.h
index 4601a59e..5313b939 100644
--- a/MdePkg/Include/IndustryStandard/Nvme.h
+++ b/MdePkg/Include/IndustryStandard/Nvme.h
@@ -2,11 +2,13 @@
Definitions based on NVMe spec. version 1.1.
(C) Copyright 2016 Hewlett Packard Enterprise Development LP
- Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
NVMe Specification 1.1
+ NVMe Specification 1.4
+ NVMe Specification 2.0
**/
@@ -18,26 +20,28 @@
//
// controller register offsets
//
-#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities
-#define NVME_VER_OFFSET 0x0008 // Version
-#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set
-#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear
-#define NVME_CC_OFFSET 0x0014 // Controller Configuration
-#define NVME_CSTS_OFFSET 0x001c // Controller Status
-#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset
-#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes
-#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address
-#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address
-#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell
-#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell
+#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities
+#define NVME_VER_OFFSET 0x0008 // Version
+#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set
+#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear
+#define NVME_CC_OFFSET 0x0014 // Controller Configuration
+#define NVME_CSTS_OFFSET 0x001c // Controller Status
+#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset
+#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes
+#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address
+#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address
+#define NVME_BPINFO_OFFSET 0x0040 // Boot Partition Information
+#define NVME_BPRSEL_OFFSET 0x0044 // Boot Partition Read Select
+#define NVME_BPMBL_OFFSET 0x0048 // Boot Partition Memory Buffer Location
+#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell
+#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell
//
// These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))
// Get the doorbell stride bit shift value from the controller capabilities.
//
-#define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell
-#define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell
-
+#define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell
+#define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell
#pragma pack(1)
@@ -45,90 +49,122 @@
// 3.1.1 Offset 00h: CAP - Controller Capabilities
//
typedef struct {
- UINT16 Mqes; // Maximum Queue Entries Supported
- UINT8 Cqr:1; // Contiguous Queues Required
- UINT8 Ams:2; // Arbitration Mechanism Supported
- UINT8 Rsvd1:5;
- UINT8 To; // Timeout
- UINT16 Dstrd:4;
- UINT16 Nssrs:1; // NVM Subsystem Reset Supported NSSRS
- UINT16 Css:4; // Command Sets Supported - Bit 37
- UINT16 Rsvd3:7;
- UINT8 Mpsmin:4;
- UINT8 Mpsmax:4;
- UINT8 Rsvd4;
+ UINT16 Mqes; // Maximum Queue Entries Supported
+ UINT8 Cqr : 1; // Contiguous Queues Required
+ UINT8 Ams : 2; // Arbitration Mechanism Supported
+ UINT8 Rsvd1 : 5;
+ UINT8 To; // Timeout
+ UINT16 Dstrd : 4;
+ UINT16 Nssrs : 1; // NVM Subsystem Reset Supported NSSRS
+ UINT16 Css : 8; // Command Sets Supported - Bit 37
+ UINT16 Bps : 1; // Boot Partition Support - Bit 45 in NVMe1.4
+ UINT16 Rsvd3 : 2;
+ UINT8 Mpsmin : 4;
+ UINT8 Mpsmax : 4;
+ UINT8 Pmrs : 1;
+ UINT8 Cmbs : 1;
+ UINT8 Rsvd4 : 6;
} NVME_CAP;
//
// 3.1.2 Offset 08h: VS - Version
//
typedef struct {
- UINT16 Mnr; // Minor version number
- UINT16 Mjr; // Major version number
+ UINT16 Mnr; // Minor version number
+ UINT16 Mjr; // Major version number
} NVME_VER;
//
// 3.1.5 Offset 14h: CC - Controller Configuration
//
typedef struct {
- UINT16 En:1; // Enable
- UINT16 Rsvd1:3;
- UINT16 Css:3; // I/O Command Set Selected
- UINT16 Mps:4; // Memory Page Size
- UINT16 Ams:3; // Arbitration Mechanism Selected
- UINT16 Shn:2; // Shutdown Notification
- UINT8 Iosqes:4; // I/O Submission Queue Entry Size
- UINT8 Iocqes:4; // I/O Completion Queue Entry Size
- UINT8 Rsvd2;
+ UINT16 En : 1; // Enable
+ UINT16 Rsvd1 : 3;
+ UINT16 Css : 3; // I/O Command Set Selected
+ UINT16 Mps : 4; // Memory Page Size
+ UINT16 Ams : 3; // Arbitration Mechanism Selected
+ UINT16 Shn : 2; // Shutdown Notification
+ UINT8 Iosqes : 4; // I/O Submission Queue Entry Size
+ UINT8 Iocqes : 4; // I/O Completion Queue Entry Size
+ UINT8 Rsvd2;
} NVME_CC;
-#define NVME_CC_SHN_NORMAL_SHUTDOWN 1
-#define NVME_CC_SHN_ABRUPT_SHUTDOWN 2
+#define NVME_CC_SHN_NORMAL_SHUTDOWN 1
+#define NVME_CC_SHN_ABRUPT_SHUTDOWN 2
//
// 3.1.6 Offset 1Ch: CSTS - Controller Status
//
typedef struct {
- UINT32 Rdy:1; // Ready
- UINT32 Cfs:1; // Controller Fatal Status
- UINT32 Shst:2; // Shutdown Status
- UINT32 Nssro:1; // NVM Subsystem Reset Occurred
- UINT32 Rsvd1:27;
+ UINT32 Rdy : 1; // Ready
+ UINT32 Cfs : 1; // Controller Fatal Status
+ UINT32 Shst : 2; // Shutdown Status
+ UINT32 Nssro : 1; // NVM Subsystem Reset Occurred
+ UINT32 Rsvd1 : 27;
} NVME_CSTS;
-#define NVME_CSTS_SHST_SHUTDOWN_OCCURRING 1
-#define NVME_CSTS_SHST_SHUTDOWN_COMPLETED 2
+#define NVME_CSTS_SHST_SHUTDOWN_OCCURRING 1
+#define NVME_CSTS_SHST_SHUTDOWN_COMPLETED 2
//
// 3.1.8 Offset 24h: AQA - Admin Queue Attributes
//
typedef struct {
- UINT16 Asqs:12; // Submission Queue Size
- UINT16 Rsvd1:4;
- UINT16 Acqs:12; // Completion Queue Size
- UINT16 Rsvd2:4;
+ UINT16 Asqs : 12; // Submission Queue Size
+ UINT16 Rsvd1 : 4;
+ UINT16 Acqs : 12; // Completion Queue Size
+ UINT16 Rsvd2 : 4;
} NVME_AQA;
//
// 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address
//
-#define NVME_ASQ UINT64
+#define NVME_ASQ UINT64
//
// 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address
//
-#define NVME_ACQ UINT64
+#define NVME_ACQ UINT64
//
-// 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell
+// 3.1.13 Offset 40h: BPINFO - Boot Partition Information
//
typedef struct {
- UINT16 Sqt;
- UINT16 Rsvd1;
+ UINT32 Bpsz : 15; // Boot Partition Size
+ UINT32 Rsvd1 : 9;
+ UINT32 Brs : 2; // Boot Read Status
+ UINT32 Rsvd2 : 5;
+ UINT32 Abpid : 1; // Active Boot Partition ID
+} NVME_BPINFO;
+
+//
+// 3.1.14 Offset 44h: BPRSEL - Boot Partition Read Select
+//
+typedef struct {
+ UINT32 Bprsz : 10; // Boot Partition Read Size
+ UINT32 Bprof : 20; // Boot Partition Read Offset
+ UINT32 Rsvd1 : 1;
+ UINT32 Bpid : 1; // Boot Partition Identifier
+} NVME_BPRSEL;
+
+//
+// 3.1.15 Offset 48h: BPMBL - Boot Partition Memory Buffer Location (Optional)
+//
+typedef struct {
+ UINT64 Rsvd1 : 12;
+ UINT64 Bmbba : 52; // Boot Partition Memory Buffer Base Address
+} NVME_BPMBL;
+
+//
+// 3.1.25 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell
+//
+typedef struct {
+ UINT16 Sqt;
+ UINT16 Rsvd1;
} NVME_SQTDBL;
//
// 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell
//
typedef struct {
- UINT16 Cqh;
- UINT16 Rsvd1;
+ UINT16 Cqh;
+ UINT16 Rsvd1;
} NVME_CQHDBL;
//
@@ -140,32 +176,32 @@ typedef struct {
//
// CDW 10, 11
//
- UINT64 Slba; /* Starting Sector Address */
+ UINT64 Slba; /* Starting Sector Address */
//
// CDW 12
//
- UINT16 Nlb; /* Number of Sectors */
- UINT16 Rsvd1:10;
- UINT16 Prinfo:4; /* Protection Info Check */
- UINT16 Fua:1; /* Force Unit Access */
- UINT16 Lr:1; /* Limited Retry */
+ UINT16 Nlb; /* Number of Sectors */
+ UINT16 Rsvd1 : 10;
+ UINT16 Prinfo : 4; /* Protection Info Check */
+ UINT16 Fua : 1; /* Force Unit Access */
+ UINT16 Lr : 1; /* Limited Retry */
//
// CDW 13
//
- UINT32 Af:4; /* Access Frequency */
- UINT32 Al:2; /* Access Latency */
- UINT32 Sr:1; /* Sequential Request */
- UINT32 In:1; /* Incompressible */
- UINT32 Rsvd2:24;
+ UINT32 Af : 4; /* Access Frequency */
+ UINT32 Al : 2; /* Access Latency */
+ UINT32 Sr : 1; /* Sequential Request */
+ UINT32 In : 1; /* Incompressible */
+ UINT32 Rsvd2 : 24;
//
// CDW 14
//
- UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */
+ UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */
//
// CDW 15
//
- UINT16 Elbat; /* Expected Logical Block Application Tag */
- UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */
+ UINT16 Elbat; /* Expected Logical Block Application Tag */
+ UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */
} NVME_READ;
//
@@ -175,32 +211,32 @@ typedef struct {
//
// CDW 10, 11
//
- UINT64 Slba; /* Starting Sector Address */
+ UINT64 Slba; /* Starting Sector Address */
//
// CDW 12
//
- UINT16 Nlb; /* Number of Sectors */
- UINT16 Rsvd1:10;
- UINT16 Prinfo:4; /* Protection Info Check */
- UINT16 Fua:1; /* Force Unit Access */
- UINT16 Lr:1; /* Limited Retry */
+ UINT16 Nlb; /* Number of Sectors */
+ UINT16 Rsvd1 : 10;
+ UINT16 Prinfo : 4; /* Protection Info Check */
+ UINT16 Fua : 1; /* Force Unit Access */
+ UINT16 Lr : 1; /* Limited Retry */
//
// CDW 13
//
- UINT32 Af:4; /* Access Frequency */
- UINT32 Al:2; /* Access Latency */
- UINT32 Sr:1; /* Sequential Request */
- UINT32 In:1; /* Incompressible */
- UINT32 Rsvd2:24;
+ UINT32 Af : 4; /* Access Frequency */
+ UINT32 Al : 2; /* Access Latency */
+ UINT32 Sr : 1; /* Sequential Request */
+ UINT32 In : 1; /* Incompressible */
+ UINT32 Rsvd2 : 24;
//
// CDW 14
//
- UINT32 Ilbrt; /* Initial Logical Block Reference Tag */
+ UINT32 Ilbrt; /* Initial Logical Block Reference Tag */
//
// CDW 15
//
- UINT16 Lbat; /* Logical Block Application Tag */
- UINT16 Lbatm; /* Logical Block Application Tag Mask */
+ UINT16 Lbat; /* Logical Block Application Tag */
+ UINT16 Lbatm; /* Logical Block Application Tag Mask */
} NVME_WRITE;
//
@@ -210,7 +246,7 @@ typedef struct {
//
// CDW 10
//
- UINT32 Flush; /* Flush */
+ UINT32 Flush; /* Flush */
} NVME_FLUSH;
//
@@ -220,12 +256,12 @@ typedef struct {
//
// CDW 10, 11
//
- UINT64 Slba; /* Starting LBA */
+ UINT64 Slba; /* Starting LBA */
//
// CDW 12
//
- UINT32 Nlb:16; /* Number of Logical Blocks */
- UINT32 Rsvd1:16;
+ UINT32 Nlb : 16; /* Number of Logical Blocks */
+ UINT32 Rsvd1 : 16;
} NVME_WRITE_UNCORRECTABLE;
//
@@ -235,28 +271,28 @@ typedef struct {
//
// CDW 10, 11
//
- UINT64 Slba; /* Starting LBA */
+ UINT64 Slba; /* Starting LBA */
//
// CDW 12
//
- UINT16 Nlb; /* Number of Logical Blocks */
- UINT16 Rsvd1:10;
- UINT16 Prinfo:4; /* Protection Info Check */
- UINT16 Fua:1; /* Force Unit Access */
- UINT16 Lr:1; /* Limited Retry */
+ UINT16 Nlb; /* Number of Logical Blocks */
+ UINT16 Rsvd1 : 10;
+ UINT16 Prinfo : 4; /* Protection Info Check */
+ UINT16 Fua : 1; /* Force Unit Access */
+ UINT16 Lr : 1; /* Limited Retry */
//
// CDW 13
//
- UINT32 Rsvd2;
+ UINT32 Rsvd2;
//
// CDW 14
//
- UINT32 Ilbrt; /* Initial Logical Block Reference Tag */
+ UINT32 Ilbrt; /* Initial Logical Block Reference Tag */
//
// CDW 15
//
- UINT16 Lbat; /* Logical Block Application Tag */
- UINT16 Lbatm; /* Logical Block Application Tag Mask */
+ UINT16 Lbat; /* Logical Block Application Tag */
+ UINT16 Lbatm; /* Logical Block Application Tag Mask */
} NVME_WRITE_ZEROES;
//
@@ -266,28 +302,28 @@ typedef struct {
//
// CDW 10, 11
//
- UINT64 Slba; /* Starting LBA */
+ UINT64 Slba; /* Starting LBA */
//
// CDW 12
//
- UINT16 Nlb; /* Number of Logical Blocks */
- UINT16 Rsvd1:10;
- UINT16 Prinfo:4; /* Protection Info Check */
- UINT16 Fua:1; /* Force Unit Access */
- UINT16 Lr:1; /* Limited Retry */
+ UINT16 Nlb; /* Number of Logical Blocks */
+ UINT16 Rsvd1 : 10;
+ UINT16 Prinfo : 4; /* Protection Info Check */
+ UINT16 Fua : 1; /* Force Unit Access */
+ UINT16 Lr : 1; /* Limited Retry */
//
// CDW 13
//
- UINT32 Rsvd2;
+ UINT32 Rsvd2;
//
// CDW 14
//
- UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */
+ UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */
//
// CDW 15
//
- UINT16 Elbat; /* Expected Logical Block Application Tag */
- UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */
+ UINT16 Elbat; /* Expected Logical Block Application Tag */
+ UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */
} NVME_COMPARE;
typedef union {
@@ -300,22 +336,22 @@ typedef union {
} NVME_CMD;
typedef struct {
- UINT16 Mp; /* Maximum Power */
- UINT8 Rsvd1; /* Reserved as of Nvm Express 1.1 Spec */
- UINT8 Mps:1; /* Max Power Scale */
- UINT8 Nops:1; /* Non-Operational State */
- UINT8 Rsvd2:6; /* Reserved as of Nvm Express 1.1 Spec */
- UINT32 Enlat; /* Entry Latency */
- UINT32 Exlat; /* Exit Latency */
- UINT8 Rrt:5; /* Relative Read Throughput */
- UINT8 Rsvd3:3; /* Reserved as of Nvm Express 1.1 Spec */
- UINT8 Rrl:5; /* Relative Read Latency */
- UINT8 Rsvd4:3; /* Reserved as of Nvm Express 1.1 Spec */
- UINT8 Rwt:5; /* Relative Write Throughput */
- UINT8 Rsvd5:3; /* Reserved as of Nvm Express 1.1 Spec */
- UINT8 Rwl:5; /* Relative Write Latency */
- UINT8 Rsvd6:3; /* Reserved as of Nvm Express 1.1 Spec */
- UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT16 Mp; /* Maximum Power */
+ UINT8 Rsvd1; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT8 Mps : 1; /* Max Power Scale */
+ UINT8 Nops : 1; /* Non-Operational State */
+ UINT8 Rsvd2 : 6; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT32 Enlat; /* Entry Latency */
+ UINT32 Exlat; /* Exit Latency */
+ UINT8 Rrt : 5; /* Relative Read Throughput */
+ UINT8 Rsvd3 : 3; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT8 Rrl : 5; /* Relative Read Latency */
+ UINT8 Rsvd4 : 3; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT8 Rwt : 5; /* Relative Write Throughput */
+ UINT8 Rsvd5 : 3; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT8 Rwl : 5; /* Relative Write Latency */
+ UINT8 Rsvd6 : 3; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */
} NVME_PSDESCRIPTOR;
//
@@ -325,84 +361,89 @@ typedef struct {
//
// Controller Capabilities and Features 0-255
//
- UINT16 Vid; /* PCI Vendor ID */
- UINT16 Ssvid; /* PCI sub-system vendor ID */
- UINT8 Sn[20]; /* Product serial number */
+ UINT16 Vid; /* PCI Vendor ID */
+ UINT16 Ssvid; /* PCI sub-system vendor ID */
+ UINT8 Sn[20]; /* Product serial number */
- UINT8 Mn[40]; /* Product model number */
- UINT8 Fr[8]; /* Firmware Revision */
- UINT8 Rab; /* Recommended Arbitration Burst */
- UINT8 Ieee_oui[3]; /* Organization Unique Identifier */
- UINT8 Cmic; /* Multi-interface Capabilities */
- UINT8 Mdts; /* Maximum Data Transfer Size */
- UINT8 Cntlid[2]; /* Controller ID */
- UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT8 Mn[40]; /* Product model number */
+ UINT8 Fr[8]; /* Firmware Revision */
+ UINT8 Rab; /* Recommended Arbitration Burst */
+ UINT8 Ieee_oui[3]; /* Organization Unique Identifier */
+ UINT8 Cmic; /* Multi-interface Capabilities */
+ UINT8 Mdts; /* Maximum Data Transfer Size */
+ UINT8 Cntlid[2]; /* Controller ID */
+ UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */
//
// Admin Command Set Attributes
//
- UINT16 Oacs; /* Optional Admin Command Support */
- #define NAMESPACE_MANAGEMENT_SUPPORTED BIT3
- #define FW_DOWNLOAD_ACTIVATE_SUPPORTED BIT2
- #define FORMAT_NVM_SUPPORTED BIT1
- #define SECURITY_SEND_RECEIVE_SUPPORTED BIT0
- UINT8 Acl; /* Abort Command Limit */
- UINT8 Aerl; /* Async Event Request Limit */
- UINT8 Frmw; /* Firmware updates */
- UINT8 Lpa; /* Log Page Attributes */
- UINT8 Elpe; /* Error Log Page Entries */
- UINT8 Npss; /* Number of Power States Support */
- UINT8 Avscc; /* Admin Vendor Specific Command Configuration */
- UINT8 Apsta; /* Autonomous Power State Transition Attributes */
+ UINT16 Oacs; /* Optional Admin Command Support */
+ #define NAMESPACE_MANAGEMENT_SUPPORTED BIT3
+ #define FW_DOWNLOAD_ACTIVATE_SUPPORTED BIT2
+ #define FORMAT_NVM_SUPPORTED BIT1
+ #define SECURITY_SEND_RECEIVE_SUPPORTED BIT0
+ UINT8 Acl; /* Abort Command Limit */
+ UINT8 Aerl; /* Async Event Request Limit */
+ UINT8 Frmw; /* Firmware updates */
+ UINT8 Lpa; /* Log Page Attributes */
+ UINT8 Elpe; /* Error Log Page Entries */
+ UINT8 Npss; /* Number of Power States Support */
+ UINT8 Avscc; /* Admin Vendor Specific Command Configuration */
+ UINT8 Apsta; /* Autonomous Power State Transition Attributes */
//
- // Below fields before Rsvd2 are defined in NVM Express 1.3 Spec
+ // Below fields before Rsvd2 are defined in NVM Express 1.4 Spec
//
- UINT16 Wctemp; /* Warning Composite Temperature Threshold */
- UINT16 Cctemp; /* Critical Composite Temperature Threshold */
- UINT16 Mtfa; /* Maximum Time for Firmware Activation */
- UINT32 Hmpre; /* Host Memory Buffer Preferred Size */
- UINT32 Hmmin; /* Host Memory Buffer Minimum Size */
- UINT8 Tnvmcap[16]; /* Total NVM Capacity */
- UINT8 Rsvd2[216]; /* Reserved as of NVM Express */
+ UINT16 Wctemp; /* Warning Composite Temperature Threshold */
+ UINT16 Cctemp; /* Critical Composite Temperature Threshold */
+ UINT16 Mtfa; /* Maximum Time for Firmware Activation */
+ UINT32 Hmpre; /* Host Memory Buffer Preferred Size */
+ UINT32 Hmmin; /* Host Memory Buffer Minimum Size */
+ UINT8 Tnvmcap[16]; /* Total NVM Capacity */
+ UINT8 Unvmcap[16]; /* Unallocated NVM Capacity */
+ UINT32 Rpmbs; /* Replay Protected Memory Block Support */
+ UINT16 Edstt; /* Extended Device Self-test Time */
+ UINT8 Dsto; /* Device Self-test Options */
+ UINT8 Fwug; /* Firmware Update Granularity */
+ UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.4 Spec */
//
// NVM Command Set Attributes
//
- UINT8 Sqes; /* Submission Queue Entry Size */
- UINT8 Cqes; /* Completion Queue Entry Size */
- UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */
- UINT32 Nn; /* Number of Namespaces */
- UINT16 Oncs; /* Optional NVM Command Support */
- UINT16 Fuses; /* Fused Operation Support */
- UINT8 Fna; /* Format NVM Attributes */
- UINT8 Vwc; /* Volatile Write Cache */
- UINT16 Awun; /* Atomic Write Unit Normal */
- UINT16 Awupf; /* Atomic Write Unit Power Fail */
- UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */
- UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */
- UINT16 Acwu; /* Atomic Compare & Write Unit */
- UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */
- UINT32 Sgls; /* SGL Support */
- UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT8 Sqes; /* Submission Queue Entry Size */
+ UINT8 Cqes; /* Completion Queue Entry Size */
+ UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT32 Nn; /* Number of Namespaces */
+ UINT16 Oncs; /* Optional NVM Command Support */
+ UINT16 Fuses; /* Fused Operation Support */
+ UINT8 Fna; /* Format NVM Attributes */
+ UINT8 Vwc; /* Volatile Write Cache */
+ UINT16 Awun; /* Atomic Write Unit Normal */
+ UINT16 Awupf; /* Atomic Write Unit Power Fail */
+ UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */
+ UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT16 Acwu; /* Atomic Compare & Write Unit */
+ UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT32 Sgls; /* SGL Support */
+ UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */
//
// I/O Command set Attributes
//
- UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */
//
// Power State Descriptors
//
- NVME_PSDESCRIPTOR PsDescriptor[32];
+ NVME_PSDESCRIPTOR PsDescriptor[32];
- UINT8 VendorData[1024]; /* Vendor specific data */
+ UINT8 VendorData[1024]; /* Vendor specific data */
} NVME_ADMIN_CONTROLLER_DATA;
typedef struct {
- UINT16 Ms; /* Metadata Size */
- UINT8 Lbads; /* LBA Data Size */
- UINT8 Rp:2; /* Relative Performance */
- #define LBAF_RP_BEST 00b
- #define LBAF_RP_BETTER 01b
- #define LBAF_RP_GOOD 10b
- #define LBAF_RP_DEGRADED 11b
- UINT8 Rsvd1:6; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT16 Ms; /* Metadata Size */
+ UINT8 Lbads; /* LBA Data Size */
+ UINT8 Rp : 2; /* Relative Performance */
+ #define LBAF_RP_BEST 00b
+ #define LBAF_RP_BETTER 01b
+ #define LBAF_RP_GOOD 10b
+ #define LBAF_RP_DEGRADED 11b
+ UINT8 Rsvd1 : 6; /* Reserved as of Nvm Express 1.1 Spec */
} NVME_LBAFORMAT;
//
@@ -412,28 +453,112 @@ typedef struct {
//
// NVM Command Set Specific
//
- UINT64 Nsze; /* Namespace Size (total number of blocks in formatted namespace) */
- UINT64 Ncap; /* Namespace Capacity (max number of logical blocks) */
- UINT64 Nuse; /* Namespace Utilization */
- UINT8 Nsfeat; /* Namespace Features */
- UINT8 Nlbaf; /* Number of LBA Formats */
- UINT8 Flbas; /* Formatted LBA size */
- UINT8 Mc; /* Metadata Capabilities */
- UINT8 Dpc; /* End-to-end Data Protection capabilities */
- UINT8 Dps; /* End-to-end Data Protection Type Settings */
- UINT8 Nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */
- UINT8 Rescap; /* Reservation Capabilities */
- UINT8 Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */
- UINT64 Eui64; /* IEEE Extended Unique Identifier */
+ UINT64 Nsze; /* Namespace Size (total number of blocks in formatted namespace) */
+ UINT64 Ncap; /* Namespace Capacity (max number of logical blocks) */
+ UINT64 Nuse; /* Namespace Utilization */
+ UINT8 Nsfeat; /* Namespace Features */
+ UINT8 Nlbaf; /* Number of LBA Formats */
+ UINT8 Flbas; /* Formatted LBA size */
+ UINT8 Mc; /* Metadata Capabilities */
+ UINT8 Dpc; /* End-to-end Data Protection capabilities */
+ UINT8 Dps; /* End-to-end Data Protection Type Settings */
+ UINT8 Nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */
+ UINT8 Rescap; /* Reservation Capabilities */
+ UINT8 Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT64 Eui64; /* IEEE Extended Unique Identifier */
//
// LBA Format
//
- NVME_LBAFORMAT LbaFormat[16];
+ NVME_LBAFORMAT LbaFormat[16];
- UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.1 Spec */
- UINT8 VendorData[3712]; /* Vendor specific data */
+ UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT8 VendorData[3712]; /* Vendor specific data */
} NVME_ADMIN_NAMESPACE_DATA;
+//
+// RPMB Device Configuration Block Data Structure as of Nvm Express 1.4 Spec
+//
+typedef struct {
+ UINT8 Bppe; /* Boot Partition Protection Enable */
+ UINT8 Bpl; /* Boot Partition Lock */
+ UINT8 Nwpac; /* Namespace Write Protection Authentication Control */
+ UINT8 Rsvd1[509]; /* Reserved as of Nvm Express 1.4 Spec */
+} NVME_RPMB_CONFIGURATION_DATA;
+
+#define RPMB_FRAME_STUFF_BYTES 223
+
+//
+// RPMB Data Frame as of Nvm Express 1.4 Spec
+//
+typedef struct {
+ UINT8 Sbakamc[RPMB_FRAME_STUFF_BYTES]; /* [222-N:00] Stuff Bytes */
+ /* [222:222-(N-1)] Authentication Key or Message Authentication Code (MAC) */
+ UINT8 Rpmbt; /* RPMB Target */
+ UINT64 Nonce[2];
+ UINT32 Wcounter; /* Write Counter */
+ UINT32 Address; /* Starting address of data to be programmed to or read from the RPMB. */
+ UINT32 Scount; /* Sector Count */
+ UINT16 Result;
+ UINT16 Rpmessage; /* Request/Response Message */
+ // UINT8 *Data; /* Data to be written or read by signed access where M = 512 * Sector Count. */
+} NVME_RPMB_DATA_FRAME;
+
+//
+// RPMB Device Configuration Block Data Structure.
+// (ref. NVMe Base spec. v2.0 Figure 460).
+//
+typedef struct {
+ UINT8 BPPEnable; /* Boot Partition Protection Enabled */
+ UINT8 BPLock; /* Boot Partition Lock */
+ UINT8 NameSpaceWrP; /* Namespace Write Protection */
+ UINT8 Rsvd1[509]; /* Reserved as of Nvm Express 2.0 Spec */
+} NVME_RPMB_DCB;
+
+//
+// RPMB Request and Response Message Types.
+// (ref. NVMe Base spec. v2.0 Figure 461).
+//
+#define NVME_RPMB_AUTHKEY_PROGRAM 0x0001
+#define NVME_RPMB_COUNTER_READ 0x0002
+#define NVME_RPMB_AUTHDATA_WRITE 0x0003
+#define NVME_RPMB_AUTHDATA_READ 0x0004
+#define NVME_RPMB_RESULT_READ 0x0005
+#define NVME_RPMB_DCB_WRITE 0x0006
+#define NVME_RPMB_DCB_READ 0x0007
+#define NVME_RPMB_AUTHKEY_PROGRAM_RESPONSE 0x0100
+#define NVME_RPMB_COUNTER_READ_RESPONSE 0x0200
+#define NVME_RPMB_AUTHDATA_WRITE_RESPONSE 0x0300
+#define NVME_RPMB_AUTHDATA_READ_RESPONSE 0x0400
+#define NVME_RPMB_DCB_WRITE_RESPONSE 0x0600
+#define NVME_RPMB_DCB_READ_RESPONSE 0x0700
+
+//
+// RPMB Operation Result.
+// (ref. NVMe Base spec. v2.0 Figure 462).
+//
+#define NVME_RPMB_RESULT_SUCCESS 0x00
+#define NVME_RPMB_RESULT_GENERAL_FAILURE 0x01
+#define NVME_RPMB_RESULT_AHTHENTICATION_FAILURE 0x02
+#define NVME_RPMB_RESULT_COUNTER_FAILURE 0x03
+#define NVME_RPMB_RESULT_ADDRESS_FAILURE 0x04
+#define NVME_RPMB_RESULT_WRITE_FAILURE 0x05
+#define NVME_RPMB_RESULT_READ_FAILURE 0x06
+#define NVME_RPMB_RESULT_AUTHKEY_NOT_PROGRAMMED 0x07
+#define NVME_RPMB_RESULT_INVALID_DCB 0x08
+
+//
+// Get Log Page - Boot Partition Log Header.
+// (ref. NVMe Base spec. v2.0 Figure 262).
+//
+typedef struct {
+ UINT8 LogIdentifier; /* Log Identifier, shall be set to 15h */
+ UINT8 Rsvd1[3];
+ UINT32 Bpsz : 15; /* Boot Partition Size */
+ UINT32 Rsvd2 : 16;
+ UINT32 Abpid : 1; /* Active Boot Partition ID */
+ UINT8 Rsvd3[8];
+} NVME_BOOT_PARTITION_HEADER;
+
//
// NvmExpress Admin Identify Cmd
//
@@ -441,8 +566,8 @@ typedef struct {
//
// CDW 10
//
- UINT32 Cns:2;
- UINT32 Rsvd1:30;
+ UINT32 Cns : 2;
+ UINT32 Rsvd1 : 30;
} NVME_ADMIN_IDENTIFY;
//
@@ -452,16 +577,16 @@ typedef struct {
//
// CDW 10
//
- UINT32 Qid:16; /* Queue Identifier */
- UINT32 Qsize:16; /* Queue Size */
+ UINT32 Qid : 16; /* Queue Identifier */
+ UINT32 Qsize : 16; /* Queue Size */
//
// CDW 11
//
- UINT32 Pc:1; /* Physically Contiguous */
- UINT32 Ien:1; /* Interrupts Enabled */
- UINT32 Rsvd1:14; /* reserved as of Nvm Express 1.1 Spec */
- UINT32 Iv:16; /* Interrupt Vector for MSI-X or MSI*/
+ UINT32 Pc : 1; /* Physically Contiguous */
+ UINT32 Ien : 1; /* Interrupts Enabled */
+ UINT32 Rsvd1 : 14; /* reserved as of Nvm Express 1.1 Spec */
+ UINT32 Iv : 16; /* Interrupt Vector for MSI-X or MSI*/
} NVME_ADMIN_CRIOCQ;
//
@@ -471,16 +596,16 @@ typedef struct {
//
// CDW 10
//
- UINT32 Qid:16; /* Queue Identifier */
- UINT32 Qsize:16; /* Queue Size */
+ UINT32 Qid : 16; /* Queue Identifier */
+ UINT32 Qsize : 16; /* Queue Size */
//
// CDW 11
//
- UINT32 Pc:1; /* Physically Contiguous */
- UINT32 Qprio:2; /* Queue Priority */
- UINT32 Rsvd1:13; /* Reserved as of Nvm Express 1.1 Spec */
- UINT32 Cqid:16; /* Completion Queue ID */
+ UINT32 Pc : 1; /* Physically Contiguous */
+ UINT32 Qprio : 2; /* Queue Priority */
+ UINT32 Rsvd1 : 13; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT32 Cqid : 16; /* Completion Queue ID */
} NVME_ADMIN_CRIOSQ;
//
@@ -490,8 +615,8 @@ typedef struct {
//
// CDW 10
//
- UINT16 Qid;
- UINT16 Rsvd1;
+ UINT16 Qid;
+ UINT16 Rsvd1;
} NVME_ADMIN_DEIOCQ;
//
@@ -501,8 +626,8 @@ typedef struct {
//
// CDW 10
//
- UINT16 Qid;
- UINT16 Rsvd1;
+ UINT16 Qid;
+ UINT16 Rsvd1;
} NVME_ADMIN_DEIOSQ;
//
@@ -512,8 +637,8 @@ typedef struct {
//
// CDW 10
//
- UINT32 Sqid:16; /* Submission Queue identifier */
- UINT32 Cid:16; /* Command Identifier */
+ UINT32 Sqid : 16; /* Submission Queue identifier */
+ UINT32 Cid : 16; /* Command Identifier */
} NVME_ADMIN_ABORT;
//
@@ -523,9 +648,9 @@ typedef struct {
//
// CDW 10
//
- UINT32 Fs:3; /* Submission Queue identifier */
- UINT32 Aa:2; /* Command Identifier */
- UINT32 Rsvd1:27;
+ UINT32 Fs : 3; /* Submission Queue identifier */
+ UINT32 Aa : 2; /* Command Identifier */
+ UINT32 Rsvd1 : 27;
} NVME_ADMIN_FIRMWARE_ACTIVATE;
//
@@ -535,11 +660,11 @@ typedef struct {
//
// CDW 10
//
- UINT32 Numd; /* Number of Dwords */
+ UINT32 Numd; /* Number of Dwords */
//
// CDW 11
//
- UINT32 Ofst; /* Offset */
+ UINT32 Ofst; /* Offset */
} NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;
//
@@ -549,9 +674,9 @@ typedef struct {
//
// CDW 10
//
- UINT32 Fid:8; /* Feature Identifier */
- UINT32 Sel:3; /* Select */
- UINT32 Rsvd1:21;
+ UINT32 Fid : 8; /* Feature Identifier */
+ UINT32 Sel : 3; /* Select */
+ UINT32 Rsvd1 : 21;
} NVME_ADMIN_GET_FEATURES;
//
@@ -561,13 +686,14 @@ typedef struct {
//
// CDW 10
//
- UINT32 Lid:8; /* Log Page Identifier */
- #define LID_ERROR_INFO 0x1
- #define LID_SMART_INFO 0x2
- #define LID_FW_SLOT_INFO 0x3
- UINT32 Rsvd1:8;
- UINT32 Numd:12; /* Number of Dwords */
- UINT32 Rsvd2:4; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT32 Lid : 8; /* Log Page Identifier */
+ #define LID_ERROR_INFO 0x1
+ #define LID_SMART_INFO 0x2
+ #define LID_FW_SLOT_INFO 0x3
+ #define LID_BP_INFO 0x15
+ UINT32 Rsvd1 : 8;
+ UINT32 Numd : 12; /* Number of Dwords */
+ UINT32 Rsvd2 : 4; /* Reserved as of Nvm Express 1.1 Spec */
} NVME_ADMIN_GET_LOG_PAGE;
//
@@ -577,9 +703,9 @@ typedef struct {
//
// CDW 10
//
- UINT32 Fid:8; /* Feature Identifier */
- UINT32 Rsvd1:23;
- UINT32 Sv:1; /* Save */
+ UINT32 Fid : 8; /* Feature Identifier */
+ UINT32 Rsvd1 : 23;
+ UINT32 Sv : 1; /* Save */
} NVME_ADMIN_SET_FEATURES;
//
@@ -589,12 +715,12 @@ typedef struct {
//
// CDW 10
//
- UINT32 Lbaf:4; /* LBA Format */
- UINT32 Ms:1; /* Metadata Settings */
- UINT32 Pi:3; /* Protection Information */
- UINT32 Pil:1; /* Protection Information Location */
- UINT32 Ses:3; /* Secure Erase Settings */
- UINT32 Rsvd1:20;
+ UINT32 Lbaf : 4; /* LBA Format */
+ UINT32 Ms : 1; /* Metadata Settings */
+ UINT32 Pi : 3; /* Protection Information */
+ UINT32 Pil : 1; /* Protection Information Location */
+ UINT32 Ses : 3; /* Secure Erase Settings */
+ UINT32 Rsvd1 : 20;
} NVME_ADMIN_FORMAT_NVM;
//
@@ -604,13 +730,13 @@ typedef struct {
//
// CDW 10
//
- UINT32 Rsvd1:8;
- UINT32 Spsp:16; /* SP Specific */
- UINT32 Secp:8; /* Security Protocol */
+ UINT32 Rsvd1 : 8;
+ UINT32 Spsp : 16; /* SP Specific */
+ UINT32 Secp : 8; /* Security Protocol */
//
// CDW 11
//
- UINT32 Al; /* Allocation Length */
+ UINT32 Al; /* Allocation Length */
} NVME_ADMIN_SECURITY_RECEIVE;
//
@@ -620,13 +746,13 @@ typedef struct {
//
// CDW 10
//
- UINT32 Rsvd1:8;
- UINT32 Spsp:16; /* SP Specific */
- UINT32 Secp:8; /* Security Protocol */
+ UINT32 Rsvd1 : 8;
+ UINT32 Spsp : 16; /* SP Specific */
+ UINT32 Secp : 8; /* Security Protocol */
//
// CDW 11
//
- UINT32 Tl; /* Transfer Length */
+ UINT32 Tl; /* Transfer Length */
} NVME_ADMIN_SECURITY_SEND;
typedef union {
@@ -647,18 +773,18 @@ typedef union {
} NVME_ADMIN_CMD;
typedef struct {
- UINT32 Cdw10;
- UINT32 Cdw11;
- UINT32 Cdw12;
- UINT32 Cdw13;
- UINT32 Cdw14;
- UINT32 Cdw15;
+ UINT32 Cdw10;
+ UINT32 Cdw11;
+ UINT32 Cdw12;
+ UINT32 Cdw13;
+ UINT32 Cdw14;
+ UINT32 Cdw15;
} NVME_RAW;
typedef union {
- NVME_ADMIN_CMD Admin; // Union of Admin commands
- NVME_CMD Nvm; // Union of Nvm commands
- NVME_RAW Raw;
+ NVME_ADMIN_CMD Admin; // Union of Admin commands
+ NVME_CMD Nvm; // Union of Nvm commands
+ NVME_RAW Raw;
} NVME_PAYLOAD;
//
@@ -668,34 +794,33 @@ typedef struct {
//
// CDW 0, Common to all commands
//
- UINT8 Opc; // Opcode
- UINT8 Fuse:2; // Fused Operation
- UINT8 Rsvd1:5;
- UINT8 Psdt:1; // PRP or SGL for Data Transfer
- UINT16 Cid; // Command Identifier
+ UINT8 Opc; // Opcode
+ UINT8 Fuse : 2; // Fused Operation
+ UINT8 Rsvd1 : 5;
+ UINT8 Psdt : 1; // PRP or SGL for Data Transfer
+ UINT16 Cid; // Command Identifier
//
// CDW 1
//
- UINT32 Nsid; // Namespace Identifier
+ UINT32 Nsid; // Namespace Identifier
//
// CDW 2,3
//
- UINT64 Rsvd2;
+ UINT64 Rsvd2;
//
// CDW 4,5
//
- UINT64 Mptr; // Metadata Pointer
+ UINT64 Mptr; // Metadata Pointer
//
// CDW 6-9
//
- UINT64 Prp[2]; // First and second PRP entries
-
- NVME_PAYLOAD Payload;
+ UINT64 Prp[2]; // First and second PRP entries
+ NVME_PAYLOAD Payload;
} NVME_SQ;
//
@@ -705,71 +830,71 @@ typedef struct {
//
// CDW 0
//
- UINT32 Dword0;
+ UINT32 Dword0;
//
// CDW 1
//
- UINT32 Rsvd1;
+ UINT32 Rsvd1;
//
// CDW 2
//
- UINT16 Sqhd; // Submission Queue Head Pointer
- UINT16 Sqid; // Submission Queue Identifier
+ UINT16 Sqhd; // Submission Queue Head Pointer
+ UINT16 Sqid; // Submission Queue Identifier
//
// CDW 3
//
- UINT16 Cid; // Command Identifier
- UINT16 Pt:1; // Phase Tag
- UINT16 Sc:8; // Status Code
- UINT16 Sct:3; // Status Code Type
- UINT16 Rsvd2:2;
- UINT16 Mo:1; // More
- UINT16 Dnr:1; // Do Not Retry
+ UINT16 Cid; // Command Identifier
+ UINT16 Pt : 1; // Phase Tag
+ UINT16 Sc : 8; // Status Code
+ UINT16 Sct : 3; // Status Code Type
+ UINT16 Rsvd2 : 2;
+ UINT16 Mo : 1; // More
+ UINT16 Dnr : 1; // Do Not Retry
} NVME_CQ;
//
// Nvm Express Admin cmd opcodes
//
-#define NVME_ADMIN_DEIOSQ_CMD 0x00
-#define NVME_ADMIN_CRIOSQ_CMD 0x01
-#define NVME_ADMIN_GET_LOG_PAGE_CMD 0x02
-#define NVME_ADMIN_DEIOCQ_CMD 0x04
-#define NVME_ADMIN_CRIOCQ_CMD 0x05
-#define NVME_ADMIN_IDENTIFY_CMD 0x06
-#define NVME_ADMIN_ABORT_CMD 0x08
-#define NVME_ADMIN_SET_FEATURES_CMD 0x09
-#define NVME_ADMIN_GET_FEATURES_CMD 0x0A
-#define NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD 0x0C
-#define NVME_ADMIN_NAMESACE_MANAGEMENT_CMD 0x0D
-#define NVME_ADMIN_FW_COMMIT_CMD 0x10
-#define NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD 0x11
-#define NVME_ADMIN_NAMESACE_ATTACHMENT_CMD 0x15
-#define NVME_ADMIN_FORMAT_NVM_CMD 0x80
-#define NVME_ADMIN_SECURITY_SEND_CMD 0x81
-#define NVME_ADMIN_SECURITY_RECEIVE_CMD 0x82
+#define NVME_ADMIN_DEIOSQ_CMD 0x00
+#define NVME_ADMIN_CRIOSQ_CMD 0x01
+#define NVME_ADMIN_GET_LOG_PAGE_CMD 0x02
+#define NVME_ADMIN_DEIOCQ_CMD 0x04
+#define NVME_ADMIN_CRIOCQ_CMD 0x05
+#define NVME_ADMIN_IDENTIFY_CMD 0x06
+#define NVME_ADMIN_ABORT_CMD 0x08
+#define NVME_ADMIN_SET_FEATURES_CMD 0x09
+#define NVME_ADMIN_GET_FEATURES_CMD 0x0A
+#define NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD 0x0C
+#define NVME_ADMIN_NAMESACE_MANAGEMENT_CMD 0x0D
+#define NVME_ADMIN_FW_COMMIT_CMD 0x10
+#define NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD 0x11
+#define NVME_ADMIN_NAMESACE_ATTACHMENT_CMD 0x15
+#define NVME_ADMIN_FORMAT_NVM_CMD 0x80
+#define NVME_ADMIN_SECURITY_SEND_CMD 0x81
+#define NVME_ADMIN_SECURITY_RECEIVE_CMD 0x82
-#define NVME_IO_FLUSH_OPC 0
-#define NVME_IO_WRITE_OPC 1
-#define NVME_IO_READ_OPC 2
+#define NVME_IO_FLUSH_OPC 0
+#define NVME_IO_WRITE_OPC 1
+#define NVME_IO_READ_OPC 2
typedef enum {
DeleteIOSubmissionQueueOpcode = NVME_ADMIN_DEIOSQ_CMD,
CreateIOSubmissionQueueOpcode = NVME_ADMIN_CRIOSQ_CMD,
- GetLogPageOpcode = NVME_ADMIN_GET_LOG_PAGE_CMD,
+ GetLogPageOpcode = NVME_ADMIN_GET_LOG_PAGE_CMD,
DeleteIOCompletionQueueOpcode = NVME_ADMIN_DEIOCQ_CMD,
CreateIOCompletionQueueOpcode = NVME_ADMIN_CRIOCQ_CMD,
- IdentifyOpcode = NVME_ADMIN_IDENTIFY_CMD,
- AbortOpcode = NVME_ADMIN_ABORT_CMD,
- SetFeaturesOpcode = NVME_ADMIN_SET_FEATURES_CMD,
- GetFeaturesOpcode = NVME_ADMIN_GET_FEATURES_CMD,
- AsyncEventRequestOpcode = NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD,
- NamespaceManagementOpcode = NVME_ADMIN_NAMESACE_MANAGEMENT_CMD,
- FirmwareCommitOpcode = NVME_ADMIN_FW_COMMIT_CMD,
- FirmwareImageDownloadOpcode = NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD,
- NamespaceAttachmentOpcode = NVME_ADMIN_NAMESACE_ATTACHMENT_CMD,
- FormatNvmOpcode = NVME_ADMIN_FORMAT_NVM_CMD,
- SecuritySendOpcode = NVME_ADMIN_SECURITY_SEND_CMD,
- SecurityReceiveOpcode = NVME_ADMIN_SECURITY_RECEIVE_CMD
+ IdentifyOpcode = NVME_ADMIN_IDENTIFY_CMD,
+ AbortOpcode = NVME_ADMIN_ABORT_CMD,
+ SetFeaturesOpcode = NVME_ADMIN_SET_FEATURES_CMD,
+ GetFeaturesOpcode = NVME_ADMIN_GET_FEATURES_CMD,
+ AsyncEventRequestOpcode = NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD,
+ NamespaceManagementOpcode = NVME_ADMIN_NAMESACE_MANAGEMENT_CMD,
+ FirmwareCommitOpcode = NVME_ADMIN_FW_COMMIT_CMD,
+ FirmwareImageDownloadOpcode = NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD,
+ NamespaceAttachmentOpcode = NVME_ADMIN_NAMESACE_ATTACHMENT_CMD,
+ FormatNvmOpcode = NVME_ADMIN_FORMAT_NVM_CMD,
+ SecuritySendOpcode = NVME_ADMIN_SECURITY_SEND_CMD,
+ SecurityReceiveOpcode = NVME_ADMIN_SECURITY_RECEIVE_CMD
} NVME_ADMIN_COMMAND_OPCODE;
//
@@ -777,9 +902,9 @@ typedef enum {
// (ref. spec. v1.1 figure 82).
//
typedef enum {
-IdentifyNamespaceCns = 0x0,
-IdentifyControllerCns = 0x1,
-IdentifyActiveNsListCns = 0x2
+ IdentifyNamespaceCns = 0x0,
+ IdentifyControllerCns = 0x1,
+ IdentifyActiveNsListCns = 0x2
} NVME_ADMIN_IDENTIFY_CNS;
//
@@ -787,9 +912,9 @@ IdentifyActiveNsListCns = 0x2
// (ref. spec. 1.1 figure 60).
//
typedef enum {
- ActivateActionReplace = 0x0,
+ ActivateActionReplace = 0x0,
ActivateActionReplaceActivate = 0x1,
- ActivateActionActivate = 0x2
+ ActivateActionActivate = 0x2
} NVME_FW_ACTIVATE_ACTION;
//
@@ -798,13 +923,13 @@ typedef enum {
//
typedef enum {
FirmwareSlotCtrlChooses = 0x0,
- FirmwareSlot1 = 0x1,
- FirmwareSlot2 = 0x2,
- FirmwareSlot3 = 0x3,
- FirmwareSlot4 = 0x4,
- FirmwareSlot5 = 0x5,
- FirmwareSlot6 = 0x6,
- FirmwareSlot7 = 0x7
+ FirmwareSlot1 = 0x1,
+ FirmwareSlot2 = 0x2,
+ FirmwareSlot3 = 0x3,
+ FirmwareSlot4 = 0x4,
+ FirmwareSlot5 = 0x5,
+ FirmwareSlot6 = 0x6,
+ FirmwareSlot7 = 0x7
} NVME_FW_ACTIVATE_SLOT;
//
@@ -812,8 +937,8 @@ typedef enum {
// (ref. spec. v1.1 Figure 73).
//
typedef enum {
- ErrorInfoLogID = LID_ERROR_INFO,
- SmartHealthInfoLogID = LID_SMART_INFO,
+ ErrorInfoLogID = LID_ERROR_INFO,
+ SmartHealthInfoLogID = LID_SMART_INFO,
FirmwareSlotInfoLogID = LID_FW_SLOT_INFO
} NVME_LOG_ID;
@@ -825,13 +950,13 @@ typedef struct {
//
// Indicates the firmware slot from which the actively running firmware revision was loaded.
//
- UINT8 ActivelyRunningFwSlot:3;
- UINT8 :1;
+ UINT8 ActivelyRunningFwSlot : 3;
+ UINT8 : 1;
//
// Indicates the firmware slot that is going to be activated at the next controller reset. If this field is 0h, then the controller does not indicate the firmware slot that is going to be activated at the next controller reset.
//
- UINT8 NextActiveFwSlot:3;
- UINT8 :1;
+ UINT8 NextActiveFwSlot : 3;
+ UINT8 : 1;
} NVME_ACTIVE_FW_INFO;
//
@@ -841,14 +966,14 @@ typedef struct {
typedef struct {
//
// Specifies information about the active firmware revision.
- //s
- NVME_ACTIVE_FW_INFO ActiveFwInfo;
- UINT8 Reserved1[7];
+ // s
+ NVME_ACTIVE_FW_INFO ActiveFwInfo;
+ UINT8 Reserved1[7];
//
// Contains the revision of the firmware downloaded to firmware slot 1/7. If no valid firmware revision is present or if this slot is unsupported, all zeros shall be returned.
//
- CHAR8 FwRevisionSlot[7][8];
- UINT8 Reserved2[448];
+ CHAR8 FwRevisionSlot[7][8];
+ UINT8 Reserved2[448];
} NVME_FW_SLOT_INFO_LOG;
//
@@ -859,82 +984,82 @@ typedef struct {
//
// This field indicates critical warnings for the state of the controller.
//
- UINT8 CriticalWarningAvailableSpare:1;
- UINT8 CriticalWarningTemperature:1;
- UINT8 CriticalWarningReliability:1;
- UINT8 CriticalWarningMediaReadOnly:1;
- UINT8 CriticalWarningVolatileBackup:1;
- UINT8 CriticalWarningReserved:3;
+ UINT8 CriticalWarningAvailableSpare : 1;
+ UINT8 CriticalWarningTemperature : 1;
+ UINT8 CriticalWarningReliability : 1;
+ UINT8 CriticalWarningMediaReadOnly : 1;
+ UINT8 CriticalWarningVolatileBackup : 1;
+ UINT8 CriticalWarningReserved : 3;
//
// Contains a value corresponding to a temperature in degrees Kelvin that represents the current composite temperature of the controller and namespace(s) associated with that controller. The manner in which this value is computed is implementation specific and may not represent the actual temperature of any physical point in the NVM subsystem.
//
- UINT16 CompositeTemp;
+ UINT16 CompositeTemp;
//
// Contains a normalized percentage (0 to 100%) of the remaining spare capacity available.
//
- UINT8 AvailableSpare;
+ UINT8 AvailableSpare;
//
// When the Available Spare falls below the threshold indicated in this field, an asynchronous event completion may occur. The value is indicated as a normalized percentage (0 to 100%).
//
- UINT8 AvailableSpareThreshold;
+ UINT8 AvailableSpareThreshold;
//
// Contains a vendor specific estimate of the percentage of NVM subsystem life used based on the actual usage and the manufacturer's prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value is allowed to exceed 100. Percentages greater than 254 shall be represented as 255. This value shall be updated once per power-on hour (when the controller is not in a sleep state).
//
- UINT8 PercentageUsed;
- UINT8 Reserved1[26];
+ UINT8 PercentageUsed;
+ UINT8 Reserved1[26];
//
// Contains the number of 512 byte data units the host has read from the controller; this value does not include metadata.
//
- UINT8 DataUnitsRead[16];
+ UINT8 DataUnitsRead[16];
//
// Contains the number of 512 byte data units the host has written to the controller; this value does not include metadata.
//
- UINT8 DataUnitsWritten[16];
+ UINT8 DataUnitsWritten[16];
//
// Contains the number of read commands completed by the controller.
//
- UINT8 HostReadCommands[16];
+ UINT8 HostReadCommands[16];
//
// Contains the number of write commands completed by the controller.
//
- UINT8 HostWriteCommands[16];
+ UINT8 HostWriteCommands[16];
//
// Contains the amount of time the controller is busy with I/O commands. This value is reported in minutes.
//
- UINT8 ControllerBusyTime[16];
+ UINT8 ControllerBusyTime[16];
//
// Contains the number of power cycles.
//
- UINT8 PowerCycles[16];
+ UINT8 PowerCycles[16];
//
// Contains the number of power-on hours.
//
- UINT8 PowerOnHours[16];
+ UINT8 PowerOnHours[16];
//
// Contains the number of unsafe shutdowns.
//
- UINT8 UnsafeShutdowns[16];
+ UINT8 UnsafeShutdowns[16];
//
// Contains the number of occurrences where the controller detected an unrecovered data integrity error.
//
- UINT8 MediaAndDataIntegrityErrors[16];
+ UINT8 MediaAndDataIntegrityErrors[16];
//
// Contains the number of Error Information log entries over the life of the controller.
//
- UINT8 NumberErrorInformationLogEntries[16];
+ UINT8 NumberErrorInformationLogEntries[16];
//
// Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater than or equal to the Warning Composite Temperature Threshold (WCTEMP) field and less than the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.
//
- UINT32 WarningCompositeTemperatureTime;
+ UINT32 WarningCompositeTemperatureTime;
//
// Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.
//
- UINT32 CriticalCompositeTemperatureTime;
+ UINT32 CriticalCompositeTemperatureTime;
//
// Contains the current temperature in degrees Kelvin reported by the temperature sensor. An implementation that does not implement the temperature sensor reports a temperature of zero degrees Kelvin.
//
- UINT16 TemperatureSensor[8];
- UINT8 Reserved2[296];
+ UINT16 TemperatureSensor[8];
+ UINT8 Reserved2[296];
} NVME_SMART_HEALTH_INFO_LOG;
#pragma pack()
diff --git a/MdePkg/Include/IndustryStandard/Pci22.h b/MdePkg/Include/IndustryStandard/Pci22.h
index 69e15f7a..1d95e71c 100644
--- a/MdePkg/Include/IndustryStandard/Pci22.h
+++ b/MdePkg/Include/IndustryStandard/Pci22.h
@@ -27,16 +27,16 @@
/// Section 6.1, PCI Local Bus Specification, 2.2
///
typedef struct {
- UINT16 VendorId;
- UINT16 DeviceId;
- UINT16 Command;
- UINT16 Status;
- UINT8 RevisionID;
- UINT8 ClassCode[3];
- UINT8 CacheLineSize;
- UINT8 LatencyTimer;
- UINT8 HeaderType;
- UINT8 BIST;
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT16 Command;
+ UINT16 Status;
+ UINT8 RevisionID;
+ UINT8 ClassCode[3];
+ UINT8 CacheLineSize;
+ UINT8 LatencyTimer;
+ UINT8 HeaderType;
+ UINT8 BIST;
} PCI_DEVICE_INDEPENDENT_REGION;
///
@@ -44,18 +44,18 @@ typedef struct {
/// Section 6.1, PCI Local Bus Specification, 2.2
///
typedef struct {
- UINT32 Bar[6];
- UINT32 CISPtr;
- UINT16 SubsystemVendorID;
- UINT16 SubsystemID;
- UINT32 ExpansionRomBar;
- UINT8 CapabilityPtr;
- UINT8 Reserved1[3];
- UINT32 Reserved2;
- UINT8 InterruptLine;
- UINT8 InterruptPin;
- UINT8 MinGnt;
- UINT8 MaxLat;
+ UINT32 Bar[6];
+ UINT32 CISPtr;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemID;
+ UINT32 ExpansionRomBar;
+ UINT8 CapabilityPtr;
+ UINT8 Reserved1[3];
+ UINT32 Reserved2;
+ UINT8 InterruptLine;
+ UINT8 InterruptPin;
+ UINT8 MinGnt;
+ UINT8 MaxLat;
} PCI_DEVICE_HEADER_TYPE_REGION;
///
@@ -63,8 +63,8 @@ typedef struct {
/// Section 6.1, PCI Local Bus Specification, 2.2
///
typedef struct {
- PCI_DEVICE_INDEPENDENT_REGION Hdr;
- PCI_DEVICE_HEADER_TYPE_REGION Device;
+ PCI_DEVICE_INDEPENDENT_REGION Hdr;
+ PCI_DEVICE_HEADER_TYPE_REGION Device;
} PCI_TYPE00;
///
@@ -72,28 +72,28 @@ typedef struct {
/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
///
typedef struct {
- UINT32 Bar[2];
- UINT8 PrimaryBus;
- UINT8 SecondaryBus;
- UINT8 SubordinateBus;
- UINT8 SecondaryLatencyTimer;
- UINT8 IoBase;
- UINT8 IoLimit;
- UINT16 SecondaryStatus;
- UINT16 MemoryBase;
- UINT16 MemoryLimit;
- UINT16 PrefetchableMemoryBase;
- UINT16 PrefetchableMemoryLimit;
- UINT32 PrefetchableBaseUpper32;
- UINT32 PrefetchableLimitUpper32;
- UINT16 IoBaseUpper16;
- UINT16 IoLimitUpper16;
- UINT8 CapabilityPtr;
- UINT8 Reserved[3];
- UINT32 ExpansionRomBAR;
- UINT8 InterruptLine;
- UINT8 InterruptPin;
- UINT16 BridgeControl;
+ UINT32 Bar[2];
+ UINT8 PrimaryBus;
+ UINT8 SecondaryBus;
+ UINT8 SubordinateBus;
+ UINT8 SecondaryLatencyTimer;
+ UINT8 IoBase;
+ UINT8 IoLimit;
+ UINT16 SecondaryStatus;
+ UINT16 MemoryBase;
+ UINT16 MemoryLimit;
+ UINT16 PrefetchableMemoryBase;
+ UINT16 PrefetchableMemoryLimit;
+ UINT32 PrefetchableBaseUpper32;
+ UINT32 PrefetchableLimitUpper32;
+ UINT16 IoBaseUpper16;
+ UINT16 IoLimitUpper16;
+ UINT8 CapabilityPtr;
+ UINT8 Reserved[3];
+ UINT32 ExpansionRomBAR;
+ UINT8 InterruptLine;
+ UINT8 InterruptPin;
+ UINT16 BridgeControl;
} PCI_BRIDGE_CONTROL_REGISTER;
///
@@ -101,13 +101,13 @@ typedef struct {
/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
///
typedef struct {
- PCI_DEVICE_INDEPENDENT_REGION Hdr;
- PCI_BRIDGE_CONTROL_REGISTER Bridge;
+ PCI_DEVICE_INDEPENDENT_REGION Hdr;
+ PCI_BRIDGE_CONTROL_REGISTER Bridge;
} PCI_TYPE01;
typedef union {
- PCI_TYPE00 Device;
- PCI_TYPE01 Bridge;
+ PCI_TYPE00 Device;
+ PCI_TYPE01 Bridge;
} PCI_TYPE_GENERIC;
///
@@ -115,188 +115,188 @@ typedef union {
/// Section 4.5.1, PC Card Standard. 8.0
///
typedef struct {
- UINT32 CardBusSocketReg; ///< Cardbus Socket/ExCA Base
- UINT8 Cap_Ptr;
- UINT8 Reserved;
- UINT16 SecondaryStatus; ///< Secondary Status
- UINT8 PciBusNumber; ///< PCI Bus Number
- UINT8 CardBusBusNumber; ///< CardBus Bus Number
- UINT8 SubordinateBusNumber; ///< Subordinate Bus Number
- UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer
- UINT32 MemoryBase0; ///< Memory Base Register 0
- UINT32 MemoryLimit0; ///< Memory Limit Register 0
- UINT32 MemoryBase1;
- UINT32 MemoryLimit1;
- UINT32 IoBase0;
- UINT32 IoLimit0; ///< I/O Base Register 0
- UINT32 IoBase1; ///< I/O Limit Register 0
- UINT32 IoLimit1;
- UINT8 InterruptLine; ///< Interrupt Line
- UINT8 InterruptPin; ///< Interrupt Pin
- UINT16 BridgeControl; ///< Bridge Control
+ UINT32 CardBusSocketReg; ///< Cardbus Socket/ExCA Base
+ UINT8 Cap_Ptr;
+ UINT8 Reserved;
+ UINT16 SecondaryStatus; ///< Secondary Status
+ UINT8 PciBusNumber; ///< PCI Bus Number
+ UINT8 CardBusBusNumber; ///< CardBus Bus Number
+ UINT8 SubordinateBusNumber; ///< Subordinate Bus Number
+ UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer
+ UINT32 MemoryBase0; ///< Memory Base Register 0
+ UINT32 MemoryLimit0; ///< Memory Limit Register 0
+ UINT32 MemoryBase1;
+ UINT32 MemoryLimit1;
+ UINT32 IoBase0;
+ UINT32 IoLimit0; ///< I/O Base Register 0
+ UINT32 IoBase1; ///< I/O Limit Register 0
+ UINT32 IoLimit1;
+ UINT8 InterruptLine; ///< Interrupt Line
+ UINT8 InterruptPin; ///< Interrupt Pin
+ UINT16 BridgeControl; ///< Bridge Control
} PCI_CARDBUS_CONTROL_REGISTER;
//
// Definitions of PCI class bytes and manipulation macros.
//
-#define PCI_CLASS_OLD 0x00
-#define PCI_CLASS_OLD_OTHER 0x00
-#define PCI_CLASS_OLD_VGA 0x01
+#define PCI_CLASS_OLD 0x00
+#define PCI_CLASS_OLD_OTHER 0x00
+#define PCI_CLASS_OLD_VGA 0x01
-#define PCI_CLASS_MASS_STORAGE 0x01
-#define PCI_CLASS_MASS_STORAGE_SCSI 0x00
-#define PCI_CLASS_MASS_STORAGE_IDE 0x01
-#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
-#define PCI_CLASS_MASS_STORAGE_IPI 0x03
-#define PCI_CLASS_MASS_STORAGE_RAID 0x04
-#define PCI_CLASS_MASS_STORAGE_OTHER 0x80
+#define PCI_CLASS_MASS_STORAGE 0x01
+#define PCI_CLASS_MASS_STORAGE_SCSI 0x00
+#define PCI_CLASS_MASS_STORAGE_IDE 0x01
+#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
+#define PCI_CLASS_MASS_STORAGE_IPI 0x03
+#define PCI_CLASS_MASS_STORAGE_RAID 0x04
+#define PCI_CLASS_MASS_STORAGE_OTHER 0x80
-#define PCI_CLASS_NETWORK 0x02
-#define PCI_CLASS_NETWORK_ETHERNET 0x00
-#define PCI_CLASS_NETWORK_TOKENRING 0x01
-#define PCI_CLASS_NETWORK_FDDI 0x02
-#define PCI_CLASS_NETWORK_ATM 0x03
-#define PCI_CLASS_NETWORK_ISDN 0x04
-#define PCI_CLASS_NETWORK_OTHER 0x80
+#define PCI_CLASS_NETWORK 0x02
+#define PCI_CLASS_NETWORK_ETHERNET 0x00
+#define PCI_CLASS_NETWORK_TOKENRING 0x01
+#define PCI_CLASS_NETWORK_FDDI 0x02
+#define PCI_CLASS_NETWORK_ATM 0x03
+#define PCI_CLASS_NETWORK_ISDN 0x04
+#define PCI_CLASS_NETWORK_OTHER 0x80
-#define PCI_CLASS_DISPLAY 0x03
-#define PCI_CLASS_DISPLAY_VGA 0x00
-#define PCI_IF_VGA_VGA 0x00
-#define PCI_IF_VGA_8514 0x01
-#define PCI_CLASS_DISPLAY_XGA 0x01
-#define PCI_CLASS_DISPLAY_3D 0x02
-#define PCI_CLASS_DISPLAY_OTHER 0x80
+#define PCI_CLASS_DISPLAY 0x03
+#define PCI_CLASS_DISPLAY_VGA 0x00
+#define PCI_IF_VGA_VGA 0x00
+#define PCI_IF_VGA_8514 0x01
+#define PCI_CLASS_DISPLAY_XGA 0x01
+#define PCI_CLASS_DISPLAY_3D 0x02
+#define PCI_CLASS_DISPLAY_OTHER 0x80
-#define PCI_CLASS_MEDIA 0x04
-#define PCI_CLASS_MEDIA_VIDEO 0x00
-#define PCI_CLASS_MEDIA_AUDIO 0x01
-#define PCI_CLASS_MEDIA_TELEPHONE 0x02
-#define PCI_CLASS_MEDIA_OTHER 0x80
+#define PCI_CLASS_MEDIA 0x04
+#define PCI_CLASS_MEDIA_VIDEO 0x00
+#define PCI_CLASS_MEDIA_AUDIO 0x01
+#define PCI_CLASS_MEDIA_TELEPHONE 0x02
+#define PCI_CLASS_MEDIA_OTHER 0x80
-#define PCI_CLASS_MEMORY_CONTROLLER 0x05
-#define PCI_CLASS_MEMORY_RAM 0x00
-#define PCI_CLASS_MEMORY_FLASH 0x01
-#define PCI_CLASS_MEMORY_OTHER 0x80
+#define PCI_CLASS_MEMORY_CONTROLLER 0x05
+#define PCI_CLASS_MEMORY_RAM 0x00
+#define PCI_CLASS_MEMORY_FLASH 0x01
+#define PCI_CLASS_MEMORY_OTHER 0x80
-#define PCI_CLASS_BRIDGE 0x06
-#define PCI_CLASS_BRIDGE_HOST 0x00
-#define PCI_CLASS_BRIDGE_ISA 0x01
-#define PCI_CLASS_BRIDGE_EISA 0x02
-#define PCI_CLASS_BRIDGE_MCA 0x03
-#define PCI_CLASS_BRIDGE_P2P 0x04
-#define PCI_IF_BRIDGE_P2P 0x00
-#define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01
-#define PCI_CLASS_BRIDGE_PCMCIA 0x05
-#define PCI_CLASS_BRIDGE_NUBUS 0x06
-#define PCI_CLASS_BRIDGE_CARDBUS 0x07
-#define PCI_CLASS_BRIDGE_RACEWAY 0x08
-#define PCI_CLASS_BRIDGE_OTHER 0x80
-#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
+#define PCI_CLASS_BRIDGE 0x06
+#define PCI_CLASS_BRIDGE_HOST 0x00
+#define PCI_CLASS_BRIDGE_ISA 0x01
+#define PCI_CLASS_BRIDGE_EISA 0x02
+#define PCI_CLASS_BRIDGE_MCA 0x03
+#define PCI_CLASS_BRIDGE_P2P 0x04
+#define PCI_IF_BRIDGE_P2P 0x00
+#define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01
+#define PCI_CLASS_BRIDGE_PCMCIA 0x05
+#define PCI_CLASS_BRIDGE_NUBUS 0x06
+#define PCI_CLASS_BRIDGE_CARDBUS 0x07
+#define PCI_CLASS_BRIDGE_RACEWAY 0x08
+#define PCI_CLASS_BRIDGE_OTHER 0x80
+#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
-#define PCI_CLASS_SCC 0x07 ///< Simple communications controllers
-#define PCI_SUBCLASS_SERIAL 0x00
-#define PCI_IF_GENERIC_XT 0x00
-#define PCI_IF_16450 0x01
-#define PCI_IF_16550 0x02
-#define PCI_IF_16650 0x03
-#define PCI_IF_16750 0x04
-#define PCI_IF_16850 0x05
-#define PCI_IF_16950 0x06
-#define PCI_SUBCLASS_PARALLEL 0x01
-#define PCI_IF_PARALLEL_PORT 0x00
-#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
-#define PCI_IF_ECP_PARALLEL_PORT 0x02
-#define PCI_IF_1284_CONTROLLER 0x03
-#define PCI_IF_1284_DEVICE 0xFE
-#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
-#define PCI_SUBCLASS_MODEM 0x03
-#define PCI_IF_GENERIC_MODEM 0x00
-#define PCI_IF_16450_MODEM 0x01
-#define PCI_IF_16550_MODEM 0x02
-#define PCI_IF_16650_MODEM 0x03
-#define PCI_IF_16750_MODEM 0x04
-#define PCI_SUBCLASS_SCC_OTHER 0x80
+#define PCI_CLASS_SCC 0x07///< Simple communications controllers
+#define PCI_SUBCLASS_SERIAL 0x00
+#define PCI_IF_GENERIC_XT 0x00
+#define PCI_IF_16450 0x01
+#define PCI_IF_16550 0x02
+#define PCI_IF_16650 0x03
+#define PCI_IF_16750 0x04
+#define PCI_IF_16850 0x05
+#define PCI_IF_16950 0x06
+#define PCI_SUBCLASS_PARALLEL 0x01
+#define PCI_IF_PARALLEL_PORT 0x00
+#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
+#define PCI_IF_ECP_PARALLEL_PORT 0x02
+#define PCI_IF_1284_CONTROLLER 0x03
+#define PCI_IF_1284_DEVICE 0xFE
+#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
+#define PCI_SUBCLASS_MODEM 0x03
+#define PCI_IF_GENERIC_MODEM 0x00
+#define PCI_IF_16450_MODEM 0x01
+#define PCI_IF_16550_MODEM 0x02
+#define PCI_IF_16650_MODEM 0x03
+#define PCI_IF_16750_MODEM 0x04
+#define PCI_SUBCLASS_SCC_OTHER 0x80
-#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
-#define PCI_SUBCLASS_PIC 0x00
-#define PCI_IF_8259_PIC 0x00
-#define PCI_IF_ISA_PIC 0x01
-#define PCI_IF_EISA_PIC 0x02
-#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 byte none-prefetchable memory.
-#define PCI_IF_APIC_CONTROLLER2 0x20
-#define PCI_SUBCLASS_DMA 0x01
-#define PCI_IF_8237_DMA 0x00
-#define PCI_IF_ISA_DMA 0x01
-#define PCI_IF_EISA_DMA 0x02
-#define PCI_SUBCLASS_TIMER 0x02
-#define PCI_IF_8254_TIMER 0x00
-#define PCI_IF_ISA_TIMER 0x01
-#define PCI_IF_EISA_TIMER 0x02
-#define PCI_SUBCLASS_RTC 0x03
-#define PCI_IF_GENERIC_RTC 0x00
-#define PCI_IF_ISA_RTC 0x01
-#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller
-#define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80
+#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
+#define PCI_SUBCLASS_PIC 0x00
+#define PCI_IF_8259_PIC 0x00
+#define PCI_IF_ISA_PIC 0x01
+#define PCI_IF_EISA_PIC 0x02
+#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 byte none-prefetchable memory.
+#define PCI_IF_APIC_CONTROLLER2 0x20
+#define PCI_SUBCLASS_DMA 0x01
+#define PCI_IF_8237_DMA 0x00
+#define PCI_IF_ISA_DMA 0x01
+#define PCI_IF_EISA_DMA 0x02
+#define PCI_SUBCLASS_TIMER 0x02
+#define PCI_IF_8254_TIMER 0x00
+#define PCI_IF_ISA_TIMER 0x01
+#define PCI_IF_EISA_TIMER 0x02
+#define PCI_SUBCLASS_RTC 0x03
+#define PCI_IF_GENERIC_RTC 0x00
+#define PCI_IF_ISA_RTC 0x01
+#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller
+#define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80
-#define PCI_CLASS_INPUT_DEVICE 0x09
-#define PCI_SUBCLASS_KEYBOARD 0x00
-#define PCI_SUBCLASS_PEN 0x01
-#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
-#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
-#define PCI_SUBCLASS_GAMEPORT 0x04
-#define PCI_IF_GAMEPORT 0x00
-#define PCI_IF_GAMEPORT1 0x10
-#define PCI_SUBCLASS_INPUT_OTHER 0x80
+#define PCI_CLASS_INPUT_DEVICE 0x09
+#define PCI_SUBCLASS_KEYBOARD 0x00
+#define PCI_SUBCLASS_PEN 0x01
+#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
+#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
+#define PCI_SUBCLASS_GAMEPORT 0x04
+#define PCI_IF_GAMEPORT 0x00
+#define PCI_IF_GAMEPORT1 0x10
+#define PCI_SUBCLASS_INPUT_OTHER 0x80
-#define PCI_CLASS_DOCKING_STATION 0x0A
+#define PCI_CLASS_DOCKING_STATION 0x0A
#define PCI_SUBCLASS_DOCKING_GENERIC 0x00
#define PCI_SUBCLASS_DOCKING_OTHER 0x80
-#define PCI_CLASS_PROCESSOR 0x0B
-#define PCI_SUBCLASS_PROC_386 0x00
-#define PCI_SUBCLASS_PROC_486 0x01
-#define PCI_SUBCLASS_PROC_PENTIUM 0x02
-#define PCI_SUBCLASS_PROC_ALPHA 0x10
-#define PCI_SUBCLASS_PROC_POWERPC 0x20
-#define PCI_SUBCLASS_PROC_MIPS 0x30
-#define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor
+#define PCI_CLASS_PROCESSOR 0x0B
+#define PCI_SUBCLASS_PROC_386 0x00
+#define PCI_SUBCLASS_PROC_486 0x01
+#define PCI_SUBCLASS_PROC_PENTIUM 0x02
+#define PCI_SUBCLASS_PROC_ALPHA 0x10
+#define PCI_SUBCLASS_PROC_POWERPC 0x20
+#define PCI_SUBCLASS_PROC_MIPS 0x30
+#define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor
-#define PCI_CLASS_SERIAL 0x0C
-#define PCI_CLASS_SERIAL_FIREWIRE 0x00
-#define PCI_IF_1394 0x00
-#define PCI_IF_1394_OPEN_HCI 0x10
-#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
-#define PCI_CLASS_SERIAL_SSA 0x02
-#define PCI_CLASS_SERIAL_USB 0x03
-#define PCI_IF_UHCI 0x00
-#define PCI_IF_OHCI 0x10
-#define PCI_IF_USB_OTHER 0x80
-#define PCI_IF_USB_DEVICE 0xFE
-#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
-#define PCI_CLASS_SERIAL_SMB 0x05
+#define PCI_CLASS_SERIAL 0x0C
+#define PCI_CLASS_SERIAL_FIREWIRE 0x00
+#define PCI_IF_1394 0x00
+#define PCI_IF_1394_OPEN_HCI 0x10
+#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
+#define PCI_CLASS_SERIAL_SSA 0x02
+#define PCI_CLASS_SERIAL_USB 0x03
+#define PCI_IF_UHCI 0x00
+#define PCI_IF_OHCI 0x10
+#define PCI_IF_USB_OTHER 0x80
+#define PCI_IF_USB_DEVICE 0xFE
+#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
+#define PCI_CLASS_SERIAL_SMB 0x05
-#define PCI_CLASS_WIRELESS 0x0D
-#define PCI_SUBCLASS_IRDA 0x00
-#define PCI_SUBCLASS_IR 0x01
-#define PCI_SUBCLASS_RF 0x10
-#define PCI_SUBCLASS_WIRELESS_OTHER 0x80
+#define PCI_CLASS_WIRELESS 0x0D
+#define PCI_SUBCLASS_IRDA 0x00
+#define PCI_SUBCLASS_IR 0x01
+#define PCI_SUBCLASS_RF 0x10
+#define PCI_SUBCLASS_WIRELESS_OTHER 0x80
-#define PCI_CLASS_INTELLIGENT_IO 0x0E
+#define PCI_CLASS_INTELLIGENT_IO 0x0E
-#define PCI_CLASS_SATELLITE 0x0F
-#define PCI_SUBCLASS_TV 0x01
-#define PCI_SUBCLASS_AUDIO 0x02
-#define PCI_SUBCLASS_VOICE 0x03
-#define PCI_SUBCLASS_DATA 0x04
+#define PCI_CLASS_SATELLITE 0x0F
+#define PCI_SUBCLASS_TV 0x01
+#define PCI_SUBCLASS_AUDIO 0x02
+#define PCI_SUBCLASS_VOICE 0x03
+#define PCI_SUBCLASS_DATA 0x04
-#define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller
-#define PCI_SUBCLASS_NET_COMPUT 0x00
-#define PCI_SUBCLASS_ENTERTAINMENT 0x10
-#define PCI_SUBCLASS_SECURITY_OTHER 0x80
+#define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller
+#define PCI_SUBCLASS_NET_COMPUT 0x00
+#define PCI_SUBCLASS_ENTERTAINMENT 0x10
+#define PCI_SUBCLASS_SECURITY_OTHER 0x80
-#define PCI_CLASS_DPIO 0x11
-#define PCI_SUBCLASS_DPIO 0x00
-#define PCI_SUBCLASS_DPIO_OTHER 0x80
+#define PCI_CLASS_DPIO 0x11
+#define PCI_SUBCLASS_DPIO 0x00
+#define PCI_SUBCLASS_DPIO_OTHER 0x80
/**
Macro that checks whether the Base Class code of device matched.
@@ -308,7 +308,8 @@ typedef struct {
@retval FALSE Base Class code doesn't match the specified device.
**/
-#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
+#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
+
/**
Macro that checks whether the Base Class code and Sub-Class code of device matched.
@@ -320,7 +321,8 @@ typedef struct {
@retval FALSE Base Class code and Sub-Class code don't match the specified device.
**/
-#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
+#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
+
/**
Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.
@@ -333,7 +335,7 @@ typedef struct {
@retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device.
**/
-#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
+#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
/**
Macro that checks whether device is a display controller.
@@ -344,7 +346,8 @@ typedef struct {
@retval FALSE Device is not a display controller.
**/
-#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
+#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
+
/**
Macro that checks whether device is a VGA-compatible controller.
@@ -354,7 +357,8 @@ typedef struct {
@retval FALSE Device is not a VGA-compatible controller.
**/
-#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)
+#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)
+
/**
Macro that checks whether device is an 8514-compatible controller.
@@ -364,7 +368,8 @@ typedef struct {
@retval FALSE Device is not an 8514-compatible controller.
**/
-#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)
+#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)
+
/**
Macro that checks whether device is built before the Class Code field was defined.
@@ -374,7 +379,8 @@ typedef struct {
@retval FALSE Device is not an old device.
**/
-#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
+#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
+
/**
Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.
@@ -384,7 +390,8 @@ typedef struct {
@retval FALSE Device is not an old VGA-compatible device.
**/
-#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
+#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
+
/**
Macro that checks whether device is an IDE controller.
@@ -394,7 +401,8 @@ typedef struct {
@retval FALSE Device is not an IDE controller.
**/
-#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
+#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
+
/**
Macro that checks whether device is a SCSI bus controller.
@@ -404,7 +412,8 @@ typedef struct {
@retval FALSE Device is not a SCSI bus controller.
**/
-#define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)
+#define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)
+
/**
Macro that checks whether device is a RAID controller.
@@ -414,7 +423,8 @@ typedef struct {
@retval FALSE Device is not a RAID controller.
**/
-#define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)
+#define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)
+
/**
Macro that checks whether device is an ISA bridge.
@@ -424,7 +434,8 @@ typedef struct {
@retval FALSE Device is not an ISA bridge.
**/
-#define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)
+#define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)
+
/**
Macro that checks whether device is a PCI-to-PCI bridge.
@@ -434,7 +445,8 @@ typedef struct {
@retval FALSE Device is not a PCI-to-PCI bridge.
**/
-#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)
+#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)
+
/**
Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.
@@ -444,7 +456,8 @@ typedef struct {
@retval FALSE Device is not a Subtractive Decode PCI-to-PCI bridge.
**/
-#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)
+#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)
+
/**
Macro that checks whether device is a 16550-compatible serial controller.
@@ -454,7 +467,8 @@ typedef struct {
@retval FALSE Device is not a 16550-compatible serial controller.
**/
-#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
+#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
+
/**
Macro that checks whether device is a Universal Serial Bus controller.
@@ -464,19 +478,20 @@ typedef struct {
@retval FALSE Device is not a Universal Serial Bus controller.
**/
-#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
+#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
//
// the definition of Header Type
//
-#define HEADER_TYPE_DEVICE 0x00
-#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
-#define HEADER_TYPE_CARDBUS_BRIDGE 0x02
-#define HEADER_TYPE_MULTI_FUNCTION 0x80
+#define HEADER_TYPE_DEVICE 0x00
+#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
+#define HEADER_TYPE_CARDBUS_BRIDGE 0x02
+#define HEADER_TYPE_MULTI_FUNCTION 0x80
//
// Mask of Header type
//
-#define HEADER_LAYOUT_CODE 0x7f
+#define HEADER_LAYOUT_CODE 0x7f
+
/**
Macro that checks whether device is a PCI-PCI bridge.
@@ -486,7 +501,8 @@ typedef struct {
@retval FALSE Device is not a PCI-PCI bridge.
**/
-#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
+#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
+
/**
Macro that checks whether device is a CardBus bridge.
@@ -496,7 +512,8 @@ typedef struct {
@retval FALSE Device is not a CardBus bridge.
**/
-#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
+#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
+
/**
Macro that checks whether device is a multiple functions device.
@@ -506,38 +523,38 @@ typedef struct {
@retval FALSE Device is not a multiple functions device.
**/
-#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
+#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
///
/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecture Specification,
///
-#define PCI_BRIDGE_ROMBAR 0x38
+#define PCI_BRIDGE_ROMBAR 0x38
-#define PCI_MAX_BAR 0x0006
-#define PCI_MAX_CONFIG_OFFSET 0x0100
+#define PCI_MAX_BAR 0x0006
+#define PCI_MAX_CONFIG_OFFSET 0x0100
-#define PCI_VENDOR_ID_OFFSET 0x00
-#define PCI_DEVICE_ID_OFFSET 0x02
-#define PCI_COMMAND_OFFSET 0x04
-#define PCI_PRIMARY_STATUS_OFFSET 0x06
-#define PCI_REVISION_ID_OFFSET 0x08
-#define PCI_CLASSCODE_OFFSET 0x09
-#define PCI_CACHELINE_SIZE_OFFSET 0x0C
-#define PCI_LATENCY_TIMER_OFFSET 0x0D
-#define PCI_HEADER_TYPE_OFFSET 0x0E
-#define PCI_BIST_OFFSET 0x0F
-#define PCI_BASE_ADDRESSREG_OFFSET 0x10
-#define PCI_CARDBUS_CIS_OFFSET 0x28
-#define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id
-#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
-#define PCI_SID_OFFSET 0x2E ///< SubSystem ID
-#define PCI_SUBSYSTEM_ID_OFFSET 0x2E
-#define PCI_EXPANSION_ROM_BASE 0x30
-#define PCI_CAPBILITY_POINTER_OFFSET 0x34
-#define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register
-#define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register
-#define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register
-#define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register
+#define PCI_VENDOR_ID_OFFSET 0x00
+#define PCI_DEVICE_ID_OFFSET 0x02
+#define PCI_COMMAND_OFFSET 0x04
+#define PCI_PRIMARY_STATUS_OFFSET 0x06
+#define PCI_REVISION_ID_OFFSET 0x08
+#define PCI_CLASSCODE_OFFSET 0x09
+#define PCI_CACHELINE_SIZE_OFFSET 0x0C
+#define PCI_LATENCY_TIMER_OFFSET 0x0D
+#define PCI_HEADER_TYPE_OFFSET 0x0E
+#define PCI_BIST_OFFSET 0x0F
+#define PCI_BASE_ADDRESSREG_OFFSET 0x10
+#define PCI_CARDBUS_CIS_OFFSET 0x28
+#define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id
+#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
+#define PCI_SID_OFFSET 0x2E ///< SubSystem ID
+#define PCI_SUBSYSTEM_ID_OFFSET 0x2E
+#define PCI_EXPANSION_ROM_BASE 0x30
+#define PCI_CAPBILITY_POINTER_OFFSET 0x34
+#define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register
+#define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register
+#define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register
+#define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register
//
// defined in PCI-to-PCI Bridge Architecture Specification
@@ -552,35 +569,35 @@ typedef struct {
///
/// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
///
-#define PCI_INT_LINE_UNKNOWN 0xFF
+#define PCI_INT_LINE_UNKNOWN 0xFF
///
/// PCI Access Data Format
///
typedef union {
struct {
- UINT32 Reg : 8;
- UINT32 Func : 3;
- UINT32 Dev : 5;
- UINT32 Bus : 8;
- UINT32 Reserved : 7;
- UINT32 Enable : 1;
+ UINT32 Reg : 8;
+ UINT32 Func : 3;
+ UINT32 Dev : 5;
+ UINT32 Bus : 8;
+ UINT32 Reserved : 7;
+ UINT32 Enable : 1;
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_CONFIG_ACCESS_CF8;
#pragma pack()
-#define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001
-#define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002
-#define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004
-#define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008
-#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010
-#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020
-#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040
-#define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080
-#define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100
-#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200
+#define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001
+#define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002
+#define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004
+#define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008
+#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010
+#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020
+#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040
+#define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080
+#define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100
+#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200
//
// defined in PCI-to-PCI Bridge Architecture Specification
@@ -601,43 +618,43 @@ typedef union {
//
// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard
//
-#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080
-#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100
-#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200
-#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400
+#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080
+#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100
+#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200
+#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400
//
// Following are the PCI status control bit
//
-#define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010
-#define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020
-#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080
-#define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100
+#define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010
+#define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020
+#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080
+#define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100
///
/// defined in PC Card Standard
///
-#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
+#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
#pragma pack(1)
//
// PCI Capability List IDs and records
//
-#define EFI_PCI_CAPABILITY_ID_PMI 0x01
-#define EFI_PCI_CAPABILITY_ID_AGP 0x02
-#define EFI_PCI_CAPABILITY_ID_VPD 0x03
-#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
-#define EFI_PCI_CAPABILITY_ID_MSI 0x05
-#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
-#define EFI_PCI_CAPABILITY_ID_SHPC 0x0C
+#define EFI_PCI_CAPABILITY_ID_PMI 0x01
+#define EFI_PCI_CAPABILITY_ID_AGP 0x02
+#define EFI_PCI_CAPABILITY_ID_VPD 0x03
+#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
+#define EFI_PCI_CAPABILITY_ID_MSI 0x05
+#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
+#define EFI_PCI_CAPABILITY_ID_SHPC 0x0C
///
/// Capabilities List Header
/// Section 6.7, PCI Local Bus Specification, 2.2
///
typedef struct {
- UINT8 CapabilityID;
- UINT8 NextItemPtr;
+ UINT8 CapabilityID;
+ UINT8 NextItemPtr;
} EFI_PCI_CAPABILITY_HDR;
///
@@ -646,19 +663,19 @@ typedef struct {
///
typedef union {
struct {
- UINT16 Version : 3;
- UINT16 PmeClock : 1;
- UINT16 Reserved : 1;
- UINT16 DeviceSpecificInitialization : 1;
- UINT16 AuxCurrent : 3;
- UINT16 D1Support : 1;
- UINT16 D2Support : 1;
- UINT16 PmeSupport : 5;
+ UINT16 Version : 3;
+ UINT16 PmeClock : 1;
+ UINT16 Reserved : 1;
+ UINT16 DeviceSpecificInitialization : 1;
+ UINT16 AuxCurrent : 3;
+ UINT16 D1Support : 1;
+ UINT16 D2Support : 1;
+ UINT16 PmeSupport : 5;
} Bits;
- UINT16 Data;
+ UINT16 Data;
} EFI_PCI_PMC;
-#define EFI_PCI_PMC_D3_COLD_MASK (BIT15)
+#define EFI_PCI_PMC_D3_COLD_MASK (BIT15)
///
/// PMCSR - Power Management Control/Status
@@ -666,22 +683,22 @@ typedef union {
///
typedef union {
struct {
- UINT16 PowerState : 2;
- UINT16 ReservedForPciExpress : 1;
- UINT16 NoSoftReset : 1;
- UINT16 Reserved : 4;
- UINT16 PmeEnable : 1;
- UINT16 DataSelect : 4;
- UINT16 DataScale : 2;
- UINT16 PmeStatus : 1;
+ UINT16 PowerState : 2;
+ UINT16 ReservedForPciExpress : 1;
+ UINT16 NoSoftReset : 1;
+ UINT16 Reserved : 4;
+ UINT16 PmeEnable : 1;
+ UINT16 DataSelect : 4;
+ UINT16 DataScale : 2;
+ UINT16 PmeStatus : 1;
} Bits;
- UINT16 Data;
+ UINT16 Data;
} EFI_PCI_PMCSR;
-#define PCI_POWER_STATE_D0 0
-#define PCI_POWER_STATE_D1 1
-#define PCI_POWER_STATE_D2 2
-#define PCI_POWER_STATE_D3_HOT 3
+#define PCI_POWER_STATE_D0 0
+#define PCI_POWER_STATE_D1 1
+#define PCI_POWER_STATE_D2 2
+#define PCI_POWER_STATE_D3_HOT 3
///
/// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions
@@ -689,11 +706,11 @@ typedef union {
///
typedef union {
struct {
- UINT8 Reserved : 6;
- UINT8 B2B3 : 1;
- UINT8 BusPowerClockControl : 1;
+ UINT8 Reserved : 6;
+ UINT8 B2B3 : 1;
+ UINT8 BusPowerClockControl : 1;
} Bits;
- UINT8 Uint8;
+ UINT8 Uint8;
} EFI_PCI_PMCSR_BSE;
///
@@ -701,11 +718,11 @@ typedef union {
/// Section 3.2, PCI Power Management Interface Specification, Revision 1.2
///
typedef struct {
- EFI_PCI_CAPABILITY_HDR Hdr;
- EFI_PCI_PMC PMC;
- EFI_PCI_PMCSR PMCSR;
- EFI_PCI_PMCSR_BSE BridgeExtention;
- UINT8 Data;
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ EFI_PCI_PMC PMC;
+ EFI_PCI_PMCSR PMCSR;
+ EFI_PCI_PMCSR_BSE BridgeExtention;
+ UINT8 Data;
} EFI_PCI_CAPABILITY_PMI;
///
@@ -713,11 +730,11 @@ typedef struct {
/// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0
///
typedef struct {
- EFI_PCI_CAPABILITY_HDR Hdr;
- UINT8 Rev;
- UINT8 Reserved;
- UINT32 Status;
- UINT32 Command;
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT8 Rev;
+ UINT8 Reserved;
+ UINT32 Status;
+ UINT32 Command;
} EFI_PCI_CAPABILITY_AGP;
///
@@ -725,9 +742,9 @@ typedef struct {
/// Appendix I, PCI Local Bus Specification, 2.2
///
typedef struct {
- EFI_PCI_CAPABILITY_HDR Hdr;
- UINT16 AddrReg;
- UINT32 DataReg;
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 AddrReg;
+ UINT32 DataReg;
} EFI_PCI_CAPABILITY_VPD;
///
@@ -735,9 +752,9 @@ typedef struct {
/// Section 3.2.6, PCI-to-PCI Bridge Architecture Specification, Revision 1.2
///
typedef struct {
- EFI_PCI_CAPABILITY_HDR Hdr;
- UINT8 ExpnsSlotReg;
- UINT8 ChassisNo;
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT8 ExpnsSlotReg;
+ UINT8 ChassisNo;
} EFI_PCI_CAPABILITY_SLOTID;
///
@@ -745,10 +762,10 @@ typedef struct {
/// Section 6.8.1, PCI Local Bus Specification, 2.2
///
typedef struct {
- EFI_PCI_CAPABILITY_HDR Hdr;
- UINT16 MsgCtrlReg;
- UINT32 MsgAddrReg;
- UINT16 MsgDataReg;
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 MsgCtrlReg;
+ UINT32 MsgAddrReg;
+ UINT16 MsgDataReg;
} EFI_PCI_CAPABILITY_MSI32;
///
@@ -756,11 +773,11 @@ typedef struct {
/// Section 6.8.1, PCI Local Bus Specification, 2.2
///
typedef struct {
- EFI_PCI_CAPABILITY_HDR Hdr;
- UINT16 MsgCtrlReg;
- UINT32 MsgAddrRegLsdw;
- UINT32 MsgAddrRegMsdw;
- UINT16 MsgDataReg;
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 MsgCtrlReg;
+ UINT32 MsgAddrRegLsdw;
+ UINT32 MsgAddrRegMsdw;
+ UINT16 MsgDataReg;
} EFI_PCI_CAPABILITY_MSI64;
///
@@ -768,38 +785,38 @@ typedef struct {
/// CompactPCI Hot Swap Specification PICMG 2.1, R1.0
///
typedef struct {
- EFI_PCI_CAPABILITY_HDR Hdr;
+ EFI_PCI_CAPABILITY_HDR Hdr;
///
/// not finished - fields need to go here
///
} EFI_PCI_CAPABILITY_HOTPLUG;
-#define PCI_BAR_IDX0 0x00
-#define PCI_BAR_IDX1 0x01
-#define PCI_BAR_IDX2 0x02
-#define PCI_BAR_IDX3 0x03
-#define PCI_BAR_IDX4 0x04
-#define PCI_BAR_IDX5 0x05
+#define PCI_BAR_IDX0 0x00
+#define PCI_BAR_IDX1 0x01
+#define PCI_BAR_IDX2 0x02
+#define PCI_BAR_IDX3 0x03
+#define PCI_BAR_IDX4 0x04
+#define PCI_BAR_IDX5 0x05
///
/// EFI PCI Option ROM definitions
///
-#define EFI_ROOT_BRIDGE_LIST 'eprb'
-#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.
+#define EFI_ROOT_BRIDGE_LIST 'eprb'
+#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.
-#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
-#define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')
-#define PCI_CODE_TYPE_PCAT_IMAGE 0x00
-#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.
+#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
+#define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')
+#define PCI_CODE_TYPE_PCAT_IMAGE 0x00
+#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.
///
/// Standard PCI Expansion ROM Header
/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
///
typedef struct {
- UINT16 Signature; ///< 0xaa55
- UINT8 Reserved[0x16];
- UINT16 PcirOffset;
+ UINT16 Signature; ///< 0xaa55
+ UINT8 Reserved[0x16];
+ UINT16 PcirOffset;
} PCI_EXPANSION_ROM_HEADER;
///
@@ -807,11 +824,11 @@ typedef struct {
/// Section 6.3.3.1, PCI Local Bus Specification, 2.2
///
typedef struct {
- UINT16 Signature; ///< 0xaa55
- UINT8 Size512;
- UINT8 InitEntryPoint[3];
- UINT8 Reserved[0x12];
- UINT16 PcirOffset;
+ UINT16 Signature; ///< 0xaa55
+ UINT8 Size512;
+ UINT8 InitEntryPoint[3];
+ UINT8 Reserved[0x12];
+ UINT16 PcirOffset;
} EFI_LEGACY_EXPANSION_ROM_HEADER;
///
@@ -819,18 +836,18 @@ typedef struct {
/// Section 6.3.1.2, PCI Local Bus Specification, 2.2
///
typedef struct {
- UINT32 Signature; ///< "PCIR"
- UINT16 VendorId;
- UINT16 DeviceId;
- UINT16 Reserved0;
- UINT16 Length;
- UINT8 Revision;
- UINT8 ClassCode[3];
- UINT16 ImageLength;
- UINT16 CodeRevision;
- UINT8 CodeType;
- UINT8 Indicator;
- UINT16 Reserved1;
+ UINT32 Signature; ///< "PCIR"
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT16 Reserved0;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT8 ClassCode[3];
+ UINT16 ImageLength;
+ UINT16 CodeRevision;
+ UINT8 CodeType;
+ UINT8 Indicator;
+ UINT16 Reserved1;
} PCI_DATA_STRUCTURE;
///
@@ -838,22 +855,22 @@ typedef struct {
/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
///
typedef struct {
- UINT16 Signature; ///< 0xaa55
- UINT16 InitializationSize;
- UINT32 EfiSignature; ///< 0x0EF1
- UINT16 EfiSubsystem;
- UINT16 EfiMachineType;
- UINT16 CompressionType;
- UINT8 Reserved[8];
- UINT16 EfiImageHeaderOffset;
- UINT16 PcirOffset;
+ UINT16 Signature; ///< 0xaa55
+ UINT16 InitializationSize;
+ UINT32 EfiSignature; ///< 0x0EF1
+ UINT16 EfiSubsystem;
+ UINT16 EfiMachineType;
+ UINT16 CompressionType;
+ UINT8 Reserved[8];
+ UINT16 EfiImageHeaderOffset;
+ UINT16 PcirOffset;
} EFI_PCI_EXPANSION_ROM_HEADER;
typedef union {
- UINT8 *Raw;
- PCI_EXPANSION_ROM_HEADER *Generic;
- EFI_PCI_EXPANSION_ROM_HEADER *Efi;
- EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;
+ UINT8 *Raw;
+ PCI_EXPANSION_ROM_HEADER *Generic;
+ EFI_PCI_EXPANSION_ROM_HEADER *Efi;
+ EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;
} EFI_PCI_ROM_HEADER;
#pragma pack()
diff --git a/MdePkg/Include/IndustryStandard/Pci23.h b/MdePkg/Include/IndustryStandard/Pci23.h
index 0ce38eb8..bce5cd67 100644
--- a/MdePkg/Include/IndustryStandard/Pci23.h
+++ b/MdePkg/Include/IndustryStandard/Pci23.h
@@ -15,7 +15,7 @@
/// PCI_CLASS_MASS_STORAGE, Base Class 01h.
///
///@{
-#define PCI_CLASS_MASS_STORAGE_ATA 0x05
+#define PCI_CLASS_MASS_STORAGE_ATA 0x05
#define PCI_IF_MASS_STORAGE_SINGLE_DMA 0x20
#define PCI_IF_MASS_STORAGE_CHAINED_DMA 0x30
///@}
@@ -24,63 +24,63 @@
/// PCI_CLASS_NETWORK, Base Class 02h.
///
///@{
-#define PCI_CLASS_NETWORK_WORLDFIP 0x05
-#define PCI_CLASS_NETWORK_PICMG_MULTI_COMPUTING 0x06
+#define PCI_CLASS_NETWORK_WORLDFIP 0x05
+#define PCI_CLASS_NETWORK_PICMG_MULTI_COMPUTING 0x06
///@}
///
/// PCI_CLASS_BRIDGE, Base Class 06h.
///
///@{
-#define PCI_CLASS_BRIDGE_SEMI_TRANSPARENT_P2P 0x09
-#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_PRIMARY 0x40
-#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_SECONDARY 0x80
-#define PCI_CLASS_BRIDGE_INFINIBAND_TO_PCI 0x0A
+#define PCI_CLASS_BRIDGE_SEMI_TRANSPARENT_P2P 0x09
+#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_PRIMARY 0x40
+#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_SECONDARY 0x80
+#define PCI_CLASS_BRIDGE_INFINIBAND_TO_PCI 0x0A
///@}
///
/// PCI_CLASS_SCC, Base Class 07h.
///
///@{
-#define PCI_SUBCLASS_GPIB 0x04
-#define PCI_SUBCLASS_SMART_CARD 0x05
+#define PCI_SUBCLASS_GPIB 0x04
+#define PCI_SUBCLASS_SMART_CARD 0x05
///@}
///
/// PCI_CLASS_SERIAL, Base Class 0Ch.
///
///@{
-#define PCI_IF_EHCI 0x20
-#define PCI_CLASS_SERIAL_IB 0x06
-#define PCI_CLASS_SERIAL_IPMI 0x07
-#define PCI_IF_IPMI_SMIC 0x00
-#define PCI_IF_IPMI_KCS 0x01 ///< Keyboard Controller Style
-#define PCI_IF_IPMI_BT 0x02 ///< Block Transfer
-#define PCI_CLASS_SERIAL_SERCOS 0x08
-#define PCI_CLASS_SERIAL_CANBUS 0x09
+#define PCI_IF_EHCI 0x20
+#define PCI_CLASS_SERIAL_IB 0x06
+#define PCI_CLASS_SERIAL_IPMI 0x07
+#define PCI_IF_IPMI_SMIC 0x00
+#define PCI_IF_IPMI_KCS 0x01 ///< Keyboard Controller Style
+#define PCI_IF_IPMI_BT 0x02 ///< Block Transfer
+#define PCI_CLASS_SERIAL_SERCOS 0x08
+#define PCI_CLASS_SERIAL_CANBUS 0x09
///@}
///
/// PCI_CLASS_WIRELESS, Base Class 0Dh.
///
///@{
-#define PCI_SUBCLASS_BLUETOOTH 0x11
-#define PCI_SUBCLASS_BROADBAND 0x12
+#define PCI_SUBCLASS_BLUETOOTH 0x11
+#define PCI_SUBCLASS_BROADBAND 0x12
///@}
///
/// PCI_CLASS_DPIO, Base Class 11h.
///
///@{
-#define PCI_SUBCLASS_PERFORMANCE_COUNTERS 0x01
-#define PCI_SUBCLASS_COMMUNICATION_SYNCHRONIZATION 0x10
-#define PCI_SUBCLASS_MANAGEMENT_CARD 0x20
+#define PCI_SUBCLASS_PERFORMANCE_COUNTERS 0x01
+#define PCI_SUBCLASS_COMMUNICATION_SYNCHRONIZATION 0x10
+#define PCI_SUBCLASS_MANAGEMENT_CARD 0x20
///@}
///
/// defined in PCI Express Spec.
///
-#define PCI_EXP_MAX_CONFIG_OFFSET 0x1000
+#define PCI_EXP_MAX_CONFIG_OFFSET 0x1000
///
/// PCI Capability List IDs and records.
@@ -94,9 +94,9 @@
/// Section 7.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.
///
typedef struct {
- EFI_PCI_CAPABILITY_HDR Hdr;
- UINT16 CommandReg;
- UINT32 StatusReg;
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 CommandReg;
+ UINT32 StatusReg;
} EFI_PCI_CAPABILITY_PCIX;
///
@@ -104,11 +104,11 @@ typedef struct {
/// Section 8.6.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.
///
typedef struct {
- EFI_PCI_CAPABILITY_HDR Hdr;
- UINT16 SecStatusReg;
- UINT32 StatusReg;
- UINT32 SplitTransCtrlRegUp;
- UINT32 SplitTransCtrlRegDn;
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 SecStatusReg;
+ UINT32 StatusReg;
+ UINT32 SplitTransCtrlRegUp;
+ UINT32 SplitTransCtrlRegDn;
} EFI_PCI_CAPABILITY_PCIX_BRDG;
///
@@ -116,12 +116,12 @@ typedef struct {
/// Table H-1: Capability IDs, PCI Local Bus Specification, 2.3
///
typedef struct {
- EFI_PCI_CAPABILITY_HDR Hdr;
- UINT8 Length;
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT8 Length;
} EFI_PCI_CAPABILITY_VENDOR_HDR;
#pragma pack()
-#define PCI_CODE_TYPE_EFI_IMAGE 0x03
+#define PCI_CODE_TYPE_EFI_IMAGE 0x03
#endif
diff --git a/MdePkg/Include/IndustryStandard/Pci30.h b/MdePkg/Include/IndustryStandard/Pci30.h
index beefb1ae..d25ac292 100644
--- a/MdePkg/Include/IndustryStandard/Pci30.h
+++ b/MdePkg/Include/IndustryStandard/Pci30.h
@@ -9,24 +9,23 @@
#ifndef __PCI30_H__
#define __PCI30_H__
-
#include
///
/// PCI_CLASS_MASS_STORAGE, Base Class 01h.
///
///@{
-#define PCI_CLASS_MASS_STORAGE_SATADPA 0x06
-#define PCI_IF_MASS_STORAGE_SATA 0x00
-#define PCI_IF_MASS_STORAGE_AHCI 0x01
+#define PCI_CLASS_MASS_STORAGE_SATADPA 0x06
+#define PCI_IF_MASS_STORAGE_SATA 0x00
+#define PCI_IF_MASS_STORAGE_AHCI 0x01
///@}
///
/// PCI_CLASS_WIRELESS, Base Class 0Dh.
///
///@{
-#define PCI_SUBCLASS_ETHERNET_80211A 0x20
-#define PCI_SUBCLASS_ETHERNET_80211B 0x21
+#define PCI_SUBCLASS_ETHERNET_80211A 0x20
+#define PCI_SUBCLASS_ETHERNET_80211B 0x21
///@}
/**
@@ -38,7 +37,7 @@
@retval FALSE Device is not a SATA controller.
**/
-#define IS_PCI_SATADPA(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SATADPA)
+#define IS_PCI_SATADPA(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SATADPA)
///
/// PCI Capability List IDs and records
@@ -52,20 +51,20 @@
/// Section 5.1.2, PCI Firmware Specification, Revision 3.0
///
typedef struct {
- UINT32 Signature; ///< "PCIR"
- UINT16 VendorId;
- UINT16 DeviceId;
- UINT16 DeviceListOffset;
- UINT16 Length;
- UINT8 Revision;
- UINT8 ClassCode[3];
- UINT16 ImageLength;
- UINT16 CodeRevision;
- UINT8 CodeType;
- UINT8 Indicator;
- UINT16 MaxRuntimeImageLength;
- UINT16 ConfigUtilityCodeHeaderOffset;
- UINT16 DMTFCLPEntryPointOffset;
+ UINT32 Signature; ///< "PCIR"
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT16 DeviceListOffset;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT8 ClassCode[3];
+ UINT16 ImageLength;
+ UINT16 CodeRevision;
+ UINT8 CodeType;
+ UINT8 Indicator;
+ UINT16 MaxRuntimeImageLength;
+ UINT16 ConfigUtilityCodeHeaderOffset;
+ UINT16 DMTFCLPEntryPointOffset;
} PCI_3_0_DATA_STRUCTURE;
#pragma pack()
diff --git a/MdePkg/Include/IndustryStandard/PciCodeId.h b/MdePkg/Include/IndustryStandard/PciCodeId.h
index e5b63c3f..e7f0cfa3 100644
--- a/MdePkg/Include/IndustryStandard/PciCodeId.h
+++ b/MdePkg/Include/IndustryStandard/PciCodeId.h
@@ -10,70 +10,69 @@
#ifndef __PCI_CODE_ID_H__
#define __PCI_CODE_ID_H__
-
///
/// PCI_CLASS_MASS_STORAGE, Base Class 01h.
///
///@{
-#define PCI_IF_MASS_STORAGE_SCSI_VENDOR_SPECIFIC 0x00
-#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_PQI 0x11
-#define PCI_IF_MASS_STORAGE_SCSI_CONTROLLER_PQI 0x12
-#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_CONTROLLER_PQI 0x13
-#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_NVM_EXPRESS 0x21
-#define PCI_IF_MASS_STORAGE_SATA_SERIAL_BUS 0x02
-#define PCI_CLASS_MASS_STORAGE_SAS 0x07
-#define PCI_IF_MASS_STORAGE_SAS 0x00
-#define PCI_IF_MASS_STORAGE_SAS_SERIAL_BUS 0x01
-#define PCI_CLASS_MASS_STORAGE_SOLID_STATE 0x08
-#define PCI_IF_MASS_STORAGE_SOLID_STATE 0x00
-#define PCI_IF_MASS_STORAGE_SOLID_STATE_NVMHCI 0x01
-#define PCI_IF_MASS_STORAGE_SOLID_STATE_ENTERPRISE_NVMHCI 0x02
+#define PCI_IF_MASS_STORAGE_SCSI_VENDOR_SPECIFIC 0x00
+#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_PQI 0x11
+#define PCI_IF_MASS_STORAGE_SCSI_CONTROLLER_PQI 0x12
+#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_CONTROLLER_PQI 0x13
+#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_NVM_EXPRESS 0x21
+#define PCI_IF_MASS_STORAGE_SATA_SERIAL_BUS 0x02
+#define PCI_CLASS_MASS_STORAGE_SAS 0x07
+#define PCI_IF_MASS_STORAGE_SAS 0x00
+#define PCI_IF_MASS_STORAGE_SAS_SERIAL_BUS 0x01
+#define PCI_CLASS_MASS_STORAGE_SOLID_STATE 0x08
+#define PCI_IF_MASS_STORAGE_SOLID_STATE 0x00
+#define PCI_IF_MASS_STORAGE_SOLID_STATE_NVMHCI 0x01
+#define PCI_IF_MASS_STORAGE_SOLID_STATE_ENTERPRISE_NVMHCI 0x02
///@}
///
/// PCI_CLASS_NETWORK, Base Class 02h.
///
///@{
-#define PCI_CLASS_NETWORK_INFINIBAND 0x07
+#define PCI_CLASS_NETWORK_INFINIBAND 0x07
///@}
///
/// PCI_CLASS_MEDIA, Base Class 04h.
///
///@{
-#define PCI_CLASS_MEDIA_MIXED_MODE 0x03
+#define PCI_CLASS_MEDIA_MIXED_MODE 0x03
///@}
///
/// PCI_CLASS_BRIDGE, Base Class 06h.
///
///@{
-#define PCI_CLASS_BRIDGE_ADVANCED_SWITCHING_TO_PCI 0x0B
-#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_CUSTOM 0x00
-#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_ASI_SIG 0x01
+#define PCI_CLASS_BRIDGE_ADVANCED_SWITCHING_TO_PCI 0x0B
+#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_CUSTOM 0x00
+#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_ASI_SIG 0x01
///@}
///
/// PCI_CLASS_SYSTEM_PERIPHERAL, Base Class 08h.
///
///@{
-#define PCI_IF_HPET 0x03
-#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05
-#define PCI_SUBCLASS_IOMMU 0x06
+#define PCI_IF_HPET 0x03
+#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05
+#define PCI_SUBCLASS_IOMMU 0x06
///@}
///
/// PCI_CLASS_PROCESSOR, Base Class 0Bh.
///
///@{
-#define PCI_SUBCLASS_PROC_OTHER 0x80
+#define PCI_SUBCLASS_PROC_OTHER 0x80
///@}
///
/// PCI_CLASS_SERIAL, Base Class 0Ch.
///
///@{
-#define PCI_IF_XHCI 0x30
+#define PCI_IF_XHCI 0x30
#define PCI_CLASS_SERIAL_OTHER 0x80
///@}
@@ -81,7 +80,7 @@
/// PCI_CLASS_SATELLITE, Base Class 0Fh.
///
///@{
-#define PCI_SUBCLASS_SATELLITE_OTHER 0x80
+#define PCI_SUBCLASS_SATELLITE_OTHER 0x80
///@}
///
diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Include/IndustryStandard/PciExpress21.h
index dbe6349d..7b611c68 100644
--- a/MdePkg/Include/IndustryStandard/PciExpress21.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress21.h
@@ -26,7 +26,7 @@
@return The encode ECAM address.
**/
-#define PCI_ECAM_ADDRESS(Bus,Device,Function,Offset) \
+#define PCI_ECAM_ADDRESS(Bus, Device, Function, Offset) \
(((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
#pragma pack(1)
@@ -35,60 +35,60 @@
///
typedef union {
struct {
- UINT16 Version : 4;
- UINT16 DevicePortType : 4;
- UINT16 SlotImplemented : 1;
- UINT16 InterruptMessageNumber : 5;
- UINT16 Undefined : 1;
- UINT16 Reserved : 1;
+ UINT16 Version : 4;
+ UINT16 DevicePortType : 4;
+ UINT16 SlotImplemented : 1;
+ UINT16 InterruptMessageNumber : 5;
+ UINT16 Undefined : 1;
+ UINT16 Reserved : 1;
} Bits;
- UINT16 Uint16;
+ UINT16 Uint16;
} PCI_REG_PCIE_CAPABILITY;
-#define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT 0
-#define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT 1
-#define PCIE_DEVICE_PORT_TYPE_ROOT_PORT 4
-#define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT 5
-#define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT 6
-#define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE 7
-#define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE 8
-#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9
-#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10
+#define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT 0
+#define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT 1
+#define PCIE_DEVICE_PORT_TYPE_ROOT_PORT 4
+#define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT 5
+#define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT 6
+#define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE 7
+#define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE 8
+#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9
+#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10
typedef union {
struct {
- UINT32 MaxPayloadSize : 3;
- UINT32 PhantomFunctions : 2;
- UINT32 ExtendedTagField : 1;
- UINT32 EndpointL0sAcceptableLatency : 3;
- UINT32 EndpointL1AcceptableLatency : 3;
- UINT32 Undefined : 3;
- UINT32 RoleBasedErrorReporting : 1;
- UINT32 Reserved : 2;
- UINT32 CapturedSlotPowerLimitValue : 8;
- UINT32 CapturedSlotPowerLimitScale : 2;
- UINT32 FunctionLevelReset : 1;
- UINT32 Reserved2 : 3;
+ UINT32 MaxPayloadSize : 3;
+ UINT32 PhantomFunctions : 2;
+ UINT32 ExtendedTagField : 1;
+ UINT32 EndpointL0sAcceptableLatency : 3;
+ UINT32 EndpointL1AcceptableLatency : 3;
+ UINT32 Undefined : 3;
+ UINT32 RoleBasedErrorReporting : 1;
+ UINT32 Reserved : 2;
+ UINT32 CapturedSlotPowerLimitValue : 8;
+ UINT32 CapturedSlotPowerLimitScale : 2;
+ UINT32 FunctionLevelReset : 1;
+ UINT32 Reserved2 : 3;
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_REG_PCIE_DEVICE_CAPABILITY;
typedef union {
struct {
- UINT16 CorrectableError : 1;
- UINT16 NonFatalError : 1;
- UINT16 FatalError : 1;
- UINT16 UnsupportedRequest : 1;
- UINT16 RelaxedOrdering : 1;
- UINT16 MaxPayloadSize : 3;
- UINT16 ExtendedTagField : 1;
- UINT16 PhantomFunctions : 1;
- UINT16 AuxPower : 1;
- UINT16 NoSnoop : 1;
- UINT16 MaxReadRequestSize : 3;
- UINT16 BridgeConfigurationRetryOrFunctionLevelReset : 1;
+ UINT16 CorrectableError : 1;
+ UINT16 NonFatalError : 1;
+ UINT16 FatalError : 1;
+ UINT16 UnsupportedRequest : 1;
+ UINT16 RelaxedOrdering : 1;
+ UINT16 MaxPayloadSize : 3;
+ UINT16 ExtendedTagField : 1;
+ UINT16 PhantomFunctions : 1;
+ UINT16 AuxPower : 1;
+ UINT16 NoSnoop : 1;
+ UINT16 MaxReadRequestSize : 3;
+ UINT16 BridgeConfigurationRetryOrFunctionLevelReset : 1;
} Bits;
- UINT16 Uint16;
+ UINT16 Uint16;
} PCI_REG_PCIE_DEVICE_CONTROL;
#define PCIE_MAX_PAYLOAD_SIZE_128B 0
@@ -100,404 +100,404 @@ typedef union {
#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6
#define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7
-#define PCIE_MAX_READ_REQ_SIZE_128B 0
-#define PCIE_MAX_READ_REQ_SIZE_256B 1
-#define PCIE_MAX_READ_REQ_SIZE_512B 2
-#define PCIE_MAX_READ_REQ_SIZE_1024B 3
-#define PCIE_MAX_READ_REQ_SIZE_2048B 4
-#define PCIE_MAX_READ_REQ_SIZE_4096B 5
-#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
-#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
+#define PCIE_MAX_READ_REQ_SIZE_128B 0
+#define PCIE_MAX_READ_REQ_SIZE_256B 1
+#define PCIE_MAX_READ_REQ_SIZE_512B 2
+#define PCIE_MAX_READ_REQ_SIZE_1024B 3
+#define PCIE_MAX_READ_REQ_SIZE_2048B 4
+#define PCIE_MAX_READ_REQ_SIZE_4096B 5
+#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
+#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
typedef union {
struct {
- UINT16 CorrectableError : 1;
- UINT16 NonFatalError : 1;
- UINT16 FatalError : 1;
- UINT16 UnsupportedRequest : 1;
- UINT16 AuxPower : 1;
- UINT16 TransactionsPending : 1;
- UINT16 Reserved : 10;
+ UINT16 CorrectableError : 1;
+ UINT16 NonFatalError : 1;
+ UINT16 FatalError : 1;
+ UINT16 UnsupportedRequest : 1;
+ UINT16 AuxPower : 1;
+ UINT16 TransactionsPending : 1;
+ UINT16 Reserved : 10;
} Bits;
- UINT16 Uint16;
+ UINT16 Uint16;
} PCI_REG_PCIE_DEVICE_STATUS;
typedef union {
struct {
- UINT32 MaxLinkSpeed : 4;
- UINT32 MaxLinkWidth : 6;
- UINT32 Aspm : 2;
- UINT32 L0sExitLatency : 3;
- UINT32 L1ExitLatency : 3;
- UINT32 ClockPowerManagement : 1;
- UINT32 SurpriseDownError : 1;
- UINT32 DataLinkLayerLinkActive : 1;
- UINT32 LinkBandwidthNotification : 1;
- UINT32 AspmOptionalityCompliance : 1;
- UINT32 Reserved : 1;
- UINT32 PortNumber : 8;
+ UINT32 MaxLinkSpeed : 4;
+ UINT32 MaxLinkWidth : 6;
+ UINT32 Aspm : 2;
+ UINT32 L0sExitLatency : 3;
+ UINT32 L1ExitLatency : 3;
+ UINT32 ClockPowerManagement : 1;
+ UINT32 SurpriseDownError : 1;
+ UINT32 DataLinkLayerLinkActive : 1;
+ UINT32 LinkBandwidthNotification : 1;
+ UINT32 AspmOptionalityCompliance : 1;
+ UINT32 Reserved : 1;
+ UINT32 PortNumber : 8;
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_REG_PCIE_LINK_CAPABILITY;
-#define PCIE_LINK_ASPM_L0S BIT0
-#define PCIE_LINK_ASPM_L1 BIT1
+#define PCIE_LINK_ASPM_L0S BIT0
+#define PCIE_LINK_ASPM_L1 BIT1
typedef union {
struct {
- UINT16 AspmControl : 2;
- UINT16 Reserved : 1;
- UINT16 ReadCompletionBoundary : 1;
- UINT16 LinkDisable : 1;
- UINT16 RetrainLink : 1;
- UINT16 CommonClockConfiguration : 1;
- UINT16 ExtendedSynch : 1;
- UINT16 ClockPowerManagement : 1;
- UINT16 HardwareAutonomousWidthDisable : 1;
- UINT16 LinkBandwidthManagementInterrupt : 1;
- UINT16 LinkAutonomousBandwidthInterrupt : 1;
+ UINT16 AspmControl : 2;
+ UINT16 Reserved : 1;
+ UINT16 ReadCompletionBoundary : 1;
+ UINT16 LinkDisable : 1;
+ UINT16 RetrainLink : 1;
+ UINT16 CommonClockConfiguration : 1;
+ UINT16 ExtendedSynch : 1;
+ UINT16 ClockPowerManagement : 1;
+ UINT16 HardwareAutonomousWidthDisable : 1;
+ UINT16 LinkBandwidthManagementInterrupt : 1;
+ UINT16 LinkAutonomousBandwidthInterrupt : 1;
} Bits;
- UINT16 Uint16;
+ UINT16 Uint16;
} PCI_REG_PCIE_LINK_CONTROL;
typedef union {
struct {
- UINT16 CurrentLinkSpeed : 4;
- UINT16 NegotiatedLinkWidth : 6;
- UINT16 Undefined : 1;
- UINT16 LinkTraining : 1;
- UINT16 SlotClockConfiguration : 1;
- UINT16 DataLinkLayerLinkActive : 1;
- UINT16 LinkBandwidthManagement : 1;
- UINT16 LinkAutonomousBandwidth : 1;
+ UINT16 CurrentLinkSpeed : 4;
+ UINT16 NegotiatedLinkWidth : 6;
+ UINT16 Undefined : 1;
+ UINT16 LinkTraining : 1;
+ UINT16 SlotClockConfiguration : 1;
+ UINT16 DataLinkLayerLinkActive : 1;
+ UINT16 LinkBandwidthManagement : 1;
+ UINT16 LinkAutonomousBandwidth : 1;
} Bits;
- UINT16 Uint16;
+ UINT16 Uint16;
} PCI_REG_PCIE_LINK_STATUS;
typedef union {
struct {
- UINT32 AttentionButton : 1;
- UINT32 PowerController : 1;
- UINT32 MrlSensor : 1;
- UINT32 AttentionIndicator : 1;
- UINT32 PowerIndicator : 1;
- UINT32 HotPlugSurprise : 1;
- UINT32 HotPlugCapable : 1;
- UINT32 SlotPowerLimitValue : 8;
- UINT32 SlotPowerLimitScale : 2;
- UINT32 ElectromechanicalInterlock : 1;
- UINT32 NoCommandCompleted : 1;
- UINT32 PhysicalSlotNumber : 13;
+ UINT32 AttentionButton : 1;
+ UINT32 PowerController : 1;
+ UINT32 MrlSensor : 1;
+ UINT32 AttentionIndicator : 1;
+ UINT32 PowerIndicator : 1;
+ UINT32 HotPlugSurprise : 1;
+ UINT32 HotPlugCapable : 1;
+ UINT32 SlotPowerLimitValue : 8;
+ UINT32 SlotPowerLimitScale : 2;
+ UINT32 ElectromechanicalInterlock : 1;
+ UINT32 NoCommandCompleted : 1;
+ UINT32 PhysicalSlotNumber : 13;
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_REG_PCIE_SLOT_CAPABILITY;
typedef union {
struct {
- UINT16 AttentionButtonPressed : 1;
- UINT16 PowerFaultDetected : 1;
- UINT16 MrlSensorChanged : 1;
- UINT16 PresenceDetectChanged : 1;
- UINT16 CommandCompletedInterrupt : 1;
- UINT16 HotPlugInterrupt : 1;
- UINT16 AttentionIndicator : 2;
- UINT16 PowerIndicator : 2;
- UINT16 PowerController : 1;
- UINT16 ElectromechanicalInterlock : 1;
- UINT16 DataLinkLayerStateChanged : 1;
- UINT16 Reserved : 3;
+ UINT16 AttentionButtonPressed : 1;
+ UINT16 PowerFaultDetected : 1;
+ UINT16 MrlSensorChanged : 1;
+ UINT16 PresenceDetectChanged : 1;
+ UINT16 CommandCompletedInterrupt : 1;
+ UINT16 HotPlugInterrupt : 1;
+ UINT16 AttentionIndicator : 2;
+ UINT16 PowerIndicator : 2;
+ UINT16 PowerController : 1;
+ UINT16 ElectromechanicalInterlock : 1;
+ UINT16 DataLinkLayerStateChanged : 1;
+ UINT16 Reserved : 3;
} Bits;
- UINT16 Uint16;
+ UINT16 Uint16;
} PCI_REG_PCIE_SLOT_CONTROL;
typedef union {
struct {
- UINT16 AttentionButtonPressed : 1;
- UINT16 PowerFaultDetected : 1;
- UINT16 MrlSensorChanged : 1;
- UINT16 PresenceDetectChanged : 1;
- UINT16 CommandCompleted : 1;
- UINT16 MrlSensor : 1;
- UINT16 PresenceDetect : 1;
- UINT16 ElectromechanicalInterlock : 1;
- UINT16 DataLinkLayerStateChanged : 1;
- UINT16 Reserved : 7;
+ UINT16 AttentionButtonPressed : 1;
+ UINT16 PowerFaultDetected : 1;
+ UINT16 MrlSensorChanged : 1;
+ UINT16 PresenceDetectChanged : 1;
+ UINT16 CommandCompleted : 1;
+ UINT16 MrlSensor : 1;
+ UINT16 PresenceDetect : 1;
+ UINT16 ElectromechanicalInterlock : 1;
+ UINT16 DataLinkLayerStateChanged : 1;
+ UINT16 Reserved : 7;
} Bits;
- UINT16 Uint16;
+ UINT16 Uint16;
} PCI_REG_PCIE_SLOT_STATUS;
typedef union {
struct {
- UINT16 SystemErrorOnCorrectableError : 1;
- UINT16 SystemErrorOnNonFatalError : 1;
- UINT16 SystemErrorOnFatalError : 1;
- UINT16 PmeInterrupt : 1;
- UINT16 CrsSoftwareVisibility : 1;
- UINT16 Reserved : 11;
+ UINT16 SystemErrorOnCorrectableError : 1;
+ UINT16 SystemErrorOnNonFatalError : 1;
+ UINT16 SystemErrorOnFatalError : 1;
+ UINT16 PmeInterrupt : 1;
+ UINT16 CrsSoftwareVisibility : 1;
+ UINT16 Reserved : 11;
} Bits;
- UINT16 Uint16;
+ UINT16 Uint16;
} PCI_REG_PCIE_ROOT_CONTROL;
typedef union {
struct {
- UINT16 CrsSoftwareVisibility : 1;
- UINT16 Reserved : 15;
+ UINT16 CrsSoftwareVisibility : 1;
+ UINT16 Reserved : 15;
} Bits;
- UINT16 Uint16;
+ UINT16 Uint16;
} PCI_REG_PCIE_ROOT_CAPABILITY;
typedef union {
struct {
- UINT32 PmeRequesterId : 16;
- UINT32 PmeStatus : 1;
- UINT32 PmePending : 1;
- UINT32 Reserved : 14;
+ UINT32 PmeRequesterId : 16;
+ UINT32 PmeStatus : 1;
+ UINT32 PmePending : 1;
+ UINT32 Reserved : 14;
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_REG_PCIE_ROOT_STATUS;
typedef union {
struct {
- UINT32 CompletionTimeoutRanges : 4;
- UINT32 CompletionTimeoutDisable : 1;
- UINT32 AriForwarding : 1;
- UINT32 AtomicOpRouting : 1;
- UINT32 AtomicOp32Completer : 1;
- UINT32 AtomicOp64Completer : 1;
- UINT32 Cas128Completer : 1;
- UINT32 NoRoEnabledPrPrPassing : 1;
- UINT32 LtrMechanism : 1;
- UINT32 TphCompleter : 2;
- UINT32 LnSystemCLS : 2;
- UINT32 TenBitTagCompleterSupported : 1;
- UINT32 TenBitTagRequesterSupported : 1;
- UINT32 Obff : 2;
- UINT32 ExtendedFmtField : 1;
- UINT32 EndEndTlpPrefix : 1;
- UINT32 MaxEndEndTlpPrefixes : 2;
- UINT32 EmergencyPowerReductionSupported : 2;
- UINT32 EmergencyPowerReductionInitializationRequired : 1;
- UINT32 Reserved3 : 4;
- UINT32 FrsSupported : 1;
+ UINT32 CompletionTimeoutRanges : 4;
+ UINT32 CompletionTimeoutDisable : 1;
+ UINT32 AriForwarding : 1;
+ UINT32 AtomicOpRouting : 1;
+ UINT32 AtomicOp32Completer : 1;
+ UINT32 AtomicOp64Completer : 1;
+ UINT32 Cas128Completer : 1;
+ UINT32 NoRoEnabledPrPrPassing : 1;
+ UINT32 LtrMechanism : 1;
+ UINT32 TphCompleter : 2;
+ UINT32 LnSystemCLS : 2;
+ UINT32 TenBitTagCompleterSupported : 1;
+ UINT32 TenBitTagRequesterSupported : 1;
+ UINT32 Obff : 2;
+ UINT32 ExtendedFmtField : 1;
+ UINT32 EndEndTlpPrefix : 1;
+ UINT32 MaxEndEndTlpPrefixes : 2;
+ UINT32 EmergencyPowerReductionSupported : 2;
+ UINT32 EmergencyPowerReductionInitializationRequired : 1;
+ UINT32 Reserved3 : 4;
+ UINT32 FrsSupported : 1;
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_REG_PCIE_DEVICE_CAPABILITY2;
-#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0
-#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1
-#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2
-#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3
-#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6
-#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7
-#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14
-#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15
+#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15
-#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
-#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
+#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
+#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
typedef union {
struct {
- UINT16 CompletionTimeoutValue : 4;
- UINT16 CompletionTimeoutDisable : 1;
- UINT16 AriForwarding : 1;
- UINT16 AtomicOpRequester : 1;
- UINT16 AtomicOpEgressBlocking : 1;
- UINT16 IdoRequest : 1;
- UINT16 IdoCompletion : 1;
- UINT16 LtrMechanism : 1;
- UINT16 EmergencyPowerReductionRequest : 1;
- UINT16 TenBitTagRequesterEnable : 1;
- UINT16 Obff : 2;
- UINT16 EndEndTlpPrefixBlocking : 1;
+ UINT16 CompletionTimeoutValue : 4;
+ UINT16 CompletionTimeoutDisable : 1;
+ UINT16 AriForwarding : 1;
+ UINT16 AtomicOpRequester : 1;
+ UINT16 AtomicOpEgressBlocking : 1;
+ UINT16 IdoRequest : 1;
+ UINT16 IdoCompletion : 1;
+ UINT16 LtrMechanism : 1;
+ UINT16 EmergencyPowerReductionRequest : 1;
+ UINT16 TenBitTagRequesterEnable : 1;
+ UINT16 Obff : 2;
+ UINT16 EndEndTlpPrefixBlocking : 1;
} Bits;
- UINT16 Uint16;
+ UINT16 Uint16;
} PCI_REG_PCIE_DEVICE_CONTROL2;
-#define PCIE_COMPLETION_TIMEOUT_50US_50MS 0
-#define PCIE_COMPLETION_TIMEOUT_50US_100US 1
-#define PCIE_COMPLETION_TIMEOUT_1MS_10MS 2
-#define PCIE_COMPLETION_TIMEOUT_16MS_55MS 5
-#define PCIE_COMPLETION_TIMEOUT_65MS_210MS 6
-#define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9
-#define PCIE_COMPLETION_TIMEOUT_1S_3_5S 10
-#define PCIE_COMPLETION_TIMEOUT_4S_13S 13
-#define PCIE_COMPLETION_TIMEOUT_17S_64S 14
+#define PCIE_COMPLETION_TIMEOUT_50US_50MS 0
+#define PCIE_COMPLETION_TIMEOUT_50US_100US 1
+#define PCIE_COMPLETION_TIMEOUT_1MS_10MS 2
+#define PCIE_COMPLETION_TIMEOUT_16MS_55MS 5
+#define PCIE_COMPLETION_TIMEOUT_65MS_210MS 6
+#define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9
+#define PCIE_COMPLETION_TIMEOUT_1S_3_5S 10
+#define PCIE_COMPLETION_TIMEOUT_4S_13S 13
+#define PCIE_COMPLETION_TIMEOUT_17S_64S 14
-#define PCIE_DEVICE_CONTROL_OBFF_DISABLED 0
-#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1
-#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2
-#define PCIE_DEVICE_CONTROL_OBFF_WAKE 3
+#define PCIE_DEVICE_CONTROL_OBFF_DISABLED 0
+#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1
+#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2
+#define PCIE_DEVICE_CONTROL_OBFF_WAKE 3
typedef union {
struct {
- UINT32 Reserved : 1;
- UINT32 LinkSpeedsVector : 7;
- UINT32 Crosslink : 1;
- UINT32 Reserved2 : 23;
+ UINT32 Reserved : 1;
+ UINT32 LinkSpeedsVector : 7;
+ UINT32 Crosslink : 1;
+ UINT32 Reserved2 : 23;
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_REG_PCIE_LINK_CAPABILITY2;
typedef union {
struct {
- UINT16 TargetLinkSpeed : 4;
- UINT16 EnterCompliance : 1;
- UINT16 HardwareAutonomousSpeedDisable : 1;
- UINT16 SelectableDeemphasis : 1;
- UINT16 TransmitMargin : 3;
- UINT16 EnterModifiedCompliance : 1;
- UINT16 ComplianceSos : 1;
- UINT16 CompliancePresetDeemphasis : 4;
+ UINT16 TargetLinkSpeed : 4;
+ UINT16 EnterCompliance : 1;
+ UINT16 HardwareAutonomousSpeedDisable : 1;
+ UINT16 SelectableDeemphasis : 1;
+ UINT16 TransmitMargin : 3;
+ UINT16 EnterModifiedCompliance : 1;
+ UINT16 ComplianceSos : 1;
+ UINT16 CompliancePresetDeemphasis : 4;
} Bits;
- UINT16 Uint16;
+ UINT16 Uint16;
} PCI_REG_PCIE_LINK_CONTROL2;
typedef union {
struct {
- UINT16 CurrentDeemphasisLevel : 1;
- UINT16 EqualizationComplete : 1;
- UINT16 EqualizationPhase1Successful : 1;
- UINT16 EqualizationPhase2Successful : 1;
- UINT16 EqualizationPhase3Successful : 1;
- UINT16 LinkEqualizationRequest : 1;
- UINT16 Reserved : 10;
+ UINT16 CurrentDeemphasisLevel : 1;
+ UINT16 EqualizationComplete : 1;
+ UINT16 EqualizationPhase1Successful : 1;
+ UINT16 EqualizationPhase2Successful : 1;
+ UINT16 EqualizationPhase3Successful : 1;
+ UINT16 LinkEqualizationRequest : 1;
+ UINT16 Reserved : 10;
} Bits;
- UINT16 Uint16;
+ UINT16 Uint16;
} PCI_REG_PCIE_LINK_STATUS2;
typedef struct {
- EFI_PCI_CAPABILITY_HDR Hdr;
- PCI_REG_PCIE_CAPABILITY Capability;
- PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability;
- PCI_REG_PCIE_DEVICE_CONTROL DeviceControl;
- PCI_REG_PCIE_DEVICE_STATUS DeviceStatus;
- PCI_REG_PCIE_LINK_CAPABILITY LinkCapability;
- PCI_REG_PCIE_LINK_CONTROL LinkControl;
- PCI_REG_PCIE_LINK_STATUS LinkStatus;
- PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;
- PCI_REG_PCIE_SLOT_CONTROL SlotControl;
- PCI_REG_PCIE_SLOT_STATUS SlotStatus;
- PCI_REG_PCIE_ROOT_CONTROL RootControl;
- PCI_REG_PCIE_ROOT_CAPABILITY RootCapability;
- PCI_REG_PCIE_ROOT_STATUS RootStatus;
- PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;
- PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2;
- UINT16 DeviceStatus2;
- PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;
- PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;
- PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;
- UINT32 SlotCapability2;
- UINT16 SlotControl2;
- UINT16 SlotStatus2;
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ PCI_REG_PCIE_CAPABILITY Capability;
+ PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability;
+ PCI_REG_PCIE_DEVICE_CONTROL DeviceControl;
+ PCI_REG_PCIE_DEVICE_STATUS DeviceStatus;
+ PCI_REG_PCIE_LINK_CAPABILITY LinkCapability;
+ PCI_REG_PCIE_LINK_CONTROL LinkControl;
+ PCI_REG_PCIE_LINK_STATUS LinkStatus;
+ PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;
+ PCI_REG_PCIE_SLOT_CONTROL SlotControl;
+ PCI_REG_PCIE_SLOT_STATUS SlotStatus;
+ PCI_REG_PCIE_ROOT_CONTROL RootControl;
+ PCI_REG_PCIE_ROOT_CAPABILITY RootCapability;
+ PCI_REG_PCIE_ROOT_STATUS RootStatus;
+ PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;
+ PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2;
+ UINT16 DeviceStatus2;
+ PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;
+ PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;
+ PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;
+ UINT32 SlotCapability2;
+ UINT16 SlotControl2;
+ UINT16 SlotStatus2;
} PCI_CAPABILITY_PCIEXP;
-#define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10
-#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24
-#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20
-#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28
-#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20
+#define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10
+#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24
+#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20
+#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28
+#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20
//
// for SR-IOV
//
-#define EFI_PCIE_CAPABILITY_ID_ARI 0x0E
-#define EFI_PCIE_CAPABILITY_ID_ATS 0x0F
-#define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10
-#define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11
+#define EFI_PCIE_CAPABILITY_ID_ARI 0x0E
+#define EFI_PCIE_CAPABILITY_ID_ATS 0x0F
+#define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10
+#define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11
typedef struct {
- UINT32 CapabilityHeader;
- UINT32 Capability;
- UINT16 Control;
- UINT16 Status;
- UINT16 InitialVFs;
- UINT16 TotalVFs;
- UINT16 NumVFs;
- UINT8 FunctionDependencyLink;
- UINT8 Reserved0;
- UINT16 FirstVFOffset;
- UINT16 VFStride;
- UINT16 Reserved1;
- UINT16 VFDeviceID;
- UINT32 SupportedPageSize;
- UINT32 SystemPageSize;
- UINT32 VFBar[6];
- UINT32 VFMigrationStateArrayOffset;
+ UINT32 CapabilityHeader;
+ UINT32 Capability;
+ UINT16 Control;
+ UINT16 Status;
+ UINT16 InitialVFs;
+ UINT16 TotalVFs;
+ UINT16 NumVFs;
+ UINT8 FunctionDependencyLink;
+ UINT8 Reserved0;
+ UINT16 FirstVFOffset;
+ UINT16 VFStride;
+ UINT16 Reserved1;
+ UINT16 VFDeviceID;
+ UINT32 SupportedPageSize;
+ UINT32 SystemPageSize;
+ UINT32 VFBar[6];
+ UINT32 VFMigrationStateArrayOffset;
} SR_IOV_CAPABILITY_REGISTER;
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C
typedef struct {
- UINT32 CapabilityId:16;
- UINT32 CapabilityVersion:4;
- UINT32 NextCapabilityOffset:12;
+ UINT32 CapabilityId : 16;
+ UINT32 CapabilityVersion : 4;
+ UINT32 NextCapabilityOffset : 12;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER;
-#define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER
+#define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2
typedef union {
struct {
- UINT32 Undefined : 1;
- UINT32 Reserved : 3;
- UINT32 DataLinkProtocolError : 1;
- UINT32 SurpriseDownError : 1;
- UINT32 Reserved2 : 6;
- UINT32 PoisonedTlp : 1;
- UINT32 FlowControlProtocolError : 1;
- UINT32 CompletionTimeout : 1;
- UINT32 CompleterAbort : 1;
- UINT32 UnexpectedCompletion : 1;
- UINT32 ReceiverOverflow : 1;
- UINT32 MalformedTlp : 1;
- UINT32 EcrcError : 1;
- UINT32 UnsupportedRequestError : 1;
- UINT32 AcsVoilation : 1;
- UINT32 UncorrectableInternalError : 1;
- UINT32 McBlockedTlp : 1;
- UINT32 AtomicOpEgressBlocked : 1;
- UINT32 TlpPrefixBlockedError : 1;
- UINT32 Reserved3 : 6;
+ UINT32 Undefined : 1;
+ UINT32 Reserved : 3;
+ UINT32 DataLinkProtocolError : 1;
+ UINT32 SurpriseDownError : 1;
+ UINT32 Reserved2 : 6;
+ UINT32 PoisonedTlp : 1;
+ UINT32 FlowControlProtocolError : 1;
+ UINT32 CompletionTimeout : 1;
+ UINT32 CompleterAbort : 1;
+ UINT32 UnexpectedCompletion : 1;
+ UINT32 ReceiverOverflow : 1;
+ UINT32 MalformedTlp : 1;
+ UINT32 EcrcError : 1;
+ UINT32 UnsupportedRequestError : 1;
+ UINT32 AcsVoilation : 1;
+ UINT32 UncorrectableInternalError : 1;
+ UINT32 McBlockedTlp : 1;
+ UINT32 AtomicOpEgressBlocked : 1;
+ UINT32 TlpPrefixBlockedError : 1;
+ UINT32 Reserved3 : 6;
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_EXPRESS_REG_UNCORRECTABLE_ERROR;
typedef struct {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
- PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorStatus;
- PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorMask;
- PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorSeverity;
- UINT32 CorrectableErrorStatus;
- UINT32 CorrectableErrorMask;
- UINT32 AdvancedErrorCapabilitiesAndControl;
- UINT32 HeaderLog[4];
- UINT32 RootErrorCommand;
- UINT32 RootErrorStatus;
- UINT16 ErrorSourceIdentification;
- UINT16 CorrectableErrorSourceIdentification;
- UINT32 TlpPrefixLog[4];
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorStatus;
+ PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorMask;
+ PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorStatus;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 HeaderLog[4];
+ UINT32 RootErrorCommand;
+ UINT32 RootErrorStatus;
+ UINT16 ErrorSourceIdentification;
+ UINT16 CorrectableErrorSourceIdentification;
+ UINT32 TlpPrefixLog[4];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING;
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID 0x0002
@@ -505,86 +505,86 @@ typedef struct {
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1 0x1
typedef struct {
- UINT32 VcResourceCapability:24;
- UINT32 PortArbTableOffset:8;
- UINT32 VcResourceControl;
- UINT16 Reserved1;
- UINT16 VcResourceStatus;
+ UINT32 VcResourceCapability : 24;
+ UINT32 PortArbTableOffset : 8;
+ UINT32 VcResourceControl;
+ UINT16 Reserved1;
+ UINT16 VcResourceStatus;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC;
typedef struct {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
- UINT32 ExtendedVcCount:3;
- UINT32 PortVcCapability1:29;
- UINT32 PortVcCapability2:24;
- UINT32 VcArbTableOffset:8;
- UINT16 PortVcControl;
- UINT16 PortVcStatus;
- PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC Capability[1];
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT32 ExtendedVcCount : 3;
+ UINT32 PortVcCapability1 : 29;
+ UINT32 PortVcCapability2 : 24;
+ UINT32 VcArbTableOffset : 8;
+ UINT16 PortVcControl;
+ UINT16 PortVcStatus;
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC Capability[1];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY;
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID 0x0003
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1 0x1
typedef struct {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
- UINT64 SerialNumber;
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT64 SerialNumber;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER;
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1
typedef struct {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
- UINT32 ElementSelfDescription;
- UINT32 Reserved;
- UINT32 LinkEntry[1];
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT32 ElementSelfDescription;
+ UINT32 Reserved;
+ UINT32 LinkEntry[1];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION;
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1
typedef struct {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
- UINT32 RootComplexLinkCapabilities;
- UINT16 RootComplexLinkControl;
- UINT16 RootComplexLinkStatus;
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT32 RootComplexLinkCapabilities;
+ UINT16 RootComplexLinkControl;
+ UINT16 RootComplexLinkStatus;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL;
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1
typedef struct {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
- UINT32 DataSelect:8;
- UINT32 Reserved:24;
- UINT32 Data;
- UINT32 PowerBudgetCapability:1;
- UINT32 Reserved2:7;
- UINT32 Reserved3:24;
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT32 DataSelect : 8;
+ UINT32 Reserved : 24;
+ UINT32 Data;
+ UINT32 PowerBudgetCapability : 1;
+ UINT32 Reserved2 : 7;
+ UINT32 Reserved3 : 24;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING;
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1
typedef struct {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
- UINT16 AcsCapability;
- UINT16 AcsControl;
- UINT8 EgressControlVectorArray[1];
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT16 AcsCapability;
+ UINT16 AcsControl;
+ UINT8 EgressControlVectorArray[1];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED;
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1
typedef struct {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
- UINT32 AssociationBitmap;
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT32 AssociationBitmap;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION;
#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID 0x0008
@@ -592,41 +592,41 @@ typedef struct {
typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY;
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1
typedef struct {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
- UINT32 VendorSpecificHeader;
- UINT8 VendorSpecific[1];
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT32 VendorSpecificHeader;
+ UINT8 VendorSpecific[1];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC;
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1
typedef struct {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
- UINT16 VendorId;
- UINT16 DeviceId;
- UINT32 RcrbCapabilities;
- UINT32 RcrbControl;
- UINT32 Reserved;
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT32 RcrbCapabilities;
+ UINT32 RcrbControl;
+ UINT32 Reserved;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER;
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1
typedef struct {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
- UINT16 MultiCastCapability;
- UINT16 MulticastControl;
- UINT64 McBaseAddress;
- UINT64 McReceiveAddress;
- UINT64 McBlockAll;
- UINT64 McBlockUntranslated;
- UINT64 McOverlayBar;
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT16 MultiCastCapability;
+ UINT16 MulticastControl;
+ UINT64 McBaseAddress;
+ UINT64 McReceiveAddress;
+ UINT64 McBlockAll;
+ UINT64 McBlockUntranslated;
+ UINT64 McOverlayBar;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST;
#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID 0x0015
@@ -634,81 +634,79 @@ typedef struct {
typedef union {
struct {
- UINT32 Reserved:4;
- UINT32 BarSizeCapability:28;
+ UINT32 Reserved : 4;
+ UINT32 BarSizeCapability : 28;
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY;
-
typedef union {
struct {
- UINT32 BarIndex:3;
- UINT32 Reserved:2;
- UINT32 ResizableBarNumber:3;
- UINT32 BarSize:6;
- UINT32 Reserved2:2;
- UINT32 BarSizeCapability:16;
+ UINT32 BarIndex : 3;
+ UINT32 Reserved : 2;
+ UINT32 ResizableBarNumber : 3;
+ UINT32 BarSize : 6;
+ UINT32 Reserved2 : 2;
+ UINT32 BarSizeCapability : 16;
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL;
typedef struct {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY ResizableBarCapability;
- PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL ResizableBarControl;
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY ResizableBarCapability;
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL ResizableBarControl;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY;
typedef struct {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
- PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Capability[1];
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Capability[1];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR;
-#define GET_NUMBER_RESIZABLE_BARS(x) (x->Capability[0].ResizableBarControl.Bits.ResizableBarNumber)
+#define GET_NUMBER_RESIZABLE_BARS(x) (x->Capability[0].ResizableBarControl.Bits.ResizableBarNumber)
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID 0x000E
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1 0x1
typedef struct {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
- UINT16 AriCapability;
- UINT16 AriControl;
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT16 AriCapability;
+ UINT16 AriControl;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY;
#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID 0x0016
#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1 0x1
typedef struct {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
- UINT32 DpaCapability;
- UINT32 DpaLatencyIndicator;
- UINT16 DpaStatus;
- UINT16 DpaControl;
- UINT8 DpaPowerAllocationArray[1];
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT32 DpaCapability;
+ UINT32 DpaLatencyIndicator;
+ UINT16 DpaStatus;
+ UINT16 DpaControl;
+ UINT8 DpaPowerAllocationArray[1];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION;
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT16)(((POWER->DpaCapability)&0x0000000F))
-
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT16)(((POWER->DpaCapability)&0x0000000F))
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID 0x0018
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1 0x1
typedef struct {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
- UINT16 MaxSnoopLatency;
- UINT16 MaxNoSnoopLatency;
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT16 MaxSnoopLatency;
+ UINT16 MaxNoSnoopLatency;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING;
#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID 0x0017
#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1 0x1
typedef struct {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
- UINT32 TphRequesterCapability;
- UINT32 TphRequesterControl;
- UINT16 TphStTable[1];
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT32 TphRequesterCapability;
+ UINT32 TphRequesterControl;
+ UINT16 TphStTable[1];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH;
-#define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)
+#define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)
#pragma pack()
diff --git a/MdePkg/Include/IndustryStandard/PciExpress30.h b/MdePkg/Include/IndustryStandard/PciExpress30.h
index 2e52e078..5db3b668 100644
--- a/MdePkg/Include/IndustryStandard/PciExpress30.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress30.h
@@ -20,30 +20,30 @@
typedef union {
struct {
- UINT32 PerformEqualization : 1;
- UINT32 LinkEqualizationRequestInterruptEnable : 1;
- UINT32 Reserved : 30;
+ UINT32 PerformEqualization : 1;
+ UINT32 LinkEqualizationRequestInterruptEnable : 1;
+ UINT32 Reserved : 30;
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_EXPRESS_REG_LINK_CONTROL3;
typedef union {
struct {
- UINT16 DownstreamPortTransmitterPreset : 4;
- UINT16 DownstreamPortReceiverPresetHint : 3;
- UINT16 Reserved : 1;
- UINT16 UpstreamPortTransmitterPreset : 4;
- UINT16 UpstreamPortReceiverPresetHint : 3;
- UINT16 Reserved2 : 1;
+ UINT16 DownstreamPortTransmitterPreset : 4;
+ UINT16 DownstreamPortReceiverPresetHint : 3;
+ UINT16 Reserved : 1;
+ UINT16 UpstreamPortTransmitterPreset : 4;
+ UINT16 UpstreamPortReceiverPresetHint : 3;
+ UINT16 Reserved2 : 1;
} Bits;
- UINT16 Uint16;
+ UINT16 Uint16;
} PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL;
typedef struct {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
- PCI_EXPRESS_REG_LINK_CONTROL3 LinkControl3;
- UINT32 LaneErrorStatus;
- PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL EqualizationControl[2];
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_REG_LINK_CONTROL3 LinkControl3;
+ UINT32 LaneErrorStatus;
+ PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL EqualizationControl[2];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE;
#pragma pack()
diff --git a/MdePkg/Include/IndustryStandard/PciExpress31.h b/MdePkg/Include/IndustryStandard/PciExpress31.h
index 2e5e097b..2bc468dc 100644
--- a/MdePkg/Include/IndustryStandard/PciExpress31.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress31.h
@@ -20,51 +20,51 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
typedef union {
struct {
- UINT32 PciPmL12 : 1;
- UINT32 PciPmL11 : 1;
- UINT32 AspmL12 : 1;
- UINT32 AspmL11 : 1;
- UINT32 L1PmSubstates : 1;
- UINT32 Reserved : 3;
- UINT32 CommonModeRestoreTime : 8;
- UINT32 TPowerOnScale : 2;
- UINT32 Reserved2 : 1;
- UINT32 TPowerOnValue : 5;
- UINT32 Reserved3 : 8;
+ UINT32 PciPmL12 : 1;
+ UINT32 PciPmL11 : 1;
+ UINT32 AspmL12 : 1;
+ UINT32 AspmL11 : 1;
+ UINT32 L1PmSubstates : 1;
+ UINT32 Reserved : 3;
+ UINT32 CommonModeRestoreTime : 8;
+ UINT32 TPowerOnScale : 2;
+ UINT32 Reserved2 : 1;
+ UINT32 TPowerOnValue : 5;
+ UINT32 Reserved3 : 8;
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY;
typedef union {
struct {
- UINT32 PciPmL12 : 1;
- UINT32 PciPmL11 : 1;
- UINT32 AspmL12 : 1;
- UINT32 AspmL11 : 1;
- UINT32 Reserved : 4;
- UINT32 CommonModeRestoreTime : 8;
- UINT32 LtrL12ThresholdValue : 10;
- UINT32 Reserved2 : 3;
- UINT32 LtrL12ThresholdScale : 3;
+ UINT32 PciPmL12 : 1;
+ UINT32 PciPmL11 : 1;
+ UINT32 AspmL12 : 1;
+ UINT32 AspmL11 : 1;
+ UINT32 Reserved : 4;
+ UINT32 CommonModeRestoreTime : 8;
+ UINT32 LtrL12ThresholdValue : 10;
+ UINT32 Reserved2 : 3;
+ UINT32 LtrL12ThresholdScale : 3;
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1;
typedef union {
struct {
- UINT32 TPowerOnScale : 2;
- UINT32 Reserved : 1;
- UINT32 TPowerOnValue : 5;
- UINT32 Reserved2 : 24;
+ UINT32 TPowerOnScale : 2;
+ UINT32 Reserved : 1;
+ UINT32 TPowerOnValue : 5;
+ UINT32 Reserved2 : 24;
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2;
typedef struct {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
- PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY Capability;
- PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1 Control1;
- PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2 Control2;
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY Capability;
+ PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1 Control1;
+ PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2 Control2;
} PCI_EXPRESS_EXTENDED_CAPABILITIES_L1_PM_SUBSTATES;
#pragma pack()
diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h b/MdePkg/Include/IndustryStandard/PciExpress40.h
index a76f1bd5..b2f78959 100644
--- a/MdePkg/Include/IndustryStandard/PciExpress40.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress40.h
@@ -24,86 +24,88 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1 0x1
// Register offsets from Physical Layer PCI-E Ext Cap Header
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET 0x04
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET 0x08
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET 0x0C
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSET 0x10
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STATUS_OFFSET 0x14
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STATUS_OFFSET 0x18
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET 0x04
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET 0x08
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET 0x0C
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSET 0x10
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STATUS_OFFSET 0x14
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STATUS_OFFSET 0x18
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20
typedef union {
struct {
- UINT32 Reserved : 32; // Reserved bit 0:31
+ UINT32 Reserved : 32; // Reserved bit 0:31
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES;
typedef union {
struct {
- UINT32 Reserved : 32; // Reserved bit 0:31
+ UINT32 Reserved : 32; // Reserved bit 0:31
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL;
typedef union {
struct {
- UINT32 EqualizationComplete : 1; // bit 0
- UINT32 EqualizationPhase1Success : 1; // bit 1
- UINT32 EqualizationPhase2Success : 1; // bit 2
- UINT32 EqualizationPhase3Success : 1; // bit 3
- UINT32 LinkEqualizationRequest : 1; // bit 4
- UINT32 Reserved : 27; // Reserved bit 5:31
+ UINT32 EqualizationComplete : 1; // bit 0
+ UINT32 EqualizationPhase1Success : 1; // bit 1
+ UINT32 EqualizationPhase2Success : 1; // bit 2
+ UINT32 EqualizationPhase3Success : 1; // bit 3
+ UINT32 LinkEqualizationRequest : 1; // bit 4
+ UINT32 Reserved : 27; // Reserved bit 5:31
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS;
typedef union {
struct {
- UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3
- UINT8 UpstreamPortTransmitterPreset : 4; //bit 4..7
+ UINT8 DownstreamPortTransmitterPreset : 4; // bit 0..3
+ UINT8 UpstreamPortTransmitterPreset : 4; // bit 4..7
} Bits;
- UINT8 Uint8;
+ UINT8 Uint8;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL;
typedef struct {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
- PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES Capablities;
- PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL Control;
- PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS Status;
- UINT32 LocalDataParityMismatchStatus;
- UINT32 FirstRetimerDataParityMismatchStatus;
- UINT32 SecondRetimerDataParityMismatchStatus;
- UINT32 Reserved;
- PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES Capablities;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL Control;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS Status;
+ UINT32 LocalDataParityMismatchStatus;
+ UINT32 FirstRetimerDataParityMismatchStatus;
+ UINT32 SecondRetimerDataParityMismatchStatus;
+ UINT32 Reserved;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;
///@}
/// The Designated Vendor Specific Capability definitions
/// Based on section 7.9.6 of PCI Express Base Specification 4.0.
///@{
-typedef union {
- struct {
- UINT32 DvsecVendorId : 16; //bit 0..15
- UINT32 DvsecRevision : 4; //bit 16..19
- UINT32 DvsecLength : 12; //bit 20..31
- }Bits;
- UINT32 Uint32;
-}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_DESIGNATED_VENDOR_SPECIFIC_ID 0x0023
typedef union {
struct {
- UINT16 DvsecId : 16; //bit 0..15
- }Bits;
- UINT16 Uint16;
-}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;
+ UINT32 DvsecVendorId : 16; // bit 0..15
+ UINT32 DvsecRevision : 4; // bit 16..19
+ UINT32 DvsecLength : 12; // bit 20..31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;
+
+typedef union {
+ struct {
+ UINT16 DvsecId : 16; // bit 0..15
+ } Bits;
+ UINT16 Uint16;
+} PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;
typedef struct {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
- PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1;
- PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2;
- UINT8 DesignatedVendorSpecific[1];
-}PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1;
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2;
+ UINT8 DesignatedVendorSpecific[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;
///@}
#pragma pack()
diff --git a/MdePkg/Include/IndustryStandard/PciExpress50.h b/MdePkg/Include/IndustryStandard/PciExpress50.h
index 37658758..fcfa564c 100644
--- a/MdePkg/Include/IndustryStandard/PciExpress50.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress50.h
@@ -23,111 +23,111 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_VER1 0x1
// Register offsets from Physical Layer PCI-E Ext Cap Header
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES_OFFSET 0x04
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL_OFFSET 0x08
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS_OFFSET 0x0C
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1_OFFSET 0x10
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2_OFFSET 0x14
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1_OFFSET 0x18
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2_OFFSET 0x1C
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES_OFFSET 0x04
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL_OFFSET 0x08
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS_OFFSET 0x0C
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1_OFFSET 0x10
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2_OFFSET 0x14
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1_OFFSET 0x18
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2_OFFSET 0x1C
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20
typedef union {
struct {
- UINT32 EqualizationByPassToHighestRateSupport : 1; // bit 0
- UINT32 NoEqualizationNeededSupport : 1; // bit 1
- UINT32 Reserved1 : 6; // Reserved bit 2:7
- UINT32 ModifiedTSUsageMode0Support : 1; // bit 8
- UINT32 ModifiedTSUsageMode1Support : 1; // bit 9
- UINT32 ModifiedTSUsageMode2Support : 1; // bit 10
- UINT32 ModifiedTSReservedUsageModes : 5; // bit 11:15
- UINT32 Reserved2 : 16; // Reserved bit 16:31
+ UINT32 EqualizationByPassToHighestRateSupport : 1; // bit 0
+ UINT32 NoEqualizationNeededSupport : 1; // bit 1
+ UINT32 Reserved1 : 6; // Reserved bit 2:7
+ UINT32 ModifiedTSUsageMode0Support : 1; // bit 8
+ UINT32 ModifiedTSUsageMode1Support : 1; // bit 9
+ UINT32 ModifiedTSUsageMode2Support : 1; // bit 10
+ UINT32 ModifiedTSReservedUsageModes : 5; // bit 11:15
+ UINT32 Reserved2 : 16; // Reserved bit 16:31
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES;
typedef union {
struct {
- UINT32 EqualizationByPassToHighestRateDisable : 1; // bit 0
- UINT32 NoEqualizationNeededDisable : 1; // bit 1
- UINT32 Reserved1 : 6; // Reserved bit 2:7
- UINT32 ModifiedTSUsageModeSelected : 3; // bit 8:10
- UINT32 Reserved2 : 21; // Reserved bit 11:31
+ UINT32 EqualizationByPassToHighestRateDisable : 1; // bit 0
+ UINT32 NoEqualizationNeededDisable : 1; // bit 1
+ UINT32 Reserved1 : 6; // Reserved bit 2:7
+ UINT32 ModifiedTSUsageModeSelected : 3; // bit 8:10
+ UINT32 Reserved2 : 21; // Reserved bit 11:31
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL;
typedef union {
struct {
- UINT32 EqualizationComplete : 1; // bit 0
- UINT32 EqualizationPhase1Success : 1; // bit 1
- UINT32 EqualizationPhase2Success : 1; // bit 2
- UINT32 EqualizationPhase3Success : 1; // bit 3
- UINT32 LinkEqualizationRequest : 1; // bit 4
- UINT32 ModifiedTSRcvd : 1; // bit 5
- UINT32 RcvdEnhancedLinkControl : 2; // bit 6:7
- UINT32 TransmitterPrecodingOn : 1; // bit 8
- UINT32 TransmitterPrecodeRequest : 1; // bit 9
- UINT32 NoEqualizationNeededRcvd : 1; // bit 10
- UINT32 Reserved : 21; // Reserved bit 11:31
+ UINT32 EqualizationComplete : 1; // bit 0
+ UINT32 EqualizationPhase1Success : 1; // bit 1
+ UINT32 EqualizationPhase2Success : 1; // bit 2
+ UINT32 EqualizationPhase3Success : 1; // bit 3
+ UINT32 LinkEqualizationRequest : 1; // bit 4
+ UINT32 ModifiedTSRcvd : 1; // bit 5
+ UINT32 RcvdEnhancedLinkControl : 2; // bit 6:7
+ UINT32 TransmitterPrecodingOn : 1; // bit 8
+ UINT32 TransmitterPrecodeRequest : 1; // bit 9
+ UINT32 NoEqualizationNeededRcvd : 1; // bit 10
+ UINT32 Reserved : 21; // Reserved bit 11:31
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS;
typedef union {
struct {
- UINT32 RcvdModifiedTSUsageMode : 3; // bit 0:2
- UINT32 RcvdModifiedTSUsageInfo1 : 13; // bit 3:15
- UINT32 RcvdModifiedTSVendorId : 16; // bit 16:31
+ UINT32 RcvdModifiedTSUsageMode : 3; // bit 0:2
+ UINT32 RcvdModifiedTSUsageInfo1 : 13; // bit 3:15
+ UINT32 RcvdModifiedTSVendorId : 16; // bit 16:31
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1;
typedef union {
struct {
- UINT32 RcvdModifiedTSUsageInfo2 : 24; // bit 0:23
- UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25
- UINT32 Reserved : 6; // Reserved bit 26:31
+ UINT32 RcvdModifiedTSUsageInfo2 : 24; // bit 0:23
+ UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25
+ UINT32 Reserved : 6; // Reserved bit 26:31
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2;
typedef union {
struct {
- UINT32 TransModifiedTSUsageMode : 3; // bit 0:2
- UINT32 TransModifiedTSUsageInfo1 : 13; // bit 3:15
- UINT32 TransModifiedTSVendorId : 16; // bit 16:31
+ UINT32 TransModifiedTSUsageMode : 3; // bit 0:2
+ UINT32 TransModifiedTSUsageInfo1 : 13; // bit 3:15
+ UINT32 TransModifiedTSVendorId : 16; // bit 16:31
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1;
typedef union {
struct {
- UINT32 TransModifiedTSUsageInfo2 : 24; // bit 0:23
- UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25
- UINT32 Reserved : 6; // Reserved bit 26:31
+ UINT32 TransModifiedTSUsageInfo2 : 24; // bit 0:23
+ UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25
+ UINT32 Reserved : 6; // Reserved bit 26:31
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2;
typedef union {
struct {
- UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3
- UINT8 UpstreamPortTransmitterPreset : 4; //bit 4..7
+ UINT8 DownstreamPortTransmitterPreset : 4; // bit 0..3
+ UINT8 UpstreamPortTransmitterPreset : 4; // bit 4..7
} Bits;
- UINT8 Uint8;
+ UINT8 Uint8;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL;
typedef struct {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
- PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES Capablities;
- PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL Control;
- PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS Status;
- PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1 RcvdModifiedTs1Data;
- PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2 RcvdModifiedTs2Data;
- PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1 TransModifiedTs1Data;
- PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2 TransModifiedTs2Data;
- PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES Capablities;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL Control;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS Status;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1 RcvdModifiedTs1Data;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2 RcvdModifiedTs2Data;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1 TransModifiedTs1Data;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2 TransModifiedTs2Data;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_32_0;
///@}
diff --git a/MdePkg/Include/IndustryStandard/PeImage.h b/MdePkg/Include/IndustryStandard/PeImage.h
index 15a713ea..455928e6 100644
--- a/MdePkg/Include/IndustryStandard/PeImage.h
+++ b/MdePkg/Include/IndustryStandard/PeImage.h
@@ -4,12 +4,13 @@
EFI_IMAGE_NT_HEADERS64 is for PE32+.
This file is coded to the Visual Studio, Microsoft Portable Executable and
- Common Object File Format Specification, Revision 8.3 - February 6, 2013.
+ Common Object File Format Specification, Revision 9.3 - December 29, 2015.
This file also includes some definitions in PI Specification, Revision 1.0.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
Portions Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -21,11 +22,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// PE32+ Subsystem type for EFI images
//
-#define EFI_IMAGE_SUBSYSTEM_EFI_APPLICATION 10
-#define EFI_IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER 11
-#define EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER 12
-#define EFI_IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER 13 ///< defined PI Specification, 1.0
-
+#define EFI_IMAGE_SUBSYSTEM_EFI_APPLICATION 10
+#define EFI_IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER 11
+#define EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER 12
+#define EFI_IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER 13///< defined PI Specification, 1.0
//
// PE32+ Machine type for EFI images
@@ -39,6 +39,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define IMAGE_FILE_MACHINE_RISCV32 0x5032
#define IMAGE_FILE_MACHINE_RISCV64 0x5064
#define IMAGE_FILE_MACHINE_RISCV128 0x5128
+#define IMAGE_FILE_MACHINE_LOONGARCH32 0x6232
+#define IMAGE_FILE_MACHINE_LOONGARCH64 0x6264
//
// EXE file formats
@@ -53,44 +55,44 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
/// under DOS it can print an error message.
///
typedef struct {
- UINT16 e_magic; ///< Magic number.
- UINT16 e_cblp; ///< Bytes on last page of file.
- UINT16 e_cp; ///< Pages in file.
- UINT16 e_crlc; ///< Relocations.
- UINT16 e_cparhdr; ///< Size of header in paragraphs.
- UINT16 e_minalloc; ///< Minimum extra paragraphs needed.
- UINT16 e_maxalloc; ///< Maximum extra paragraphs needed.
- UINT16 e_ss; ///< Initial (relative) SS value.
- UINT16 e_sp; ///< Initial SP value.
- UINT16 e_csum; ///< Checksum.
- UINT16 e_ip; ///< Initial IP value.
- UINT16 e_cs; ///< Initial (relative) CS value.
- UINT16 e_lfarlc; ///< File address of relocation table.
- UINT16 e_ovno; ///< Overlay number.
- UINT16 e_res[4]; ///< Reserved words.
- UINT16 e_oemid; ///< OEM identifier (for e_oeminfo).
- UINT16 e_oeminfo; ///< OEM information; e_oemid specific.
- UINT16 e_res2[10]; ///< Reserved words.
- UINT32 e_lfanew; ///< File address of new exe header.
+ UINT16 e_magic; ///< Magic number.
+ UINT16 e_cblp; ///< Bytes on last page of file.
+ UINT16 e_cp; ///< Pages in file.
+ UINT16 e_crlc; ///< Relocations.
+ UINT16 e_cparhdr; ///< Size of header in paragraphs.
+ UINT16 e_minalloc; ///< Minimum extra paragraphs needed.
+ UINT16 e_maxalloc; ///< Maximum extra paragraphs needed.
+ UINT16 e_ss; ///< Initial (relative) SS value.
+ UINT16 e_sp; ///< Initial SP value.
+ UINT16 e_csum; ///< Checksum.
+ UINT16 e_ip; ///< Initial IP value.
+ UINT16 e_cs; ///< Initial (relative) CS value.
+ UINT16 e_lfarlc; ///< File address of relocation table.
+ UINT16 e_ovno; ///< Overlay number.
+ UINT16 e_res[4]; ///< Reserved words.
+ UINT16 e_oemid; ///< OEM identifier (for e_oeminfo).
+ UINT16 e_oeminfo; ///< OEM information; e_oemid specific.
+ UINT16 e_res2[10]; ///< Reserved words.
+ UINT32 e_lfanew; ///< File address of new exe header.
} EFI_IMAGE_DOS_HEADER;
///
/// COFF File Header (Object and Image).
///
typedef struct {
- UINT16 Machine;
- UINT16 NumberOfSections;
- UINT32 TimeDateStamp;
- UINT32 PointerToSymbolTable;
- UINT32 NumberOfSymbols;
- UINT16 SizeOfOptionalHeader;
- UINT16 Characteristics;
+ UINT16 Machine;
+ UINT16 NumberOfSections;
+ UINT32 TimeDateStamp;
+ UINT32 PointerToSymbolTable;
+ UINT32 NumberOfSymbols;
+ UINT16 SizeOfOptionalHeader;
+ UINT16 Characteristics;
} EFI_IMAGE_FILE_HEADER;
///
/// Size of EFI_IMAGE_FILE_HEADER.
///
-#define EFI_IMAGE_SIZEOF_FILE_HEADER 20
+#define EFI_IMAGE_SIZEOF_FILE_HEADER 20
//
// Characteristics
@@ -99,6 +101,7 @@ typedef struct {
#define EFI_IMAGE_FILE_EXECUTABLE_IMAGE BIT1 ///< 0x0002 File is executable (i.e. no unresolved externel references).
#define EFI_IMAGE_FILE_LINE_NUMS_STRIPPED BIT2 ///< 0x0004 Line numbers stripped from file.
#define EFI_IMAGE_FILE_LOCAL_SYMS_STRIPPED BIT3 ///< 0x0008 Local symbols stripped from file.
+#define EFI_IMAGE_FILE_LARGE_ADDRESS_AWARE BIT5 ///< 0x0020 Supports addresses > 2-GB
#define EFI_IMAGE_FILE_BYTES_REVERSED_LO BIT7 ///< 0x0080 Bytes of machine word are reversed.
#define EFI_IMAGE_FILE_32BIT_MACHINE BIT8 ///< 0x0100 32 bit word machine.
#define EFI_IMAGE_FILE_DEBUG_STRIPPED BIT9 ///< 0x0200 Debugging info stripped from file in .DBG file.
@@ -110,26 +113,26 @@ typedef struct {
/// Header Data Directories.
///
typedef struct {
- UINT32 VirtualAddress;
- UINT32 Size;
+ UINT32 VirtualAddress;
+ UINT32 Size;
} EFI_IMAGE_DATA_DIRECTORY;
//
// Directory Entries
//
-#define EFI_IMAGE_DIRECTORY_ENTRY_EXPORT 0
-#define EFI_IMAGE_DIRECTORY_ENTRY_IMPORT 1
-#define EFI_IMAGE_DIRECTORY_ENTRY_RESOURCE 2
-#define EFI_IMAGE_DIRECTORY_ENTRY_EXCEPTION 3
-#define EFI_IMAGE_DIRECTORY_ENTRY_SECURITY 4
-#define EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC 5
-#define EFI_IMAGE_DIRECTORY_ENTRY_DEBUG 6
-#define EFI_IMAGE_DIRECTORY_ENTRY_COPYRIGHT 7
-#define EFI_IMAGE_DIRECTORY_ENTRY_GLOBALPTR 8
-#define EFI_IMAGE_DIRECTORY_ENTRY_TLS 9
-#define EFI_IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG 10
+#define EFI_IMAGE_DIRECTORY_ENTRY_EXPORT 0
+#define EFI_IMAGE_DIRECTORY_ENTRY_IMPORT 1
+#define EFI_IMAGE_DIRECTORY_ENTRY_RESOURCE 2
+#define EFI_IMAGE_DIRECTORY_ENTRY_EXCEPTION 3
+#define EFI_IMAGE_DIRECTORY_ENTRY_SECURITY 4
+#define EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC 5
+#define EFI_IMAGE_DIRECTORY_ENTRY_DEBUG 6
+#define EFI_IMAGE_DIRECTORY_ENTRY_COPYRIGHT 7
+#define EFI_IMAGE_DIRECTORY_ENTRY_GLOBALPTR 8
+#define EFI_IMAGE_DIRECTORY_ENTRY_TLS 9
+#define EFI_IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG 10
-#define EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES 16
+#define EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES 16
///
/// @attention
@@ -137,7 +140,7 @@ typedef struct {
/// EFI_IMAGE_OPTIONAL_HEADER32 must be used. The data structures only vary
/// after NT additional fields.
///
-#define EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC 0x10b
+#define EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC 0x10b
///
/// Optional Header Standard Fields for PE32.
@@ -146,40 +149,40 @@ typedef struct {
///
/// Standard fields.
///
- UINT16 Magic;
- UINT8 MajorLinkerVersion;
- UINT8 MinorLinkerVersion;
- UINT32 SizeOfCode;
- UINT32 SizeOfInitializedData;
- UINT32 SizeOfUninitializedData;
- UINT32 AddressOfEntryPoint;
- UINT32 BaseOfCode;
- UINT32 BaseOfData; ///< PE32 contains this additional field, which is absent in PE32+.
+ UINT16 Magic;
+ UINT8 MajorLinkerVersion;
+ UINT8 MinorLinkerVersion;
+ UINT32 SizeOfCode;
+ UINT32 SizeOfInitializedData;
+ UINT32 SizeOfUninitializedData;
+ UINT32 AddressOfEntryPoint;
+ UINT32 BaseOfCode;
+ UINT32 BaseOfData; ///< PE32 contains this additional field, which is absent in PE32+.
///
/// Optional Header Windows-Specific Fields.
///
- UINT32 ImageBase;
- UINT32 SectionAlignment;
- UINT32 FileAlignment;
- UINT16 MajorOperatingSystemVersion;
- UINT16 MinorOperatingSystemVersion;
- UINT16 MajorImageVersion;
- UINT16 MinorImageVersion;
- UINT16 MajorSubsystemVersion;
- UINT16 MinorSubsystemVersion;
- UINT32 Win32VersionValue;
- UINT32 SizeOfImage;
- UINT32 SizeOfHeaders;
- UINT32 CheckSum;
- UINT16 Subsystem;
- UINT16 DllCharacteristics;
- UINT32 SizeOfStackReserve;
- UINT32 SizeOfStackCommit;
- UINT32 SizeOfHeapReserve;
- UINT32 SizeOfHeapCommit;
- UINT32 LoaderFlags;
- UINT32 NumberOfRvaAndSizes;
- EFI_IMAGE_DATA_DIRECTORY DataDirectory[EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES];
+ UINT32 ImageBase;
+ UINT32 SectionAlignment;
+ UINT32 FileAlignment;
+ UINT16 MajorOperatingSystemVersion;
+ UINT16 MinorOperatingSystemVersion;
+ UINT16 MajorImageVersion;
+ UINT16 MinorImageVersion;
+ UINT16 MajorSubsystemVersion;
+ UINT16 MinorSubsystemVersion;
+ UINT32 Win32VersionValue;
+ UINT32 SizeOfImage;
+ UINT32 SizeOfHeaders;
+ UINT32 CheckSum;
+ UINT16 Subsystem;
+ UINT16 DllCharacteristics;
+ UINT32 SizeOfStackReserve;
+ UINT32 SizeOfStackCommit;
+ UINT32 SizeOfHeapReserve;
+ UINT32 SizeOfHeapCommit;
+ UINT32 LoaderFlags;
+ UINT32 NumberOfRvaAndSizes;
+ EFI_IMAGE_DATA_DIRECTORY DataDirectory[EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES];
} EFI_IMAGE_OPTIONAL_HEADER32;
///
@@ -188,7 +191,7 @@ typedef struct {
/// EFI_IMAGE_OPTIONAL_HEADER64 must be used. The data structures only vary
/// after NT additional fields.
///
-#define EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC 0x20b
+#define EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC 0x20b
///
/// Optional Header Standard Fields for PE32+.
@@ -197,166 +200,180 @@ typedef struct {
///
/// Standard fields.
///
- UINT16 Magic;
- UINT8 MajorLinkerVersion;
- UINT8 MinorLinkerVersion;
- UINT32 SizeOfCode;
- UINT32 SizeOfInitializedData;
- UINT32 SizeOfUninitializedData;
- UINT32 AddressOfEntryPoint;
- UINT32 BaseOfCode;
+ UINT16 Magic;
+ UINT8 MajorLinkerVersion;
+ UINT8 MinorLinkerVersion;
+ UINT32 SizeOfCode;
+ UINT32 SizeOfInitializedData;
+ UINT32 SizeOfUninitializedData;
+ UINT32 AddressOfEntryPoint;
+ UINT32 BaseOfCode;
///
/// Optional Header Windows-Specific Fields.
///
- UINT64 ImageBase;
- UINT32 SectionAlignment;
- UINT32 FileAlignment;
- UINT16 MajorOperatingSystemVersion;
- UINT16 MinorOperatingSystemVersion;
- UINT16 MajorImageVersion;
- UINT16 MinorImageVersion;
- UINT16 MajorSubsystemVersion;
- UINT16 MinorSubsystemVersion;
- UINT32 Win32VersionValue;
- UINT32 SizeOfImage;
- UINT32 SizeOfHeaders;
- UINT32 CheckSum;
- UINT16 Subsystem;
- UINT16 DllCharacteristics;
- UINT64 SizeOfStackReserve;
- UINT64 SizeOfStackCommit;
- UINT64 SizeOfHeapReserve;
- UINT64 SizeOfHeapCommit;
- UINT32 LoaderFlags;
- UINT32 NumberOfRvaAndSizes;
- EFI_IMAGE_DATA_DIRECTORY DataDirectory[EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES];
+ UINT64 ImageBase;
+ UINT32 SectionAlignment;
+ UINT32 FileAlignment;
+ UINT16 MajorOperatingSystemVersion;
+ UINT16 MinorOperatingSystemVersion;
+ UINT16 MajorImageVersion;
+ UINT16 MinorImageVersion;
+ UINT16 MajorSubsystemVersion;
+ UINT16 MinorSubsystemVersion;
+ UINT32 Win32VersionValue;
+ UINT32 SizeOfImage;
+ UINT32 SizeOfHeaders;
+ UINT32 CheckSum;
+ UINT16 Subsystem;
+ UINT16 DllCharacteristics;
+ UINT64 SizeOfStackReserve;
+ UINT64 SizeOfStackCommit;
+ UINT64 SizeOfHeapReserve;
+ UINT64 SizeOfHeapCommit;
+ UINT32 LoaderFlags;
+ UINT32 NumberOfRvaAndSizes;
+ EFI_IMAGE_DATA_DIRECTORY DataDirectory[EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES];
} EFI_IMAGE_OPTIONAL_HEADER64;
-
///
/// @attention
/// EFI_IMAGE_NT_HEADERS32 is for use ONLY by tools.
///
typedef struct {
- UINT32 Signature;
- EFI_IMAGE_FILE_HEADER FileHeader;
- EFI_IMAGE_OPTIONAL_HEADER32 OptionalHeader;
+ UINT32 Signature;
+ EFI_IMAGE_FILE_HEADER FileHeader;
+ EFI_IMAGE_OPTIONAL_HEADER32 OptionalHeader;
} EFI_IMAGE_NT_HEADERS32;
-#define EFI_IMAGE_SIZEOF_NT_OPTIONAL32_HEADER sizeof (EFI_IMAGE_NT_HEADERS32)
+#define EFI_IMAGE_SIZEOF_NT_OPTIONAL32_HEADER sizeof (EFI_IMAGE_NT_HEADERS32)
///
/// @attention
/// EFI_IMAGE_HEADERS64 is for use ONLY by tools.
///
typedef struct {
- UINT32 Signature;
- EFI_IMAGE_FILE_HEADER FileHeader;
- EFI_IMAGE_OPTIONAL_HEADER64 OptionalHeader;
+ UINT32 Signature;
+ EFI_IMAGE_FILE_HEADER FileHeader;
+ EFI_IMAGE_OPTIONAL_HEADER64 OptionalHeader;
} EFI_IMAGE_NT_HEADERS64;
-#define EFI_IMAGE_SIZEOF_NT_OPTIONAL64_HEADER sizeof (EFI_IMAGE_NT_HEADERS64)
+#define EFI_IMAGE_SIZEOF_NT_OPTIONAL64_HEADER sizeof (EFI_IMAGE_NT_HEADERS64)
//
// Other Windows Subsystem Values
//
-#define EFI_IMAGE_SUBSYSTEM_UNKNOWN 0
-#define EFI_IMAGE_SUBSYSTEM_NATIVE 1
-#define EFI_IMAGE_SUBSYSTEM_WINDOWS_GUI 2
-#define EFI_IMAGE_SUBSYSTEM_WINDOWS_CUI 3
-#define EFI_IMAGE_SUBSYSTEM_OS2_CUI 5
-#define EFI_IMAGE_SUBSYSTEM_POSIX_CUI 7
+#define EFI_IMAGE_SUBSYSTEM_UNKNOWN 0
+#define EFI_IMAGE_SUBSYSTEM_NATIVE 1
+#define EFI_IMAGE_SUBSYSTEM_WINDOWS_GUI 2
+#define EFI_IMAGE_SUBSYSTEM_WINDOWS_CUI 3
+#define EFI_IMAGE_SUBSYSTEM_OS2_CUI 5
+#define EFI_IMAGE_SUBSYSTEM_POSIX_CUI 7
+
+//
+// DLL Characteristics
+//
+#define IMAGE_DLLCHARACTERISTICS_HIGH_ENTROPY_VA 0x0020
+#define IMAGE_DLLCHARACTERISTICS_DYNAMIC_BASE 0x0040
+#define IMAGE_DLLCHARACTERISTICS_FORCE_INTEGRITY 0x0080
+#define IMAGE_DLLCHARACTERISTICS_NX_COMPAT 0x0100
+#define IMAGE_DLLCHARACTERISTICS_NO_ISOLATION 0x0200
+#define IMAGE_DLLCHARACTERISTICS_NO_SEH 0x0400
+#define IMAGE_DLLCHARACTERISTICS_NO_BIND 0x0800
+#define IMAGE_DLLCHARACTERISTICS_APPCONTAINER 0x1000
+#define IMAGE_DLLCHARACTERISTICS_WDM_DRIVER 0x2000
+#define IMAGE_DLLCHARACTERISTICS_GUARD_CF 0x4000
+#define IMAGE_DLLCHARACTERISTICS_TERMINAL_SERVER_AWARE 0x8000
///
/// Length of ShortName.
///
-#define EFI_IMAGE_SIZEOF_SHORT_NAME 8
+#define EFI_IMAGE_SIZEOF_SHORT_NAME 8
///
/// Section Table. This table immediately follows the optional header.
///
typedef struct {
- UINT8 Name[EFI_IMAGE_SIZEOF_SHORT_NAME];
+ UINT8 Name[EFI_IMAGE_SIZEOF_SHORT_NAME];
union {
- UINT32 PhysicalAddress;
- UINT32 VirtualSize;
+ UINT32 PhysicalAddress;
+ UINT32 VirtualSize;
} Misc;
- UINT32 VirtualAddress;
- UINT32 SizeOfRawData;
- UINT32 PointerToRawData;
- UINT32 PointerToRelocations;
- UINT32 PointerToLinenumbers;
- UINT16 NumberOfRelocations;
- UINT16 NumberOfLinenumbers;
- UINT32 Characteristics;
+ UINT32 VirtualAddress;
+ UINT32 SizeOfRawData;
+ UINT32 PointerToRawData;
+ UINT32 PointerToRelocations;
+ UINT32 PointerToLinenumbers;
+ UINT16 NumberOfRelocations;
+ UINT16 NumberOfLinenumbers;
+ UINT32 Characteristics;
} EFI_IMAGE_SECTION_HEADER;
///
/// Size of EFI_IMAGE_SECTION_HEADER.
///
-#define EFI_IMAGE_SIZEOF_SECTION_HEADER 40
+#define EFI_IMAGE_SIZEOF_SECTION_HEADER 40
//
// Section Flags Values
//
-#define EFI_IMAGE_SCN_TYPE_NO_PAD BIT3 ///< 0x00000008 ///< Reserved.
-#define EFI_IMAGE_SCN_CNT_CODE BIT5 ///< 0x00000020
-#define EFI_IMAGE_SCN_CNT_INITIALIZED_DATA BIT6 ///< 0x00000040
-#define EFI_IMAGE_SCN_CNT_UNINITIALIZED_DATA BIT7 ///< 0x00000080
+#define EFI_IMAGE_SCN_TYPE_NO_PAD BIT3 ///< 0x00000008 ///< Reserved.
+#define EFI_IMAGE_SCN_CNT_CODE BIT5 ///< 0x00000020
+#define EFI_IMAGE_SCN_CNT_INITIALIZED_DATA BIT6 ///< 0x00000040
+#define EFI_IMAGE_SCN_CNT_UNINITIALIZED_DATA BIT7 ///< 0x00000080
-#define EFI_IMAGE_SCN_LNK_OTHER BIT8 ///< 0x00000100 ///< Reserved.
-#define EFI_IMAGE_SCN_LNK_INFO BIT9 ///< 0x00000200 ///< Section contains comments or some other type of information.
-#define EFI_IMAGE_SCN_LNK_REMOVE BIT11 ///< 0x00000800 ///< Section contents will not become part of image.
-#define EFI_IMAGE_SCN_LNK_COMDAT BIT12 ///< 0x00001000
+#define EFI_IMAGE_SCN_LNK_OTHER BIT8 ///< 0x00000100 ///< Reserved.
+#define EFI_IMAGE_SCN_LNK_INFO BIT9 ///< 0x00000200 ///< Section contains comments or some other type of information.
+#define EFI_IMAGE_SCN_LNK_REMOVE BIT11 ///< 0x00000800 ///< Section contents will not become part of image.
+#define EFI_IMAGE_SCN_LNK_COMDAT BIT12 ///< 0x00001000
-#define EFI_IMAGE_SCN_ALIGN_1BYTES BIT20 ///< 0x00100000
-#define EFI_IMAGE_SCN_ALIGN_2BYTES BIT21 ///< 0x00200000
-#define EFI_IMAGE_SCN_ALIGN_4BYTES (BIT20|BIT21) ///< 0x00300000
-#define EFI_IMAGE_SCN_ALIGN_8BYTES BIT22 ///< 0x00400000
-#define EFI_IMAGE_SCN_ALIGN_16BYTES (BIT20|BIT22) ///< 0x00500000
-#define EFI_IMAGE_SCN_ALIGN_32BYTES (BIT21|BIT22) ///< 0x00600000
-#define EFI_IMAGE_SCN_ALIGN_64BYTES (BIT20|BIT21|BIT22) ///< 0x00700000
+#define EFI_IMAGE_SCN_ALIGN_1BYTES BIT20 ///< 0x00100000
+#define EFI_IMAGE_SCN_ALIGN_2BYTES BIT21 ///< 0x00200000
+#define EFI_IMAGE_SCN_ALIGN_4BYTES (BIT20|BIT21) ///< 0x00300000
+#define EFI_IMAGE_SCN_ALIGN_8BYTES BIT22 ///< 0x00400000
+#define EFI_IMAGE_SCN_ALIGN_16BYTES (BIT20|BIT22) ///< 0x00500000
+#define EFI_IMAGE_SCN_ALIGN_32BYTES (BIT21|BIT22) ///< 0x00600000
+#define EFI_IMAGE_SCN_ALIGN_64BYTES (BIT20|BIT21|BIT22) ///< 0x00700000
-#define EFI_IMAGE_SCN_MEM_DISCARDABLE BIT25 ///< 0x02000000
-#define EFI_IMAGE_SCN_MEM_NOT_CACHED BIT26 ///< 0x04000000
-#define EFI_IMAGE_SCN_MEM_NOT_PAGED BIT27 ///< 0x08000000
-#define EFI_IMAGE_SCN_MEM_SHARED BIT28 ///< 0x10000000
-#define EFI_IMAGE_SCN_MEM_EXECUTE BIT29 ///< 0x20000000
-#define EFI_IMAGE_SCN_MEM_READ BIT30 ///< 0x40000000
-#define EFI_IMAGE_SCN_MEM_WRITE BIT31 ///< 0x80000000
+#define EFI_IMAGE_SCN_MEM_DISCARDABLE BIT25 ///< 0x02000000
+#define EFI_IMAGE_SCN_MEM_NOT_CACHED BIT26 ///< 0x04000000
+#define EFI_IMAGE_SCN_MEM_NOT_PAGED BIT27 ///< 0x08000000
+#define EFI_IMAGE_SCN_MEM_SHARED BIT28 ///< 0x10000000
+#define EFI_IMAGE_SCN_MEM_EXECUTE BIT29 ///< 0x20000000
+#define EFI_IMAGE_SCN_MEM_READ BIT30 ///< 0x40000000
+#define EFI_IMAGE_SCN_MEM_WRITE BIT31 ///< 0x80000000
///
/// Size of a Symbol Table Record.
///
-#define EFI_IMAGE_SIZEOF_SYMBOL 18
+#define EFI_IMAGE_SIZEOF_SYMBOL 18
//
// Symbols have a section number of the section in which they are
// defined. Otherwise, section numbers have the following meanings:
//
-#define EFI_IMAGE_SYM_UNDEFINED (UINT16) 0 ///< Symbol is undefined or is common.
-#define EFI_IMAGE_SYM_ABSOLUTE (UINT16) -1 ///< Symbol is an absolute value.
-#define EFI_IMAGE_SYM_DEBUG (UINT16) -2 ///< Symbol is a special debug item.
+#define EFI_IMAGE_SYM_UNDEFINED (UINT16) 0 ///< Symbol is undefined or is common.
+#define EFI_IMAGE_SYM_ABSOLUTE (UINT16) -1 ///< Symbol is an absolute value.
+#define EFI_IMAGE_SYM_DEBUG (UINT16) -2 ///< Symbol is a special debug item.
//
// Symbol Type (fundamental) values.
//
-#define EFI_IMAGE_SYM_TYPE_NULL 0 ///< no type.
-#define EFI_IMAGE_SYM_TYPE_VOID 1 ///< no valid type.
-#define EFI_IMAGE_SYM_TYPE_CHAR 2 ///< type character.
-#define EFI_IMAGE_SYM_TYPE_SHORT 3 ///< type short integer.
-#define EFI_IMAGE_SYM_TYPE_INT 4
-#define EFI_IMAGE_SYM_TYPE_LONG 5
-#define EFI_IMAGE_SYM_TYPE_FLOAT 6
-#define EFI_IMAGE_SYM_TYPE_DOUBLE 7
-#define EFI_IMAGE_SYM_TYPE_STRUCT 8
-#define EFI_IMAGE_SYM_TYPE_UNION 9
-#define EFI_IMAGE_SYM_TYPE_ENUM 10 ///< enumeration.
-#define EFI_IMAGE_SYM_TYPE_MOE 11 ///< member of enumeration.
-#define EFI_IMAGE_SYM_TYPE_BYTE 12
-#define EFI_IMAGE_SYM_TYPE_WORD 13
-#define EFI_IMAGE_SYM_TYPE_UINT 14
-#define EFI_IMAGE_SYM_TYPE_DWORD 15
+#define EFI_IMAGE_SYM_TYPE_NULL 0 ///< no type.
+#define EFI_IMAGE_SYM_TYPE_VOID 1 ///< no valid type.
+#define EFI_IMAGE_SYM_TYPE_CHAR 2 ///< type character.
+#define EFI_IMAGE_SYM_TYPE_SHORT 3 ///< type short integer.
+#define EFI_IMAGE_SYM_TYPE_INT 4
+#define EFI_IMAGE_SYM_TYPE_LONG 5
+#define EFI_IMAGE_SYM_TYPE_FLOAT 6
+#define EFI_IMAGE_SYM_TYPE_DOUBLE 7
+#define EFI_IMAGE_SYM_TYPE_STRUCT 8
+#define EFI_IMAGE_SYM_TYPE_UNION 9
+#define EFI_IMAGE_SYM_TYPE_ENUM 10 ///< enumeration.
+#define EFI_IMAGE_SYM_TYPE_MOE 11 ///< member of enumeration.
+#define EFI_IMAGE_SYM_TYPE_BYTE 12
+#define EFI_IMAGE_SYM_TYPE_WORD 13
+#define EFI_IMAGE_SYM_TYPE_UINT 14
+#define EFI_IMAGE_SYM_TYPE_DWORD 15
//
// Symbol Type (derived) values.
@@ -409,11 +426,11 @@ typedef struct {
//
// Communal selection types.
//
-#define EFI_IMAGE_COMDAT_SELECT_NODUPLICATES 1
-#define EFI_IMAGE_COMDAT_SELECT_ANY 2
-#define EFI_IMAGE_COMDAT_SELECT_SAME_SIZE 3
-#define EFI_IMAGE_COMDAT_SELECT_EXACT_MATCH 4
-#define EFI_IMAGE_COMDAT_SELECT_ASSOCIATIVE 5
+#define EFI_IMAGE_COMDAT_SELECT_NODUPLICATES 1
+#define EFI_IMAGE_COMDAT_SELECT_ANY 2
+#define EFI_IMAGE_COMDAT_SELECT_SAME_SIZE 3
+#define EFI_IMAGE_COMDAT_SELECT_EXACT_MATCH 4
+#define EFI_IMAGE_COMDAT_SELECT_ASSOCIATIVE 5
//
// the following values only be referred in PeCoff, not defined in PECOFF.
@@ -426,28 +443,28 @@ typedef struct {
/// Relocation format.
///
typedef struct {
- UINT32 VirtualAddress;
- UINT32 SymbolTableIndex;
- UINT16 Type;
+ UINT32 VirtualAddress;
+ UINT32 SymbolTableIndex;
+ UINT16 Type;
} EFI_IMAGE_RELOCATION;
///
/// Size of EFI_IMAGE_RELOCATION
///
-#define EFI_IMAGE_SIZEOF_RELOCATION 10
+#define EFI_IMAGE_SIZEOF_RELOCATION 10
//
// I386 relocation types.
//
-#define EFI_IMAGE_REL_I386_ABSOLUTE 0x0000 ///< Reference is absolute, no relocation is necessary.
-#define EFI_IMAGE_REL_I386_DIR16 0x0001 ///< Direct 16-bit reference to the symbols virtual address.
-#define EFI_IMAGE_REL_I386_REL16 0x0002 ///< PC-relative 16-bit reference to the symbols virtual address.
-#define EFI_IMAGE_REL_I386_DIR32 0x0006 ///< Direct 32-bit reference to the symbols virtual address.
-#define EFI_IMAGE_REL_I386_DIR32NB 0x0007 ///< Direct 32-bit reference to the symbols virtual address, base not included.
-#define EFI_IMAGE_REL_I386_SEG12 0x0009 ///< Direct 16-bit reference to the segment-selector bits of a 32-bit virtual address.
-#define EFI_IMAGE_REL_I386_SECTION 0x000A
-#define EFI_IMAGE_REL_I386_SECREL 0x000B
-#define EFI_IMAGE_REL_I386_REL32 0x0014 ///< PC-relative 32-bit reference to the symbols virtual address.
+#define EFI_IMAGE_REL_I386_ABSOLUTE 0x0000 ///< Reference is absolute, no relocation is necessary.
+#define EFI_IMAGE_REL_I386_DIR16 0x0001 ///< Direct 16-bit reference to the symbols virtual address.
+#define EFI_IMAGE_REL_I386_REL16 0x0002 ///< PC-relative 16-bit reference to the symbols virtual address.
+#define EFI_IMAGE_REL_I386_DIR32 0x0006 ///< Direct 32-bit reference to the symbols virtual address.
+#define EFI_IMAGE_REL_I386_DIR32NB 0x0007 ///< Direct 32-bit reference to the symbols virtual address, base not included.
+#define EFI_IMAGE_REL_I386_SEG12 0x0009 ///< Direct 16-bit reference to the segment-selector bits of a 32-bit virtual address.
+#define EFI_IMAGE_REL_I386_SECTION 0x000A
+#define EFI_IMAGE_REL_I386_SECREL 0x000B
+#define EFI_IMAGE_REL_I386_REL32 0x0014 ///< PC-relative 32-bit reference to the symbols virtual address.
//
// x64 processor relocation types.
@@ -474,8 +491,8 @@ typedef struct {
/// Based relocation format.
///
typedef struct {
- UINT32 VirtualAddress;
- UINT32 SizeOfBlock;
+ UINT32 VirtualAddress;
+ UINT32 SizeOfBlock;
} EFI_IMAGE_BASE_RELOCATION;
///
@@ -501,25 +518,31 @@ typedef struct {
///
/// Relocation types of RISC-V processor.
///
-#define EFI_IMAGE_REL_BASED_RISCV_HI20 5
-#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7
-#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8
+#define EFI_IMAGE_REL_BASED_RISCV_HI20 5
+#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7
+#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8
+
+//
+// Relocation types of LoongArch processor.
+//
+#define EFI_IMAGE_REL_BASED_LOONGARCH32_MARK_LA 8
+#define EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA 8
///
/// Line number format.
///
typedef struct {
union {
- UINT32 SymbolTableIndex; ///< Symbol table index of function name if Linenumber is 0.
- UINT32 VirtualAddress; ///< Virtual address of line number.
+ UINT32 SymbolTableIndex; ///< Symbol table index of function name if Linenumber is 0.
+ UINT32 VirtualAddress; ///< Virtual address of line number.
} Type;
- UINT16 Linenumber; ///< Line number.
+ UINT16 Linenumber; ///< Line number.
} EFI_IMAGE_LINENUMBER;
///
/// Size of EFI_IMAGE_LINENUMBER.
///
-#define EFI_IMAGE_SIZEOF_LINENUMBER 6
+#define EFI_IMAGE_SIZEOF_LINENUMBER 6
//
// Archive format.
@@ -535,20 +558,19 @@ typedef struct {
/// Archive Member Headers
///
typedef struct {
- UINT8 Name[16]; ///< File member name - `/' terminated.
- UINT8 Date[12]; ///< File member date - decimal.
- UINT8 UserID[6]; ///< File member user id - decimal.
- UINT8 GroupID[6]; ///< File member group id - decimal.
- UINT8 Mode[8]; ///< File member mode - octal.
- UINT8 Size[10]; ///< File member size - decimal.
- UINT8 EndHeader[2]; ///< String to end header. (0x60 0x0A).
+ UINT8 Name[16]; ///< File member name - `/' terminated.
+ UINT8 Date[12]; ///< File member date - decimal.
+ UINT8 UserID[6]; ///< File member user id - decimal.
+ UINT8 GroupID[6]; ///< File member group id - decimal.
+ UINT8 Mode[8]; ///< File member mode - octal.
+ UINT8 Size[10]; ///< File member size - decimal.
+ UINT8 EndHeader[2]; ///< String to end header. (0x60 0x0A).
} EFI_IMAGE_ARCHIVE_MEMBER_HEADER;
///
/// Size of EFI_IMAGE_ARCHIVE_MEMBER_HEADER.
///
-#define EFI_IMAGE_SIZEOF_ARCHIVE_MEMBER_HDR 60
-
+#define EFI_IMAGE_SIZEOF_ARCHIVE_MEMBER_HDR 60
//
// DLL Support
@@ -558,25 +580,32 @@ typedef struct {
/// Export Directory Table.
///
typedef struct {
- UINT32 Characteristics;
- UINT32 TimeDateStamp;
- UINT16 MajorVersion;
- UINT16 MinorVersion;
- UINT32 Name;
- UINT32 Base;
- UINT32 NumberOfFunctions;
- UINT32 NumberOfNames;
- UINT32 AddressOfFunctions;
- UINT32 AddressOfNames;
- UINT32 AddressOfNameOrdinals;
+ UINT32 Characteristics;
+ UINT32 TimeDateStamp;
+ UINT16 MajorVersion;
+ UINT16 MinorVersion;
+ UINT32 Name;
+ UINT32 Base;
+ UINT32 NumberOfFunctions;
+ UINT32 NumberOfNames;
+ UINT32 AddressOfFunctions;
+ UINT32 AddressOfNames;
+ UINT32 AddressOfNameOrdinals;
} EFI_IMAGE_EXPORT_DIRECTORY;
+//
+// Based export types.
+//
+#define EFI_IMAGE_EXPORT_ORDINAL_BASE 1
+#define EFI_IMAGE_EXPORT_ADDR_SIZE 4
+#define EFI_IMAGE_EXPORT_ORDINAL_SIZE 2
+
///
/// Hint/Name Table.
///
typedef struct {
- UINT16 Hint;
- UINT8 Name[1];
+ UINT16 Hint;
+ UINT8 Name[1];
} EFI_IMAGE_IMPORT_BY_NAME;
///
@@ -584,13 +613,13 @@ typedef struct {
///
typedef struct {
union {
- UINT32 Function;
- UINT32 Ordinal;
- EFI_IMAGE_IMPORT_BY_NAME *AddressOfData;
+ UINT32 Function;
+ UINT32 Ordinal;
+ EFI_IMAGE_IMPORT_BY_NAME *AddressOfData;
} u1;
} EFI_IMAGE_THUNK_DATA;
-#define EFI_IMAGE_ORDINAL_FLAG BIT31 ///< Flag for PE32.
+#define EFI_IMAGE_ORDINAL_FLAG BIT31 ///< Flag for PE32.
#define EFI_IMAGE_SNAP_BY_ORDINAL(Ordinal) ((Ordinal & EFI_IMAGE_ORDINAL_FLAG) != 0)
#define EFI_IMAGE_ORDINAL(Ordinal) (Ordinal & 0xffff)
@@ -598,39 +627,39 @@ typedef struct {
/// Import Directory Table
///
typedef struct {
- UINT32 Characteristics;
- UINT32 TimeDateStamp;
- UINT32 ForwarderChain;
- UINT32 Name;
- EFI_IMAGE_THUNK_DATA *FirstThunk;
+ UINT32 Characteristics;
+ UINT32 TimeDateStamp;
+ UINT32 ForwarderChain;
+ UINT32 Name;
+ EFI_IMAGE_THUNK_DATA *FirstThunk;
} EFI_IMAGE_IMPORT_DESCRIPTOR;
-
///
/// Debug Directory Format.
///
typedef struct {
- UINT32 Characteristics;
- UINT32 TimeDateStamp;
- UINT16 MajorVersion;
- UINT16 MinorVersion;
- UINT32 Type;
- UINT32 SizeOfData;
- UINT32 RVA; ///< The address of the debug data when loaded, relative to the image base.
- UINT32 FileOffset; ///< The file pointer to the debug data.
+ UINT32 Characteristics;
+ UINT32 TimeDateStamp;
+ UINT16 MajorVersion;
+ UINT16 MinorVersion;
+ UINT32 Type;
+ UINT32 SizeOfData;
+ UINT32 RVA; ///< The address of the debug data when loaded, relative to the image base.
+ UINT32 FileOffset; ///< The file pointer to the debug data.
} EFI_IMAGE_DEBUG_DIRECTORY_ENTRY;
-#define EFI_IMAGE_DEBUG_TYPE_CODEVIEW 2 ///< The Visual C++ debug information.
+#define EFI_IMAGE_DEBUG_TYPE_CODEVIEW 2 ///< The Visual C++ debug information.
+#define EFI_IMAGE_DEBUG_TYPE_EX_DLLCHARACTERISTICS 20
///
/// Debug Data Structure defined in Microsoft C++.
///
#define CODEVIEW_SIGNATURE_NB10 SIGNATURE_32('N', 'B', '1', '0')
typedef struct {
- UINT32 Signature; ///< "NB10"
- UINT32 Unknown;
- UINT32 Unknown2;
- UINT32 Unknown3;
+ UINT32 Signature; ///< "NB10"
+ UINT32 Unknown;
+ UINT32 Unknown2;
+ UINT32 Unknown3;
//
// Filename of .PDB goes here
//
@@ -641,18 +670,17 @@ typedef struct {
///
#define CODEVIEW_SIGNATURE_RSDS SIGNATURE_32('R', 'S', 'D', 'S')
typedef struct {
- UINT32 Signature; ///< "RSDS".
- UINT32 Unknown;
- UINT32 Unknown2;
- UINT32 Unknown3;
- UINT32 Unknown4;
- UINT32 Unknown5;
+ UINT32 Signature; ///< "RSDS".
+ UINT32 Unknown;
+ UINT32 Unknown2;
+ UINT32 Unknown3;
+ UINT32 Unknown4;
+ UINT32 Unknown5;
//
// Filename of .PDB goes here
//
} EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY;
-
///
/// Debug Data Structure defined by Apple Mach-O to Coff utility.
///
@@ -665,16 +693,44 @@ typedef struct {
//
} EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY;
+//
+// .pdata entries for X64
+//
+typedef struct {
+ UINT32 FunctionStartAddress;
+ UINT32 FunctionEndAddress;
+ UINT32 UnwindInfoAddress;
+} RUNTIME_FUNCTION;
+
+typedef struct {
+ UINT8 Version : 3;
+ UINT8 Flags : 5;
+ UINT8 SizeOfProlog;
+ UINT8 CountOfUnwindCodes;
+ UINT8 FrameRegister : 4;
+ UINT8 FrameRegisterOffset : 4;
+} UNWIND_INFO;
+
+///
+/// Extended DLL Characteristics
+///
+#define EFI_IMAGE_DLLCHARACTERISTICS_EX_CET_COMPAT 0x0001
+#define EFI_IMAGE_DLLCHARACTERISTICS_EX_FORWARD_CFI_COMPAT 0x0040
+
+typedef struct {
+ UINT32 DllCharacteristicsEx;
+} EFI_IMAGE_DEBUG_EX_DLLCHARACTERISTICS_ENTRY;
+
///
/// Resource format.
///
typedef struct {
- UINT32 Characteristics;
- UINT32 TimeDateStamp;
- UINT16 MajorVersion;
- UINT16 MinorVersion;
- UINT16 NumberOfNamedEntries;
- UINT16 NumberOfIdEntries;
+ UINT32 Characteristics;
+ UINT32 TimeDateStamp;
+ UINT16 MajorVersion;
+ UINT16 MinorVersion;
+ UINT16 NumberOfNamedEntries;
+ UINT16 NumberOfIdEntries;
//
// Array of EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY entries goes here.
//
@@ -686,16 +742,16 @@ typedef struct {
typedef struct {
union {
struct {
- UINT32 NameOffset:31;
- UINT32 NameIsString:1;
+ UINT32 NameOffset : 31;
+ UINT32 NameIsString : 1;
} s;
- UINT32 Id;
+ UINT32 Id;
} u1;
union {
- UINT32 OffsetToData;
+ UINT32 OffsetToData;
struct {
- UINT32 OffsetToDirectory:31;
- UINT32 DataIsDirectory:1;
+ UINT32 OffsetToDirectory : 31;
+ UINT32 DataIsDirectory : 1;
} s;
} u2;
} EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY;
@@ -704,36 +760,35 @@ typedef struct {
/// Resource directory entry for string.
///
typedef struct {
- UINT16 Length;
- CHAR16 String[1];
+ UINT16 Length;
+ CHAR16 String[1];
} EFI_IMAGE_RESOURCE_DIRECTORY_STRING;
///
/// Resource directory entry for data array.
///
typedef struct {
- UINT32 OffsetToData;
- UINT32 Size;
- UINT32 CodePage;
- UINT32 Reserved;
+ UINT32 OffsetToData;
+ UINT32 Size;
+ UINT32 CodePage;
+ UINT32 Reserved;
} EFI_IMAGE_RESOURCE_DATA_ENTRY;
///
/// Header format for TE images, defined in the PI Specification, 1.0.
///
typedef struct {
- UINT16 Signature; ///< The signature for TE format = "VZ".
- UINT16 Machine; ///< From the original file header.
- UINT8 NumberOfSections; ///< From the original file header.
- UINT8 Subsystem; ///< From original optional header.
- UINT16 StrippedSize; ///< Number of bytes we removed from the header.
- UINT32 AddressOfEntryPoint; ///< Offset to entry point -- from original optional header.
- UINT32 BaseOfCode; ///< From original image -- required for ITP debug.
- UINT64 ImageBase; ///< From original file header.
- EFI_IMAGE_DATA_DIRECTORY DataDirectory[2]; ///< Only base relocation and debug directory.
+ UINT16 Signature; ///< The signature for TE format = "VZ".
+ UINT16 Machine; ///< From the original file header.
+ UINT8 NumberOfSections; ///< From the original file header.
+ UINT8 Subsystem; ///< From original optional header.
+ UINT16 StrippedSize; ///< Number of bytes we removed from the header.
+ UINT32 AddressOfEntryPoint; ///< Offset to entry point -- from original optional header.
+ UINT32 BaseOfCode; ///< From original image -- required for ITP debug.
+ UINT64 ImageBase; ///< From original file header.
+ EFI_IMAGE_DATA_DIRECTORY DataDirectory[2]; ///< Only base relocation and debug directory.
} EFI_TE_IMAGE_HEADER;
-
#define EFI_TE_IMAGE_HEADER_SIGNATURE SIGNATURE_16('V', 'Z')
//
@@ -742,21 +797,20 @@ typedef struct {
#define EFI_TE_IMAGE_DIRECTORY_ENTRY_BASERELOC 0
#define EFI_TE_IMAGE_DIRECTORY_ENTRY_DEBUG 1
-
///
/// Union of PE32, PE32+, and TE headers.
///
typedef union {
- EFI_IMAGE_NT_HEADERS32 Pe32;
- EFI_IMAGE_NT_HEADERS64 Pe32Plus;
- EFI_TE_IMAGE_HEADER Te;
+ EFI_IMAGE_NT_HEADERS32 Pe32;
+ EFI_IMAGE_NT_HEADERS64 Pe32Plus;
+ EFI_TE_IMAGE_HEADER Te;
} EFI_IMAGE_OPTIONAL_HEADER_UNION;
typedef union {
- EFI_IMAGE_NT_HEADERS32 *Pe32;
- EFI_IMAGE_NT_HEADERS64 *Pe32Plus;
- EFI_TE_IMAGE_HEADER *Te;
- EFI_IMAGE_OPTIONAL_HEADER_UNION *Union;
+ EFI_IMAGE_NT_HEADERS32 *Pe32;
+ EFI_IMAGE_NT_HEADERS64 *Pe32Plus;
+ EFI_TE_IMAGE_HEADER *Te;
+ EFI_IMAGE_OPTIONAL_HEADER_UNION *Union;
} EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION;
#endif
diff --git a/MdePkg/Include/IndustryStandard/Scsi.h b/MdePkg/Include/IndustryStandard/Scsi.h
index f49c55b0..2ce3722e 100644
--- a/MdePkg/Include/IndustryStandard/Scsi.h
+++ b/MdePkg/Include/IndustryStandard/Scsi.h
@@ -15,58 +15,58 @@
//
// Commands for all device types
//
-#define EFI_SCSI_OP_CHANGE_DEFINITION 0x40
-#define EFI_SCSI_OP_COMPARE 0x39
-#define EFI_SCSI_OP_COPY 0x18
-#define EFI_SCSI_OP_COPY_VERIFY 0x3a
-#define EFI_SCSI_OP_INQUIRY 0x12
-#define EFI_SCSI_OP_LOG_SELECT 0x4c
-#define EFI_SCSI_OP_LOG_SENSE 0x4d
-#define EFI_SCSI_OP_MODE_SEL6 0x15
-#define EFI_SCSI_OP_MODE_SEL10 0x55
-#define EFI_SCSI_OP_MODE_SEN6 0x1a
-#define EFI_SCSI_OP_MODE_SEN10 0x5a
-#define EFI_SCSI_OP_READ_BUFFER 0x3c
-#define EFI_SCSI_OP_RECEIVE_DIAG 0x1c
-#define EFI_SCSI_OP_REQUEST_SENSE 0x03
-#define EFI_SCSI_OP_SEND_DIAG 0x1d
-#define EFI_SCSI_OP_TEST_UNIT_READY 0x00
-#define EFI_SCSI_OP_WRITE_BUFF 0x3b
+#define EFI_SCSI_OP_CHANGE_DEFINITION 0x40
+#define EFI_SCSI_OP_COMPARE 0x39
+#define EFI_SCSI_OP_COPY 0x18
+#define EFI_SCSI_OP_COPY_VERIFY 0x3a
+#define EFI_SCSI_OP_INQUIRY 0x12
+#define EFI_SCSI_OP_LOG_SELECT 0x4c
+#define EFI_SCSI_OP_LOG_SENSE 0x4d
+#define EFI_SCSI_OP_MODE_SEL6 0x15
+#define EFI_SCSI_OP_MODE_SEL10 0x55
+#define EFI_SCSI_OP_MODE_SEN6 0x1a
+#define EFI_SCSI_OP_MODE_SEN10 0x5a
+#define EFI_SCSI_OP_READ_BUFFER 0x3c
+#define EFI_SCSI_OP_RECEIVE_DIAG 0x1c
+#define EFI_SCSI_OP_REQUEST_SENSE 0x03
+#define EFI_SCSI_OP_SEND_DIAG 0x1d
+#define EFI_SCSI_OP_TEST_UNIT_READY 0x00
+#define EFI_SCSI_OP_WRITE_BUFF 0x3b
//
// Additional commands for Direct Access Devices
//
-#define EFI_SCSI_OP_FORMAT 0x04
-#define EFI_SCSI_OP_LOCK_UN_CACHE 0x36
-#define EFI_SCSI_OP_PREFETCH 0x34
-#define EFI_SCSI_OP_MEDIA_REMOVAL 0x1e
-#define EFI_SCSI_OP_READ6 0x08
-#define EFI_SCSI_OP_READ10 0x28
-#define EFI_SCSI_OP_READ16 0x88
-#define EFI_SCSI_OP_READ_CAPACITY 0x25
-#define EFI_SCSI_OP_READ_CAPACITY16 0x9e
-#define EFI_SCSI_OP_READ_DEFECT 0x37
-#define EFI_SCSI_OP_READ_LONG 0x3e
-#define EFI_SCSI_OP_REASSIGN_BLK 0x07
-#define EFI_SCSI_OP_RELEASE 0x17
-#define EFI_SCSI_OP_REZERO 0x01
-#define EFI_SCSI_OP_SEARCH_DATA_E 0x31
-#define EFI_SCSI_OP_SEARCH_DATA_H 0x30
-#define EFI_SCSI_OP_SEARCH_DATA_L 0x32
-#define EFI_SCSI_OP_SEEK6 0x0b
-#define EFI_SCSI_OP_SEEK10 0x2b
-#define EFI_SCSI_OP_SEND_DIAG 0x1d
-#define EFI_SCSI_OP_SET_LIMIT 0x33
-#define EFI_SCSI_OP_START_STOP_UNIT 0x1b
-#define EFI_SCSI_OP_SYNC_CACHE 0x35
-#define EFI_SCSI_OP_VERIFY 0x2f
-#define EFI_SCSI_OP_WRITE6 0x0a
-#define EFI_SCSI_OP_WRITE10 0x2a
-#define EFI_SCSI_OP_WRITE16 0x8a
-#define EFI_SCSI_OP_WRITE_VERIFY 0x2e
-#define EFI_SCSI_OP_WRITE_LONG 0x3f
-#define EFI_SCSI_OP_WRITE_SAME 0x41
-#define EFI_SCSI_OP_UNMAP 0x42
+#define EFI_SCSI_OP_FORMAT 0x04
+#define EFI_SCSI_OP_LOCK_UN_CACHE 0x36
+#define EFI_SCSI_OP_PREFETCH 0x34
+#define EFI_SCSI_OP_MEDIA_REMOVAL 0x1e
+#define EFI_SCSI_OP_READ6 0x08
+#define EFI_SCSI_OP_READ10 0x28
+#define EFI_SCSI_OP_READ16 0x88
+#define EFI_SCSI_OP_READ_CAPACITY 0x25
+#define EFI_SCSI_OP_READ_CAPACITY16 0x9e
+#define EFI_SCSI_OP_READ_DEFECT 0x37
+#define EFI_SCSI_OP_READ_LONG 0x3e
+#define EFI_SCSI_OP_REASSIGN_BLK 0x07
+#define EFI_SCSI_OP_RELEASE 0x17
+#define EFI_SCSI_OP_REZERO 0x01
+#define EFI_SCSI_OP_SEARCH_DATA_E 0x31
+#define EFI_SCSI_OP_SEARCH_DATA_H 0x30
+#define EFI_SCSI_OP_SEARCH_DATA_L 0x32
+#define EFI_SCSI_OP_SEEK6 0x0b
+#define EFI_SCSI_OP_SEEK10 0x2b
+#define EFI_SCSI_OP_SEND_DIAG 0x1d
+#define EFI_SCSI_OP_SET_LIMIT 0x33
+#define EFI_SCSI_OP_START_STOP_UNIT 0x1b
+#define EFI_SCSI_OP_SYNC_CACHE 0x35
+#define EFI_SCSI_OP_VERIFY 0x2f
+#define EFI_SCSI_OP_WRITE6 0x0a
+#define EFI_SCSI_OP_WRITE10 0x2a
+#define EFI_SCSI_OP_WRITE16 0x8a
+#define EFI_SCSI_OP_WRITE_VERIFY 0x2e
+#define EFI_SCSI_OP_WRITE_LONG 0x3f
+#define EFI_SCSI_OP_WRITE_SAME 0x41
+#define EFI_SCSI_OP_UNMAP 0x42
//
// Additional commands for Sequential Access Devices
@@ -95,8 +95,8 @@
//
// Additional commands for Processor Devices
//
-#define EFI_SCSI_OP_RECEIVE 0x08
-#define EFI_SCSI_OP_SEND 0x0a
+#define EFI_SCSI_OP_RECEIVE 0x08
+#define EFI_SCSI_OP_SEND 0x0a
//
// Additional commands for Write-Once Devices
@@ -133,11 +133,11 @@
//
// Additional commands for Scanner Devices
//
-#define EFI_SCSI_OP_GET_DATABUFF_STAT 0x34
-#define EFI_SCSI_OP_GET_WINDOW 0x25
-#define EFI_SCSI_OP_OBJECT_POS 0x31
-#define EFI_SCSI_OP_SCAN 0x1b
-#define EFI_SCSI_OP_SET_WINDOW 0x24
+#define EFI_SCSI_OP_GET_DATABUFF_STAT 0x34
+#define EFI_SCSI_OP_GET_WINDOW 0x25
+#define EFI_SCSI_OP_OBJECT_POS 0x31
+#define EFI_SCSI_OP_SCAN 0x1b
+#define EFI_SCSI_OP_SET_WINDOW 0x24
//
// Additional commands for Optical Memory Devices
@@ -147,11 +147,11 @@
//
// Additional commands for Medium Changer Devices
//
-#define EFI_SCSI_OP_EXCHANGE_MEDIUM 0xa6
-#define EFI_SCSI_OP_INIT_ELEMENT_STAT 0x07
-#define EFI_SCSI_OP_POS_TO_ELEMENT 0x2b
-#define EFI_SCSI_OP_REQUEST_VE_ADDR 0xb5
-#define EFI_SCSI_OP_SEND_VOL_TAG 0xb6
+#define EFI_SCSI_OP_EXCHANGE_MEDIUM 0xa6
+#define EFI_SCSI_OP_INIT_ELEMENT_STAT 0x07
+#define EFI_SCSI_OP_POS_TO_ELEMENT 0x2b
+#define EFI_SCSI_OP_REQUEST_VE_ADDR 0xb5
+#define EFI_SCSI_OP_SEND_VOL_TAG 0xb6
//
// Additional commands for Communication Devices
@@ -166,14 +166,14 @@
//
// Additional commands for Secure Transactions
//
-#define EFI_SCSI_OP_SECURITY_PROTOCOL_IN 0xa2
-#define EFI_SCSI_OP_SECURITY_PROTOCOL_OUT 0xb5
+#define EFI_SCSI_OP_SECURITY_PROTOCOL_IN 0xa2
+#define EFI_SCSI_OP_SECURITY_PROTOCOL_OUT 0xb5
//
// SCSI Data Transfer Direction
//
-#define EFI_SCSI_DATA_IN 0
-#define EFI_SCSI_DATA_OUT 1
+#define EFI_SCSI_DATA_IN 0
+#define EFI_SCSI_DATA_OUT 1
//
// SCSI Block Command Cache Control Parameters
@@ -184,229 +184,228 @@
//
// Peripheral Device Type Definitions
//
-#define EFI_SCSI_TYPE_DISK 0x00 ///< Direct-access device (e.g. magnetic disk)
-#define EFI_SCSI_TYPE_TAPE 0x01 ///< Sequential-access device (e.g. magnetic tape)
-#define EFI_SCSI_TYPE_PRINTER 0x02 ///< Printer device
-#define EFI_SCSI_TYPE_PROCESSOR 0x03 ///< Processor device
-#define EFI_SCSI_TYPE_WORM 0x04 ///< Write-once device (e.g. some optical disks)
-#define EFI_SCSI_TYPE_CDROM 0x05 ///< CD/DVD device
-#define EFI_SCSI_TYPE_SCANNER 0x06 ///< Scanner device (obsolete)
-#define EFI_SCSI_TYPE_OPTICAL 0x07 ///< Optical memory device (e.g. some optical disks)
-#define EFI_SCSI_TYPE_MEDIUMCHANGER 0x08 ///< Medium changer device (e.g. jukeboxes)
-#define EFI_SCSI_TYPE_COMMUNICATION 0x09 ///< Communications device (obsolete)
-#define EFI_SCSI_TYPE_ASCIT8_1 0x0A ///< Defined by ASC IT8 (Graphic arts pre-press devices)
-#define EFI_SCSI_TYPE_ASCIT8_2 0x0B ///< Defined by ASC IT8 (Graphic arts pre-press devices)
-#define EFI_SCSI_TYPE_RAID 0x0C ///< Storage array controller device (e.g., RAID)
-#define EFI_SCSI_TYPE_SES 0x0D ///< Enclosure services device
-#define EFI_SCSI_TYPE_RBC 0x0E ///< Simplified direct-access device (e.g., magnetic disk)
-#define EFI_SCSI_TYPE_OCRW 0x0F ///< Optical card reader/writer device
-#define EFI_SCSI_TYPE_BRIDGE 0x10 ///< Bridge Controller Commands
-#define EFI_SCSI_TYPE_OSD 0x11 ///< Object-based Storage Device
-#define EFI_SCSI_TYPE_AUTOMATION 0x12 ///< Automation/Drive Interface
-#define EFI_SCSI_TYPE_SECURITYMANAGER 0x13 ///< Security manager device
-#define EFI_SCSI_TYPE_RESERVED_LOW 0x14 ///< Reserved (low)
-#define EFI_SCSI_TYPE_RESERVED_HIGH 0x1D ///< Reserved (high)
-#define EFI_SCSI_TYPE_WLUN 0x1E ///< Well known logical unit
-#define EFI_SCSI_TYPE_UNKNOWN 0x1F ///< Unknown or no device type
+#define EFI_SCSI_TYPE_DISK 0x00 ///< Direct-access device (e.g. magnetic disk)
+#define EFI_SCSI_TYPE_TAPE 0x01 ///< Sequential-access device (e.g. magnetic tape)
+#define EFI_SCSI_TYPE_PRINTER 0x02 ///< Printer device
+#define EFI_SCSI_TYPE_PROCESSOR 0x03 ///< Processor device
+#define EFI_SCSI_TYPE_WORM 0x04 ///< Write-once device (e.g. some optical disks)
+#define EFI_SCSI_TYPE_CDROM 0x05 ///< CD/DVD device
+#define EFI_SCSI_TYPE_SCANNER 0x06 ///< Scanner device (obsolete)
+#define EFI_SCSI_TYPE_OPTICAL 0x07 ///< Optical memory device (e.g. some optical disks)
+#define EFI_SCSI_TYPE_MEDIUMCHANGER 0x08 ///< Medium changer device (e.g. jukeboxes)
+#define EFI_SCSI_TYPE_COMMUNICATION 0x09 ///< Communications device (obsolete)
+#define EFI_SCSI_TYPE_ASCIT8_1 0x0A ///< Defined by ASC IT8 (Graphic arts pre-press devices)
+#define EFI_SCSI_TYPE_ASCIT8_2 0x0B ///< Defined by ASC IT8 (Graphic arts pre-press devices)
+#define EFI_SCSI_TYPE_RAID 0x0C ///< Storage array controller device (e.g., RAID)
+#define EFI_SCSI_TYPE_SES 0x0D ///< Enclosure services device
+#define EFI_SCSI_TYPE_RBC 0x0E ///< Simplified direct-access device (e.g., magnetic disk)
+#define EFI_SCSI_TYPE_OCRW 0x0F ///< Optical card reader/writer device
+#define EFI_SCSI_TYPE_BRIDGE 0x10 ///< Bridge Controller Commands
+#define EFI_SCSI_TYPE_OSD 0x11 ///< Object-based Storage Device
+#define EFI_SCSI_TYPE_AUTOMATION 0x12 ///< Automation/Drive Interface
+#define EFI_SCSI_TYPE_SECURITYMANAGER 0x13 ///< Security manager device
+#define EFI_SCSI_TYPE_RESERVED_LOW 0x14 ///< Reserved (low)
+#define EFI_SCSI_TYPE_RESERVED_HIGH 0x1D ///< Reserved (high)
+#define EFI_SCSI_TYPE_WLUN 0x1E ///< Well known logical unit
+#define EFI_SCSI_TYPE_UNKNOWN 0x1F ///< Unknown or no device type
//
// Page Codes for INQUIRY command
//
-#define EFI_SCSI_PAGE_CODE_SUPPORTED_VPD 0x00
-#define EFI_SCSI_PAGE_CODE_BLOCK_LIMITS_VPD 0xB0
+#define EFI_SCSI_PAGE_CODE_SUPPORTED_VPD 0x00
+#define EFI_SCSI_PAGE_CODE_BLOCK_LIMITS_VPD 0xB0
#pragma pack(1)
///
/// Standard INQUIRY data format
///
typedef struct {
- UINT8 Peripheral_Type : 5;
- UINT8 Peripheral_Qualifier : 3;
- UINT8 DeviceType_Modifier : 7;
- UINT8 Rmb : 1;
- UINT8 Version;
- UINT8 Response_Data_Format;
- UINT8 Addnl_Length;
- UINT8 Reserved_5_95[95 - 5 + 1];
+ UINT8 Peripheral_Type : 5;
+ UINT8 Peripheral_Qualifier : 3;
+ UINT8 DeviceType_Modifier : 7;
+ UINT8 Rmb : 1;
+ UINT8 Version;
+ UINT8 Response_Data_Format;
+ UINT8 Addnl_Length;
+ UINT8 Reserved_5_95[95 - 5 + 1];
} EFI_SCSI_INQUIRY_DATA;
///
/// Supported VPD Pages VPD page
///
typedef struct {
- UINT8 Peripheral_Type : 5;
- UINT8 Peripheral_Qualifier : 3;
- UINT8 PageCode;
- UINT8 PageLength2;
- UINT8 PageLength1;
- UINT8 SupportedVpdPageList[0x100];
+ UINT8 Peripheral_Type : 5;
+ UINT8 Peripheral_Qualifier : 3;
+ UINT8 PageCode;
+ UINT8 PageLength2;
+ UINT8 PageLength1;
+ UINT8 SupportedVpdPageList[0x100];
} EFI_SCSI_SUPPORTED_VPD_PAGES_VPD_PAGE;
///
/// Block Limits VPD page
///
typedef struct {
- UINT8 Peripheral_Type : 5;
- UINT8 Peripheral_Qualifier : 3;
- UINT8 PageCode;
- UINT8 PageLength2;
- UINT8 PageLength1;
- UINT8 WriteSameNonZero : 1;
- UINT8 Reserved_4 : 7;
- UINT8 MaximumCompareAndWriteLength;
- UINT8 OptimalTransferLengthGranularity2;
- UINT8 OptimalTransferLengthGranularity1;
- UINT8 MaximumTransferLength4;
- UINT8 MaximumTransferLength3;
- UINT8 MaximumTransferLength2;
- UINT8 MaximumTransferLength1;
- UINT8 OptimalTransferLength4;
- UINT8 OptimalTransferLength3;
- UINT8 OptimalTransferLength2;
- UINT8 OptimalTransferLength1;
- UINT8 MaximumPrefetchXdreadXdwriteTransferLength4;
- UINT8 MaximumPrefetchXdreadXdwriteTransferLength3;
- UINT8 MaximumPrefetchXdreadXdwriteTransferLength2;
- UINT8 MaximumPrefetchXdreadXdwriteTransferLength1;
- UINT8 MaximumUnmapLbaCount4;
- UINT8 MaximumUnmapLbaCount3;
- UINT8 MaximumUnmapLbaCount2;
- UINT8 MaximumUnmapLbaCount1;
- UINT8 MaximumUnmapBlockDescriptorCount4;
- UINT8 MaximumUnmapBlockDescriptorCount3;
- UINT8 MaximumUnmapBlockDescriptorCount2;
- UINT8 MaximumUnmapBlockDescriptorCount1;
- UINT8 OptimalUnmapGranularity4;
- UINT8 OptimalUnmapGranularity3;
- UINT8 OptimalUnmapGranularity2;
- UINT8 OptimalUnmapGranularity1;
- UINT8 UnmapGranularityAlignment4 : 7;
- UINT8 UnmapGranularityAlignmentValid : 1;
- UINT8 UnmapGranularityAlignment3;
- UINT8 UnmapGranularityAlignment2;
- UINT8 UnmapGranularityAlignment1;
- UINT8 MaximumWriteSameLength4;
- UINT8 MaximumWriteSameLength3;
- UINT8 MaximumWriteSameLength2;
- UINT8 MaximumWriteSameLength1;
- UINT8 MaximumAtomicTransferLength4;
- UINT8 MaximumAtomicTransferLength3;
- UINT8 MaximumAtomicTransferLength2;
- UINT8 MaximumAtomicTransferLength1;
- UINT8 AtomicAlignment4;
- UINT8 AtomicAlignment3;
- UINT8 AtomicAlignment2;
- UINT8 AtomicAlignment1;
- UINT8 AtomicTransferLengthGranularity4;
- UINT8 AtomicTransferLengthGranularity3;
- UINT8 AtomicTransferLengthGranularity2;
- UINT8 AtomicTransferLengthGranularity1;
- UINT8 MaximumAtomicTransferLengthWithAtomicBoundary4;
- UINT8 MaximumAtomicTransferLengthWithAtomicBoundary3;
- UINT8 MaximumAtomicTransferLengthWithAtomicBoundary2;
- UINT8 MaximumAtomicTransferLengthWithAtomicBoundary1;
- UINT8 MaximumAtomicBoundarySize4;
- UINT8 MaximumAtomicBoundarySize3;
- UINT8 MaximumAtomicBoundarySize2;
- UINT8 MaximumAtomicBoundarySize1;
+ UINT8 Peripheral_Type : 5;
+ UINT8 Peripheral_Qualifier : 3;
+ UINT8 PageCode;
+ UINT8 PageLength2;
+ UINT8 PageLength1;
+ UINT8 WriteSameNonZero : 1;
+ UINT8 Reserved_4 : 7;
+ UINT8 MaximumCompareAndWriteLength;
+ UINT8 OptimalTransferLengthGranularity2;
+ UINT8 OptimalTransferLengthGranularity1;
+ UINT8 MaximumTransferLength4;
+ UINT8 MaximumTransferLength3;
+ UINT8 MaximumTransferLength2;
+ UINT8 MaximumTransferLength1;
+ UINT8 OptimalTransferLength4;
+ UINT8 OptimalTransferLength3;
+ UINT8 OptimalTransferLength2;
+ UINT8 OptimalTransferLength1;
+ UINT8 MaximumPrefetchXdreadXdwriteTransferLength4;
+ UINT8 MaximumPrefetchXdreadXdwriteTransferLength3;
+ UINT8 MaximumPrefetchXdreadXdwriteTransferLength2;
+ UINT8 MaximumPrefetchXdreadXdwriteTransferLength1;
+ UINT8 MaximumUnmapLbaCount4;
+ UINT8 MaximumUnmapLbaCount3;
+ UINT8 MaximumUnmapLbaCount2;
+ UINT8 MaximumUnmapLbaCount1;
+ UINT8 MaximumUnmapBlockDescriptorCount4;
+ UINT8 MaximumUnmapBlockDescriptorCount3;
+ UINT8 MaximumUnmapBlockDescriptorCount2;
+ UINT8 MaximumUnmapBlockDescriptorCount1;
+ UINT8 OptimalUnmapGranularity4;
+ UINT8 OptimalUnmapGranularity3;
+ UINT8 OptimalUnmapGranularity2;
+ UINT8 OptimalUnmapGranularity1;
+ UINT8 UnmapGranularityAlignment4 : 7;
+ UINT8 UnmapGranularityAlignmentValid : 1;
+ UINT8 UnmapGranularityAlignment3;
+ UINT8 UnmapGranularityAlignment2;
+ UINT8 UnmapGranularityAlignment1;
+ UINT8 MaximumWriteSameLength4;
+ UINT8 MaximumWriteSameLength3;
+ UINT8 MaximumWriteSameLength2;
+ UINT8 MaximumWriteSameLength1;
+ UINT8 MaximumAtomicTransferLength4;
+ UINT8 MaximumAtomicTransferLength3;
+ UINT8 MaximumAtomicTransferLength2;
+ UINT8 MaximumAtomicTransferLength1;
+ UINT8 AtomicAlignment4;
+ UINT8 AtomicAlignment3;
+ UINT8 AtomicAlignment2;
+ UINT8 AtomicAlignment1;
+ UINT8 AtomicTransferLengthGranularity4;
+ UINT8 AtomicTransferLengthGranularity3;
+ UINT8 AtomicTransferLengthGranularity2;
+ UINT8 AtomicTransferLengthGranularity1;
+ UINT8 MaximumAtomicTransferLengthWithAtomicBoundary4;
+ UINT8 MaximumAtomicTransferLengthWithAtomicBoundary3;
+ UINT8 MaximumAtomicTransferLengthWithAtomicBoundary2;
+ UINT8 MaximumAtomicTransferLengthWithAtomicBoundary1;
+ UINT8 MaximumAtomicBoundarySize4;
+ UINT8 MaximumAtomicBoundarySize3;
+ UINT8 MaximumAtomicBoundarySize2;
+ UINT8 MaximumAtomicBoundarySize1;
} EFI_SCSI_BLOCK_LIMITS_VPD_PAGE;
///
/// Error codes 70h and 71h sense data format
///
typedef struct {
- UINT8 Error_Code : 7;
- UINT8 Valid : 1;
- UINT8 Segment_Number;
- UINT8 Sense_Key : 4;
- UINT8 Reserved_21 : 1;
- UINT8 Ili : 1;
- UINT8 Reserved_22 : 2;
- UINT8 Information_3_6[4];
- UINT8 Addnl_Sense_Length; ///< Additional sense length (n-7)
- UINT8 Vendor_Specific_8_11[4];
- UINT8 Addnl_Sense_Code; ///< Additional sense code
- UINT8 Addnl_Sense_Code_Qualifier; ///< Additional sense code qualifier
- UINT8 Field_Replaceable_Unit_Code; ///< Field replaceable unit code
- UINT8 Reserved_15_17[3];
+ UINT8 Error_Code : 7;
+ UINT8 Valid : 1;
+ UINT8 Segment_Number;
+ UINT8 Sense_Key : 4;
+ UINT8 Reserved_21 : 1;
+ UINT8 Ili : 1;
+ UINT8 Reserved_22 : 2;
+ UINT8 Information_3_6[4];
+ UINT8 Addnl_Sense_Length; ///< Additional sense length (n-7)
+ UINT8 Vendor_Specific_8_11[4];
+ UINT8 Addnl_Sense_Code; ///< Additional sense code
+ UINT8 Addnl_Sense_Code_Qualifier; ///< Additional sense code qualifier
+ UINT8 Field_Replaceable_Unit_Code; ///< Field replaceable unit code
+ UINT8 Reserved_15_17[3];
} EFI_SCSI_SENSE_DATA;
///
/// SCSI Disk READ CAPACITY Data
///
typedef struct {
- UINT8 LastLba3;
- UINT8 LastLba2;
- UINT8 LastLba1;
- UINT8 LastLba0;
- UINT8 BlockSize3;
- UINT8 BlockSize2;
- UINT8 BlockSize1;
- UINT8 BlockSize0;
+ UINT8 LastLba3;
+ UINT8 LastLba2;
+ UINT8 LastLba1;
+ UINT8 LastLba0;
+ UINT8 BlockSize3;
+ UINT8 BlockSize2;
+ UINT8 BlockSize1;
+ UINT8 BlockSize0;
} EFI_SCSI_DISK_CAPACITY_DATA;
typedef struct {
- UINT8 LastLba7;
- UINT8 LastLba6;
- UINT8 LastLba5;
- UINT8 LastLba4;
- UINT8 LastLba3;
- UINT8 LastLba2;
- UINT8 LastLba1;
- UINT8 LastLba0;
- UINT8 BlockSize3;
- UINT8 BlockSize2;
- UINT8 BlockSize1;
- UINT8 BlockSize0;
- UINT8 Protection;
- UINT8 LogicPerPhysical;
- UINT8 LowestAlignLogic2;
- UINT8 LowestAlignLogic1;
- UINT8 Reserved[16];
+ UINT8 LastLba7;
+ UINT8 LastLba6;
+ UINT8 LastLba5;
+ UINT8 LastLba4;
+ UINT8 LastLba3;
+ UINT8 LastLba2;
+ UINT8 LastLba1;
+ UINT8 LastLba0;
+ UINT8 BlockSize3;
+ UINT8 BlockSize2;
+ UINT8 BlockSize1;
+ UINT8 BlockSize0;
+ UINT8 Protection;
+ UINT8 LogicPerPhysical;
+ UINT8 LowestAlignLogic2;
+ UINT8 LowestAlignLogic1;
+ UINT8 Reserved[16];
} EFI_SCSI_DISK_CAPACITY_DATA16;
typedef struct {
- UINT16 DataLen;
- UINT16 BlkDespDataLen;
- UINT8 Reserved[4];
+ UINT16 DataLen;
+ UINT16 BlkDespDataLen;
+ UINT8 Reserved[4];
} EFI_SCSI_DISK_UNMAP_PARAM_LIST_HEADER;
typedef struct {
- UINT64 Lba;
- UINT32 BlockNum;
- UINT8 Reserved[4];
+ UINT64 Lba;
+ UINT32 BlockNum;
+ UINT8 Reserved[4];
} EFI_SCSI_DISK_UNMAP_BLOCK_DESP;
-
#pragma pack()
//
// Sense Key
//
-#define EFI_SCSI_SK_NO_SENSE (0x0)
-#define EFI_SCSI_SK_RECOVERY_ERROR (0x1)
-#define EFI_SCSI_SK_NOT_READY (0x2)
-#define EFI_SCSI_SK_MEDIUM_ERROR (0x3)
-#define EFI_SCSI_SK_HARDWARE_ERROR (0x4)
-#define EFI_SCSI_SK_ILLEGAL_REQUEST (0x5)
-#define EFI_SCSI_SK_UNIT_ATTENTION (0x6)
-#define EFI_SCSI_SK_DATA_PROTECT (0x7)
-#define EFI_SCSI_SK_BLANK_CHECK (0x8)
-#define EFI_SCSI_SK_VENDOR_SPECIFIC (0x9)
-#define EFI_SCSI_SK_RESERVED_A (0xA)
-#define EFI_SCSI_SK_ABORT (0xB)
-#define EFI_SCSI_SK_RESERVED_C (0xC)
-#define EFI_SCSI_SK_OVERFLOW (0xD)
-#define EFI_SCSI_SK_MISCOMPARE (0xE)
-#define EFI_SCSI_SK_RESERVED_F (0xF)
+#define EFI_SCSI_SK_NO_SENSE (0x0)
+#define EFI_SCSI_SK_RECOVERY_ERROR (0x1)
+#define EFI_SCSI_SK_NOT_READY (0x2)
+#define EFI_SCSI_SK_MEDIUM_ERROR (0x3)
+#define EFI_SCSI_SK_HARDWARE_ERROR (0x4)
+#define EFI_SCSI_SK_ILLEGAL_REQUEST (0x5)
+#define EFI_SCSI_SK_UNIT_ATTENTION (0x6)
+#define EFI_SCSI_SK_DATA_PROTECT (0x7)
+#define EFI_SCSI_SK_BLANK_CHECK (0x8)
+#define EFI_SCSI_SK_VENDOR_SPECIFIC (0x9)
+#define EFI_SCSI_SK_RESERVED_A (0xA)
+#define EFI_SCSI_SK_ABORT (0xB)
+#define EFI_SCSI_SK_RESERVED_C (0xC)
+#define EFI_SCSI_SK_OVERFLOW (0xD)
+#define EFI_SCSI_SK_MISCOMPARE (0xE)
+#define EFI_SCSI_SK_RESERVED_F (0xF)
//
// Additional Sense Codes and Sense Code Qualifiers.
// Only some frequently used additional sense codes and qualifiers are
// defined here. Please refer to SCSI standard for full value definition.
//
-#define EFI_SCSI_ASC_NOT_READY (0x04)
-#define EFI_SCSI_ASCQ_IN_PROGRESS (0x01)
+#define EFI_SCSI_ASC_NOT_READY (0x04)
+#define EFI_SCSI_ASCQ_IN_PROGRESS (0x01)
#define EFI_SCSI_ASC_MEDIA_ERR1 (0x10)
#define EFI_SCSI_ASC_MEDIA_ERR2 (0x11)
diff --git a/MdePkg/Include/IndustryStandard/Sd.h b/MdePkg/Include/IndustryStandard/Sd.h
index 415aaf89..3cfdad21 100644
--- a/MdePkg/Include/IndustryStandard/Sd.h
+++ b/MdePkg/Include/IndustryStandard/Sd.h
@@ -15,44 +15,44 @@
//
// SD command index
//
-#define SD_GO_IDLE_STATE 0
-#define SD_ALL_SEND_CID 2
-#define SD_SET_RELATIVE_ADDR 3
-#define SD_SET_DSR 4
-#define SDIO_SEND_OP_COND 5
-#define SD_SWITCH_FUNC 6
-#define SD_SELECT_DESELECT_CARD 7
-#define SD_SEND_IF_COND 8
-#define SD_SEND_CSD 9
-#define SD_SEND_CID 10
-#define SD_VOLTAGE_SWITCH 11
-#define SD_STOP_TRANSMISSION 12
-#define SD_SEND_STATUS 13
-#define SD_GO_INACTIVE_STATE 15
-#define SD_SET_BLOCKLEN 16
-#define SD_READ_SINGLE_BLOCK 17
-#define SD_READ_MULTIPLE_BLOCK 18
-#define SD_SEND_TUNING_BLOCK 19
-#define SD_SPEED_CLASS_CONTROL 20
-#define SD_SET_BLOCK_COUNT 23
-#define SD_WRITE_SINGLE_BLOCK 24
-#define SD_WRITE_MULTIPLE_BLOCK 25
-#define SD_PROGRAM_CSD 27
-#define SD_SET_WRITE_PROT 28
-#define SD_CLR_WRITE_PROT 29
-#define SD_SEND_WRITE_PROT 30
-#define SD_ERASE_WR_BLK_START 32
-#define SD_ERASE_WR_BLK_END 33
-#define SD_ERASE 38
-#define SD_LOCK_UNLOCK 42
-#define SD_READ_EXTR_SINGLE 48
-#define SD_WRITE_EXTR_SINGLE 49
-#define SDIO_RW_DIRECT 52
-#define SDIO_RW_EXTENDED 53
-#define SD_APP_CMD 55
-#define SD_GEN_CMD 56
-#define SD_READ_EXTR_MULTI 58
-#define SD_WRITE_EXTR_MULTI 59
+#define SD_GO_IDLE_STATE 0
+#define SD_ALL_SEND_CID 2
+#define SD_SET_RELATIVE_ADDR 3
+#define SD_SET_DSR 4
+#define SDIO_SEND_OP_COND 5
+#define SD_SWITCH_FUNC 6
+#define SD_SELECT_DESELECT_CARD 7
+#define SD_SEND_IF_COND 8
+#define SD_SEND_CSD 9
+#define SD_SEND_CID 10
+#define SD_VOLTAGE_SWITCH 11
+#define SD_STOP_TRANSMISSION 12
+#define SD_SEND_STATUS 13
+#define SD_GO_INACTIVE_STATE 15
+#define SD_SET_BLOCKLEN 16
+#define SD_READ_SINGLE_BLOCK 17
+#define SD_READ_MULTIPLE_BLOCK 18
+#define SD_SEND_TUNING_BLOCK 19
+#define SD_SPEED_CLASS_CONTROL 20
+#define SD_SET_BLOCK_COUNT 23
+#define SD_WRITE_SINGLE_BLOCK 24
+#define SD_WRITE_MULTIPLE_BLOCK 25
+#define SD_PROGRAM_CSD 27
+#define SD_SET_WRITE_PROT 28
+#define SD_CLR_WRITE_PROT 29
+#define SD_SEND_WRITE_PROT 30
+#define SD_ERASE_WR_BLK_START 32
+#define SD_ERASE_WR_BLK_END 33
+#define SD_ERASE 38
+#define SD_LOCK_UNLOCK 42
+#define SD_READ_EXTR_SINGLE 48
+#define SD_WRITE_EXTR_SINGLE 49
+#define SDIO_RW_DIRECT 52
+#define SDIO_RW_EXTENDED 53
+#define SD_APP_CMD 55
+#define SD_GEN_CMD 56
+#define SD_READ_EXTR_MULTI 58
+#define SD_WRITE_EXTR_MULTI 59
#define SD_SET_BUS_WIDTH 6 // ACMD6
#define SD_STATUS 13 // ACMD13
@@ -64,110 +64,110 @@
#pragma pack(1)
typedef struct {
- UINT8 NotUsed:1; // Not used [0:0]
- UINT8 Crc:7; // CRC [7:1]
- UINT16 ManufacturingDate:12; // Manufacturing date [19:8]
- UINT16 Reserved:4; // Reserved [23:20]
- UINT8 ProductSerialNumber[4]; // Product serial number [55:24]
- UINT8 ProductRevision; // Product revision [63:56]
- UINT8 ProductName[5]; // Product name [103:64]
- UINT8 OemId[2]; // OEM/Application ID [119:104]
- UINT8 ManufacturerId; // Manufacturer ID [127:120]
+ UINT8 NotUsed : 1; // Not used [0:0]
+ UINT8 Crc : 7; // CRC [7:1]
+ UINT16 ManufacturingDate : 12; // Manufacturing date [19:8]
+ UINT16 Reserved : 4; // Reserved [23:20]
+ UINT8 ProductSerialNumber[4]; // Product serial number [55:24]
+ UINT8 ProductRevision; // Product revision [63:56]
+ UINT8 ProductName[5]; // Product name [103:64]
+ UINT8 OemId[2]; // OEM/Application ID [119:104]
+ UINT8 ManufacturerId; // Manufacturer ID [127:120]
} SD_CID;
typedef struct {
- UINT32 NotUsed:1; // Not used [0:0]
- UINT32 Crc:7; // CRC [7:1]
- UINT32 Reserved:2; // Reserved [9:8]
- UINT32 FileFormat:2; // File format [11:10]
- UINT32 TmpWriteProtect:1; // Temporary write protection [12:12]
- UINT32 PermWriteProtect:1; // Permanent write protection [13:13]
- UINT32 Copy:1; // Copy flag (OTP) [14:14]
- UINT32 FileFormatGrp:1; // File format group [15:15]
- UINT32 Reserved1:5; // Reserved [20:16]
- UINT32 WriteBlPartial:1; // Partial blocks for write allowed [21:21]
- UINT32 WriteBlLen:4; // Max. write data block length [25:22]
- UINT32 R2WFactor:3; // Write speed factor [28:26]
- UINT32 Reserved2:2; // Manufacturer default ECC [30:29]
- UINT32 WpGrpEnable:1; // Write protect group enable [31:31]
+ UINT32 NotUsed : 1; // Not used [0:0]
+ UINT32 Crc : 7; // CRC [7:1]
+ UINT32 Reserved : 2; // Reserved [9:8]
+ UINT32 FileFormat : 2; // File format [11:10]
+ UINT32 TmpWriteProtect : 1; // Temporary write protection [12:12]
+ UINT32 PermWriteProtect : 1; // Permanent write protection [13:13]
+ UINT32 Copy : 1; // Copy flag (OTP) [14:14]
+ UINT32 FileFormatGrp : 1; // File format group [15:15]
+ UINT32 Reserved1 : 5; // Reserved [20:16]
+ UINT32 WriteBlPartial : 1; // Partial blocks for write allowed [21:21]
+ UINT32 WriteBlLen : 4; // Max. write data block length [25:22]
+ UINT32 R2WFactor : 3; // Write speed factor [28:26]
+ UINT32 Reserved2 : 2; // Manufacturer default ECC [30:29]
+ UINT32 WpGrpEnable : 1; // Write protect group enable [31:31]
- UINT32 WpGrpSize:7; // Write protect group size [38:32]
- UINT32 SectorSize:7; // Erase sector size [45:39]
- UINT32 EraseBlkEn:1; // Erase single block enable [46:46]
- UINT32 CSizeMul:3; // device size multiplier [49:47]
- UINT32 VddWCurrMax:3; // max. write current @VDD max [52:50]
- UINT32 VddWCurrMin:3; // max. write current @VDD min [55:53]
- UINT32 VddRCurrMax:3; // max. read current @VDD max [58:56]
- UINT32 VddRCurrMin:3; // max. read current @VDD min [61:59]
- UINT32 CSizeLow:2; // Device size low 2 bits [63:62]
+ UINT32 WpGrpSize : 7; // Write protect group size [38:32]
+ UINT32 SectorSize : 7; // Erase sector size [45:39]
+ UINT32 EraseBlkEn : 1; // Erase single block enable [46:46]
+ UINT32 CSizeMul : 3; // device size multiplier [49:47]
+ UINT32 VddWCurrMax : 3; // max. write current @VDD max [52:50]
+ UINT32 VddWCurrMin : 3; // max. write current @VDD min [55:53]
+ UINT32 VddRCurrMax : 3; // max. read current @VDD max [58:56]
+ UINT32 VddRCurrMin : 3; // max. read current @VDD min [61:59]
+ UINT32 CSizeLow : 2; // Device size low 2 bits [63:62]
- UINT32 CSizeHigh:10; // Device size high 10 bits [73:64]
- UINT32 Reserved4:2; // Reserved [75:74]
- UINT32 DsrImp:1; // DSR implemented [76:76]
- UINT32 ReadBlkMisalign:1; // Read block misalignment [77:77]
- UINT32 WriteBlkMisalign:1; // Write block misalignment [78:78]
- UINT32 ReadBlPartial:1; // Partial blocks for read allowed [79:79]
- UINT32 ReadBlLen:4; // Max. read data block length [83:80]
- UINT32 Ccc:12; // Card command classes [95:84]
+ UINT32 CSizeHigh : 10; // Device size high 10 bits [73:64]
+ UINT32 Reserved4 : 2; // Reserved [75:74]
+ UINT32 DsrImp : 1; // DSR implemented [76:76]
+ UINT32 ReadBlkMisalign : 1; // Read block misalignment [77:77]
+ UINT32 WriteBlkMisalign : 1; // Write block misalignment [78:78]
+ UINT32 ReadBlPartial : 1; // Partial blocks for read allowed [79:79]
+ UINT32 ReadBlLen : 4; // Max. read data block length [83:80]
+ UINT32 Ccc : 12; // Card command classes [95:84]
- UINT32 TranSpeed:8; // Max. data transfer rate [103:96]
- UINT32 Nsac:8; // Data read access-time in CLK cycles (NSAC*100) [111:104]
- UINT32 Taac:8; // Data read access-time [119:112]
- UINT32 Reserved5:6; // Reserved [125:120]
- UINT32 CsdStructure:2; // CSD structure [127:126]
+ UINT32 TranSpeed : 8; // Max. data transfer rate [103:96]
+ UINT32 Nsac : 8; // Data read access-time in CLK cycles (NSAC*100) [111:104]
+ UINT32 Taac : 8; // Data read access-time [119:112]
+ UINT32 Reserved5 : 6; // Reserved [125:120]
+ UINT32 CsdStructure : 2; // CSD structure [127:126]
} SD_CSD;
typedef struct {
- UINT32 NotUsed:1; // Not used [0:0]
- UINT32 Crc:7; // CRC [7:1]
- UINT32 Reserved:2; // Reserved [9:8]
- UINT32 FileFormat:2; // File format [11:10]
- UINT32 TmpWriteProtect:1; // Temporary write protection [12:12]
- UINT32 PermWriteProtect:1; // Permanent write protection [13:13]
- UINT32 Copy:1; // Copy flag (OTP) [14:14]
- UINT32 FileFormatGrp:1; // File format group [15:15]
- UINT32 Reserved1:5; // Reserved [20:16]
- UINT32 WriteBlPartial:1; // Partial blocks for write allowed [21:21]
- UINT32 WriteBlLen:4; // Max. write data block length [25:22]
- UINT32 R2WFactor:3; // Write speed factor [28:26]
- UINT32 Reserved2:2; // Manufacturer default ECC [30:29]
- UINT32 WpGrpEnable:1; // Write protect group enable [31:31]
+ UINT32 NotUsed : 1; // Not used [0:0]
+ UINT32 Crc : 7; // CRC [7:1]
+ UINT32 Reserved : 2; // Reserved [9:8]
+ UINT32 FileFormat : 2; // File format [11:10]
+ UINT32 TmpWriteProtect : 1; // Temporary write protection [12:12]
+ UINT32 PermWriteProtect : 1; // Permanent write protection [13:13]
+ UINT32 Copy : 1; // Copy flag (OTP) [14:14]
+ UINT32 FileFormatGrp : 1; // File format group [15:15]
+ UINT32 Reserved1 : 5; // Reserved [20:16]
+ UINT32 WriteBlPartial : 1; // Partial blocks for write allowed [21:21]
+ UINT32 WriteBlLen : 4; // Max. write data block length [25:22]
+ UINT32 R2WFactor : 3; // Write speed factor [28:26]
+ UINT32 Reserved2 : 2; // Manufacturer default ECC [30:29]
+ UINT32 WpGrpEnable : 1; // Write protect group enable [31:31]
- UINT32 WpGrpSize:7; // Write protect group size [38:32]
- UINT32 SectorSize:7; // Erase sector size [45:39]
- UINT32 EraseBlkEn:1; // Erase single block enable [46:46]
- UINT32 Reserved3:1; // Reserved [47:47]
- UINT32 CSizeLow:16; // Device size low 16 bits [63:48]
+ UINT32 WpGrpSize : 7; // Write protect group size [38:32]
+ UINT32 SectorSize : 7; // Erase sector size [45:39]
+ UINT32 EraseBlkEn : 1; // Erase single block enable [46:46]
+ UINT32 Reserved3 : 1; // Reserved [47:47]
+ UINT32 CSizeLow : 16; // Device size low 16 bits [63:48]
- UINT32 CSizeHigh:6; // Device size high 6 bits [69:64]
- UINT32 Reserved4:6; // Reserved [75:70]
- UINT32 DsrImp:1; // DSR implemented [76:76]
- UINT32 ReadBlkMisalign:1; // Read block misalignment [77:77]
- UINT32 WriteBlkMisalign:1; // Write block misalignment [78:78]
- UINT32 ReadBlPartial:1; // Partial blocks for read allowed [79:79]
- UINT32 ReadBlLen:4; // Max. read data block length [83:80]
- UINT32 Ccc:12; // Card command classes [95:84]
+ UINT32 CSizeHigh : 6; // Device size high 6 bits [69:64]
+ UINT32 Reserved4 : 6; // Reserved [75:70]
+ UINT32 DsrImp : 1; // DSR implemented [76:76]
+ UINT32 ReadBlkMisalign : 1; // Read block misalignment [77:77]
+ UINT32 WriteBlkMisalign : 1; // Write block misalignment [78:78]
+ UINT32 ReadBlPartial : 1; // Partial blocks for read allowed [79:79]
+ UINT32 ReadBlLen : 4; // Max. read data block length [83:80]
+ UINT32 Ccc : 12; // Card command classes [95:84]
- UINT32 TranSpeed:8; // Max. data transfer rate [103:96]
- UINT32 Nsac:8; // Data read access-time in CLK cycles (NSAC*100) [111:104]
- UINT32 Taac:8; // Data read access-time [119:112]
- UINT32 Reserved5:6; // Reserved [125:120]
- UINT32 CsdStructure:2; // CSD structure [127:126]
+ UINT32 TranSpeed : 8; // Max. data transfer rate [103:96]
+ UINT32 Nsac : 8; // Data read access-time in CLK cycles (NSAC*100) [111:104]
+ UINT32 Taac : 8; // Data read access-time [119:112]
+ UINT32 Reserved5 : 6; // Reserved [125:120]
+ UINT32 CsdStructure : 2; // CSD structure [127:126]
} SD_CSD2;
typedef struct {
- UINT32 Reserved; // Reserved [31:0]
+ UINT32 Reserved; // Reserved [31:0]
- UINT32 CmdSupport:4; // Command Support bits [35:32]
- UINT32 Reserved1:6; // Reserved [41:36]
- UINT32 SdSpec4:1; // Spec. Version 4.00 or higher [42:42]
- UINT32 ExSecurity:4; // Extended Security Support [46:43]
- UINT32 SdSpec3:1; // Spec. Version 3.00 or higher [47:47]
- UINT32 SdBusWidths:4; // DAT Bus widths supported [51:48]
- UINT32 SdSecurity:3; // CPRM security support [54:52]
- UINT32 DataStatAfterErase:1; // Data status after erases [55]
- UINT32 SdSpec:4; // SD Memory Card Spec. Version [59:56]
- UINT32 ScrStructure:4; // SCR Structure [63:60]
+ UINT32 CmdSupport : 4; // Command Support bits [35:32]
+ UINT32 Reserved1 : 6; // Reserved [41:36]
+ UINT32 SdSpec4 : 1; // Spec. Version 4.00 or higher [42:42]
+ UINT32 ExSecurity : 4; // Extended Security Support [46:43]
+ UINT32 SdSpec3 : 1; // Spec. Version 3.00 or higher [47:47]
+ UINT32 SdBusWidths : 4; // DAT Bus widths supported [51:48]
+ UINT32 SdSecurity : 3; // CPRM security support [54:52]
+ UINT32 DataStatAfterErase : 1; // Data status after erases [55]
+ UINT32 SdSpec : 4; // SD Memory Card Spec. Version [59:56]
+ UINT32 ScrStructure : 4; // SCR Structure [63:60]
} SD_SCR;
#pragma pack()
diff --git a/MdePkg/Include/IndustryStandard/SmBios.h b/MdePkg/Include/IndustryStandard/SmBios.h
index 486e984c..d36bd54d 100644
--- a/MdePkg/Include/IndustryStandard/SmBios.h
+++ b/MdePkg/Include/IndustryStandard/SmBios.h
@@ -1,9 +1,11 @@
/** @file
- Industry Standard Definitions of SMBIOS Table Specification v3.3.0.
+ Industry Standard Definitions of SMBIOS Table Specification v3.7.0.
-Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
(C) Copyright 2015-2017 Hewlett Packard Enterprise Development LP
(C) Copyright 2015 - 2019 Hewlett Packard Enterprise Development LP
+Copyright (c) 2022, AMD Incorporated. All rights reserved.
+Copyright (c) 1985 - 2022, American Megatrends International LLC.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -16,7 +18,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
/// For v2.1 and later, handle values in the range 0FF00h to 0FFFFh are reserved for
/// use by this specification.
///
-#define SMBIOS_HANDLE_RESERVED_BEGIN 0xFF00
+#define SMBIOS_HANDLE_RESERVED_BEGIN 0xFF00
///
/// Reference SMBIOS 2.7, chapter 6.1.2.
@@ -24,7 +26,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
/// EFI_SMBIOS_PROTOCOL.Add() function to mean "assign an unused handle number automatically."
/// This number is not used for any other purpose by the SMBIOS specification.
///
-#define SMBIOS_HANDLE_PI_RESERVED 0xFFFE
+#define SMBIOS_HANDLE_PI_RESERVED 0xFFFE
///
/// Reference SMBIOS 2.6, chapter 3.1.3.
@@ -32,90 +34,110 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
/// Reference SMBIOS 2.7, chapter 6.1.3.
/// It will have no limit on the length of each individual text string.
///
-#define SMBIOS_STRING_MAX_LENGTH 64
+#define SMBIOS_STRING_MAX_LENGTH 64
//
// The length of the entire structure table (including all strings) must be reported
// in the Structure Table Length field of the SMBIOS Structure Table Entry Point,
// which is a WORD field limited to 65,535 bytes.
//
-#define SMBIOS_TABLE_MAX_LENGTH 0xFFFF
+#define SMBIOS_TABLE_MAX_LENGTH 0xFFFF
//
// For SMBIOS 3.0, Structure table maximum size in Entry Point structure is DWORD field limited to 0xFFFFFFFF bytes.
//
-#define SMBIOS_3_0_TABLE_MAX_LENGTH 0xFFFFFFFF
+#define SMBIOS_3_0_TABLE_MAX_LENGTH 0xFFFFFFFF
+
+///
+/// Reference SMBIOS 3.4, chapter 5.2.1 SMBIOS 2.1 (32-bit) Entry Point
+/// Table 1 - SMBIOS 2.1 (32-bit) Entry Point structure, offset 00h
+/// _SM_, specified as four ASCII characters (5F 53 4D 5F).
+///@{
+#define SMBIOS_ANCHOR_STRING "_SM_"
+#define SMBIOS_ANCHOR_STRING_LENGTH 4
+///@}
+
+///
+/// Reference SMBIOS 3.4, chapter 5.2.2 SMBIOS 3.0 (64-bit) Entry Point
+/// Table 2 - SMBIOS 3.0 (64-bit) Entry Point structure, offset 00h
+/// _SM3_, specified as five ASCII characters (5F 53 4D 33 5F).
+///@{
+#define SMBIOS_3_0_ANCHOR_STRING "_SM3_"
+#define SMBIOS_3_0_ANCHOR_STRING_LENGTH 5
+///@}
//
// SMBIOS type macros which is according to SMBIOS 3.3.0 specification.
//
-#define SMBIOS_TYPE_BIOS_INFORMATION 0
-#define SMBIOS_TYPE_SYSTEM_INFORMATION 1
-#define SMBIOS_TYPE_BASEBOARD_INFORMATION 2
-#define SMBIOS_TYPE_SYSTEM_ENCLOSURE 3
-#define SMBIOS_TYPE_PROCESSOR_INFORMATION 4
-#define SMBIOS_TYPE_MEMORY_CONTROLLER_INFORMATION 5
-#define SMBIOS_TYPE_MEMORY_MODULE_INFORMATON 6
-#define SMBIOS_TYPE_CACHE_INFORMATION 7
-#define SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION 8
-#define SMBIOS_TYPE_SYSTEM_SLOTS 9
-#define SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION 10
-#define SMBIOS_TYPE_OEM_STRINGS 11
-#define SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS 12
-#define SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION 13
-#define SMBIOS_TYPE_GROUP_ASSOCIATIONS 14
-#define SMBIOS_TYPE_SYSTEM_EVENT_LOG 15
-#define SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY 16
-#define SMBIOS_TYPE_MEMORY_DEVICE 17
-#define SMBIOS_TYPE_32BIT_MEMORY_ERROR_INFORMATION 18
-#define SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS 19
-#define SMBIOS_TYPE_MEMORY_DEVICE_MAPPED_ADDRESS 20
-#define SMBIOS_TYPE_BUILT_IN_POINTING_DEVICE 21
-#define SMBIOS_TYPE_PORTABLE_BATTERY 22
-#define SMBIOS_TYPE_SYSTEM_RESET 23
-#define SMBIOS_TYPE_HARDWARE_SECURITY 24
-#define SMBIOS_TYPE_SYSTEM_POWER_CONTROLS 25
-#define SMBIOS_TYPE_VOLTAGE_PROBE 26
-#define SMBIOS_TYPE_COOLING_DEVICE 27
-#define SMBIOS_TYPE_TEMPERATURE_PROBE 28
-#define SMBIOS_TYPE_ELECTRICAL_CURRENT_PROBE 29
-#define SMBIOS_TYPE_OUT_OF_BAND_REMOTE_ACCESS 30
-#define SMBIOS_TYPE_BOOT_INTEGRITY_SERVICE 31
-#define SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION 32
-#define SMBIOS_TYPE_64BIT_MEMORY_ERROR_INFORMATION 33
-#define SMBIOS_TYPE_MANAGEMENT_DEVICE 34
-#define SMBIOS_TYPE_MANAGEMENT_DEVICE_COMPONENT 35
-#define SMBIOS_TYPE_MANAGEMENT_DEVICE_THRESHOLD_DATA 36
-#define SMBIOS_TYPE_MEMORY_CHANNEL 37
-#define SMBIOS_TYPE_IPMI_DEVICE_INFORMATION 38
-#define SMBIOS_TYPE_SYSTEM_POWER_SUPPLY 39
-#define SMBIOS_TYPE_ADDITIONAL_INFORMATION 40
-#define SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION 41
-#define SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE 42
-#define SMBIOS_TYPE_TPM_DEVICE 43
-#define SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION 44
+#define SMBIOS_TYPE_BIOS_INFORMATION 0
+#define SMBIOS_TYPE_SYSTEM_INFORMATION 1
+#define SMBIOS_TYPE_BASEBOARD_INFORMATION 2
+#define SMBIOS_TYPE_SYSTEM_ENCLOSURE 3
+#define SMBIOS_TYPE_PROCESSOR_INFORMATION 4
+#define SMBIOS_TYPE_MEMORY_CONTROLLER_INFORMATION 5
+#define SMBIOS_TYPE_MEMORY_MODULE_INFORMATON 6
+#define SMBIOS_TYPE_CACHE_INFORMATION 7
+#define SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION 8
+#define SMBIOS_TYPE_SYSTEM_SLOTS 9
+#define SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION 10
+#define SMBIOS_TYPE_OEM_STRINGS 11
+#define SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS 12
+#define SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION 13
+#define SMBIOS_TYPE_GROUP_ASSOCIATIONS 14
+#define SMBIOS_TYPE_SYSTEM_EVENT_LOG 15
+#define SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY 16
+#define SMBIOS_TYPE_MEMORY_DEVICE 17
+#define SMBIOS_TYPE_32BIT_MEMORY_ERROR_INFORMATION 18
+#define SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS 19
+#define SMBIOS_TYPE_MEMORY_DEVICE_MAPPED_ADDRESS 20
+#define SMBIOS_TYPE_BUILT_IN_POINTING_DEVICE 21
+#define SMBIOS_TYPE_PORTABLE_BATTERY 22
+#define SMBIOS_TYPE_SYSTEM_RESET 23
+#define SMBIOS_TYPE_HARDWARE_SECURITY 24
+#define SMBIOS_TYPE_SYSTEM_POWER_CONTROLS 25
+#define SMBIOS_TYPE_VOLTAGE_PROBE 26
+#define SMBIOS_TYPE_COOLING_DEVICE 27
+#define SMBIOS_TYPE_TEMPERATURE_PROBE 28
+#define SMBIOS_TYPE_ELECTRICAL_CURRENT_PROBE 29
+#define SMBIOS_TYPE_OUT_OF_BAND_REMOTE_ACCESS 30
+#define SMBIOS_TYPE_BOOT_INTEGRITY_SERVICE 31
+#define SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION 32
+#define SMBIOS_TYPE_64BIT_MEMORY_ERROR_INFORMATION 33
+#define SMBIOS_TYPE_MANAGEMENT_DEVICE 34
+#define SMBIOS_TYPE_MANAGEMENT_DEVICE_COMPONENT 35
+#define SMBIOS_TYPE_MANAGEMENT_DEVICE_THRESHOLD_DATA 36
+#define SMBIOS_TYPE_MEMORY_CHANNEL 37
+#define SMBIOS_TYPE_IPMI_DEVICE_INFORMATION 38
+#define SMBIOS_TYPE_SYSTEM_POWER_SUPPLY 39
+#define SMBIOS_TYPE_ADDITIONAL_INFORMATION 40
+#define SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION 41
+#define SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE 42
+#define SMBIOS_TYPE_TPM_DEVICE 43
+#define SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION 44
+#define SMBIOS_TYPE_FIRMWARE_INVENTORY_INFORMATION 45
+#define SMBIOS_TYPE_STRING_PROPERTY_INFORMATION 46
///
/// Inactive type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.43.
/// Upper-level software that interprets the SMBIOS structure-table should bypass an
/// Inactive structure just like a structure type that the software does not recognize.
///
-#define SMBIOS_TYPE_INACTIVE 0x007E
+#define SMBIOS_TYPE_INACTIVE 0x007E
///
/// End-of-table type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.44.
/// The end-of-table indicator is used in the last physical structure in a table
///
-#define SMBIOS_TYPE_END_OF_TABLE 0x007F
+#define SMBIOS_TYPE_END_OF_TABLE 0x007F
-#define SMBIOS_OEM_BEGIN 128
-#define SMBIOS_OEM_END 255
+#define SMBIOS_OEM_BEGIN 128
+#define SMBIOS_OEM_END 255
///
/// Types 0 through 127 (7Fh) are reserved for and defined by this
/// specification. Types 128 through 256 (80h to FFh) are available for system- and OEM-specific information.
///
-typedef UINT8 SMBIOS_TYPE;
+typedef UINT8 SMBIOS_TYPE;
///
/// Specifies the structure's handle, a unique 16-bit number in the range 0 to 0FFFEh (for version
@@ -134,42 +156,42 @@ typedef UINT16 SMBIOS_HANDLE;
///
#pragma pack(1)
typedef struct {
- UINT8 AnchorString[4];
- UINT8 EntryPointStructureChecksum;
- UINT8 EntryPointLength;
- UINT8 MajorVersion;
- UINT8 MinorVersion;
- UINT16 MaxStructureSize;
- UINT8 EntryPointRevision;
- UINT8 FormattedArea[5];
- UINT8 IntermediateAnchorString[5];
- UINT8 IntermediateChecksum;
- UINT16 TableLength;
- UINT32 TableAddress;
- UINT16 NumberOfSmbiosStructures;
- UINT8 SmbiosBcdRevision;
+ UINT8 AnchorString[SMBIOS_ANCHOR_STRING_LENGTH];
+ UINT8 EntryPointStructureChecksum;
+ UINT8 EntryPointLength;
+ UINT8 MajorVersion;
+ UINT8 MinorVersion;
+ UINT16 MaxStructureSize;
+ UINT8 EntryPointRevision;
+ UINT8 FormattedArea[5];
+ UINT8 IntermediateAnchorString[5];
+ UINT8 IntermediateChecksum;
+ UINT16 TableLength;
+ UINT32 TableAddress;
+ UINT16 NumberOfSmbiosStructures;
+ UINT8 SmbiosBcdRevision;
} SMBIOS_TABLE_ENTRY_POINT;
typedef struct {
- UINT8 AnchorString[5];
- UINT8 EntryPointStructureChecksum;
- UINT8 EntryPointLength;
- UINT8 MajorVersion;
- UINT8 MinorVersion;
- UINT8 DocRev;
- UINT8 EntryPointRevision;
- UINT8 Reserved;
- UINT32 TableMaximumSize;
- UINT64 TableAddress;
+ UINT8 AnchorString[SMBIOS_3_0_ANCHOR_STRING_LENGTH];
+ UINT8 EntryPointStructureChecksum;
+ UINT8 EntryPointLength;
+ UINT8 MajorVersion;
+ UINT8 MinorVersion;
+ UINT8 DocRev;
+ UINT8 EntryPointRevision;
+ UINT8 Reserved;
+ UINT32 TableMaximumSize;
+ UINT64 TableAddress;
} SMBIOS_TABLE_3_0_ENTRY_POINT;
///
/// The Smbios structure header.
///
typedef struct {
- SMBIOS_TYPE Type;
- UINT8 Length;
- SMBIOS_HANDLE Handle;
+ SMBIOS_TYPE Type;
+ UINT8 Length;
+ SMBIOS_HANDLE Handle;
} SMBIOS_STRUCTURE;
///
@@ -190,39 +212,39 @@ typedef UINT8 SMBIOS_TABLE_STRING;
/// Defines which functions the BIOS supports. PCI, PCMCIA, Flash, etc.
///
typedef struct {
- UINT32 Reserved :2; ///< Bits 0-1.
- UINT32 Unknown :1;
- UINT32 BiosCharacteristicsNotSupported :1;
- UINT32 IsaIsSupported :1;
- UINT32 McaIsSupported :1;
- UINT32 EisaIsSupported :1;
- UINT32 PciIsSupported :1;
- UINT32 PcmciaIsSupported :1;
- UINT32 PlugAndPlayIsSupported :1;
- UINT32 ApmIsSupported :1;
- UINT32 BiosIsUpgradable :1;
- UINT32 BiosShadowingAllowed :1;
- UINT32 VlVesaIsSupported :1;
- UINT32 EscdSupportIsAvailable :1;
- UINT32 BootFromCdIsSupported :1;
- UINT32 SelectableBootIsSupported :1;
- UINT32 RomBiosIsSocketed :1;
- UINT32 BootFromPcmciaIsSupported :1;
- UINT32 EDDSpecificationIsSupported :1;
- UINT32 JapaneseNecFloppyIsSupported :1;
- UINT32 JapaneseToshibaFloppyIsSupported :1;
- UINT32 Floppy525_360IsSupported :1;
- UINT32 Floppy525_12IsSupported :1;
- UINT32 Floppy35_720IsSupported :1;
- UINT32 Floppy35_288IsSupported :1;
- UINT32 PrintScreenIsSupported :1;
- UINT32 Keyboard8042IsSupported :1;
- UINT32 SerialIsSupported :1;
- UINT32 PrinterIsSupported :1;
- UINT32 CgaMonoIsSupported :1;
- UINT32 NecPc98 :1;
- UINT32 ReservedForVendor :32; ///< Bits 32-63. Bits 32-47 reserved for BIOS vendor
- ///< and bits 48-63 reserved for System Vendor.
+ UINT32 Reserved : 2; ///< Bits 0-1.
+ UINT32 Unknown : 1;
+ UINT32 BiosCharacteristicsNotSupported : 1;
+ UINT32 IsaIsSupported : 1;
+ UINT32 McaIsSupported : 1;
+ UINT32 EisaIsSupported : 1;
+ UINT32 PciIsSupported : 1;
+ UINT32 PcmciaIsSupported : 1;
+ UINT32 PlugAndPlayIsSupported : 1;
+ UINT32 ApmIsSupported : 1;
+ UINT32 BiosIsUpgradable : 1;
+ UINT32 BiosShadowingAllowed : 1;
+ UINT32 VlVesaIsSupported : 1;
+ UINT32 EscdSupportIsAvailable : 1;
+ UINT32 BootFromCdIsSupported : 1;
+ UINT32 SelectableBootIsSupported : 1;
+ UINT32 RomBiosIsSocketed : 1;
+ UINT32 BootFromPcmciaIsSupported : 1;
+ UINT32 EDDSpecificationIsSupported : 1;
+ UINT32 JapaneseNecFloppyIsSupported : 1;
+ UINT32 JapaneseToshibaFloppyIsSupported : 1;
+ UINT32 Floppy525_360IsSupported : 1;
+ UINT32 Floppy525_12IsSupported : 1;
+ UINT32 Floppy35_720IsSupported : 1;
+ UINT32 Floppy35_288IsSupported : 1;
+ UINT32 PrintScreenIsSupported : 1;
+ UINT32 Keyboard8042IsSupported : 1;
+ UINT32 SerialIsSupported : 1;
+ UINT32 PrinterIsSupported : 1;
+ UINT32 CgaMonoIsSupported : 1;
+ UINT32 NecPc98 : 1;
+ UINT32 ReservedForVendor : 32; ///< Bits 32-63. Bits 32-47 reserved for BIOS vendor
+ ///< and bits 48-63 reserved for System Vendor.
} MISC_BIOS_CHARACTERISTICS;
///
@@ -231,14 +253,14 @@ typedef struct {
/// within the BIOS Information structure.
///
typedef struct {
- UINT8 AcpiIsSupported :1;
- UINT8 UsbLegacyIsSupported :1;
- UINT8 AgpIsSupported :1;
- UINT8 I2OBootIsSupported :1;
- UINT8 Ls120BootIsSupported :1;
- UINT8 AtapiZipDriveBootIsSupported :1;
- UINT8 Boot1394IsSupported :1;
- UINT8 SmartBatteryIsSupported :1;
+ UINT8 AcpiIsSupported : 1;
+ UINT8 UsbLegacyIsSupported : 1;
+ UINT8 AgpIsSupported : 1;
+ UINT8 I2OBootIsSupported : 1;
+ UINT8 Ls120BootIsSupported : 1;
+ UINT8 AtapiZipDriveBootIsSupported : 1;
+ UINT8 Boot1394IsSupported : 1;
+ UINT8 SmartBatteryIsSupported : 1;
} MBCE_BIOS_RESERVED;
///
@@ -247,65 +269,67 @@ typedef struct {
/// within the BIOS Information structure.
///
typedef struct {
- UINT8 BiosBootSpecIsSupported :1;
- UINT8 FunctionKeyNetworkBootIsSupported :1;
- UINT8 TargetContentDistributionEnabled :1;
- UINT8 UefiSpecificationSupported :1;
- UINT8 VirtualMachineSupported :1;
- UINT8 ExtensionByte2Reserved :3;
+ UINT8 BiosBootSpecIsSupported : 1;
+ UINT8 FunctionKeyNetworkBootIsSupported : 1;
+ UINT8 TargetContentDistributionEnabled : 1;
+ UINT8 UefiSpecificationSupported : 1;
+ UINT8 VirtualMachineSupported : 1;
+ UINT8 ManufacturingModeSupported : 1;
+ UINT8 ManufacturingModeEnabled : 1;
+ UINT8 ExtensionByte2Reserved : 1;
} MBCE_SYSTEM_RESERVED;
///
/// BIOS Characteristics Extension Bytes.
///
typedef struct {
- MBCE_BIOS_RESERVED BiosReserved;
- MBCE_SYSTEM_RESERVED SystemReserved;
+ MBCE_BIOS_RESERVED BiosReserved;
+ MBCE_SYSTEM_RESERVED SystemReserved;
} MISC_BIOS_CHARACTERISTICS_EXTENSION;
///
/// Extended BIOS ROM size.
///
typedef struct {
- UINT16 Size :14;
- UINT16 Unit :2;
+ UINT16 Size : 14;
+ UINT16 Unit : 2;
} EXTENDED_BIOS_ROM_SIZE;
///
/// BIOS Information (Type 0).
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- SMBIOS_TABLE_STRING Vendor;
- SMBIOS_TABLE_STRING BiosVersion;
- UINT16 BiosSegment;
- SMBIOS_TABLE_STRING BiosReleaseDate;
- UINT8 BiosSize;
- MISC_BIOS_CHARACTERISTICS BiosCharacteristics;
- UINT8 BIOSCharacteristicsExtensionBytes[2];
- UINT8 SystemBiosMajorRelease;
- UINT8 SystemBiosMinorRelease;
- UINT8 EmbeddedControllerFirmwareMajorRelease;
- UINT8 EmbeddedControllerFirmwareMinorRelease;
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING Vendor;
+ SMBIOS_TABLE_STRING BiosVersion;
+ UINT16 BiosSegment;
+ SMBIOS_TABLE_STRING BiosReleaseDate;
+ UINT8 BiosSize;
+ MISC_BIOS_CHARACTERISTICS BiosCharacteristics;
+ UINT8 BIOSCharacteristicsExtensionBytes[2];
+ UINT8 SystemBiosMajorRelease;
+ UINT8 SystemBiosMinorRelease;
+ UINT8 EmbeddedControllerFirmwareMajorRelease;
+ UINT8 EmbeddedControllerFirmwareMinorRelease;
//
// Add for smbios 3.1.0
//
- EXTENDED_BIOS_ROM_SIZE ExtendedBiosSize;
+ EXTENDED_BIOS_ROM_SIZE ExtendedBiosSize;
} SMBIOS_TABLE_TYPE0;
///
/// System Wake-up Type.
///
typedef enum {
- SystemWakeupTypeReserved = 0x00,
- SystemWakeupTypeOther = 0x01,
- SystemWakeupTypeUnknown = 0x02,
- SystemWakeupTypeApmTimer = 0x03,
- SystemWakeupTypeModemRing = 0x04,
- SystemWakeupTypeLanRemote = 0x05,
- SystemWakeupTypePowerSwitch = 0x06,
- SystemWakeupTypePciPme = 0x07,
- SystemWakeupTypeAcPowerRestored = 0x08
+ SystemWakeupTypeReserved = 0x00,
+ SystemWakeupTypeOther = 0x01,
+ SystemWakeupTypeUnknown = 0x02,
+ SystemWakeupTypeApmTimer = 0x03,
+ SystemWakeupTypeModemRing = 0x04,
+ SystemWakeupTypeLanRemote = 0x05,
+ SystemWakeupTypePowerSwitch = 0x06,
+ SystemWakeupTypePciPme = 0x07,
+ SystemWakeupTypeAcPowerRestored = 0x08
} MISC_SYSTEM_WAKEUP_TYPE;
///
@@ -317,46 +341,46 @@ typedef enum {
/// one and only one System Information (Type 1) structure.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- SMBIOS_TABLE_STRING Manufacturer;
- SMBIOS_TABLE_STRING ProductName;
- SMBIOS_TABLE_STRING Version;
- SMBIOS_TABLE_STRING SerialNumber;
- GUID Uuid;
- UINT8 WakeUpType; ///< The enumeration value from MISC_SYSTEM_WAKEUP_TYPE.
- SMBIOS_TABLE_STRING SKUNumber;
- SMBIOS_TABLE_STRING Family;
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING Manufacturer;
+ SMBIOS_TABLE_STRING ProductName;
+ SMBIOS_TABLE_STRING Version;
+ SMBIOS_TABLE_STRING SerialNumber;
+ GUID Uuid;
+ UINT8 WakeUpType; ///< The enumeration value from MISC_SYSTEM_WAKEUP_TYPE.
+ SMBIOS_TABLE_STRING SKUNumber;
+ SMBIOS_TABLE_STRING Family;
} SMBIOS_TABLE_TYPE1;
///
/// Base Board - Feature Flags.
///
typedef struct {
- UINT8 Motherboard :1;
- UINT8 RequiresDaughterCard :1;
- UINT8 Removable :1;
- UINT8 Replaceable :1;
- UINT8 HotSwappable :1;
- UINT8 Reserved :3;
+ UINT8 Motherboard : 1;
+ UINT8 RequiresDaughterCard : 1;
+ UINT8 Removable : 1;
+ UINT8 Replaceable : 1;
+ UINT8 HotSwappable : 1;
+ UINT8 Reserved : 3;
} BASE_BOARD_FEATURE_FLAGS;
///
/// Base Board - Board Type.
///
typedef enum {
- BaseBoardTypeUnknown = 0x1,
- BaseBoardTypeOther = 0x2,
- BaseBoardTypeServerBlade = 0x3,
- BaseBoardTypeConnectivitySwitch = 0x4,
- BaseBoardTypeSystemManagementModule = 0x5,
- BaseBoardTypeProcessorModule = 0x6,
- BaseBoardTypeIOModule = 0x7,
- BaseBoardTypeMemoryModule = 0x8,
- BaseBoardTypeDaughterBoard = 0x9,
- BaseBoardTypeMotherBoard = 0xA,
- BaseBoardTypeProcessorMemoryModule = 0xB,
- BaseBoardTypeProcessorIOModule = 0xC,
- BaseBoardTypeInterconnectBoard = 0xD
+ BaseBoardTypeUnknown = 0x1,
+ BaseBoardTypeOther = 0x2,
+ BaseBoardTypeServerBlade = 0x3,
+ BaseBoardTypeConnectivitySwitch = 0x4,
+ BaseBoardTypeSystemManagementModule = 0x5,
+ BaseBoardTypeProcessorModule = 0x6,
+ BaseBoardTypeIOModule = 0x7,
+ BaseBoardTypeMemoryModule = 0x8,
+ BaseBoardTypeDaughterBoard = 0x9,
+ BaseBoardTypeMotherBoard = 0xA,
+ BaseBoardTypeProcessorMemoryModule = 0xB,
+ BaseBoardTypeProcessorIOModule = 0xC,
+ BaseBoardTypeInterconnectBoard = 0xD
} BASE_BOARD_TYPE;
///
@@ -366,72 +390,72 @@ typedef enum {
/// for example a motherboard, planar, or server blade or other standard system module.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- SMBIOS_TABLE_STRING Manufacturer;
- SMBIOS_TABLE_STRING ProductName;
- SMBIOS_TABLE_STRING Version;
- SMBIOS_TABLE_STRING SerialNumber;
- SMBIOS_TABLE_STRING AssetTag;
- BASE_BOARD_FEATURE_FLAGS FeatureFlag;
- SMBIOS_TABLE_STRING LocationInChassis;
- UINT16 ChassisHandle;
- UINT8 BoardType; ///< The enumeration value from BASE_BOARD_TYPE.
- UINT8 NumberOfContainedObjectHandles;
- UINT16 ContainedObjectHandles[1];
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING Manufacturer;
+ SMBIOS_TABLE_STRING ProductName;
+ SMBIOS_TABLE_STRING Version;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING AssetTag;
+ BASE_BOARD_FEATURE_FLAGS FeatureFlag;
+ SMBIOS_TABLE_STRING LocationInChassis;
+ UINT16 ChassisHandle;
+ UINT8 BoardType; ///< The enumeration value from BASE_BOARD_TYPE.
+ UINT8 NumberOfContainedObjectHandles;
+ UINT16 ContainedObjectHandles[1];
} SMBIOS_TABLE_TYPE2;
///
/// System Enclosure or Chassis Types
///
typedef enum {
- MiscChassisTypeOther = 0x01,
- MiscChassisTypeUnknown = 0x02,
- MiscChassisTypeDeskTop = 0x03,
- MiscChassisTypeLowProfileDesktop = 0x04,
- MiscChassisTypePizzaBox = 0x05,
- MiscChassisTypeMiniTower = 0x06,
- MiscChassisTypeTower = 0x07,
- MiscChassisTypePortable = 0x08,
- MiscChassisTypeLapTop = 0x09,
- MiscChassisTypeNotebook = 0x0A,
- MiscChassisTypeHandHeld = 0x0B,
- MiscChassisTypeDockingStation = 0x0C,
- MiscChassisTypeAllInOne = 0x0D,
- MiscChassisTypeSubNotebook = 0x0E,
- MiscChassisTypeSpaceSaving = 0x0F,
- MiscChassisTypeLunchBox = 0x10,
- MiscChassisTypeMainServerChassis = 0x11,
- MiscChassisTypeExpansionChassis = 0x12,
- MiscChassisTypeSubChassis = 0x13,
- MiscChassisTypeBusExpansionChassis = 0x14,
- MiscChassisTypePeripheralChassis = 0x15,
- MiscChassisTypeRaidChassis = 0x16,
- MiscChassisTypeRackMountChassis = 0x17,
- MiscChassisTypeSealedCasePc = 0x18,
- MiscChassisMultiSystemChassis = 0x19,
- MiscChassisCompactPCI = 0x1A,
- MiscChassisAdvancedTCA = 0x1B,
- MiscChassisBlade = 0x1C,
- MiscChassisBladeEnclosure = 0x1D,
- MiscChassisTablet = 0x1E,
- MiscChassisConvertible = 0x1F,
- MiscChassisDetachable = 0x20,
- MiscChassisIoTGateway = 0x21,
- MiscChassisEmbeddedPc = 0x22,
- MiscChassisMiniPc = 0x23,
- MiscChassisStickPc = 0x24
+ MiscChassisTypeOther = 0x01,
+ MiscChassisTypeUnknown = 0x02,
+ MiscChassisTypeDeskTop = 0x03,
+ MiscChassisTypeLowProfileDesktop = 0x04,
+ MiscChassisTypePizzaBox = 0x05,
+ MiscChassisTypeMiniTower = 0x06,
+ MiscChassisTypeTower = 0x07,
+ MiscChassisTypePortable = 0x08,
+ MiscChassisTypeLapTop = 0x09,
+ MiscChassisTypeNotebook = 0x0A,
+ MiscChassisTypeHandHeld = 0x0B,
+ MiscChassisTypeDockingStation = 0x0C,
+ MiscChassisTypeAllInOne = 0x0D,
+ MiscChassisTypeSubNotebook = 0x0E,
+ MiscChassisTypeSpaceSaving = 0x0F,
+ MiscChassisTypeLunchBox = 0x10,
+ MiscChassisTypeMainServerChassis = 0x11,
+ MiscChassisTypeExpansionChassis = 0x12,
+ MiscChassisTypeSubChassis = 0x13,
+ MiscChassisTypeBusExpansionChassis = 0x14,
+ MiscChassisTypePeripheralChassis = 0x15,
+ MiscChassisTypeRaidChassis = 0x16,
+ MiscChassisTypeRackMountChassis = 0x17,
+ MiscChassisTypeSealedCasePc = 0x18,
+ MiscChassisMultiSystemChassis = 0x19,
+ MiscChassisCompactPCI = 0x1A,
+ MiscChassisAdvancedTCA = 0x1B,
+ MiscChassisBlade = 0x1C,
+ MiscChassisBladeEnclosure = 0x1D,
+ MiscChassisTablet = 0x1E,
+ MiscChassisConvertible = 0x1F,
+ MiscChassisDetachable = 0x20,
+ MiscChassisIoTGateway = 0x21,
+ MiscChassisEmbeddedPc = 0x22,
+ MiscChassisMiniPc = 0x23,
+ MiscChassisStickPc = 0x24
} MISC_CHASSIS_TYPE;
///
/// System Enclosure or Chassis States .
///
typedef enum {
- ChassisStateOther = 0x01,
- ChassisStateUnknown = 0x02,
- ChassisStateSafe = 0x03,
- ChassisStateWarning = 0x04,
- ChassisStateCritical = 0x05,
- ChassisStateNonRecoverable = 0x06
+ ChassisStateOther = 0x01,
+ ChassisStateUnknown = 0x02,
+ ChassisStateSafe = 0x03,
+ ChassisStateWarning = 0x04,
+ ChassisStateCritical = 0x05,
+ ChassisStateNonRecoverable = 0x06
} MISC_CHASSIS_STATE;
///
@@ -449,12 +473,11 @@ typedef enum {
/// Contained Element record
///
typedef struct {
- UINT8 ContainedElementType;
- UINT8 ContainedElementMinimum;
- UINT8 ContainedElementMaximum;
+ UINT8 ContainedElementType;
+ UINT8 ContainedElementMinimum;
+ UINT8 ContainedElementMaximum;
} CONTAINED_ELEMENT;
-
///
/// System Enclosure or Chassis (Type 3).
///
@@ -465,25 +488,25 @@ typedef struct {
/// support the population of the CIM_Chassis class.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- SMBIOS_TABLE_STRING Manufacturer;
- UINT8 Type;
- SMBIOS_TABLE_STRING Version;
- SMBIOS_TABLE_STRING SerialNumber;
- SMBIOS_TABLE_STRING AssetTag;
- UINT8 BootupState; ///< The enumeration value from MISC_CHASSIS_STATE.
- UINT8 PowerSupplyState; ///< The enumeration value from MISC_CHASSIS_STATE.
- UINT8 ThermalState; ///< The enumeration value from MISC_CHASSIS_STATE.
- UINT8 SecurityStatus; ///< The enumeration value from MISC_CHASSIS_SECURITY_STATE.
- UINT8 OemDefined[4];
- UINT8 Height;
- UINT8 NumberofPowerCords;
- UINT8 ContainedElementCount;
- UINT8 ContainedElementRecordLength;
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING Manufacturer;
+ UINT8 Type;
+ SMBIOS_TABLE_STRING Version;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING AssetTag;
+ UINT8 BootupState; ///< The enumeration value from MISC_CHASSIS_STATE.
+ UINT8 PowerSupplyState; ///< The enumeration value from MISC_CHASSIS_STATE.
+ UINT8 ThermalState; ///< The enumeration value from MISC_CHASSIS_STATE.
+ UINT8 SecurityStatus; ///< The enumeration value from MISC_CHASSIS_SECURITY_STATE.
+ UINT8 OemDefined[4];
+ UINT8 Height;
+ UINT8 NumberofPowerCords;
+ UINT8 ContainedElementCount;
+ UINT8 ContainedElementRecordLength;
//
// Can have 0 to (ContainedElementCount * ContainedElementRecordLength) contained elements
//
- CONTAINED_ELEMENT ContainedElements[1];
+ CONTAINED_ELEMENT ContainedElements[1];
//
// Add for smbios 2.7
//
@@ -510,289 +533,308 @@ typedef enum {
/// Processor Information - Processor Family.
///
typedef enum {
- ProcessorFamilyOther = 0x01,
- ProcessorFamilyUnknown = 0x02,
- ProcessorFamily8086 = 0x03,
- ProcessorFamily80286 = 0x04,
- ProcessorFamilyIntel386 = 0x05,
- ProcessorFamilyIntel486 = 0x06,
- ProcessorFamily8087 = 0x07,
- ProcessorFamily80287 = 0x08,
- ProcessorFamily80387 = 0x09,
- ProcessorFamily80487 = 0x0A,
- ProcessorFamilyPentium = 0x0B,
- ProcessorFamilyPentiumPro = 0x0C,
- ProcessorFamilyPentiumII = 0x0D,
- ProcessorFamilyPentiumMMX = 0x0E,
- ProcessorFamilyCeleron = 0x0F,
- ProcessorFamilyPentiumIIXeon = 0x10,
- ProcessorFamilyPentiumIII = 0x11,
- ProcessorFamilyM1 = 0x12,
- ProcessorFamilyM2 = 0x13,
- ProcessorFamilyIntelCeleronM = 0x14,
- ProcessorFamilyIntelPentium4Ht = 0x15,
- ProcessorFamilyAmdDuron = 0x18,
- ProcessorFamilyK5 = 0x19,
- ProcessorFamilyK6 = 0x1A,
- ProcessorFamilyK6_2 = 0x1B,
- ProcessorFamilyK6_3 = 0x1C,
- ProcessorFamilyAmdAthlon = 0x1D,
- ProcessorFamilyAmd29000 = 0x1E,
- ProcessorFamilyK6_2Plus = 0x1F,
- ProcessorFamilyPowerPC = 0x20,
- ProcessorFamilyPowerPC601 = 0x21,
- ProcessorFamilyPowerPC603 = 0x22,
- ProcessorFamilyPowerPC603Plus = 0x23,
- ProcessorFamilyPowerPC604 = 0x24,
- ProcessorFamilyPowerPC620 = 0x25,
- ProcessorFamilyPowerPCx704 = 0x26,
- ProcessorFamilyPowerPC750 = 0x27,
- ProcessorFamilyIntelCoreDuo = 0x28,
- ProcessorFamilyIntelCoreDuoMobile = 0x29,
- ProcessorFamilyIntelCoreSoloMobile = 0x2A,
- ProcessorFamilyIntelAtom = 0x2B,
- ProcessorFamilyIntelCoreM = 0x2C,
- ProcessorFamilyIntelCorem3 = 0x2D,
- ProcessorFamilyIntelCorem5 = 0x2E,
- ProcessorFamilyIntelCorem7 = 0x2F,
- ProcessorFamilyAlpha = 0x30,
- ProcessorFamilyAlpha21064 = 0x31,
- ProcessorFamilyAlpha21066 = 0x32,
- ProcessorFamilyAlpha21164 = 0x33,
- ProcessorFamilyAlpha21164PC = 0x34,
- ProcessorFamilyAlpha21164a = 0x35,
- ProcessorFamilyAlpha21264 = 0x36,
- ProcessorFamilyAlpha21364 = 0x37,
- ProcessorFamilyAmdTurionIIUltraDualCoreMobileM = 0x38,
- ProcessorFamilyAmdTurionIIDualCoreMobileM = 0x39,
- ProcessorFamilyAmdAthlonIIDualCoreM = 0x3A,
- ProcessorFamilyAmdOpteron6100Series = 0x3B,
- ProcessorFamilyAmdOpteron4100Series = 0x3C,
- ProcessorFamilyAmdOpteron6200Series = 0x3D,
- ProcessorFamilyAmdOpteron4200Series = 0x3E,
- ProcessorFamilyAmdFxSeries = 0x3F,
- ProcessorFamilyMips = 0x40,
- ProcessorFamilyMIPSR4000 = 0x41,
- ProcessorFamilyMIPSR4200 = 0x42,
- ProcessorFamilyMIPSR4400 = 0x43,
- ProcessorFamilyMIPSR4600 = 0x44,
- ProcessorFamilyMIPSR10000 = 0x45,
- ProcessorFamilyAmdCSeries = 0x46,
- ProcessorFamilyAmdESeries = 0x47,
- ProcessorFamilyAmdASeries = 0x48, ///< SMBIOS spec 2.8.0 updated the name
- ProcessorFamilyAmdGSeries = 0x49,
- ProcessorFamilyAmdZSeries = 0x4A,
- ProcessorFamilyAmdRSeries = 0x4B,
- ProcessorFamilyAmdOpteron4300 = 0x4C,
- ProcessorFamilyAmdOpteron6300 = 0x4D,
- ProcessorFamilyAmdOpteron3300 = 0x4E,
- ProcessorFamilyAmdFireProSeries = 0x4F,
- ProcessorFamilySparc = 0x50,
- ProcessorFamilySuperSparc = 0x51,
- ProcessorFamilymicroSparcII = 0x52,
- ProcessorFamilymicroSparcIIep = 0x53,
- ProcessorFamilyUltraSparc = 0x54,
- ProcessorFamilyUltraSparcII = 0x55,
- ProcessorFamilyUltraSparcIii = 0x56,
- ProcessorFamilyUltraSparcIII = 0x57,
- ProcessorFamilyUltraSparcIIIi = 0x58,
- ProcessorFamily68040 = 0x60,
- ProcessorFamily68xxx = 0x61,
- ProcessorFamily68000 = 0x62,
- ProcessorFamily68010 = 0x63,
- ProcessorFamily68020 = 0x64,
- ProcessorFamily68030 = 0x65,
- ProcessorFamilyAmdAthlonX4QuadCore = 0x66,
- ProcessorFamilyAmdOpteronX1000Series = 0x67,
- ProcessorFamilyAmdOpteronX2000Series = 0x68,
- ProcessorFamilyAmdOpteronASeries = 0x69,
- ProcessorFamilyAmdOpteronX3000Series = 0x6A,
- ProcessorFamilyAmdZen = 0x6B,
- ProcessorFamilyHobbit = 0x70,
- ProcessorFamilyCrusoeTM5000 = 0x78,
- ProcessorFamilyCrusoeTM3000 = 0x79,
- ProcessorFamilyEfficeonTM8000 = 0x7A,
- ProcessorFamilyWeitek = 0x80,
- ProcessorFamilyItanium = 0x82,
- ProcessorFamilyAmdAthlon64 = 0x83,
- ProcessorFamilyAmdOpteron = 0x84,
- ProcessorFamilyAmdSempron = 0x85,
- ProcessorFamilyAmdTurion64Mobile = 0x86,
- ProcessorFamilyDualCoreAmdOpteron = 0x87,
- ProcessorFamilyAmdAthlon64X2DualCore = 0x88,
- ProcessorFamilyAmdTurion64X2Mobile = 0x89,
- ProcessorFamilyQuadCoreAmdOpteron = 0x8A,
- ProcessorFamilyThirdGenerationAmdOpteron = 0x8B,
- ProcessorFamilyAmdPhenomFxQuadCore = 0x8C,
- ProcessorFamilyAmdPhenomX4QuadCore = 0x8D,
- ProcessorFamilyAmdPhenomX2DualCore = 0x8E,
- ProcessorFamilyAmdAthlonX2DualCore = 0x8F,
- ProcessorFamilyPARISC = 0x90,
- ProcessorFamilyPaRisc8500 = 0x91,
- ProcessorFamilyPaRisc8000 = 0x92,
- ProcessorFamilyPaRisc7300LC = 0x93,
- ProcessorFamilyPaRisc7200 = 0x94,
- ProcessorFamilyPaRisc7100LC = 0x95,
- ProcessorFamilyPaRisc7100 = 0x96,
- ProcessorFamilyV30 = 0xA0,
- ProcessorFamilyQuadCoreIntelXeon3200Series = 0xA1,
- ProcessorFamilyDualCoreIntelXeon3000Series = 0xA2,
- ProcessorFamilyQuadCoreIntelXeon5300Series = 0xA3,
- ProcessorFamilyDualCoreIntelXeon5100Series = 0xA4,
- ProcessorFamilyDualCoreIntelXeon5000Series = 0xA5,
- ProcessorFamilyDualCoreIntelXeonLV = 0xA6,
- ProcessorFamilyDualCoreIntelXeonULV = 0xA7,
- ProcessorFamilyDualCoreIntelXeon7100Series = 0xA8,
- ProcessorFamilyQuadCoreIntelXeon5400Series = 0xA9,
- ProcessorFamilyQuadCoreIntelXeon = 0xAA,
- ProcessorFamilyDualCoreIntelXeon5200Series = 0xAB,
- ProcessorFamilyDualCoreIntelXeon7200Series = 0xAC,
- ProcessorFamilyQuadCoreIntelXeon7300Series = 0xAD,
- ProcessorFamilyQuadCoreIntelXeon7400Series = 0xAE,
- ProcessorFamilyMultiCoreIntelXeon7400Series = 0xAF,
- ProcessorFamilyPentiumIIIXeon = 0xB0,
- ProcessorFamilyPentiumIIISpeedStep = 0xB1,
- ProcessorFamilyPentium4 = 0xB2,
- ProcessorFamilyIntelXeon = 0xB3,
- ProcessorFamilyAS400 = 0xB4,
- ProcessorFamilyIntelXeonMP = 0xB5,
- ProcessorFamilyAMDAthlonXP = 0xB6,
- ProcessorFamilyAMDAthlonMP = 0xB7,
- ProcessorFamilyIntelItanium2 = 0xB8,
- ProcessorFamilyIntelPentiumM = 0xB9,
- ProcessorFamilyIntelCeleronD = 0xBA,
- ProcessorFamilyIntelPentiumD = 0xBB,
- ProcessorFamilyIntelPentiumEx = 0xBC,
- ProcessorFamilyIntelCoreSolo = 0xBD, ///< SMBIOS spec 2.6 updated this value
- ProcessorFamilyReserved = 0xBE,
- ProcessorFamilyIntelCore2 = 0xBF,
- ProcessorFamilyIntelCore2Solo = 0xC0,
- ProcessorFamilyIntelCore2Extreme = 0xC1,
- ProcessorFamilyIntelCore2Quad = 0xC2,
- ProcessorFamilyIntelCore2ExtremeMobile = 0xC3,
- ProcessorFamilyIntelCore2DuoMobile = 0xC4,
- ProcessorFamilyIntelCore2SoloMobile = 0xC5,
- ProcessorFamilyIntelCoreI7 = 0xC6,
- ProcessorFamilyDualCoreIntelCeleron = 0xC7,
- ProcessorFamilyIBM390 = 0xC8,
- ProcessorFamilyG4 = 0xC9,
- ProcessorFamilyG5 = 0xCA,
- ProcessorFamilyG6 = 0xCB,
- ProcessorFamilyzArchitecture = 0xCC,
- ProcessorFamilyIntelCoreI5 = 0xCD,
- ProcessorFamilyIntelCoreI3 = 0xCE,
- ProcessorFamilyIntelCoreI9 = 0xCF,
- ProcessorFamilyViaC7M = 0xD2,
- ProcessorFamilyViaC7D = 0xD3,
- ProcessorFamilyViaC7 = 0xD4,
- ProcessorFamilyViaEden = 0xD5,
- ProcessorFamilyMultiCoreIntelXeon = 0xD6,
- ProcessorFamilyDualCoreIntelXeon3Series = 0xD7,
- ProcessorFamilyQuadCoreIntelXeon3Series = 0xD8,
- ProcessorFamilyViaNano = 0xD9,
- ProcessorFamilyDualCoreIntelXeon5Series = 0xDA,
- ProcessorFamilyQuadCoreIntelXeon5Series = 0xDB,
- ProcessorFamilyDualCoreIntelXeon7Series = 0xDD,
- ProcessorFamilyQuadCoreIntelXeon7Series = 0xDE,
- ProcessorFamilyMultiCoreIntelXeon7Series = 0xDF,
- ProcessorFamilyMultiCoreIntelXeon3400Series = 0xE0,
- ProcessorFamilyAmdOpteron3000Series = 0xE4,
- ProcessorFamilyAmdSempronII = 0xE5,
- ProcessorFamilyEmbeddedAmdOpteronQuadCore = 0xE6,
- ProcessorFamilyAmdPhenomTripleCore = 0xE7,
- ProcessorFamilyAmdTurionUltraDualCoreMobile = 0xE8,
- ProcessorFamilyAmdTurionDualCoreMobile = 0xE9,
- ProcessorFamilyAmdAthlonDualCore = 0xEA,
- ProcessorFamilyAmdSempronSI = 0xEB,
- ProcessorFamilyAmdPhenomII = 0xEC,
- ProcessorFamilyAmdAthlonII = 0xED,
- ProcessorFamilySixCoreAmdOpteron = 0xEE,
- ProcessorFamilyAmdSempronM = 0xEF,
- ProcessorFamilyi860 = 0xFA,
- ProcessorFamilyi960 = 0xFB,
- ProcessorFamilyIndicatorFamily2 = 0xFE,
- ProcessorFamilyReserved1 = 0xFF
+ ProcessorFamilyOther = 0x01,
+ ProcessorFamilyUnknown = 0x02,
+ ProcessorFamily8086 = 0x03,
+ ProcessorFamily80286 = 0x04,
+ ProcessorFamilyIntel386 = 0x05,
+ ProcessorFamilyIntel486 = 0x06,
+ ProcessorFamily8087 = 0x07,
+ ProcessorFamily80287 = 0x08,
+ ProcessorFamily80387 = 0x09,
+ ProcessorFamily80487 = 0x0A,
+ ProcessorFamilyPentium = 0x0B,
+ ProcessorFamilyPentiumPro = 0x0C,
+ ProcessorFamilyPentiumII = 0x0D,
+ ProcessorFamilyPentiumMMX = 0x0E,
+ ProcessorFamilyCeleron = 0x0F,
+ ProcessorFamilyPentiumIIXeon = 0x10,
+ ProcessorFamilyPentiumIII = 0x11,
+ ProcessorFamilyM1 = 0x12,
+ ProcessorFamilyM2 = 0x13,
+ ProcessorFamilyIntelCeleronM = 0x14,
+ ProcessorFamilyIntelPentium4Ht = 0x15,
+ ProcessorFamilyIntel = 0x16,
+ ProcessorFamilyAmdDuron = 0x18,
+ ProcessorFamilyK5 = 0x19,
+ ProcessorFamilyK6 = 0x1A,
+ ProcessorFamilyK6_2 = 0x1B,
+ ProcessorFamilyK6_3 = 0x1C,
+ ProcessorFamilyAmdAthlon = 0x1D,
+ ProcessorFamilyAmd29000 = 0x1E,
+ ProcessorFamilyK6_2Plus = 0x1F,
+ ProcessorFamilyPowerPC = 0x20,
+ ProcessorFamilyPowerPC601 = 0x21,
+ ProcessorFamilyPowerPC603 = 0x22,
+ ProcessorFamilyPowerPC603Plus = 0x23,
+ ProcessorFamilyPowerPC604 = 0x24,
+ ProcessorFamilyPowerPC620 = 0x25,
+ ProcessorFamilyPowerPCx704 = 0x26,
+ ProcessorFamilyPowerPC750 = 0x27,
+ ProcessorFamilyIntelCoreDuo = 0x28,
+ ProcessorFamilyIntelCoreDuoMobile = 0x29,
+ ProcessorFamilyIntelCoreSoloMobile = 0x2A,
+ ProcessorFamilyIntelAtom = 0x2B,
+ ProcessorFamilyIntelCoreM = 0x2C,
+ ProcessorFamilyIntelCorem3 = 0x2D,
+ ProcessorFamilyIntelCorem5 = 0x2E,
+ ProcessorFamilyIntelCorem7 = 0x2F,
+ ProcessorFamilyAlpha = 0x30,
+ ProcessorFamilyAlpha21064 = 0x31,
+ ProcessorFamilyAlpha21066 = 0x32,
+ ProcessorFamilyAlpha21164 = 0x33,
+ ProcessorFamilyAlpha21164PC = 0x34,
+ ProcessorFamilyAlpha21164a = 0x35,
+ ProcessorFamilyAlpha21264 = 0x36,
+ ProcessorFamilyAlpha21364 = 0x37,
+ ProcessorFamilyAmdTurionIIUltraDualCoreMobileM = 0x38,
+ ProcessorFamilyAmdTurionIIDualCoreMobileM = 0x39,
+ ProcessorFamilyAmdAthlonIIDualCoreM = 0x3A,
+ ProcessorFamilyAmdOpteron6100Series = 0x3B,
+ ProcessorFamilyAmdOpteron4100Series = 0x3C,
+ ProcessorFamilyAmdOpteron6200Series = 0x3D,
+ ProcessorFamilyAmdOpteron4200Series = 0x3E,
+ ProcessorFamilyAmdFxSeries = 0x3F,
+ ProcessorFamilyMips = 0x40,
+ ProcessorFamilyMIPSR4000 = 0x41,
+ ProcessorFamilyMIPSR4200 = 0x42,
+ ProcessorFamilyMIPSR4400 = 0x43,
+ ProcessorFamilyMIPSR4600 = 0x44,
+ ProcessorFamilyMIPSR10000 = 0x45,
+ ProcessorFamilyAmdCSeries = 0x46,
+ ProcessorFamilyAmdESeries = 0x47,
+ ProcessorFamilyAmdASeries = 0x48, ///< SMBIOS spec 2.8.0 updated the name
+ ProcessorFamilyAmdGSeries = 0x49,
+ ProcessorFamilyAmdZSeries = 0x4A,
+ ProcessorFamilyAmdRSeries = 0x4B,
+ ProcessorFamilyAmdOpteron4300 = 0x4C,
+ ProcessorFamilyAmdOpteron6300 = 0x4D,
+ ProcessorFamilyAmdOpteron3300 = 0x4E,
+ ProcessorFamilyAmdFireProSeries = 0x4F,
+ ProcessorFamilySparc = 0x50,
+ ProcessorFamilySuperSparc = 0x51,
+ ProcessorFamilymicroSparcII = 0x52,
+ ProcessorFamilymicroSparcIIep = 0x53,
+ ProcessorFamilyUltraSparc = 0x54,
+ ProcessorFamilyUltraSparcII = 0x55,
+ ProcessorFamilyUltraSparcIii = 0x56,
+ ProcessorFamilyUltraSparcIII = 0x57,
+ ProcessorFamilyUltraSparcIIIi = 0x58,
+ ProcessorFamily68040 = 0x60,
+ ProcessorFamily68xxx = 0x61,
+ ProcessorFamily68000 = 0x62,
+ ProcessorFamily68010 = 0x63,
+ ProcessorFamily68020 = 0x64,
+ ProcessorFamily68030 = 0x65,
+ ProcessorFamilyAmdAthlonX4QuadCore = 0x66,
+ ProcessorFamilyAmdOpteronX1000Series = 0x67,
+ ProcessorFamilyAmdOpteronX2000Series = 0x68,
+ ProcessorFamilyAmdOpteronASeries = 0x69,
+ ProcessorFamilyAmdOpteronX3000Series = 0x6A,
+ ProcessorFamilyAmdZen = 0x6B,
+ ProcessorFamilyHobbit = 0x70,
+ ProcessorFamilyCrusoeTM5000 = 0x78,
+ ProcessorFamilyCrusoeTM3000 = 0x79,
+ ProcessorFamilyEfficeonTM8000 = 0x7A,
+ ProcessorFamilyWeitek = 0x80,
+ ProcessorFamilyItanium = 0x82,
+ ProcessorFamilyAmdAthlon64 = 0x83,
+ ProcessorFamilyAmdOpteron = 0x84,
+ ProcessorFamilyAmdSempron = 0x85,
+ ProcessorFamilyAmdTurion64Mobile = 0x86,
+ ProcessorFamilyDualCoreAmdOpteron = 0x87,
+ ProcessorFamilyAmdAthlon64X2DualCore = 0x88,
+ ProcessorFamilyAmdTurion64X2Mobile = 0x89,
+ ProcessorFamilyQuadCoreAmdOpteron = 0x8A,
+ ProcessorFamilyThirdGenerationAmdOpteron = 0x8B,
+ ProcessorFamilyAmdPhenomFxQuadCore = 0x8C,
+ ProcessorFamilyAmdPhenomX4QuadCore = 0x8D,
+ ProcessorFamilyAmdPhenomX2DualCore = 0x8E,
+ ProcessorFamilyAmdAthlonX2DualCore = 0x8F,
+ ProcessorFamilyPARISC = 0x90,
+ ProcessorFamilyPaRisc8500 = 0x91,
+ ProcessorFamilyPaRisc8000 = 0x92,
+ ProcessorFamilyPaRisc7300LC = 0x93,
+ ProcessorFamilyPaRisc7200 = 0x94,
+ ProcessorFamilyPaRisc7100LC = 0x95,
+ ProcessorFamilyPaRisc7100 = 0x96,
+ ProcessorFamilyV30 = 0xA0,
+ ProcessorFamilyQuadCoreIntelXeon3200Series = 0xA1,
+ ProcessorFamilyDualCoreIntelXeon3000Series = 0xA2,
+ ProcessorFamilyQuadCoreIntelXeon5300Series = 0xA3,
+ ProcessorFamilyDualCoreIntelXeon5100Series = 0xA4,
+ ProcessorFamilyDualCoreIntelXeon5000Series = 0xA5,
+ ProcessorFamilyDualCoreIntelXeonLV = 0xA6,
+ ProcessorFamilyDualCoreIntelXeonULV = 0xA7,
+ ProcessorFamilyDualCoreIntelXeon7100Series = 0xA8,
+ ProcessorFamilyQuadCoreIntelXeon5400Series = 0xA9,
+ ProcessorFamilyQuadCoreIntelXeon = 0xAA,
+ ProcessorFamilyDualCoreIntelXeon5200Series = 0xAB,
+ ProcessorFamilyDualCoreIntelXeon7200Series = 0xAC,
+ ProcessorFamilyQuadCoreIntelXeon7300Series = 0xAD,
+ ProcessorFamilyQuadCoreIntelXeon7400Series = 0xAE,
+ ProcessorFamilyMultiCoreIntelXeon7400Series = 0xAF,
+ ProcessorFamilyPentiumIIIXeon = 0xB0,
+ ProcessorFamilyPentiumIIISpeedStep = 0xB1,
+ ProcessorFamilyPentium4 = 0xB2,
+ ProcessorFamilyIntelXeon = 0xB3,
+ ProcessorFamilyAS400 = 0xB4,
+ ProcessorFamilyIntelXeonMP = 0xB5,
+ ProcessorFamilyAMDAthlonXP = 0xB6,
+ ProcessorFamilyAMDAthlonMP = 0xB7,
+ ProcessorFamilyIntelItanium2 = 0xB8,
+ ProcessorFamilyIntelPentiumM = 0xB9,
+ ProcessorFamilyIntelCeleronD = 0xBA,
+ ProcessorFamilyIntelPentiumD = 0xBB,
+ ProcessorFamilyIntelPentiumEx = 0xBC,
+ ProcessorFamilyIntelCoreSolo = 0xBD, ///< SMBIOS spec 2.6 updated this value
+ ProcessorFamilyReserved = 0xBE,
+ ProcessorFamilyIntelCore2 = 0xBF,
+ ProcessorFamilyIntelCore2Solo = 0xC0,
+ ProcessorFamilyIntelCore2Extreme = 0xC1,
+ ProcessorFamilyIntelCore2Quad = 0xC2,
+ ProcessorFamilyIntelCore2ExtremeMobile = 0xC3,
+ ProcessorFamilyIntelCore2DuoMobile = 0xC4,
+ ProcessorFamilyIntelCore2SoloMobile = 0xC5,
+ ProcessorFamilyIntelCoreI7 = 0xC6,
+ ProcessorFamilyDualCoreIntelCeleron = 0xC7,
+ ProcessorFamilyIBM390 = 0xC8,
+ ProcessorFamilyG4 = 0xC9,
+ ProcessorFamilyG5 = 0xCA,
+ ProcessorFamilyG6 = 0xCB,
+ ProcessorFamilyzArchitecture = 0xCC,
+ ProcessorFamilyIntelCoreI5 = 0xCD,
+ ProcessorFamilyIntelCoreI3 = 0xCE,
+ ProcessorFamilyIntelCoreI9 = 0xCF,
+ ProcessorFamilyViaC7M = 0xD2,
+ ProcessorFamilyViaC7D = 0xD3,
+ ProcessorFamilyViaC7 = 0xD4,
+ ProcessorFamilyViaEden = 0xD5,
+ ProcessorFamilyMultiCoreIntelXeon = 0xD6,
+ ProcessorFamilyDualCoreIntelXeon3Series = 0xD7,
+ ProcessorFamilyQuadCoreIntelXeon3Series = 0xD8,
+ ProcessorFamilyViaNano = 0xD9,
+ ProcessorFamilyDualCoreIntelXeon5Series = 0xDA,
+ ProcessorFamilyQuadCoreIntelXeon5Series = 0xDB,
+ ProcessorFamilyDualCoreIntelXeon7Series = 0xDD,
+ ProcessorFamilyQuadCoreIntelXeon7Series = 0xDE,
+ ProcessorFamilyMultiCoreIntelXeon7Series = 0xDF,
+ ProcessorFamilyMultiCoreIntelXeon3400Series = 0xE0,
+ ProcessorFamilyAmdOpteron3000Series = 0xE4,
+ ProcessorFamilyAmdSempronII = 0xE5,
+ ProcessorFamilyEmbeddedAmdOpteronQuadCore = 0xE6,
+ ProcessorFamilyAmdPhenomTripleCore = 0xE7,
+ ProcessorFamilyAmdTurionUltraDualCoreMobile = 0xE8,
+ ProcessorFamilyAmdTurionDualCoreMobile = 0xE9,
+ ProcessorFamilyAmdAthlonDualCore = 0xEA,
+ ProcessorFamilyAmdSempronSI = 0xEB,
+ ProcessorFamilyAmdPhenomII = 0xEC,
+ ProcessorFamilyAmdAthlonII = 0xED,
+ ProcessorFamilySixCoreAmdOpteron = 0xEE,
+ ProcessorFamilyAmdSempronM = 0xEF,
+ ProcessorFamilyi860 = 0xFA,
+ ProcessorFamilyi960 = 0xFB,
+ ProcessorFamilyIndicatorFamily2 = 0xFE,
+ ProcessorFamilyReserved1 = 0xFF
} PROCESSOR_FAMILY_DATA;
///
/// Processor Information2 - Processor Family2.
///
typedef enum {
- ProcessorFamilyARMv7 = 0x0100,
- ProcessorFamilyARMv8 = 0x0101,
- ProcessorFamilySH3 = 0x0104,
- ProcessorFamilySH4 = 0x0105,
- ProcessorFamilyARM = 0x0118,
- ProcessorFamilyStrongARM = 0x0119,
- ProcessorFamily6x86 = 0x012C,
- ProcessorFamilyMediaGX = 0x012D,
- ProcessorFamilyMII = 0x012E,
- ProcessorFamilyWinChip = 0x0140,
- ProcessorFamilyDSP = 0x015E,
- ProcessorFamilyVideoProcessor = 0x01F4,
- ProcessorFamilyRiscvRV32 = 0x0200,
- ProcessorFamilyRiscVRV64 = 0x0201,
- ProcessorFamilyRiscVRV128 = 0x0202
+ ProcessorFamilyARMv7 = 0x0100,
+ ProcessorFamilyARMv8 = 0x0101,
+ ProcessorFamilyARMv9 = 0x0102,
+ ProcessorFamilySH3 = 0x0104,
+ ProcessorFamilySH4 = 0x0105,
+ ProcessorFamilyARM = 0x0118,
+ ProcessorFamilyStrongARM = 0x0119,
+ ProcessorFamily6x86 = 0x012C,
+ ProcessorFamilyMediaGX = 0x012D,
+ ProcessorFamilyMII = 0x012E,
+ ProcessorFamilyWinChip = 0x0140,
+ ProcessorFamilyDSP = 0x015E,
+ ProcessorFamilyVideoProcessor = 0x01F4,
+ ProcessorFamilyRiscvRV32 = 0x0200,
+ ProcessorFamilyRiscVRV64 = 0x0201,
+ ProcessorFamilyRiscVRV128 = 0x0202,
+ ProcessorFamilyLoongArch = 0x0258,
+ ProcessorFamilyLoongson1 = 0x0259,
+ ProcessorFamilyLoongson2 = 0x025A,
+ ProcessorFamilyLoongson3 = 0x025B,
+ ProcessorFamilyLoongson2K = 0x025C,
+ ProcessorFamilyLoongson3A = 0x025D,
+ ProcessorFamilyLoongson3B = 0x025E,
+ ProcessorFamilyLoongson3C = 0x025F,
+ ProcessorFamilyLoongson3D = 0x0260,
+ ProcessorFamilyLoongson3E = 0x0261,
+ ProcessorFamilyDualCoreLoongson2K = 0x0262,
+ ProcessorFamilyQuadCoreLoongson3A = 0x026C,
+ ProcessorFamilyMultiCoreLoongson3A = 0x026D,
+ ProcessorFamilyQuadCoreLoongson3B = 0x026E,
+ ProcessorFamilyMultiCoreLoongson3B = 0x026F,
+ ProcessorFamilyMultiCoreLoongson3C = 0x0270,
+ ProcessorFamilyMultiCoreLoongson3D = 0x0271
} PROCESSOR_FAMILY2_DATA;
///
/// Processor Information - Voltage.
///
typedef struct {
- UINT8 ProcessorVoltageCapability5V :1;
- UINT8 ProcessorVoltageCapability3_3V :1;
- UINT8 ProcessorVoltageCapability2_9V :1;
- UINT8 ProcessorVoltageCapabilityReserved :1; ///< Bit 3, must be zero.
- UINT8 ProcessorVoltageReserved :3; ///< Bits 4-6, must be zero.
- UINT8 ProcessorVoltageIndicateLegacy :1;
+ UINT8 ProcessorVoltageCapability5V : 1;
+ UINT8 ProcessorVoltageCapability3_3V : 1;
+ UINT8 ProcessorVoltageCapability2_9V : 1;
+ UINT8 ProcessorVoltageCapabilityReserved : 1; ///< Bit 3, must be zero.
+ UINT8 ProcessorVoltageReserved : 3; ///< Bits 4-6, must be zero.
+ UINT8 ProcessorVoltageIndicateLegacy : 1;
} PROCESSOR_VOLTAGE;
///
/// Processor Information - Processor Upgrade.
///
typedef enum {
- ProcessorUpgradeOther = 0x01,
- ProcessorUpgradeUnknown = 0x02,
- ProcessorUpgradeDaughterBoard = 0x03,
- ProcessorUpgradeZIFSocket = 0x04,
- ProcessorUpgradePiggyBack = 0x05, ///< Replaceable.
- ProcessorUpgradeNone = 0x06,
- ProcessorUpgradeLIFSocket = 0x07,
- ProcessorUpgradeSlot1 = 0x08,
- ProcessorUpgradeSlot2 = 0x09,
- ProcessorUpgrade370PinSocket = 0x0A,
- ProcessorUpgradeSlotA = 0x0B,
- ProcessorUpgradeSlotM = 0x0C,
- ProcessorUpgradeSocket423 = 0x0D,
- ProcessorUpgradeSocketA = 0x0E, ///< Socket 462.
- ProcessorUpgradeSocket478 = 0x0F,
- ProcessorUpgradeSocket754 = 0x10,
- ProcessorUpgradeSocket940 = 0x11,
- ProcessorUpgradeSocket939 = 0x12,
- ProcessorUpgradeSocketmPGA604 = 0x13,
- ProcessorUpgradeSocketLGA771 = 0x14,
- ProcessorUpgradeSocketLGA775 = 0x15,
- ProcessorUpgradeSocketS1 = 0x16,
- ProcessorUpgradeAM2 = 0x17,
- ProcessorUpgradeF1207 = 0x18,
- ProcessorSocketLGA1366 = 0x19,
- ProcessorUpgradeSocketG34 = 0x1A,
- ProcessorUpgradeSocketAM3 = 0x1B,
- ProcessorUpgradeSocketC32 = 0x1C,
- ProcessorUpgradeSocketLGA1156 = 0x1D,
- ProcessorUpgradeSocketLGA1567 = 0x1E,
- ProcessorUpgradeSocketPGA988A = 0x1F,
- ProcessorUpgradeSocketBGA1288 = 0x20,
- ProcessorUpgradeSocketrPGA988B = 0x21,
- ProcessorUpgradeSocketBGA1023 = 0x22,
- ProcessorUpgradeSocketBGA1224 = 0x23,
- ProcessorUpgradeSocketLGA1155 = 0x24, ///< SMBIOS spec 2.8.0 updated the name
- ProcessorUpgradeSocketLGA1356 = 0x25,
- ProcessorUpgradeSocketLGA2011 = 0x26,
- ProcessorUpgradeSocketFS1 = 0x27,
- ProcessorUpgradeSocketFS2 = 0x28,
- ProcessorUpgradeSocketFM1 = 0x29,
- ProcessorUpgradeSocketFM2 = 0x2A,
+ ProcessorUpgradeOther = 0x01,
+ ProcessorUpgradeUnknown = 0x02,
+ ProcessorUpgradeDaughterBoard = 0x03,
+ ProcessorUpgradeZIFSocket = 0x04,
+ ProcessorUpgradePiggyBack = 0x05, ///< Replaceable.
+ ProcessorUpgradeNone = 0x06,
+ ProcessorUpgradeLIFSocket = 0x07,
+ ProcessorUpgradeSlot1 = 0x08,
+ ProcessorUpgradeSlot2 = 0x09,
+ ProcessorUpgrade370PinSocket = 0x0A,
+ ProcessorUpgradeSlotA = 0x0B,
+ ProcessorUpgradeSlotM = 0x0C,
+ ProcessorUpgradeSocket423 = 0x0D,
+ ProcessorUpgradeSocketA = 0x0E, ///< Socket 462.
+ ProcessorUpgradeSocket478 = 0x0F,
+ ProcessorUpgradeSocket754 = 0x10,
+ ProcessorUpgradeSocket940 = 0x11,
+ ProcessorUpgradeSocket939 = 0x12,
+ ProcessorUpgradeSocketmPGA604 = 0x13,
+ ProcessorUpgradeSocketLGA771 = 0x14,
+ ProcessorUpgradeSocketLGA775 = 0x15,
+ ProcessorUpgradeSocketS1 = 0x16,
+ ProcessorUpgradeAM2 = 0x17,
+ ProcessorUpgradeF1207 = 0x18,
+ ProcessorSocketLGA1366 = 0x19,
+ ProcessorUpgradeSocketG34 = 0x1A,
+ ProcessorUpgradeSocketAM3 = 0x1B,
+ ProcessorUpgradeSocketC32 = 0x1C,
+ ProcessorUpgradeSocketLGA1156 = 0x1D,
+ ProcessorUpgradeSocketLGA1567 = 0x1E,
+ ProcessorUpgradeSocketPGA988A = 0x1F,
+ ProcessorUpgradeSocketBGA1288 = 0x20,
+ ProcessorUpgradeSocketrPGA988B = 0x21,
+ ProcessorUpgradeSocketBGA1023 = 0x22,
+ ProcessorUpgradeSocketBGA1224 = 0x23,
+ ProcessorUpgradeSocketLGA1155 = 0x24, ///< SMBIOS spec 2.8.0 updated the name
+ ProcessorUpgradeSocketLGA1356 = 0x25,
+ ProcessorUpgradeSocketLGA2011 = 0x26,
+ ProcessorUpgradeSocketFS1 = 0x27,
+ ProcessorUpgradeSocketFS2 = 0x28,
+ ProcessorUpgradeSocketFM1 = 0x29,
+ ProcessorUpgradeSocketFM2 = 0x2A,
ProcessorUpgradeSocketLGA2011_3 = 0x2B,
ProcessorUpgradeSocketLGA1356_3 = 0x2C,
ProcessorUpgradeSocketLGA1150 = 0x2D,
@@ -813,69 +855,86 @@ typedef enum {
ProcessorUpgradeSocketBGA1528 = 0x3C,
ProcessorUpgradeSocketLGA4189 = 0x3D,
ProcessorUpgradeSocketLGA1200 = 0x3E,
- ProcessorUpgradeSocketLGA4677 = 0x3F
+ ProcessorUpgradeSocketLGA4677 = 0x3F,
+ ProcessorUpgradeSocketLGA1700 = 0x40,
+ ProcessorUpgradeSocketBGA1744 = 0x41,
+ ProcessorUpgradeSocketBGA1781 = 0x42,
+ ProcessorUpgradeSocketBGA1211 = 0x43,
+ ProcessorUpgradeSocketBGA2422 = 0x44,
+ ProcessorUpgradeSocketLGA1211 = 0x45,
+ ProcessorUpgradeSocketLGA2422 = 0x46,
+ ProcessorUpgradeSocketLGA5773 = 0x47,
+ ProcessorUpgradeSocketBGA5773 = 0x48,
+ ProcessorUpgradeSocketAM5 = 0x49,
+ ProcessorUpgradeSocketSP5 = 0x4A,
+ ProcessorUpgradeSocketSP6 = 0x4B,
+ ProcessorUpgradeSocketBGA883 = 0x4C,
+ ProcessorUpgradeSocketBGA1190 = 0x4D,
+ ProcessorUpgradeSocketBGA4129 = 0x4E,
+ ProcessorUpgradeSocketLGA4710 = 0x4F,
+ ProcessorUpgradeSocketLGA7529 = 0x50
} PROCESSOR_UPGRADE;
///
/// Processor ID Field Description
///
typedef struct {
- UINT32 ProcessorSteppingId:4;
- UINT32 ProcessorModel: 4;
- UINT32 ProcessorFamily: 4;
- UINT32 ProcessorType: 2;
- UINT32 ProcessorReserved1: 2;
- UINT32 ProcessorXModel: 4;
- UINT32 ProcessorXFamily: 8;
- UINT32 ProcessorReserved2: 4;
+ UINT32 ProcessorSteppingId : 4;
+ UINT32 ProcessorModel : 4;
+ UINT32 ProcessorFamily : 4;
+ UINT32 ProcessorType : 2;
+ UINT32 ProcessorReserved1 : 2;
+ UINT32 ProcessorXModel : 4;
+ UINT32 ProcessorXFamily : 8;
+ UINT32 ProcessorReserved2 : 4;
} PROCESSOR_SIGNATURE;
typedef struct {
- UINT32 ProcessorFpu :1;
- UINT32 ProcessorVme :1;
- UINT32 ProcessorDe :1;
- UINT32 ProcessorPse :1;
- UINT32 ProcessorTsc :1;
- UINT32 ProcessorMsr :1;
- UINT32 ProcessorPae :1;
- UINT32 ProcessorMce :1;
- UINT32 ProcessorCx8 :1;
- UINT32 ProcessorApic :1;
- UINT32 ProcessorReserved1 :1;
- UINT32 ProcessorSep :1;
- UINT32 ProcessorMtrr :1;
- UINT32 ProcessorPge :1;
- UINT32 ProcessorMca :1;
- UINT32 ProcessorCmov :1;
- UINT32 ProcessorPat :1;
- UINT32 ProcessorPse36 :1;
- UINT32 ProcessorPsn :1;
- UINT32 ProcessorClfsh :1;
- UINT32 ProcessorReserved2 :1;
- UINT32 ProcessorDs :1;
- UINT32 ProcessorAcpi :1;
- UINT32 ProcessorMmx :1;
- UINT32 ProcessorFxsr :1;
- UINT32 ProcessorSse :1;
- UINT32 ProcessorSse2 :1;
- UINT32 ProcessorSs :1;
- UINT32 ProcessorReserved3 :1;
- UINT32 ProcessorTm :1;
- UINT32 ProcessorReserved4 :2;
+ UINT32 ProcessorFpu : 1;
+ UINT32 ProcessorVme : 1;
+ UINT32 ProcessorDe : 1;
+ UINT32 ProcessorPse : 1;
+ UINT32 ProcessorTsc : 1;
+ UINT32 ProcessorMsr : 1;
+ UINT32 ProcessorPae : 1;
+ UINT32 ProcessorMce : 1;
+ UINT32 ProcessorCx8 : 1;
+ UINT32 ProcessorApic : 1;
+ UINT32 ProcessorReserved1 : 1;
+ UINT32 ProcessorSep : 1;
+ UINT32 ProcessorMtrr : 1;
+ UINT32 ProcessorPge : 1;
+ UINT32 ProcessorMca : 1;
+ UINT32 ProcessorCmov : 1;
+ UINT32 ProcessorPat : 1;
+ UINT32 ProcessorPse36 : 1;
+ UINT32 ProcessorPsn : 1;
+ UINT32 ProcessorClfsh : 1;
+ UINT32 ProcessorReserved2 : 1;
+ UINT32 ProcessorDs : 1;
+ UINT32 ProcessorAcpi : 1;
+ UINT32 ProcessorMmx : 1;
+ UINT32 ProcessorFxsr : 1;
+ UINT32 ProcessorSse : 1;
+ UINT32 ProcessorSse2 : 1;
+ UINT32 ProcessorSs : 1;
+ UINT32 ProcessorReserved3 : 1;
+ UINT32 ProcessorTm : 1;
+ UINT32 ProcessorReserved4 : 2;
} PROCESSOR_FEATURE_FLAGS;
typedef struct {
- UINT16 ProcessorReserved1 :1;
- UINT16 ProcessorUnknown :1;
- UINT16 Processor64BitCapable :1;
- UINT16 ProcessorMultiCore :1;
- UINT16 ProcessorHardwareThread :1;
- UINT16 ProcessorExecuteProtection :1;
- UINT16 ProcessorEnhancedVirtualization :1;
- UINT16 ProcessorPowerPerformanceCtrl :1;
- UINT16 Processor128BitCapable :1;
- UINT16 ProcessorArm64SocId :1;
- UINT16 ProcessorReserved2 :6;
+ UINT16 ProcessorReserved1 : 1;
+ UINT16 ProcessorUnknown : 1;
+ UINT16 Processor64BitCapable : 1;
+ UINT16 ProcessorMultiCore : 1;
+ UINT16 ProcessorHardwareThread : 1;
+ UINT16 ProcessorExecuteProtection : 1;
+ UINT16 ProcessorEnhancedVirtualization : 1;
+ UINT16 ProcessorPowerPerformanceCtrl : 1;
+ UINT16 Processor128BitCapable : 1;
+ UINT16 ProcessorArm64SocId : 1;
+ UINT16 ProcessorReserved2 : 6;
} PROCESSOR_CHARACTERISTIC_FLAGS;
///
@@ -883,17 +942,17 @@ typedef struct {
///
typedef union {
struct {
- UINT8 CpuStatus :3; ///< Indicates the status of the processor.
- UINT8 Reserved1 :3; ///< Reserved for future use. Must be set to zero.
- UINT8 SocketPopulated :1; ///< Indicates if the processor socket is populated or not.
- UINT8 Reserved2 :1; ///< Reserved for future use. Must be set to zero.
+ UINT8 CpuStatus : 3; ///< Indicates the status of the processor.
+ UINT8 Reserved1 : 3; ///< Reserved for future use. Must be set to zero.
+ UINT8 SocketPopulated : 1; ///< Indicates if the processor socket is populated or not.
+ UINT8 Reserved2 : 1; ///< Reserved for future use. Must be set to zero.
} Bits;
- UINT8 Data;
+ UINT8 Data;
} PROCESSOR_STATUS_DATA;
typedef struct {
- PROCESSOR_SIGNATURE Signature;
- PROCESSOR_FEATURE_FLAGS FeatureFlags;
+ PROCESSOR_SIGNATURE Signature;
+ PROCESSOR_FEATURE_FLAGS FeatureFlags;
} PROCESSOR_ID_DATA;
///
@@ -906,42 +965,46 @@ typedef struct {
/// to describe the main CPU, and a second structure to describe the 80487 co-processor.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- SMBIOS_TABLE_STRING Socket;
- UINT8 ProcessorType; ///< The enumeration value from PROCESSOR_TYPE_DATA.
- UINT8 ProcessorFamily; ///< The enumeration value from PROCESSOR_FAMILY_DATA.
- SMBIOS_TABLE_STRING ProcessorManufacturer;
- PROCESSOR_ID_DATA ProcessorId;
- SMBIOS_TABLE_STRING ProcessorVersion;
- PROCESSOR_VOLTAGE Voltage;
- UINT16 ExternalClock;
- UINT16 MaxSpeed;
- UINT16 CurrentSpeed;
- UINT8 Status;
- UINT8 ProcessorUpgrade; ///< The enumeration value from PROCESSOR_UPGRADE.
- UINT16 L1CacheHandle;
- UINT16 L2CacheHandle;
- UINT16 L3CacheHandle;
- SMBIOS_TABLE_STRING SerialNumber;
- SMBIOS_TABLE_STRING AssetTag;
- SMBIOS_TABLE_STRING PartNumber;
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING Socket;
+ UINT8 ProcessorType; ///< The enumeration value from PROCESSOR_TYPE_DATA.
+ UINT8 ProcessorFamily; ///< The enumeration value from PROCESSOR_FAMILY_DATA.
+ SMBIOS_TABLE_STRING ProcessorManufacturer;
+ PROCESSOR_ID_DATA ProcessorId;
+ SMBIOS_TABLE_STRING ProcessorVersion;
+ PROCESSOR_VOLTAGE Voltage;
+ UINT16 ExternalClock;
+ UINT16 MaxSpeed;
+ UINT16 CurrentSpeed;
+ UINT8 Status;
+ UINT8 ProcessorUpgrade; ///< The enumeration value from PROCESSOR_UPGRADE.
+ UINT16 L1CacheHandle;
+ UINT16 L2CacheHandle;
+ UINT16 L3CacheHandle;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING AssetTag;
+ SMBIOS_TABLE_STRING PartNumber;
//
// Add for smbios 2.5
//
- UINT8 CoreCount;
- UINT8 EnabledCoreCount;
- UINT8 ThreadCount;
- UINT16 ProcessorCharacteristics;
+ UINT8 CoreCount;
+ UINT8 EnabledCoreCount;
+ UINT8 ThreadCount;
+ UINT16 ProcessorCharacteristics;
//
// Add for smbios 2.6
//
- UINT16 ProcessorFamily2;
+ UINT16 ProcessorFamily2;
//
// Add for smbios 3.0
//
- UINT16 CoreCount2;
- UINT16 EnabledCoreCount2;
- UINT16 ThreadCount2;
+ UINT16 CoreCount2;
+ UINT16 EnabledCoreCount2;
+ UINT16 ThreadCount2;
+ //
+ // Add for smbios 3.6
+ //
+ UINT16 ThreadEnabled;
} SMBIOS_TABLE_TYPE4;
///
@@ -962,13 +1025,13 @@ typedef enum {
/// Memory Controller Error Correcting Capability.
///
typedef struct {
- UINT8 Other :1;
- UINT8 Unknown :1;
- UINT8 None :1;
- UINT8 SingleBitErrorCorrect :1;
- UINT8 DoubleBitErrorCorrect :1;
- UINT8 ErrorScrubbing :1;
- UINT8 Reserved :2;
+ UINT8 Other : 1;
+ UINT8 Unknown : 1;
+ UINT8 None : 1;
+ UINT8 SingleBitErrorCorrect : 1;
+ UINT8 DoubleBitErrorCorrect : 1;
+ UINT8 ErrorScrubbing : 1;
+ UINT8 Reserved : 2;
} MEMORY_ERROR_CORRECT_CAPABILITY;
///
@@ -988,12 +1051,12 @@ typedef enum {
/// Memory Controller Information - Memory Speeds.
///
typedef struct {
- UINT16 Other :1;
- UINT16 Unknown :1;
- UINT16 SeventyNs:1;
- UINT16 SixtyNs :1;
- UINT16 FiftyNs :1;
- UINT16 Reserved :11;
+ UINT16 Other : 1;
+ UINT16 Unknown : 1;
+ UINT16 SeventyNs : 1;
+ UINT16 SixtyNs : 1;
+ UINT16 FiftyNs : 1;
+ UINT16 Reserved : 11;
} MEMORY_SPEED_TYPE;
///
@@ -1009,43 +1072,43 @@ typedef struct {
/// to properly display the system's memory attributes.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT8 ErrDetectMethod; ///< The enumeration value from MEMORY_ERROR_DETECT_METHOD.
- MEMORY_ERROR_CORRECT_CAPABILITY ErrCorrectCapability;
- UINT8 SupportInterleave; ///< The enumeration value from MEMORY_SUPPORT_INTERLEAVE_TYPE.
- UINT8 CurrentInterleave; ///< The enumeration value from MEMORY_SUPPORT_INTERLEAVE_TYPE .
- UINT8 MaxMemoryModuleSize;
- MEMORY_SPEED_TYPE SupportSpeed;
- UINT16 SupportMemoryType;
- UINT8 MemoryModuleVoltage;
- UINT8 AssociatedMemorySlotNum;
- UINT16 MemoryModuleConfigHandles[1];
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 ErrDetectMethod; ///< The enumeration value from MEMORY_ERROR_DETECT_METHOD.
+ MEMORY_ERROR_CORRECT_CAPABILITY ErrCorrectCapability;
+ UINT8 SupportInterleave; ///< The enumeration value from MEMORY_SUPPORT_INTERLEAVE_TYPE.
+ UINT8 CurrentInterleave; ///< The enumeration value from MEMORY_SUPPORT_INTERLEAVE_TYPE .
+ UINT8 MaxMemoryModuleSize;
+ MEMORY_SPEED_TYPE SupportSpeed;
+ UINT16 SupportMemoryType;
+ UINT8 MemoryModuleVoltage;
+ UINT8 AssociatedMemorySlotNum;
+ UINT16 MemoryModuleConfigHandles[1];
} SMBIOS_TABLE_TYPE5;
///
/// Memory Module Information - Memory Types
///
typedef struct {
- UINT16 Other :1;
- UINT16 Unknown :1;
- UINT16 Standard :1;
- UINT16 FastPageMode:1;
- UINT16 Edo :1;
- UINT16 Parity :1;
- UINT16 Ecc :1;
- UINT16 Simm :1;
- UINT16 Dimm :1;
- UINT16 BurstEdo :1;
- UINT16 Sdram :1;
- UINT16 Reserved :5;
+ UINT16 Other : 1;
+ UINT16 Unknown : 1;
+ UINT16 Standard : 1;
+ UINT16 FastPageMode : 1;
+ UINT16 Edo : 1;
+ UINT16 Parity : 1;
+ UINT16 Ecc : 1;
+ UINT16 Simm : 1;
+ UINT16 Dimm : 1;
+ UINT16 BurstEdo : 1;
+ UINT16 Sdram : 1;
+ UINT16 Reserved : 5;
} MEMORY_CURRENT_TYPE;
///
/// Memory Module Information - Memory Size.
///
typedef struct {
- UINT8 InstalledOrEnabledSize :7; ///< Size (n), where 2**n is the size in MB.
- UINT8 SingleOrDoubleBank :1;
+ UINT8 InstalledOrEnabledSize : 7; ///< Size (n), where 2**n is the size in MB.
+ UINT8 SingleOrDoubleBank : 1;
} MEMORY_INSTALLED_ENABLED_SIZE;
///
@@ -1060,28 +1123,28 @@ typedef struct {
/// and Memory Device (Type 17) structures should be used instead.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- SMBIOS_TABLE_STRING SocketDesignation;
- UINT8 BankConnections;
- UINT8 CurrentSpeed;
- MEMORY_CURRENT_TYPE CurrentMemoryType;
- MEMORY_INSTALLED_ENABLED_SIZE InstalledSize;
- MEMORY_INSTALLED_ENABLED_SIZE EnabledSize;
- UINT8 ErrorStatus;
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING SocketDesignation;
+ UINT8 BankConnections;
+ UINT8 CurrentSpeed;
+ MEMORY_CURRENT_TYPE CurrentMemoryType;
+ MEMORY_INSTALLED_ENABLED_SIZE InstalledSize;
+ MEMORY_INSTALLED_ENABLED_SIZE EnabledSize;
+ UINT8 ErrorStatus;
} SMBIOS_TABLE_TYPE6;
///
/// Cache Information - SRAM Type.
///
typedef struct {
- UINT16 Other :1;
- UINT16 Unknown :1;
- UINT16 NonBurst :1;
- UINT16 Burst :1;
- UINT16 PipelineBurst :1;
- UINT16 Synchronous :1;
- UINT16 Asynchronous :1;
- UINT16 Reserved :9;
+ UINT16 Other : 1;
+ UINT16 Unknown : 1;
+ UINT16 NonBurst : 1;
+ UINT16 Burst : 1;
+ UINT16 PipelineBurst : 1;
+ UINT16 Synchronous : 1;
+ UINT16 Asynchronous : 1;
+ UINT16 Reserved : 9;
} CACHE_SRAM_TYPE_DATA;
///
@@ -1136,115 +1199,115 @@ typedef enum {
/// in one or two ways, depending on the SMBIOS version.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- SMBIOS_TABLE_STRING SocketDesignation;
- UINT16 CacheConfiguration;
- UINT16 MaximumCacheSize;
- UINT16 InstalledSize;
- CACHE_SRAM_TYPE_DATA SupportedSRAMType;
- CACHE_SRAM_TYPE_DATA CurrentSRAMType;
- UINT8 CacheSpeed;
- UINT8 ErrorCorrectionType; ///< The enumeration value from CACHE_ERROR_TYPE_DATA.
- UINT8 SystemCacheType; ///< The enumeration value from CACHE_TYPE_DATA.
- UINT8 Associativity; ///< The enumeration value from CACHE_ASSOCIATIVITY_DATA.
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING SocketDesignation;
+ UINT16 CacheConfiguration;
+ UINT16 MaximumCacheSize;
+ UINT16 InstalledSize;
+ CACHE_SRAM_TYPE_DATA SupportedSRAMType;
+ CACHE_SRAM_TYPE_DATA CurrentSRAMType;
+ UINT8 CacheSpeed;
+ UINT8 ErrorCorrectionType; ///< The enumeration value from CACHE_ERROR_TYPE_DATA.
+ UINT8 SystemCacheType; ///< The enumeration value from CACHE_TYPE_DATA.
+ UINT8 Associativity; ///< The enumeration value from CACHE_ASSOCIATIVITY_DATA.
//
// Add for smbios 3.1.0
//
- UINT32 MaximumCacheSize2;
- UINT32 InstalledSize2;
+ UINT32 MaximumCacheSize2;
+ UINT32 InstalledSize2;
} SMBIOS_TABLE_TYPE7;
///
/// Port Connector Information - Connector Types.
///
typedef enum {
- PortConnectorTypeNone = 0x00,
- PortConnectorTypeCentronics = 0x01,
- PortConnectorTypeMiniCentronics = 0x02,
- PortConnectorTypeProprietary = 0x03,
- PortConnectorTypeDB25Male = 0x04,
- PortConnectorTypeDB25Female = 0x05,
- PortConnectorTypeDB15Male = 0x06,
- PortConnectorTypeDB15Female = 0x07,
- PortConnectorTypeDB9Male = 0x08,
- PortConnectorTypeDB9Female = 0x09,
- PortConnectorTypeRJ11 = 0x0A,
- PortConnectorTypeRJ45 = 0x0B,
- PortConnectorType50PinMiniScsi = 0x0C,
- PortConnectorTypeMiniDin = 0x0D,
- PortConnectorTypeMicroDin = 0x0E,
- PortConnectorTypePS2 = 0x0F,
- PortConnectorTypeInfrared = 0x10,
- PortConnectorTypeHpHil = 0x11,
- PortConnectorTypeUsb = 0x12,
- PortConnectorTypeSsaScsi = 0x13,
- PortConnectorTypeCircularDin8Male = 0x14,
- PortConnectorTypeCircularDin8Female = 0x15,
- PortConnectorTypeOnboardIde = 0x16,
- PortConnectorTypeOnboardFloppy = 0x17,
- PortConnectorType9PinDualInline = 0x18,
- PortConnectorType25PinDualInline = 0x19,
- PortConnectorType50PinDualInline = 0x1A,
- PortConnectorType68PinDualInline = 0x1B,
- PortConnectorTypeOnboardSoundInput = 0x1C,
- PortConnectorTypeMiniCentronicsType14 = 0x1D,
- PortConnectorTypeMiniCentronicsType26 = 0x1E,
- PortConnectorTypeHeadPhoneMiniJack = 0x1F,
- PortConnectorTypeBNC = 0x20,
- PortConnectorType1394 = 0x21,
- PortConnectorTypeSasSata = 0x22,
- PortConnectorTypeUsbTypeC = 0x23,
- PortConnectorTypePC98 = 0xA0,
- PortConnectorTypePC98Hireso = 0xA1,
- PortConnectorTypePCH98 = 0xA2,
- PortConnectorTypePC98Note = 0xA3,
- PortConnectorTypePC98Full = 0xA4,
- PortConnectorTypeOther = 0xFF
+ PortConnectorTypeNone = 0x00,
+ PortConnectorTypeCentronics = 0x01,
+ PortConnectorTypeMiniCentronics = 0x02,
+ PortConnectorTypeProprietary = 0x03,
+ PortConnectorTypeDB25Male = 0x04,
+ PortConnectorTypeDB25Female = 0x05,
+ PortConnectorTypeDB15Male = 0x06,
+ PortConnectorTypeDB15Female = 0x07,
+ PortConnectorTypeDB9Male = 0x08,
+ PortConnectorTypeDB9Female = 0x09,
+ PortConnectorTypeRJ11 = 0x0A,
+ PortConnectorTypeRJ45 = 0x0B,
+ PortConnectorType50PinMiniScsi = 0x0C,
+ PortConnectorTypeMiniDin = 0x0D,
+ PortConnectorTypeMicroDin = 0x0E,
+ PortConnectorTypePS2 = 0x0F,
+ PortConnectorTypeInfrared = 0x10,
+ PortConnectorTypeHpHil = 0x11,
+ PortConnectorTypeUsb = 0x12,
+ PortConnectorTypeSsaScsi = 0x13,
+ PortConnectorTypeCircularDin8Male = 0x14,
+ PortConnectorTypeCircularDin8Female = 0x15,
+ PortConnectorTypeOnboardIde = 0x16,
+ PortConnectorTypeOnboardFloppy = 0x17,
+ PortConnectorType9PinDualInline = 0x18,
+ PortConnectorType25PinDualInline = 0x19,
+ PortConnectorType50PinDualInline = 0x1A,
+ PortConnectorType68PinDualInline = 0x1B,
+ PortConnectorTypeOnboardSoundInput = 0x1C,
+ PortConnectorTypeMiniCentronicsType14 = 0x1D,
+ PortConnectorTypeMiniCentronicsType26 = 0x1E,
+ PortConnectorTypeHeadPhoneMiniJack = 0x1F,
+ PortConnectorTypeBNC = 0x20,
+ PortConnectorType1394 = 0x21,
+ PortConnectorTypeSasSata = 0x22,
+ PortConnectorTypeUsbTypeC = 0x23,
+ PortConnectorTypePC98 = 0xA0,
+ PortConnectorTypePC98Hireso = 0xA1,
+ PortConnectorTypePCH98 = 0xA2,
+ PortConnectorTypePC98Note = 0xA3,
+ PortConnectorTypePC98Full = 0xA4,
+ PortConnectorTypeOther = 0xFF
} MISC_PORT_CONNECTOR_TYPE;
///
/// Port Connector Information - Port Types
///
typedef enum {
- PortTypeNone = 0x00,
- PortTypeParallelXtAtCompatible = 0x01,
- PortTypeParallelPortPs2 = 0x02,
- PortTypeParallelPortEcp = 0x03,
- PortTypeParallelPortEpp = 0x04,
- PortTypeParallelPortEcpEpp = 0x05,
- PortTypeSerialXtAtCompatible = 0x06,
- PortTypeSerial16450Compatible = 0x07,
- PortTypeSerial16550Compatible = 0x08,
- PortTypeSerial16550ACompatible = 0x09,
- PortTypeScsi = 0x0A,
- PortTypeMidi = 0x0B,
- PortTypeJoyStick = 0x0C,
- PortTypeKeyboard = 0x0D,
- PortTypeMouse = 0x0E,
- PortTypeSsaScsi = 0x0F,
- PortTypeUsb = 0x10,
- PortTypeFireWire = 0x11,
- PortTypePcmciaTypeI = 0x12,
- PortTypePcmciaTypeII = 0x13,
- PortTypePcmciaTypeIII = 0x14,
- PortTypeCardBus = 0x15,
- PortTypeAccessBusPort = 0x16,
- PortTypeScsiII = 0x17,
- PortTypeScsiWide = 0x18,
- PortTypePC98 = 0x19,
- PortTypePC98Hireso = 0x1A,
- PortTypePCH98 = 0x1B,
- PortTypeVideoPort = 0x1C,
- PortTypeAudioPort = 0x1D,
- PortTypeModemPort = 0x1E,
- PortTypeNetworkPort = 0x1F,
- PortTypeSata = 0x20,
- PortTypeSas = 0x21,
- PortTypeMfdp = 0x22, ///< Multi-Function Display Port
- PortTypeThunderbolt = 0x23,
- PortType8251Compatible = 0xA0,
- PortType8251FifoCompatible = 0xA1,
- PortTypeOther = 0xFF
+ PortTypeNone = 0x00,
+ PortTypeParallelXtAtCompatible = 0x01,
+ PortTypeParallelPortPs2 = 0x02,
+ PortTypeParallelPortEcp = 0x03,
+ PortTypeParallelPortEpp = 0x04,
+ PortTypeParallelPortEcpEpp = 0x05,
+ PortTypeSerialXtAtCompatible = 0x06,
+ PortTypeSerial16450Compatible = 0x07,
+ PortTypeSerial16550Compatible = 0x08,
+ PortTypeSerial16550ACompatible = 0x09,
+ PortTypeScsi = 0x0A,
+ PortTypeMidi = 0x0B,
+ PortTypeJoyStick = 0x0C,
+ PortTypeKeyboard = 0x0D,
+ PortTypeMouse = 0x0E,
+ PortTypeSsaScsi = 0x0F,
+ PortTypeUsb = 0x10,
+ PortTypeFireWire = 0x11,
+ PortTypePcmciaTypeI = 0x12,
+ PortTypePcmciaTypeII = 0x13,
+ PortTypePcmciaTypeIII = 0x14,
+ PortTypeCardBus = 0x15,
+ PortTypeAccessBusPort = 0x16,
+ PortTypeScsiII = 0x17,
+ PortTypeScsiWide = 0x18,
+ PortTypePC98 = 0x19,
+ PortTypePC98Hireso = 0x1A,
+ PortTypePCH98 = 0x1B,
+ PortTypeVideoPort = 0x1C,
+ PortTypeAudioPort = 0x1D,
+ PortTypeModemPort = 0x1E,
+ PortTypeNetworkPort = 0x1F,
+ PortTypeSata = 0x20,
+ PortTypeSas = 0x21,
+ PortTypeMfdp = 0x22, ///< Multi-Function Display Port
+ PortTypeThunderbolt = 0x23,
+ PortType8251Compatible = 0xA0,
+ PortType8251FifoCompatible = 0xA1,
+ PortTypeOther = 0xFF
} MISC_PORT_TYPE;
///
@@ -1255,114 +1318,161 @@ typedef enum {
/// are provided. One structure is present for each port provided by the system.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- SMBIOS_TABLE_STRING InternalReferenceDesignator;
- UINT8 InternalConnectorType; ///< The enumeration value from MISC_PORT_CONNECTOR_TYPE.
- SMBIOS_TABLE_STRING ExternalReferenceDesignator;
- UINT8 ExternalConnectorType; ///< The enumeration value from MISC_PORT_CONNECTOR_TYPE.
- UINT8 PortType; ///< The enumeration value from MISC_PORT_TYPE.
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING InternalReferenceDesignator;
+ UINT8 InternalConnectorType; ///< The enumeration value from MISC_PORT_CONNECTOR_TYPE.
+ SMBIOS_TABLE_STRING ExternalReferenceDesignator;
+ UINT8 ExternalConnectorType; ///< The enumeration value from MISC_PORT_CONNECTOR_TYPE.
+ UINT8 PortType; ///< The enumeration value from MISC_PORT_TYPE.
} SMBIOS_TABLE_TYPE8;
///
/// System Slots - Slot Type
///
typedef enum {
- SlotTypeOther = 0x01,
- SlotTypeUnknown = 0x02,
- SlotTypeIsa = 0x03,
- SlotTypeMca = 0x04,
- SlotTypeEisa = 0x05,
- SlotTypePci = 0x06,
- SlotTypePcmcia = 0x07,
- SlotTypeVlVesa = 0x08,
- SlotTypeProprietary = 0x09,
- SlotTypeProcessorCardSlot = 0x0A,
- SlotTypeProprietaryMemoryCardSlot = 0x0B,
- SlotTypeIORiserCardSlot = 0x0C,
- SlotTypeNuBus = 0x0D,
- SlotTypePci66MhzCapable = 0x0E,
- SlotTypeAgp = 0x0F,
- SlotTypeApg2X = 0x10,
- SlotTypeAgp4X = 0x11,
- SlotTypePciX = 0x12,
- SlotTypeAgp8X = 0x13,
- SlotTypeM2Socket1_DP = 0x14,
- SlotTypeM2Socket1_SD = 0x15,
- SlotTypeM2Socket2 = 0x16,
- SlotTypeM2Socket3 = 0x17,
- SlotTypeMxmTypeI = 0x18,
- SlotTypeMxmTypeII = 0x19,
- SlotTypeMxmTypeIIIStandard = 0x1A,
- SlotTypeMxmTypeIIIHe = 0x1B,
- SlotTypeMxmTypeIV = 0x1C,
- SlotTypeMxm30TypeA = 0x1D,
- SlotTypeMxm30TypeB = 0x1E,
- SlotTypePciExpressGen2Sff_8639 = 0x1F,
- SlotTypePciExpressGen3Sff_8639 = 0x20,
- SlotTypePciExpressMini52pinWithBSKO = 0x21, ///< PCI Express Mini 52-pin (CEM spec. 2.0) with bottom-side keep-outs.
- SlotTypePciExpressMini52pinWithoutBSKO = 0x22, ///< PCI Express Mini 52-pin (CEM spec. 2.0) without bottom-side keep-outs.
- SlotTypePciExpressMini76pin = 0x23, ///< PCI Express Mini 76-pin (CEM spec. 2.0) Corresponds to Display-Mini card.
- SlotTypeCXLFlexbus10 = 0x30,
- SlotTypePC98C20 = 0xA0,
- SlotTypePC98C24 = 0xA1,
- SlotTypePC98E = 0xA2,
- SlotTypePC98LocalBus = 0xA3,
- SlotTypePC98Card = 0xA4,
- SlotTypePciExpress = 0xA5,
- SlotTypePciExpressX1 = 0xA6,
- SlotTypePciExpressX2 = 0xA7,
- SlotTypePciExpressX4 = 0xA8,
- SlotTypePciExpressX8 = 0xA9,
- SlotTypePciExpressX16 = 0xAA,
- SlotTypePciExpressGen2 = 0xAB,
- SlotTypePciExpressGen2X1 = 0xAC,
- SlotTypePciExpressGen2X2 = 0xAD,
- SlotTypePciExpressGen2X4 = 0xAE,
- SlotTypePciExpressGen2X8 = 0xAF,
- SlotTypePciExpressGen2X16 = 0xB0,
- SlotTypePciExpressGen3 = 0xB1,
- SlotTypePciExpressGen3X1 = 0xB2,
- SlotTypePciExpressGen3X2 = 0xB3,
- SlotTypePciExpressGen3X4 = 0xB4,
- SlotTypePciExpressGen3X8 = 0xB5,
- SlotTypePciExpressGen3X16 = 0xB6,
- SlotTypePciExpressGen4 = 0xB8,
- SlotTypePciExpressGen4X1 = 0xB9,
- SlotTypePciExpressGen4X2 = 0xBA,
- SlotTypePciExpressGen4X4 = 0xBB,
- SlotTypePciExpressGen4X8 = 0xBC,
- SlotTypePciExpressGen4X16 = 0xBD
+ SlotTypeOther = 0x01,
+ SlotTypeUnknown = 0x02,
+ SlotTypeIsa = 0x03,
+ SlotTypeMca = 0x04,
+ SlotTypeEisa = 0x05,
+ SlotTypePci = 0x06,
+ SlotTypePcmcia = 0x07,
+ SlotTypeVlVesa = 0x08,
+ SlotTypeProprietary = 0x09,
+ SlotTypeProcessorCardSlot = 0x0A,
+ SlotTypeProprietaryMemoryCardSlot = 0x0B,
+ SlotTypeIORiserCardSlot = 0x0C,
+ SlotTypeNuBus = 0x0D,
+ SlotTypePci66MhzCapable = 0x0E,
+ SlotTypeAgp = 0x0F,
+ SlotTypeApg2X = 0x10,
+ SlotTypeAgp4X = 0x11,
+ SlotTypePciX = 0x12,
+ SlotTypeAgp8X = 0x13,
+ SlotTypeM2Socket1_DP = 0x14,
+ SlotTypeM2Socket1_SD = 0x15,
+ SlotTypeM2Socket2 = 0x16,
+ SlotTypeM2Socket3 = 0x17,
+ SlotTypeMxmTypeI = 0x18,
+ SlotTypeMxmTypeII = 0x19,
+ SlotTypeMxmTypeIIIStandard = 0x1A,
+ SlotTypeMxmTypeIIIHe = 0x1B,
+ SlotTypeMxmTypeIV = 0x1C,
+ SlotTypeMxm30TypeA = 0x1D,
+ SlotTypeMxm30TypeB = 0x1E,
+ SlotTypePciExpressGen2Sff_8639 = 0x1F,
+ SlotTypePciExpressGen3Sff_8639 = 0x20,
+ SlotTypePciExpressMini52pinWithBSKO = 0x21, ///< PCI Express Mini 52-pin (CEM spec. 2.0) with bottom-side keep-outs.
+ SlotTypePciExpressMini52pinWithoutBSKO = 0x22, ///< PCI Express Mini 52-pin (CEM spec. 2.0) without bottom-side keep-outs.
+ SlotTypePciExpressMini76pin = 0x23, ///< PCI Express Mini 76-pin (CEM spec. 2.0) Corresponds to Display-Mini card.
+ SlotTypePCIExpressGen4SFF_8639 = 0x24, ///< U.2
+ SlotTypePCIExpressGen5SFF_8639 = 0x25, ///< U.2
+ SlotTypeOCPNIC30SmallFormFactor = 0x26, ///< SFF
+ SlotTypeOCPNIC30LargeFormFactor = 0x27, ///< LFF
+ SlotTypeOCPNICPriorto30 = 0x28,
+ SlotTypeCXLFlexbus10 = 0x30,
+ SlotTypePC98C20 = 0xA0,
+ SlotTypePC98C24 = 0xA1,
+ SlotTypePC98E = 0xA2,
+ SlotTypePC98LocalBus = 0xA3,
+ SlotTypePC98Card = 0xA4,
+ SlotTypePciExpress = 0xA5,
+ SlotTypePciExpressX1 = 0xA6,
+ SlotTypePciExpressX2 = 0xA7,
+ SlotTypePciExpressX4 = 0xA8,
+ SlotTypePciExpressX8 = 0xA9,
+ SlotTypePciExpressX16 = 0xAA,
+ SlotTypePciExpressGen2 = 0xAB,
+ SlotTypePciExpressGen2X1 = 0xAC,
+ SlotTypePciExpressGen2X2 = 0xAD,
+ SlotTypePciExpressGen2X4 = 0xAE,
+ SlotTypePciExpressGen2X8 = 0xAF,
+ SlotTypePciExpressGen2X16 = 0xB0,
+ SlotTypePciExpressGen3 = 0xB1,
+ SlotTypePciExpressGen3X1 = 0xB2,
+ SlotTypePciExpressGen3X2 = 0xB3,
+ SlotTypePciExpressGen3X4 = 0xB4,
+ SlotTypePciExpressGen3X8 = 0xB5,
+ SlotTypePciExpressGen3X16 = 0xB6,
+ SlotTypePciExpressGen4 = 0xB8,
+ SlotTypePciExpressGen4X1 = 0xB9,
+ SlotTypePciExpressGen4X2 = 0xBA,
+ SlotTypePciExpressGen4X4 = 0xBB,
+ SlotTypePciExpressGen4X8 = 0xBC,
+ SlotTypePciExpressGen4X16 = 0xBD,
+ SlotTypePCIExpressGen5 = 0xBE,
+ SlotTypePCIExpressGen5X1 = 0xBF,
+ SlotTypePCIExpressGen5X2 = 0xC0,
+ SlotTypePCIExpressGen5X4 = 0xC1,
+ SlotTypePCIExpressGen5X8 = 0xC2,
+ SlotTypePCIExpressGen5X16 = 0xC3,
+ SlotTypePCIExpressGen6andBeyond = 0xC4,
+ SlotTypeEnterpriseandDatacenter1UE1FormFactorSlot = 0xC5,
+ SlotTypeEnterpriseandDatacenter3E3FormFactorSlot = 0xC6
} MISC_SLOT_TYPE;
///
/// System Slots - Slot Data Bus Width.
///
typedef enum {
- SlotDataBusWidthOther = 0x01,
- SlotDataBusWidthUnknown = 0x02,
- SlotDataBusWidth8Bit = 0x03,
- SlotDataBusWidth16Bit = 0x04,
- SlotDataBusWidth32Bit = 0x05,
- SlotDataBusWidth64Bit = 0x06,
- SlotDataBusWidth128Bit = 0x07,
- SlotDataBusWidth1X = 0x08, ///< Or X1
- SlotDataBusWidth2X = 0x09, ///< Or X2
- SlotDataBusWidth4X = 0x0A, ///< Or X4
- SlotDataBusWidth8X = 0x0B, ///< Or X8
- SlotDataBusWidth12X = 0x0C, ///< Or X12
- SlotDataBusWidth16X = 0x0D, ///< Or X16
- SlotDataBusWidth32X = 0x0E ///< Or X32
+ SlotDataBusWidthOther = 0x01,
+ SlotDataBusWidthUnknown = 0x02,
+ SlotDataBusWidth8Bit = 0x03,
+ SlotDataBusWidth16Bit = 0x04,
+ SlotDataBusWidth32Bit = 0x05,
+ SlotDataBusWidth64Bit = 0x06,
+ SlotDataBusWidth128Bit = 0x07,
+ SlotDataBusWidth1X = 0x08, ///< Or X1
+ SlotDataBusWidth2X = 0x09, ///< Or X2
+ SlotDataBusWidth4X = 0x0A, ///< Or X4
+ SlotDataBusWidth8X = 0x0B, ///< Or X8
+ SlotDataBusWidth12X = 0x0C, ///< Or X12
+ SlotDataBusWidth16X = 0x0D, ///< Or X16
+ SlotDataBusWidth32X = 0x0E ///< Or X32
} MISC_SLOT_DATA_BUS_WIDTH;
+///
+/// System Slots - Slot Physical Width.
+///
+typedef enum {
+ SlotPhysicalWidthOther = 0x01,
+ SlotPhysicalWidthUnknown = 0x02,
+ SlotPhysicalWidth8Bit = 0x03,
+ SlotPhysicalWidth16Bit = 0x04,
+ SlotPhysicalWidth32Bit = 0x05,
+ SlotPhysicalWidth64Bit = 0x06,
+ SlotPhysicalWidth128Bit = 0x07,
+ SlotPhysicalWidth1X = 0x08, ///< Or X1
+ SlotPhysicalWidth2X = 0x09, ///< Or X2
+ SlotPhysicalWidth4X = 0x0A, ///< Or X4
+ SlotPhysicalWidth8X = 0x0B, ///< Or X8
+ SlotPhysicalWidth12X = 0x0C, ///< Or X12
+ SlotPhysicalWidth16X = 0x0D, ///< Or X16
+ SlotPhysicalWidth32X = 0x0E ///< Or X32
+} MISC_SLOT_PHYSICAL_WIDTH;
+
+///
+/// System Slots - Slot Information.
+///
+typedef enum {
+ Others = 0x00,
+ Gen1 = 0x01,
+ Gen2 = 0x01,
+ Gen3 = 0x03,
+ Gen4 = 0x04,
+ Gen5 = 0x05,
+ Gen6 = 0x06
+} MISC_SLOT_INFORMATION;
+
///
/// System Slots - Current Usage.
///
typedef enum {
- SlotUsageOther = 0x01,
- SlotUsageUnknown = 0x02,
- SlotUsageAvailable = 0x03,
- SlotUsageInUse = 0x04,
- SlotUsageUnavailable = 0x05
+ SlotUsageOther = 0x01,
+ SlotUsageUnknown = 0x02,
+ SlotUsageAvailable = 0x03,
+ SlotUsageInUse = 0x04,
+ SlotUsageUnavailable = 0x05
} MISC_SLOT_USAGE;
///
@@ -1379,37 +1489,48 @@ typedef enum {
/// System Slots - Slot Characteristics 1.
///
typedef struct {
- UINT8 CharacteristicsUnknown :1;
- UINT8 Provides50Volts :1;
- UINT8 Provides33Volts :1;
- UINT8 SharedSlot :1;
- UINT8 PcCard16Supported :1;
- UINT8 CardBusSupported :1;
- UINT8 ZoomVideoSupported :1;
- UINT8 ModemRingResumeSupported:1;
+ UINT8 CharacteristicsUnknown : 1;
+ UINT8 Provides50Volts : 1;
+ UINT8 Provides33Volts : 1;
+ UINT8 SharedSlot : 1;
+ UINT8 PcCard16Supported : 1;
+ UINT8 CardBusSupported : 1;
+ UINT8 ZoomVideoSupported : 1;
+ UINT8 ModemRingResumeSupported : 1;
} MISC_SLOT_CHARACTERISTICS1;
///
/// System Slots - Slot Characteristics 2.
///
typedef struct {
- UINT8 PmeSignalSupported :1;
- UINT8 HotPlugDevicesSupported :1;
- UINT8 SmbusSignalSupported :1;
- UINT8 BifurcationSupported :1;
- UINT8 AsyncSurpriseRemoval :1;
- UINT8 FlexbusSlotCxl10Capable :1;
- UINT8 FlexbusSlotCxl20Capable :1;
- UINT8 Reserved :1; ///< Set to 0.
+ UINT8 PmeSignalSupported : 1;
+ UINT8 HotPlugDevicesSupported : 1;
+ UINT8 SmbusSignalSupported : 1;
+ UINT8 BifurcationSupported : 1;
+ UINT8 AsyncSurpriseRemoval : 1;
+ UINT8 FlexbusSlotCxl10Capable : 1;
+ UINT8 FlexbusSlotCxl20Capable : 1;
+ UINT8 Reserved : 1; ///< Set to 0.
} MISC_SLOT_CHARACTERISTICS2;
+///
+/// System Slots - Slot Height
+///
+typedef enum {
+ SlotHeightNone = 0x00,
+ SlotHeightOther = 0x01,
+ SlotHeightUnknown = 0x02,
+ SlotHeightFullHeight = 0x03,
+ SlotHeightLowProfile = 0x04
+} MISC_SLOT_HEIGHT;
+
///
/// System Slots - Peer Segment/Bus/Device/Function/Width Groups
///
typedef struct {
- UINT16 SegmentGroupNum;
- UINT8 BusNum;
- UINT8 DevFuncNum;
- UINT8 DataBusWidth;
+ UINT16 SegmentGroupNum;
+ UINT8 BusNum;
+ UINT8 DevFuncNum;
+ UINT8 DataBusWidth;
} MISC_SLOT_PEER_GROUP;
///
@@ -1420,34 +1541,49 @@ typedef struct {
///
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- SMBIOS_TABLE_STRING SlotDesignation;
- UINT8 SlotType; ///< The enumeration value from MISC_SLOT_TYPE.
- UINT8 SlotDataBusWidth; ///< The enumeration value from MISC_SLOT_DATA_BUS_WIDTH.
- UINT8 CurrentUsage; ///< The enumeration value from MISC_SLOT_USAGE.
- UINT8 SlotLength; ///< The enumeration value from MISC_SLOT_LENGTH.
- UINT16 SlotID;
- MISC_SLOT_CHARACTERISTICS1 SlotCharacteristics1;
- MISC_SLOT_CHARACTERISTICS2 SlotCharacteristics2;
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING SlotDesignation;
+ UINT8 SlotType; ///< The enumeration value from MISC_SLOT_TYPE.
+ UINT8 SlotDataBusWidth; ///< The enumeration value from MISC_SLOT_DATA_BUS_WIDTH.
+ UINT8 CurrentUsage; ///< The enumeration value from MISC_SLOT_USAGE.
+ UINT8 SlotLength; ///< The enumeration value from MISC_SLOT_LENGTH.
+ UINT16 SlotID;
+ MISC_SLOT_CHARACTERISTICS1 SlotCharacteristics1;
+ MISC_SLOT_CHARACTERISTICS2 SlotCharacteristics2;
//
// Add for smbios 2.6
//
- UINT16 SegmentGroupNum;
- UINT8 BusNum;
- UINT8 DevFuncNum;
+ UINT16 SegmentGroupNum;
+ UINT8 BusNum;
+ UINT8 DevFuncNum;
//
// Add for smbios 3.2
//
- UINT8 DataBusWidth;
- UINT8 PeerGroupingCount;
- MISC_SLOT_PEER_GROUP PeerGroups[1];
+ UINT8 DataBusWidth;
+ UINT8 PeerGroupingCount;
+ MISC_SLOT_PEER_GROUP PeerGroups[1];
+ //
+ // Since PeerGroups has a variable number of entries, must not define new
+ // fields in the structure. Remaining fields can be referenced using
+ // SMBIOS_TABLE_TYPE9_EXTENDED structure
+ //
+} SMBIOS_TABLE_TYPE9;
+
+///
+/// Extended structure for System Slots (Type 9)
+///
+typedef struct {
//
// Add for smbios 3.4
//
- UINT8 SlotInformation;
- UINT8 SlotPhysicalWidth;
- UINT16 SlotPitch;
-} SMBIOS_TABLE_TYPE9;
+ UINT8 SlotInformation;
+ UINT8 SlotPhysicalWidth;
+ UINT16 SlotPitch;
+ //
+ // Add for smbios 3.5
+ //
+ UINT8 SlotHeight; ///< The enumeration value from MISC_SLOT_HEIGHT.
+} SMBIOS_TABLE_TYPE9_EXTENDED;
///
/// On Board Devices Information - Device Types.
@@ -1469,9 +1605,9 @@ typedef enum {
/// Device Item Entry
///
typedef struct {
- UINT8 DeviceType; ///< Bit [6:0] - enumeration type of device from MISC_ONBOARD_DEVICE_TYPE.
+ UINT8 DeviceType; ///< Bit [6:0] - enumeration type of device from MISC_ONBOARD_DEVICE_TYPE.
///< Bit 7 - 1 : device enabled, 0 : device disabled.
- SMBIOS_TABLE_STRING DescriptionString;
+ SMBIOS_TABLE_STRING DescriptionString;
} DEVICE_STRUCT;
///
@@ -1485,8 +1621,8 @@ typedef struct {
/// has some level of control over the enabling of the associated device for use by the system.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- DEVICE_STRUCT Device[1];
+ SMBIOS_STRUCTURE Hdr;
+ DEVICE_STRUCT Device[1];
} SMBIOS_TABLE_TYPE10;
///
@@ -1495,8 +1631,8 @@ typedef struct {
/// Part Numbers for Reference Documents for the system, contact information for the manufacturer, etc.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT8 StringCount;
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 StringCount;
} SMBIOS_TABLE_TYPE11;
///
@@ -1505,30 +1641,29 @@ typedef struct {
/// This structure contains information required to configure the base board's Jumpers and Switches.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT8 StringCount;
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 StringCount;
} SMBIOS_TABLE_TYPE12;
-
///
/// BIOS Language Information (Type 13).
///
/// The information in this structure defines the installable language attributes of the BIOS.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT8 InstallableLanguages;
- UINT8 Flags;
- UINT8 Reserved[15];
- SMBIOS_TABLE_STRING CurrentLanguages;
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 InstallableLanguages;
+ UINT8 Flags;
+ UINT8 Reserved[15];
+ SMBIOS_TABLE_STRING CurrentLanguages;
} SMBIOS_TABLE_TYPE13;
///
/// Group Item Entry
///
typedef struct {
- UINT8 ItemType;
- UINT16 ItemHandle;
+ UINT8 ItemType;
+ UINT16 ItemHandle;
} GROUP_STRUCT;
///
@@ -1539,64 +1674,64 @@ typedef struct {
/// within the system.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- SMBIOS_TABLE_STRING GroupName;
- GROUP_STRUCT Group[1];
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING GroupName;
+ GROUP_STRUCT Group[1];
} SMBIOS_TABLE_TYPE14;
///
/// System Event Log - Event Log Types.
///
typedef enum {
- EventLogTypeReserved = 0x00,
- EventLogTypeSingleBitECC = 0x01,
- EventLogTypeMultiBitECC = 0x02,
- EventLogTypeParityMemErr = 0x03,
- EventLogTypeBusTimeOut = 0x04,
- EventLogTypeIOChannelCheck = 0x05,
- EventLogTypeSoftwareNMI = 0x06,
- EventLogTypePOSTMemResize = 0x07,
- EventLogTypePOSTErr = 0x08,
- EventLogTypePCIParityErr = 0x09,
- EventLogTypePCISystemErr = 0x0A,
- EventLogTypeCPUFailure = 0x0B,
- EventLogTypeEISATimeOut = 0x0C,
- EventLogTypeMemLogDisabled = 0x0D,
- EventLogTypeLoggingDisabled = 0x0E,
- EventLogTypeSysLimitExce = 0x10,
- EventLogTypeAsyncHWTimer = 0x11,
- EventLogTypeSysConfigInfo = 0x12,
- EventLogTypeHDInfo = 0x13,
- EventLogTypeSysReconfig = 0x14,
- EventLogTypeUncorrectCPUErr = 0x15,
- EventLogTypeAreaResetAndClr = 0x16,
- EventLogTypeSystemBoot = 0x17,
- EventLogTypeUnused = 0x18, ///< 0x18 - 0x7F
- EventLogTypeAvailForSys = 0x80, ///< 0x80 - 0xFE
- EventLogTypeEndOfLog = 0xFF
+ EventLogTypeReserved = 0x00,
+ EventLogTypeSingleBitECC = 0x01,
+ EventLogTypeMultiBitECC = 0x02,
+ EventLogTypeParityMemErr = 0x03,
+ EventLogTypeBusTimeOut = 0x04,
+ EventLogTypeIOChannelCheck = 0x05,
+ EventLogTypeSoftwareNMI = 0x06,
+ EventLogTypePOSTMemResize = 0x07,
+ EventLogTypePOSTErr = 0x08,
+ EventLogTypePCIParityErr = 0x09,
+ EventLogTypePCISystemErr = 0x0A,
+ EventLogTypeCPUFailure = 0x0B,
+ EventLogTypeEISATimeOut = 0x0C,
+ EventLogTypeMemLogDisabled = 0x0D,
+ EventLogTypeLoggingDisabled = 0x0E,
+ EventLogTypeSysLimitExce = 0x10,
+ EventLogTypeAsyncHWTimer = 0x11,
+ EventLogTypeSysConfigInfo = 0x12,
+ EventLogTypeHDInfo = 0x13,
+ EventLogTypeSysReconfig = 0x14,
+ EventLogTypeUncorrectCPUErr = 0x15,
+ EventLogTypeAreaResetAndClr = 0x16,
+ EventLogTypeSystemBoot = 0x17,
+ EventLogTypeUnused = 0x18, ///< 0x18 - 0x7F
+ EventLogTypeAvailForSys = 0x80, ///< 0x80 - 0xFE
+ EventLogTypeEndOfLog = 0xFF
} EVENT_LOG_TYPE_DATA;
///
/// System Event Log - Variable Data Format Types.
///
typedef enum {
- EventLogVariableNone = 0x00,
- EventLogVariableHandle = 0x01,
- EventLogVariableMutilEvent = 0x02,
- EventLogVariableMutilEventHandle = 0x03,
- EventLogVariablePOSTResultBitmap = 0x04,
- EventLogVariableSysManagementType = 0x05,
- EventLogVariableMutliEventSysManagmentType = 0x06,
- EventLogVariableUnused = 0x07,
- EventLogVariableOEMAssigned = 0x80
+ EventLogVariableNone = 0x00,
+ EventLogVariableHandle = 0x01,
+ EventLogVariableMutilEvent = 0x02,
+ EventLogVariableMutilEventHandle = 0x03,
+ EventLogVariablePOSTResultBitmap = 0x04,
+ EventLogVariableSysManagementType = 0x05,
+ EventLogVariableMutliEventSysManagmentType = 0x06,
+ EventLogVariableUnused = 0x07,
+ EventLogVariableOEMAssigned = 0x80
} EVENT_LOG_VARIABLE_DATA;
///
/// Event Log Type Descriptors
///
typedef struct {
- UINT8 LogType; ///< The enumeration value from EVENT_LOG_TYPE_DATA.
- UINT8 DataFormatType;
+ UINT8 LogType; ///< The enumeration value from EVENT_LOG_TYPE_DATA.
+ UINT8 DataFormatType;
} EVENT_LOG_TYPE;
///
@@ -1608,18 +1743,18 @@ typedef struct {
/// record, followed by one or more variable-length log records.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT16 LogAreaLength;
- UINT16 LogHeaderStartOffset;
- UINT16 LogDataStartOffset;
- UINT8 AccessMethod;
- UINT8 LogStatus;
- UINT32 LogChangeToken;
- UINT32 AccessMethodAddress;
- UINT8 LogHeaderFormat;
- UINT8 NumberOfSupportedLogTypeDescriptors;
- UINT8 LengthOfLogTypeDescriptor;
- EVENT_LOG_TYPE EventLogTypeDescriptors[1];
+ SMBIOS_STRUCTURE Hdr;
+ UINT16 LogAreaLength;
+ UINT16 LogHeaderStartOffset;
+ UINT16 LogDataStartOffset;
+ UINT8 AccessMethod;
+ UINT8 LogStatus;
+ UINT32 LogChangeToken;
+ UINT32 AccessMethodAddress;
+ UINT8 LogHeaderFormat;
+ UINT8 NumberOfSupportedLogTypeDescriptors;
+ UINT8 LengthOfLogTypeDescriptor;
+ EVENT_LOG_TYPE EventLogTypeDescriptors[1];
} SMBIOS_TABLE_TYPE15;
///
@@ -1647,26 +1782,26 @@ typedef enum {
/// Physical Memory Array - Use.
///
typedef enum {
- MemoryArrayUseOther = 0x01,
- MemoryArrayUseUnknown = 0x02,
- MemoryArrayUseSystemMemory = 0x03,
- MemoryArrayUseVideoMemory = 0x04,
- MemoryArrayUseFlashMemory = 0x05,
- MemoryArrayUseNonVolatileRam = 0x06,
- MemoryArrayUseCacheMemory = 0x07
+ MemoryArrayUseOther = 0x01,
+ MemoryArrayUseUnknown = 0x02,
+ MemoryArrayUseSystemMemory = 0x03,
+ MemoryArrayUseVideoMemory = 0x04,
+ MemoryArrayUseFlashMemory = 0x05,
+ MemoryArrayUseNonVolatileRam = 0x06,
+ MemoryArrayUseCacheMemory = 0x07
} MEMORY_ARRAY_USE;
///
/// Physical Memory Array - Error Correction Types.
///
typedef enum {
- MemoryErrorCorrectionOther = 0x01,
- MemoryErrorCorrectionUnknown = 0x02,
- MemoryErrorCorrectionNone = 0x03,
- MemoryErrorCorrectionParity = 0x04,
- MemoryErrorCorrectionSingleBitEcc = 0x05,
- MemoryErrorCorrectionMultiBitEcc = 0x06,
- MemoryErrorCorrectionCrc = 0x07
+ MemoryErrorCorrectionOther = 0x01,
+ MemoryErrorCorrectionUnknown = 0x02,
+ MemoryErrorCorrectionNone = 0x03,
+ MemoryErrorCorrectionParity = 0x04,
+ MemoryErrorCorrectionSingleBitEcc = 0x05,
+ MemoryErrorCorrectionMultiBitEcc = 0x06,
+ MemoryErrorCorrectionCrc = 0x07
} MEMORY_ERROR_CORRECTION;
///
@@ -1676,117 +1811,117 @@ typedef enum {
/// together to form a memory address space.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT8 Location; ///< The enumeration value from MEMORY_ARRAY_LOCATION.
- UINT8 Use; ///< The enumeration value from MEMORY_ARRAY_USE.
- UINT8 MemoryErrorCorrection; ///< The enumeration value from MEMORY_ERROR_CORRECTION.
- UINT32 MaximumCapacity;
- UINT16 MemoryErrorInformationHandle;
- UINT16 NumberOfMemoryDevices;
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 Location; ///< The enumeration value from MEMORY_ARRAY_LOCATION.
+ UINT8 Use; ///< The enumeration value from MEMORY_ARRAY_USE.
+ UINT8 MemoryErrorCorrection; ///< The enumeration value from MEMORY_ERROR_CORRECTION.
+ UINT32 MaximumCapacity;
+ UINT16 MemoryErrorInformationHandle;
+ UINT16 NumberOfMemoryDevices;
//
// Add for smbios 2.7
//
- UINT64 ExtendedMaximumCapacity;
+ UINT64 ExtendedMaximumCapacity;
} SMBIOS_TABLE_TYPE16;
///
/// Memory Device - Form Factor.
///
typedef enum {
- MemoryFormFactorOther = 0x01,
- MemoryFormFactorUnknown = 0x02,
- MemoryFormFactorSimm = 0x03,
- MemoryFormFactorSip = 0x04,
- MemoryFormFactorChip = 0x05,
- MemoryFormFactorDip = 0x06,
- MemoryFormFactorZip = 0x07,
- MemoryFormFactorProprietaryCard = 0x08,
- MemoryFormFactorDimm = 0x09,
- MemoryFormFactorTsop = 0x0A,
- MemoryFormFactorRowOfChips = 0x0B,
- MemoryFormFactorRimm = 0x0C,
- MemoryFormFactorSodimm = 0x0D,
- MemoryFormFactorSrimm = 0x0E,
- MemoryFormFactorFbDimm = 0x0F,
- MemoryFormFactorDie = 0x10
+ MemoryFormFactorOther = 0x01,
+ MemoryFormFactorUnknown = 0x02,
+ MemoryFormFactorSimm = 0x03,
+ MemoryFormFactorSip = 0x04,
+ MemoryFormFactorChip = 0x05,
+ MemoryFormFactorDip = 0x06,
+ MemoryFormFactorZip = 0x07,
+ MemoryFormFactorProprietaryCard = 0x08,
+ MemoryFormFactorDimm = 0x09,
+ MemoryFormFactorTsop = 0x0A,
+ MemoryFormFactorRowOfChips = 0x0B,
+ MemoryFormFactorRimm = 0x0C,
+ MemoryFormFactorSodimm = 0x0D,
+ MemoryFormFactorSrimm = 0x0E,
+ MemoryFormFactorFbDimm = 0x0F,
+ MemoryFormFactorDie = 0x10
} MEMORY_FORM_FACTOR;
///
/// Memory Device - Type
///
typedef enum {
- MemoryTypeOther = 0x01,
- MemoryTypeUnknown = 0x02,
- MemoryTypeDram = 0x03,
- MemoryTypeEdram = 0x04,
- MemoryTypeVram = 0x05,
- MemoryTypeSram = 0x06,
- MemoryTypeRam = 0x07,
- MemoryTypeRom = 0x08,
- MemoryTypeFlash = 0x09,
- MemoryTypeEeprom = 0x0A,
- MemoryTypeFeprom = 0x0B,
- MemoryTypeEprom = 0x0C,
- MemoryTypeCdram = 0x0D,
- MemoryType3Dram = 0x0E,
- MemoryTypeSdram = 0x0F,
- MemoryTypeSgram = 0x10,
- MemoryTypeRdram = 0x11,
- MemoryTypeDdr = 0x12,
- MemoryTypeDdr2 = 0x13,
- MemoryTypeDdr2FbDimm = 0x14,
- MemoryTypeDdr3 = 0x18,
- MemoryTypeFbd2 = 0x19,
- MemoryTypeDdr4 = 0x1A,
- MemoryTypeLpddr = 0x1B,
- MemoryTypeLpddr2 = 0x1C,
- MemoryTypeLpddr3 = 0x1D,
- MemoryTypeLpddr4 = 0x1E,
- MemoryTypeLogicalNonVolatileDevice = 0x1F,
- MemoryTypeHBM = 0x20,
- MemoryTypeHBM2 = 0x21,
- MemoryTypeDdr5 = 0x22,
- MemoryTypeLpddr5 = 0x23
+ MemoryTypeOther = 0x01,
+ MemoryTypeUnknown = 0x02,
+ MemoryTypeDram = 0x03,
+ MemoryTypeEdram = 0x04,
+ MemoryTypeVram = 0x05,
+ MemoryTypeSram = 0x06,
+ MemoryTypeRam = 0x07,
+ MemoryTypeRom = 0x08,
+ MemoryTypeFlash = 0x09,
+ MemoryTypeEeprom = 0x0A,
+ MemoryTypeFeprom = 0x0B,
+ MemoryTypeEprom = 0x0C,
+ MemoryTypeCdram = 0x0D,
+ MemoryType3Dram = 0x0E,
+ MemoryTypeSdram = 0x0F,
+ MemoryTypeSgram = 0x10,
+ MemoryTypeRdram = 0x11,
+ MemoryTypeDdr = 0x12,
+ MemoryTypeDdr2 = 0x13,
+ MemoryTypeDdr2FbDimm = 0x14,
+ MemoryTypeDdr3 = 0x18,
+ MemoryTypeFbd2 = 0x19,
+ MemoryTypeDdr4 = 0x1A,
+ MemoryTypeLpddr = 0x1B,
+ MemoryTypeLpddr2 = 0x1C,
+ MemoryTypeLpddr3 = 0x1D,
+ MemoryTypeLpddr4 = 0x1E,
+ MemoryTypeLogicalNonVolatileDevice = 0x1F,
+ MemoryTypeHBM = 0x20,
+ MemoryTypeHBM2 = 0x21,
+ MemoryTypeDdr5 = 0x22,
+ MemoryTypeLpddr5 = 0x23,
+ MemoryTypeHBM3 = 0x24
} MEMORY_DEVICE_TYPE;
///
/// Memory Device - Type Detail
///
typedef struct {
- UINT16 Reserved :1;
- UINT16 Other :1;
- UINT16 Unknown :1;
- UINT16 FastPaged :1;
- UINT16 StaticColumn :1;
- UINT16 PseudoStatic :1;
- UINT16 Rambus :1;
- UINT16 Synchronous :1;
- UINT16 Cmos :1;
- UINT16 Edo :1;
- UINT16 WindowDram :1;
- UINT16 CacheDram :1;
- UINT16 Nonvolatile :1;
- UINT16 Registered :1;
- UINT16 Unbuffered :1;
- UINT16 LrDimm :1;
+ UINT16 Reserved : 1;
+ UINT16 Other : 1;
+ UINT16 Unknown : 1;
+ UINT16 FastPaged : 1;
+ UINT16 StaticColumn : 1;
+ UINT16 PseudoStatic : 1;
+ UINT16 Rambus : 1;
+ UINT16 Synchronous : 1;
+ UINT16 Cmos : 1;
+ UINT16 Edo : 1;
+ UINT16 WindowDram : 1;
+ UINT16 CacheDram : 1;
+ UINT16 Nonvolatile : 1;
+ UINT16 Registered : 1;
+ UINT16 Unbuffered : 1;
+ UINT16 LrDimm : 1;
} MEMORY_DEVICE_TYPE_DETAIL;
///
/// Memory Device - Memory Technology
///
typedef enum {
- MemoryTechnologyOther = 0x01,
- MemoryTechnologyUnknown = 0x02,
- MemoryTechnologyDram = 0x03,
- MemoryTechnologyNvdimmN = 0x04,
- MemoryTechnologyNvdimmF = 0x05,
- MemoryTechnologyNvdimmP = 0x06,
+ MemoryTechnologyOther = 0x01,
+ MemoryTechnologyUnknown = 0x02,
+ MemoryTechnologyDram = 0x03,
+ MemoryTechnologyNvdimmN = 0x04,
+ MemoryTechnologyNvdimmF = 0x05,
+ MemoryTechnologyNvdimmP = 0x06,
//
// This definition is updated to represent Intel
// Optane DC Persistent Memory in SMBIOS spec 3.4.0
//
- MemoryTechnologyIntelOptanePersistentMemory = 0x07
-
+ MemoryTechnologyIntelOptanePersistentMemory = 0x07
} MEMORY_DEVICE_TECHNOLOGY;
///
@@ -1797,18 +1932,18 @@ typedef union {
/// Individual bit fields
///
struct {
- UINT16 Reserved :1; ///< Set to 0.
- UINT16 Other :1;
- UINT16 Unknown :1;
- UINT16 VolatileMemory :1;
- UINT16 ByteAccessiblePersistentMemory :1;
- UINT16 BlockAccessiblePersistentMemory :1;
- UINT16 Reserved2 :10; ///< Set to 0.
+ UINT16 Reserved : 1; ///< Set to 0.
+ UINT16 Other : 1;
+ UINT16 Unknown : 1;
+ UINT16 VolatileMemory : 1;
+ UINT16 ByteAccessiblePersistentMemory : 1;
+ UINT16 BlockAccessiblePersistentMemory : 1;
+ UINT16 Reserved2 : 10; ///< Set to 0.
} Bits;
///
/// All bit fields as a 16-bit value
///
- UINT16 Uint16;
+ UINT16 Uint16;
} MEMORY_DEVICE_OPERATING_MODE_CAPABILITY;
///
@@ -1821,103 +1956,103 @@ typedef union {
/// socket is currently populated.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT16 MemoryArrayHandle;
- UINT16 MemoryErrorInformationHandle;
- UINT16 TotalWidth;
- UINT16 DataWidth;
- UINT16 Size;
- UINT8 FormFactor; ///< The enumeration value from MEMORY_FORM_FACTOR.
- UINT8 DeviceSet;
- SMBIOS_TABLE_STRING DeviceLocator;
- SMBIOS_TABLE_STRING BankLocator;
- UINT8 MemoryType; ///< The enumeration value from MEMORY_DEVICE_TYPE.
- MEMORY_DEVICE_TYPE_DETAIL TypeDetail;
- UINT16 Speed;
- SMBIOS_TABLE_STRING Manufacturer;
- SMBIOS_TABLE_STRING SerialNumber;
- SMBIOS_TABLE_STRING AssetTag;
- SMBIOS_TABLE_STRING PartNumber;
+ SMBIOS_STRUCTURE Hdr;
+ UINT16 MemoryArrayHandle;
+ UINT16 MemoryErrorInformationHandle;
+ UINT16 TotalWidth;
+ UINT16 DataWidth;
+ UINT16 Size;
+ UINT8 FormFactor; ///< The enumeration value from MEMORY_FORM_FACTOR.
+ UINT8 DeviceSet;
+ SMBIOS_TABLE_STRING DeviceLocator;
+ SMBIOS_TABLE_STRING BankLocator;
+ UINT8 MemoryType; ///< The enumeration value from MEMORY_DEVICE_TYPE.
+ MEMORY_DEVICE_TYPE_DETAIL TypeDetail;
+ UINT16 Speed;
+ SMBIOS_TABLE_STRING Manufacturer;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING AssetTag;
+ SMBIOS_TABLE_STRING PartNumber;
//
// Add for smbios 2.6
//
- UINT8 Attributes;
+ UINT8 Attributes;
//
// Add for smbios 2.7
//
- UINT32 ExtendedSize;
+ UINT32 ExtendedSize;
//
// Keep using name "ConfiguredMemoryClockSpeed" for compatibility
// although this field is renamed from "Configured Memory Clock Speed"
// to "Configured Memory Speed" in smbios 3.2.0.
//
- UINT16 ConfiguredMemoryClockSpeed;
+ UINT16 ConfiguredMemoryClockSpeed;
//
// Add for smbios 2.8.0
//
- UINT16 MinimumVoltage;
- UINT16 MaximumVoltage;
- UINT16 ConfiguredVoltage;
+ UINT16 MinimumVoltage;
+ UINT16 MaximumVoltage;
+ UINT16 ConfiguredVoltage;
//
// Add for smbios 3.2.0
//
- UINT8 MemoryTechnology; ///< The enumeration value from MEMORY_DEVICE_TECHNOLOGY
- MEMORY_DEVICE_OPERATING_MODE_CAPABILITY MemoryOperatingModeCapability;
- SMBIOS_TABLE_STRING FirmwareVersion;
- UINT16 ModuleManufacturerID;
- UINT16 ModuleProductID;
- UINT16 MemorySubsystemControllerManufacturerID;
- UINT16 MemorySubsystemControllerProductID;
- UINT64 NonVolatileSize;
- UINT64 VolatileSize;
- UINT64 CacheSize;
- UINT64 LogicalSize;
+ UINT8 MemoryTechnology; ///< The enumeration value from MEMORY_DEVICE_TECHNOLOGY
+ MEMORY_DEVICE_OPERATING_MODE_CAPABILITY MemoryOperatingModeCapability;
+ SMBIOS_TABLE_STRING FirmwareVersion;
+ UINT16 ModuleManufacturerID;
+ UINT16 ModuleProductID;
+ UINT16 MemorySubsystemControllerManufacturerID;
+ UINT16 MemorySubsystemControllerProductID;
+ UINT64 NonVolatileSize;
+ UINT64 VolatileSize;
+ UINT64 CacheSize;
+ UINT64 LogicalSize;
//
// Add for smbios 3.3.0
//
- UINT32 ExtendedSpeed;
- UINT32 ExtendedConfiguredMemorySpeed;
+ UINT32 ExtendedSpeed;
+ UINT32 ExtendedConfiguredMemorySpeed;
} SMBIOS_TABLE_TYPE17;
///
/// 32-bit Memory Error Information - Error Type.
///
typedef enum {
- MemoryErrorOther = 0x01,
- MemoryErrorUnknown = 0x02,
- MemoryErrorOk = 0x03,
- MemoryErrorBadRead = 0x04,
- MemoryErrorParity = 0x05,
- MemoryErrorSigleBit = 0x06,
- MemoryErrorDoubleBit = 0x07,
- MemoryErrorMultiBit = 0x08,
- MemoryErrorNibble = 0x09,
- MemoryErrorChecksum = 0x0A,
- MemoryErrorCrc = 0x0B,
- MemoryErrorCorrectSingleBit = 0x0C,
- MemoryErrorCorrected = 0x0D,
- MemoryErrorUnCorrectable = 0x0E
+ MemoryErrorOther = 0x01,
+ MemoryErrorUnknown = 0x02,
+ MemoryErrorOk = 0x03,
+ MemoryErrorBadRead = 0x04,
+ MemoryErrorParity = 0x05,
+ MemoryErrorSigleBit = 0x06,
+ MemoryErrorDoubleBit = 0x07,
+ MemoryErrorMultiBit = 0x08,
+ MemoryErrorNibble = 0x09,
+ MemoryErrorChecksum = 0x0A,
+ MemoryErrorCrc = 0x0B,
+ MemoryErrorCorrectSingleBit = 0x0C,
+ MemoryErrorCorrected = 0x0D,
+ MemoryErrorUnCorrectable = 0x0E
} MEMORY_ERROR_TYPE;
///
/// 32-bit Memory Error Information - Error Granularity.
///
typedef enum {
- MemoryGranularityOther = 0x01,
- MemoryGranularityOtherUnknown = 0x02,
- MemoryGranularityDeviceLevel = 0x03,
- MemoryGranularityMemPartitionLevel = 0x04
+ MemoryGranularityOther = 0x01,
+ MemoryGranularityOtherUnknown = 0x02,
+ MemoryGranularityDeviceLevel = 0x03,
+ MemoryGranularityMemPartitionLevel = 0x04
} MEMORY_ERROR_GRANULARITY;
///
/// 32-bit Memory Error Information - Error Operation.
///
typedef enum {
- MemoryErrorOperationOther = 0x01,
- MemoryErrorOperationUnknown = 0x02,
- MemoryErrorOperationRead = 0x03,
- MemoryErrorOperationWrite = 0x04,
- MemoryErrorOperationPartialWrite = 0x05
+ MemoryErrorOperationOther = 0x01,
+ MemoryErrorOperationUnknown = 0x02,
+ MemoryErrorOperationRead = 0x03,
+ MemoryErrorOperationWrite = 0x04,
+ MemoryErrorOperationPartialWrite = 0x05
} MEMORY_ERROR_OPERATION;
///
@@ -1927,14 +2062,14 @@ typedef enum {
/// within a Physical Memory Array.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT8 ErrorType; ///< The enumeration value from MEMORY_ERROR_TYPE.
- UINT8 ErrorGranularity; ///< The enumeration value from MEMORY_ERROR_GRANULARITY.
- UINT8 ErrorOperation; ///< The enumeration value from MEMORY_ERROR_OPERATION.
- UINT32 VendorSyndrome;
- UINT32 MemoryArrayErrorAddress;
- UINT32 DeviceErrorAddress;
- UINT32 ErrorResolution;
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 ErrorType; ///< The enumeration value from MEMORY_ERROR_TYPE.
+ UINT8 ErrorGranularity; ///< The enumeration value from MEMORY_ERROR_GRANULARITY.
+ UINT8 ErrorOperation; ///< The enumeration value from MEMORY_ERROR_OPERATION.
+ UINT32 VendorSyndrome;
+ UINT32 MemoryArrayErrorAddress;
+ UINT32 DeviceErrorAddress;
+ UINT32 ErrorResolution;
} SMBIOS_TABLE_TYPE18;
///
@@ -1944,16 +2079,16 @@ typedef struct {
/// One structure is present for each contiguous address range described.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT32 StartingAddress;
- UINT32 EndingAddress;
- UINT16 MemoryArrayHandle;
- UINT8 PartitionWidth;
+ SMBIOS_STRUCTURE Hdr;
+ UINT32 StartingAddress;
+ UINT32 EndingAddress;
+ UINT16 MemoryArrayHandle;
+ UINT8 PartitionWidth;
//
// Add for smbios 2.7
//
- UINT64 ExtendedStartingAddress;
- UINT64 ExtendedEndingAddress;
+ UINT64 ExtendedStartingAddress;
+ UINT64 ExtendedEndingAddress;
} SMBIOS_TABLE_TYPE19;
///
@@ -1963,51 +2098,53 @@ typedef struct {
/// One structure is present for each contiguous address range described.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT32 StartingAddress;
- UINT32 EndingAddress;
- UINT16 MemoryDeviceHandle;
- UINT16 MemoryArrayMappedAddressHandle;
- UINT8 PartitionRowPosition;
- UINT8 InterleavePosition;
- UINT8 InterleavedDataDepth;
+ SMBIOS_STRUCTURE Hdr;
+ UINT32 StartingAddress;
+ UINT32 EndingAddress;
+ UINT16 MemoryDeviceHandle;
+ UINT16 MemoryArrayMappedAddressHandle;
+ UINT8 PartitionRowPosition;
+ UINT8 InterleavePosition;
+ UINT8 InterleavedDataDepth;
//
// Add for smbios 2.7
//
- UINT64 ExtendedStartingAddress;
- UINT64 ExtendedEndingAddress;
+ UINT64 ExtendedStartingAddress;
+ UINT64 ExtendedEndingAddress;
} SMBIOS_TABLE_TYPE20;
///
/// Built-in Pointing Device - Type
///
typedef enum {
- PointingDeviceTypeOther = 0x01,
- PointingDeviceTypeUnknown = 0x02,
- PointingDeviceTypeMouse = 0x03,
- PointingDeviceTypeTrackBall = 0x04,
- PointingDeviceTypeTrackPoint = 0x05,
- PointingDeviceTypeGlidePoint = 0x06,
- PointingDeviceTouchPad = 0x07,
- PointingDeviceTouchScreen = 0x08,
- PointingDeviceOpticalSensor = 0x09
+ PointingDeviceTypeOther = 0x01,
+ PointingDeviceTypeUnknown = 0x02,
+ PointingDeviceTypeMouse = 0x03,
+ PointingDeviceTypeTrackBall = 0x04,
+ PointingDeviceTypeTrackPoint = 0x05,
+ PointingDeviceTypeGlidePoint = 0x06,
+ PointingDeviceTouchPad = 0x07,
+ PointingDeviceTouchScreen = 0x08,
+ PointingDeviceOpticalSensor = 0x09
} BUILTIN_POINTING_DEVICE_TYPE;
///
/// Built-in Pointing Device - Interface.
///
typedef enum {
- PointingDeviceInterfaceOther = 0x01,
- PointingDeviceInterfaceUnknown = 0x02,
- PointingDeviceInterfaceSerial = 0x03,
- PointingDeviceInterfacePs2 = 0x04,
- PointingDeviceInterfaceInfrared = 0x05,
- PointingDeviceInterfaceHpHil = 0x06,
- PointingDeviceInterfaceBusMouse = 0x07,
- PointingDeviceInterfaceADB = 0x08,
- PointingDeviceInterfaceBusMouseDB9 = 0xA0,
- PointingDeviceInterfaceBusMouseMicroDin = 0xA1,
- PointingDeviceInterfaceUsb = 0xA2
+ PointingDeviceInterfaceOther = 0x01,
+ PointingDeviceInterfaceUnknown = 0x02,
+ PointingDeviceInterfaceSerial = 0x03,
+ PointingDeviceInterfacePs2 = 0x04,
+ PointingDeviceInterfaceInfrared = 0x05,
+ PointingDeviceInterfaceHpHil = 0x06,
+ PointingDeviceInterfaceBusMouse = 0x07,
+ PointingDeviceInterfaceADB = 0x08,
+ PointingDeviceInterfaceBusMouseDB9 = 0xA0,
+ PointingDeviceInterfaceBusMouseMicroDin = 0xA1,
+ PointingDeviceInterfaceUsb = 0xA2,
+ PointingDeviceInterfaceI2c = 0xA3,
+ PointingDeviceInterfaceSpi = 0xA4
} BUILTIN_POINTING_DEVICE_INTERFACE;
///
@@ -2018,24 +2155,24 @@ typedef enum {
/// pointing device is active for the system's use!
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT8 Type; ///< The enumeration value from BUILTIN_POINTING_DEVICE_TYPE.
- UINT8 Interface; ///< The enumeration value from BUILTIN_POINTING_DEVICE_INTERFACE.
- UINT8 NumberOfButtons;
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 Type; ///< The enumeration value from BUILTIN_POINTING_DEVICE_TYPE.
+ UINT8 Interface; ///< The enumeration value from BUILTIN_POINTING_DEVICE_INTERFACE.
+ UINT8 NumberOfButtons;
} SMBIOS_TABLE_TYPE21;
///
/// Portable Battery - Device Chemistry
///
typedef enum {
- PortableBatteryDeviceChemistryOther = 0x01,
- PortableBatteryDeviceChemistryUnknown = 0x02,
- PortableBatteryDeviceChemistryLeadAcid = 0x03,
- PortableBatteryDeviceChemistryNickelCadmium = 0x04,
- PortableBatteryDeviceChemistryNickelMetalHydride = 0x05,
- PortableBatteryDeviceChemistryLithiumIon = 0x06,
- PortableBatteryDeviceChemistryZincAir = 0x07,
- PortableBatteryDeviceChemistryLithiumPolymer = 0x08
+ PortableBatteryDeviceChemistryOther = 0x01,
+ PortableBatteryDeviceChemistryUnknown = 0x02,
+ PortableBatteryDeviceChemistryLeadAcid = 0x03,
+ PortableBatteryDeviceChemistryNickelCadmium = 0x04,
+ PortableBatteryDeviceChemistryNickelMetalHydride = 0x05,
+ PortableBatteryDeviceChemistryLithiumIon = 0x06,
+ PortableBatteryDeviceChemistryZincAir = 0x07,
+ PortableBatteryDeviceChemistryLithiumPolymer = 0x08
} PORTABLE_BATTERY_DEVICE_CHEMISTRY;
///
@@ -2046,22 +2183,22 @@ typedef enum {
/// a single battery pack's attributes.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- SMBIOS_TABLE_STRING Location;
- SMBIOS_TABLE_STRING Manufacturer;
- SMBIOS_TABLE_STRING ManufactureDate;
- SMBIOS_TABLE_STRING SerialNumber;
- SMBIOS_TABLE_STRING DeviceName;
- UINT8 DeviceChemistry; ///< The enumeration value from PORTABLE_BATTERY_DEVICE_CHEMISTRY.
- UINT16 DeviceCapacity;
- UINT16 DesignVoltage;
- SMBIOS_TABLE_STRING SBDSVersionNumber;
- UINT8 MaximumErrorInBatteryData;
- UINT16 SBDSSerialNumber;
- UINT16 SBDSManufactureDate;
- SMBIOS_TABLE_STRING SBDSDeviceChemistry;
- UINT8 DesignCapacityMultiplier;
- UINT32 OEMSpecific;
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING Location;
+ SMBIOS_TABLE_STRING Manufacturer;
+ SMBIOS_TABLE_STRING ManufactureDate;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING DeviceName;
+ UINT8 DeviceChemistry; ///< The enumeration value from PORTABLE_BATTERY_DEVICE_CHEMISTRY.
+ UINT16 DeviceCapacity;
+ UINT16 DesignVoltage;
+ SMBIOS_TABLE_STRING SBDSVersionNumber;
+ UINT8 MaximumErrorInBatteryData;
+ UINT16 SBDSSerialNumber;
+ UINT16 SBDSManufactureDate;
+ SMBIOS_TABLE_STRING SBDSDeviceChemistry;
+ UINT8 DesignCapacityMultiplier;
+ UINT32 OEMSpecific;
} SMBIOS_TABLE_TYPE22;
///
@@ -2074,12 +2211,12 @@ typedef struct {
/// the system will re-boot according to the Boot Option at Limit.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT8 Capabilities;
- UINT16 ResetCount;
- UINT16 ResetLimit;
- UINT16 TimerInterval;
- UINT16 Timeout;
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 Capabilities;
+ UINT16 ResetCount;
+ UINT16 ResetLimit;
+ UINT16 TimerInterval;
+ UINT16 Timeout;
} SMBIOS_TABLE_TYPE23;
///
@@ -2088,8 +2225,8 @@ typedef struct {
/// This structure describes the system-wide hardware security settings.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT8 HardwareSecuritySettings;
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 HardwareSecuritySettings;
} SMBIOS_TABLE_TYPE24;
///
@@ -2101,20 +2238,20 @@ typedef struct {
/// this structure implies that a timed power-on facility is available for the system.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT8 NextScheduledPowerOnMonth;
- UINT8 NextScheduledPowerOnDayOfMonth;
- UINT8 NextScheduledPowerOnHour;
- UINT8 NextScheduledPowerOnMinute;
- UINT8 NextScheduledPowerOnSecond;
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 NextScheduledPowerOnMonth;
+ UINT8 NextScheduledPowerOnDayOfMonth;
+ UINT8 NextScheduledPowerOnHour;
+ UINT8 NextScheduledPowerOnMinute;
+ UINT8 NextScheduledPowerOnSecond;
} SMBIOS_TABLE_TYPE25;
///
/// Voltage Probe - Location and Status.
///
typedef struct {
- UINT8 VoltageProbeSite :5;
- UINT8 VoltageProbeStatus :3;
+ UINT8 VoltageProbeSite : 5;
+ UINT8 VoltageProbeStatus : 3;
} MISC_VOLTAGE_PROBE_LOCATION;
///
@@ -2124,24 +2261,24 @@ typedef struct {
/// Each structure describes a single voltage probe.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- SMBIOS_TABLE_STRING Description;
- MISC_VOLTAGE_PROBE_LOCATION LocationAndStatus;
- UINT16 MaximumValue;
- UINT16 MinimumValue;
- UINT16 Resolution;
- UINT16 Tolerance;
- UINT16 Accuracy;
- UINT32 OEMDefined;
- UINT16 NominalValue;
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING Description;
+ MISC_VOLTAGE_PROBE_LOCATION LocationAndStatus;
+ UINT16 MaximumValue;
+ UINT16 MinimumValue;
+ UINT16 Resolution;
+ UINT16 Tolerance;
+ UINT16 Accuracy;
+ UINT32 OEMDefined;
+ UINT16 NominalValue;
} SMBIOS_TABLE_TYPE26;
///
/// Cooling Device - Device Type and Status.
///
typedef struct {
- UINT8 CoolingDevice :5;
- UINT8 CoolingDeviceStatus :3;
+ UINT8 CoolingDevice : 5;
+ UINT8 CoolingDeviceStatus : 3;
} MISC_COOLING_DEVICE_TYPE;
///
@@ -2151,24 +2288,24 @@ typedef struct {
/// Each structure describes a single cooling device.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT16 TemperatureProbeHandle;
- MISC_COOLING_DEVICE_TYPE DeviceTypeAndStatus;
- UINT8 CoolingUnitGroup;
- UINT32 OEMDefined;
- UINT16 NominalSpeed;
+ SMBIOS_STRUCTURE Hdr;
+ UINT16 TemperatureProbeHandle;
+ MISC_COOLING_DEVICE_TYPE DeviceTypeAndStatus;
+ UINT8 CoolingUnitGroup;
+ UINT32 OEMDefined;
+ UINT16 NominalSpeed;
//
// Add for smbios 2.7
//
- SMBIOS_TABLE_STRING Description;
+ SMBIOS_TABLE_STRING Description;
} SMBIOS_TABLE_TYPE27;
///
/// Temperature Probe - Location and Status.
///
typedef struct {
- UINT8 TemperatureProbeSite :5;
- UINT8 TemperatureProbeStatus :3;
+ UINT8 TemperatureProbeSite : 5;
+ UINT8 TemperatureProbeStatus : 3;
} MISC_TEMPERATURE_PROBE_LOCATION;
///
@@ -2178,24 +2315,24 @@ typedef struct {
/// Each structure describes a single temperature probe.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- SMBIOS_TABLE_STRING Description;
- MISC_TEMPERATURE_PROBE_LOCATION LocationAndStatus;
- UINT16 MaximumValue;
- UINT16 MinimumValue;
- UINT16 Resolution;
- UINT16 Tolerance;
- UINT16 Accuracy;
- UINT32 OEMDefined;
- UINT16 NominalValue;
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING Description;
+ MISC_TEMPERATURE_PROBE_LOCATION LocationAndStatus;
+ UINT16 MaximumValue;
+ UINT16 MinimumValue;
+ UINT16 Resolution;
+ UINT16 Tolerance;
+ UINT16 Accuracy;
+ UINT32 OEMDefined;
+ UINT16 NominalValue;
} SMBIOS_TABLE_TYPE28;
///
/// Electrical Current Probe - Location and Status.
///
typedef struct {
- UINT8 ElectricalCurrentProbeSite :5;
- UINT8 ElectricalCurrentProbeStatus :3;
+ UINT8 ElectricalCurrentProbeSite : 5;
+ UINT8 ElectricalCurrentProbeStatus : 3;
} MISC_ELECTRICAL_CURRENT_PROBE_LOCATION;
///
@@ -2205,16 +2342,16 @@ typedef struct {
/// Each structure describes a single electrical current probe.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- SMBIOS_TABLE_STRING Description;
- MISC_ELECTRICAL_CURRENT_PROBE_LOCATION LocationAndStatus;
- UINT16 MaximumValue;
- UINT16 MinimumValue;
- UINT16 Resolution;
- UINT16 Tolerance;
- UINT16 Accuracy;
- UINT32 OEMDefined;
- UINT16 NominalValue;
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING Description;
+ MISC_ELECTRICAL_CURRENT_PROBE_LOCATION LocationAndStatus;
+ UINT16 MaximumValue;
+ UINT16 MinimumValue;
+ UINT16 Resolution;
+ UINT16 Tolerance;
+ UINT16 Accuracy;
+ UINT32 OEMDefined;
+ UINT16 NominalValue;
} SMBIOS_TABLE_TYPE29;
///
@@ -2225,9 +2362,9 @@ typedef struct {
/// is not available due to power-down status, hardware failures, or boot failures.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- SMBIOS_TABLE_STRING ManufacturerName;
- UINT8 Connections;
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING ManufacturerName;
+ UINT8 Connections;
} SMBIOS_TABLE_TYPE30;
///
@@ -2236,32 +2373,32 @@ typedef struct {
/// Structure type 31 (decimal) is reserved for use by the Boot Integrity Services (BIS).
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT8 Checksum;
- UINT8 Reserved1;
- UINT16 Reserved2;
- UINT32 BisEntry16;
- UINT32 BisEntry32;
- UINT64 Reserved3;
- UINT32 Reserved4;
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 Checksum;
+ UINT8 Reserved1;
+ UINT16 Reserved2;
+ UINT32 BisEntry16;
+ UINT32 BisEntry32;
+ UINT64 Reserved3;
+ UINT32 Reserved4;
} SMBIOS_TABLE_TYPE31;
///
/// System Boot Information - System Boot Status.
///
typedef enum {
- BootInformationStatusNoError = 0x00,
- BootInformationStatusNoBootableMedia = 0x01,
- BootInformationStatusNormalOSFailedLoading = 0x02,
- BootInformationStatusFirmwareDetectedFailure = 0x03,
- BootInformationStatusOSDetectedFailure = 0x04,
- BootInformationStatusUserRequestedBoot = 0x05,
- BootInformationStatusSystemSecurityViolation = 0x06,
- BootInformationStatusPreviousRequestedImage = 0x07,
- BootInformationStatusWatchdogTimerExpired = 0x08,
- BootInformationStatusStartReserved = 0x09,
- BootInformationStatusStartOemSpecific = 0x80,
- BootInformationStatusStartProductSpecific = 0xC0
+ BootInformationStatusNoError = 0x00,
+ BootInformationStatusNoBootableMedia = 0x01,
+ BootInformationStatusNormalOSFailedLoading = 0x02,
+ BootInformationStatusFirmwareDetectedFailure = 0x03,
+ BootInformationStatusOSDetectedFailure = 0x04,
+ BootInformationStatusUserRequestedBoot = 0x05,
+ BootInformationStatusSystemSecurityViolation = 0x06,
+ BootInformationStatusPreviousRequestedImage = 0x07,
+ BootInformationStatusWatchdogTimerExpired = 0x08,
+ BootInformationStatusStartReserved = 0x09,
+ BootInformationStatusStartOemSpecific = 0x80,
+ BootInformationStatusStartProductSpecific = 0xC0
} MISC_BOOT_INFORMATION_STATUS_DATA_TYPE;
///
@@ -2276,9 +2413,9 @@ typedef enum {
/// reason code indicated either a firmware- or operating system-detected hardware failure.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT8 Reserved[6];
- UINT8 BootStatus; ///< The enumeration value from MISC_BOOT_INFORMATION_STATUS_DATA_TYPE.
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 Reserved[6];
+ UINT8 BootStatus; ///< The enumeration value from MISC_BOOT_INFORMATION_STATUS_DATA_TYPE.
} SMBIOS_TABLE_TYPE32;
///
@@ -2288,33 +2425,33 @@ typedef struct {
/// when the error address is above 4G (0xFFFFFFFF).
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT8 ErrorType; ///< The enumeration value from MEMORY_ERROR_TYPE.
- UINT8 ErrorGranularity; ///< The enumeration value from MEMORY_ERROR_GRANULARITY.
- UINT8 ErrorOperation; ///< The enumeration value from MEMORY_ERROR_OPERATION.
- UINT32 VendorSyndrome;
- UINT64 MemoryArrayErrorAddress;
- UINT64 DeviceErrorAddress;
- UINT32 ErrorResolution;
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 ErrorType; ///< The enumeration value from MEMORY_ERROR_TYPE.
+ UINT8 ErrorGranularity; ///< The enumeration value from MEMORY_ERROR_GRANULARITY.
+ UINT8 ErrorOperation; ///< The enumeration value from MEMORY_ERROR_OPERATION.
+ UINT32 VendorSyndrome;
+ UINT64 MemoryArrayErrorAddress;
+ UINT64 DeviceErrorAddress;
+ UINT32 ErrorResolution;
} SMBIOS_TABLE_TYPE33;
///
/// Management Device - Type.
///
typedef enum {
- ManagementDeviceTypeOther = 0x01,
- ManagementDeviceTypeUnknown = 0x02,
- ManagementDeviceTypeLm75 = 0x03,
- ManagementDeviceTypeLm78 = 0x04,
- ManagementDeviceTypeLm79 = 0x05,
- ManagementDeviceTypeLm80 = 0x06,
- ManagementDeviceTypeLm81 = 0x07,
- ManagementDeviceTypeAdm9240 = 0x08,
- ManagementDeviceTypeDs1780 = 0x09,
- ManagementDeviceTypeMaxim1617 = 0x0A,
- ManagementDeviceTypeGl518Sm = 0x0B,
- ManagementDeviceTypeW83781D = 0x0C,
- ManagementDeviceTypeHt82H791 = 0x0D
+ ManagementDeviceTypeOther = 0x01,
+ ManagementDeviceTypeUnknown = 0x02,
+ ManagementDeviceTypeLm75 = 0x03,
+ ManagementDeviceTypeLm78 = 0x04,
+ ManagementDeviceTypeLm79 = 0x05,
+ ManagementDeviceTypeLm80 = 0x06,
+ ManagementDeviceTypeLm81 = 0x07,
+ ManagementDeviceTypeAdm9240 = 0x08,
+ ManagementDeviceTypeDs1780 = 0x09,
+ ManagementDeviceTypeMaxim1617 = 0x0A,
+ ManagementDeviceTypeGl518Sm = 0x0B,
+ ManagementDeviceTypeW83781D = 0x0C,
+ ManagementDeviceTypeHt82H791 = 0x0D
} MISC_MANAGEMENT_DEVICE_TYPE;
///
@@ -2336,11 +2473,11 @@ typedef enum {
/// probes as defined by one or more Management Device Component structures.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- SMBIOS_TABLE_STRING Description;
- UINT8 Type; ///< The enumeration value from MISC_MANAGEMENT_DEVICE_TYPE.
- UINT32 Address;
- UINT8 AddressType; ///< The enumeration value from MISC_MANAGEMENT_DEVICE_ADDRESS_TYPE.
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING Description;
+ UINT8 Type; ///< The enumeration value from MISC_MANAGEMENT_DEVICE_TYPE.
+ UINT32 Address;
+ UINT8 AddressType; ///< The enumeration value from MISC_MANAGEMENT_DEVICE_ADDRESS_TYPE.
} SMBIOS_TABLE_TYPE34;
///
@@ -2350,11 +2487,11 @@ typedef struct {
/// that define the controlling hardware device and (optionally) the component's thresholds.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- SMBIOS_TABLE_STRING Description;
- UINT16 ManagementDeviceHandle;
- UINT16 ComponentHandle;
- UINT16 ThresholdHandle;
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING Description;
+ UINT16 ManagementDeviceHandle;
+ UINT16 ComponentHandle;
+ UINT16 ThresholdHandle;
} SMBIOS_TABLE_TYPE35;
///
@@ -2364,31 +2501,31 @@ typedef struct {
/// a component (probe or cooling-unit) contained within a Management Device.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT16 LowerThresholdNonCritical;
- UINT16 UpperThresholdNonCritical;
- UINT16 LowerThresholdCritical;
- UINT16 UpperThresholdCritical;
- UINT16 LowerThresholdNonRecoverable;
- UINT16 UpperThresholdNonRecoverable;
+ SMBIOS_STRUCTURE Hdr;
+ UINT16 LowerThresholdNonCritical;
+ UINT16 UpperThresholdNonCritical;
+ UINT16 LowerThresholdCritical;
+ UINT16 UpperThresholdCritical;
+ UINT16 LowerThresholdNonRecoverable;
+ UINT16 UpperThresholdNonRecoverable;
} SMBIOS_TABLE_TYPE36;
///
/// Memory Channel Entry.
///
typedef struct {
- UINT8 DeviceLoad;
- UINT16 DeviceHandle;
+ UINT8 DeviceLoad;
+ UINT16 DeviceHandle;
} MEMORY_DEVICE;
///
/// Memory Channel - Channel Type.
///
typedef enum {
- MemoryChannelTypeOther = 0x01,
- MemoryChannelTypeUnknown = 0x02,
- MemoryChannelTypeRambus = 0x03,
- MemoryChannelTypeSyncLink = 0x04
+ MemoryChannelTypeOther = 0x01,
+ MemoryChannelTypeUnknown = 0x02,
+ MemoryChannelTypeRambus = 0x03,
+ MemoryChannelTypeSyncLink = 0x04
} MEMORY_CHANNEL_TYPE;
///
@@ -2399,22 +2536,22 @@ typedef enum {
/// The sum of all device loads cannot exceed the channel's defined maximum.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT8 ChannelType;
- UINT8 MaximumChannelLoad;
- UINT8 MemoryDeviceCount;
- MEMORY_DEVICE MemoryDevice[1];
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 ChannelType;
+ UINT8 MaximumChannelLoad;
+ UINT8 MemoryDeviceCount;
+ MEMORY_DEVICE MemoryDevice[1];
} SMBIOS_TABLE_TYPE37;
///
/// IPMI Device Information - BMC Interface Type
///
typedef enum {
- IPMIDeviceInfoInterfaceTypeUnknown = 0x00,
- IPMIDeviceInfoInterfaceTypeKCS = 0x01, ///< The Keyboard Controller Style.
- IPMIDeviceInfoInterfaceTypeSMIC = 0x02, ///< The Server Management Interface Chip.
- IPMIDeviceInfoInterfaceTypeBT = 0x03, ///< The Block Transfer
- IPMIDeviceInfoInterfaceTypeSSIF = 0x04 ///< SMBus System Interface
+ IPMIDeviceInfoInterfaceTypeUnknown = 0x00,
+ IPMIDeviceInfoInterfaceTypeKCS = 0x01, ///< The Keyboard Controller Style.
+ IPMIDeviceInfoInterfaceTypeSMIC = 0x02, ///< The Server Management Interface Chip.
+ IPMIDeviceInfoInterfaceTypeBT = 0x03, ///< The Block Transfer
+ IPMIDeviceInfoInterfaceTypeSSIF = 0x04 ///< SMBus System Interface
} BMC_INTERFACE_TYPE;
///
@@ -2429,27 +2566,27 @@ typedef enum {
/// Providing Type 38 is recommended for backward compatibility.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT8 InterfaceType; ///< The enumeration value from BMC_INTERFACE_TYPE.
- UINT8 IPMISpecificationRevision;
- UINT8 I2CSlaveAddress;
- UINT8 NVStorageDeviceAddress;
- UINT64 BaseAddress;
- UINT8 BaseAddressModifier_InterruptInfo;
- UINT8 InterruptNumber;
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 InterfaceType; ///< The enumeration value from BMC_INTERFACE_TYPE.
+ UINT8 IPMISpecificationRevision;
+ UINT8 I2CSlaveAddress;
+ UINT8 NVStorageDeviceAddress;
+ UINT64 BaseAddress;
+ UINT8 BaseAddressModifier_InterruptInfo;
+ UINT8 InterruptNumber;
} SMBIOS_TABLE_TYPE38;
///
/// System Power Supply - Power Supply Characteristics.
///
typedef struct {
- UINT16 PowerSupplyHotReplaceable:1;
- UINT16 PowerSupplyPresent :1;
- UINT16 PowerSupplyUnplugged :1;
- UINT16 InputVoltageRangeSwitch :4;
- UINT16 PowerSupplyStatus :3;
- UINT16 PowerSupplyType :4;
- UINT16 Reserved :2;
+ UINT16 PowerSupplyHotReplaceable : 1;
+ UINT16 PowerSupplyPresent : 1;
+ UINT16 PowerSupplyUnplugged : 1;
+ UINT16 InputVoltageRangeSwitch : 4;
+ UINT16 PowerSupplyStatus : 3;
+ UINT16 PowerSupplyType : 4;
+ UINT16 Reserved : 2;
} SYS_POWER_SUPPLY_CHARACTERISTICS;
///
@@ -2459,31 +2596,31 @@ typedef struct {
/// of this record is present for each possible power supply in a system.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT8 PowerUnitGroup;
- SMBIOS_TABLE_STRING Location;
- SMBIOS_TABLE_STRING DeviceName;
- SMBIOS_TABLE_STRING Manufacturer;
- SMBIOS_TABLE_STRING SerialNumber;
- SMBIOS_TABLE_STRING AssetTagNumber;
- SMBIOS_TABLE_STRING ModelPartNumber;
- SMBIOS_TABLE_STRING RevisionLevel;
- UINT16 MaxPowerCapacity;
- SYS_POWER_SUPPLY_CHARACTERISTICS PowerSupplyCharacteristics;
- UINT16 InputVoltageProbeHandle;
- UINT16 CoolingDeviceHandle;
- UINT16 InputCurrentProbeHandle;
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 PowerUnitGroup;
+ SMBIOS_TABLE_STRING Location;
+ SMBIOS_TABLE_STRING DeviceName;
+ SMBIOS_TABLE_STRING Manufacturer;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING AssetTagNumber;
+ SMBIOS_TABLE_STRING ModelPartNumber;
+ SMBIOS_TABLE_STRING RevisionLevel;
+ UINT16 MaxPowerCapacity;
+ SYS_POWER_SUPPLY_CHARACTERISTICS PowerSupplyCharacteristics;
+ UINT16 InputVoltageProbeHandle;
+ UINT16 CoolingDeviceHandle;
+ UINT16 InputCurrentProbeHandle;
} SMBIOS_TABLE_TYPE39;
///
/// Additional Information Entry Format.
///
typedef struct {
- UINT8 EntryLength;
- UINT16 ReferencedHandle;
- UINT8 ReferencedOffset;
- SMBIOS_TABLE_STRING EntryString;
- UINT8 Value[1];
+ UINT8 EntryLength;
+ UINT16 ReferencedHandle;
+ UINT8 ReferencedOffset;
+ SMBIOS_TABLE_STRING EntryString;
+ UINT8 Value[1];
} ADDITIONAL_INFORMATION_ENTRY;
///
@@ -2493,15 +2630,15 @@ typedef struct {
/// enumerated values and interim field updates in another structure.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT8 NumberOfAdditionalInformationEntries;
- ADDITIONAL_INFORMATION_ENTRY AdditionalInfoEntries[1];
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 NumberOfAdditionalInformationEntries;
+ ADDITIONAL_INFORMATION_ENTRY AdditionalInfoEntries[1];
} SMBIOS_TABLE_TYPE40;
///
/// Onboard Devices Extended Information - Onboard Device Types.
///
-typedef enum{
+typedef enum {
OnBoardDeviceExtendedTypeOther = 0x01,
OnBoardDeviceExtendedTypeUnknown = 0x02,
OnBoardDeviceExtendedTypeVideo = 0x03,
@@ -2511,7 +2648,13 @@ typedef enum{
OnBoardDeviceExtendedTypeSound = 0x07,
OnBoardDeviceExtendedTypePATAController = 0x08,
OnBoardDeviceExtendedTypeSATAController = 0x09,
- OnBoardDeviceExtendedTypeSASController = 0x0A
+ OnBoardDeviceExtendedTypeSASController = 0x0A,
+ OnBoardDeviceExtendedTypeWirelessLAN = 0x0B,
+ OnBoardDeviceExtendedTypeBluetooth = 0x0C,
+ OnBoardDeviceExtendedTypeWWAN = 0x0D,
+ OnBoardDeviceExtendedTypeeMMC = 0x0E,
+ OnBoardDeviceExtendedTypeNvme = 0x0F,
+ OnBoardDeviceExtendedTypeUfc = 0x10
} ONBOARD_DEVICE_EXTENDED_INFO_TYPE;
///
@@ -2523,41 +2666,41 @@ typedef enum{
/// control over the enabling of the associated device for use by the system.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- SMBIOS_TABLE_STRING ReferenceDesignation;
- UINT8 DeviceType; ///< The enumeration value from ONBOARD_DEVICE_EXTENDED_INFO_TYPE
- UINT8 DeviceTypeInstance;
- UINT16 SegmentGroupNum;
- UINT8 BusNum;
- UINT8 DevFuncNum;
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING ReferenceDesignation;
+ UINT8 DeviceType; ///< The enumeration value from ONBOARD_DEVICE_EXTENDED_INFO_TYPE
+ UINT8 DeviceTypeInstance;
+ UINT16 SegmentGroupNum;
+ UINT8 BusNum;
+ UINT8 DevFuncNum;
} SMBIOS_TABLE_TYPE41;
///
/// Management Controller Host Interface - Protocol Record Data Format.
///
typedef struct {
- UINT8 ProtocolType;
- UINT8 ProtocolTypeDataLen;
- UINT8 ProtocolTypeData[1];
+ UINT8 ProtocolType;
+ UINT8 ProtocolTypeDataLen;
+ UINT8 ProtocolTypeData[1];
} MC_HOST_INTERFACE_PROTOCOL_RECORD;
///
/// Management Controller Host Interface - Interface Types.
/// 00h - 3Fh: MCTP Host Interfaces
///
-typedef enum{
- MCHostInterfaceTypeNetworkHostInterface = 0x40,
- MCHostInterfaceTypeOemDefined = 0xF0
+typedef enum {
+ MCHostInterfaceTypeNetworkHostInterface = 0x40,
+ MCHostInterfaceTypeOemDefined = 0xF0
} MC_HOST_INTERFACE_TYPE;
///
/// Management Controller Host Interface - Protocol Types.
///
-typedef enum{
- MCHostInterfaceProtocolTypeIPMI = 0x02,
- MCHostInterfaceProtocolTypeMCTP = 0x03,
- MCHostInterfaceProtocolTypeRedfishOverIP = 0x04,
- MCHostInterfaceProtocolTypeOemDefined = 0xF0
+typedef enum {
+ MCHostInterfaceProtocolTypeIPMI = 0x02,
+ MCHostInterfaceProtocolTypeMCTP = 0x03,
+ MCHostInterfaceProtocolTypeRedfishOverIP = 0x04,
+ MCHostInterfaceProtocolTypeOemDefined = 0xF0
} MC_HOST_INTERFACE_PROTOCOL_TYPE;
///
@@ -2578,34 +2721,35 @@ typedef enum{
/// that do not yet recognize the Type 42 structure.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT8 InterfaceType; ///< The enumeration value from MC_HOST_INTERFACE_TYPE
- UINT8 InterfaceTypeSpecificDataLength;
- UINT8 InterfaceTypeSpecificData[4]; ///< This field has a minimum of four bytes
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 InterfaceType; ///< The enumeration value from MC_HOST_INTERFACE_TYPE
+ UINT8 InterfaceTypeSpecificDataLength;
+ UINT8 InterfaceTypeSpecificData[4]; ///< This field has a minimum of four bytes
} SMBIOS_TABLE_TYPE42;
-
///
/// Processor Specific Block - Processor Architecture Type
///
-typedef enum{
- ProcessorSpecificBlockArchTypeReserved = 0x00,
- ProcessorSpecificBlockArchTypeIa32 = 0x01,
- ProcessorSpecificBlockArchTypeX64 = 0x02,
- ProcessorSpecificBlockArchTypeItanium = 0x03,
- ProcessorSpecificBlockArchTypeAarch32 = 0x04,
- ProcessorSpecificBlockArchTypeAarch64 = 0x05,
- ProcessorSpecificBlockArchTypeRiscVRV32 = 0x06,
- ProcessorSpecificBlockArchTypeRiscVRV64 = 0x07,
- ProcessorSpecificBlockArchTypeRiscVRV128 = 0x08
+typedef enum {
+ ProcessorSpecificBlockArchTypeReserved = 0x00,
+ ProcessorSpecificBlockArchTypeIa32 = 0x01,
+ ProcessorSpecificBlockArchTypeX64 = 0x02,
+ ProcessorSpecificBlockArchTypeItanium = 0x03,
+ ProcessorSpecificBlockArchTypeAarch32 = 0x04,
+ ProcessorSpecificBlockArchTypeAarch64 = 0x05,
+ ProcessorSpecificBlockArchTypeRiscVRV32 = 0x06,
+ ProcessorSpecificBlockArchTypeRiscVRV64 = 0x07,
+ ProcessorSpecificBlockArchTypeRiscVRV128 = 0x08,
+ ProcessorSpecificBlockArchTypeLoongArch32 = 0x09,
+ ProcessorSpecificBlockArchTypeLoongArch64 = 0x0A
} PROCESSOR_SPECIFIC_BLOCK_ARCH_TYPE;
///
/// Processor Specific Block is the standard container of processor-specific data.
///
typedef struct {
- UINT8 Length;
- UINT8 ProcessorArchType;
+ UINT8 Length;
+ UINT8 ProcessorArchType;
///
/// Below followed by Processor-specific data
///
@@ -2627,96 +2771,201 @@ typedef struct {
/// architecture workgroups or vendors in separate documents.
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- SMBIOS_HANDLE RefHandle; ///< This field refer to associated SMBIOS type 4
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_HANDLE RefHandle; ///< This field refer to associated SMBIOS type 4
///
/// Below followed by Processor-specific block
///
- PROCESSOR_SPECIFIC_BLOCK ProcessorSpecificBlock;
+ PROCESSOR_SPECIFIC_BLOCK ProcessorSpecificBlock;
} SMBIOS_TABLE_TYPE44;
///
/// TPM Device (Type 43).
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
- UINT8 VendorID[4];
- UINT8 MajorSpecVersion;
- UINT8 MinorSpecVersion;
- UINT32 FirmwareVersion1;
- UINT32 FirmwareVersion2;
- SMBIOS_TABLE_STRING Description;
- UINT64 Characteristics;
- UINT32 OemDefined;
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 VendorID[4];
+ UINT8 MajorSpecVersion;
+ UINT8 MinorSpecVersion;
+ UINT32 FirmwareVersion1;
+ UINT32 FirmwareVersion2;
+ SMBIOS_TABLE_STRING Description;
+ UINT64 Characteristics;
+ UINT32 OemDefined;
} SMBIOS_TABLE_TYPE43;
+///
+/// Firmware Inventory Version Format Type (Type 45).
+///
+typedef enum {
+ VersionFormatTypeFreeForm = 0x00,
+ VersionFormatTypeMajorMinor = 0x01,
+ VersionFormatType32BitHex = 0x02,
+ VersionFormatType64BitHex = 0x03,
+ VersionFormatTypeReserved = 0x04, /// 0x04 - 0x7F are reserved
+ VersionFormatTypeOem = 0x80 /// 0x80 - 0xFF are BIOS Vendor/OEM-specific
+} FIRMWARE_INVENTORY_VERSION_FORMAT_TYPE;
+
+///
+/// Firmware Inventory Firmware Id Format Type (Type 45).
+///
+typedef enum {
+ FirmwareIdFormatTypeFreeForm = 0x00,
+ FirmwareIdFormatTypeUuid = 0x01,
+ FirmwareIdFormatTypeReserved = 0x04, /// 0x04 - 0x7F are reserved
+ InventoryFirmwareIdFormatTypeOem = 0x80 /// 0x80 - 0xFF are BIOS Vendor/OEM-specific
+} FIRMWARE_INVENTORY_FIRMWARE_ID_FORMAT_TYPE;
+
+///
+/// Firmware Inventory Firmware Characteristics (Type 45).
+///
+typedef struct {
+ UINT16 Updatable : 1;
+ UINT16 WriteProtected : 1;
+ UINT16 Reserved : 14;
+} FIRMWARE_CHARACTERISTICS;
+
+///
+/// Firmware Inventory State Information (Type 45).
+///
+typedef enum {
+ FirmwareInventoryStateOther = 0x01,
+ FirmwareInventoryStateUnknown = 0x02,
+ FirmwareInventoryStateDisabled = 0x03,
+ FirmwareInventoryStateEnabled = 0x04,
+ FirmwareInventoryStateAbsent = 0x05,
+ FirmwareInventoryStateStandbyOffline = 0x06,
+ FirmwareInventoryStateStandbySpare = 0x07,
+ FirmwareInventoryStateUnavailableOffline = 0x08
+} FIRMWARE_INVENTORY_STATE;
+
+///
+/// Firmware Inventory Information (Type 45)
+///
+/// The information in this structure defines an inventory of firmware
+/// components in the system. This can include firmware components such as
+/// BIOS, BMC, as well as firmware for other devices in the system.
+/// The information can be used by software to display the firmware inventory
+/// in a uniform manner. It can also be used by a management controller,
+/// such as a BMC, for remote system management.
+/// This structure is not intended to replace other standard programmatic
+/// interfaces for firmware updates.
+/// One Type 45 structure is provided for each firmware component.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING FirmwareComponentName;
+ SMBIOS_TABLE_STRING FirmwareVersion;
+ UINT8 FirmwareVersionFormat; ///< The enumeration value from FIRMWARE_INVENTORY_VERSION_FORMAT_TYPE
+ SMBIOS_TABLE_STRING FirmwareId;
+ UINT8 FirmwareIdFormat; ///< The enumeration value from FIRMWARE_INVENTORY_FIRMWARE_ID_FORMAT_TYPE.
+ SMBIOS_TABLE_STRING ReleaseDate;
+ SMBIOS_TABLE_STRING Manufacturer;
+ SMBIOS_TABLE_STRING LowestSupportedVersion;
+ UINT64 ImageSize;
+ FIRMWARE_CHARACTERISTICS Characteristics;
+ UINT8 State; ///< The enumeration value from FIRMWARE_INVENTORY_STATE.
+ UINT8 AssociatedComponentCount;
+ ///
+ /// zero or n-number of handles depends on AssociatedComponentCount
+ /// handles are of type SMBIOS_HANDLE
+ ///
+} SMBIOS_TABLE_TYPE45;
+
+///
+/// String Property IDs (Type 46).
+///
+typedef enum {
+ StringPropertyIdNone = 0x0000,
+ StringPropertyIdDevicePath = 0x0001,
+ StringPropertyIdReserved = 0x0002, /// Reserved 0x0002 - 0x7FFF
+ StringPropertyIdBiosVendor = 0x8000, /// BIOS vendor 0x8000 - 0xBFFF
+ StringPropertyIdOem = 0xC000 /// OEM range 0xC000 - 0xFFFF
+} STRING_PROPERTY_ID;
+
+///
+/// This structure defines a string property for another structure.
+/// This allows adding string properties that are common to several structures
+/// without having to modify the definitions of these structures.
+/// Multiple type 46 structures can add string properties to the same
+/// parent structure.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT16 StringPropertyId; ///< The enumeration value from STRING_PROPERTY_ID.
+ SMBIOS_TABLE_STRING StringPropertyValue;
+ SMBIOS_HANDLE ParentHandle;
+} SMBIOS_TABLE_TYPE46;
+
///
/// Inactive (Type 126)
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
+ SMBIOS_STRUCTURE Hdr;
} SMBIOS_TABLE_TYPE126;
///
/// End-of-Table (Type 127)
///
typedef struct {
- SMBIOS_STRUCTURE Hdr;
+ SMBIOS_STRUCTURE Hdr;
} SMBIOS_TABLE_TYPE127;
///
/// Union of all the possible SMBIOS record types.
///
typedef union {
- SMBIOS_STRUCTURE *Hdr;
- SMBIOS_TABLE_TYPE0 *Type0;
- SMBIOS_TABLE_TYPE1 *Type1;
- SMBIOS_TABLE_TYPE2 *Type2;
- SMBIOS_TABLE_TYPE3 *Type3;
- SMBIOS_TABLE_TYPE4 *Type4;
- SMBIOS_TABLE_TYPE5 *Type5;
- SMBIOS_TABLE_TYPE6 *Type6;
- SMBIOS_TABLE_TYPE7 *Type7;
- SMBIOS_TABLE_TYPE8 *Type8;
- SMBIOS_TABLE_TYPE9 *Type9;
- SMBIOS_TABLE_TYPE10 *Type10;
- SMBIOS_TABLE_TYPE11 *Type11;
- SMBIOS_TABLE_TYPE12 *Type12;
- SMBIOS_TABLE_TYPE13 *Type13;
- SMBIOS_TABLE_TYPE14 *Type14;
- SMBIOS_TABLE_TYPE15 *Type15;
- SMBIOS_TABLE_TYPE16 *Type16;
- SMBIOS_TABLE_TYPE17 *Type17;
- SMBIOS_TABLE_TYPE18 *Type18;
- SMBIOS_TABLE_TYPE19 *Type19;
- SMBIOS_TABLE_TYPE20 *Type20;
- SMBIOS_TABLE_TYPE21 *Type21;
- SMBIOS_TABLE_TYPE22 *Type22;
- SMBIOS_TABLE_TYPE23 *Type23;
- SMBIOS_TABLE_TYPE24 *Type24;
- SMBIOS_TABLE_TYPE25 *Type25;
- SMBIOS_TABLE_TYPE26 *Type26;
- SMBIOS_TABLE_TYPE27 *Type27;
- SMBIOS_TABLE_TYPE28 *Type28;
- SMBIOS_TABLE_TYPE29 *Type29;
- SMBIOS_TABLE_TYPE30 *Type30;
- SMBIOS_TABLE_TYPE31 *Type31;
- SMBIOS_TABLE_TYPE32 *Type32;
- SMBIOS_TABLE_TYPE33 *Type33;
- SMBIOS_TABLE_TYPE34 *Type34;
- SMBIOS_TABLE_TYPE35 *Type35;
- SMBIOS_TABLE_TYPE36 *Type36;
- SMBIOS_TABLE_TYPE37 *Type37;
- SMBIOS_TABLE_TYPE38 *Type38;
- SMBIOS_TABLE_TYPE39 *Type39;
- SMBIOS_TABLE_TYPE40 *Type40;
- SMBIOS_TABLE_TYPE41 *Type41;
- SMBIOS_TABLE_TYPE42 *Type42;
- SMBIOS_TABLE_TYPE43 *Type43;
- SMBIOS_TABLE_TYPE44 *Type44;
- SMBIOS_TABLE_TYPE126 *Type126;
- SMBIOS_TABLE_TYPE127 *Type127;
- UINT8 *Raw;
+ SMBIOS_STRUCTURE *Hdr;
+ SMBIOS_TABLE_TYPE0 *Type0;
+ SMBIOS_TABLE_TYPE1 *Type1;
+ SMBIOS_TABLE_TYPE2 *Type2;
+ SMBIOS_TABLE_TYPE3 *Type3;
+ SMBIOS_TABLE_TYPE4 *Type4;
+ SMBIOS_TABLE_TYPE5 *Type5;
+ SMBIOS_TABLE_TYPE6 *Type6;
+ SMBIOS_TABLE_TYPE7 *Type7;
+ SMBIOS_TABLE_TYPE8 *Type8;
+ SMBIOS_TABLE_TYPE9 *Type9;
+ SMBIOS_TABLE_TYPE10 *Type10;
+ SMBIOS_TABLE_TYPE11 *Type11;
+ SMBIOS_TABLE_TYPE12 *Type12;
+ SMBIOS_TABLE_TYPE13 *Type13;
+ SMBIOS_TABLE_TYPE14 *Type14;
+ SMBIOS_TABLE_TYPE15 *Type15;
+ SMBIOS_TABLE_TYPE16 *Type16;
+ SMBIOS_TABLE_TYPE17 *Type17;
+ SMBIOS_TABLE_TYPE18 *Type18;
+ SMBIOS_TABLE_TYPE19 *Type19;
+ SMBIOS_TABLE_TYPE20 *Type20;
+ SMBIOS_TABLE_TYPE21 *Type21;
+ SMBIOS_TABLE_TYPE22 *Type22;
+ SMBIOS_TABLE_TYPE23 *Type23;
+ SMBIOS_TABLE_TYPE24 *Type24;
+ SMBIOS_TABLE_TYPE25 *Type25;
+ SMBIOS_TABLE_TYPE26 *Type26;
+ SMBIOS_TABLE_TYPE27 *Type27;
+ SMBIOS_TABLE_TYPE28 *Type28;
+ SMBIOS_TABLE_TYPE29 *Type29;
+ SMBIOS_TABLE_TYPE30 *Type30;
+ SMBIOS_TABLE_TYPE31 *Type31;
+ SMBIOS_TABLE_TYPE32 *Type32;
+ SMBIOS_TABLE_TYPE33 *Type33;
+ SMBIOS_TABLE_TYPE34 *Type34;
+ SMBIOS_TABLE_TYPE35 *Type35;
+ SMBIOS_TABLE_TYPE36 *Type36;
+ SMBIOS_TABLE_TYPE37 *Type37;
+ SMBIOS_TABLE_TYPE38 *Type38;
+ SMBIOS_TABLE_TYPE39 *Type39;
+ SMBIOS_TABLE_TYPE40 *Type40;
+ SMBIOS_TABLE_TYPE41 *Type41;
+ SMBIOS_TABLE_TYPE42 *Type42;
+ SMBIOS_TABLE_TYPE43 *Type43;
+ SMBIOS_TABLE_TYPE44 *Type44;
+ SMBIOS_TABLE_TYPE45 *Type45;
+ SMBIOS_TABLE_TYPE46 *Type46;
+ SMBIOS_TABLE_TYPE126 *Type126;
+ SMBIOS_TABLE_TYPE127 *Type127;
+ UINT8 *Raw;
} SMBIOS_STRUCTURE_POINTER;
#pragma pack()
diff --git a/MdePkg/Include/IndustryStandard/SmBus.h b/MdePkg/Include/IndustryStandard/SmBus.h
index 43bf6f59..ad0d8b0e 100644
--- a/MdePkg/Include/IndustryStandard/SmBus.h
+++ b/MdePkg/Include/IndustryStandard/SmBus.h
@@ -10,19 +10,18 @@
#ifndef _SMBUS_H_
#define _SMBUS_H_
-
///
/// UDID of SMBUS device.
///
typedef struct {
- UINT32 VendorSpecificId;
- UINT16 SubsystemDeviceId;
- UINT16 SubsystemVendorId;
- UINT16 Interface;
- UINT16 DeviceId;
- UINT16 VendorId;
- UINT8 VendorRevision;
- UINT8 DeviceCapabilities;
+ UINT32 VendorSpecificId;
+ UINT16 SubsystemDeviceId;
+ UINT16 SubsystemVendorId;
+ UINT16 Interface;
+ UINT16 DeviceId;
+ UINT16 VendorId;
+ UINT8 VendorRevision;
+ UINT8 DeviceCapabilities;
} EFI_SMBUS_UDID;
///
@@ -32,7 +31,7 @@ typedef struct {
///
/// The SMBUS hardware address to which the SMBUS device is preassigned or allocated.
///
- UINTN SmbusDeviceAddress : 7;
+ UINTN SmbusDeviceAddress : 7;
} EFI_SMBUS_DEVICE_ADDRESS;
typedef struct {
@@ -40,12 +39,12 @@ typedef struct {
/// The SMBUS hardware address to which the SMBUS device is preassigned or
/// allocated. Type EFI_SMBUS_DEVICE_ADDRESS is defined in EFI_PEI_SMBUS2_PPI.Execute().
///
- EFI_SMBUS_DEVICE_ADDRESS SmbusDeviceAddress;
+ EFI_SMBUS_DEVICE_ADDRESS SmbusDeviceAddress;
///
/// The SMBUS Unique Device Identifier (UDID) as defined in EFI_SMBUS_UDID.
/// Type EFI_SMBUS_UDID is defined in EFI_PEI_SMBUS2_PPI.ArpDevice().
///
- EFI_SMBUS_UDID SmbusDeviceUdid;
+ EFI_SMBUS_UDID SmbusDeviceUdid;
} EFI_SMBUS_DEVICE_MAP;
///
@@ -69,7 +68,6 @@ typedef enum _EFI_SMBUS_OPERATION {
///
/// EFI_SMBUS_DEVICE_COMMAND
///
-typedef UINTN EFI_SMBUS_DEVICE_COMMAND;
+typedef UINTN EFI_SMBUS_DEVICE_COMMAND;
#endif
-
diff --git a/MdePkg/Include/IndustryStandard/Tpm12.h b/MdePkg/Include/IndustryStandard/Tpm12.h
index 4ac86c4c..031b2067 100644
--- a/MdePkg/Include/IndustryStandard/Tpm12.h
+++ b/MdePkg/Include/IndustryStandard/Tpm12.h
@@ -6,14 +6,13 @@
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
-
#ifndef _TPM12_H_
#define _TPM12_H_
///
/// The start of TPM return codes
///
-#define TPM_BASE 0
+#define TPM_BASE 0
//
// All structures MUST be packed on a byte boundary.
@@ -27,246 +26,246 @@
///
/// Indicates the conditions where it is required that authorization be presented
///
-typedef UINT8 TPM_AUTH_DATA_USAGE;
+typedef UINT8 TPM_AUTH_DATA_USAGE;
///
/// The information as to what the payload is in an encrypted structure
///
-typedef UINT8 TPM_PAYLOAD_TYPE;
+typedef UINT8 TPM_PAYLOAD_TYPE;
///
/// The version info breakdown
///
-typedef UINT8 TPM_VERSION_BYTE;
+typedef UINT8 TPM_VERSION_BYTE;
///
/// The state of the dictionary attack mitigation logic
///
-typedef UINT8 TPM_DA_STATE;
+typedef UINT8 TPM_DA_STATE;
///
/// The request or response authorization type
///
-typedef UINT16 TPM_TAG;
+typedef UINT16 TPM_TAG;
///
/// The protocol in use
///
-typedef UINT16 TPM_PROTOCOL_ID;
+typedef UINT16 TPM_PROTOCOL_ID;
///
/// Indicates the start state
///
-typedef UINT16 TPM_STARTUP_TYPE;
+typedef UINT16 TPM_STARTUP_TYPE;
///
/// The definition of the encryption scheme
///
-typedef UINT16 TPM_ENC_SCHEME;
+typedef UINT16 TPM_ENC_SCHEME;
///
/// The definition of the signature scheme
///
-typedef UINT16 TPM_SIG_SCHEME;
+typedef UINT16 TPM_SIG_SCHEME;
///
/// The definition of the migration scheme
///
-typedef UINT16 TPM_MIGRATE_SCHEME;
+typedef UINT16 TPM_MIGRATE_SCHEME;
///
/// Sets the state of the physical presence mechanism
///
-typedef UINT16 TPM_PHYSICAL_PRESENCE;
+typedef UINT16 TPM_PHYSICAL_PRESENCE;
///
/// Indicates the types of entity that are supported by the TPM
///
-typedef UINT16 TPM_ENTITY_TYPE;
+typedef UINT16 TPM_ENTITY_TYPE;
///
/// Indicates the permitted usage of the key
///
-typedef UINT16 TPM_KEY_USAGE;
+typedef UINT16 TPM_KEY_USAGE;
///
/// The type of asymmetric encrypted structure in use by the endorsement key
///
-typedef UINT16 TPM_EK_TYPE;
+typedef UINT16 TPM_EK_TYPE;
///
/// The tag for the structure
///
-typedef UINT16 TPM_STRUCTURE_TAG;
+typedef UINT16 TPM_STRUCTURE_TAG;
///
/// The platform specific spec to which the information relates to
///
-typedef UINT16 TPM_PLATFORM_SPECIFIC;
+typedef UINT16 TPM_PLATFORM_SPECIFIC;
///
/// The command ordinal
///
-typedef UINT32 TPM_COMMAND_CODE;
+typedef UINT32 TPM_COMMAND_CODE;
///
/// Identifies a TPM capability area
///
-typedef UINT32 TPM_CAPABILITY_AREA;
+typedef UINT32 TPM_CAPABILITY_AREA;
///
/// Indicates information regarding a key
///
-typedef UINT32 TPM_KEY_FLAGS;
+typedef UINT32 TPM_KEY_FLAGS;
///
/// Indicates the type of algorithm
///
-typedef UINT32 TPM_ALGORITHM_ID;
+typedef UINT32 TPM_ALGORITHM_ID;
///
/// The locality modifier
///
-typedef UINT32 TPM_MODIFIER_INDICATOR;
+typedef UINT32 TPM_MODIFIER_INDICATOR;
///
/// The actual number of a counter
///
-typedef UINT32 TPM_ACTUAL_COUNT;
+typedef UINT32 TPM_ACTUAL_COUNT;
///
/// Attributes that define what options are in use for a transport session
///
-typedef UINT32 TPM_TRANSPORT_ATTRIBUTES;
+typedef UINT32 TPM_TRANSPORT_ATTRIBUTES;
///
/// Handle to an authorization session
///
-typedef UINT32 TPM_AUTHHANDLE;
+typedef UINT32 TPM_AUTHHANDLE;
///
/// Index to a DIR register
///
-typedef UINT32 TPM_DIRINDEX;
+typedef UINT32 TPM_DIRINDEX;
///
/// The area where a key is held assigned by the TPM
///
-typedef UINT32 TPM_KEY_HANDLE;
+typedef UINT32 TPM_KEY_HANDLE;
///
/// Index to a PCR register
///
-typedef UINT32 TPM_PCRINDEX;
+typedef UINT32 TPM_PCRINDEX;
///
/// The return code from a function
///
-typedef UINT32 TPM_RESULT;
+typedef UINT32 TPM_RESULT;
///
/// The types of resources that a TPM may have using internal resources
///
-typedef UINT32 TPM_RESOURCE_TYPE;
+typedef UINT32 TPM_RESOURCE_TYPE;
///
/// Allows for controlling of the key when loaded and how to handle TPM_Startup issues
///
-typedef UINT32 TPM_KEY_CONTROL;
+typedef UINT32 TPM_KEY_CONTROL;
///
/// The index into the NV storage area
///
-typedef UINT32 TPM_NV_INDEX;
+typedef UINT32 TPM_NV_INDEX;
///
/// The family ID. Family IDs are automatically assigned a sequence number by the TPM.
/// A trusted process can set the FamilyID value in an individual row to NULL, which
/// invalidates that row. The family ID resets to NULL on each change of TPM Owner.
///
-typedef UINT32 TPM_FAMILY_ID;
+typedef UINT32 TPM_FAMILY_ID;
///
/// IA value used as a label for the most recent verification of this family. Set to zero when not in use.
///
-typedef UINT32 TPM_FAMILY_VERIFICATION;
+typedef UINT32 TPM_FAMILY_VERIFICATION;
///
/// How the TPM handles var
///
-typedef UINT32 TPM_STARTUP_EFFECTS;
+typedef UINT32 TPM_STARTUP_EFFECTS;
///
/// The mode of a symmetric encryption
///
-typedef UINT32 TPM_SYM_MODE;
+typedef UINT32 TPM_SYM_MODE;
///
/// The family flags
///
-typedef UINT32 TPM_FAMILY_FLAGS;
+typedef UINT32 TPM_FAMILY_FLAGS;
///
/// The index value for the delegate NV table
///
-typedef UINT32 TPM_DELEGATE_INDEX;
+typedef UINT32 TPM_DELEGATE_INDEX;
///
/// The restrictions placed on delegation of CMK commands
///
-typedef UINT32 TPM_CMK_DELEGATE;
+typedef UINT32 TPM_CMK_DELEGATE;
///
/// The ID value of a monotonic counter
///
-typedef UINT32 TPM_COUNT_ID;
+typedef UINT32 TPM_COUNT_ID;
///
/// A command to execute
///
-typedef UINT32 TPM_REDIT_COMMAND;
+typedef UINT32 TPM_REDIT_COMMAND;
///
/// A transport session handle
///
-typedef UINT32 TPM_TRANSHANDLE;
+typedef UINT32 TPM_TRANSHANDLE;
///
/// A generic handle could be key, transport etc
///
-typedef UINT32 TPM_HANDLE;
+typedef UINT32 TPM_HANDLE;
///
/// What operation is happening
///
-typedef UINT32 TPM_FAMILY_OPERATION;
+typedef UINT32 TPM_FAMILY_OPERATION;
//
// Part 2, section 2.2.4: Vendor specific
// The following defines allow for the quick specification of a
// vendor specific item.
//
-#define TPM_Vendor_Specific32 ((UINT32) 0x00000400)
-#define TPM_Vendor_Specific8 ((UINT8) 0x80)
+#define TPM_Vendor_Specific32 ((UINT32) 0x00000400)
+#define TPM_Vendor_Specific8 ((UINT8) 0x80)
//
// Part 2, section 3.1: TPM_STRUCTURE_TAG
//
-#define TPM_TAG_CONTEXTBLOB ((TPM_STRUCTURE_TAG) 0x0001)
-#define TPM_TAG_CONTEXT_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0002)
-#define TPM_TAG_CONTEXTPOINTER ((TPM_STRUCTURE_TAG) 0x0003)
-#define TPM_TAG_CONTEXTLIST ((TPM_STRUCTURE_TAG) 0x0004)
-#define TPM_TAG_SIGNINFO ((TPM_STRUCTURE_TAG) 0x0005)
-#define TPM_TAG_PCR_INFO_LONG ((TPM_STRUCTURE_TAG) 0x0006)
-#define TPM_TAG_PERSISTENT_FLAGS ((TPM_STRUCTURE_TAG) 0x0007)
-#define TPM_TAG_VOLATILE_FLAGS ((TPM_STRUCTURE_TAG) 0x0008)
-#define TPM_TAG_PERSISTENT_DATA ((TPM_STRUCTURE_TAG) 0x0009)
-#define TPM_TAG_VOLATILE_DATA ((TPM_STRUCTURE_TAG) 0x000A)
-#define TPM_TAG_SV_DATA ((TPM_STRUCTURE_TAG) 0x000B)
-#define TPM_TAG_EK_BLOB ((TPM_STRUCTURE_TAG) 0x000C)
-#define TPM_TAG_EK_BLOB_AUTH ((TPM_STRUCTURE_TAG) 0x000D)
-#define TPM_TAG_COUNTER_VALUE ((TPM_STRUCTURE_TAG) 0x000E)
-#define TPM_TAG_TRANSPORT_INTERNAL ((TPM_STRUCTURE_TAG) 0x000F)
-#define TPM_TAG_TRANSPORT_LOG_IN ((TPM_STRUCTURE_TAG) 0x0010)
-#define TPM_TAG_TRANSPORT_LOG_OUT ((TPM_STRUCTURE_TAG) 0x0011)
-#define TPM_TAG_AUDIT_EVENT_IN ((TPM_STRUCTURE_TAG) 0x0012)
-#define TPM_TAG_AUDIT_EVENT_OUT ((TPM_STRUCTURE_TAG) 0x0013)
-#define TPM_TAG_CURRENT_TICKS ((TPM_STRUCTURE_TAG) 0x0014)
-#define TPM_TAG_KEY ((TPM_STRUCTURE_TAG) 0x0015)
-#define TPM_TAG_STORED_DATA12 ((TPM_STRUCTURE_TAG) 0x0016)
-#define TPM_TAG_NV_ATTRIBUTES ((TPM_STRUCTURE_TAG) 0x0017)
-#define TPM_TAG_NV_DATA_PUBLIC ((TPM_STRUCTURE_TAG) 0x0018)
-#define TPM_TAG_NV_DATA_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0019)
-#define TPM_TAG_DELEGATIONS ((TPM_STRUCTURE_TAG) 0x001A)
-#define TPM_TAG_DELEGATE_PUBLIC ((TPM_STRUCTURE_TAG) 0x001B)
-#define TPM_TAG_DELEGATE_TABLE_ROW ((TPM_STRUCTURE_TAG) 0x001C)
-#define TPM_TAG_TRANSPORT_AUTH ((TPM_STRUCTURE_TAG) 0x001D)
-#define TPM_TAG_TRANSPORT_PUBLIC ((TPM_STRUCTURE_TAG) 0x001E)
-#define TPM_TAG_PERMANENT_FLAGS ((TPM_STRUCTURE_TAG) 0x001F)
-#define TPM_TAG_STCLEAR_FLAGS ((TPM_STRUCTURE_TAG) 0x0020)
-#define TPM_TAG_STANY_FLAGS ((TPM_STRUCTURE_TAG) 0x0021)
-#define TPM_TAG_PERMANENT_DATA ((TPM_STRUCTURE_TAG) 0x0022)
-#define TPM_TAG_STCLEAR_DATA ((TPM_STRUCTURE_TAG) 0x0023)
-#define TPM_TAG_STANY_DATA ((TPM_STRUCTURE_TAG) 0x0024)
-#define TPM_TAG_FAMILY_TABLE_ENTRY ((TPM_STRUCTURE_TAG) 0x0025)
-#define TPM_TAG_DELEGATE_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0026)
-#define TPM_TAG_DELG_KEY_BLOB ((TPM_STRUCTURE_TAG) 0x0027)
-#define TPM_TAG_KEY12 ((TPM_STRUCTURE_TAG) 0x0028)
-#define TPM_TAG_CERTIFY_INFO2 ((TPM_STRUCTURE_TAG) 0x0029)
-#define TPM_TAG_DELEGATE_OWNER_BLOB ((TPM_STRUCTURE_TAG) 0x002A)
-#define TPM_TAG_EK_BLOB_ACTIVATE ((TPM_STRUCTURE_TAG) 0x002B)
-#define TPM_TAG_DAA_BLOB ((TPM_STRUCTURE_TAG) 0x002C)
-#define TPM_TAG_DAA_CONTEXT ((TPM_STRUCTURE_TAG) 0x002D)
-#define TPM_TAG_DAA_ENFORCE ((TPM_STRUCTURE_TAG) 0x002E)
-#define TPM_TAG_DAA_ISSUER ((TPM_STRUCTURE_TAG) 0x002F)
-#define TPM_TAG_CAP_VERSION_INFO ((TPM_STRUCTURE_TAG) 0x0030)
-#define TPM_TAG_DAA_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0031)
-#define TPM_TAG_DAA_TPM ((TPM_STRUCTURE_TAG) 0x0032)
-#define TPM_TAG_CMK_MIGAUTH ((TPM_STRUCTURE_TAG) 0x0033)
-#define TPM_TAG_CMK_SIGTICKET ((TPM_STRUCTURE_TAG) 0x0034)
-#define TPM_TAG_CMK_MA_APPROVAL ((TPM_STRUCTURE_TAG) 0x0035)
-#define TPM_TAG_QUOTE_INFO2 ((TPM_STRUCTURE_TAG) 0x0036)
-#define TPM_TAG_DA_INFO ((TPM_STRUCTURE_TAG) 0x0037)
-#define TPM_TAG_DA_LIMITED ((TPM_STRUCTURE_TAG) 0x0038)
-#define TPM_TAG_DA_ACTION_TYPE ((TPM_STRUCTURE_TAG) 0x0039)
+#define TPM_TAG_CONTEXTBLOB ((TPM_STRUCTURE_TAG) 0x0001)
+#define TPM_TAG_CONTEXT_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0002)
+#define TPM_TAG_CONTEXTPOINTER ((TPM_STRUCTURE_TAG) 0x0003)
+#define TPM_TAG_CONTEXTLIST ((TPM_STRUCTURE_TAG) 0x0004)
+#define TPM_TAG_SIGNINFO ((TPM_STRUCTURE_TAG) 0x0005)
+#define TPM_TAG_PCR_INFO_LONG ((TPM_STRUCTURE_TAG) 0x0006)
+#define TPM_TAG_PERSISTENT_FLAGS ((TPM_STRUCTURE_TAG) 0x0007)
+#define TPM_TAG_VOLATILE_FLAGS ((TPM_STRUCTURE_TAG) 0x0008)
+#define TPM_TAG_PERSISTENT_DATA ((TPM_STRUCTURE_TAG) 0x0009)
+#define TPM_TAG_VOLATILE_DATA ((TPM_STRUCTURE_TAG) 0x000A)
+#define TPM_TAG_SV_DATA ((TPM_STRUCTURE_TAG) 0x000B)
+#define TPM_TAG_EK_BLOB ((TPM_STRUCTURE_TAG) 0x000C)
+#define TPM_TAG_EK_BLOB_AUTH ((TPM_STRUCTURE_TAG) 0x000D)
+#define TPM_TAG_COUNTER_VALUE ((TPM_STRUCTURE_TAG) 0x000E)
+#define TPM_TAG_TRANSPORT_INTERNAL ((TPM_STRUCTURE_TAG) 0x000F)
+#define TPM_TAG_TRANSPORT_LOG_IN ((TPM_STRUCTURE_TAG) 0x0010)
+#define TPM_TAG_TRANSPORT_LOG_OUT ((TPM_STRUCTURE_TAG) 0x0011)
+#define TPM_TAG_AUDIT_EVENT_IN ((TPM_STRUCTURE_TAG) 0x0012)
+#define TPM_TAG_AUDIT_EVENT_OUT ((TPM_STRUCTURE_TAG) 0x0013)
+#define TPM_TAG_CURRENT_TICKS ((TPM_STRUCTURE_TAG) 0x0014)
+#define TPM_TAG_KEY ((TPM_STRUCTURE_TAG) 0x0015)
+#define TPM_TAG_STORED_DATA12 ((TPM_STRUCTURE_TAG) 0x0016)
+#define TPM_TAG_NV_ATTRIBUTES ((TPM_STRUCTURE_TAG) 0x0017)
+#define TPM_TAG_NV_DATA_PUBLIC ((TPM_STRUCTURE_TAG) 0x0018)
+#define TPM_TAG_NV_DATA_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0019)
+#define TPM_TAG_DELEGATIONS ((TPM_STRUCTURE_TAG) 0x001A)
+#define TPM_TAG_DELEGATE_PUBLIC ((TPM_STRUCTURE_TAG) 0x001B)
+#define TPM_TAG_DELEGATE_TABLE_ROW ((TPM_STRUCTURE_TAG) 0x001C)
+#define TPM_TAG_TRANSPORT_AUTH ((TPM_STRUCTURE_TAG) 0x001D)
+#define TPM_TAG_TRANSPORT_PUBLIC ((TPM_STRUCTURE_TAG) 0x001E)
+#define TPM_TAG_PERMANENT_FLAGS ((TPM_STRUCTURE_TAG) 0x001F)
+#define TPM_TAG_STCLEAR_FLAGS ((TPM_STRUCTURE_TAG) 0x0020)
+#define TPM_TAG_STANY_FLAGS ((TPM_STRUCTURE_TAG) 0x0021)
+#define TPM_TAG_PERMANENT_DATA ((TPM_STRUCTURE_TAG) 0x0022)
+#define TPM_TAG_STCLEAR_DATA ((TPM_STRUCTURE_TAG) 0x0023)
+#define TPM_TAG_STANY_DATA ((TPM_STRUCTURE_TAG) 0x0024)
+#define TPM_TAG_FAMILY_TABLE_ENTRY ((TPM_STRUCTURE_TAG) 0x0025)
+#define TPM_TAG_DELEGATE_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0026)
+#define TPM_TAG_DELG_KEY_BLOB ((TPM_STRUCTURE_TAG) 0x0027)
+#define TPM_TAG_KEY12 ((TPM_STRUCTURE_TAG) 0x0028)
+#define TPM_TAG_CERTIFY_INFO2 ((TPM_STRUCTURE_TAG) 0x0029)
+#define TPM_TAG_DELEGATE_OWNER_BLOB ((TPM_STRUCTURE_TAG) 0x002A)
+#define TPM_TAG_EK_BLOB_ACTIVATE ((TPM_STRUCTURE_TAG) 0x002B)
+#define TPM_TAG_DAA_BLOB ((TPM_STRUCTURE_TAG) 0x002C)
+#define TPM_TAG_DAA_CONTEXT ((TPM_STRUCTURE_TAG) 0x002D)
+#define TPM_TAG_DAA_ENFORCE ((TPM_STRUCTURE_TAG) 0x002E)
+#define TPM_TAG_DAA_ISSUER ((TPM_STRUCTURE_TAG) 0x002F)
+#define TPM_TAG_CAP_VERSION_INFO ((TPM_STRUCTURE_TAG) 0x0030)
+#define TPM_TAG_DAA_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0031)
+#define TPM_TAG_DAA_TPM ((TPM_STRUCTURE_TAG) 0x0032)
+#define TPM_TAG_CMK_MIGAUTH ((TPM_STRUCTURE_TAG) 0x0033)
+#define TPM_TAG_CMK_SIGTICKET ((TPM_STRUCTURE_TAG) 0x0034)
+#define TPM_TAG_CMK_MA_APPROVAL ((TPM_STRUCTURE_TAG) 0x0035)
+#define TPM_TAG_QUOTE_INFO2 ((TPM_STRUCTURE_TAG) 0x0036)
+#define TPM_TAG_DA_INFO ((TPM_STRUCTURE_TAG) 0x0037)
+#define TPM_TAG_DA_LIMITED ((TPM_STRUCTURE_TAG) 0x0038)
+#define TPM_TAG_DA_ACTION_TYPE ((TPM_STRUCTURE_TAG) 0x0039)
//
// Part 2, section 4: TPM Types
@@ -275,69 +274,69 @@ typedef UINT32 TPM_FAMILY_OPERATION;
//
// Part 2, section 4.1: TPM_RESOURCE_TYPE
//
-#define TPM_RT_KEY ((TPM_RESOURCE_TYPE) 0x00000001) ///< The handle is a key handle and is the result of a LoadKey type operation
-#define TPM_RT_AUTH ((TPM_RESOURCE_TYPE) 0x00000002) ///< The handle is an authorization handle. Auth handles come from TPM_OIAP, TPM_OSAP and TPM_DSAP
-#define TPM_RT_HASH ((TPM_RESOURCE_TYPE) 0x00000003) ///< Reserved for hashes
-#define TPM_RT_TRANS ((TPM_RESOURCE_TYPE) 0x00000004) ///< The handle is for a transport session. Transport handles come from TPM_EstablishTransport
-#define TPM_RT_CONTEXT ((TPM_RESOURCE_TYPE) 0x00000005) ///< Resource wrapped and held outside the TPM using the context save/restore commands
-#define TPM_RT_COUNTER ((TPM_RESOURCE_TYPE) 0x00000006) ///< Reserved for counters
-#define TPM_RT_DELEGATE ((TPM_RESOURCE_TYPE) 0x00000007) ///< The handle is for a delegate row. These are the internal rows held in NV storage by the TPM
-#define TPM_RT_DAA_TPM ((TPM_RESOURCE_TYPE) 0x00000008) ///< The value is a DAA TPM specific blob
-#define TPM_RT_DAA_V0 ((TPM_RESOURCE_TYPE) 0x00000009) ///< The value is a DAA V0 parameter
-#define TPM_RT_DAA_V1 ((TPM_RESOURCE_TYPE) 0x0000000A) ///< The value is a DAA V1 parameter
+#define TPM_RT_KEY ((TPM_RESOURCE_TYPE) 0x00000001) ///< The handle is a key handle and is the result of a LoadKey type operation
+#define TPM_RT_AUTH ((TPM_RESOURCE_TYPE) 0x00000002) ///< The handle is an authorization handle. Auth handles come from TPM_OIAP, TPM_OSAP and TPM_DSAP
+#define TPM_RT_HASH ((TPM_RESOURCE_TYPE) 0x00000003) ///< Reserved for hashes
+#define TPM_RT_TRANS ((TPM_RESOURCE_TYPE) 0x00000004) ///< The handle is for a transport session. Transport handles come from TPM_EstablishTransport
+#define TPM_RT_CONTEXT ((TPM_RESOURCE_TYPE) 0x00000005) ///< Resource wrapped and held outside the TPM using the context save/restore commands
+#define TPM_RT_COUNTER ((TPM_RESOURCE_TYPE) 0x00000006) ///< Reserved for counters
+#define TPM_RT_DELEGATE ((TPM_RESOURCE_TYPE) 0x00000007) ///< The handle is for a delegate row. These are the internal rows held in NV storage by the TPM
+#define TPM_RT_DAA_TPM ((TPM_RESOURCE_TYPE) 0x00000008) ///< The value is a DAA TPM specific blob
+#define TPM_RT_DAA_V0 ((TPM_RESOURCE_TYPE) 0x00000009) ///< The value is a DAA V0 parameter
+#define TPM_RT_DAA_V1 ((TPM_RESOURCE_TYPE) 0x0000000A) ///< The value is a DAA V1 parameter
//
// Part 2, section 4.2: TPM_PAYLOAD_TYPE
//
-#define TPM_PT_ASYM ((TPM_PAYLOAD_TYPE) 0x01) ///< The entity is an asymmetric key
-#define TPM_PT_BIND ((TPM_PAYLOAD_TYPE) 0x02) ///< The entity is bound data
-#define TPM_PT_MIGRATE ((TPM_PAYLOAD_TYPE) 0x03) ///< The entity is a migration blob
-#define TPM_PT_MAINT ((TPM_PAYLOAD_TYPE) 0x04) ///< The entity is a maintenance blob
-#define TPM_PT_SEAL ((TPM_PAYLOAD_TYPE) 0x05) ///< The entity is sealed data
-#define TPM_PT_MIGRATE_RESTRICTED ((TPM_PAYLOAD_TYPE) 0x06) ///< The entity is a restricted-migration asymmetric key
-#define TPM_PT_MIGRATE_EXTERNAL ((TPM_PAYLOAD_TYPE) 0x07) ///< The entity is a external migratable key
-#define TPM_PT_CMK_MIGRATE ((TPM_PAYLOAD_TYPE) 0x08) ///< The entity is a CMK migratable blob
-#define TPM_PT_VENDOR_SPECIFIC ((TPM_PAYLOAD_TYPE) 0x80) ///< 0x80 - 0xFF Vendor specific payloads
+#define TPM_PT_ASYM ((TPM_PAYLOAD_TYPE) 0x01) ///< The entity is an asymmetric key
+#define TPM_PT_BIND ((TPM_PAYLOAD_TYPE) 0x02) ///< The entity is bound data
+#define TPM_PT_MIGRATE ((TPM_PAYLOAD_TYPE) 0x03) ///< The entity is a migration blob
+#define TPM_PT_MAINT ((TPM_PAYLOAD_TYPE) 0x04) ///< The entity is a maintenance blob
+#define TPM_PT_SEAL ((TPM_PAYLOAD_TYPE) 0x05) ///< The entity is sealed data
+#define TPM_PT_MIGRATE_RESTRICTED ((TPM_PAYLOAD_TYPE) 0x06) ///< The entity is a restricted-migration asymmetric key
+#define TPM_PT_MIGRATE_EXTERNAL ((TPM_PAYLOAD_TYPE) 0x07) ///< The entity is a external migratable key
+#define TPM_PT_CMK_MIGRATE ((TPM_PAYLOAD_TYPE) 0x08) ///< The entity is a CMK migratable blob
+#define TPM_PT_VENDOR_SPECIFIC ((TPM_PAYLOAD_TYPE) 0x80) ///< 0x80 - 0xFF Vendor specific payloads
//
// Part 2, section 4.3: TPM_ENTITY_TYPE
//
-#define TPM_ET_KEYHANDLE ((UINT16) 0x0001) ///< The entity is a keyHandle or key
-#define TPM_ET_OWNER ((UINT16) 0x0002) ///< The entity is the TPM Owner
-#define TPM_ET_DATA ((UINT16) 0x0003) ///< The entity is some data
-#define TPM_ET_SRK ((UINT16) 0x0004) ///< The entity is the SRK
-#define TPM_ET_KEY ((UINT16) 0x0005) ///< The entity is a key or keyHandle
-#define TPM_ET_REVOKE ((UINT16) 0x0006) ///< The entity is the RevokeTrust value
-#define TPM_ET_DEL_OWNER_BLOB ((UINT16) 0x0007) ///< The entity is a delegate owner blob
-#define TPM_ET_DEL_ROW ((UINT16) 0x0008) ///< The entity is a delegate row
-#define TPM_ET_DEL_KEY_BLOB ((UINT16) 0x0009) ///< The entity is a delegate key blob
-#define TPM_ET_COUNTER ((UINT16) 0x000A) ///< The entity is a counter
-#define TPM_ET_NV ((UINT16) 0x000B) ///< The entity is a NV index
-#define TPM_ET_OPERATOR ((UINT16) 0x000C) ///< The entity is the operator
-#define TPM_ET_RESERVED_HANDLE ((UINT16) 0x0040) ///< Reserved. This value avoids collisions with the handle MSB setting.
+#define TPM_ET_KEYHANDLE ((UINT16) 0x0001) ///< The entity is a keyHandle or key
+#define TPM_ET_OWNER ((UINT16) 0x0002) ///< The entity is the TPM Owner
+#define TPM_ET_DATA ((UINT16) 0x0003) ///< The entity is some data
+#define TPM_ET_SRK ((UINT16) 0x0004) ///< The entity is the SRK
+#define TPM_ET_KEY ((UINT16) 0x0005) ///< The entity is a key or keyHandle
+#define TPM_ET_REVOKE ((UINT16) 0x0006) ///< The entity is the RevokeTrust value
+#define TPM_ET_DEL_OWNER_BLOB ((UINT16) 0x0007) ///< The entity is a delegate owner blob
+#define TPM_ET_DEL_ROW ((UINT16) 0x0008) ///< The entity is a delegate row
+#define TPM_ET_DEL_KEY_BLOB ((UINT16) 0x0009) ///< The entity is a delegate key blob
+#define TPM_ET_COUNTER ((UINT16) 0x000A) ///< The entity is a counter
+#define TPM_ET_NV ((UINT16) 0x000B) ///< The entity is a NV index
+#define TPM_ET_OPERATOR ((UINT16) 0x000C) ///< The entity is the operator
+#define TPM_ET_RESERVED_HANDLE ((UINT16) 0x0040) ///< Reserved. This value avoids collisions with the handle MSB setting.
//
// TPM_ENTITY_TYPE MSB Values: The MSB is used to indicate the ADIP encryption sheme when applicable
//
-#define TPM_ET_XOR ((UINT16) 0x0000) ///< ADIP encryption scheme: XOR
-#define TPM_ET_AES128 ((UINT16) 0x0006) ///< ADIP encryption scheme: AES 128 bits
+#define TPM_ET_XOR ((UINT16) 0x0000) ///< ADIP encryption scheme: XOR
+#define TPM_ET_AES128 ((UINT16) 0x0006) ///< ADIP encryption scheme: AES 128 bits
//
// Part 2, section 4.4.1: Reserved Key Handles
//
-#define TPM_KH_SRK ((TPM_KEY_HANDLE) 0x40000000) ///< The handle points to the SRK
-#define TPM_KH_OWNER ((TPM_KEY_HANDLE) 0x40000001) ///< The handle points to the TPM Owner
-#define TPM_KH_REVOKE ((TPM_KEY_HANDLE) 0x40000002) ///< The handle points to the RevokeTrust value
-#define TPM_KH_TRANSPORT ((TPM_KEY_HANDLE) 0x40000003) ///< The handle points to the EstablishTransport static authorization
-#define TPM_KH_OPERATOR ((TPM_KEY_HANDLE) 0x40000004) ///< The handle points to the Operator auth
-#define TPM_KH_ADMIN ((TPM_KEY_HANDLE) 0x40000005) ///< The handle points to the delegation administration auth
-#define TPM_KH_EK ((TPM_KEY_HANDLE) 0x40000006) ///< The handle points to the PUBEK, only usable with TPM_OwnerReadInternalPub
+#define TPM_KH_SRK ((TPM_KEY_HANDLE) 0x40000000) ///< The handle points to the SRK
+#define TPM_KH_OWNER ((TPM_KEY_HANDLE) 0x40000001) ///< The handle points to the TPM Owner
+#define TPM_KH_REVOKE ((TPM_KEY_HANDLE) 0x40000002) ///< The handle points to the RevokeTrust value
+#define TPM_KH_TRANSPORT ((TPM_KEY_HANDLE) 0x40000003) ///< The handle points to the EstablishTransport static authorization
+#define TPM_KH_OPERATOR ((TPM_KEY_HANDLE) 0x40000004) ///< The handle points to the Operator auth
+#define TPM_KH_ADMIN ((TPM_KEY_HANDLE) 0x40000005) ///< The handle points to the delegation administration auth
+#define TPM_KH_EK ((TPM_KEY_HANDLE) 0x40000006) ///< The handle points to the PUBEK, only usable with TPM_OwnerReadInternalPub
//
// Part 2, section 4.5: TPM_STARTUP_TYPE
//
-#define TPM_ST_CLEAR ((TPM_STARTUP_TYPE) 0x0001) ///< The TPM is starting up from a clean state
-#define TPM_ST_STATE ((TPM_STARTUP_TYPE) 0x0002) ///< The TPM is starting up from a saved state
-#define TPM_ST_DEACTIVATED ((TPM_STARTUP_TYPE) 0x0003) ///< The TPM is to startup and set the deactivated flag to TRUE
+#define TPM_ST_CLEAR ((TPM_STARTUP_TYPE) 0x0001) ///< The TPM is starting up from a clean state
+#define TPM_ST_STATE ((TPM_STARTUP_TYPE) 0x0002) ///< The TPM is starting up from a saved state
+#define TPM_ST_DEACTIVATED ((TPM_STARTUP_TYPE) 0x0003) ///< The TPM is to startup and set the deactivated flag to TRUE
//
// Part 2, section 4.6: TPM_STATUP_EFFECTS
@@ -347,65 +346,65 @@ typedef UINT32 TPM_FAMILY_OPERATION;
//
// Part 2, section 4.7: TPM_PROTOCOL_ID
//
-#define TPM_PID_OIAP ((TPM_PROTOCOL_ID) 0x0001) ///< The OIAP protocol.
-#define TPM_PID_OSAP ((TPM_PROTOCOL_ID) 0x0002) ///< The OSAP protocol.
-#define TPM_PID_ADIP ((TPM_PROTOCOL_ID) 0x0003) ///< The ADIP protocol.
-#define TPM_PID_ADCP ((TPM_PROTOCOL_ID) 0x0004) ///< The ADCP protocol.
-#define TPM_PID_OWNER ((TPM_PROTOCOL_ID) 0x0005) ///< The protocol for taking ownership of a TPM.
-#define TPM_PID_DSAP ((TPM_PROTOCOL_ID) 0x0006) ///< The DSAP protocol
-#define TPM_PID_TRANSPORT ((TPM_PROTOCOL_ID) 0x0007) ///< The transport protocol
+#define TPM_PID_OIAP ((TPM_PROTOCOL_ID) 0x0001) ///< The OIAP protocol.
+#define TPM_PID_OSAP ((TPM_PROTOCOL_ID) 0x0002) ///< The OSAP protocol.
+#define TPM_PID_ADIP ((TPM_PROTOCOL_ID) 0x0003) ///< The ADIP protocol.
+#define TPM_PID_ADCP ((TPM_PROTOCOL_ID) 0x0004) ///< The ADCP protocol.
+#define TPM_PID_OWNER ((TPM_PROTOCOL_ID) 0x0005) ///< The protocol for taking ownership of a TPM.
+#define TPM_PID_DSAP ((TPM_PROTOCOL_ID) 0x0006) ///< The DSAP protocol
+#define TPM_PID_TRANSPORT ((TPM_PROTOCOL_ID) 0x0007) ///< The transport protocol
//
// Part 2, section 4.8: TPM_ALGORITHM_ID
// The TPM MUST support the algorithms TPM_ALG_RSA, TPM_ALG_SHA, TPM_ALG_HMAC,
// TPM_ALG_MGF1
//
-#define TPM_ALG_RSA ((TPM_ALGORITHM_ID) 0x00000001) ///< The RSA algorithm.
-#define TPM_ALG_DES ((TPM_ALGORITHM_ID) 0x00000002) ///< The DES algorithm
-#define TPM_ALG_3DES ((TPM_ALGORITHM_ID) 0x00000003) ///< The 3DES algorithm in EDE mode
-#define TPM_ALG_SHA ((TPM_ALGORITHM_ID) 0x00000004) ///< The SHA1 algorithm
-#define TPM_ALG_HMAC ((TPM_ALGORITHM_ID) 0x00000005) ///< The RFC 2104 HMAC algorithm
-#define TPM_ALG_AES128 ((TPM_ALGORITHM_ID) 0x00000006) ///< The AES algorithm, key size 128
-#define TPM_ALG_MGF1 ((TPM_ALGORITHM_ID) 0x00000007) ///< The XOR algorithm using MGF1 to create a string the size of the encrypted block
-#define TPM_ALG_AES192 ((TPM_ALGORITHM_ID) 0x00000008) ///< AES, key size 192
-#define TPM_ALG_AES256 ((TPM_ALGORITHM_ID) 0x00000009) ///< AES, key size 256
-#define TPM_ALG_XOR ((TPM_ALGORITHM_ID) 0x0000000A) ///< XOR using the rolling nonces
+#define TPM_ALG_RSA ((TPM_ALGORITHM_ID) 0x00000001) ///< The RSA algorithm.
+#define TPM_ALG_DES ((TPM_ALGORITHM_ID) 0x00000002) ///< The DES algorithm
+#define TPM_ALG_3DES ((TPM_ALGORITHM_ID) 0x00000003) ///< The 3DES algorithm in EDE mode
+#define TPM_ALG_SHA ((TPM_ALGORITHM_ID) 0x00000004) ///< The SHA1 algorithm
+#define TPM_ALG_HMAC ((TPM_ALGORITHM_ID) 0x00000005) ///< The RFC 2104 HMAC algorithm
+#define TPM_ALG_AES128 ((TPM_ALGORITHM_ID) 0x00000006) ///< The AES algorithm, key size 128
+#define TPM_ALG_MGF1 ((TPM_ALGORITHM_ID) 0x00000007) ///< The XOR algorithm using MGF1 to create a string the size of the encrypted block
+#define TPM_ALG_AES192 ((TPM_ALGORITHM_ID) 0x00000008) ///< AES, key size 192
+#define TPM_ALG_AES256 ((TPM_ALGORITHM_ID) 0x00000009) ///< AES, key size 256
+#define TPM_ALG_XOR ((TPM_ALGORITHM_ID) 0x0000000A) ///< XOR using the rolling nonces
//
// Part 2, section 4.9: TPM_PHYSICAL_PRESENCE
//
-#define TPM_PHYSICAL_PRESENCE_HW_DISABLE ((TPM_PHYSICAL_PRESENCE) 0x0200) ///< Sets the physicalPresenceHWEnable to FALSE
-#define TPM_PHYSICAL_PRESENCE_CMD_DISABLE ((TPM_PHYSICAL_PRESENCE) 0x0100) ///< Sets the physicalPresenceCMDEnable to FALSE
-#define TPM_PHYSICAL_PRESENCE_LIFETIME_LOCK ((TPM_PHYSICAL_PRESENCE) 0x0080) ///< Sets the physicalPresenceLifetimeLock to TRUE
-#define TPM_PHYSICAL_PRESENCE_HW_ENABLE ((TPM_PHYSICAL_PRESENCE) 0x0040) ///< Sets the physicalPresenceHWEnable to TRUE
-#define TPM_PHYSICAL_PRESENCE_CMD_ENABLE ((TPM_PHYSICAL_PRESENCE) 0x0020) ///< Sets the physicalPresenceCMDEnable to TRUE
-#define TPM_PHYSICAL_PRESENCE_NOTPRESENT ((TPM_PHYSICAL_PRESENCE) 0x0010) ///< Sets PhysicalPresence = FALSE
-#define TPM_PHYSICAL_PRESENCE_PRESENT ((TPM_PHYSICAL_PRESENCE) 0x0008) ///< Sets PhysicalPresence = TRUE
-#define TPM_PHYSICAL_PRESENCE_LOCK ((TPM_PHYSICAL_PRESENCE) 0x0004) ///< Sets PhysicalPresenceLock = TRUE
+#define TPM_PHYSICAL_PRESENCE_HW_DISABLE ((TPM_PHYSICAL_PRESENCE) 0x0200) ///< Sets the physicalPresenceHWEnable to FALSE
+#define TPM_PHYSICAL_PRESENCE_CMD_DISABLE ((TPM_PHYSICAL_PRESENCE) 0x0100) ///< Sets the physicalPresenceCMDEnable to FALSE
+#define TPM_PHYSICAL_PRESENCE_LIFETIME_LOCK ((TPM_PHYSICAL_PRESENCE) 0x0080) ///< Sets the physicalPresenceLifetimeLock to TRUE
+#define TPM_PHYSICAL_PRESENCE_HW_ENABLE ((TPM_PHYSICAL_PRESENCE) 0x0040) ///< Sets the physicalPresenceHWEnable to TRUE
+#define TPM_PHYSICAL_PRESENCE_CMD_ENABLE ((TPM_PHYSICAL_PRESENCE) 0x0020) ///< Sets the physicalPresenceCMDEnable to TRUE
+#define TPM_PHYSICAL_PRESENCE_NOTPRESENT ((TPM_PHYSICAL_PRESENCE) 0x0010) ///< Sets PhysicalPresence = FALSE
+#define TPM_PHYSICAL_PRESENCE_PRESENT ((TPM_PHYSICAL_PRESENCE) 0x0008) ///< Sets PhysicalPresence = TRUE
+#define TPM_PHYSICAL_PRESENCE_LOCK ((TPM_PHYSICAL_PRESENCE) 0x0004) ///< Sets PhysicalPresenceLock = TRUE
//
// Part 2, section 4.10: TPM_MIGRATE_SCHEME
//
-#define TPM_MS_MIGRATE ((TPM_MIGRATE_SCHEME) 0x0001) ///< A public key that can be used with all TPM migration commands other than 'ReWrap' mode.
-#define TPM_MS_REWRAP ((TPM_MIGRATE_SCHEME) 0x0002) ///< A public key that can be used for the ReWrap mode of TPM_CreateMigrationBlob.
-#define TPM_MS_MAINT ((TPM_MIGRATE_SCHEME) 0x0003) ///< A public key that can be used for the Maintenance commands
-#define TPM_MS_RESTRICT_MIGRATE ((TPM_MIGRATE_SCHEME) 0x0004) ///< The key is to be migrated to a Migration Authority.
-#define TPM_MS_RESTRICT_APPROVE_DOUBLE ((TPM_MIGRATE_SCHEME) 0x0005) ///< The key is to be migrated to an entity approved by a Migration Authority using double wrapping
+#define TPM_MS_MIGRATE ((TPM_MIGRATE_SCHEME) 0x0001) ///< A public key that can be used with all TPM migration commands other than 'ReWrap' mode.
+#define TPM_MS_REWRAP ((TPM_MIGRATE_SCHEME) 0x0002) ///< A public key that can be used for the ReWrap mode of TPM_CreateMigrationBlob.
+#define TPM_MS_MAINT ((TPM_MIGRATE_SCHEME) 0x0003) ///< A public key that can be used for the Maintenance commands
+#define TPM_MS_RESTRICT_MIGRATE ((TPM_MIGRATE_SCHEME) 0x0004) ///< The key is to be migrated to a Migration Authority.
+#define TPM_MS_RESTRICT_APPROVE_DOUBLE ((TPM_MIGRATE_SCHEME) 0x0005) ///< The key is to be migrated to an entity approved by a Migration Authority using double wrapping
//
// Part 2, section 4.11: TPM_EK_TYPE
//
-#define TPM_EK_TYPE_ACTIVATE ((TPM_EK_TYPE) 0x0001) ///< The blob MUST be TPM_EK_BLOB_ACTIVATE
-#define TPM_EK_TYPE_AUTH ((TPM_EK_TYPE) 0x0002) ///< The blob MUST be TPM_EK_BLOB_AUTH
+#define TPM_EK_TYPE_ACTIVATE ((TPM_EK_TYPE) 0x0001) ///< The blob MUST be TPM_EK_BLOB_ACTIVATE
+#define TPM_EK_TYPE_AUTH ((TPM_EK_TYPE) 0x0002) ///< The blob MUST be TPM_EK_BLOB_AUTH
//
// Part 2, section 4.12: TPM_PLATFORM_SPECIFIC
//
-#define TPM_PS_PC_11 ((TPM_PLATFORM_SPECIFIC) 0x0001) ///< PC Specific version 1.1
-#define TPM_PS_PC_12 ((TPM_PLATFORM_SPECIFIC) 0x0002) ///< PC Specific version 1.2
-#define TPM_PS_PDA_12 ((TPM_PLATFORM_SPECIFIC) 0x0003) ///< PDA Specific version 1.2
-#define TPM_PS_Server_12 ((TPM_PLATFORM_SPECIFIC) 0x0004) ///< Server Specific version 1.2
-#define TPM_PS_Mobile_12 ((TPM_PLATFORM_SPECIFIC) 0x0005) ///< Mobil Specific version 1.2
+#define TPM_PS_PC_11 ((TPM_PLATFORM_SPECIFIC) 0x0001) ///< PC Specific version 1.1
+#define TPM_PS_PC_12 ((TPM_PLATFORM_SPECIFIC) 0x0002) ///< PC Specific version 1.2
+#define TPM_PS_PDA_12 ((TPM_PLATFORM_SPECIFIC) 0x0003) ///< PDA Specific version 1.2
+#define TPM_PS_Server_12 ((TPM_PLATFORM_SPECIFIC) 0x0004) ///< Server Specific version 1.2
+#define TPM_PS_Mobile_12 ((TPM_PLATFORM_SPECIFIC) 0x0005) ///< Mobil Specific version 1.2
//
// Part 2, section 5: Basic Structures
@@ -415,72 +414,71 @@ typedef UINT32 TPM_FAMILY_OPERATION;
/// Part 2, section 5.1: TPM_STRUCT_VER
///
typedef struct tdTPM_STRUCT_VER {
- UINT8 major;
- UINT8 minor;
- UINT8 revMajor;
- UINT8 revMinor;
+ UINT8 major;
+ UINT8 minor;
+ UINT8 revMajor;
+ UINT8 revMinor;
} TPM_STRUCT_VER;
///
/// Part 2, section 5.3: TPM_VERSION
///
typedef struct tdTPM_VERSION {
- TPM_VERSION_BYTE major;
- TPM_VERSION_BYTE minor;
- UINT8 revMajor;
- UINT8 revMinor;
+ TPM_VERSION_BYTE major;
+ TPM_VERSION_BYTE minor;
+ UINT8 revMajor;
+ UINT8 revMinor;
} TPM_VERSION;
-
-#define TPM_SHA1_160_HASH_LEN 0x14
-#define TPM_SHA1BASED_NONCE_LEN TPM_SHA1_160_HASH_LEN
+#define TPM_SHA1_160_HASH_LEN 0x14
+#define TPM_SHA1BASED_NONCE_LEN TPM_SHA1_160_HASH_LEN
///
/// Part 2, section 5.4: TPM_DIGEST
///
-typedef struct tdTPM_DIGEST{
- UINT8 digest[TPM_SHA1_160_HASH_LEN];
+typedef struct tdTPM_DIGEST {
+ UINT8 digest[TPM_SHA1_160_HASH_LEN];
} TPM_DIGEST;
///
/// This SHALL be the digest of the chosen identityLabel and privacyCA for a new TPM identity
///
-typedef TPM_DIGEST TPM_CHOSENID_HASH;
+typedef TPM_DIGEST TPM_CHOSENID_HASH;
///
/// This SHALL be the hash of a list of PCR indexes and PCR values that a key or data is bound to
///
-typedef TPM_DIGEST TPM_COMPOSITE_HASH;
+typedef TPM_DIGEST TPM_COMPOSITE_HASH;
///
/// This SHALL be the value of a DIR register
///
-typedef TPM_DIGEST TPM_DIRVALUE;
+typedef TPM_DIGEST TPM_DIRVALUE;
-typedef TPM_DIGEST TPM_HMAC;
+typedef TPM_DIGEST TPM_HMAC;
///
/// The value inside of the PCR
///
-typedef TPM_DIGEST TPM_PCRVALUE;
+typedef TPM_DIGEST TPM_PCRVALUE;
///
/// This SHALL be the value of the current internal audit state
///
-typedef TPM_DIGEST TPM_AUDITDIGEST;
+typedef TPM_DIGEST TPM_AUDITDIGEST;
///
/// Part 2, section 5.5: TPM_NONCE
///
-typedef struct tdTPM_NONCE{
- UINT8 nonce[20];
+typedef struct tdTPM_NONCE {
+ UINT8 nonce[20];
} TPM_NONCE;
///
/// This SHALL be a random value generated by a TPM immediately after the EK is installed
/// in that TPM, whenever an EK is installed in that TPM
///
-typedef TPM_NONCE TPM_DAA_TPM_SEED;
+typedef TPM_NONCE TPM_DAA_TPM_SEED;
///
/// This SHALL be a random value
///
-typedef TPM_NONCE TPM_DAA_CONTEXT_SEED;
+typedef TPM_NONCE TPM_DAA_CONTEXT_SEED;
//
// Part 2, section 5.6: TPM_AUTHDATA
@@ -489,25 +487,25 @@ typedef TPM_NONCE TPM_DAA_CONTEXT_SEED;
/// The AuthData data is the information that is saved or passed to provide proof of ownership
/// 296 of an entity
///
-typedef UINT8 tdTPM_AUTHDATA[20];
+typedef UINT8 tdTPM_AUTHDATA[20];
-typedef tdTPM_AUTHDATA TPM_AUTHDATA;
+typedef tdTPM_AUTHDATA TPM_AUTHDATA;
///
/// A secret plaintext value used in the authorization process
///
-typedef TPM_AUTHDATA TPM_SECRET;
+typedef TPM_AUTHDATA TPM_SECRET;
///
/// A ciphertext (encrypted) version of AuthData data. The encryption mechanism depends on the context
///
-typedef TPM_AUTHDATA TPM_ENCAUTH;
+typedef TPM_AUTHDATA TPM_ENCAUTH;
///
/// Part 2, section 5.7: TPM_KEY_HANDLE_LIST
/// Size of handle is loaded * sizeof(TPM_KEY_HANDLE)
///
typedef struct tdTPM_KEY_HANDLE_LIST {
- UINT16 loaded;
- TPM_KEY_HANDLE handle[1];
+ UINT16 loaded;
+ TPM_KEY_HANDLE handle[1];
} TPM_KEY_HANDLE_LIST;
//
@@ -518,27 +516,27 @@ typedef struct tdTPM_KEY_HANDLE_LIST {
/// used for signing operations, only. This means that it MUST be a leaf of the
/// Protected Storage key hierarchy.
///
-#define TPM_KEY_SIGNING ((UINT16) 0x0010)
+#define TPM_KEY_SIGNING ((UINT16) 0x0010)
///
/// TPM_KEY_STORAGE SHALL indicate a storage key. The key SHALL be used to wrap
/// and unwrap other keys in the Protected Storage hierarchy
///
-#define TPM_KEY_STORAGE ((UINT16) 0x0011)
+#define TPM_KEY_STORAGE ((UINT16) 0x0011)
///
/// TPM_KEY_IDENTITY SHALL indicate an identity key. The key SHALL be used for
/// operations that require a TPM identity, only.
///
-#define TPM_KEY_IDENTITY ((UINT16) 0x0012)
+#define TPM_KEY_IDENTITY ((UINT16) 0x0012)
///
/// TPM_KEY_AUTHCHANGE SHALL indicate an ephemeral key that is in use during
/// the ChangeAuthAsym process, only.
///
-#define TPM_KEY_AUTHCHANGE ((UINT16) 0x0013)
+#define TPM_KEY_AUTHCHANGE ((UINT16) 0x0013)
///
/// TPM_KEY_BIND SHALL indicate a key that can be used for TPM_Bind and
/// TPM_Unbind operations only.
///
-#define TPM_KEY_BIND ((UINT16) 0x0014)
+#define TPM_KEY_BIND ((UINT16) 0x0014)
///
/// TPM_KEY_LEGACY SHALL indicate a key that can perform signing and binding
/// operations. The key MAY be used for both signing and binding operations.
@@ -547,11 +545,11 @@ typedef struct tdTPM_KEY_HANDLE_LIST {
/// key type is not recommended TPM_KEY_MIGRATE 0x0016 This SHALL indicate a
/// key in use for TPM_MigrateKey
///
-#define TPM_KEY_LEGACY ((UINT16) 0x0015)
+#define TPM_KEY_LEGACY ((UINT16) 0x0015)
///
/// TPM_KEY_MIGRAGE SHALL indicate a key in use for TPM_MigrateKey
///
-#define TPM_KEY_MIGRATE ((UINT16) 0x0016)
+#define TPM_KEY_MIGRATE ((UINT16) 0x0016)
//
// Part 2, section 5.8.1: Mandatory Key Usage Schemes
@@ -572,27 +570,27 @@ typedef struct tdTPM_KEY_HANDLE_LIST {
//
// Part 2, section 5.9: TPM_AUTH_DATA_USAGE values
//
-#define TPM_AUTH_NEVER ((TPM_AUTH_DATA_USAGE) 0x00)
-#define TPM_AUTH_ALWAYS ((TPM_AUTH_DATA_USAGE) 0x01)
-#define TPM_AUTH_PRIV_USE_ONLY ((TPM_AUTH_DATA_USAGE) 0x03)
+#define TPM_AUTH_NEVER ((TPM_AUTH_DATA_USAGE) 0x00)
+#define TPM_AUTH_ALWAYS ((TPM_AUTH_DATA_USAGE) 0x01)
+#define TPM_AUTH_PRIV_USE_ONLY ((TPM_AUTH_DATA_USAGE) 0x03)
///
/// Part 2, section 5.10: TPM_KEY_FLAGS
///
typedef enum tdTPM_KEY_FLAGS {
- redirection = 0x00000001,
- migratable = 0x00000002,
- isVolatile = 0x00000004,
- pcrIgnoredOnRead = 0x00000008,
- migrateAuthority = 0x00000010
+ redirection = 0x00000001,
+ migratable = 0x00000002,
+ isVolatile = 0x00000004,
+ pcrIgnoredOnRead = 0x00000008,
+ migrateAuthority = 0x00000010
} TPM_KEY_FLAGS_BITS;
///
/// Part 2, section 5.11: TPM_CHANGEAUTH_VALIDATE
///
typedef struct tdTPM_CHANGEAUTH_VALIDATE {
- TPM_SECRET newAuthSecret;
- TPM_NONCE n1;
+ TPM_SECRET newAuthSecret;
+ TPM_NONCE n1;
} TPM_CHANGEAUTH_VALIDATE;
///
@@ -603,45 +601,45 @@ typedef struct tdTPM_CHANGEAUTH_VALIDATE {
/// [size_is(parmSize)] BYTE* parms;
///
typedef struct tdTPM_KEY_PARMS {
- TPM_ALGORITHM_ID algorithmID;
- TPM_ENC_SCHEME encScheme;
- TPM_SIG_SCHEME sigScheme;
- UINT32 parmSize;
- UINT8 *parms;
+ TPM_ALGORITHM_ID algorithmID;
+ TPM_ENC_SCHEME encScheme;
+ TPM_SIG_SCHEME sigScheme;
+ UINT32 parmSize;
+ UINT8 *parms;
} TPM_KEY_PARMS;
///
/// Part 2, section 10.4: TPM_STORE_PUBKEY
///
typedef struct tdTPM_STORE_PUBKEY {
- UINT32 keyLength;
- UINT8 key[1];
+ UINT32 keyLength;
+ UINT8 key[1];
} TPM_STORE_PUBKEY;
///
/// Part 2, section 10.5: TPM_PUBKEY
///
-typedef struct tdTPM_PUBKEY{
- TPM_KEY_PARMS algorithmParms;
- TPM_STORE_PUBKEY pubKey;
+typedef struct tdTPM_PUBKEY {
+ TPM_KEY_PARMS algorithmParms;
+ TPM_STORE_PUBKEY pubKey;
} TPM_PUBKEY;
///
/// Part 2, section 5.12: TPM_MIGRATIONKEYAUTH
///
-typedef struct tdTPM_MIGRATIONKEYAUTH{
- TPM_PUBKEY migrationKey;
- TPM_MIGRATE_SCHEME migrationScheme;
- TPM_DIGEST digest;
+typedef struct tdTPM_MIGRATIONKEYAUTH {
+ TPM_PUBKEY migrationKey;
+ TPM_MIGRATE_SCHEME migrationScheme;
+ TPM_DIGEST digest;
} TPM_MIGRATIONKEYAUTH;
///
/// Part 2, section 5.13: TPM_COUNTER_VALUE
///
-typedef struct tdTPM_COUNTER_VALUE{
- TPM_STRUCTURE_TAG tag;
- UINT8 label[4];
- TPM_ACTUAL_COUNT counter;
+typedef struct tdTPM_COUNTER_VALUE {
+ TPM_STRUCTURE_TAG tag;
+ UINT8 label[4];
+ TPM_ACTUAL_COUNT counter;
} TPM_COUNTER_VALUE;
///
@@ -649,11 +647,11 @@ typedef struct tdTPM_COUNTER_VALUE{
/// Size of data indicated by dataLen
///
typedef struct tdTPM_SIGN_INFO {
- TPM_STRUCTURE_TAG tag;
- UINT8 fixed[4];
- TPM_NONCE replay;
- UINT32 dataLen;
- UINT8 *data;
+ TPM_STRUCTURE_TAG tag;
+ UINT8 fixed[4];
+ TPM_NONCE replay;
+ UINT32 dataLen;
+ UINT8 *data;
} TPM_SIGN_INFO;
///
@@ -661,163 +659,163 @@ typedef struct tdTPM_SIGN_INFO {
/// Number of migAuthDigest indicated by MSAlist
///
typedef struct tdTPM_MSA_COMPOSITE {
- UINT32 MSAlist;
- TPM_DIGEST migAuthDigest[1];
+ UINT32 MSAlist;
+ TPM_DIGEST migAuthDigest[1];
} TPM_MSA_COMPOSITE;
///
/// Part 2, section 5.16: TPM_CMK_AUTH
///
-typedef struct tdTPM_CMK_AUTH{
- TPM_DIGEST migrationAuthorityDigest;
- TPM_DIGEST destinationKeyDigest;
- TPM_DIGEST sourceKeyDigest;
+typedef struct tdTPM_CMK_AUTH {
+ TPM_DIGEST migrationAuthorityDigest;
+ TPM_DIGEST destinationKeyDigest;
+ TPM_DIGEST sourceKeyDigest;
} TPM_CMK_AUTH;
//
// Part 2, section 5.17: TPM_CMK_DELEGATE
//
-#define TPM_CMK_DELEGATE_SIGNING ((TPM_CMK_DELEGATE) BIT31)
-#define TPM_CMK_DELEGATE_STORAGE ((TPM_CMK_DELEGATE) BIT30)
-#define TPM_CMK_DELEGATE_BIND ((TPM_CMK_DELEGATE) BIT29)
-#define TPM_CMK_DELEGATE_LEGACY ((TPM_CMK_DELEGATE) BIT28)
-#define TPM_CMK_DELEGATE_MIGRATE ((TPM_CMK_DELEGATE) BIT27)
+#define TPM_CMK_DELEGATE_SIGNING ((TPM_CMK_DELEGATE) BIT31)
+#define TPM_CMK_DELEGATE_STORAGE ((TPM_CMK_DELEGATE) BIT30)
+#define TPM_CMK_DELEGATE_BIND ((TPM_CMK_DELEGATE) BIT29)
+#define TPM_CMK_DELEGATE_LEGACY ((TPM_CMK_DELEGATE) BIT28)
+#define TPM_CMK_DELEGATE_MIGRATE ((TPM_CMK_DELEGATE) BIT27)
///
/// Part 2, section 5.18: TPM_SELECT_SIZE
///
typedef struct tdTPM_SELECT_SIZE {
- UINT8 major;
- UINT8 minor;
- UINT16 reqSize;
+ UINT8 major;
+ UINT8 minor;
+ UINT16 reqSize;
} TPM_SELECT_SIZE;
///
/// Part 2, section 5,19: TPM_CMK_MIGAUTH
///
-typedef struct tdTPM_CMK_MIGAUTH{
- TPM_STRUCTURE_TAG tag;
- TPM_DIGEST msaDigest;
- TPM_DIGEST pubKeyDigest;
+typedef struct tdTPM_CMK_MIGAUTH {
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST msaDigest;
+ TPM_DIGEST pubKeyDigest;
} TPM_CMK_MIGAUTH;
///
/// Part 2, section 5.20: TPM_CMK_SIGTICKET
///
-typedef struct tdTPM_CMK_SIGTICKET{
- TPM_STRUCTURE_TAG tag;
- TPM_DIGEST verKeyDigest;
- TPM_DIGEST signedData;
+typedef struct tdTPM_CMK_SIGTICKET {
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST verKeyDigest;
+ TPM_DIGEST signedData;
} TPM_CMK_SIGTICKET;
///
/// Part 2, section 5.21: TPM_CMK_MA_APPROVAL
///
-typedef struct tdTPM_CMK_MA_APPROVAL{
- TPM_STRUCTURE_TAG tag;
- TPM_DIGEST migrationAuthorityDigest;
+typedef struct tdTPM_CMK_MA_APPROVAL {
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST migrationAuthorityDigest;
} TPM_CMK_MA_APPROVAL;
//
// Part 2, section 6: Command Tags
//
-#define TPM_TAG_RQU_COMMAND ((TPM_STRUCTURE_TAG) 0x00C1)
-#define TPM_TAG_RQU_AUTH1_COMMAND ((TPM_STRUCTURE_TAG) 0x00C2)
-#define TPM_TAG_RQU_AUTH2_COMMAND ((TPM_STRUCTURE_TAG) 0x00C3)
-#define TPM_TAG_RSP_COMMAND ((TPM_STRUCTURE_TAG) 0x00C4)
-#define TPM_TAG_RSP_AUTH1_COMMAND ((TPM_STRUCTURE_TAG) 0x00C5)
-#define TPM_TAG_RSP_AUTH2_COMMAND ((TPM_STRUCTURE_TAG) 0x00C6)
+#define TPM_TAG_RQU_COMMAND ((TPM_STRUCTURE_TAG) 0x00C1)
+#define TPM_TAG_RQU_AUTH1_COMMAND ((TPM_STRUCTURE_TAG) 0x00C2)
+#define TPM_TAG_RQU_AUTH2_COMMAND ((TPM_STRUCTURE_TAG) 0x00C3)
+#define TPM_TAG_RSP_COMMAND ((TPM_STRUCTURE_TAG) 0x00C4)
+#define TPM_TAG_RSP_AUTH1_COMMAND ((TPM_STRUCTURE_TAG) 0x00C5)
+#define TPM_TAG_RSP_AUTH2_COMMAND ((TPM_STRUCTURE_TAG) 0x00C6)
///
/// Part 2, section 7.1: TPM_PERMANENT_FLAGS
///
-typedef struct tdTPM_PERMANENT_FLAGS{
- TPM_STRUCTURE_TAG tag;
- BOOLEAN disable;
- BOOLEAN ownership;
- BOOLEAN deactivated;
- BOOLEAN readPubek;
- BOOLEAN disableOwnerClear;
- BOOLEAN allowMaintenance;
- BOOLEAN physicalPresenceLifetimeLock;
- BOOLEAN physicalPresenceHWEnable;
- BOOLEAN physicalPresenceCMDEnable;
- BOOLEAN CEKPUsed;
- BOOLEAN TPMpost;
- BOOLEAN TPMpostLock;
- BOOLEAN FIPS;
+typedef struct tdTPM_PERMANENT_FLAGS {
+ TPM_STRUCTURE_TAG tag;
+ BOOLEAN disable;
+ BOOLEAN ownership;
+ BOOLEAN deactivated;
+ BOOLEAN readPubek;
+ BOOLEAN disableOwnerClear;
+ BOOLEAN allowMaintenance;
+ BOOLEAN physicalPresenceLifetimeLock;
+ BOOLEAN physicalPresenceHWEnable;
+ BOOLEAN physicalPresenceCMDEnable;
+ BOOLEAN CEKPUsed;
+ BOOLEAN TPMpost;
+ BOOLEAN TPMpostLock;
+ BOOLEAN FIPS;
BOOLEAN operator;
BOOLEAN enableRevokeEK;
- BOOLEAN nvLocked;
- BOOLEAN readSRKPub;
- BOOLEAN tpmEstablished;
- BOOLEAN maintenanceDone;
- BOOLEAN disableFullDALogicInfo;
+ BOOLEAN nvLocked;
+ BOOLEAN readSRKPub;
+ BOOLEAN tpmEstablished;
+ BOOLEAN maintenanceDone;
+ BOOLEAN disableFullDALogicInfo;
} TPM_PERMANENT_FLAGS;
//
// Part 2, section 7.1.1: Flag Restrictions (of TPM_PERMANENT_FLAGS)
//
-#define TPM_PF_DISABLE ((TPM_CAPABILITY_AREA) 1)
-#define TPM_PF_OWNERSHIP ((TPM_CAPABILITY_AREA) 2)
-#define TPM_PF_DEACTIVATED ((TPM_CAPABILITY_AREA) 3)
-#define TPM_PF_READPUBEK ((TPM_CAPABILITY_AREA) 4)
-#define TPM_PF_DISABLEOWNERCLEAR ((TPM_CAPABILITY_AREA) 5)
-#define TPM_PF_ALLOWMAINTENANCE ((TPM_CAPABILITY_AREA) 6)
-#define TPM_PF_PHYSICALPRESENCELIFETIMELOCK ((TPM_CAPABILITY_AREA) 7)
-#define TPM_PF_PHYSICALPRESENCEHWENABLE ((TPM_CAPABILITY_AREA) 8)
-#define TPM_PF_PHYSICALPRESENCECMDENABLE ((TPM_CAPABILITY_AREA) 9)
-#define TPM_PF_CEKPUSED ((TPM_CAPABILITY_AREA) 10)
-#define TPM_PF_TPMPOST ((TPM_CAPABILITY_AREA) 11)
-#define TPM_PF_TPMPOSTLOCK ((TPM_CAPABILITY_AREA) 12)
-#define TPM_PF_FIPS ((TPM_CAPABILITY_AREA) 13)
-#define TPM_PF_OPERATOR ((TPM_CAPABILITY_AREA) 14)
-#define TPM_PF_ENABLEREVOKEEK ((TPM_CAPABILITY_AREA) 15)
-#define TPM_PF_NV_LOCKED ((TPM_CAPABILITY_AREA) 16)
-#define TPM_PF_READSRKPUB ((TPM_CAPABILITY_AREA) 17)
-#define TPM_PF_TPMESTABLISHED ((TPM_CAPABILITY_AREA) 18)
-#define TPM_PF_MAINTENANCEDONE ((TPM_CAPABILITY_AREA) 19)
-#define TPM_PF_DISABLEFULLDALOGICINFO ((TPM_CAPABILITY_AREA) 20)
+#define TPM_PF_DISABLE ((TPM_CAPABILITY_AREA) 1)
+#define TPM_PF_OWNERSHIP ((TPM_CAPABILITY_AREA) 2)
+#define TPM_PF_DEACTIVATED ((TPM_CAPABILITY_AREA) 3)
+#define TPM_PF_READPUBEK ((TPM_CAPABILITY_AREA) 4)
+#define TPM_PF_DISABLEOWNERCLEAR ((TPM_CAPABILITY_AREA) 5)
+#define TPM_PF_ALLOWMAINTENANCE ((TPM_CAPABILITY_AREA) 6)
+#define TPM_PF_PHYSICALPRESENCELIFETIMELOCK ((TPM_CAPABILITY_AREA) 7)
+#define TPM_PF_PHYSICALPRESENCEHWENABLE ((TPM_CAPABILITY_AREA) 8)
+#define TPM_PF_PHYSICALPRESENCECMDENABLE ((TPM_CAPABILITY_AREA) 9)
+#define TPM_PF_CEKPUSED ((TPM_CAPABILITY_AREA) 10)
+#define TPM_PF_TPMPOST ((TPM_CAPABILITY_AREA) 11)
+#define TPM_PF_TPMPOSTLOCK ((TPM_CAPABILITY_AREA) 12)
+#define TPM_PF_FIPS ((TPM_CAPABILITY_AREA) 13)
+#define TPM_PF_OPERATOR ((TPM_CAPABILITY_AREA) 14)
+#define TPM_PF_ENABLEREVOKEEK ((TPM_CAPABILITY_AREA) 15)
+#define TPM_PF_NV_LOCKED ((TPM_CAPABILITY_AREA) 16)
+#define TPM_PF_READSRKPUB ((TPM_CAPABILITY_AREA) 17)
+#define TPM_PF_TPMESTABLISHED ((TPM_CAPABILITY_AREA) 18)
+#define TPM_PF_MAINTENANCEDONE ((TPM_CAPABILITY_AREA) 19)
+#define TPM_PF_DISABLEFULLDALOGICINFO ((TPM_CAPABILITY_AREA) 20)
///
/// Part 2, section 7.2: TPM_STCLEAR_FLAGS
///
-typedef struct tdTPM_STCLEAR_FLAGS{
- TPM_STRUCTURE_TAG tag;
- BOOLEAN deactivated;
- BOOLEAN disableForceClear;
- BOOLEAN physicalPresence;
- BOOLEAN physicalPresenceLock;
- BOOLEAN bGlobalLock;
+typedef struct tdTPM_STCLEAR_FLAGS {
+ TPM_STRUCTURE_TAG tag;
+ BOOLEAN deactivated;
+ BOOLEAN disableForceClear;
+ BOOLEAN physicalPresence;
+ BOOLEAN physicalPresenceLock;
+ BOOLEAN bGlobalLock;
} TPM_STCLEAR_FLAGS;
//
// Part 2, section 7.2.1: Flag Restrictions (of TPM_STCLEAR_FLAGS)
//
-#define TPM_SF_DEACTIVATED ((TPM_CAPABILITY_AREA) 1)
-#define TPM_SF_DISABLEFORCECLEAR ((TPM_CAPABILITY_AREA) 2)
-#define TPM_SF_PHYSICALPRESENCE ((TPM_CAPABILITY_AREA) 3)
-#define TPM_SF_PHYSICALPRESENCELOCK ((TPM_CAPABILITY_AREA) 4)
-#define TPM_SF_BGLOBALLOCK ((TPM_CAPABILITY_AREA) 5)
+#define TPM_SF_DEACTIVATED ((TPM_CAPABILITY_AREA) 1)
+#define TPM_SF_DISABLEFORCECLEAR ((TPM_CAPABILITY_AREA) 2)
+#define TPM_SF_PHYSICALPRESENCE ((TPM_CAPABILITY_AREA) 3)
+#define TPM_SF_PHYSICALPRESENCELOCK ((TPM_CAPABILITY_AREA) 4)
+#define TPM_SF_BGLOBALLOCK ((TPM_CAPABILITY_AREA) 5)
///
/// Part 2, section 7.3: TPM_STANY_FLAGS
///
-typedef struct tdTPM_STANY_FLAGS{
- TPM_STRUCTURE_TAG tag;
- BOOLEAN postInitialise;
- TPM_MODIFIER_INDICATOR localityModifier;
- BOOLEAN transportExclusive;
- BOOLEAN TOSPresent;
+typedef struct tdTPM_STANY_FLAGS {
+ TPM_STRUCTURE_TAG tag;
+ BOOLEAN postInitialise;
+ TPM_MODIFIER_INDICATOR localityModifier;
+ BOOLEAN transportExclusive;
+ BOOLEAN TOSPresent;
} TPM_STANY_FLAGS;
//
// Part 2, section 7.3.1: Flag Restrictions (of TPM_STANY_FLAGS)
//
-#define TPM_AF_POSTINITIALISE ((TPM_CAPABILITY_AREA) 1)
-#define TPM_AF_LOCALITYMODIFIER ((TPM_CAPABILITY_AREA) 2)
-#define TPM_AF_TRANSPORTEXCLUSIVE ((TPM_CAPABILITY_AREA) 3)
-#define TPM_AF_TOSPRESENT ((TPM_CAPABILITY_AREA) 4)
+#define TPM_AF_POSTINITIALISE ((TPM_CAPABILITY_AREA) 1)
+#define TPM_AF_LOCALITYMODIFIER ((TPM_CAPABILITY_AREA) 2)
+#define TPM_AF_TRANSPORTEXCLUSIVE ((TPM_CAPABILITY_AREA) 3)
+#define TPM_AF_TOSPRESENT ((TPM_CAPABILITY_AREA) 4)
//
// All those structures defined in section 7.4, 7.5, 7.6 are not normative and
@@ -825,10 +823,10 @@ typedef struct tdTPM_STANY_FLAGS{
//
// Part 2, section 7.4: TPM_PERMANENT_DATA
//
-#define TPM_MIN_COUNTERS 4 ///< the minimum number of counters is 4
-#define TPM_DELEGATE_KEY TPM_KEY
-#define TPM_NUM_PCR 16
-#define TPM_MAX_NV_WRITE_NOOWNER 64
+#define TPM_MIN_COUNTERS 4 ///< the minimum number of counters is 4
+#define TPM_DELEGATE_KEY TPM_KEY
+#define TPM_NUM_PCR 16
+#define TPM_MAX_NV_WRITE_NOOWNER 64
//
// Part 2, section 7.4.1: PERMANENT_DATA Subcap for SetCapability
@@ -863,35 +861,35 @@ typedef struct tdTPM_STANY_FLAGS{
/// Part 2, section 7.5: TPM_STCLEAR_DATA
/// available inside TPM only
///
- typedef struct tdTPM_STCLEAR_DATA{
- TPM_STRUCTURE_TAG tag;
- TPM_NONCE contextNonceKey;
- TPM_COUNT_ID countID;
- UINT32 ownerReference;
- BOOLEAN disableResetLock;
- TPM_PCRVALUE PCR[TPM_NUM_PCR];
- UINT32 deferredPhysicalPresence;
- }TPM_STCLEAR_DATA;
+typedef struct tdTPM_STCLEAR_DATA {
+ TPM_STRUCTURE_TAG tag;
+ TPM_NONCE contextNonceKey;
+ TPM_COUNT_ID countID;
+ UINT32 ownerReference;
+ BOOLEAN disableResetLock;
+ TPM_PCRVALUE PCR[TPM_NUM_PCR];
+ UINT32 deferredPhysicalPresence;
+} TPM_STCLEAR_DATA;
//
// Part 2, section 7.5.1: STCLEAR_DATA Subcap for SetCapability
//
-#define TPM_SD_CONTEXTNONCEKEY ((TPM_CAPABILITY_AREA)0x00000001)
-#define TPM_SD_COUNTID ((TPM_CAPABILITY_AREA)0x00000002)
-#define TPM_SD_OWNERREFERENCE ((TPM_CAPABILITY_AREA)0x00000003)
-#define TPM_SD_DISABLERESETLOCK ((TPM_CAPABILITY_AREA)0x00000004)
-#define TPM_SD_PCR ((TPM_CAPABILITY_AREA)0x00000005)
-#define TPM_SD_DEFERREDPHYSICALPRESENCE ((TPM_CAPABILITY_AREA)0x00000006)
+#define TPM_SD_CONTEXTNONCEKEY ((TPM_CAPABILITY_AREA)0x00000001)
+#define TPM_SD_COUNTID ((TPM_CAPABILITY_AREA)0x00000002)
+#define TPM_SD_OWNERREFERENCE ((TPM_CAPABILITY_AREA)0x00000003)
+#define TPM_SD_DISABLERESETLOCK ((TPM_CAPABILITY_AREA)0x00000004)
+#define TPM_SD_PCR ((TPM_CAPABILITY_AREA)0x00000005)
+#define TPM_SD_DEFERREDPHYSICALPRESENCE ((TPM_CAPABILITY_AREA)0x00000006)
//
// Part 2, section 7.6.1: STANY_DATA Subcap for SetCapability
//
-#define TPM_AD_CONTEXTNONCESESSION ((TPM_CAPABILITY_AREA) 1)
-#define TPM_AD_AUDITDIGEST ((TPM_CAPABILITY_AREA) 2)
-#define TPM_AD_CURRENTTICKS ((TPM_CAPABILITY_AREA) 3)
-#define TPM_AD_CONTEXTCOUNT ((TPM_CAPABILITY_AREA) 4)
-#define TPM_AD_CONTEXTLIST ((TPM_CAPABILITY_AREA) 5)
-#define TPM_AD_SESSIONS ((TPM_CAPABILITY_AREA) 6)
+#define TPM_AD_CONTEXTNONCESESSION ((TPM_CAPABILITY_AREA) 1)
+#define TPM_AD_AUDITDIGEST ((TPM_CAPABILITY_AREA) 2)
+#define TPM_AD_CURRENTTICKS ((TPM_CAPABILITY_AREA) 3)
+#define TPM_AD_CONTEXTCOUNT ((TPM_CAPABILITY_AREA) 4)
+#define TPM_AD_CONTEXTLIST ((TPM_CAPABILITY_AREA) 5)
+#define TPM_AD_SESSIONS ((TPM_CAPABILITY_AREA) 6)
//
// Part 2, section 8: PCR Structures
@@ -902,8 +900,8 @@ typedef struct tdTPM_STANY_FLAGS{
/// Size of pcrSelect[] indicated by sizeOfSelect
///
typedef struct tdTPM_PCR_SELECTION {
- UINT16 sizeOfSelect;
- UINT8 pcrSelect[1];
+ UINT16 sizeOfSelect;
+ UINT8 pcrSelect[1];
} TPM_PCR_SELECTION;
///
@@ -911,60 +909,60 @@ typedef struct tdTPM_PCR_SELECTION {
/// Size of pcrValue[] indicated by valueSize
///
typedef struct tdTPM_PCR_COMPOSITE {
- TPM_PCR_SELECTION select;
- UINT32 valueSize;
- TPM_PCRVALUE pcrValue[1];
+ TPM_PCR_SELECTION select;
+ UINT32 valueSize;
+ TPM_PCRVALUE pcrValue[1];
} TPM_PCR_COMPOSITE;
///
/// Part 2, section 8.3: TPM_PCR_INFO
///
typedef struct tdTPM_PCR_INFO {
- TPM_PCR_SELECTION pcrSelection;
- TPM_COMPOSITE_HASH digestAtRelease;
- TPM_COMPOSITE_HASH digestAtCreation;
+ TPM_PCR_SELECTION pcrSelection;
+ TPM_COMPOSITE_HASH digestAtRelease;
+ TPM_COMPOSITE_HASH digestAtCreation;
} TPM_PCR_INFO;
///
/// Part 2, section 8.6: TPM_LOCALITY_SELECTION
///
-typedef UINT8 TPM_LOCALITY_SELECTION;
+typedef UINT8 TPM_LOCALITY_SELECTION;
-#define TPM_LOC_FOUR ((UINT8) 0x10)
-#define TPM_LOC_THREE ((UINT8) 0x08)
-#define TPM_LOC_TWO ((UINT8) 0x04)
-#define TPM_LOC_ONE ((UINT8) 0x02)
-#define TPM_LOC_ZERO ((UINT8) 0x01)
+#define TPM_LOC_FOUR ((UINT8) 0x10)
+#define TPM_LOC_THREE ((UINT8) 0x08)
+#define TPM_LOC_TWO ((UINT8) 0x04)
+#define TPM_LOC_ONE ((UINT8) 0x02)
+#define TPM_LOC_ZERO ((UINT8) 0x01)
///
/// Part 2, section 8.4: TPM_PCR_INFO_LONG
///
typedef struct tdTPM_PCR_INFO_LONG {
- TPM_STRUCTURE_TAG tag;
- TPM_LOCALITY_SELECTION localityAtCreation;
- TPM_LOCALITY_SELECTION localityAtRelease;
- TPM_PCR_SELECTION creationPCRSelection;
- TPM_PCR_SELECTION releasePCRSelection;
- TPM_COMPOSITE_HASH digestAtCreation;
- TPM_COMPOSITE_HASH digestAtRelease;
+ TPM_STRUCTURE_TAG tag;
+ TPM_LOCALITY_SELECTION localityAtCreation;
+ TPM_LOCALITY_SELECTION localityAtRelease;
+ TPM_PCR_SELECTION creationPCRSelection;
+ TPM_PCR_SELECTION releasePCRSelection;
+ TPM_COMPOSITE_HASH digestAtCreation;
+ TPM_COMPOSITE_HASH digestAtRelease;
} TPM_PCR_INFO_LONG;
///
/// Part 2, section 8.5: TPM_PCR_INFO_SHORT
///
-typedef struct tdTPM_PCR_INFO_SHORT{
- TPM_PCR_SELECTION pcrSelection;
- TPM_LOCALITY_SELECTION localityAtRelease;
- TPM_COMPOSITE_HASH digestAtRelease;
+typedef struct tdTPM_PCR_INFO_SHORT {
+ TPM_PCR_SELECTION pcrSelection;
+ TPM_LOCALITY_SELECTION localityAtRelease;
+ TPM_COMPOSITE_HASH digestAtRelease;
} TPM_PCR_INFO_SHORT;
///
/// Part 2, section 8.8: TPM_PCR_ATTRIBUTES
///
-typedef struct tdTPM_PCR_ATTRIBUTES{
- BOOLEAN pcrReset;
- TPM_LOCALITY_SELECTION pcrExtendLocal;
- TPM_LOCALITY_SELECTION pcrResetLocal;
+typedef struct tdTPM_PCR_ATTRIBUTES {
+ BOOLEAN pcrReset;
+ TPM_LOCALITY_SELECTION pcrExtendLocal;
+ TPM_LOCALITY_SELECTION pcrResetLocal;
} TPM_PCR_ATTRIBUTES;
//
@@ -977,11 +975,11 @@ typedef struct tdTPM_PCR_ATTRIBUTES{
/// [size_is(encDataSize)] BYTE* encData;
///
typedef struct tdTPM_STORED_DATA {
- TPM_STRUCT_VER ver;
- UINT32 sealInfoSize;
- UINT8 *sealInfo;
- UINT32 encDataSize;
- UINT8 *encData;
+ TPM_STRUCT_VER ver;
+ UINT32 sealInfoSize;
+ UINT8 *sealInfo;
+ UINT32 encDataSize;
+ UINT8 *encData;
} TPM_STORED_DATA;
///
@@ -990,12 +988,12 @@ typedef struct tdTPM_STORED_DATA {
/// [size_is(encDataSize)] BYTE* encData;
///
typedef struct tdTPM_STORED_DATA12 {
- TPM_STRUCTURE_TAG tag;
- TPM_ENTITY_TYPE et;
- UINT32 sealInfoSize;
- UINT8 *sealInfo;
- UINT32 encDataSize;
- UINT8 *encData;
+ TPM_STRUCTURE_TAG tag;
+ TPM_ENTITY_TYPE et;
+ UINT32 sealInfoSize;
+ UINT8 *sealInfo;
+ UINT32 encDataSize;
+ UINT8 *encData;
} TPM_STORED_DATA12;
///
@@ -1003,12 +1001,12 @@ typedef struct tdTPM_STORED_DATA12 {
/// [size_is(dataSize)] BYTE* data;
///
typedef struct tdTPM_SEALED_DATA {
- TPM_PAYLOAD_TYPE payload;
- TPM_SECRET authData;
- TPM_NONCE tpmProof;
- TPM_DIGEST storedDigest;
- UINT32 dataSize;
- UINT8 *data;
+ TPM_PAYLOAD_TYPE payload;
+ TPM_SECRET authData;
+ TPM_NONCE tpmProof;
+ TPM_DIGEST storedDigest;
+ UINT32 dataSize;
+ UINT8 *data;
} TPM_SEALED_DATA;
///
@@ -1016,19 +1014,19 @@ typedef struct tdTPM_SEALED_DATA {
/// [size_is(size)] BYTE* data;
///
typedef struct tdTPM_SYMMETRIC_KEY {
- TPM_ALGORITHM_ID algId;
- TPM_ENC_SCHEME encScheme;
- UINT16 dataSize;
- UINT8 *data;
+ TPM_ALGORITHM_ID algId;
+ TPM_ENC_SCHEME encScheme;
+ UINT16 dataSize;
+ UINT8 *data;
} TPM_SYMMETRIC_KEY;
///
/// Part 2, section 9.5: TPM_BOUND_DATA
///
typedef struct tdTPM_BOUND_DATA {
- TPM_STRUCT_VER ver;
- TPM_PAYLOAD_TYPE payload;
- UINT8 payloadData[1];
+ TPM_STRUCT_VER ver;
+ TPM_PAYLOAD_TYPE payload;
+ UINT8 payloadData[1];
} TPM_BOUND_DATA;
//
@@ -1043,35 +1041,35 @@ typedef struct tdTPM_BOUND_DATA {
/// Part 2, section 10.2: TPM_KEY
/// [size_is(encDataSize)] BYTE* encData;
///
-typedef struct tdTPM_KEY{
- TPM_STRUCT_VER ver;
- TPM_KEY_USAGE keyUsage;
- TPM_KEY_FLAGS keyFlags;
- TPM_AUTH_DATA_USAGE authDataUsage;
- TPM_KEY_PARMS algorithmParms;
- UINT32 PCRInfoSize;
- UINT8 *PCRInfo;
- TPM_STORE_PUBKEY pubKey;
- UINT32 encDataSize;
- UINT8 *encData;
+typedef struct tdTPM_KEY {
+ TPM_STRUCT_VER ver;
+ TPM_KEY_USAGE keyUsage;
+ TPM_KEY_FLAGS keyFlags;
+ TPM_AUTH_DATA_USAGE authDataUsage;
+ TPM_KEY_PARMS algorithmParms;
+ UINT32 PCRInfoSize;
+ UINT8 *PCRInfo;
+ TPM_STORE_PUBKEY pubKey;
+ UINT32 encDataSize;
+ UINT8 *encData;
} TPM_KEY;
///
/// Part 2, section 10.3: TPM_KEY12
/// [size_is(encDataSize)] BYTE* encData;
///
-typedef struct tdTPM_KEY12{
- TPM_STRUCTURE_TAG tag;
- UINT16 fill;
- TPM_KEY_USAGE keyUsage;
- TPM_KEY_FLAGS keyFlags;
- TPM_AUTH_DATA_USAGE authDataUsage;
- TPM_KEY_PARMS algorithmParms;
- UINT32 PCRInfoSize;
- UINT8 *PCRInfo;
- TPM_STORE_PUBKEY pubKey;
- UINT32 encDataSize;
- UINT8 *encData;
+typedef struct tdTPM_KEY12 {
+ TPM_STRUCTURE_TAG tag;
+ UINT16 fill;
+ TPM_KEY_USAGE keyUsage;
+ TPM_KEY_FLAGS keyFlags;
+ TPM_AUTH_DATA_USAGE authDataUsage;
+ TPM_KEY_PARMS algorithmParms;
+ UINT32 PCRInfoSize;
+ UINT8 *PCRInfo;
+ TPM_STORE_PUBKEY pubKey;
+ UINT32 encDataSize;
+ UINT8 *encData;
} TPM_KEY12;
///
@@ -1079,37 +1077,39 @@ typedef struct tdTPM_KEY12{
/// [size_is(keyLength)] BYTE* key;
///
typedef struct tdTPM_STORE_PRIVKEY {
- UINT32 keyLength;
- UINT8 *key;
+ UINT32 keyLength;
+ UINT8 *key;
} TPM_STORE_PRIVKEY;
///
/// Part 2, section 10.6: TPM_STORE_ASYMKEY
///
-typedef struct tdTPM_STORE_ASYMKEY { // pos len total
- TPM_PAYLOAD_TYPE payload; // 0 1 1
- TPM_SECRET usageAuth; // 1 20 21
- TPM_SECRET migrationAuth; // 21 20 41
- TPM_DIGEST pubDataDigest; // 41 20 61
- TPM_STORE_PRIVKEY privKey; // 61 132-151 193-214
+typedef struct tdTPM_STORE_ASYMKEY {
+ // pos len total
+ TPM_PAYLOAD_TYPE payload; // 0 1 1
+ TPM_SECRET usageAuth; // 1 20 21
+ TPM_SECRET migrationAuth; // 21 20 41
+ TPM_DIGEST pubDataDigest; // 41 20 61
+ TPM_STORE_PRIVKEY privKey; // 61 132-151 193-214
} TPM_STORE_ASYMKEY;
///
/// Part 2, section 10.8: TPM_MIGRATE_ASYMKEY
/// [size_is(partPrivKeyLen)] BYTE* partPrivKey;
///
-typedef struct tdTPM_MIGRATE_ASYMKEY { // pos len total
- TPM_PAYLOAD_TYPE payload; // 0 1 1
- TPM_SECRET usageAuth; // 1 20 21
- TPM_DIGEST pubDataDigest; // 21 20 41
- UINT32 partPrivKeyLen; // 41 4 45
- UINT8 *partPrivKey; // 45 112-127 157-172
+typedef struct tdTPM_MIGRATE_ASYMKEY {
+ // pos len total
+ TPM_PAYLOAD_TYPE payload; // 0 1 1
+ TPM_SECRET usageAuth; // 1 20 21
+ TPM_DIGEST pubDataDigest; // 21 20 41
+ UINT32 partPrivKeyLen; // 41 4 45
+ UINT8 *partPrivKey; // 45 112-127 157-172
} TPM_MIGRATE_ASYMKEY;
///
/// Part 2, section 10.9: TPM_KEY_CONTROL
///
-#define TPM_KEY_CONTROL_OWNER_EVICT ((UINT32) 0x00000001)
+#define TPM_KEY_CONTROL_OWNER_EVICT ((UINT32) 0x00000001)
//
// Part 2, section 11: Signed Structures
@@ -1119,56 +1119,56 @@ typedef struct tdTPM_MIGRATE_ASYMKEY { // pos len total
/// Part 2, section 11.1: TPM_CERTIFY_INFO Structure
///
typedef struct tdTPM_CERTIFY_INFO {
- TPM_STRUCT_VER version;
- TPM_KEY_USAGE keyUsage;
- TPM_KEY_FLAGS keyFlags;
- TPM_AUTH_DATA_USAGE authDataUsage;
- TPM_KEY_PARMS algorithmParms;
- TPM_DIGEST pubkeyDigest;
- TPM_NONCE data;
- BOOLEAN parentPCRStatus;
- UINT32 PCRInfoSize;
- UINT8 *PCRInfo;
+ TPM_STRUCT_VER version;
+ TPM_KEY_USAGE keyUsage;
+ TPM_KEY_FLAGS keyFlags;
+ TPM_AUTH_DATA_USAGE authDataUsage;
+ TPM_KEY_PARMS algorithmParms;
+ TPM_DIGEST pubkeyDigest;
+ TPM_NONCE data;
+ BOOLEAN parentPCRStatus;
+ UINT32 PCRInfoSize;
+ UINT8 *PCRInfo;
} TPM_CERTIFY_INFO;
///
/// Part 2, section 11.2: TPM_CERTIFY_INFO2 Structure
///
typedef struct tdTPM_CERTIFY_INFO2 {
- TPM_STRUCTURE_TAG tag;
- UINT8 fill;
- TPM_PAYLOAD_TYPE payloadType;
- TPM_KEY_USAGE keyUsage;
- TPM_KEY_FLAGS keyFlags;
- TPM_AUTH_DATA_USAGE authDataUsage;
- TPM_KEY_PARMS algorithmParms;
- TPM_DIGEST pubkeyDigest;
- TPM_NONCE data;
- BOOLEAN parentPCRStatus;
- UINT32 PCRInfoSize;
- UINT8 *PCRInfo;
- UINT32 migrationAuthoritySize;
- UINT8 *migrationAuthority;
+ TPM_STRUCTURE_TAG tag;
+ UINT8 fill;
+ TPM_PAYLOAD_TYPE payloadType;
+ TPM_KEY_USAGE keyUsage;
+ TPM_KEY_FLAGS keyFlags;
+ TPM_AUTH_DATA_USAGE authDataUsage;
+ TPM_KEY_PARMS algorithmParms;
+ TPM_DIGEST pubkeyDigest;
+ TPM_NONCE data;
+ BOOLEAN parentPCRStatus;
+ UINT32 PCRInfoSize;
+ UINT8 *PCRInfo;
+ UINT32 migrationAuthoritySize;
+ UINT8 *migrationAuthority;
} TPM_CERTIFY_INFO2;
///
/// Part 2, section 11.3 TPM_QUOTE_INFO Structure
///
typedef struct tdTPM_QUOTE_INFO {
- TPM_STRUCT_VER version;
- UINT8 fixed[4];
- TPM_COMPOSITE_HASH digestValue;
- TPM_NONCE externalData;
+ TPM_STRUCT_VER version;
+ UINT8 fixed[4];
+ TPM_COMPOSITE_HASH digestValue;
+ TPM_NONCE externalData;
} TPM_QUOTE_INFO;
///
/// Part 2, section 11.4 TPM_QUOTE_INFO2 Structure
///
typedef struct tdTPM_QUOTE_INFO2 {
- TPM_STRUCTURE_TAG tag;
- UINT8 fixed[4];
- TPM_NONCE externalData;
- TPM_PCR_INFO_SHORT infoShort;
+ TPM_STRUCTURE_TAG tag;
+ UINT8 fixed[4];
+ TPM_NONCE externalData;
+ TPM_PCR_INFO_SHORT infoShort;
} TPM_QUOTE_INFO2;
//
@@ -1179,86 +1179,85 @@ typedef struct tdTPM_QUOTE_INFO2 {
/// Part 2, section 12.1 TPM_EK_BLOB
///
typedef struct tdTPM_EK_BLOB {
- TPM_STRUCTURE_TAG tag;
- TPM_EK_TYPE ekType;
- UINT32 blobSize;
- UINT8 *blob;
+ TPM_STRUCTURE_TAG tag;
+ TPM_EK_TYPE ekType;
+ UINT32 blobSize;
+ UINT8 *blob;
} TPM_EK_BLOB;
///
/// Part 2, section 12.2 TPM_EK_BLOB_ACTIVATE
///
typedef struct tdTPM_EK_BLOB_ACTIVATE {
- TPM_STRUCTURE_TAG tag;
- TPM_SYMMETRIC_KEY sessionKey;
- TPM_DIGEST idDigest;
- TPM_PCR_INFO_SHORT pcrInfo;
+ TPM_STRUCTURE_TAG tag;
+ TPM_SYMMETRIC_KEY sessionKey;
+ TPM_DIGEST idDigest;
+ TPM_PCR_INFO_SHORT pcrInfo;
} TPM_EK_BLOB_ACTIVATE;
///
/// Part 2, section 12.3 TPM_EK_BLOB_AUTH
///
typedef struct tdTPM_EK_BLOB_AUTH {
- TPM_STRUCTURE_TAG tag;
- TPM_SECRET authValue;
+ TPM_STRUCTURE_TAG tag;
+ TPM_SECRET authValue;
} TPM_EK_BLOB_AUTH;
-
///
/// Part 2, section 12.5 TPM_IDENTITY_CONTENTS
///
typedef struct tdTPM_IDENTITY_CONTENTS {
- TPM_STRUCT_VER ver;
- UINT32 ordinal;
- TPM_CHOSENID_HASH labelPrivCADigest;
- TPM_PUBKEY identityPubKey;
+ TPM_STRUCT_VER ver;
+ UINT32 ordinal;
+ TPM_CHOSENID_HASH labelPrivCADigest;
+ TPM_PUBKEY identityPubKey;
} TPM_IDENTITY_CONTENTS;
///
/// Part 2, section 12.6 TPM_IDENTITY_REQ
///
typedef struct tdTPM_IDENTITY_REQ {
- UINT32 asymSize;
- UINT32 symSize;
- TPM_KEY_PARMS asymAlgorithm;
- TPM_KEY_PARMS symAlgorithm;
- UINT8 *asymBlob;
- UINT8 *symBlob;
+ UINT32 asymSize;
+ UINT32 symSize;
+ TPM_KEY_PARMS asymAlgorithm;
+ TPM_KEY_PARMS symAlgorithm;
+ UINT8 *asymBlob;
+ UINT8 *symBlob;
} TPM_IDENTITY_REQ;
///
/// Part 2, section 12.7 TPM_IDENTITY_PROOF
///
typedef struct tdTPM_IDENTITY_PROOF {
- TPM_STRUCT_VER ver;
- UINT32 labelSize;
- UINT32 identityBindingSize;
- UINT32 endorsementSize;
- UINT32 platformSize;
- UINT32 conformanceSize;
- TPM_PUBKEY identityKey;
- UINT8 *labelArea;
- UINT8 *identityBinding;
- UINT8 *endorsementCredential;
- UINT8 *platformCredential;
- UINT8 *conformanceCredential;
+ TPM_STRUCT_VER ver;
+ UINT32 labelSize;
+ UINT32 identityBindingSize;
+ UINT32 endorsementSize;
+ UINT32 platformSize;
+ UINT32 conformanceSize;
+ TPM_PUBKEY identityKey;
+ UINT8 *labelArea;
+ UINT8 *identityBinding;
+ UINT8 *endorsementCredential;
+ UINT8 *platformCredential;
+ UINT8 *conformanceCredential;
} TPM_IDENTITY_PROOF;
///
/// Part 2, section 12.8 TPM_ASYM_CA_CONTENTS
///
typedef struct tdTPM_ASYM_CA_CONTENTS {
- TPM_SYMMETRIC_KEY sessionKey;
- TPM_DIGEST idDigest;
+ TPM_SYMMETRIC_KEY sessionKey;
+ TPM_DIGEST idDigest;
} TPM_ASYM_CA_CONTENTS;
///
/// Part 2, section 12.9 TPM_SYM_CA_ATTESTATION
///
typedef struct tdTPM_SYM_CA_ATTESTATION {
- UINT32 credSize;
- TPM_KEY_PARMS algorithm;
- UINT8 *credential;
+ UINT32 credSize;
+ TPM_KEY_PARMS algorithm;
+ UINT8 *credential;
} TPM_SYM_CA_ATTESTATION;
///
@@ -1266,10 +1265,10 @@ typedef struct tdTPM_SYM_CA_ATTESTATION {
/// Placed here out of order because definitions are used in section 13.
///
typedef struct tdTPM_CURRENT_TICKS {
- TPM_STRUCTURE_TAG tag;
- UINT64 currentTicks;
- UINT16 tickRate;
- TPM_NONCE tickNonce;
+ TPM_STRUCTURE_TAG tag;
+ UINT64 currentTicks;
+ UINT16 tickRate;
+ TPM_NONCE tickNonce;
} TPM_CURRENT_TICKS;
///
@@ -1280,56 +1279,56 @@ typedef struct tdTPM_CURRENT_TICKS {
/// Part 2, section 13.1: TPM _TRANSPORT_PUBLIC
///
typedef struct tdTPM_TRANSPORT_PUBLIC {
- TPM_STRUCTURE_TAG tag;
- TPM_TRANSPORT_ATTRIBUTES transAttributes;
- TPM_ALGORITHM_ID algId;
- TPM_ENC_SCHEME encScheme;
+ TPM_STRUCTURE_TAG tag;
+ TPM_TRANSPORT_ATTRIBUTES transAttributes;
+ TPM_ALGORITHM_ID algId;
+ TPM_ENC_SCHEME encScheme;
} TPM_TRANSPORT_PUBLIC;
//
// Part 2, section 13.1.1 TPM_TRANSPORT_ATTRIBUTES Definitions
//
-#define TPM_TRANSPORT_ENCRYPT ((UINT32)BIT0)
-#define TPM_TRANSPORT_LOG ((UINT32)BIT1)
-#define TPM_TRANSPORT_EXCLUSIVE ((UINT32)BIT2)
+#define TPM_TRANSPORT_ENCRYPT ((UINT32)BIT0)
+#define TPM_TRANSPORT_LOG ((UINT32)BIT1)
+#define TPM_TRANSPORT_EXCLUSIVE ((UINT32)BIT2)
///
/// Part 2, section 13.2 TPM_TRANSPORT_INTERNAL
///
typedef struct tdTPM_TRANSPORT_INTERNAL {
- TPM_STRUCTURE_TAG tag;
- TPM_AUTHDATA authData;
- TPM_TRANSPORT_PUBLIC transPublic;
- TPM_TRANSHANDLE transHandle;
- TPM_NONCE transNonceEven;
- TPM_DIGEST transDigest;
+ TPM_STRUCTURE_TAG tag;
+ TPM_AUTHDATA authData;
+ TPM_TRANSPORT_PUBLIC transPublic;
+ TPM_TRANSHANDLE transHandle;
+ TPM_NONCE transNonceEven;
+ TPM_DIGEST transDigest;
} TPM_TRANSPORT_INTERNAL;
///
/// Part 2, section 13.3 TPM_TRANSPORT_LOG_IN structure
///
typedef struct tdTPM_TRANSPORT_LOG_IN {
- TPM_STRUCTURE_TAG tag;
- TPM_DIGEST parameters;
- TPM_DIGEST pubKeyHash;
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST parameters;
+ TPM_DIGEST pubKeyHash;
} TPM_TRANSPORT_LOG_IN;
///
/// Part 2, section 13.4 TPM_TRANSPORT_LOG_OUT structure
///
typedef struct tdTPM_TRANSPORT_LOG_OUT {
- TPM_STRUCTURE_TAG tag;
- TPM_CURRENT_TICKS currentTicks;
- TPM_DIGEST parameters;
- TPM_MODIFIER_INDICATOR locality;
+ TPM_STRUCTURE_TAG tag;
+ TPM_CURRENT_TICKS currentTicks;
+ TPM_DIGEST parameters;
+ TPM_MODIFIER_INDICATOR locality;
} TPM_TRANSPORT_LOG_OUT;
///
/// Part 2, section 13.5 TPM_TRANSPORT_AUTH structure
///
typedef struct tdTPM_TRANSPORT_AUTH {
- TPM_STRUCTURE_TAG tag;
- TPM_AUTHDATA authData;
+ TPM_STRUCTURE_TAG tag;
+ TPM_AUTHDATA authData;
} TPM_TRANSPORT_AUTH;
//
@@ -1340,28 +1339,28 @@ typedef struct tdTPM_TRANSPORT_AUTH {
/// Part 2, section 14.1 TPM_AUDIT_EVENT_IN structure
///
typedef struct tdTPM_AUDIT_EVENT_IN {
- TPM_STRUCTURE_TAG tag;
- TPM_DIGEST inputParms;
- TPM_COUNTER_VALUE auditCount;
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST inputParms;
+ TPM_COUNTER_VALUE auditCount;
} TPM_AUDIT_EVENT_IN;
///
/// Part 2, section 14.2 TPM_AUDIT_EVENT_OUT structure
///
typedef struct tdTPM_AUDIT_EVENT_OUT {
- TPM_STRUCTURE_TAG tag;
- TPM_COMMAND_CODE ordinal;
- TPM_DIGEST outputParms;
- TPM_COUNTER_VALUE auditCount;
- TPM_RESULT returnCode;
+ TPM_STRUCTURE_TAG tag;
+ TPM_COMMAND_CODE ordinal;
+ TPM_DIGEST outputParms;
+ TPM_COUNTER_VALUE auditCount;
+ TPM_RESULT returnCode;
} TPM_AUDIT_EVENT_OUT;
//
// Part 2, section 16: Return Codes
//
-#define TPM_VENDOR_ERROR TPM_Vendor_Specific32
-#define TPM_NON_FATAL 0x00000800
+#define TPM_VENDOR_ERROR TPM_Vendor_Specific32
+#define TPM_NON_FATAL 0x00000800
#define TPM_SUCCESS ((TPM_RESULT) TPM_BASE)
#define TPM_AUTHFAIL ((TPM_RESULT) (TPM_BASE + 1))
@@ -1463,10 +1462,10 @@ typedef struct tdTPM_AUDIT_EVENT_OUT {
#define TPM_BAD_SIGNATURE ((TPM_RESULT) (TPM_BASE + 98))
#define TPM_NOCONTEXTSPACE ((TPM_RESULT) (TPM_BASE + 99))
-#define TPM_RETRY ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL))
-#define TPM_NEEDS_SELFTEST ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 1))
-#define TPM_DOING_SELFTEST ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 2))
-#define TPM_DEFEND_LOCK_RUNNING ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 3))
+#define TPM_RETRY ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL))
+#define TPM_NEEDS_SELFTEST ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 1))
+#define TPM_DOING_SELFTEST ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 2))
+#define TPM_DEFEND_LOCK_RUNNING ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 3))
//
// Part 2, section 17: Ordinals
@@ -1496,131 +1495,131 @@ typedef struct tdTPM_AUDIT_EVENT_OUT {
// * All reserved area bits are set to 0.
//
-#define TPM_ORD_ActivateIdentity ((TPM_COMMAND_CODE) 0x0000007A)
-#define TPM_ORD_AuthorizeMigrationKey ((TPM_COMMAND_CODE) 0x0000002B)
-#define TPM_ORD_CertifyKey ((TPM_COMMAND_CODE) 0x00000032)
-#define TPM_ORD_CertifyKey2 ((TPM_COMMAND_CODE) 0x00000033)
-#define TPM_ORD_CertifySelfTest ((TPM_COMMAND_CODE) 0x00000052)
-#define TPM_ORD_ChangeAuth ((TPM_COMMAND_CODE) 0x0000000C)
-#define TPM_ORD_ChangeAuthAsymFinish ((TPM_COMMAND_CODE) 0x0000000F)
-#define TPM_ORD_ChangeAuthAsymStart ((TPM_COMMAND_CODE) 0x0000000E)
-#define TPM_ORD_ChangeAuthOwner ((TPM_COMMAND_CODE) 0x00000010)
-#define TPM_ORD_CMK_ApproveMA ((TPM_COMMAND_CODE) 0x0000001D)
-#define TPM_ORD_CMK_ConvertMigration ((TPM_COMMAND_CODE) 0x00000024)
-#define TPM_ORD_CMK_CreateBlob ((TPM_COMMAND_CODE) 0x0000001B)
-#define TPM_ORD_CMK_CreateKey ((TPM_COMMAND_CODE) 0x00000013)
-#define TPM_ORD_CMK_CreateTicket ((TPM_COMMAND_CODE) 0x00000012)
-#define TPM_ORD_CMK_SetRestrictions ((TPM_COMMAND_CODE) 0x0000001C)
-#define TPM_ORD_ContinueSelfTest ((TPM_COMMAND_CODE) 0x00000053)
-#define TPM_ORD_ConvertMigrationBlob ((TPM_COMMAND_CODE) 0x0000002A)
-#define TPM_ORD_CreateCounter ((TPM_COMMAND_CODE) 0x000000DC)
-#define TPM_ORD_CreateEndorsementKeyPair ((TPM_COMMAND_CODE) 0x00000078)
-#define TPM_ORD_CreateMaintenanceArchive ((TPM_COMMAND_CODE) 0x0000002C)
-#define TPM_ORD_CreateMigrationBlob ((TPM_COMMAND_CODE) 0x00000028)
-#define TPM_ORD_CreateRevocableEK ((TPM_COMMAND_CODE) 0x0000007F)
-#define TPM_ORD_CreateWrapKey ((TPM_COMMAND_CODE) 0x0000001F)
-#define TPM_ORD_DAA_JOIN ((TPM_COMMAND_CODE) 0x00000029)
-#define TPM_ORD_DAA_SIGN ((TPM_COMMAND_CODE) 0x00000031)
-#define TPM_ORD_Delegate_CreateKeyDelegation ((TPM_COMMAND_CODE) 0x000000D4)
-#define TPM_ORD_Delegate_CreateOwnerDelegation ((TPM_COMMAND_CODE) 0x000000D5)
-#define TPM_ORD_Delegate_LoadOwnerDelegation ((TPM_COMMAND_CODE) 0x000000D8)
-#define TPM_ORD_Delegate_Manage ((TPM_COMMAND_CODE) 0x000000D2)
-#define TPM_ORD_Delegate_ReadTable ((TPM_COMMAND_CODE) 0x000000DB)
-#define TPM_ORD_Delegate_UpdateVerification ((TPM_COMMAND_CODE) 0x000000D1)
-#define TPM_ORD_Delegate_VerifyDelegation ((TPM_COMMAND_CODE) 0x000000D6)
-#define TPM_ORD_DirRead ((TPM_COMMAND_CODE) 0x0000001A)
-#define TPM_ORD_DirWriteAuth ((TPM_COMMAND_CODE) 0x00000019)
-#define TPM_ORD_DisableForceClear ((TPM_COMMAND_CODE) 0x0000005E)
-#define TPM_ORD_DisableOwnerClear ((TPM_COMMAND_CODE) 0x0000005C)
-#define TPM_ORD_DisablePubekRead ((TPM_COMMAND_CODE) 0x0000007E)
-#define TPM_ORD_DSAP ((TPM_COMMAND_CODE) 0x00000011)
-#define TPM_ORD_EstablishTransport ((TPM_COMMAND_CODE) 0x000000E6)
-#define TPM_ORD_EvictKey ((TPM_COMMAND_CODE) 0x00000022)
-#define TPM_ORD_ExecuteTransport ((TPM_COMMAND_CODE) 0x000000E7)
-#define TPM_ORD_Extend ((TPM_COMMAND_CODE) 0x00000014)
-#define TPM_ORD_FieldUpgrade ((TPM_COMMAND_CODE) 0x000000AA)
-#define TPM_ORD_FlushSpecific ((TPM_COMMAND_CODE) 0x000000BA)
-#define TPM_ORD_ForceClear ((TPM_COMMAND_CODE) 0x0000005D)
-#define TPM_ORD_GetAuditDigest ((TPM_COMMAND_CODE) 0x00000085)
-#define TPM_ORD_GetAuditDigestSigned ((TPM_COMMAND_CODE) 0x00000086)
-#define TPM_ORD_GetAuditEvent ((TPM_COMMAND_CODE) 0x00000082)
-#define TPM_ORD_GetAuditEventSigned ((TPM_COMMAND_CODE) 0x00000083)
-#define TPM_ORD_GetCapability ((TPM_COMMAND_CODE) 0x00000065)
-#define TPM_ORD_GetCapabilityOwner ((TPM_COMMAND_CODE) 0x00000066)
-#define TPM_ORD_GetCapabilitySigned ((TPM_COMMAND_CODE) 0x00000064)
-#define TPM_ORD_GetOrdinalAuditStatus ((TPM_COMMAND_CODE) 0x0000008C)
-#define TPM_ORD_GetPubKey ((TPM_COMMAND_CODE) 0x00000021)
-#define TPM_ORD_GetRandom ((TPM_COMMAND_CODE) 0x00000046)
-#define TPM_ORD_GetTestResult ((TPM_COMMAND_CODE) 0x00000054)
-#define TPM_ORD_GetTicks ((TPM_COMMAND_CODE) 0x000000F1)
-#define TPM_ORD_IncrementCounter ((TPM_COMMAND_CODE) 0x000000DD)
-#define TPM_ORD_Init ((TPM_COMMAND_CODE) 0x00000097)
-#define TPM_ORD_KeyControlOwner ((TPM_COMMAND_CODE) 0x00000023)
-#define TPM_ORD_KillMaintenanceFeature ((TPM_COMMAND_CODE) 0x0000002E)
-#define TPM_ORD_LoadAuthContext ((TPM_COMMAND_CODE) 0x000000B7)
-#define TPM_ORD_LoadContext ((TPM_COMMAND_CODE) 0x000000B9)
-#define TPM_ORD_LoadKey ((TPM_COMMAND_CODE) 0x00000020)
-#define TPM_ORD_LoadKey2 ((TPM_COMMAND_CODE) 0x00000041)
-#define TPM_ORD_LoadKeyContext ((TPM_COMMAND_CODE) 0x000000B5)
-#define TPM_ORD_LoadMaintenanceArchive ((TPM_COMMAND_CODE) 0x0000002D)
-#define TPM_ORD_LoadManuMaintPub ((TPM_COMMAND_CODE) 0x0000002F)
-#define TPM_ORD_MakeIdentity ((TPM_COMMAND_CODE) 0x00000079)
-#define TPM_ORD_MigrateKey ((TPM_COMMAND_CODE) 0x00000025)
-#define TPM_ORD_NV_DefineSpace ((TPM_COMMAND_CODE) 0x000000CC)
-#define TPM_ORD_NV_ReadValue ((TPM_COMMAND_CODE) 0x000000CF)
-#define TPM_ORD_NV_ReadValueAuth ((TPM_COMMAND_CODE) 0x000000D0)
-#define TPM_ORD_NV_WriteValue ((TPM_COMMAND_CODE) 0x000000CD)
-#define TPM_ORD_NV_WriteValueAuth ((TPM_COMMAND_CODE) 0x000000CE)
-#define TPM_ORD_OIAP ((TPM_COMMAND_CODE) 0x0000000A)
-#define TPM_ORD_OSAP ((TPM_COMMAND_CODE) 0x0000000B)
-#define TPM_ORD_OwnerClear ((TPM_COMMAND_CODE) 0x0000005B)
-#define TPM_ORD_OwnerReadInternalPub ((TPM_COMMAND_CODE) 0x00000081)
-#define TPM_ORD_OwnerReadPubek ((TPM_COMMAND_CODE) 0x0000007D)
-#define TPM_ORD_OwnerSetDisable ((TPM_COMMAND_CODE) 0x0000006E)
-#define TPM_ORD_PCR_Reset ((TPM_COMMAND_CODE) 0x000000C8)
-#define TPM_ORD_PcrRead ((TPM_COMMAND_CODE) 0x00000015)
-#define TPM_ORD_PhysicalDisable ((TPM_COMMAND_CODE) 0x00000070)
-#define TPM_ORD_PhysicalEnable ((TPM_COMMAND_CODE) 0x0000006F)
-#define TPM_ORD_PhysicalSetDeactivated ((TPM_COMMAND_CODE) 0x00000072)
-#define TPM_ORD_Quote ((TPM_COMMAND_CODE) 0x00000016)
-#define TPM_ORD_Quote2 ((TPM_COMMAND_CODE) 0x0000003E)
-#define TPM_ORD_ReadCounter ((TPM_COMMAND_CODE) 0x000000DE)
-#define TPM_ORD_ReadManuMaintPub ((TPM_COMMAND_CODE) 0x00000030)
-#define TPM_ORD_ReadPubek ((TPM_COMMAND_CODE) 0x0000007C)
-#define TPM_ORD_ReleaseCounter ((TPM_COMMAND_CODE) 0x000000DF)
-#define TPM_ORD_ReleaseCounterOwner ((TPM_COMMAND_CODE) 0x000000E0)
-#define TPM_ORD_ReleaseTransportSigned ((TPM_COMMAND_CODE) 0x000000E8)
-#define TPM_ORD_Reset ((TPM_COMMAND_CODE) 0x0000005A)
-#define TPM_ORD_ResetLockValue ((TPM_COMMAND_CODE) 0x00000040)
-#define TPM_ORD_RevokeTrust ((TPM_COMMAND_CODE) 0x00000080)
-#define TPM_ORD_SaveAuthContext ((TPM_COMMAND_CODE) 0x000000B6)
-#define TPM_ORD_SaveContext ((TPM_COMMAND_CODE) 0x000000B8)
-#define TPM_ORD_SaveKeyContext ((TPM_COMMAND_CODE) 0x000000B4)
-#define TPM_ORD_SaveState ((TPM_COMMAND_CODE) 0x00000098)
-#define TPM_ORD_Seal ((TPM_COMMAND_CODE) 0x00000017)
-#define TPM_ORD_Sealx ((TPM_COMMAND_CODE) 0x0000003D)
-#define TPM_ORD_SelfTestFull ((TPM_COMMAND_CODE) 0x00000050)
-#define TPM_ORD_SetCapability ((TPM_COMMAND_CODE) 0x0000003F)
-#define TPM_ORD_SetOperatorAuth ((TPM_COMMAND_CODE) 0x00000074)
-#define TPM_ORD_SetOrdinalAuditStatus ((TPM_COMMAND_CODE) 0x0000008D)
-#define TPM_ORD_SetOwnerInstall ((TPM_COMMAND_CODE) 0x00000071)
-#define TPM_ORD_SetOwnerPointer ((TPM_COMMAND_CODE) 0x00000075)
-#define TPM_ORD_SetRedirection ((TPM_COMMAND_CODE) 0x0000009A)
-#define TPM_ORD_SetTempDeactivated ((TPM_COMMAND_CODE) 0x00000073)
-#define TPM_ORD_SHA1Complete ((TPM_COMMAND_CODE) 0x000000A2)
-#define TPM_ORD_SHA1CompleteExtend ((TPM_COMMAND_CODE) 0x000000A3)
-#define TPM_ORD_SHA1Start ((TPM_COMMAND_CODE) 0x000000A0)
-#define TPM_ORD_SHA1Update ((TPM_COMMAND_CODE) 0x000000A1)
-#define TPM_ORD_Sign ((TPM_COMMAND_CODE) 0x0000003C)
-#define TPM_ORD_Startup ((TPM_COMMAND_CODE) 0x00000099)
-#define TPM_ORD_StirRandom ((TPM_COMMAND_CODE) 0x00000047)
-#define TPM_ORD_TakeOwnership ((TPM_COMMAND_CODE) 0x0000000D)
-#define TPM_ORD_Terminate_Handle ((TPM_COMMAND_CODE) 0x00000096)
-#define TPM_ORD_TickStampBlob ((TPM_COMMAND_CODE) 0x000000F2)
-#define TPM_ORD_UnBind ((TPM_COMMAND_CODE) 0x0000001E)
-#define TPM_ORD_Unseal ((TPM_COMMAND_CODE) 0x00000018)
-#define TSC_ORD_PhysicalPresence ((TPM_COMMAND_CODE) 0x4000000A)
-#define TSC_ORD_ResetEstablishmentBit ((TPM_COMMAND_CODE) 0x4000000B)
+#define TPM_ORD_ActivateIdentity ((TPM_COMMAND_CODE) 0x0000007A)
+#define TPM_ORD_AuthorizeMigrationKey ((TPM_COMMAND_CODE) 0x0000002B)
+#define TPM_ORD_CertifyKey ((TPM_COMMAND_CODE) 0x00000032)
+#define TPM_ORD_CertifyKey2 ((TPM_COMMAND_CODE) 0x00000033)
+#define TPM_ORD_CertifySelfTest ((TPM_COMMAND_CODE) 0x00000052)
+#define TPM_ORD_ChangeAuth ((TPM_COMMAND_CODE) 0x0000000C)
+#define TPM_ORD_ChangeAuthAsymFinish ((TPM_COMMAND_CODE) 0x0000000F)
+#define TPM_ORD_ChangeAuthAsymStart ((TPM_COMMAND_CODE) 0x0000000E)
+#define TPM_ORD_ChangeAuthOwner ((TPM_COMMAND_CODE) 0x00000010)
+#define TPM_ORD_CMK_ApproveMA ((TPM_COMMAND_CODE) 0x0000001D)
+#define TPM_ORD_CMK_ConvertMigration ((TPM_COMMAND_CODE) 0x00000024)
+#define TPM_ORD_CMK_CreateBlob ((TPM_COMMAND_CODE) 0x0000001B)
+#define TPM_ORD_CMK_CreateKey ((TPM_COMMAND_CODE) 0x00000013)
+#define TPM_ORD_CMK_CreateTicket ((TPM_COMMAND_CODE) 0x00000012)
+#define TPM_ORD_CMK_SetRestrictions ((TPM_COMMAND_CODE) 0x0000001C)
+#define TPM_ORD_ContinueSelfTest ((TPM_COMMAND_CODE) 0x00000053)
+#define TPM_ORD_ConvertMigrationBlob ((TPM_COMMAND_CODE) 0x0000002A)
+#define TPM_ORD_CreateCounter ((TPM_COMMAND_CODE) 0x000000DC)
+#define TPM_ORD_CreateEndorsementKeyPair ((TPM_COMMAND_CODE) 0x00000078)
+#define TPM_ORD_CreateMaintenanceArchive ((TPM_COMMAND_CODE) 0x0000002C)
+#define TPM_ORD_CreateMigrationBlob ((TPM_COMMAND_CODE) 0x00000028)
+#define TPM_ORD_CreateRevocableEK ((TPM_COMMAND_CODE) 0x0000007F)
+#define TPM_ORD_CreateWrapKey ((TPM_COMMAND_CODE) 0x0000001F)
+#define TPM_ORD_DAA_JOIN ((TPM_COMMAND_CODE) 0x00000029)
+#define TPM_ORD_DAA_SIGN ((TPM_COMMAND_CODE) 0x00000031)
+#define TPM_ORD_Delegate_CreateKeyDelegation ((TPM_COMMAND_CODE) 0x000000D4)
+#define TPM_ORD_Delegate_CreateOwnerDelegation ((TPM_COMMAND_CODE) 0x000000D5)
+#define TPM_ORD_Delegate_LoadOwnerDelegation ((TPM_COMMAND_CODE) 0x000000D8)
+#define TPM_ORD_Delegate_Manage ((TPM_COMMAND_CODE) 0x000000D2)
+#define TPM_ORD_Delegate_ReadTable ((TPM_COMMAND_CODE) 0x000000DB)
+#define TPM_ORD_Delegate_UpdateVerification ((TPM_COMMAND_CODE) 0x000000D1)
+#define TPM_ORD_Delegate_VerifyDelegation ((TPM_COMMAND_CODE) 0x000000D6)
+#define TPM_ORD_DirRead ((TPM_COMMAND_CODE) 0x0000001A)
+#define TPM_ORD_DirWriteAuth ((TPM_COMMAND_CODE) 0x00000019)
+#define TPM_ORD_DisableForceClear ((TPM_COMMAND_CODE) 0x0000005E)
+#define TPM_ORD_DisableOwnerClear ((TPM_COMMAND_CODE) 0x0000005C)
+#define TPM_ORD_DisablePubekRead ((TPM_COMMAND_CODE) 0x0000007E)
+#define TPM_ORD_DSAP ((TPM_COMMAND_CODE) 0x00000011)
+#define TPM_ORD_EstablishTransport ((TPM_COMMAND_CODE) 0x000000E6)
+#define TPM_ORD_EvictKey ((TPM_COMMAND_CODE) 0x00000022)
+#define TPM_ORD_ExecuteTransport ((TPM_COMMAND_CODE) 0x000000E7)
+#define TPM_ORD_Extend ((TPM_COMMAND_CODE) 0x00000014)
+#define TPM_ORD_FieldUpgrade ((TPM_COMMAND_CODE) 0x000000AA)
+#define TPM_ORD_FlushSpecific ((TPM_COMMAND_CODE) 0x000000BA)
+#define TPM_ORD_ForceClear ((TPM_COMMAND_CODE) 0x0000005D)
+#define TPM_ORD_GetAuditDigest ((TPM_COMMAND_CODE) 0x00000085)
+#define TPM_ORD_GetAuditDigestSigned ((TPM_COMMAND_CODE) 0x00000086)
+#define TPM_ORD_GetAuditEvent ((TPM_COMMAND_CODE) 0x00000082)
+#define TPM_ORD_GetAuditEventSigned ((TPM_COMMAND_CODE) 0x00000083)
+#define TPM_ORD_GetCapability ((TPM_COMMAND_CODE) 0x00000065)
+#define TPM_ORD_GetCapabilityOwner ((TPM_COMMAND_CODE) 0x00000066)
+#define TPM_ORD_GetCapabilitySigned ((TPM_COMMAND_CODE) 0x00000064)
+#define TPM_ORD_GetOrdinalAuditStatus ((TPM_COMMAND_CODE) 0x0000008C)
+#define TPM_ORD_GetPubKey ((TPM_COMMAND_CODE) 0x00000021)
+#define TPM_ORD_GetRandom ((TPM_COMMAND_CODE) 0x00000046)
+#define TPM_ORD_GetTestResult ((TPM_COMMAND_CODE) 0x00000054)
+#define TPM_ORD_GetTicks ((TPM_COMMAND_CODE) 0x000000F1)
+#define TPM_ORD_IncrementCounter ((TPM_COMMAND_CODE) 0x000000DD)
+#define TPM_ORD_Init ((TPM_COMMAND_CODE) 0x00000097)
+#define TPM_ORD_KeyControlOwner ((TPM_COMMAND_CODE) 0x00000023)
+#define TPM_ORD_KillMaintenanceFeature ((TPM_COMMAND_CODE) 0x0000002E)
+#define TPM_ORD_LoadAuthContext ((TPM_COMMAND_CODE) 0x000000B7)
+#define TPM_ORD_LoadContext ((TPM_COMMAND_CODE) 0x000000B9)
+#define TPM_ORD_LoadKey ((TPM_COMMAND_CODE) 0x00000020)
+#define TPM_ORD_LoadKey2 ((TPM_COMMAND_CODE) 0x00000041)
+#define TPM_ORD_LoadKeyContext ((TPM_COMMAND_CODE) 0x000000B5)
+#define TPM_ORD_LoadMaintenanceArchive ((TPM_COMMAND_CODE) 0x0000002D)
+#define TPM_ORD_LoadManuMaintPub ((TPM_COMMAND_CODE) 0x0000002F)
+#define TPM_ORD_MakeIdentity ((TPM_COMMAND_CODE) 0x00000079)
+#define TPM_ORD_MigrateKey ((TPM_COMMAND_CODE) 0x00000025)
+#define TPM_ORD_NV_DefineSpace ((TPM_COMMAND_CODE) 0x000000CC)
+#define TPM_ORD_NV_ReadValue ((TPM_COMMAND_CODE) 0x000000CF)
+#define TPM_ORD_NV_ReadValueAuth ((TPM_COMMAND_CODE) 0x000000D0)
+#define TPM_ORD_NV_WriteValue ((TPM_COMMAND_CODE) 0x000000CD)
+#define TPM_ORD_NV_WriteValueAuth ((TPM_COMMAND_CODE) 0x000000CE)
+#define TPM_ORD_OIAP ((TPM_COMMAND_CODE) 0x0000000A)
+#define TPM_ORD_OSAP ((TPM_COMMAND_CODE) 0x0000000B)
+#define TPM_ORD_OwnerClear ((TPM_COMMAND_CODE) 0x0000005B)
+#define TPM_ORD_OwnerReadInternalPub ((TPM_COMMAND_CODE) 0x00000081)
+#define TPM_ORD_OwnerReadPubek ((TPM_COMMAND_CODE) 0x0000007D)
+#define TPM_ORD_OwnerSetDisable ((TPM_COMMAND_CODE) 0x0000006E)
+#define TPM_ORD_PCR_Reset ((TPM_COMMAND_CODE) 0x000000C8)
+#define TPM_ORD_PcrRead ((TPM_COMMAND_CODE) 0x00000015)
+#define TPM_ORD_PhysicalDisable ((TPM_COMMAND_CODE) 0x00000070)
+#define TPM_ORD_PhysicalEnable ((TPM_COMMAND_CODE) 0x0000006F)
+#define TPM_ORD_PhysicalSetDeactivated ((TPM_COMMAND_CODE) 0x00000072)
+#define TPM_ORD_Quote ((TPM_COMMAND_CODE) 0x00000016)
+#define TPM_ORD_Quote2 ((TPM_COMMAND_CODE) 0x0000003E)
+#define TPM_ORD_ReadCounter ((TPM_COMMAND_CODE) 0x000000DE)
+#define TPM_ORD_ReadManuMaintPub ((TPM_COMMAND_CODE) 0x00000030)
+#define TPM_ORD_ReadPubek ((TPM_COMMAND_CODE) 0x0000007C)
+#define TPM_ORD_ReleaseCounter ((TPM_COMMAND_CODE) 0x000000DF)
+#define TPM_ORD_ReleaseCounterOwner ((TPM_COMMAND_CODE) 0x000000E0)
+#define TPM_ORD_ReleaseTransportSigned ((TPM_COMMAND_CODE) 0x000000E8)
+#define TPM_ORD_Reset ((TPM_COMMAND_CODE) 0x0000005A)
+#define TPM_ORD_ResetLockValue ((TPM_COMMAND_CODE) 0x00000040)
+#define TPM_ORD_RevokeTrust ((TPM_COMMAND_CODE) 0x00000080)
+#define TPM_ORD_SaveAuthContext ((TPM_COMMAND_CODE) 0x000000B6)
+#define TPM_ORD_SaveContext ((TPM_COMMAND_CODE) 0x000000B8)
+#define TPM_ORD_SaveKeyContext ((TPM_COMMAND_CODE) 0x000000B4)
+#define TPM_ORD_SaveState ((TPM_COMMAND_CODE) 0x00000098)
+#define TPM_ORD_Seal ((TPM_COMMAND_CODE) 0x00000017)
+#define TPM_ORD_Sealx ((TPM_COMMAND_CODE) 0x0000003D)
+#define TPM_ORD_SelfTestFull ((TPM_COMMAND_CODE) 0x00000050)
+#define TPM_ORD_SetCapability ((TPM_COMMAND_CODE) 0x0000003F)
+#define TPM_ORD_SetOperatorAuth ((TPM_COMMAND_CODE) 0x00000074)
+#define TPM_ORD_SetOrdinalAuditStatus ((TPM_COMMAND_CODE) 0x0000008D)
+#define TPM_ORD_SetOwnerInstall ((TPM_COMMAND_CODE) 0x00000071)
+#define TPM_ORD_SetOwnerPointer ((TPM_COMMAND_CODE) 0x00000075)
+#define TPM_ORD_SetRedirection ((TPM_COMMAND_CODE) 0x0000009A)
+#define TPM_ORD_SetTempDeactivated ((TPM_COMMAND_CODE) 0x00000073)
+#define TPM_ORD_SHA1Complete ((TPM_COMMAND_CODE) 0x000000A2)
+#define TPM_ORD_SHA1CompleteExtend ((TPM_COMMAND_CODE) 0x000000A3)
+#define TPM_ORD_SHA1Start ((TPM_COMMAND_CODE) 0x000000A0)
+#define TPM_ORD_SHA1Update ((TPM_COMMAND_CODE) 0x000000A1)
+#define TPM_ORD_Sign ((TPM_COMMAND_CODE) 0x0000003C)
+#define TPM_ORD_Startup ((TPM_COMMAND_CODE) 0x00000099)
+#define TPM_ORD_StirRandom ((TPM_COMMAND_CODE) 0x00000047)
+#define TPM_ORD_TakeOwnership ((TPM_COMMAND_CODE) 0x0000000D)
+#define TPM_ORD_Terminate_Handle ((TPM_COMMAND_CODE) 0x00000096)
+#define TPM_ORD_TickStampBlob ((TPM_COMMAND_CODE) 0x000000F2)
+#define TPM_ORD_UnBind ((TPM_COMMAND_CODE) 0x0000001E)
+#define TPM_ORD_Unseal ((TPM_COMMAND_CODE) 0x00000018)
+#define TSC_ORD_PhysicalPresence ((TPM_COMMAND_CODE) 0x4000000A)
+#define TSC_ORD_ResetEstablishmentBit ((TPM_COMMAND_CODE) 0x4000000B)
//
// Part 2, section 18: Context structures
@@ -1630,26 +1629,26 @@ typedef struct tdTPM_AUDIT_EVENT_OUT {
/// Part 2, section 18.1: TPM_CONTEXT_BLOB
///
typedef struct tdTPM_CONTEXT_BLOB {
- TPM_STRUCTURE_TAG tag;
- TPM_RESOURCE_TYPE resourceType;
- TPM_HANDLE handle;
- UINT8 label[16];
- UINT32 contextCount;
- TPM_DIGEST integrityDigest;
- UINT32 additionalSize;
- UINT8 *additionalData;
- UINT32 sensitiveSize;
- UINT8 *sensitiveData;
+ TPM_STRUCTURE_TAG tag;
+ TPM_RESOURCE_TYPE resourceType;
+ TPM_HANDLE handle;
+ UINT8 label[16];
+ UINT32 contextCount;
+ TPM_DIGEST integrityDigest;
+ UINT32 additionalSize;
+ UINT8 *additionalData;
+ UINT32 sensitiveSize;
+ UINT8 *sensitiveData;
} TPM_CONTEXT_BLOB;
///
/// Part 2, section 18.2 TPM_CONTEXT_SENSITIVE
///
typedef struct tdTPM_CONTEXT_SENSITIVE {
- TPM_STRUCTURE_TAG tag;
- TPM_NONCE contextNonce;
- UINT32 internalSize;
- UINT8 *internalData;
+ TPM_STRUCTURE_TAG tag;
+ TPM_NONCE contextNonce;
+ UINT32 internalSize;
+ UINT8 *internalData;
} TPM_CONTEXT_SENSITIVE;
//
@@ -1659,382 +1658,382 @@ typedef struct tdTPM_CONTEXT_SENSITIVE {
//
// Part 2, section 19.1.1: Required TPM_NV_INDEX values
//
-#define TPM_NV_INDEX_LOCK ((UINT32)0xffffffff)
-#define TPM_NV_INDEX0 ((UINT32)0x00000000)
-#define TPM_NV_INDEX_DIR ((UINT32)0x10000001)
-#define TPM_NV_INDEX_EKCert ((UINT32)0x0000f000)
-#define TPM_NV_INDEX_TPM_CC ((UINT32)0x0000f001)
-#define TPM_NV_INDEX_PlatformCert ((UINT32)0x0000f002)
-#define TPM_NV_INDEX_Platform_CC ((UINT32)0x0000f003)
+#define TPM_NV_INDEX_LOCK ((UINT32)0xffffffff)
+#define TPM_NV_INDEX0 ((UINT32)0x00000000)
+#define TPM_NV_INDEX_DIR ((UINT32)0x10000001)
+#define TPM_NV_INDEX_EKCert ((UINT32)0x0000f000)
+#define TPM_NV_INDEX_TPM_CC ((UINT32)0x0000f001)
+#define TPM_NV_INDEX_PlatformCert ((UINT32)0x0000f002)
+#define TPM_NV_INDEX_Platform_CC ((UINT32)0x0000f003)
//
// Part 2, section 19.1.2: Reserved Index values
//
-#define TPM_NV_INDEX_TSS_BASE ((UINT32)0x00011100)
-#define TPM_NV_INDEX_PC_BASE ((UINT32)0x00011200)
-#define TPM_NV_INDEX_SERVER_BASE ((UINT32)0x00011300)
-#define TPM_NV_INDEX_MOBILE_BASE ((UINT32)0x00011400)
-#define TPM_NV_INDEX_PERIPHERAL_BASE ((UINT32)0x00011500)
-#define TPM_NV_INDEX_GROUP_RESV_BASE ((UINT32)0x00010000)
+#define TPM_NV_INDEX_TSS_BASE ((UINT32)0x00011100)
+#define TPM_NV_INDEX_PC_BASE ((UINT32)0x00011200)
+#define TPM_NV_INDEX_SERVER_BASE ((UINT32)0x00011300)
+#define TPM_NV_INDEX_MOBILE_BASE ((UINT32)0x00011400)
+#define TPM_NV_INDEX_PERIPHERAL_BASE ((UINT32)0x00011500)
+#define TPM_NV_INDEX_GROUP_RESV_BASE ((UINT32)0x00010000)
///
/// Part 2, section 19.2: TPM_NV_ATTRIBUTES
///
typedef struct tdTPM_NV_ATTRIBUTES {
- TPM_STRUCTURE_TAG tag;
- UINT32 attributes;
+ TPM_STRUCTURE_TAG tag;
+ UINT32 attributes;
} TPM_NV_ATTRIBUTES;
-#define TPM_NV_PER_READ_STCLEAR (BIT31)
-#define TPM_NV_PER_AUTHREAD (BIT18)
-#define TPM_NV_PER_OWNERREAD (BIT17)
-#define TPM_NV_PER_PPREAD (BIT16)
-#define TPM_NV_PER_GLOBALLOCK (BIT15)
-#define TPM_NV_PER_WRITE_STCLEAR (BIT14)
-#define TPM_NV_PER_WRITEDEFINE (BIT13)
-#define TPM_NV_PER_WRITEALL (BIT12)
-#define TPM_NV_PER_AUTHWRITE (BIT2)
-#define TPM_NV_PER_OWNERWRITE (BIT1)
-#define TPM_NV_PER_PPWRITE (BIT0)
+#define TPM_NV_PER_READ_STCLEAR (BIT31)
+#define TPM_NV_PER_AUTHREAD (BIT18)
+#define TPM_NV_PER_OWNERREAD (BIT17)
+#define TPM_NV_PER_PPREAD (BIT16)
+#define TPM_NV_PER_GLOBALLOCK (BIT15)
+#define TPM_NV_PER_WRITE_STCLEAR (BIT14)
+#define TPM_NV_PER_WRITEDEFINE (BIT13)
+#define TPM_NV_PER_WRITEALL (BIT12)
+#define TPM_NV_PER_AUTHWRITE (BIT2)
+#define TPM_NV_PER_OWNERWRITE (BIT1)
+#define TPM_NV_PER_PPWRITE (BIT0)
///
/// Part 2, section 19.3: TPM_NV_DATA_PUBLIC
///
typedef struct tdTPM_NV_DATA_PUBLIC {
- TPM_STRUCTURE_TAG tag;
- TPM_NV_INDEX nvIndex;
- TPM_PCR_INFO_SHORT pcrInfoRead;
- TPM_PCR_INFO_SHORT pcrInfoWrite;
- TPM_NV_ATTRIBUTES permission;
- BOOLEAN bReadSTClear;
- BOOLEAN bWriteSTClear;
- BOOLEAN bWriteDefine;
- UINT32 dataSize;
+ TPM_STRUCTURE_TAG tag;
+ TPM_NV_INDEX nvIndex;
+ TPM_PCR_INFO_SHORT pcrInfoRead;
+ TPM_PCR_INFO_SHORT pcrInfoWrite;
+ TPM_NV_ATTRIBUTES permission;
+ BOOLEAN bReadSTClear;
+ BOOLEAN bWriteSTClear;
+ BOOLEAN bWriteDefine;
+ UINT32 dataSize;
} TPM_NV_DATA_PUBLIC;
//
// Part 2, section 20: Delegate Structures
//
-#define TPM_DEL_OWNER_BITS ((UINT32)0x00000001)
-#define TPM_DEL_KEY_BITS ((UINT32)0x00000002)
+#define TPM_DEL_OWNER_BITS ((UINT32)0x00000001)
+#define TPM_DEL_KEY_BITS ((UINT32)0x00000002)
///
/// Part 2, section 20.2: Delegate Definitions
///
typedef struct tdTPM_DELEGATIONS {
- TPM_STRUCTURE_TAG tag;
- UINT32 delegateType;
- UINT32 per1;
- UINT32 per2;
+ TPM_STRUCTURE_TAG tag;
+ UINT32 delegateType;
+ UINT32 per1;
+ UINT32 per2;
} TPM_DELEGATIONS;
//
// Part 2, section 20.2.1: Owner Permission Settings
//
-#define TPM_DELEGATE_SetOrdinalAuditStatus (BIT30)
-#define TPM_DELEGATE_DirWriteAuth (BIT29)
-#define TPM_DELEGATE_CMK_ApproveMA (BIT28)
-#define TPM_DELEGATE_NV_WriteValue (BIT27)
-#define TPM_DELEGATE_CMK_CreateTicket (BIT26)
-#define TPM_DELEGATE_NV_ReadValue (BIT25)
-#define TPM_DELEGATE_Delegate_LoadOwnerDelegation (BIT24)
-#define TPM_DELEGATE_DAA_Join (BIT23)
-#define TPM_DELEGATE_AuthorizeMigrationKey (BIT22)
-#define TPM_DELEGATE_CreateMaintenanceArchive (BIT21)
-#define TPM_DELEGATE_LoadMaintenanceArchive (BIT20)
-#define TPM_DELEGATE_KillMaintenanceFeature (BIT19)
-#define TPM_DELEGATE_OwnerReadInteralPub (BIT18)
-#define TPM_DELEGATE_ResetLockValue (BIT17)
-#define TPM_DELEGATE_OwnerClear (BIT16)
-#define TPM_DELEGATE_DisableOwnerClear (BIT15)
-#define TPM_DELEGATE_NV_DefineSpace (BIT14)
-#define TPM_DELEGATE_OwnerSetDisable (BIT13)
-#define TPM_DELEGATE_SetCapability (BIT12)
-#define TPM_DELEGATE_MakeIdentity (BIT11)
-#define TPM_DELEGATE_ActivateIdentity (BIT10)
-#define TPM_DELEGATE_OwnerReadPubek (BIT9)
-#define TPM_DELEGATE_DisablePubekRead (BIT8)
-#define TPM_DELEGATE_SetRedirection (BIT7)
-#define TPM_DELEGATE_FieldUpgrade (BIT6)
-#define TPM_DELEGATE_Delegate_UpdateVerification (BIT5)
-#define TPM_DELEGATE_CreateCounter (BIT4)
-#define TPM_DELEGATE_ReleaseCounterOwner (BIT3)
-#define TPM_DELEGATE_DelegateManage (BIT2)
-#define TPM_DELEGATE_Delegate_CreateOwnerDelegation (BIT1)
-#define TPM_DELEGATE_DAA_Sign (BIT0)
+#define TPM_DELEGATE_SetOrdinalAuditStatus (BIT30)
+#define TPM_DELEGATE_DirWriteAuth (BIT29)
+#define TPM_DELEGATE_CMK_ApproveMA (BIT28)
+#define TPM_DELEGATE_NV_WriteValue (BIT27)
+#define TPM_DELEGATE_CMK_CreateTicket (BIT26)
+#define TPM_DELEGATE_NV_ReadValue (BIT25)
+#define TPM_DELEGATE_Delegate_LoadOwnerDelegation (BIT24)
+#define TPM_DELEGATE_DAA_Join (BIT23)
+#define TPM_DELEGATE_AuthorizeMigrationKey (BIT22)
+#define TPM_DELEGATE_CreateMaintenanceArchive (BIT21)
+#define TPM_DELEGATE_LoadMaintenanceArchive (BIT20)
+#define TPM_DELEGATE_KillMaintenanceFeature (BIT19)
+#define TPM_DELEGATE_OwnerReadInteralPub (BIT18)
+#define TPM_DELEGATE_ResetLockValue (BIT17)
+#define TPM_DELEGATE_OwnerClear (BIT16)
+#define TPM_DELEGATE_DisableOwnerClear (BIT15)
+#define TPM_DELEGATE_NV_DefineSpace (BIT14)
+#define TPM_DELEGATE_OwnerSetDisable (BIT13)
+#define TPM_DELEGATE_SetCapability (BIT12)
+#define TPM_DELEGATE_MakeIdentity (BIT11)
+#define TPM_DELEGATE_ActivateIdentity (BIT10)
+#define TPM_DELEGATE_OwnerReadPubek (BIT9)
+#define TPM_DELEGATE_DisablePubekRead (BIT8)
+#define TPM_DELEGATE_SetRedirection (BIT7)
+#define TPM_DELEGATE_FieldUpgrade (BIT6)
+#define TPM_DELEGATE_Delegate_UpdateVerification (BIT5)
+#define TPM_DELEGATE_CreateCounter (BIT4)
+#define TPM_DELEGATE_ReleaseCounterOwner (BIT3)
+#define TPM_DELEGATE_DelegateManage (BIT2)
+#define TPM_DELEGATE_Delegate_CreateOwnerDelegation (BIT1)
+#define TPM_DELEGATE_DAA_Sign (BIT0)
//
// Part 2, section 20.2.3: Key Permission settings
//
-#define TPM_KEY_DELEGATE_CMK_ConvertMigration (BIT28)
-#define TPM_KEY_DELEGATE_TickStampBlob (BIT27)
-#define TPM_KEY_DELEGATE_ChangeAuthAsymStart (BIT26)
-#define TPM_KEY_DELEGATE_ChangeAuthAsymFinish (BIT25)
-#define TPM_KEY_DELEGATE_CMK_CreateKey (BIT24)
-#define TPM_KEY_DELEGATE_MigrateKey (BIT23)
-#define TPM_KEY_DELEGATE_LoadKey2 (BIT22)
-#define TPM_KEY_DELEGATE_EstablishTransport (BIT21)
-#define TPM_KEY_DELEGATE_ReleaseTransportSigned (BIT20)
-#define TPM_KEY_DELEGATE_Quote2 (BIT19)
-#define TPM_KEY_DELEGATE_Sealx (BIT18)
-#define TPM_KEY_DELEGATE_MakeIdentity (BIT17)
-#define TPM_KEY_DELEGATE_ActivateIdentity (BIT16)
-#define TPM_KEY_DELEGATE_GetAuditDigestSigned (BIT15)
-#define TPM_KEY_DELEGATE_Sign (BIT14)
-#define TPM_KEY_DELEGATE_CertifyKey2 (BIT13)
-#define TPM_KEY_DELEGATE_CertifyKey (BIT12)
-#define TPM_KEY_DELEGATE_CreateWrapKey (BIT11)
-#define TPM_KEY_DELEGATE_CMK_CreateBlob (BIT10)
-#define TPM_KEY_DELEGATE_CreateMigrationBlob (BIT9)
-#define TPM_KEY_DELEGATE_ConvertMigrationBlob (BIT8)
-#define TPM_KEY_DELEGATE_CreateKeyDelegation (BIT7)
-#define TPM_KEY_DELEGATE_ChangeAuth (BIT6)
-#define TPM_KEY_DELEGATE_GetPubKey (BIT5)
-#define TPM_KEY_DELEGATE_UnBind (BIT4)
-#define TPM_KEY_DELEGATE_Quote (BIT3)
-#define TPM_KEY_DELEGATE_Unseal (BIT2)
-#define TPM_KEY_DELEGATE_Seal (BIT1)
-#define TPM_KEY_DELEGATE_LoadKey (BIT0)
+#define TPM_KEY_DELEGATE_CMK_ConvertMigration (BIT28)
+#define TPM_KEY_DELEGATE_TickStampBlob (BIT27)
+#define TPM_KEY_DELEGATE_ChangeAuthAsymStart (BIT26)
+#define TPM_KEY_DELEGATE_ChangeAuthAsymFinish (BIT25)
+#define TPM_KEY_DELEGATE_CMK_CreateKey (BIT24)
+#define TPM_KEY_DELEGATE_MigrateKey (BIT23)
+#define TPM_KEY_DELEGATE_LoadKey2 (BIT22)
+#define TPM_KEY_DELEGATE_EstablishTransport (BIT21)
+#define TPM_KEY_DELEGATE_ReleaseTransportSigned (BIT20)
+#define TPM_KEY_DELEGATE_Quote2 (BIT19)
+#define TPM_KEY_DELEGATE_Sealx (BIT18)
+#define TPM_KEY_DELEGATE_MakeIdentity (BIT17)
+#define TPM_KEY_DELEGATE_ActivateIdentity (BIT16)
+#define TPM_KEY_DELEGATE_GetAuditDigestSigned (BIT15)
+#define TPM_KEY_DELEGATE_Sign (BIT14)
+#define TPM_KEY_DELEGATE_CertifyKey2 (BIT13)
+#define TPM_KEY_DELEGATE_CertifyKey (BIT12)
+#define TPM_KEY_DELEGATE_CreateWrapKey (BIT11)
+#define TPM_KEY_DELEGATE_CMK_CreateBlob (BIT10)
+#define TPM_KEY_DELEGATE_CreateMigrationBlob (BIT9)
+#define TPM_KEY_DELEGATE_ConvertMigrationBlob (BIT8)
+#define TPM_KEY_DELEGATE_CreateKeyDelegation (BIT7)
+#define TPM_KEY_DELEGATE_ChangeAuth (BIT6)
+#define TPM_KEY_DELEGATE_GetPubKey (BIT5)
+#define TPM_KEY_DELEGATE_UnBind (BIT4)
+#define TPM_KEY_DELEGATE_Quote (BIT3)
+#define TPM_KEY_DELEGATE_Unseal (BIT2)
+#define TPM_KEY_DELEGATE_Seal (BIT1)
+#define TPM_KEY_DELEGATE_LoadKey (BIT0)
//
// Part 2, section 20.3: TPM_FAMILY_FLAGS
//
-#define TPM_DELEGATE_ADMIN_LOCK (BIT1)
-#define TPM_FAMFLAG_ENABLE (BIT0)
+#define TPM_DELEGATE_ADMIN_LOCK (BIT1)
+#define TPM_FAMFLAG_ENABLE (BIT0)
///
/// Part 2, section 20.4: TPM_FAMILY_LABEL
///
typedef struct tdTPM_FAMILY_LABEL {
- UINT8 label;
+ UINT8 label;
} TPM_FAMILY_LABEL;
///
/// Part 2, section 20.5: TPM_FAMILY_TABLE_ENTRY
///
typedef struct tdTPM_FAMILY_TABLE_ENTRY {
- TPM_STRUCTURE_TAG tag;
- TPM_FAMILY_LABEL label;
- TPM_FAMILY_ID familyID;
- TPM_FAMILY_VERIFICATION verificationCount;
- TPM_FAMILY_FLAGS flags;
+ TPM_STRUCTURE_TAG tag;
+ TPM_FAMILY_LABEL label;
+ TPM_FAMILY_ID familyID;
+ TPM_FAMILY_VERIFICATION verificationCount;
+ TPM_FAMILY_FLAGS flags;
} TPM_FAMILY_TABLE_ENTRY;
//
// Part 2, section 20.6: TPM_FAMILY_TABLE
//
-#define TPM_NUM_FAMILY_TABLE_ENTRY_MIN 8
+#define TPM_NUM_FAMILY_TABLE_ENTRY_MIN 8
-typedef struct tdTPM_FAMILY_TABLE{
- TPM_FAMILY_TABLE_ENTRY famTableRow[TPM_NUM_FAMILY_TABLE_ENTRY_MIN];
+typedef struct tdTPM_FAMILY_TABLE {
+ TPM_FAMILY_TABLE_ENTRY famTableRow[TPM_NUM_FAMILY_TABLE_ENTRY_MIN];
} TPM_FAMILY_TABLE;
///
/// Part 2, section 20.7: TPM_DELEGATE_LABEL
///
typedef struct tdTPM_DELEGATE_LABEL {
- UINT8 label;
+ UINT8 label;
} TPM_DELEGATE_LABEL;
///
/// Part 2, section 20.8: TPM_DELEGATE_PUBLIC
///
typedef struct tdTPM_DELEGATE_PUBLIC {
- TPM_STRUCTURE_TAG tag;
- TPM_DELEGATE_LABEL label;
- TPM_PCR_INFO_SHORT pcrInfo;
- TPM_DELEGATIONS permissions;
- TPM_FAMILY_ID familyID;
- TPM_FAMILY_VERIFICATION verificationCount;
+ TPM_STRUCTURE_TAG tag;
+ TPM_DELEGATE_LABEL label;
+ TPM_PCR_INFO_SHORT pcrInfo;
+ TPM_DELEGATIONS permissions;
+ TPM_FAMILY_ID familyID;
+ TPM_FAMILY_VERIFICATION verificationCount;
} TPM_DELEGATE_PUBLIC;
///
/// Part 2, section 20.9: TPM_DELEGATE_TABLE_ROW
///
typedef struct tdTPM_DELEGATE_TABLE_ROW {
- TPM_STRUCTURE_TAG tag;
- TPM_DELEGATE_PUBLIC pub;
- TPM_SECRET authValue;
+ TPM_STRUCTURE_TAG tag;
+ TPM_DELEGATE_PUBLIC pub;
+ TPM_SECRET authValue;
} TPM_DELEGATE_TABLE_ROW;
//
// Part 2, section 20.10: TPM_DELEGATE_TABLE
//
-#define TPM_NUM_DELEGATE_TABLE_ENTRY_MIN 2
+#define TPM_NUM_DELEGATE_TABLE_ENTRY_MIN 2
-typedef struct tdTPM_DELEGATE_TABLE{
- TPM_DELEGATE_TABLE_ROW delRow[TPM_NUM_DELEGATE_TABLE_ENTRY_MIN];
+typedef struct tdTPM_DELEGATE_TABLE {
+ TPM_DELEGATE_TABLE_ROW delRow[TPM_NUM_DELEGATE_TABLE_ENTRY_MIN];
} TPM_DELEGATE_TABLE;
///
/// Part 2, section 20.11: TPM_DELEGATE_SENSITIVE
///
typedef struct tdTPM_DELEGATE_SENSITIVE {
- TPM_STRUCTURE_TAG tag;
- TPM_SECRET authValue;
+ TPM_STRUCTURE_TAG tag;
+ TPM_SECRET authValue;
} TPM_DELEGATE_SENSITIVE;
///
/// Part 2, section 20.12: TPM_DELEGATE_OWNER_BLOB
///
typedef struct tdTPM_DELEGATE_OWNER_BLOB {
- TPM_STRUCTURE_TAG tag;
- TPM_DELEGATE_PUBLIC pub;
- TPM_DIGEST integrityDigest;
- UINT32 additionalSize;
- UINT8 *additionalArea;
- UINT32 sensitiveSize;
- UINT8 *sensitiveArea;
+ TPM_STRUCTURE_TAG tag;
+ TPM_DELEGATE_PUBLIC pub;
+ TPM_DIGEST integrityDigest;
+ UINT32 additionalSize;
+ UINT8 *additionalArea;
+ UINT32 sensitiveSize;
+ UINT8 *sensitiveArea;
} TPM_DELEGATE_OWNER_BLOB;
///
/// Part 2, section 20.13: TTPM_DELEGATE_KEY_BLOB
///
typedef struct tdTPM_DELEGATE_KEY_BLOB {
- TPM_STRUCTURE_TAG tag;
- TPM_DELEGATE_PUBLIC pub;
- TPM_DIGEST integrityDigest;
- TPM_DIGEST pubKeyDigest;
- UINT32 additionalSize;
- UINT8 *additionalArea;
- UINT32 sensitiveSize;
- UINT8 *sensitiveArea;
+ TPM_STRUCTURE_TAG tag;
+ TPM_DELEGATE_PUBLIC pub;
+ TPM_DIGEST integrityDigest;
+ TPM_DIGEST pubKeyDigest;
+ UINT32 additionalSize;
+ UINT8 *additionalArea;
+ UINT32 sensitiveSize;
+ UINT8 *sensitiveArea;
} TPM_DELEGATE_KEY_BLOB;
//
// Part 2, section 20.14: TPM_FAMILY_OPERATION Values
//
-#define TPM_FAMILY_CREATE ((UINT32)0x00000001)
-#define TPM_FAMILY_ENABLE ((UINT32)0x00000002)
-#define TPM_FAMILY_ADMIN ((UINT32)0x00000003)
-#define TPM_FAMILY_INVALIDATE ((UINT32)0x00000004)
+#define TPM_FAMILY_CREATE ((UINT32)0x00000001)
+#define TPM_FAMILY_ENABLE ((UINT32)0x00000002)
+#define TPM_FAMILY_ADMIN ((UINT32)0x00000003)
+#define TPM_FAMILY_INVALIDATE ((UINT32)0x00000004)
//
// Part 2, section 21.1: TPM_CAPABILITY_AREA for GetCapability
//
-#define TPM_CAP_ORD ((TPM_CAPABILITY_AREA) 0x00000001)
-#define TPM_CAP_ALG ((TPM_CAPABILITY_AREA) 0x00000002)
-#define TPM_CAP_PID ((TPM_CAPABILITY_AREA) 0x00000003)
-#define TPM_CAP_FLAG ((TPM_CAPABILITY_AREA) 0x00000004)
-#define TPM_CAP_PROPERTY ((TPM_CAPABILITY_AREA) 0x00000005)
-#define TPM_CAP_VERSION ((TPM_CAPABILITY_AREA) 0x00000006)
-#define TPM_CAP_KEY_HANDLE ((TPM_CAPABILITY_AREA) 0x00000007)
-#define TPM_CAP_CHECK_LOADED ((TPM_CAPABILITY_AREA) 0x00000008)
-#define TPM_CAP_SYM_MODE ((TPM_CAPABILITY_AREA) 0x00000009)
-#define TPM_CAP_KEY_STATUS ((TPM_CAPABILITY_AREA) 0x0000000C)
-#define TPM_CAP_NV_LIST ((TPM_CAPABILITY_AREA) 0x0000000D)
-#define TPM_CAP_MFR ((TPM_CAPABILITY_AREA) 0x00000010)
-#define TPM_CAP_NV_INDEX ((TPM_CAPABILITY_AREA) 0x00000011)
-#define TPM_CAP_TRANS_ALG ((TPM_CAPABILITY_AREA) 0x00000012)
-#define TPM_CAP_HANDLE ((TPM_CAPABILITY_AREA) 0x00000014)
-#define TPM_CAP_TRANS_ES ((TPM_CAPABILITY_AREA) 0x00000015)
-#define TPM_CAP_AUTH_ENCRYPT ((TPM_CAPABILITY_AREA) 0x00000017)
-#define TPM_CAP_SELECT_SIZE ((TPM_CAPABILITY_AREA) 0x00000018)
-#define TPM_CAP_VERSION_VAL ((TPM_CAPABILITY_AREA) 0x0000001A)
+#define TPM_CAP_ORD ((TPM_CAPABILITY_AREA) 0x00000001)
+#define TPM_CAP_ALG ((TPM_CAPABILITY_AREA) 0x00000002)
+#define TPM_CAP_PID ((TPM_CAPABILITY_AREA) 0x00000003)
+#define TPM_CAP_FLAG ((TPM_CAPABILITY_AREA) 0x00000004)
+#define TPM_CAP_PROPERTY ((TPM_CAPABILITY_AREA) 0x00000005)
+#define TPM_CAP_VERSION ((TPM_CAPABILITY_AREA) 0x00000006)
+#define TPM_CAP_KEY_HANDLE ((TPM_CAPABILITY_AREA) 0x00000007)
+#define TPM_CAP_CHECK_LOADED ((TPM_CAPABILITY_AREA) 0x00000008)
+#define TPM_CAP_SYM_MODE ((TPM_CAPABILITY_AREA) 0x00000009)
+#define TPM_CAP_KEY_STATUS ((TPM_CAPABILITY_AREA) 0x0000000C)
+#define TPM_CAP_NV_LIST ((TPM_CAPABILITY_AREA) 0x0000000D)
+#define TPM_CAP_MFR ((TPM_CAPABILITY_AREA) 0x00000010)
+#define TPM_CAP_NV_INDEX ((TPM_CAPABILITY_AREA) 0x00000011)
+#define TPM_CAP_TRANS_ALG ((TPM_CAPABILITY_AREA) 0x00000012)
+#define TPM_CAP_HANDLE ((TPM_CAPABILITY_AREA) 0x00000014)
+#define TPM_CAP_TRANS_ES ((TPM_CAPABILITY_AREA) 0x00000015)
+#define TPM_CAP_AUTH_ENCRYPT ((TPM_CAPABILITY_AREA) 0x00000017)
+#define TPM_CAP_SELECT_SIZE ((TPM_CAPABILITY_AREA) 0x00000018)
+#define TPM_CAP_VERSION_VAL ((TPM_CAPABILITY_AREA) 0x0000001A)
-#define TPM_CAP_FLAG_PERMANENT ((TPM_CAPABILITY_AREA) 0x00000108)
-#define TPM_CAP_FLAG_VOLATILE ((TPM_CAPABILITY_AREA) 0x00000109)
+#define TPM_CAP_FLAG_PERMANENT ((TPM_CAPABILITY_AREA) 0x00000108)
+#define TPM_CAP_FLAG_VOLATILE ((TPM_CAPABILITY_AREA) 0x00000109)
//
// Part 2, section 21.2: CAP_PROPERTY Subcap values for GetCapability
//
-#define TPM_CAP_PROP_PCR ((TPM_CAPABILITY_AREA) 0x00000101)
-#define TPM_CAP_PROP_DIR ((TPM_CAPABILITY_AREA) 0x00000102)
-#define TPM_CAP_PROP_MANUFACTURER ((TPM_CAPABILITY_AREA) 0x00000103)
-#define TPM_CAP_PROP_KEYS ((TPM_CAPABILITY_AREA) 0x00000104)
-#define TPM_CAP_PROP_MIN_COUNTER ((TPM_CAPABILITY_AREA) 0x00000107)
-#define TPM_CAP_PROP_AUTHSESS ((TPM_CAPABILITY_AREA) 0x0000010A)
-#define TPM_CAP_PROP_TRANSESS ((TPM_CAPABILITY_AREA) 0x0000010B)
-#define TPM_CAP_PROP_COUNTERS ((TPM_CAPABILITY_AREA) 0x0000010C)
-#define TPM_CAP_PROP_MAX_AUTHSESS ((TPM_CAPABILITY_AREA) 0x0000010D)
-#define TPM_CAP_PROP_MAX_TRANSESS ((TPM_CAPABILITY_AREA) 0x0000010E)
-#define TPM_CAP_PROP_MAX_COUNTERS ((TPM_CAPABILITY_AREA) 0x0000010F)
-#define TPM_CAP_PROP_MAX_KEYS ((TPM_CAPABILITY_AREA) 0x00000110)
-#define TPM_CAP_PROP_OWNER ((TPM_CAPABILITY_AREA) 0x00000111)
-#define TPM_CAP_PROP_CONTEXT ((TPM_CAPABILITY_AREA) 0x00000112)
-#define TPM_CAP_PROP_MAX_CONTEXT ((TPM_CAPABILITY_AREA) 0x00000113)
-#define TPM_CAP_PROP_FAMILYROWS ((TPM_CAPABILITY_AREA) 0x00000114)
-#define TPM_CAP_PROP_TIS_TIMEOUT ((TPM_CAPABILITY_AREA) 0x00000115)
-#define TPM_CAP_PROP_STARTUP_EFFECT ((TPM_CAPABILITY_AREA) 0x00000116)
-#define TPM_CAP_PROP_DELEGATE_ROW ((TPM_CAPABILITY_AREA) 0x00000117)
-#define TPM_CAP_PROP_DAA_MAX ((TPM_CAPABILITY_AREA) 0x00000119)
-#define CAP_PROP_SESSION_DAA ((TPM_CAPABILITY_AREA) 0x0000011A)
-#define TPM_CAP_PROP_CONTEXT_DIST ((TPM_CAPABILITY_AREA) 0x0000011B)
-#define TPM_CAP_PROP_DAA_INTERRUPT ((TPM_CAPABILITY_AREA) 0x0000011C)
-#define TPM_CAP_PROP_SESSIONS ((TPM_CAPABILITY_AREA) 0x0000011D)
-#define TPM_CAP_PROP_MAX_SESSIONS ((TPM_CAPABILITY_AREA) 0x0000011E)
-#define TPM_CAP_PROP_CMK_RESTRICTION ((TPM_CAPABILITY_AREA) 0x0000011F)
-#define TPM_CAP_PROP_DURATION ((TPM_CAPABILITY_AREA) 0x00000120)
-#define TPM_CAP_PROP_ACTIVE_COUNTER ((TPM_CAPABILITY_AREA) 0x00000122)
-#define TPM_CAP_PROP_MAX_NV_AVAILABLE ((TPM_CAPABILITY_AREA) 0x00000123)
-#define TPM_CAP_PROP_INPUT_BUFFER ((TPM_CAPABILITY_AREA) 0x00000124)
+#define TPM_CAP_PROP_PCR ((TPM_CAPABILITY_AREA) 0x00000101)
+#define TPM_CAP_PROP_DIR ((TPM_CAPABILITY_AREA) 0x00000102)
+#define TPM_CAP_PROP_MANUFACTURER ((TPM_CAPABILITY_AREA) 0x00000103)
+#define TPM_CAP_PROP_KEYS ((TPM_CAPABILITY_AREA) 0x00000104)
+#define TPM_CAP_PROP_MIN_COUNTER ((TPM_CAPABILITY_AREA) 0x00000107)
+#define TPM_CAP_PROP_AUTHSESS ((TPM_CAPABILITY_AREA) 0x0000010A)
+#define TPM_CAP_PROP_TRANSESS ((TPM_CAPABILITY_AREA) 0x0000010B)
+#define TPM_CAP_PROP_COUNTERS ((TPM_CAPABILITY_AREA) 0x0000010C)
+#define TPM_CAP_PROP_MAX_AUTHSESS ((TPM_CAPABILITY_AREA) 0x0000010D)
+#define TPM_CAP_PROP_MAX_TRANSESS ((TPM_CAPABILITY_AREA) 0x0000010E)
+#define TPM_CAP_PROP_MAX_COUNTERS ((TPM_CAPABILITY_AREA) 0x0000010F)
+#define TPM_CAP_PROP_MAX_KEYS ((TPM_CAPABILITY_AREA) 0x00000110)
+#define TPM_CAP_PROP_OWNER ((TPM_CAPABILITY_AREA) 0x00000111)
+#define TPM_CAP_PROP_CONTEXT ((TPM_CAPABILITY_AREA) 0x00000112)
+#define TPM_CAP_PROP_MAX_CONTEXT ((TPM_CAPABILITY_AREA) 0x00000113)
+#define TPM_CAP_PROP_FAMILYROWS ((TPM_CAPABILITY_AREA) 0x00000114)
+#define TPM_CAP_PROP_TIS_TIMEOUT ((TPM_CAPABILITY_AREA) 0x00000115)
+#define TPM_CAP_PROP_STARTUP_EFFECT ((TPM_CAPABILITY_AREA) 0x00000116)
+#define TPM_CAP_PROP_DELEGATE_ROW ((TPM_CAPABILITY_AREA) 0x00000117)
+#define TPM_CAP_PROP_DAA_MAX ((TPM_CAPABILITY_AREA) 0x00000119)
+#define CAP_PROP_SESSION_DAA ((TPM_CAPABILITY_AREA) 0x0000011A)
+#define TPM_CAP_PROP_CONTEXT_DIST ((TPM_CAPABILITY_AREA) 0x0000011B)
+#define TPM_CAP_PROP_DAA_INTERRUPT ((TPM_CAPABILITY_AREA) 0x0000011C)
+#define TPM_CAP_PROP_SESSIONS ((TPM_CAPABILITY_AREA) 0x0000011D)
+#define TPM_CAP_PROP_MAX_SESSIONS ((TPM_CAPABILITY_AREA) 0x0000011E)
+#define TPM_CAP_PROP_CMK_RESTRICTION ((TPM_CAPABILITY_AREA) 0x0000011F)
+#define TPM_CAP_PROP_DURATION ((TPM_CAPABILITY_AREA) 0x00000120)
+#define TPM_CAP_PROP_ACTIVE_COUNTER ((TPM_CAPABILITY_AREA) 0x00000122)
+#define TPM_CAP_PROP_MAX_NV_AVAILABLE ((TPM_CAPABILITY_AREA) 0x00000123)
+#define TPM_CAP_PROP_INPUT_BUFFER ((TPM_CAPABILITY_AREA) 0x00000124)
//
// Part 2, section 21.4: TPM_CAPABILITY_AREA for SetCapability
//
-#define TPM_SET_PERM_FLAGS ((TPM_CAPABILITY_AREA) 0x00000001)
-#define TPM_SET_PERM_DATA ((TPM_CAPABILITY_AREA) 0x00000002)
-#define TPM_SET_STCLEAR_FLAGS ((TPM_CAPABILITY_AREA) 0x00000003)
-#define TPM_SET_STCLEAR_DATA ((TPM_CAPABILITY_AREA) 0x00000004)
-#define TPM_SET_STANY_FLAGS ((TPM_CAPABILITY_AREA) 0x00000005)
-#define TPM_SET_STANY_DATA ((TPM_CAPABILITY_AREA) 0x00000006)
+#define TPM_SET_PERM_FLAGS ((TPM_CAPABILITY_AREA) 0x00000001)
+#define TPM_SET_PERM_DATA ((TPM_CAPABILITY_AREA) 0x00000002)
+#define TPM_SET_STCLEAR_FLAGS ((TPM_CAPABILITY_AREA) 0x00000003)
+#define TPM_SET_STCLEAR_DATA ((TPM_CAPABILITY_AREA) 0x00000004)
+#define TPM_SET_STANY_FLAGS ((TPM_CAPABILITY_AREA) 0x00000005)
+#define TPM_SET_STANY_DATA ((TPM_CAPABILITY_AREA) 0x00000006)
///
/// Part 2, section 21.6: TPM_CAP_VERSION_INFO
/// [size_is(vendorSpecificSize)] BYTE* vendorSpecific;
///
typedef struct tdTPM_CAP_VERSION_INFO {
- TPM_STRUCTURE_TAG tag;
- TPM_VERSION version;
- UINT16 specLevel;
- UINT8 errataRev;
- UINT8 tpmVendorID[4];
- UINT16 vendorSpecificSize;
- UINT8 *vendorSpecific;
+ TPM_STRUCTURE_TAG tag;
+ TPM_VERSION version;
+ UINT16 specLevel;
+ UINT8 errataRev;
+ UINT8 tpmVendorID[4];
+ UINT16 vendorSpecificSize;
+ UINT8 *vendorSpecific;
} TPM_CAP_VERSION_INFO;
///
/// Part 2, section 21.10: TPM_DA_ACTION_TYPE
///
typedef struct tdTPM_DA_ACTION_TYPE {
- TPM_STRUCTURE_TAG tag;
- UINT32 actions;
+ TPM_STRUCTURE_TAG tag;
+ UINT32 actions;
} TPM_DA_ACTION_TYPE;
-#define TPM_DA_ACTION_FAILURE_MODE (((UINT32)1)<<3)
-#define TPM_DA_ACTION_DEACTIVATE (((UINT32)1)<<2)
-#define TPM_DA_ACTION_DISABLE (((UINT32)1)<<1)
-#define TPM_DA_ACTION_TIMEOUT (((UINT32)1)<<0)
+#define TPM_DA_ACTION_FAILURE_MODE (((UINT32)1)<<3)
+#define TPM_DA_ACTION_DEACTIVATE (((UINT32)1)<<2)
+#define TPM_DA_ACTION_DISABLE (((UINT32)1)<<1)
+#define TPM_DA_ACTION_TIMEOUT (((UINT32)1)<<0)
///
/// Part 2, section 21.7: TPM_DA_INFO
///
typedef struct tdTPM_DA_INFO {
- TPM_STRUCTURE_TAG tag;
- TPM_DA_STATE state;
- UINT16 currentCount;
- UINT16 thresholdCount;
- TPM_DA_ACTION_TYPE actionAtThreshold;
- UINT32 actionDependValue;
- UINT32 vendorDataSize;
- UINT8 *vendorData;
+ TPM_STRUCTURE_TAG tag;
+ TPM_DA_STATE state;
+ UINT16 currentCount;
+ UINT16 thresholdCount;
+ TPM_DA_ACTION_TYPE actionAtThreshold;
+ UINT32 actionDependValue;
+ UINT32 vendorDataSize;
+ UINT8 *vendorData;
} TPM_DA_INFO;
///
/// Part 2, section 21.8: TPM_DA_INFO_LIMITED
///
typedef struct tdTPM_DA_INFO_LIMITED {
- TPM_STRUCTURE_TAG tag;
- TPM_DA_STATE state;
- TPM_DA_ACTION_TYPE actionAtThreshold;
- UINT32 vendorDataSize;
- UINT8 *vendorData;
+ TPM_STRUCTURE_TAG tag;
+ TPM_DA_STATE state;
+ TPM_DA_ACTION_TYPE actionAtThreshold;
+ UINT32 vendorDataSize;
+ UINT8 *vendorData;
} TPM_DA_INFO_LIMITED;
//
// Part 2, section 21.9: CAP_PROPERTY Subcap values for GetCapability
//
-#define TPM_DA_STATE_INACTIVE ((UINT8)0x00)
-#define TPM_DA_STATE_ACTIVE ((UINT8)0x01)
+#define TPM_DA_STATE_INACTIVE ((UINT8)0x00)
+#define TPM_DA_STATE_ACTIVE ((UINT8)0x01)
//
// Part 2, section 22: DAA Structures
@@ -2043,94 +2042,93 @@ typedef struct tdTPM_DA_INFO_LIMITED {
//
// Part 2, section 22.1: Size definitions
//
-#define TPM_DAA_SIZE_r0 (43)
-#define TPM_DAA_SIZE_r1 (43)
-#define TPM_DAA_SIZE_r2 (128)
-#define TPM_DAA_SIZE_r3 (168)
-#define TPM_DAA_SIZE_r4 (219)
-#define TPM_DAA_SIZE_NT (20)
-#define TPM_DAA_SIZE_v0 (128)
-#define TPM_DAA_SIZE_v1 (192)
-#define TPM_DAA_SIZE_NE (256)
-#define TPM_DAA_SIZE_w (256)
-#define TPM_DAA_SIZE_issuerModulus (256)
+#define TPM_DAA_SIZE_r0 (43)
+#define TPM_DAA_SIZE_r1 (43)
+#define TPM_DAA_SIZE_r2 (128)
+#define TPM_DAA_SIZE_r3 (168)
+#define TPM_DAA_SIZE_r4 (219)
+#define TPM_DAA_SIZE_NT (20)
+#define TPM_DAA_SIZE_v0 (128)
+#define TPM_DAA_SIZE_v1 (192)
+#define TPM_DAA_SIZE_NE (256)
+#define TPM_DAA_SIZE_w (256)
+#define TPM_DAA_SIZE_issuerModulus (256)
//
// Part 2, section 22.2: Constant definitions
//
-#define TPM_DAA_power0 (104)
-#define TPM_DAA_power1 (1024)
+#define TPM_DAA_power0 (104)
+#define TPM_DAA_power1 (1024)
///
/// Part 2, section 22.3: TPM_DAA_ISSUER
///
typedef struct tdTPM_DAA_ISSUER {
- TPM_STRUCTURE_TAG tag;
- TPM_DIGEST DAA_digest_R0;
- TPM_DIGEST DAA_digest_R1;
- TPM_DIGEST DAA_digest_S0;
- TPM_DIGEST DAA_digest_S1;
- TPM_DIGEST DAA_digest_n;
- TPM_DIGEST DAA_digest_gamma;
- UINT8 DAA_generic_q[26];
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST DAA_digest_R0;
+ TPM_DIGEST DAA_digest_R1;
+ TPM_DIGEST DAA_digest_S0;
+ TPM_DIGEST DAA_digest_S1;
+ TPM_DIGEST DAA_digest_n;
+ TPM_DIGEST DAA_digest_gamma;
+ UINT8 DAA_generic_q[26];
} TPM_DAA_ISSUER;
///
/// Part 2, section 22.4: TPM_DAA_TPM
///
typedef struct tdTPM_DAA_TPM {
- TPM_STRUCTURE_TAG tag;
- TPM_DIGEST DAA_digestIssuer;
- TPM_DIGEST DAA_digest_v0;
- TPM_DIGEST DAA_digest_v1;
- TPM_DIGEST DAA_rekey;
- UINT32 DAA_count;
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST DAA_digestIssuer;
+ TPM_DIGEST DAA_digest_v0;
+ TPM_DIGEST DAA_digest_v1;
+ TPM_DIGEST DAA_rekey;
+ UINT32 DAA_count;
} TPM_DAA_TPM;
///
/// Part 2, section 22.5: TPM_DAA_CONTEXT
///
typedef struct tdTPM_DAA_CONTEXT {
- TPM_STRUCTURE_TAG tag;
- TPM_DIGEST DAA_digestContext;
- TPM_DIGEST DAA_digest;
- TPM_DAA_CONTEXT_SEED DAA_contextSeed;
- UINT8 DAA_scratch[256];
- UINT8 DAA_stage;
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST DAA_digestContext;
+ TPM_DIGEST DAA_digest;
+ TPM_DAA_CONTEXT_SEED DAA_contextSeed;
+ UINT8 DAA_scratch[256];
+ UINT8 DAA_stage;
} TPM_DAA_CONTEXT;
///
/// Part 2, section 22.6: TPM_DAA_JOINDATA
///
typedef struct tdTPM_DAA_JOINDATA {
- UINT8 DAA_join_u0[128];
- UINT8 DAA_join_u1[138];
- TPM_DIGEST DAA_digest_n0;
+ UINT8 DAA_join_u0[128];
+ UINT8 DAA_join_u1[138];
+ TPM_DIGEST DAA_digest_n0;
} TPM_DAA_JOINDATA;
///
/// Part 2, section 22.8: TPM_DAA_BLOB
///
typedef struct tdTPM_DAA_BLOB {
- TPM_STRUCTURE_TAG tag;
- TPM_RESOURCE_TYPE resourceType;
- UINT8 label[16];
- TPM_DIGEST blobIntegrity;
- UINT32 additionalSize;
- UINT8 *additionalData;
- UINT32 sensitiveSize;
- UINT8 *sensitiveData;
+ TPM_STRUCTURE_TAG tag;
+ TPM_RESOURCE_TYPE resourceType;
+ UINT8 label[16];
+ TPM_DIGEST blobIntegrity;
+ UINT32 additionalSize;
+ UINT8 *additionalData;
+ UINT32 sensitiveSize;
+ UINT8 *sensitiveData;
} TPM_DAA_BLOB;
///
/// Part 2, section 22.9: TPM_DAA_SENSITIVE
///
typedef struct tdTPM_DAA_SENSITIVE {
- TPM_STRUCTURE_TAG tag;
- UINT32 internalSize;
- UINT8 *internalData;
+ TPM_STRUCTURE_TAG tag;
+ UINT32 internalSize;
+ UINT8 *internalData;
} TPM_DAA_SENSITIVE;
-
//
// Part 2, section 23: Redirection
//
@@ -2142,24 +2140,24 @@ typedef struct tdTPM_DAA_SENSITIVE {
/// refers to exactly one name but does not give its value. We join
/// them here.
///
-#define TPM_REDIR_GPIO (0x00000001)
+#define TPM_REDIR_GPIO (0x00000001)
///
/// TPM Command Headers defined in Part 3
///
typedef struct tdTPM_RQU_COMMAND_HDR {
- TPM_STRUCTURE_TAG tag;
- UINT32 paramSize;
- TPM_COMMAND_CODE ordinal;
+ TPM_STRUCTURE_TAG tag;
+ UINT32 paramSize;
+ TPM_COMMAND_CODE ordinal;
} TPM_RQU_COMMAND_HDR;
///
/// TPM Response Headers defined in Part 3
///
typedef struct tdTPM_RSP_COMMAND_HDR {
- TPM_STRUCTURE_TAG tag;
- UINT32 paramSize;
- TPM_RESULT returnCode;
+ TPM_STRUCTURE_TAG tag;
+ UINT32 paramSize;
+ TPM_RESULT returnCode;
} TPM_RSP_COMMAND_HDR;
#pragma pack ()
diff --git a/MdePkg/Include/IndustryStandard/Tpm20.h b/MdePkg/Include/IndustryStandard/Tpm20.h
index 39332b15..5c3e76b0 100644
--- a/MdePkg/Include/IndustryStandard/Tpm20.h
+++ b/MdePkg/Include/IndustryStandard/Tpm20.h
@@ -10,7 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
-
#ifndef _TPM20_H_
#define _TPM20_H_
@@ -21,121 +20,121 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// Annex A Algorithm Constants
// Table 205 - Defines for SHA1 Hash Values
-#define SHA1_DIGEST_SIZE 20
-#define SHA1_BLOCK_SIZE 64
+#define SHA1_DIGEST_SIZE 20
+#define SHA1_BLOCK_SIZE 64
// Table 206 - Defines for SHA256 Hash Values
-#define SHA256_DIGEST_SIZE 32
-#define SHA256_BLOCK_SIZE 64
+#define SHA256_DIGEST_SIZE 32
+#define SHA256_BLOCK_SIZE 64
// Table 207 - Defines for SHA384 Hash Values
-#define SHA384_DIGEST_SIZE 48
-#define SHA384_BLOCK_SIZE 128
+#define SHA384_DIGEST_SIZE 48
+#define SHA384_BLOCK_SIZE 128
// Table 208 - Defines for SHA512 Hash Values
-#define SHA512_DIGEST_SIZE 64
-#define SHA512_BLOCK_SIZE 128
+#define SHA512_DIGEST_SIZE 64
+#define SHA512_BLOCK_SIZE 128
// Table 209 - Defines for SM3_256 Hash Values
-#define SM3_256_DIGEST_SIZE 32
-#define SM3_256_BLOCK_SIZE 64
+#define SM3_256_DIGEST_SIZE 32
+#define SM3_256_BLOCK_SIZE 64
// Table 210 - Defines for Architectural Limits Values
-#define MAX_SESSION_NUMBER 3
+#define MAX_SESSION_NUMBER 3
// Annex B Implementation Definitions
// Table 211 - Defines for Logic Values
-#define YES 1
-#define NO 0
-#define SET 1
-#define CLEAR 0
+#define YES 1
+#define NO 0
+#define SET 1
+#define CLEAR 0
// Table 215 - Defines for RSA Algorithm Constants
-#define MAX_RSA_KEY_BITS 2048
-#define MAX_RSA_KEY_BYTES ((MAX_RSA_KEY_BITS + 7) / 8)
+#define MAX_RSA_KEY_BITS 2048
+#define MAX_RSA_KEY_BYTES ((MAX_RSA_KEY_BITS + 7) / 8)
// Table 216 - Defines for ECC Algorithm Constants
-#define MAX_ECC_KEY_BITS 256
-#define MAX_ECC_KEY_BYTES ((MAX_ECC_KEY_BITS + 7) / 8)
+#define MAX_ECC_KEY_BITS 256
+#define MAX_ECC_KEY_BYTES ((MAX_ECC_KEY_BITS + 7) / 8)
// Table 217 - Defines for AES Algorithm Constants
-#define MAX_AES_KEY_BITS 128
-#define MAX_AES_BLOCK_SIZE_BYTES 16
-#define MAX_AES_KEY_BYTES ((MAX_AES_KEY_BITS + 7) / 8)
+#define MAX_AES_KEY_BITS 128
+#define MAX_AES_BLOCK_SIZE_BYTES 16
+#define MAX_AES_KEY_BYTES ((MAX_AES_KEY_BITS + 7) / 8)
// Table 218 - Defines for SM4 Algorithm Constants
-#define MAX_SM4_KEY_BITS 128
-#define MAX_SM4_BLOCK_SIZE_BYTES 16
-#define MAX_SM4_KEY_BYTES ((MAX_SM4_KEY_BITS + 7) / 8)
+#define MAX_SM4_KEY_BITS 128
+#define MAX_SM4_BLOCK_SIZE_BYTES 16
+#define MAX_SM4_KEY_BYTES ((MAX_SM4_KEY_BITS + 7) / 8)
// Table 219 - Defines for Symmetric Algorithm Constants
-#define MAX_SYM_KEY_BITS MAX_AES_KEY_BITS
-#define MAX_SYM_KEY_BYTES MAX_AES_KEY_BYTES
-#define MAX_SYM_BLOCK_SIZE MAX_AES_BLOCK_SIZE_BYTES
+#define MAX_SYM_KEY_BITS MAX_AES_KEY_BITS
+#define MAX_SYM_KEY_BYTES MAX_AES_KEY_BYTES
+#define MAX_SYM_BLOCK_SIZE MAX_AES_BLOCK_SIZE_BYTES
// Table 220 - Defines for Implementation Values
-typedef UINT16 BSIZE;
-#define BUFFER_ALIGNMENT 4
-#define IMPLEMENTATION_PCR 24
-#define PLATFORM_PCR 24
-#define DRTM_PCR 17
-#define NUM_LOCALITIES 5
-#define MAX_HANDLE_NUM 3
-#define MAX_ACTIVE_SESSIONS 64
-typedef UINT16 CONTEXT_SLOT;
-typedef UINT64 CONTEXT_COUNTER;
-#define MAX_LOADED_SESSIONS 3
-#define MAX_SESSION_NUM 3
-#define MAX_LOADED_OBJECTS 3
-#define MIN_EVICT_OBJECTS 2
-#define PCR_SELECT_MIN ((PLATFORM_PCR + 7) / 8)
-#define PCR_SELECT_MAX ((IMPLEMENTATION_PCR + 7) / 8)
-#define NUM_POLICY_PCR_GROUP 1
-#define NUM_AUTHVALUE_PCR_GROUP 1
-#define MAX_CONTEXT_SIZE 4000
-#define MAX_DIGEST_BUFFER 1024
-#define MAX_NV_INDEX_SIZE 1024
-#define MAX_CAP_BUFFER 1024
-#define NV_MEMORY_SIZE 16384
-#define NUM_STATIC_PCR 16
-#define MAX_ALG_LIST_SIZE 64
-#define TIMER_PRESCALE 100000
-#define PRIMARY_SEED_SIZE 32
-#define CONTEXT_ENCRYPT_ALG TPM_ALG_AES
-#define CONTEXT_ENCRYPT_KEY_BITS MAX_SYM_KEY_BITS
-#define CONTEXT_ENCRYPT_KEY_BYTES ((CONTEXT_ENCRYPT_KEY_BITS + 7) / 8)
-#define CONTEXT_INTEGRITY_HASH_ALG TPM_ALG_SHA256
-#define CONTEXT_INTEGRITY_HASH_SIZE SHA256_DIGEST_SIZE
-#define PROOF_SIZE CONTEXT_INTEGRITY_HASH_SIZE
-#define NV_CLOCK_UPDATE_INTERVAL 12
-#define NUM_POLICY_PCR 1
-#define MAX_COMMAND_SIZE 4096
-#define MAX_RESPONSE_SIZE 4096
-#define ORDERLY_BITS 8
-#define MAX_ORDERLY_COUNT ((1 << ORDERLY_BITS) - 1)
-#define ALG_ID_FIRST TPM_ALG_FIRST
-#define ALG_ID_LAST TPM_ALG_LAST
-#define MAX_SYM_DATA 128
-#define MAX_RNG_ENTROPY_SIZE 64
-#define RAM_INDEX_SPACE 512
-#define RSA_DEFAULT_PUBLIC_EXPONENT 0x00010001
-#define CRT_FORMAT_RSA YES
-#define PRIVATE_VENDOR_SPECIFIC_BYTES ((MAX_RSA_KEY_BYTES / 2) * ( 3 + CRT_FORMAT_RSA * 2))
+typedef UINT16 BSIZE;
+#define BUFFER_ALIGNMENT 4
+#define IMPLEMENTATION_PCR 24
+#define PLATFORM_PCR 24
+#define DRTM_PCR 17
+#define NUM_LOCALITIES 5
+#define MAX_HANDLE_NUM 3
+#define MAX_ACTIVE_SESSIONS 64
+typedef UINT16 CONTEXT_SLOT;
+typedef UINT64 CONTEXT_COUNTER;
+#define MAX_LOADED_SESSIONS 3
+#define MAX_SESSION_NUM 3
+#define MAX_LOADED_OBJECTS 3
+#define MIN_EVICT_OBJECTS 2
+#define PCR_SELECT_MIN ((PLATFORM_PCR + 7) / 8)
+#define PCR_SELECT_MAX ((IMPLEMENTATION_PCR + 7) / 8)
+#define NUM_POLICY_PCR_GROUP 1
+#define NUM_AUTHVALUE_PCR_GROUP 1
+#define MAX_CONTEXT_SIZE 4000
+#define MAX_DIGEST_BUFFER 1024
+#define MAX_NV_INDEX_SIZE 1024
+#define MAX_CAP_BUFFER 1024
+#define NV_MEMORY_SIZE 16384
+#define NUM_STATIC_PCR 16
+#define MAX_ALG_LIST_SIZE 64
+#define TIMER_PRESCALE 100000
+#define PRIMARY_SEED_SIZE 32
+#define CONTEXT_ENCRYPT_ALG TPM_ALG_AES
+#define CONTEXT_ENCRYPT_KEY_BITS MAX_SYM_KEY_BITS
+#define CONTEXT_ENCRYPT_KEY_BYTES ((CONTEXT_ENCRYPT_KEY_BITS + 7) / 8)
+#define CONTEXT_INTEGRITY_HASH_ALG TPM_ALG_SHA256
+#define CONTEXT_INTEGRITY_HASH_SIZE SHA256_DIGEST_SIZE
+#define PROOF_SIZE CONTEXT_INTEGRITY_HASH_SIZE
+#define NV_CLOCK_UPDATE_INTERVAL 12
+#define NUM_POLICY_PCR 1
+#define MAX_COMMAND_SIZE 4096
+#define MAX_RESPONSE_SIZE 4096
+#define ORDERLY_BITS 8
+#define MAX_ORDERLY_COUNT ((1 << ORDERLY_BITS) - 1)
+#define ALG_ID_FIRST TPM_ALG_FIRST
+#define ALG_ID_LAST TPM_ALG_LAST
+#define MAX_SYM_DATA 128
+#define MAX_RNG_ENTROPY_SIZE 64
+#define RAM_INDEX_SPACE 512
+#define RSA_DEFAULT_PUBLIC_EXPONENT 0x00010001
+#define CRT_FORMAT_RSA YES
+#define PRIVATE_VENDOR_SPECIFIC_BYTES ((MAX_RSA_KEY_BYTES / 2) * ( 3 + CRT_FORMAT_RSA * 2))
// Capability related MAX_ value
-#define MAX_CAP_DATA (MAX_CAP_BUFFER - sizeof(TPM_CAP) - sizeof(UINT32))
-#define MAX_CAP_ALGS (MAX_CAP_DATA / sizeof(TPMS_ALG_PROPERTY))
-#define MAX_CAP_HANDLES (MAX_CAP_DATA / sizeof(TPM_HANDLE))
-#define MAX_CAP_CC (MAX_CAP_DATA / sizeof(TPM_CC))
-#define MAX_TPM_PROPERTIES (MAX_CAP_DATA / sizeof(TPMS_TAGGED_PROPERTY))
-#define MAX_PCR_PROPERTIES (MAX_CAP_DATA / sizeof(TPMS_TAGGED_PCR_SELECT))
-#define MAX_ECC_CURVES (MAX_CAP_DATA / sizeof(TPM_ECC_CURVE))
+#define MAX_CAP_DATA (MAX_CAP_BUFFER - sizeof(TPM_CAP) - sizeof(UINT32))
+#define MAX_CAP_ALGS (MAX_CAP_DATA / sizeof(TPMS_ALG_PROPERTY))
+#define MAX_CAP_HANDLES (MAX_CAP_DATA / sizeof(TPM_HANDLE))
+#define MAX_CAP_CC (MAX_CAP_DATA / sizeof(TPM_CC))
+#define MAX_TPM_PROPERTIES (MAX_CAP_DATA / sizeof(TPMS_TAGGED_PROPERTY))
+#define MAX_PCR_PROPERTIES (MAX_CAP_DATA / sizeof(TPMS_TAGGED_PCR_SELECT))
+#define MAX_ECC_CURVES (MAX_CAP_DATA / sizeof(TPM_ECC_CURVE))
//
// Always set 5 here, because we want to support all hash algo in BIOS.
//
-#define HASH_COUNT 5
+#define HASH_COUNT 5
// 5 Base Types
@@ -146,8 +145,8 @@ typedef UINT8 BYTE;
//
// NOTE: Comment because it has same name as TPM1.2 (value is same, so not runtime issue)
//
-//typedef UINT32 TPM_ALGORITHM_ID;
-//typedef UINT32 TPM_MODIFIER_INDICATOR;
+// typedef UINT32 TPM_ALGORITHM_ID;
+// typedef UINT32 TPM_MODIFIER_INDICATOR;
typedef UINT32 TPM_AUTHORIZATION_SIZE;
typedef UINT32 TPM_PARAMETER_SIZE;
typedef UINT16 TPM_KEY_SIZE;
@@ -157,481 +156,481 @@ typedef UINT16 TPM_KEY_BITS;
// Table 6 - TPM_GENERATED Constants
typedef UINT32 TPM_GENERATED;
-#define TPM_GENERATED_VALUE (TPM_GENERATED)(0xff544347)
+#define TPM_GENERATED_VALUE (TPM_GENERATED)(0xff544347)
// Table 7 - TPM_ALG_ID Constants
typedef UINT16 TPM_ALG_ID;
//
// NOTE: Comment some algo which has same name as TPM1.2 (value is same, so not runtime issue)
//
-#define TPM_ALG_ERROR (TPM_ALG_ID)(0x0000)
-#define TPM_ALG_FIRST (TPM_ALG_ID)(0x0001)
-//#define TPM_ALG_RSA (TPM_ALG_ID)(0x0001)
-//#define TPM_ALG_SHA (TPM_ALG_ID)(0x0004)
-#define TPM_ALG_SHA1 (TPM_ALG_ID)(0x0004)
-//#define TPM_ALG_HMAC (TPM_ALG_ID)(0x0005)
-#define TPM_ALG_AES (TPM_ALG_ID)(0x0006)
-//#define TPM_ALG_MGF1 (TPM_ALG_ID)(0x0007)
-#define TPM_ALG_KEYEDHASH (TPM_ALG_ID)(0x0008)
-//#define TPM_ALG_XOR (TPM_ALG_ID)(0x000A)
-#define TPM_ALG_SHA256 (TPM_ALG_ID)(0x000B)
-#define TPM_ALG_SHA384 (TPM_ALG_ID)(0x000C)
-#define TPM_ALG_SHA512 (TPM_ALG_ID)(0x000D)
-#define TPM_ALG_NULL (TPM_ALG_ID)(0x0010)
-#define TPM_ALG_SM3_256 (TPM_ALG_ID)(0x0012)
-#define TPM_ALG_SM4 (TPM_ALG_ID)(0x0013)
-#define TPM_ALG_RSASSA (TPM_ALG_ID)(0x0014)
-#define TPM_ALG_RSAES (TPM_ALG_ID)(0x0015)
-#define TPM_ALG_RSAPSS (TPM_ALG_ID)(0x0016)
-#define TPM_ALG_OAEP (TPM_ALG_ID)(0x0017)
-#define TPM_ALG_ECDSA (TPM_ALG_ID)(0x0018)
-#define TPM_ALG_ECDH (TPM_ALG_ID)(0x0019)
-#define TPM_ALG_ECDAA (TPM_ALG_ID)(0x001A)
-#define TPM_ALG_SM2 (TPM_ALG_ID)(0x001B)
-#define TPM_ALG_ECSCHNORR (TPM_ALG_ID)(0x001C)
-#define TPM_ALG_ECMQV (TPM_ALG_ID)(0x001D)
-#define TPM_ALG_KDF1_SP800_56a (TPM_ALG_ID)(0x0020)
-#define TPM_ALG_KDF2 (TPM_ALG_ID)(0x0021)
-#define TPM_ALG_KDF1_SP800_108 (TPM_ALG_ID)(0x0022)
-#define TPM_ALG_ECC (TPM_ALG_ID)(0x0023)
-#define TPM_ALG_SYMCIPHER (TPM_ALG_ID)(0x0025)
-#define TPM_ALG_CTR (TPM_ALG_ID)(0x0040)
-#define TPM_ALG_OFB (TPM_ALG_ID)(0x0041)
-#define TPM_ALG_CBC (TPM_ALG_ID)(0x0042)
-#define TPM_ALG_CFB (TPM_ALG_ID)(0x0043)
-#define TPM_ALG_ECB (TPM_ALG_ID)(0x0044)
-#define TPM_ALG_LAST (TPM_ALG_ID)(0x0044)
+#define TPM_ALG_ERROR (TPM_ALG_ID)(0x0000)
+#define TPM_ALG_FIRST (TPM_ALG_ID)(0x0001)
+// #define TPM_ALG_RSA (TPM_ALG_ID)(0x0001)
+// #define TPM_ALG_SHA (TPM_ALG_ID)(0x0004)
+#define TPM_ALG_SHA1 (TPM_ALG_ID)(0x0004)
+// #define TPM_ALG_HMAC (TPM_ALG_ID)(0x0005)
+#define TPM_ALG_AES (TPM_ALG_ID)(0x0006)
+// #define TPM_ALG_MGF1 (TPM_ALG_ID)(0x0007)
+#define TPM_ALG_KEYEDHASH (TPM_ALG_ID)(0x0008)
+// #define TPM_ALG_XOR (TPM_ALG_ID)(0x000A)
+#define TPM_ALG_SHA256 (TPM_ALG_ID)(0x000B)
+#define TPM_ALG_SHA384 (TPM_ALG_ID)(0x000C)
+#define TPM_ALG_SHA512 (TPM_ALG_ID)(0x000D)
+#define TPM_ALG_NULL (TPM_ALG_ID)(0x0010)
+#define TPM_ALG_SM3_256 (TPM_ALG_ID)(0x0012)
+#define TPM_ALG_SM4 (TPM_ALG_ID)(0x0013)
+#define TPM_ALG_RSASSA (TPM_ALG_ID)(0x0014)
+#define TPM_ALG_RSAES (TPM_ALG_ID)(0x0015)
+#define TPM_ALG_RSAPSS (TPM_ALG_ID)(0x0016)
+#define TPM_ALG_OAEP (TPM_ALG_ID)(0x0017)
+#define TPM_ALG_ECDSA (TPM_ALG_ID)(0x0018)
+#define TPM_ALG_ECDH (TPM_ALG_ID)(0x0019)
+#define TPM_ALG_ECDAA (TPM_ALG_ID)(0x001A)
+#define TPM_ALG_SM2 (TPM_ALG_ID)(0x001B)
+#define TPM_ALG_ECSCHNORR (TPM_ALG_ID)(0x001C)
+#define TPM_ALG_ECMQV (TPM_ALG_ID)(0x001D)
+#define TPM_ALG_KDF1_SP800_56a (TPM_ALG_ID)(0x0020)
+#define TPM_ALG_KDF2 (TPM_ALG_ID)(0x0021)
+#define TPM_ALG_KDF1_SP800_108 (TPM_ALG_ID)(0x0022)
+#define TPM_ALG_ECC (TPM_ALG_ID)(0x0023)
+#define TPM_ALG_SYMCIPHER (TPM_ALG_ID)(0x0025)
+#define TPM_ALG_CTR (TPM_ALG_ID)(0x0040)
+#define TPM_ALG_OFB (TPM_ALG_ID)(0x0041)
+#define TPM_ALG_CBC (TPM_ALG_ID)(0x0042)
+#define TPM_ALG_CFB (TPM_ALG_ID)(0x0043)
+#define TPM_ALG_ECB (TPM_ALG_ID)(0x0044)
+#define TPM_ALG_LAST (TPM_ALG_ID)(0x0044)
// Table 8 - TPM_ECC_CURVE Constants
typedef UINT16 TPM_ECC_CURVE;
-#define TPM_ECC_NONE (TPM_ECC_CURVE)(0x0000)
-#define TPM_ECC_NIST_P192 (TPM_ECC_CURVE)(0x0001)
-#define TPM_ECC_NIST_P224 (TPM_ECC_CURVE)(0x0002)
-#define TPM_ECC_NIST_P256 (TPM_ECC_CURVE)(0x0003)
-#define TPM_ECC_NIST_P384 (TPM_ECC_CURVE)(0x0004)
-#define TPM_ECC_NIST_P521 (TPM_ECC_CURVE)(0x0005)
-#define TPM_ECC_BN_P256 (TPM_ECC_CURVE)(0x0010)
-#define TPM_ECC_BN_P638 (TPM_ECC_CURVE)(0x0011)
-#define TPM_ECC_SM2_P256 (TPM_ECC_CURVE)(0x0020)
+#define TPM_ECC_NONE (TPM_ECC_CURVE)(0x0000)
+#define TPM_ECC_NIST_P192 (TPM_ECC_CURVE)(0x0001)
+#define TPM_ECC_NIST_P224 (TPM_ECC_CURVE)(0x0002)
+#define TPM_ECC_NIST_P256 (TPM_ECC_CURVE)(0x0003)
+#define TPM_ECC_NIST_P384 (TPM_ECC_CURVE)(0x0004)
+#define TPM_ECC_NIST_P521 (TPM_ECC_CURVE)(0x0005)
+#define TPM_ECC_BN_P256 (TPM_ECC_CURVE)(0x0010)
+#define TPM_ECC_BN_P638 (TPM_ECC_CURVE)(0x0011)
+#define TPM_ECC_SM2_P256 (TPM_ECC_CURVE)(0x0020)
// Table 11 - TPM_CC Constants (Numeric Order)
typedef UINT32 TPM_CC;
-#define TPM_CC_FIRST (TPM_CC)(0x0000011F)
-#define TPM_CC_PP_FIRST (TPM_CC)(0x0000011F)
-#define TPM_CC_NV_UndefineSpaceSpecial (TPM_CC)(0x0000011F)
-#define TPM_CC_EvictControl (TPM_CC)(0x00000120)
-#define TPM_CC_HierarchyControl (TPM_CC)(0x00000121)
-#define TPM_CC_NV_UndefineSpace (TPM_CC)(0x00000122)
-#define TPM_CC_ChangeEPS (TPM_CC)(0x00000124)
-#define TPM_CC_ChangePPS (TPM_CC)(0x00000125)
-#define TPM_CC_Clear (TPM_CC)(0x00000126)
-#define TPM_CC_ClearControl (TPM_CC)(0x00000127)
-#define TPM_CC_ClockSet (TPM_CC)(0x00000128)
-#define TPM_CC_HierarchyChangeAuth (TPM_CC)(0x00000129)
-#define TPM_CC_NV_DefineSpace (TPM_CC)(0x0000012A)
-#define TPM_CC_PCR_Allocate (TPM_CC)(0x0000012B)
-#define TPM_CC_PCR_SetAuthPolicy (TPM_CC)(0x0000012C)
-#define TPM_CC_PP_Commands (TPM_CC)(0x0000012D)
-#define TPM_CC_SetPrimaryPolicy (TPM_CC)(0x0000012E)
-#define TPM_CC_FieldUpgradeStart (TPM_CC)(0x0000012F)
-#define TPM_CC_ClockRateAdjust (TPM_CC)(0x00000130)
-#define TPM_CC_CreatePrimary (TPM_CC)(0x00000131)
-#define TPM_CC_NV_GlobalWriteLock (TPM_CC)(0x00000132)
-#define TPM_CC_PP_LAST (TPM_CC)(0x00000132)
-#define TPM_CC_GetCommandAuditDigest (TPM_CC)(0x00000133)
-#define TPM_CC_NV_Increment (TPM_CC)(0x00000134)
-#define TPM_CC_NV_SetBits (TPM_CC)(0x00000135)
-#define TPM_CC_NV_Extend (TPM_CC)(0x00000136)
-#define TPM_CC_NV_Write (TPM_CC)(0x00000137)
-#define TPM_CC_NV_WriteLock (TPM_CC)(0x00000138)
-#define TPM_CC_DictionaryAttackLockReset (TPM_CC)(0x00000139)
-#define TPM_CC_DictionaryAttackParameters (TPM_CC)(0x0000013A)
-#define TPM_CC_NV_ChangeAuth (TPM_CC)(0x0000013B)
-#define TPM_CC_PCR_Event (TPM_CC)(0x0000013C)
-#define TPM_CC_PCR_Reset (TPM_CC)(0x0000013D)
-#define TPM_CC_SequenceComplete (TPM_CC)(0x0000013E)
-#define TPM_CC_SetAlgorithmSet (TPM_CC)(0x0000013F)
-#define TPM_CC_SetCommandCodeAuditStatus (TPM_CC)(0x00000140)
-#define TPM_CC_FieldUpgradeData (TPM_CC)(0x00000141)
-#define TPM_CC_IncrementalSelfTest (TPM_CC)(0x00000142)
-#define TPM_CC_SelfTest (TPM_CC)(0x00000143)
-#define TPM_CC_Startup (TPM_CC)(0x00000144)
-#define TPM_CC_Shutdown (TPM_CC)(0x00000145)
-#define TPM_CC_StirRandom (TPM_CC)(0x00000146)
-#define TPM_CC_ActivateCredential (TPM_CC)(0x00000147)
-#define TPM_CC_Certify (TPM_CC)(0x00000148)
-#define TPM_CC_PolicyNV (TPM_CC)(0x00000149)
-#define TPM_CC_CertifyCreation (TPM_CC)(0x0000014A)
-#define TPM_CC_Duplicate (TPM_CC)(0x0000014B)
-#define TPM_CC_GetTime (TPM_CC)(0x0000014C)
-#define TPM_CC_GetSessionAuditDigest (TPM_CC)(0x0000014D)
-#define TPM_CC_NV_Read (TPM_CC)(0x0000014E)
-#define TPM_CC_NV_ReadLock (TPM_CC)(0x0000014F)
-#define TPM_CC_ObjectChangeAuth (TPM_CC)(0x00000150)
-#define TPM_CC_PolicySecret (TPM_CC)(0x00000151)
-#define TPM_CC_Rewrap (TPM_CC)(0x00000152)
-#define TPM_CC_Create (TPM_CC)(0x00000153)
-#define TPM_CC_ECDH_ZGen (TPM_CC)(0x00000154)
-#define TPM_CC_HMAC (TPM_CC)(0x00000155)
-#define TPM_CC_Import (TPM_CC)(0x00000156)
-#define TPM_CC_Load (TPM_CC)(0x00000157)
-#define TPM_CC_Quote (TPM_CC)(0x00000158)
-#define TPM_CC_RSA_Decrypt (TPM_CC)(0x00000159)
-#define TPM_CC_HMAC_Start (TPM_CC)(0x0000015B)
-#define TPM_CC_SequenceUpdate (TPM_CC)(0x0000015C)
-#define TPM_CC_Sign (TPM_CC)(0x0000015D)
-#define TPM_CC_Unseal (TPM_CC)(0x0000015E)
-#define TPM_CC_PolicySigned (TPM_CC)(0x00000160)
-#define TPM_CC_ContextLoad (TPM_CC)(0x00000161)
-#define TPM_CC_ContextSave (TPM_CC)(0x00000162)
-#define TPM_CC_ECDH_KeyGen (TPM_CC)(0x00000163)
-#define TPM_CC_EncryptDecrypt (TPM_CC)(0x00000164)
-#define TPM_CC_FlushContext (TPM_CC)(0x00000165)
-#define TPM_CC_LoadExternal (TPM_CC)(0x00000167)
-#define TPM_CC_MakeCredential (TPM_CC)(0x00000168)
-#define TPM_CC_NV_ReadPublic (TPM_CC)(0x00000169)
-#define TPM_CC_PolicyAuthorize (TPM_CC)(0x0000016A)
-#define TPM_CC_PolicyAuthValue (TPM_CC)(0x0000016B)
-#define TPM_CC_PolicyCommandCode (TPM_CC)(0x0000016C)
-#define TPM_CC_PolicyCounterTimer (TPM_CC)(0x0000016D)
-#define TPM_CC_PolicyCpHash (TPM_CC)(0x0000016E)
-#define TPM_CC_PolicyLocality (TPM_CC)(0x0000016F)
-#define TPM_CC_PolicyNameHash (TPM_CC)(0x00000170)
-#define TPM_CC_PolicyOR (TPM_CC)(0x00000171)
-#define TPM_CC_PolicyTicket (TPM_CC)(0x00000172)
-#define TPM_CC_ReadPublic (TPM_CC)(0x00000173)
-#define TPM_CC_RSA_Encrypt (TPM_CC)(0x00000174)
-#define TPM_CC_StartAuthSession (TPM_CC)(0x00000176)
-#define TPM_CC_VerifySignature (TPM_CC)(0x00000177)
-#define TPM_CC_ECC_Parameters (TPM_CC)(0x00000178)
-#define TPM_CC_FirmwareRead (TPM_CC)(0x00000179)
-#define TPM_CC_GetCapability (TPM_CC)(0x0000017A)
-#define TPM_CC_GetRandom (TPM_CC)(0x0000017B)
-#define TPM_CC_GetTestResult (TPM_CC)(0x0000017C)
-#define TPM_CC_Hash (TPM_CC)(0x0000017D)
-#define TPM_CC_PCR_Read (TPM_CC)(0x0000017E)
-#define TPM_CC_PolicyPCR (TPM_CC)(0x0000017F)
-#define TPM_CC_PolicyRestart (TPM_CC)(0x00000180)
-#define TPM_CC_ReadClock (TPM_CC)(0x00000181)
-#define TPM_CC_PCR_Extend (TPM_CC)(0x00000182)
-#define TPM_CC_PCR_SetAuthValue (TPM_CC)(0x00000183)
-#define TPM_CC_NV_Certify (TPM_CC)(0x00000184)
-#define TPM_CC_EventSequenceComplete (TPM_CC)(0x00000185)
-#define TPM_CC_HashSequenceStart (TPM_CC)(0x00000186)
-#define TPM_CC_PolicyPhysicalPresence (TPM_CC)(0x00000187)
-#define TPM_CC_PolicyDuplicationSelect (TPM_CC)(0x00000188)
-#define TPM_CC_PolicyGetDigest (TPM_CC)(0x00000189)
-#define TPM_CC_TestParms (TPM_CC)(0x0000018A)
-#define TPM_CC_Commit (TPM_CC)(0x0000018B)
-#define TPM_CC_PolicyPassword (TPM_CC)(0x0000018C)
-#define TPM_CC_ZGen_2Phase (TPM_CC)(0x0000018D)
-#define TPM_CC_EC_Ephemeral (TPM_CC)(0x0000018E)
-#define TPM_CC_LAST (TPM_CC)(0x0000018E)
+#define TPM_CC_FIRST (TPM_CC)(0x0000011F)
+#define TPM_CC_PP_FIRST (TPM_CC)(0x0000011F)
+#define TPM_CC_NV_UndefineSpaceSpecial (TPM_CC)(0x0000011F)
+#define TPM_CC_EvictControl (TPM_CC)(0x00000120)
+#define TPM_CC_HierarchyControl (TPM_CC)(0x00000121)
+#define TPM_CC_NV_UndefineSpace (TPM_CC)(0x00000122)
+#define TPM_CC_ChangeEPS (TPM_CC)(0x00000124)
+#define TPM_CC_ChangePPS (TPM_CC)(0x00000125)
+#define TPM_CC_Clear (TPM_CC)(0x00000126)
+#define TPM_CC_ClearControl (TPM_CC)(0x00000127)
+#define TPM_CC_ClockSet (TPM_CC)(0x00000128)
+#define TPM_CC_HierarchyChangeAuth (TPM_CC)(0x00000129)
+#define TPM_CC_NV_DefineSpace (TPM_CC)(0x0000012A)
+#define TPM_CC_PCR_Allocate (TPM_CC)(0x0000012B)
+#define TPM_CC_PCR_SetAuthPolicy (TPM_CC)(0x0000012C)
+#define TPM_CC_PP_Commands (TPM_CC)(0x0000012D)
+#define TPM_CC_SetPrimaryPolicy (TPM_CC)(0x0000012E)
+#define TPM_CC_FieldUpgradeStart (TPM_CC)(0x0000012F)
+#define TPM_CC_ClockRateAdjust (TPM_CC)(0x00000130)
+#define TPM_CC_CreatePrimary (TPM_CC)(0x00000131)
+#define TPM_CC_NV_GlobalWriteLock (TPM_CC)(0x00000132)
+#define TPM_CC_PP_LAST (TPM_CC)(0x00000132)
+#define TPM_CC_GetCommandAuditDigest (TPM_CC)(0x00000133)
+#define TPM_CC_NV_Increment (TPM_CC)(0x00000134)
+#define TPM_CC_NV_SetBits (TPM_CC)(0x00000135)
+#define TPM_CC_NV_Extend (TPM_CC)(0x00000136)
+#define TPM_CC_NV_Write (TPM_CC)(0x00000137)
+#define TPM_CC_NV_WriteLock (TPM_CC)(0x00000138)
+#define TPM_CC_DictionaryAttackLockReset (TPM_CC)(0x00000139)
+#define TPM_CC_DictionaryAttackParameters (TPM_CC)(0x0000013A)
+#define TPM_CC_NV_ChangeAuth (TPM_CC)(0x0000013B)
+#define TPM_CC_PCR_Event (TPM_CC)(0x0000013C)
+#define TPM_CC_PCR_Reset (TPM_CC)(0x0000013D)
+#define TPM_CC_SequenceComplete (TPM_CC)(0x0000013E)
+#define TPM_CC_SetAlgorithmSet (TPM_CC)(0x0000013F)
+#define TPM_CC_SetCommandCodeAuditStatus (TPM_CC)(0x00000140)
+#define TPM_CC_FieldUpgradeData (TPM_CC)(0x00000141)
+#define TPM_CC_IncrementalSelfTest (TPM_CC)(0x00000142)
+#define TPM_CC_SelfTest (TPM_CC)(0x00000143)
+#define TPM_CC_Startup (TPM_CC)(0x00000144)
+#define TPM_CC_Shutdown (TPM_CC)(0x00000145)
+#define TPM_CC_StirRandom (TPM_CC)(0x00000146)
+#define TPM_CC_ActivateCredential (TPM_CC)(0x00000147)
+#define TPM_CC_Certify (TPM_CC)(0x00000148)
+#define TPM_CC_PolicyNV (TPM_CC)(0x00000149)
+#define TPM_CC_CertifyCreation (TPM_CC)(0x0000014A)
+#define TPM_CC_Duplicate (TPM_CC)(0x0000014B)
+#define TPM_CC_GetTime (TPM_CC)(0x0000014C)
+#define TPM_CC_GetSessionAuditDigest (TPM_CC)(0x0000014D)
+#define TPM_CC_NV_Read (TPM_CC)(0x0000014E)
+#define TPM_CC_NV_ReadLock (TPM_CC)(0x0000014F)
+#define TPM_CC_ObjectChangeAuth (TPM_CC)(0x00000150)
+#define TPM_CC_PolicySecret (TPM_CC)(0x00000151)
+#define TPM_CC_Rewrap (TPM_CC)(0x00000152)
+#define TPM_CC_Create (TPM_CC)(0x00000153)
+#define TPM_CC_ECDH_ZGen (TPM_CC)(0x00000154)
+#define TPM_CC_HMAC (TPM_CC)(0x00000155)
+#define TPM_CC_Import (TPM_CC)(0x00000156)
+#define TPM_CC_Load (TPM_CC)(0x00000157)
+#define TPM_CC_Quote (TPM_CC)(0x00000158)
+#define TPM_CC_RSA_Decrypt (TPM_CC)(0x00000159)
+#define TPM_CC_HMAC_Start (TPM_CC)(0x0000015B)
+#define TPM_CC_SequenceUpdate (TPM_CC)(0x0000015C)
+#define TPM_CC_Sign (TPM_CC)(0x0000015D)
+#define TPM_CC_Unseal (TPM_CC)(0x0000015E)
+#define TPM_CC_PolicySigned (TPM_CC)(0x00000160)
+#define TPM_CC_ContextLoad (TPM_CC)(0x00000161)
+#define TPM_CC_ContextSave (TPM_CC)(0x00000162)
+#define TPM_CC_ECDH_KeyGen (TPM_CC)(0x00000163)
+#define TPM_CC_EncryptDecrypt (TPM_CC)(0x00000164)
+#define TPM_CC_FlushContext (TPM_CC)(0x00000165)
+#define TPM_CC_LoadExternal (TPM_CC)(0x00000167)
+#define TPM_CC_MakeCredential (TPM_CC)(0x00000168)
+#define TPM_CC_NV_ReadPublic (TPM_CC)(0x00000169)
+#define TPM_CC_PolicyAuthorize (TPM_CC)(0x0000016A)
+#define TPM_CC_PolicyAuthValue (TPM_CC)(0x0000016B)
+#define TPM_CC_PolicyCommandCode (TPM_CC)(0x0000016C)
+#define TPM_CC_PolicyCounterTimer (TPM_CC)(0x0000016D)
+#define TPM_CC_PolicyCpHash (TPM_CC)(0x0000016E)
+#define TPM_CC_PolicyLocality (TPM_CC)(0x0000016F)
+#define TPM_CC_PolicyNameHash (TPM_CC)(0x00000170)
+#define TPM_CC_PolicyOR (TPM_CC)(0x00000171)
+#define TPM_CC_PolicyTicket (TPM_CC)(0x00000172)
+#define TPM_CC_ReadPublic (TPM_CC)(0x00000173)
+#define TPM_CC_RSA_Encrypt (TPM_CC)(0x00000174)
+#define TPM_CC_StartAuthSession (TPM_CC)(0x00000176)
+#define TPM_CC_VerifySignature (TPM_CC)(0x00000177)
+#define TPM_CC_ECC_Parameters (TPM_CC)(0x00000178)
+#define TPM_CC_FirmwareRead (TPM_CC)(0x00000179)
+#define TPM_CC_GetCapability (TPM_CC)(0x0000017A)
+#define TPM_CC_GetRandom (TPM_CC)(0x0000017B)
+#define TPM_CC_GetTestResult (TPM_CC)(0x0000017C)
+#define TPM_CC_Hash (TPM_CC)(0x0000017D)
+#define TPM_CC_PCR_Read (TPM_CC)(0x0000017E)
+#define TPM_CC_PolicyPCR (TPM_CC)(0x0000017F)
+#define TPM_CC_PolicyRestart (TPM_CC)(0x00000180)
+#define TPM_CC_ReadClock (TPM_CC)(0x00000181)
+#define TPM_CC_PCR_Extend (TPM_CC)(0x00000182)
+#define TPM_CC_PCR_SetAuthValue (TPM_CC)(0x00000183)
+#define TPM_CC_NV_Certify (TPM_CC)(0x00000184)
+#define TPM_CC_EventSequenceComplete (TPM_CC)(0x00000185)
+#define TPM_CC_HashSequenceStart (TPM_CC)(0x00000186)
+#define TPM_CC_PolicyPhysicalPresence (TPM_CC)(0x00000187)
+#define TPM_CC_PolicyDuplicationSelect (TPM_CC)(0x00000188)
+#define TPM_CC_PolicyGetDigest (TPM_CC)(0x00000189)
+#define TPM_CC_TestParms (TPM_CC)(0x0000018A)
+#define TPM_CC_Commit (TPM_CC)(0x0000018B)
+#define TPM_CC_PolicyPassword (TPM_CC)(0x0000018C)
+#define TPM_CC_ZGen_2Phase (TPM_CC)(0x0000018D)
+#define TPM_CC_EC_Ephemeral (TPM_CC)(0x0000018E)
+#define TPM_CC_LAST (TPM_CC)(0x0000018E)
// Table 15 - TPM_RC Constants (Actions)
typedef UINT32 TPM_RC;
-#define TPM_RC_SUCCESS (TPM_RC)(0x000)
-#define TPM_RC_BAD_TAG (TPM_RC)(0x030)
-#define RC_VER1 (TPM_RC)(0x100)
-#define TPM_RC_INITIALIZE (TPM_RC)(RC_VER1 + 0x000)
-#define TPM_RC_FAILURE (TPM_RC)(RC_VER1 + 0x001)
-#define TPM_RC_SEQUENCE (TPM_RC)(RC_VER1 + 0x003)
-#define TPM_RC_PRIVATE (TPM_RC)(RC_VER1 + 0x00B)
-#define TPM_RC_HMAC (TPM_RC)(RC_VER1 + 0x019)
-#define TPM_RC_DISABLED (TPM_RC)(RC_VER1 + 0x020)
-#define TPM_RC_EXCLUSIVE (TPM_RC)(RC_VER1 + 0x021)
-#define TPM_RC_AUTH_TYPE (TPM_RC)(RC_VER1 + 0x024)
-#define TPM_RC_AUTH_MISSING (TPM_RC)(RC_VER1 + 0x025)
-#define TPM_RC_POLICY (TPM_RC)(RC_VER1 + 0x026)
-#define TPM_RC_PCR (TPM_RC)(RC_VER1 + 0x027)
-#define TPM_RC_PCR_CHANGED (TPM_RC)(RC_VER1 + 0x028)
-#define TPM_RC_UPGRADE (TPM_RC)(RC_VER1 + 0x02D)
-#define TPM_RC_TOO_MANY_CONTEXTS (TPM_RC)(RC_VER1 + 0x02E)
-#define TPM_RC_AUTH_UNAVAILABLE (TPM_RC)(RC_VER1 + 0x02F)
-#define TPM_RC_REBOOT (TPM_RC)(RC_VER1 + 0x030)
-#define TPM_RC_UNBALANCED (TPM_RC)(RC_VER1 + 0x031)
-#define TPM_RC_COMMAND_SIZE (TPM_RC)(RC_VER1 + 0x042)
-#define TPM_RC_COMMAND_CODE (TPM_RC)(RC_VER1 + 0x043)
-#define TPM_RC_AUTHSIZE (TPM_RC)(RC_VER1 + 0x044)
-#define TPM_RC_AUTH_CONTEXT (TPM_RC)(RC_VER1 + 0x045)
-#define TPM_RC_NV_RANGE (TPM_RC)(RC_VER1 + 0x046)
-#define TPM_RC_NV_SIZE (TPM_RC)(RC_VER1 + 0x047)
-#define TPM_RC_NV_LOCKED (TPM_RC)(RC_VER1 + 0x048)
-#define TPM_RC_NV_AUTHORIZATION (TPM_RC)(RC_VER1 + 0x049)
-#define TPM_RC_NV_UNINITIALIZED (TPM_RC)(RC_VER1 + 0x04A)
-#define TPM_RC_NV_SPACE (TPM_RC)(RC_VER1 + 0x04B)
-#define TPM_RC_NV_DEFINED (TPM_RC)(RC_VER1 + 0x04C)
-#define TPM_RC_BAD_CONTEXT (TPM_RC)(RC_VER1 + 0x050)
-#define TPM_RC_CPHASH (TPM_RC)(RC_VER1 + 0x051)
-#define TPM_RC_PARENT (TPM_RC)(RC_VER1 + 0x052)
-#define TPM_RC_NEEDS_TEST (TPM_RC)(RC_VER1 + 0x053)
-#define TPM_RC_NO_RESULT (TPM_RC)(RC_VER1 + 0x054)
-#define TPM_RC_SENSITIVE (TPM_RC)(RC_VER1 + 0x055)
-#define RC_MAX_FM0 (TPM_RC)(RC_VER1 + 0x07F)
-#define RC_FMT1 (TPM_RC)(0x080)
-#define TPM_RC_ASYMMETRIC (TPM_RC)(RC_FMT1 + 0x001)
-#define TPM_RC_ATTRIBUTES (TPM_RC)(RC_FMT1 + 0x002)
-#define TPM_RC_HASH (TPM_RC)(RC_FMT1 + 0x003)
-#define TPM_RC_VALUE (TPM_RC)(RC_FMT1 + 0x004)
-#define TPM_RC_HIERARCHY (TPM_RC)(RC_FMT1 + 0x005)
-#define TPM_RC_KEY_SIZE (TPM_RC)(RC_FMT1 + 0x007)
-#define TPM_RC_MGF (TPM_RC)(RC_FMT1 + 0x008)
-#define TPM_RC_MODE (TPM_RC)(RC_FMT1 + 0x009)
-#define TPM_RC_TYPE (TPM_RC)(RC_FMT1 + 0x00A)
-#define TPM_RC_HANDLE (TPM_RC)(RC_FMT1 + 0x00B)
-#define TPM_RC_KDF (TPM_RC)(RC_FMT1 + 0x00C)
-#define TPM_RC_RANGE (TPM_RC)(RC_FMT1 + 0x00D)
-#define TPM_RC_AUTH_FAIL (TPM_RC)(RC_FMT1 + 0x00E)
-#define TPM_RC_NONCE (TPM_RC)(RC_FMT1 + 0x00F)
-#define TPM_RC_PP (TPM_RC)(RC_FMT1 + 0x010)
-#define TPM_RC_SCHEME (TPM_RC)(RC_FMT1 + 0x012)
-#define TPM_RC_SIZE (TPM_RC)(RC_FMT1 + 0x015)
-#define TPM_RC_SYMMETRIC (TPM_RC)(RC_FMT1 + 0x016)
-#define TPM_RC_TAG (TPM_RC)(RC_FMT1 + 0x017)
-#define TPM_RC_SELECTOR (TPM_RC)(RC_FMT1 + 0x018)
-#define TPM_RC_INSUFFICIENT (TPM_RC)(RC_FMT1 + 0x01A)
-#define TPM_RC_SIGNATURE (TPM_RC)(RC_FMT1 + 0x01B)
-#define TPM_RC_KEY (TPM_RC)(RC_FMT1 + 0x01C)
-#define TPM_RC_POLICY_FAIL (TPM_RC)(RC_FMT1 + 0x01D)
-#define TPM_RC_INTEGRITY (TPM_RC)(RC_FMT1 + 0x01F)
-#define TPM_RC_TICKET (TPM_RC)(RC_FMT1 + 0x020)
-#define TPM_RC_RESERVED_BITS (TPM_RC)(RC_FMT1 + 0x021)
-#define TPM_RC_BAD_AUTH (TPM_RC)(RC_FMT1 + 0x022)
-#define TPM_RC_EXPIRED (TPM_RC)(RC_FMT1 + 0x023)
-#define TPM_RC_POLICY_CC (TPM_RC)(RC_FMT1 + 0x024 )
-#define TPM_RC_BINDING (TPM_RC)(RC_FMT1 + 0x025)
-#define TPM_RC_CURVE (TPM_RC)(RC_FMT1 + 0x026)
-#define TPM_RC_ECC_POINT (TPM_RC)(RC_FMT1 + 0x027)
-#define RC_WARN (TPM_RC)(0x900)
-#define TPM_RC_CONTEXT_GAP (TPM_RC)(RC_WARN + 0x001)
-#define TPM_RC_OBJECT_MEMORY (TPM_RC)(RC_WARN + 0x002)
-#define TPM_RC_SESSION_MEMORY (TPM_RC)(RC_WARN + 0x003)
-#define TPM_RC_MEMORY (TPM_RC)(RC_WARN + 0x004)
-#define TPM_RC_SESSION_HANDLES (TPM_RC)(RC_WARN + 0x005)
-#define TPM_RC_OBJECT_HANDLES (TPM_RC)(RC_WARN + 0x006)
-#define TPM_RC_LOCALITY (TPM_RC)(RC_WARN + 0x007)
-#define TPM_RC_YIELDED (TPM_RC)(RC_WARN + 0x008)
-#define TPM_RC_CANCELED (TPM_RC)(RC_WARN + 0x009)
-#define TPM_RC_TESTING (TPM_RC)(RC_WARN + 0x00A)
-#define TPM_RC_REFERENCE_H0 (TPM_RC)(RC_WARN + 0x010)
-#define TPM_RC_REFERENCE_H1 (TPM_RC)(RC_WARN + 0x011)
-#define TPM_RC_REFERENCE_H2 (TPM_RC)(RC_WARN + 0x012)
-#define TPM_RC_REFERENCE_H3 (TPM_RC)(RC_WARN + 0x013)
-#define TPM_RC_REFERENCE_H4 (TPM_RC)(RC_WARN + 0x014)
-#define TPM_RC_REFERENCE_H5 (TPM_RC)(RC_WARN + 0x015)
-#define TPM_RC_REFERENCE_H6 (TPM_RC)(RC_WARN + 0x016)
-#define TPM_RC_REFERENCE_S0 (TPM_RC)(RC_WARN + 0x018)
-#define TPM_RC_REFERENCE_S1 (TPM_RC)(RC_WARN + 0x019)
-#define TPM_RC_REFERENCE_S2 (TPM_RC)(RC_WARN + 0x01A)
-#define TPM_RC_REFERENCE_S3 (TPM_RC)(RC_WARN + 0x01B)
-#define TPM_RC_REFERENCE_S4 (TPM_RC)(RC_WARN + 0x01C)
-#define TPM_RC_REFERENCE_S5 (TPM_RC)(RC_WARN + 0x01D)
-#define TPM_RC_REFERENCE_S6 (TPM_RC)(RC_WARN + 0x01E)
-#define TPM_RC_NV_RATE (TPM_RC)(RC_WARN + 0x020)
-#define TPM_RC_LOCKOUT (TPM_RC)(RC_WARN + 0x021)
-#define TPM_RC_RETRY (TPM_RC)(RC_WARN + 0x022)
-#define TPM_RC_NV_UNAVAILABLE (TPM_RC)(RC_WARN + 0x023)
-#define TPM_RC_NOT_USED (TPM_RC)(RC_WARN + 0x7F)
-#define TPM_RC_H (TPM_RC)(0x000)
-#define TPM_RC_P (TPM_RC)(0x040)
-#define TPM_RC_S (TPM_RC)(0x800)
-#define TPM_RC_1 (TPM_RC)(0x100)
-#define TPM_RC_2 (TPM_RC)(0x200)
-#define TPM_RC_3 (TPM_RC)(0x300)
-#define TPM_RC_4 (TPM_RC)(0x400)
-#define TPM_RC_5 (TPM_RC)(0x500)
-#define TPM_RC_6 (TPM_RC)(0x600)
-#define TPM_RC_7 (TPM_RC)(0x700)
-#define TPM_RC_8 (TPM_RC)(0x800)
-#define TPM_RC_9 (TPM_RC)(0x900)
-#define TPM_RC_A (TPM_RC)(0xA00)
-#define TPM_RC_B (TPM_RC)(0xB00)
-#define TPM_RC_C (TPM_RC)(0xC00)
-#define TPM_RC_D (TPM_RC)(0xD00)
-#define TPM_RC_E (TPM_RC)(0xE00)
-#define TPM_RC_F (TPM_RC)(0xF00)
-#define TPM_RC_N_MASK (TPM_RC)(0xF00)
+#define TPM_RC_SUCCESS (TPM_RC)(0x000)
+#define TPM_RC_BAD_TAG (TPM_RC)(0x030)
+#define RC_VER1 (TPM_RC)(0x100)
+#define TPM_RC_INITIALIZE (TPM_RC)(RC_VER1 + 0x000)
+#define TPM_RC_FAILURE (TPM_RC)(RC_VER1 + 0x001)
+#define TPM_RC_SEQUENCE (TPM_RC)(RC_VER1 + 0x003)
+#define TPM_RC_PRIVATE (TPM_RC)(RC_VER1 + 0x00B)
+#define TPM_RC_HMAC (TPM_RC)(RC_VER1 + 0x019)
+#define TPM_RC_DISABLED (TPM_RC)(RC_VER1 + 0x020)
+#define TPM_RC_EXCLUSIVE (TPM_RC)(RC_VER1 + 0x021)
+#define TPM_RC_AUTH_TYPE (TPM_RC)(RC_VER1 + 0x024)
+#define TPM_RC_AUTH_MISSING (TPM_RC)(RC_VER1 + 0x025)
+#define TPM_RC_POLICY (TPM_RC)(RC_VER1 + 0x026)
+#define TPM_RC_PCR (TPM_RC)(RC_VER1 + 0x027)
+#define TPM_RC_PCR_CHANGED (TPM_RC)(RC_VER1 + 0x028)
+#define TPM_RC_UPGRADE (TPM_RC)(RC_VER1 + 0x02D)
+#define TPM_RC_TOO_MANY_CONTEXTS (TPM_RC)(RC_VER1 + 0x02E)
+#define TPM_RC_AUTH_UNAVAILABLE (TPM_RC)(RC_VER1 + 0x02F)
+#define TPM_RC_REBOOT (TPM_RC)(RC_VER1 + 0x030)
+#define TPM_RC_UNBALANCED (TPM_RC)(RC_VER1 + 0x031)
+#define TPM_RC_COMMAND_SIZE (TPM_RC)(RC_VER1 + 0x042)
+#define TPM_RC_COMMAND_CODE (TPM_RC)(RC_VER1 + 0x043)
+#define TPM_RC_AUTHSIZE (TPM_RC)(RC_VER1 + 0x044)
+#define TPM_RC_AUTH_CONTEXT (TPM_RC)(RC_VER1 + 0x045)
+#define TPM_RC_NV_RANGE (TPM_RC)(RC_VER1 + 0x046)
+#define TPM_RC_NV_SIZE (TPM_RC)(RC_VER1 + 0x047)
+#define TPM_RC_NV_LOCKED (TPM_RC)(RC_VER1 + 0x048)
+#define TPM_RC_NV_AUTHORIZATION (TPM_RC)(RC_VER1 + 0x049)
+#define TPM_RC_NV_UNINITIALIZED (TPM_RC)(RC_VER1 + 0x04A)
+#define TPM_RC_NV_SPACE (TPM_RC)(RC_VER1 + 0x04B)
+#define TPM_RC_NV_DEFINED (TPM_RC)(RC_VER1 + 0x04C)
+#define TPM_RC_BAD_CONTEXT (TPM_RC)(RC_VER1 + 0x050)
+#define TPM_RC_CPHASH (TPM_RC)(RC_VER1 + 0x051)
+#define TPM_RC_PARENT (TPM_RC)(RC_VER1 + 0x052)
+#define TPM_RC_NEEDS_TEST (TPM_RC)(RC_VER1 + 0x053)
+#define TPM_RC_NO_RESULT (TPM_RC)(RC_VER1 + 0x054)
+#define TPM_RC_SENSITIVE (TPM_RC)(RC_VER1 + 0x055)
+#define RC_MAX_FM0 (TPM_RC)(RC_VER1 + 0x07F)
+#define RC_FMT1 (TPM_RC)(0x080)
+#define TPM_RC_ASYMMETRIC (TPM_RC)(RC_FMT1 + 0x001)
+#define TPM_RC_ATTRIBUTES (TPM_RC)(RC_FMT1 + 0x002)
+#define TPM_RC_HASH (TPM_RC)(RC_FMT1 + 0x003)
+#define TPM_RC_VALUE (TPM_RC)(RC_FMT1 + 0x004)
+#define TPM_RC_HIERARCHY (TPM_RC)(RC_FMT1 + 0x005)
+#define TPM_RC_KEY_SIZE (TPM_RC)(RC_FMT1 + 0x007)
+#define TPM_RC_MGF (TPM_RC)(RC_FMT1 + 0x008)
+#define TPM_RC_MODE (TPM_RC)(RC_FMT1 + 0x009)
+#define TPM_RC_TYPE (TPM_RC)(RC_FMT1 + 0x00A)
+#define TPM_RC_HANDLE (TPM_RC)(RC_FMT1 + 0x00B)
+#define TPM_RC_KDF (TPM_RC)(RC_FMT1 + 0x00C)
+#define TPM_RC_RANGE (TPM_RC)(RC_FMT1 + 0x00D)
+#define TPM_RC_AUTH_FAIL (TPM_RC)(RC_FMT1 + 0x00E)
+#define TPM_RC_NONCE (TPM_RC)(RC_FMT1 + 0x00F)
+#define TPM_RC_PP (TPM_RC)(RC_FMT1 + 0x010)
+#define TPM_RC_SCHEME (TPM_RC)(RC_FMT1 + 0x012)
+#define TPM_RC_SIZE (TPM_RC)(RC_FMT1 + 0x015)
+#define TPM_RC_SYMMETRIC (TPM_RC)(RC_FMT1 + 0x016)
+#define TPM_RC_TAG (TPM_RC)(RC_FMT1 + 0x017)
+#define TPM_RC_SELECTOR (TPM_RC)(RC_FMT1 + 0x018)
+#define TPM_RC_INSUFFICIENT (TPM_RC)(RC_FMT1 + 0x01A)
+#define TPM_RC_SIGNATURE (TPM_RC)(RC_FMT1 + 0x01B)
+#define TPM_RC_KEY (TPM_RC)(RC_FMT1 + 0x01C)
+#define TPM_RC_POLICY_FAIL (TPM_RC)(RC_FMT1 + 0x01D)
+#define TPM_RC_INTEGRITY (TPM_RC)(RC_FMT1 + 0x01F)
+#define TPM_RC_TICKET (TPM_RC)(RC_FMT1 + 0x020)
+#define TPM_RC_RESERVED_BITS (TPM_RC)(RC_FMT1 + 0x021)
+#define TPM_RC_BAD_AUTH (TPM_RC)(RC_FMT1 + 0x022)
+#define TPM_RC_EXPIRED (TPM_RC)(RC_FMT1 + 0x023)
+#define TPM_RC_POLICY_CC (TPM_RC)(RC_FMT1 + 0x024 )
+#define TPM_RC_BINDING (TPM_RC)(RC_FMT1 + 0x025)
+#define TPM_RC_CURVE (TPM_RC)(RC_FMT1 + 0x026)
+#define TPM_RC_ECC_POINT (TPM_RC)(RC_FMT1 + 0x027)
+#define RC_WARN (TPM_RC)(0x900)
+#define TPM_RC_CONTEXT_GAP (TPM_RC)(RC_WARN + 0x001)
+#define TPM_RC_OBJECT_MEMORY (TPM_RC)(RC_WARN + 0x002)
+#define TPM_RC_SESSION_MEMORY (TPM_RC)(RC_WARN + 0x003)
+#define TPM_RC_MEMORY (TPM_RC)(RC_WARN + 0x004)
+#define TPM_RC_SESSION_HANDLES (TPM_RC)(RC_WARN + 0x005)
+#define TPM_RC_OBJECT_HANDLES (TPM_RC)(RC_WARN + 0x006)
+#define TPM_RC_LOCALITY (TPM_RC)(RC_WARN + 0x007)
+#define TPM_RC_YIELDED (TPM_RC)(RC_WARN + 0x008)
+#define TPM_RC_CANCELED (TPM_RC)(RC_WARN + 0x009)
+#define TPM_RC_TESTING (TPM_RC)(RC_WARN + 0x00A)
+#define TPM_RC_REFERENCE_H0 (TPM_RC)(RC_WARN + 0x010)
+#define TPM_RC_REFERENCE_H1 (TPM_RC)(RC_WARN + 0x011)
+#define TPM_RC_REFERENCE_H2 (TPM_RC)(RC_WARN + 0x012)
+#define TPM_RC_REFERENCE_H3 (TPM_RC)(RC_WARN + 0x013)
+#define TPM_RC_REFERENCE_H4 (TPM_RC)(RC_WARN + 0x014)
+#define TPM_RC_REFERENCE_H5 (TPM_RC)(RC_WARN + 0x015)
+#define TPM_RC_REFERENCE_H6 (TPM_RC)(RC_WARN + 0x016)
+#define TPM_RC_REFERENCE_S0 (TPM_RC)(RC_WARN + 0x018)
+#define TPM_RC_REFERENCE_S1 (TPM_RC)(RC_WARN + 0x019)
+#define TPM_RC_REFERENCE_S2 (TPM_RC)(RC_WARN + 0x01A)
+#define TPM_RC_REFERENCE_S3 (TPM_RC)(RC_WARN + 0x01B)
+#define TPM_RC_REFERENCE_S4 (TPM_RC)(RC_WARN + 0x01C)
+#define TPM_RC_REFERENCE_S5 (TPM_RC)(RC_WARN + 0x01D)
+#define TPM_RC_REFERENCE_S6 (TPM_RC)(RC_WARN + 0x01E)
+#define TPM_RC_NV_RATE (TPM_RC)(RC_WARN + 0x020)
+#define TPM_RC_LOCKOUT (TPM_RC)(RC_WARN + 0x021)
+#define TPM_RC_RETRY (TPM_RC)(RC_WARN + 0x022)
+#define TPM_RC_NV_UNAVAILABLE (TPM_RC)(RC_WARN + 0x023)
+#define TPM_RC_NOT_USED (TPM_RC)(RC_WARN + 0x7F)
+#define TPM_RC_H (TPM_RC)(0x000)
+#define TPM_RC_P (TPM_RC)(0x040)
+#define TPM_RC_S (TPM_RC)(0x800)
+#define TPM_RC_1 (TPM_RC)(0x100)
+#define TPM_RC_2 (TPM_RC)(0x200)
+#define TPM_RC_3 (TPM_RC)(0x300)
+#define TPM_RC_4 (TPM_RC)(0x400)
+#define TPM_RC_5 (TPM_RC)(0x500)
+#define TPM_RC_6 (TPM_RC)(0x600)
+#define TPM_RC_7 (TPM_RC)(0x700)
+#define TPM_RC_8 (TPM_RC)(0x800)
+#define TPM_RC_9 (TPM_RC)(0x900)
+#define TPM_RC_A (TPM_RC)(0xA00)
+#define TPM_RC_B (TPM_RC)(0xB00)
+#define TPM_RC_C (TPM_RC)(0xC00)
+#define TPM_RC_D (TPM_RC)(0xD00)
+#define TPM_RC_E (TPM_RC)(0xE00)
+#define TPM_RC_F (TPM_RC)(0xF00)
+#define TPM_RC_N_MASK (TPM_RC)(0xF00)
// Table 16 - TPM_CLOCK_ADJUST Constants
typedef INT8 TPM_CLOCK_ADJUST;
-#define TPM_CLOCK_COARSE_SLOWER (TPM_CLOCK_ADJUST)(-3)
-#define TPM_CLOCK_MEDIUM_SLOWER (TPM_CLOCK_ADJUST)(-2)
-#define TPM_CLOCK_FINE_SLOWER (TPM_CLOCK_ADJUST)(-1)
-#define TPM_CLOCK_NO_CHANGE (TPM_CLOCK_ADJUST)(0)
-#define TPM_CLOCK_FINE_FASTER (TPM_CLOCK_ADJUST)(1)
-#define TPM_CLOCK_MEDIUM_FASTER (TPM_CLOCK_ADJUST)(2)
-#define TPM_CLOCK_COARSE_FASTER (TPM_CLOCK_ADJUST)(3)
+#define TPM_CLOCK_COARSE_SLOWER (TPM_CLOCK_ADJUST)(-3)
+#define TPM_CLOCK_MEDIUM_SLOWER (TPM_CLOCK_ADJUST)(-2)
+#define TPM_CLOCK_FINE_SLOWER (TPM_CLOCK_ADJUST)(-1)
+#define TPM_CLOCK_NO_CHANGE (TPM_CLOCK_ADJUST)(0)
+#define TPM_CLOCK_FINE_FASTER (TPM_CLOCK_ADJUST)(1)
+#define TPM_CLOCK_MEDIUM_FASTER (TPM_CLOCK_ADJUST)(2)
+#define TPM_CLOCK_COARSE_FASTER (TPM_CLOCK_ADJUST)(3)
// Table 17 - TPM_EO Constants
typedef UINT16 TPM_EO;
-#define TPM_EO_EQ (TPM_EO)(0x0000)
-#define TPM_EO_NEQ (TPM_EO)(0x0001)
-#define TPM_EO_SIGNED_GT (TPM_EO)(0x0002)
-#define TPM_EO_UNSIGNED_GT (TPM_EO)(0x0003)
-#define TPM_EO_SIGNED_LT (TPM_EO)(0x0004)
-#define TPM_EO_UNSIGNED_LT (TPM_EO)(0x0005)
-#define TPM_EO_SIGNED_GE (TPM_EO)(0x0006)
-#define TPM_EO_UNSIGNED_GE (TPM_EO)(0x0007)
-#define TPM_EO_SIGNED_LE (TPM_EO)(0x0008)
-#define TPM_EO_UNSIGNED_LE (TPM_EO)(0x0009)
-#define TPM_EO_BITSET (TPM_EO)(0x000A)
-#define TPM_EO_BITCLEAR (TPM_EO)(0x000B)
+#define TPM_EO_EQ (TPM_EO)(0x0000)
+#define TPM_EO_NEQ (TPM_EO)(0x0001)
+#define TPM_EO_SIGNED_GT (TPM_EO)(0x0002)
+#define TPM_EO_UNSIGNED_GT (TPM_EO)(0x0003)
+#define TPM_EO_SIGNED_LT (TPM_EO)(0x0004)
+#define TPM_EO_UNSIGNED_LT (TPM_EO)(0x0005)
+#define TPM_EO_SIGNED_GE (TPM_EO)(0x0006)
+#define TPM_EO_UNSIGNED_GE (TPM_EO)(0x0007)
+#define TPM_EO_SIGNED_LE (TPM_EO)(0x0008)
+#define TPM_EO_UNSIGNED_LE (TPM_EO)(0x0009)
+#define TPM_EO_BITSET (TPM_EO)(0x000A)
+#define TPM_EO_BITCLEAR (TPM_EO)(0x000B)
// Table 18 - TPM_ST Constants
typedef UINT16 TPM_ST;
-#define TPM_ST_RSP_COMMAND (TPM_ST)(0x00C4)
-#define TPM_ST_NULL (TPM_ST)(0X8000)
-#define TPM_ST_NO_SESSIONS (TPM_ST)(0x8001)
-#define TPM_ST_SESSIONS (TPM_ST)(0x8002)
-#define TPM_ST_ATTEST_NV (TPM_ST)(0x8014)
-#define TPM_ST_ATTEST_COMMAND_AUDIT (TPM_ST)(0x8015)
-#define TPM_ST_ATTEST_SESSION_AUDIT (TPM_ST)(0x8016)
-#define TPM_ST_ATTEST_CERTIFY (TPM_ST)(0x8017)
-#define TPM_ST_ATTEST_QUOTE (TPM_ST)(0x8018)
-#define TPM_ST_ATTEST_TIME (TPM_ST)(0x8019)
-#define TPM_ST_ATTEST_CREATION (TPM_ST)(0x801A)
-#define TPM_ST_CREATION (TPM_ST)(0x8021)
-#define TPM_ST_VERIFIED (TPM_ST)(0x8022)
-#define TPM_ST_AUTH_SECRET (TPM_ST)(0x8023)
-#define TPM_ST_HASHCHECK (TPM_ST)(0x8024)
-#define TPM_ST_AUTH_SIGNED (TPM_ST)(0x8025)
-#define TPM_ST_FU_MANIFEST (TPM_ST)(0x8029)
+#define TPM_ST_RSP_COMMAND (TPM_ST)(0x00C4)
+#define TPM_ST_NULL (TPM_ST)(0X8000)
+#define TPM_ST_NO_SESSIONS (TPM_ST)(0x8001)
+#define TPM_ST_SESSIONS (TPM_ST)(0x8002)
+#define TPM_ST_ATTEST_NV (TPM_ST)(0x8014)
+#define TPM_ST_ATTEST_COMMAND_AUDIT (TPM_ST)(0x8015)
+#define TPM_ST_ATTEST_SESSION_AUDIT (TPM_ST)(0x8016)
+#define TPM_ST_ATTEST_CERTIFY (TPM_ST)(0x8017)
+#define TPM_ST_ATTEST_QUOTE (TPM_ST)(0x8018)
+#define TPM_ST_ATTEST_TIME (TPM_ST)(0x8019)
+#define TPM_ST_ATTEST_CREATION (TPM_ST)(0x801A)
+#define TPM_ST_CREATION (TPM_ST)(0x8021)
+#define TPM_ST_VERIFIED (TPM_ST)(0x8022)
+#define TPM_ST_AUTH_SECRET (TPM_ST)(0x8023)
+#define TPM_ST_HASHCHECK (TPM_ST)(0x8024)
+#define TPM_ST_AUTH_SIGNED (TPM_ST)(0x8025)
+#define TPM_ST_FU_MANIFEST (TPM_ST)(0x8029)
// Table 19 - TPM_SU Constants
typedef UINT16 TPM_SU;
-#define TPM_SU_CLEAR (TPM_SU)(0x0000)
-#define TPM_SU_STATE (TPM_SU)(0x0001)
+#define TPM_SU_CLEAR (TPM_SU)(0x0000)
+#define TPM_SU_STATE (TPM_SU)(0x0001)
// Table 20 - TPM_SE Constants
typedef UINT8 TPM_SE;
-#define TPM_SE_HMAC (TPM_SE)(0x00)
-#define TPM_SE_POLICY (TPM_SE)(0x01)
-#define TPM_SE_TRIAL (TPM_SE)(0x03)
+#define TPM_SE_HMAC (TPM_SE)(0x00)
+#define TPM_SE_POLICY (TPM_SE)(0x01)
+#define TPM_SE_TRIAL (TPM_SE)(0x03)
// Table 21 - TPM_CAP Constants
typedef UINT32 TPM_CAP;
-#define TPM_CAP_FIRST (TPM_CAP)(0x00000000)
-#define TPM_CAP_ALGS (TPM_CAP)(0x00000000)
-#define TPM_CAP_HANDLES (TPM_CAP)(0x00000001)
-#define TPM_CAP_COMMANDS (TPM_CAP)(0x00000002)
-#define TPM_CAP_PP_COMMANDS (TPM_CAP)(0x00000003)
-#define TPM_CAP_AUDIT_COMMANDS (TPM_CAP)(0x00000004)
-#define TPM_CAP_PCRS (TPM_CAP)(0x00000005)
-#define TPM_CAP_TPM_PROPERTIES (TPM_CAP)(0x00000006)
-#define TPM_CAP_PCR_PROPERTIES (TPM_CAP)(0x00000007)
-#define TPM_CAP_ECC_CURVES (TPM_CAP)(0x00000008)
-#define TPM_CAP_LAST (TPM_CAP)(0x00000008)
-#define TPM_CAP_VENDOR_PROPERTY (TPM_CAP)(0x00000100)
+#define TPM_CAP_FIRST (TPM_CAP)(0x00000000)
+#define TPM_CAP_ALGS (TPM_CAP)(0x00000000)
+#define TPM_CAP_HANDLES (TPM_CAP)(0x00000001)
+#define TPM_CAP_COMMANDS (TPM_CAP)(0x00000002)
+#define TPM_CAP_PP_COMMANDS (TPM_CAP)(0x00000003)
+#define TPM_CAP_AUDIT_COMMANDS (TPM_CAP)(0x00000004)
+#define TPM_CAP_PCRS (TPM_CAP)(0x00000005)
+#define TPM_CAP_TPM_PROPERTIES (TPM_CAP)(0x00000006)
+#define TPM_CAP_PCR_PROPERTIES (TPM_CAP)(0x00000007)
+#define TPM_CAP_ECC_CURVES (TPM_CAP)(0x00000008)
+#define TPM_CAP_LAST (TPM_CAP)(0x00000008)
+#define TPM_CAP_VENDOR_PROPERTY (TPM_CAP)(0x00000100)
// Table 22 - TPM_PT Constants
typedef UINT32 TPM_PT;
-#define TPM_PT_NONE (TPM_PT)(0x00000000)
-#define PT_GROUP (TPM_PT)(0x00000100)
-#define PT_FIXED (TPM_PT)(PT_GROUP * 1)
-#define TPM_PT_FAMILY_INDICATOR (TPM_PT)(PT_FIXED + 0)
-#define TPM_PT_LEVEL (TPM_PT)(PT_FIXED + 1)
-#define TPM_PT_REVISION (TPM_PT)(PT_FIXED + 2)
-#define TPM_PT_DAY_OF_YEAR (TPM_PT)(PT_FIXED + 3)
-#define TPM_PT_YEAR (TPM_PT)(PT_FIXED + 4)
-#define TPM_PT_MANUFACTURER (TPM_PT)(PT_FIXED + 5)
-#define TPM_PT_VENDOR_STRING_1 (TPM_PT)(PT_FIXED + 6)
-#define TPM_PT_VENDOR_STRING_2 (TPM_PT)(PT_FIXED + 7)
-#define TPM_PT_VENDOR_STRING_3 (TPM_PT)(PT_FIXED + 8)
-#define TPM_PT_VENDOR_STRING_4 (TPM_PT)(PT_FIXED + 9)
-#define TPM_PT_VENDOR_TPM_TYPE (TPM_PT)(PT_FIXED + 10)
-#define TPM_PT_FIRMWARE_VERSION_1 (TPM_PT)(PT_FIXED + 11)
-#define TPM_PT_FIRMWARE_VERSION_2 (TPM_PT)(PT_FIXED + 12)
-#define TPM_PT_INPUT_BUFFER (TPM_PT)(PT_FIXED + 13)
-#define TPM_PT_HR_TRANSIENT_MIN (TPM_PT)(PT_FIXED + 14)
-#define TPM_PT_HR_PERSISTENT_MIN (TPM_PT)(PT_FIXED + 15)
-#define TPM_PT_HR_LOADED_MIN (TPM_PT)(PT_FIXED + 16)
-#define TPM_PT_ACTIVE_SESSIONS_MAX (TPM_PT)(PT_FIXED + 17)
-#define TPM_PT_PCR_COUNT (TPM_PT)(PT_FIXED + 18)
-#define TPM_PT_PCR_SELECT_MIN (TPM_PT)(PT_FIXED + 19)
-#define TPM_PT_CONTEXT_GAP_MAX (TPM_PT)(PT_FIXED + 20)
-#define TPM_PT_NV_COUNTERS_MAX (TPM_PT)(PT_FIXED + 22)
-#define TPM_PT_NV_INDEX_MAX (TPM_PT)(PT_FIXED + 23)
-#define TPM_PT_MEMORY (TPM_PT)(PT_FIXED + 24)
-#define TPM_PT_CLOCK_UPDATE (TPM_PT)(PT_FIXED + 25)
-#define TPM_PT_CONTEXT_HASH (TPM_PT)(PT_FIXED + 26)
-#define TPM_PT_CONTEXT_SYM (TPM_PT)(PT_FIXED + 27)
-#define TPM_PT_CONTEXT_SYM_SIZE (TPM_PT)(PT_FIXED + 28)
-#define TPM_PT_ORDERLY_COUNT (TPM_PT)(PT_FIXED + 29)
-#define TPM_PT_MAX_COMMAND_SIZE (TPM_PT)(PT_FIXED + 30)
-#define TPM_PT_MAX_RESPONSE_SIZE (TPM_PT)(PT_FIXED + 31)
-#define TPM_PT_MAX_DIGEST (TPM_PT)(PT_FIXED + 32)
-#define TPM_PT_MAX_OBJECT_CONTEXT (TPM_PT)(PT_FIXED + 33)
-#define TPM_PT_MAX_SESSION_CONTEXT (TPM_PT)(PT_FIXED + 34)
-#define TPM_PT_PS_FAMILY_INDICATOR (TPM_PT)(PT_FIXED + 35)
-#define TPM_PT_PS_LEVEL (TPM_PT)(PT_FIXED + 36)
-#define TPM_PT_PS_REVISION (TPM_PT)(PT_FIXED + 37)
-#define TPM_PT_PS_DAY_OF_YEAR (TPM_PT)(PT_FIXED + 38)
-#define TPM_PT_PS_YEAR (TPM_PT)(PT_FIXED + 39)
-#define TPM_PT_SPLIT_MAX (TPM_PT)(PT_FIXED + 40)
-#define TPM_PT_TOTAL_COMMANDS (TPM_PT)(PT_FIXED + 41)
-#define TPM_PT_LIBRARY_COMMANDS (TPM_PT)(PT_FIXED + 42)
-#define TPM_PT_VENDOR_COMMANDS (TPM_PT)(PT_FIXED + 43)
-#define PT_VAR (TPM_PT)(PT_GROUP * 2)
-#define TPM_PT_PERMANENT (TPM_PT)(PT_VAR + 0)
-#define TPM_PT_STARTUP_CLEAR (TPM_PT)(PT_VAR + 1)
-#define TPM_PT_HR_NV_INDEX (TPM_PT)(PT_VAR + 2)
-#define TPM_PT_HR_LOADED (TPM_PT)(PT_VAR + 3)
-#define TPM_PT_HR_LOADED_AVAIL (TPM_PT)(PT_VAR + 4)
-#define TPM_PT_HR_ACTIVE (TPM_PT)(PT_VAR + 5)
-#define TPM_PT_HR_ACTIVE_AVAIL (TPM_PT)(PT_VAR + 6)
-#define TPM_PT_HR_TRANSIENT_AVAIL (TPM_PT)(PT_VAR + 7)
-#define TPM_PT_HR_PERSISTENT (TPM_PT)(PT_VAR + 8)
-#define TPM_PT_HR_PERSISTENT_AVAIL (TPM_PT)(PT_VAR + 9)
-#define TPM_PT_NV_COUNTERS (TPM_PT)(PT_VAR + 10)
-#define TPM_PT_NV_COUNTERS_AVAIL (TPM_PT)(PT_VAR + 11)
-#define TPM_PT_ALGORITHM_SET (TPM_PT)(PT_VAR + 12)
-#define TPM_PT_LOADED_CURVES (TPM_PT)(PT_VAR + 13)
-#define TPM_PT_LOCKOUT_COUNTER (TPM_PT)(PT_VAR + 14)
-#define TPM_PT_MAX_AUTH_FAIL (TPM_PT)(PT_VAR + 15)
-#define TPM_PT_LOCKOUT_INTERVAL (TPM_PT)(PT_VAR + 16)
-#define TPM_PT_LOCKOUT_RECOVERY (TPM_PT)(PT_VAR + 17)
-#define TPM_PT_NV_WRITE_RECOVERY (TPM_PT)(PT_VAR + 18)
-#define TPM_PT_AUDIT_COUNTER_0 (TPM_PT)(PT_VAR + 19)
-#define TPM_PT_AUDIT_COUNTER_1 (TPM_PT)(PT_VAR + 20)
+#define TPM_PT_NONE (TPM_PT)(0x00000000)
+#define PT_GROUP (TPM_PT)(0x00000100)
+#define PT_FIXED (TPM_PT)(PT_GROUP * 1)
+#define TPM_PT_FAMILY_INDICATOR (TPM_PT)(PT_FIXED + 0)
+#define TPM_PT_LEVEL (TPM_PT)(PT_FIXED + 1)
+#define TPM_PT_REVISION (TPM_PT)(PT_FIXED + 2)
+#define TPM_PT_DAY_OF_YEAR (TPM_PT)(PT_FIXED + 3)
+#define TPM_PT_YEAR (TPM_PT)(PT_FIXED + 4)
+#define TPM_PT_MANUFACTURER (TPM_PT)(PT_FIXED + 5)
+#define TPM_PT_VENDOR_STRING_1 (TPM_PT)(PT_FIXED + 6)
+#define TPM_PT_VENDOR_STRING_2 (TPM_PT)(PT_FIXED + 7)
+#define TPM_PT_VENDOR_STRING_3 (TPM_PT)(PT_FIXED + 8)
+#define TPM_PT_VENDOR_STRING_4 (TPM_PT)(PT_FIXED + 9)
+#define TPM_PT_VENDOR_TPM_TYPE (TPM_PT)(PT_FIXED + 10)
+#define TPM_PT_FIRMWARE_VERSION_1 (TPM_PT)(PT_FIXED + 11)
+#define TPM_PT_FIRMWARE_VERSION_2 (TPM_PT)(PT_FIXED + 12)
+#define TPM_PT_INPUT_BUFFER (TPM_PT)(PT_FIXED + 13)
+#define TPM_PT_HR_TRANSIENT_MIN (TPM_PT)(PT_FIXED + 14)
+#define TPM_PT_HR_PERSISTENT_MIN (TPM_PT)(PT_FIXED + 15)
+#define TPM_PT_HR_LOADED_MIN (TPM_PT)(PT_FIXED + 16)
+#define TPM_PT_ACTIVE_SESSIONS_MAX (TPM_PT)(PT_FIXED + 17)
+#define TPM_PT_PCR_COUNT (TPM_PT)(PT_FIXED + 18)
+#define TPM_PT_PCR_SELECT_MIN (TPM_PT)(PT_FIXED + 19)
+#define TPM_PT_CONTEXT_GAP_MAX (TPM_PT)(PT_FIXED + 20)
+#define TPM_PT_NV_COUNTERS_MAX (TPM_PT)(PT_FIXED + 22)
+#define TPM_PT_NV_INDEX_MAX (TPM_PT)(PT_FIXED + 23)
+#define TPM_PT_MEMORY (TPM_PT)(PT_FIXED + 24)
+#define TPM_PT_CLOCK_UPDATE (TPM_PT)(PT_FIXED + 25)
+#define TPM_PT_CONTEXT_HASH (TPM_PT)(PT_FIXED + 26)
+#define TPM_PT_CONTEXT_SYM (TPM_PT)(PT_FIXED + 27)
+#define TPM_PT_CONTEXT_SYM_SIZE (TPM_PT)(PT_FIXED + 28)
+#define TPM_PT_ORDERLY_COUNT (TPM_PT)(PT_FIXED + 29)
+#define TPM_PT_MAX_COMMAND_SIZE (TPM_PT)(PT_FIXED + 30)
+#define TPM_PT_MAX_RESPONSE_SIZE (TPM_PT)(PT_FIXED + 31)
+#define TPM_PT_MAX_DIGEST (TPM_PT)(PT_FIXED + 32)
+#define TPM_PT_MAX_OBJECT_CONTEXT (TPM_PT)(PT_FIXED + 33)
+#define TPM_PT_MAX_SESSION_CONTEXT (TPM_PT)(PT_FIXED + 34)
+#define TPM_PT_PS_FAMILY_INDICATOR (TPM_PT)(PT_FIXED + 35)
+#define TPM_PT_PS_LEVEL (TPM_PT)(PT_FIXED + 36)
+#define TPM_PT_PS_REVISION (TPM_PT)(PT_FIXED + 37)
+#define TPM_PT_PS_DAY_OF_YEAR (TPM_PT)(PT_FIXED + 38)
+#define TPM_PT_PS_YEAR (TPM_PT)(PT_FIXED + 39)
+#define TPM_PT_SPLIT_MAX (TPM_PT)(PT_FIXED + 40)
+#define TPM_PT_TOTAL_COMMANDS (TPM_PT)(PT_FIXED + 41)
+#define TPM_PT_LIBRARY_COMMANDS (TPM_PT)(PT_FIXED + 42)
+#define TPM_PT_VENDOR_COMMANDS (TPM_PT)(PT_FIXED + 43)
+#define PT_VAR (TPM_PT)(PT_GROUP * 2)
+#define TPM_PT_PERMANENT (TPM_PT)(PT_VAR + 0)
+#define TPM_PT_STARTUP_CLEAR (TPM_PT)(PT_VAR + 1)
+#define TPM_PT_HR_NV_INDEX (TPM_PT)(PT_VAR + 2)
+#define TPM_PT_HR_LOADED (TPM_PT)(PT_VAR + 3)
+#define TPM_PT_HR_LOADED_AVAIL (TPM_PT)(PT_VAR + 4)
+#define TPM_PT_HR_ACTIVE (TPM_PT)(PT_VAR + 5)
+#define TPM_PT_HR_ACTIVE_AVAIL (TPM_PT)(PT_VAR + 6)
+#define TPM_PT_HR_TRANSIENT_AVAIL (TPM_PT)(PT_VAR + 7)
+#define TPM_PT_HR_PERSISTENT (TPM_PT)(PT_VAR + 8)
+#define TPM_PT_HR_PERSISTENT_AVAIL (TPM_PT)(PT_VAR + 9)
+#define TPM_PT_NV_COUNTERS (TPM_PT)(PT_VAR + 10)
+#define TPM_PT_NV_COUNTERS_AVAIL (TPM_PT)(PT_VAR + 11)
+#define TPM_PT_ALGORITHM_SET (TPM_PT)(PT_VAR + 12)
+#define TPM_PT_LOADED_CURVES (TPM_PT)(PT_VAR + 13)
+#define TPM_PT_LOCKOUT_COUNTER (TPM_PT)(PT_VAR + 14)
+#define TPM_PT_MAX_AUTH_FAIL (TPM_PT)(PT_VAR + 15)
+#define TPM_PT_LOCKOUT_INTERVAL (TPM_PT)(PT_VAR + 16)
+#define TPM_PT_LOCKOUT_RECOVERY (TPM_PT)(PT_VAR + 17)
+#define TPM_PT_NV_WRITE_RECOVERY (TPM_PT)(PT_VAR + 18)
+#define TPM_PT_AUDIT_COUNTER_0 (TPM_PT)(PT_VAR + 19)
+#define TPM_PT_AUDIT_COUNTER_1 (TPM_PT)(PT_VAR + 20)
// Table 23 - TPM_PT_PCR Constants
typedef UINT32 TPM_PT_PCR;
-#define TPM_PT_PCR_FIRST (TPM_PT_PCR)(0x00000000)
-#define TPM_PT_PCR_SAVE (TPM_PT_PCR)(0x00000000)
-#define TPM_PT_PCR_EXTEND_L0 (TPM_PT_PCR)(0x00000001)
-#define TPM_PT_PCR_RESET_L0 (TPM_PT_PCR)(0x00000002)
-#define TPM_PT_PCR_EXTEND_L1 (TPM_PT_PCR)(0x00000003)
-#define TPM_PT_PCR_RESET_L1 (TPM_PT_PCR)(0x00000004)
-#define TPM_PT_PCR_EXTEND_L2 (TPM_PT_PCR)(0x00000005)
-#define TPM_PT_PCR_RESET_L2 (TPM_PT_PCR)(0x00000006)
-#define TPM_PT_PCR_EXTEND_L3 (TPM_PT_PCR)(0x00000007)
-#define TPM_PT_PCR_RESET_L3 (TPM_PT_PCR)(0x00000008)
-#define TPM_PT_PCR_EXTEND_L4 (TPM_PT_PCR)(0x00000009)
-#define TPM_PT_PCR_RESET_L4 (TPM_PT_PCR)(0x0000000A)
-#define TPM_PT_PCR_NO_INCREMENT (TPM_PT_PCR)(0x00000011)
-#define TPM_PT_PCR_DRTM_RESET (TPM_PT_PCR)(0x00000012)
-#define TPM_PT_PCR_POLICY (TPM_PT_PCR)(0x00000013)
-#define TPM_PT_PCR_AUTH (TPM_PT_PCR)(0x00000014)
-#define TPM_PT_PCR_LAST (TPM_PT_PCR)(0x00000014)
+#define TPM_PT_PCR_FIRST (TPM_PT_PCR)(0x00000000)
+#define TPM_PT_PCR_SAVE (TPM_PT_PCR)(0x00000000)
+#define TPM_PT_PCR_EXTEND_L0 (TPM_PT_PCR)(0x00000001)
+#define TPM_PT_PCR_RESET_L0 (TPM_PT_PCR)(0x00000002)
+#define TPM_PT_PCR_EXTEND_L1 (TPM_PT_PCR)(0x00000003)
+#define TPM_PT_PCR_RESET_L1 (TPM_PT_PCR)(0x00000004)
+#define TPM_PT_PCR_EXTEND_L2 (TPM_PT_PCR)(0x00000005)
+#define TPM_PT_PCR_RESET_L2 (TPM_PT_PCR)(0x00000006)
+#define TPM_PT_PCR_EXTEND_L3 (TPM_PT_PCR)(0x00000007)
+#define TPM_PT_PCR_RESET_L3 (TPM_PT_PCR)(0x00000008)
+#define TPM_PT_PCR_EXTEND_L4 (TPM_PT_PCR)(0x00000009)
+#define TPM_PT_PCR_RESET_L4 (TPM_PT_PCR)(0x0000000A)
+#define TPM_PT_PCR_NO_INCREMENT (TPM_PT_PCR)(0x00000011)
+#define TPM_PT_PCR_DRTM_RESET (TPM_PT_PCR)(0x00000012)
+#define TPM_PT_PCR_POLICY (TPM_PT_PCR)(0x00000013)
+#define TPM_PT_PCR_AUTH (TPM_PT_PCR)(0x00000014)
+#define TPM_PT_PCR_LAST (TPM_PT_PCR)(0x00000014)
// Table 24 - TPM_PS Constants
typedef UINT32 TPM_PS;
-#define TPM_PS_MAIN (TPM_PS)(0x00000000)
-#define TPM_PS_PC (TPM_PS)(0x00000001)
-#define TPM_PS_PDA (TPM_PS)(0x00000002)
-#define TPM_PS_CELL_PHONE (TPM_PS)(0x00000003)
-#define TPM_PS_SERVER (TPM_PS)(0x00000004)
-#define TPM_PS_PERIPHERAL (TPM_PS)(0x00000005)
-#define TPM_PS_TSS (TPM_PS)(0x00000006)
-#define TPM_PS_STORAGE (TPM_PS)(0x00000007)
-#define TPM_PS_AUTHENTICATION (TPM_PS)(0x00000008)
-#define TPM_PS_EMBEDDED (TPM_PS)(0x00000009)
-#define TPM_PS_HARDCOPY (TPM_PS)(0x0000000A)
-#define TPM_PS_INFRASTRUCTURE (TPM_PS)(0x0000000B)
-#define TPM_PS_VIRTUALIZATION (TPM_PS)(0x0000000C)
-#define TPM_PS_TNC (TPM_PS)(0x0000000D)
-#define TPM_PS_MULTI_TENANT (TPM_PS)(0x0000000E)
-#define TPM_PS_TC (TPM_PS)(0x0000000F)
+#define TPM_PS_MAIN (TPM_PS)(0x00000000)
+#define TPM_PS_PC (TPM_PS)(0x00000001)
+#define TPM_PS_PDA (TPM_PS)(0x00000002)
+#define TPM_PS_CELL_PHONE (TPM_PS)(0x00000003)
+#define TPM_PS_SERVER (TPM_PS)(0x00000004)
+#define TPM_PS_PERIPHERAL (TPM_PS)(0x00000005)
+#define TPM_PS_TSS (TPM_PS)(0x00000006)
+#define TPM_PS_STORAGE (TPM_PS)(0x00000007)
+#define TPM_PS_AUTHENTICATION (TPM_PS)(0x00000008)
+#define TPM_PS_EMBEDDED (TPM_PS)(0x00000009)
+#define TPM_PS_HARDCOPY (TPM_PS)(0x0000000A)
+#define TPM_PS_INFRASTRUCTURE (TPM_PS)(0x0000000B)
+#define TPM_PS_VIRTUALIZATION (TPM_PS)(0x0000000C)
+#define TPM_PS_TNC (TPM_PS)(0x0000000D)
+#define TPM_PS_MULTI_TENANT (TPM_PS)(0x0000000E)
+#define TPM_PS_TC (TPM_PS)(0x0000000F)
// 7 Handles
@@ -639,117 +638,117 @@ typedef UINT32 TPM_PS;
//
// NOTE: Comment because it has same name as TPM1.2 (value is same, so not runtime issue)
//
-//typedef UINT32 TPM_HANDLE;
+// typedef UINT32 TPM_HANDLE;
// Table 26 - TPM_HT Constants
typedef UINT8 TPM_HT;
-#define TPM_HT_PCR (TPM_HT)(0x00)
-#define TPM_HT_NV_INDEX (TPM_HT)(0x01)
-#define TPM_HT_HMAC_SESSION (TPM_HT)(0x02)
-#define TPM_HT_LOADED_SESSION (TPM_HT)(0x02)
-#define TPM_HT_POLICY_SESSION (TPM_HT)(0x03)
-#define TPM_HT_ACTIVE_SESSION (TPM_HT)(0x03)
-#define TPM_HT_PERMANENT (TPM_HT)(0x40)
-#define TPM_HT_TRANSIENT (TPM_HT)(0x80)
-#define TPM_HT_PERSISTENT (TPM_HT)(0x81)
+#define TPM_HT_PCR (TPM_HT)(0x00)
+#define TPM_HT_NV_INDEX (TPM_HT)(0x01)
+#define TPM_HT_HMAC_SESSION (TPM_HT)(0x02)
+#define TPM_HT_LOADED_SESSION (TPM_HT)(0x02)
+#define TPM_HT_POLICY_SESSION (TPM_HT)(0x03)
+#define TPM_HT_ACTIVE_SESSION (TPM_HT)(0x03)
+#define TPM_HT_PERMANENT (TPM_HT)(0x40)
+#define TPM_HT_TRANSIENT (TPM_HT)(0x80)
+#define TPM_HT_PERSISTENT (TPM_HT)(0x81)
// Table 27 - TPM_RH Constants
typedef UINT32 TPM_RH;
-#define TPM_RH_FIRST (TPM_RH)(0x40000000)
-#define TPM_RH_SRK (TPM_RH)(0x40000000)
-#define TPM_RH_OWNER (TPM_RH)(0x40000001)
-#define TPM_RH_REVOKE (TPM_RH)(0x40000002)
-#define TPM_RH_TRANSPORT (TPM_RH)(0x40000003)
-#define TPM_RH_OPERATOR (TPM_RH)(0x40000004)
-#define TPM_RH_ADMIN (TPM_RH)(0x40000005)
-#define TPM_RH_EK (TPM_RH)(0x40000006)
-#define TPM_RH_NULL (TPM_RH)(0x40000007)
-#define TPM_RH_UNASSIGNED (TPM_RH)(0x40000008)
-#define TPM_RS_PW (TPM_RH)(0x40000009)
-#define TPM_RH_LOCKOUT (TPM_RH)(0x4000000A)
-#define TPM_RH_ENDORSEMENT (TPM_RH)(0x4000000B)
-#define TPM_RH_PLATFORM (TPM_RH)(0x4000000C)
-#define TPM_RH_PLATFORM_NV (TPM_RH)(0x4000000D)
-#define TPM_RH_AUTH_00 (TPM_RH)(0x40000010)
-#define TPM_RH_AUTH_FF (TPM_RH)(0x4000010F)
-#define TPM_RH_LAST (TPM_RH)(0x4000010F)
+#define TPM_RH_FIRST (TPM_RH)(0x40000000)
+#define TPM_RH_SRK (TPM_RH)(0x40000000)
+#define TPM_RH_OWNER (TPM_RH)(0x40000001)
+#define TPM_RH_REVOKE (TPM_RH)(0x40000002)
+#define TPM_RH_TRANSPORT (TPM_RH)(0x40000003)
+#define TPM_RH_OPERATOR (TPM_RH)(0x40000004)
+#define TPM_RH_ADMIN (TPM_RH)(0x40000005)
+#define TPM_RH_EK (TPM_RH)(0x40000006)
+#define TPM_RH_NULL (TPM_RH)(0x40000007)
+#define TPM_RH_UNASSIGNED (TPM_RH)(0x40000008)
+#define TPM_RS_PW (TPM_RH)(0x40000009)
+#define TPM_RH_LOCKOUT (TPM_RH)(0x4000000A)
+#define TPM_RH_ENDORSEMENT (TPM_RH)(0x4000000B)
+#define TPM_RH_PLATFORM (TPM_RH)(0x4000000C)
+#define TPM_RH_PLATFORM_NV (TPM_RH)(0x4000000D)
+#define TPM_RH_AUTH_00 (TPM_RH)(0x40000010)
+#define TPM_RH_AUTH_FF (TPM_RH)(0x4000010F)
+#define TPM_RH_LAST (TPM_RH)(0x4000010F)
// Table 28 - TPM_HC Constants
typedef TPM_HANDLE TPM_HC;
-#define HR_HANDLE_MASK (TPM_HC)(0x00FFFFFF)
-#define HR_RANGE_MASK (TPM_HC)(0xFF000000)
-#define HR_SHIFT (TPM_HC)(24)
-#define HR_PCR (TPM_HC)((TPM_HC)TPM_HT_PCR << HR_SHIFT)
-#define HR_HMAC_SESSION (TPM_HC)((TPM_HC)TPM_HT_HMAC_SESSION << HR_SHIFT)
-#define HR_POLICY_SESSION (TPM_HC)((TPM_HC)TPM_HT_POLICY_SESSION << HR_SHIFT)
-#define HR_TRANSIENT (TPM_HC)((TPM_HC)TPM_HT_TRANSIENT << HR_SHIFT)
-#define HR_PERSISTENT (TPM_HC)((TPM_HC)TPM_HT_PERSISTENT << HR_SHIFT)
-#define HR_NV_INDEX (TPM_HC)((TPM_HC)TPM_HT_NV_INDEX << HR_SHIFT)
-#define HR_PERMANENT (TPM_HC)((TPM_HC)TPM_HT_PERMANENT << HR_SHIFT)
-#define PCR_FIRST (TPM_HC)(HR_PCR + 0)
-#define PCR_LAST (TPM_HC)(PCR_FIRST + IMPLEMENTATION_PCR - 1)
-#define HMAC_SESSION_FIRST (TPM_HC)(HR_HMAC_SESSION + 0)
-#define HMAC_SESSION_LAST (TPM_HC)(HMAC_SESSION_FIRST + MAX_ACTIVE_SESSIONS - 1)
-#define LOADED_SESSION_FIRST (TPM_HC)(HMAC_SESSION_FIRST)
-#define LOADED_SESSION_LAST (TPM_HC)(HMAC_SESSION_LAST)
-#define POLICY_SESSION_FIRST (TPM_HC)(HR_POLICY_SESSION + 0)
-#define POLICY_SESSION_LAST (TPM_HC)(POLICY_SESSION_FIRST + MAX_ACTIVE_SESSIONS - 1)
-#define TRANSIENT_FIRST (TPM_HC)(HR_TRANSIENT + 0)
-#define ACTIVE_SESSION_FIRST (TPM_HC)(POLICY_SESSION_FIRST)
-#define ACTIVE_SESSION_LAST (TPM_HC)(POLICY_SESSION_LAST)
-#define TRANSIENT_LAST (TPM_HC)(TRANSIENT_FIRST+MAX_LOADED_OBJECTS - 1)
-#define PERSISTENT_FIRST (TPM_HC)(HR_PERSISTENT + 0)
-#define PERSISTENT_LAST (TPM_HC)(PERSISTENT_FIRST + 0x00FFFFFF)
-#define PLATFORM_PERSISTENT (TPM_HC)(PERSISTENT_FIRST + 0x00800000)
-#define NV_INDEX_FIRST (TPM_HC)(HR_NV_INDEX + 0)
-#define NV_INDEX_LAST (TPM_HC)(NV_INDEX_FIRST + 0x00FFFFFF)
-#define PERMANENT_FIRST (TPM_HC)(TPM_RH_FIRST)
-#define PERMANENT_LAST (TPM_HC)(TPM_RH_LAST)
+#define HR_HANDLE_MASK (TPM_HC)(0x00FFFFFF)
+#define HR_RANGE_MASK (TPM_HC)(0xFF000000)
+#define HR_SHIFT (TPM_HC)(24)
+#define HR_PCR (TPM_HC)((TPM_HC)TPM_HT_PCR << HR_SHIFT)
+#define HR_HMAC_SESSION (TPM_HC)((TPM_HC)TPM_HT_HMAC_SESSION << HR_SHIFT)
+#define HR_POLICY_SESSION (TPM_HC)((TPM_HC)TPM_HT_POLICY_SESSION << HR_SHIFT)
+#define HR_TRANSIENT (TPM_HC)((TPM_HC)TPM_HT_TRANSIENT << HR_SHIFT)
+#define HR_PERSISTENT (TPM_HC)((TPM_HC)TPM_HT_PERSISTENT << HR_SHIFT)
+#define HR_NV_INDEX (TPM_HC)((TPM_HC)TPM_HT_NV_INDEX << HR_SHIFT)
+#define HR_PERMANENT (TPM_HC)((TPM_HC)TPM_HT_PERMANENT << HR_SHIFT)
+#define PCR_FIRST (TPM_HC)(HR_PCR + 0)
+#define PCR_LAST (TPM_HC)(PCR_FIRST + IMPLEMENTATION_PCR - 1)
+#define HMAC_SESSION_FIRST (TPM_HC)(HR_HMAC_SESSION + 0)
+#define HMAC_SESSION_LAST (TPM_HC)(HMAC_SESSION_FIRST + MAX_ACTIVE_SESSIONS - 1)
+#define LOADED_SESSION_FIRST (TPM_HC)(HMAC_SESSION_FIRST)
+#define LOADED_SESSION_LAST (TPM_HC)(HMAC_SESSION_LAST)
+#define POLICY_SESSION_FIRST (TPM_HC)(HR_POLICY_SESSION + 0)
+#define POLICY_SESSION_LAST (TPM_HC)(POLICY_SESSION_FIRST + MAX_ACTIVE_SESSIONS - 1)
+#define TRANSIENT_FIRST (TPM_HC)(HR_TRANSIENT + 0)
+#define ACTIVE_SESSION_FIRST (TPM_HC)(POLICY_SESSION_FIRST)
+#define ACTIVE_SESSION_LAST (TPM_HC)(POLICY_SESSION_LAST)
+#define TRANSIENT_LAST (TPM_HC)(TRANSIENT_FIRST+MAX_LOADED_OBJECTS - 1)
+#define PERSISTENT_FIRST (TPM_HC)(HR_PERSISTENT + 0)
+#define PERSISTENT_LAST (TPM_HC)(PERSISTENT_FIRST + 0x00FFFFFF)
+#define PLATFORM_PERSISTENT (TPM_HC)(PERSISTENT_FIRST + 0x00800000)
+#define NV_INDEX_FIRST (TPM_HC)(HR_NV_INDEX + 0)
+#define NV_INDEX_LAST (TPM_HC)(NV_INDEX_FIRST + 0x00FFFFFF)
+#define PERMANENT_FIRST (TPM_HC)(TPM_RH_FIRST)
+#define PERMANENT_LAST (TPM_HC)(TPM_RH_LAST)
// 8 Attribute Structures
// Table 29 - TPMA_ALGORITHM Bits
typedef struct {
- UINT32 asymmetric : 1;
- UINT32 symmetric : 1;
- UINT32 hash : 1;
- UINT32 object : 1;
- UINT32 reserved4_7 : 4;
- UINT32 signing : 1;
- UINT32 encrypting : 1;
- UINT32 method : 1;
- UINT32 reserved11_31 : 21;
+ UINT32 asymmetric : 1;
+ UINT32 symmetric : 1;
+ UINT32 hash : 1;
+ UINT32 object : 1;
+ UINT32 reserved4_7 : 4;
+ UINT32 signing : 1;
+ UINT32 encrypting : 1;
+ UINT32 method : 1;
+ UINT32 reserved11_31 : 21;
} TPMA_ALGORITHM;
// Table 30 - TPMA_OBJECT Bits
typedef struct {
- UINT32 reserved1 : 1;
- UINT32 fixedTPM : 1;
- UINT32 stClear : 1;
- UINT32 reserved4 : 1;
- UINT32 fixedParent : 1;
- UINT32 sensitiveDataOrigin : 1;
- UINT32 userWithAuth : 1;
- UINT32 adminWithPolicy : 1;
- UINT32 reserved8_9 : 2;
- UINT32 noDA : 1;
- UINT32 encryptedDuplication : 1;
- UINT32 reserved12_15 : 4;
- UINT32 restricted : 1;
- UINT32 decrypt : 1;
- UINT32 sign : 1;
- UINT32 reserved19_31 : 13;
+ UINT32 reserved1 : 1;
+ UINT32 fixedTPM : 1;
+ UINT32 stClear : 1;
+ UINT32 reserved4 : 1;
+ UINT32 fixedParent : 1;
+ UINT32 sensitiveDataOrigin : 1;
+ UINT32 userWithAuth : 1;
+ UINT32 adminWithPolicy : 1;
+ UINT32 reserved8_9 : 2;
+ UINT32 noDA : 1;
+ UINT32 encryptedDuplication : 1;
+ UINT32 reserved12_15 : 4;
+ UINT32 restricted : 1;
+ UINT32 decrypt : 1;
+ UINT32 sign : 1;
+ UINT32 reserved19_31 : 13;
} TPMA_OBJECT;
// Table 31 - TPMA_SESSION Bits
typedef struct {
- UINT8 continueSession : 1;
- UINT8 auditExclusive : 1;
- UINT8 auditReset : 1;
- UINT8 reserved3_4 : 2;
- UINT8 decrypt : 1;
- UINT8 encrypt : 1;
- UINT8 audit : 1;
+ UINT8 continueSession : 1;
+ UINT8 auditExclusive : 1;
+ UINT8 auditReset : 1;
+ UINT8 reserved3_4 : 2;
+ UINT8 decrypt : 1;
+ UINT8 encrypt : 1;
+ UINT8 audit : 1;
} TPMA_SESSION;
// Table 32 - TPMA_LOCALITY Bits
@@ -757,54 +756,54 @@ typedef struct {
// NOTE: Use low case here to resolve conflict
//
typedef struct {
- UINT8 locZero : 1;
- UINT8 locOne : 1;
- UINT8 locTwo : 1;
- UINT8 locThree : 1;
- UINT8 locFour : 1;
- UINT8 Extended : 3;
+ UINT8 locZero : 1;
+ UINT8 locOne : 1;
+ UINT8 locTwo : 1;
+ UINT8 locThree : 1;
+ UINT8 locFour : 1;
+ UINT8 Extended : 3;
} TPMA_LOCALITY;
// Table 33 - TPMA_PERMANENT Bits
typedef struct {
- UINT32 ownerAuthSet : 1;
- UINT32 endorsementAuthSet : 1;
- UINT32 lockoutAuthSet : 1;
- UINT32 reserved3_7 : 5;
- UINT32 disableClear : 1;
- UINT32 inLockout : 1;
- UINT32 tpmGeneratedEPS : 1;
- UINT32 reserved11_31 : 21;
+ UINT32 ownerAuthSet : 1;
+ UINT32 endorsementAuthSet : 1;
+ UINT32 lockoutAuthSet : 1;
+ UINT32 reserved3_7 : 5;
+ UINT32 disableClear : 1;
+ UINT32 inLockout : 1;
+ UINT32 tpmGeneratedEPS : 1;
+ UINT32 reserved11_31 : 21;
} TPMA_PERMANENT;
// Table 34 - TPMA_STARTUP_CLEAR Bits
typedef struct {
- UINT32 phEnable : 1;
- UINT32 shEnable : 1;
- UINT32 ehEnable : 1;
- UINT32 reserved3_30 : 28;
- UINT32 orderly : 1;
+ UINT32 phEnable : 1;
+ UINT32 shEnable : 1;
+ UINT32 ehEnable : 1;
+ UINT32 reserved3_30 : 28;
+ UINT32 orderly : 1;
} TPMA_STARTUP_CLEAR;
// Table 35 - TPMA_MEMORY Bits
typedef struct {
- UINT32 sharedRAM : 1;
- UINT32 sharedNV : 1;
- UINT32 objectCopiedToRam : 1;
- UINT32 reserved3_31 : 29;
+ UINT32 sharedRAM : 1;
+ UINT32 sharedNV : 1;
+ UINT32 objectCopiedToRam : 1;
+ UINT32 reserved3_31 : 29;
} TPMA_MEMORY;
// Table 36 - TPMA_CC Bits
typedef struct {
- UINT32 commandIndex : 16;
- UINT32 reserved16_21 : 6;
- UINT32 nv : 1;
- UINT32 extensive : 1;
- UINT32 flushed : 1;
- UINT32 cHandles : 3;
- UINT32 rHandle : 1;
- UINT32 V : 1;
- UINT32 Res : 2;
+ UINT32 commandIndex : 16;
+ UINT32 reserved16_21 : 6;
+ UINT32 nv : 1;
+ UINT32 extensive : 1;
+ UINT32 flushed : 1;
+ UINT32 cHandles : 3;
+ UINT32 rHandle : 1;
+ UINT32 V : 1;
+ UINT32 Res : 2;
} TPMA_CC;
// 9 Interface Types
@@ -897,35 +896,35 @@ typedef TPM_ST TPMI_ST_COMMAND_TAG;
// Table 65 - TPMS_ALGORITHM_DESCRIPTION Structure
typedef struct {
- TPM_ALG_ID alg;
- TPMA_ALGORITHM attributes;
+ TPM_ALG_ID alg;
+ TPMA_ALGORITHM attributes;
} TPMS_ALGORITHM_DESCRIPTION;
// Table 66 - TPMU_HA Union
typedef union {
- BYTE sha1[SHA1_DIGEST_SIZE];
- BYTE sha256[SHA256_DIGEST_SIZE];
- BYTE sm3_256[SM3_256_DIGEST_SIZE];
- BYTE sha384[SHA384_DIGEST_SIZE];
- BYTE sha512[SHA512_DIGEST_SIZE];
+ BYTE sha1[SHA1_DIGEST_SIZE];
+ BYTE sha256[SHA256_DIGEST_SIZE];
+ BYTE sm3_256[SM3_256_DIGEST_SIZE];
+ BYTE sha384[SHA384_DIGEST_SIZE];
+ BYTE sha512[SHA512_DIGEST_SIZE];
} TPMU_HA;
// Table 67 - TPMT_HA Structure
typedef struct {
- TPMI_ALG_HASH hashAlg;
- TPMU_HA digest;
+ TPMI_ALG_HASH hashAlg;
+ TPMU_HA digest;
} TPMT_HA;
// Table 68 - TPM2B_DIGEST Structure
typedef struct {
- UINT16 size;
- BYTE buffer[sizeof(TPMU_HA)];
+ UINT16 size;
+ BYTE buffer[sizeof (TPMU_HA)];
} TPM2B_DIGEST;
// Table 69 - TPM2B_DATA Structure
typedef struct {
- UINT16 size;
- BYTE buffer[sizeof(TPMT_HA)];
+ UINT16 size;
+ BYTE buffer[sizeof (TPMT_HA)];
} TPM2B_DATA;
// Table 70 - TPM2B_NONCE Types
@@ -939,254 +938,254 @@ typedef TPM2B_DIGEST TPM2B_OPERAND;
// Table 73 - TPM2B_EVENT Structure
typedef struct {
- UINT16 size;
- BYTE buffer[1024];
+ UINT16 size;
+ BYTE buffer[1024];
} TPM2B_EVENT;
// Table 74 - TPM2B_MAX_BUFFER Structure
typedef struct {
- UINT16 size;
- BYTE buffer[MAX_DIGEST_BUFFER];
+ UINT16 size;
+ BYTE buffer[MAX_DIGEST_BUFFER];
} TPM2B_MAX_BUFFER;
// Table 75 - TPM2B_MAX_NV_BUFFER Structure
typedef struct {
- UINT16 size;
- BYTE buffer[MAX_NV_INDEX_SIZE];
+ UINT16 size;
+ BYTE buffer[MAX_NV_INDEX_SIZE];
} TPM2B_MAX_NV_BUFFER;
// Table 76 - TPM2B_TIMEOUT Structure
typedef struct {
- UINT16 size;
- BYTE buffer[sizeof(UINT64)];
+ UINT16 size;
+ BYTE buffer[sizeof (UINT64)];
} TPM2B_TIMEOUT;
// Table 77 -- TPM2B_IV Structure
typedef struct {
- UINT16 size;
- BYTE buffer[MAX_SYM_BLOCK_SIZE];
+ UINT16 size;
+ BYTE buffer[MAX_SYM_BLOCK_SIZE];
} TPM2B_IV;
// Table 78 - TPMU_NAME Union
typedef union {
- TPMT_HA digest;
- TPM_HANDLE handle;
+ TPMT_HA digest;
+ TPM_HANDLE handle;
} TPMU_NAME;
// Table 79 - TPM2B_NAME Structure
typedef struct {
- UINT16 size;
- BYTE name[sizeof(TPMU_NAME)];
+ UINT16 size;
+ BYTE name[sizeof (TPMU_NAME)];
} TPM2B_NAME;
// Table 80 - TPMS_PCR_SELECT Structure
typedef struct {
- UINT8 sizeofSelect;
- BYTE pcrSelect[PCR_SELECT_MAX];
+ UINT8 sizeofSelect;
+ BYTE pcrSelect[PCR_SELECT_MAX];
} TPMS_PCR_SELECT;
// Table 81 - TPMS_PCR_SELECTION Structure
typedef struct {
- TPMI_ALG_HASH hash;
- UINT8 sizeofSelect;
- BYTE pcrSelect[PCR_SELECT_MAX];
+ TPMI_ALG_HASH hash;
+ UINT8 sizeofSelect;
+ BYTE pcrSelect[PCR_SELECT_MAX];
} TPMS_PCR_SELECTION;
// Table 84 - TPMT_TK_CREATION Structure
typedef struct {
- TPM_ST tag;
- TPMI_RH_HIERARCHY hierarchy;
- TPM2B_DIGEST digest;
+ TPM_ST tag;
+ TPMI_RH_HIERARCHY hierarchy;
+ TPM2B_DIGEST digest;
} TPMT_TK_CREATION;
// Table 85 - TPMT_TK_VERIFIED Structure
typedef struct {
- TPM_ST tag;
- TPMI_RH_HIERARCHY hierarchy;
- TPM2B_DIGEST digest;
+ TPM_ST tag;
+ TPMI_RH_HIERARCHY hierarchy;
+ TPM2B_DIGEST digest;
} TPMT_TK_VERIFIED;
// Table 86 - TPMT_TK_AUTH Structure
typedef struct {
- TPM_ST tag;
- TPMI_RH_HIERARCHY hierarchy;
- TPM2B_DIGEST digest;
+ TPM_ST tag;
+ TPMI_RH_HIERARCHY hierarchy;
+ TPM2B_DIGEST digest;
} TPMT_TK_AUTH;
// Table 87 - TPMT_TK_HASHCHECK Structure
typedef struct {
- TPM_ST tag;
- TPMI_RH_HIERARCHY hierarchy;
- TPM2B_DIGEST digest;
+ TPM_ST tag;
+ TPMI_RH_HIERARCHY hierarchy;
+ TPM2B_DIGEST digest;
} TPMT_TK_HASHCHECK;
// Table 88 - TPMS_ALG_PROPERTY Structure
typedef struct {
- TPM_ALG_ID alg;
- TPMA_ALGORITHM algProperties;
+ TPM_ALG_ID alg;
+ TPMA_ALGORITHM algProperties;
} TPMS_ALG_PROPERTY;
// Table 89 - TPMS_TAGGED_PROPERTY Structure
typedef struct {
- TPM_PT property;
- UINT32 value;
+ TPM_PT property;
+ UINT32 value;
} TPMS_TAGGED_PROPERTY;
// Table 90 - TPMS_TAGGED_PCR_SELECT Structure
typedef struct {
- TPM_PT tag;
- UINT8 sizeofSelect;
- BYTE pcrSelect[PCR_SELECT_MAX];
+ TPM_PT tag;
+ UINT8 sizeofSelect;
+ BYTE pcrSelect[PCR_SELECT_MAX];
} TPMS_TAGGED_PCR_SELECT;
// Table 91 - TPML_CC Structure
typedef struct {
- UINT32 count;
- TPM_CC commandCodes[MAX_CAP_CC];
+ UINT32 count;
+ TPM_CC commandCodes[MAX_CAP_CC];
} TPML_CC;
// Table 92 - TPML_CCA Structure
typedef struct {
- UINT32 count;
- TPMA_CC commandAttributes[MAX_CAP_CC];
+ UINT32 count;
+ TPMA_CC commandAttributes[MAX_CAP_CC];
} TPML_CCA;
// Table 93 - TPML_ALG Structure
typedef struct {
- UINT32 count;
- TPM_ALG_ID algorithms[MAX_ALG_LIST_SIZE];
+ UINT32 count;
+ TPM_ALG_ID algorithms[MAX_ALG_LIST_SIZE];
} TPML_ALG;
// Table 94 - TPML_HANDLE Structure
typedef struct {
- UINT32 count;
- TPM_HANDLE handle[MAX_CAP_HANDLES];
+ UINT32 count;
+ TPM_HANDLE handle[MAX_CAP_HANDLES];
} TPML_HANDLE;
// Table 95 - TPML_DIGEST Structure
typedef struct {
- UINT32 count;
- TPM2B_DIGEST digests[8];
+ UINT32 count;
+ TPM2B_DIGEST digests[8];
} TPML_DIGEST;
// Table 96 -- TPML_DIGEST_VALUES Structure
typedef struct {
- UINT32 count;
- TPMT_HA digests[HASH_COUNT];
+ UINT32 count;
+ TPMT_HA digests[HASH_COUNT];
} TPML_DIGEST_VALUES;
// Table 97 - TPM2B_DIGEST_VALUES Structure
typedef struct {
- UINT16 size;
- BYTE buffer[sizeof(TPML_DIGEST_VALUES)];
+ UINT16 size;
+ BYTE buffer[sizeof (TPML_DIGEST_VALUES)];
} TPM2B_DIGEST_VALUES;
// Table 98 - TPML_PCR_SELECTION Structure
typedef struct {
- UINT32 count;
- TPMS_PCR_SELECTION pcrSelections[HASH_COUNT];
+ UINT32 count;
+ TPMS_PCR_SELECTION pcrSelections[HASH_COUNT];
} TPML_PCR_SELECTION;
// Table 99 - TPML_ALG_PROPERTY Structure
typedef struct {
- UINT32 count;
- TPMS_ALG_PROPERTY algProperties[MAX_CAP_ALGS];
+ UINT32 count;
+ TPMS_ALG_PROPERTY algProperties[MAX_CAP_ALGS];
} TPML_ALG_PROPERTY;
// Table 100 - TPML_TAGGED_TPM_PROPERTY Structure
typedef struct {
- UINT32 count;
- TPMS_TAGGED_PROPERTY tpmProperty[MAX_TPM_PROPERTIES];
+ UINT32 count;
+ TPMS_TAGGED_PROPERTY tpmProperty[MAX_TPM_PROPERTIES];
} TPML_TAGGED_TPM_PROPERTY;
// Table 101 - TPML_TAGGED_PCR_PROPERTY Structure
typedef struct {
- UINT32 count;
- TPMS_TAGGED_PCR_SELECT pcrProperty[MAX_PCR_PROPERTIES];
+ UINT32 count;
+ TPMS_TAGGED_PCR_SELECT pcrProperty[MAX_PCR_PROPERTIES];
} TPML_TAGGED_PCR_PROPERTY;
// Table 102 - TPML_ECC_CURVE Structure
typedef struct {
- UINT32 count;
- TPM_ECC_CURVE eccCurves[MAX_ECC_CURVES];
+ UINT32 count;
+ TPM_ECC_CURVE eccCurves[MAX_ECC_CURVES];
} TPML_ECC_CURVE;
// Table 103 - TPMU_CAPABILITIES Union
typedef union {
- TPML_ALG_PROPERTY algorithms;
- TPML_HANDLE handles;
- TPML_CCA command;
- TPML_CC ppCommands;
- TPML_CC auditCommands;
- TPML_PCR_SELECTION assignedPCR;
- TPML_TAGGED_TPM_PROPERTY tpmProperties;
- TPML_TAGGED_PCR_PROPERTY pcrProperties;
- TPML_ECC_CURVE eccCurves;
+ TPML_ALG_PROPERTY algorithms;
+ TPML_HANDLE handles;
+ TPML_CCA command;
+ TPML_CC ppCommands;
+ TPML_CC auditCommands;
+ TPML_PCR_SELECTION assignedPCR;
+ TPML_TAGGED_TPM_PROPERTY tpmProperties;
+ TPML_TAGGED_PCR_PROPERTY pcrProperties;
+ TPML_ECC_CURVE eccCurves;
} TPMU_CAPABILITIES;
// Table 104 - TPMS_CAPABILITY_DATA Structure
typedef struct {
- TPM_CAP capability;
- TPMU_CAPABILITIES data;
+ TPM_CAP capability;
+ TPMU_CAPABILITIES data;
} TPMS_CAPABILITY_DATA;
// Table 105 - TPMS_CLOCK_INFO Structure
typedef struct {
- UINT64 clock;
- UINT32 resetCount;
- UINT32 restartCount;
- TPMI_YES_NO safe;
+ UINT64 clock;
+ UINT32 resetCount;
+ UINT32 restartCount;
+ TPMI_YES_NO safe;
} TPMS_CLOCK_INFO;
// Table 106 - TPMS_TIME_INFO Structure
typedef struct {
- UINT64 time;
- TPMS_CLOCK_INFO clockInfo;
+ UINT64 time;
+ TPMS_CLOCK_INFO clockInfo;
} TPMS_TIME_INFO;
// Table 107 - TPMS_TIME_ATTEST_INFO Structure
typedef struct {
- TPMS_TIME_INFO time;
- UINT64 firmwareVersion;
+ TPMS_TIME_INFO time;
+ UINT64 firmwareVersion;
} TPMS_TIME_ATTEST_INFO;
// Table 108 - TPMS_CERTIFY_INFO Structure
typedef struct {
- TPM2B_NAME name;
- TPM2B_NAME qualifiedName;
+ TPM2B_NAME name;
+ TPM2B_NAME qualifiedName;
} TPMS_CERTIFY_INFO;
// Table 109 - TPMS_QUOTE_INFO Structure
typedef struct {
- TPML_PCR_SELECTION pcrSelect;
- TPM2B_DIGEST pcrDigest;
+ TPML_PCR_SELECTION pcrSelect;
+ TPM2B_DIGEST pcrDigest;
} TPMS_QUOTE_INFO;
// Table 110 - TPMS_COMMAND_AUDIT_INFO Structure
typedef struct {
- UINT64 auditCounter;
- TPM_ALG_ID digestAlg;
- TPM2B_DIGEST auditDigest;
- TPM2B_DIGEST commandDigest;
+ UINT64 auditCounter;
+ TPM_ALG_ID digestAlg;
+ TPM2B_DIGEST auditDigest;
+ TPM2B_DIGEST commandDigest;
} TPMS_COMMAND_AUDIT_INFO;
// Table 111 - TPMS_SESSION_AUDIT_INFO Structure
typedef struct {
- TPMI_YES_NO exclusiveSession;
- TPM2B_DIGEST sessionDigest;
+ TPMI_YES_NO exclusiveSession;
+ TPM2B_DIGEST sessionDigest;
} TPMS_SESSION_AUDIT_INFO;
// Table 112 - TPMS_CREATION_INFO Structure
typedef struct {
- TPM2B_NAME objectName;
- TPM2B_DIGEST creationHash;
+ TPM2B_NAME objectName;
+ TPM2B_DIGEST creationHash;
} TPMS_CREATION_INFO;
// Table 113 - TPMS_NV_CERTIFY_INFO Structure
typedef struct {
- TPM2B_NAME indexName;
- UINT16 offset;
- TPM2B_MAX_NV_BUFFER nvContents;
+ TPM2B_NAME indexName;
+ UINT16 offset;
+ TPM2B_MAX_NV_BUFFER nvContents;
} TPMS_NV_CERTIFY_INFO;
// Table 114 - TPMI_ST_ATTEST Type
@@ -1194,45 +1193,45 @@ typedef TPM_ST TPMI_ST_ATTEST;
// Table 115 - TPMU_ATTEST Union
typedef union {
- TPMS_CERTIFY_INFO certify;
- TPMS_CREATION_INFO creation;
- TPMS_QUOTE_INFO quote;
- TPMS_COMMAND_AUDIT_INFO commandAudit;
- TPMS_SESSION_AUDIT_INFO sessionAudit;
- TPMS_TIME_ATTEST_INFO time;
- TPMS_NV_CERTIFY_INFO nv;
+ TPMS_CERTIFY_INFO certify;
+ TPMS_CREATION_INFO creation;
+ TPMS_QUOTE_INFO quote;
+ TPMS_COMMAND_AUDIT_INFO commandAudit;
+ TPMS_SESSION_AUDIT_INFO sessionAudit;
+ TPMS_TIME_ATTEST_INFO time;
+ TPMS_NV_CERTIFY_INFO nv;
} TPMU_ATTEST;
// Table 116 - TPMS_ATTEST Structure
typedef struct {
- TPM_GENERATED magic;
- TPMI_ST_ATTEST type;
- TPM2B_NAME qualifiedSigner;
- TPM2B_DATA extraData;
- TPMS_CLOCK_INFO clockInfo;
- UINT64 firmwareVersion;
- TPMU_ATTEST attested;
+ TPM_GENERATED magic;
+ TPMI_ST_ATTEST type;
+ TPM2B_NAME qualifiedSigner;
+ TPM2B_DATA extraData;
+ TPMS_CLOCK_INFO clockInfo;
+ UINT64 firmwareVersion;
+ TPMU_ATTEST attested;
} TPMS_ATTEST;
// Table 117 - TPM2B_ATTEST Structure
typedef struct {
- UINT16 size;
- BYTE attestationData[sizeof(TPMS_ATTEST)];
+ UINT16 size;
+ BYTE attestationData[sizeof (TPMS_ATTEST)];
} TPM2B_ATTEST;
// Table 118 - TPMS_AUTH_COMMAND Structure
typedef struct {
- TPMI_SH_AUTH_SESSION sessionHandle;
- TPM2B_NONCE nonce;
- TPMA_SESSION sessionAttributes;
- TPM2B_AUTH hmac;
+ TPMI_SH_AUTH_SESSION sessionHandle;
+ TPM2B_NONCE nonce;
+ TPMA_SESSION sessionAttributes;
+ TPM2B_AUTH hmac;
} TPMS_AUTH_COMMAND;
// Table 119 - TPMS_AUTH_RESPONSE Structure
typedef struct {
- TPM2B_NONCE nonce;
- TPMA_SESSION sessionAttributes;
- TPM2B_AUTH hmac;
+ TPM2B_NONCE nonce;
+ TPMA_SESSION sessionAttributes;
+ TPM2B_AUTH hmac;
} TPMS_AUTH_RESPONSE;
// 11 Algorithm Parameters and Structures
@@ -1245,65 +1244,65 @@ typedef TPM_KEY_BITS TPMI_SM4_KEY_BITS;
// Table 122 - TPMU_SYM_KEY_BITS Union
typedef union {
- TPMI_AES_KEY_BITS aes;
- TPMI_SM4_KEY_BITS SM4;
- TPM_KEY_BITS sym;
+ TPMI_AES_KEY_BITS aes;
+ TPMI_SM4_KEY_BITS SM4;
+ TPM_KEY_BITS sym;
TPMI_ALG_HASH xor;
} TPMU_SYM_KEY_BITS;
// Table 123 - TPMU_SYM_MODE Union
typedef union {
- TPMI_ALG_SYM_MODE aes;
- TPMI_ALG_SYM_MODE SM4;
- TPMI_ALG_SYM_MODE sym;
+ TPMI_ALG_SYM_MODE aes;
+ TPMI_ALG_SYM_MODE SM4;
+ TPMI_ALG_SYM_MODE sym;
} TPMU_SYM_MODE;
// Table 125 - TPMT_SYM_DEF Structure
typedef struct {
- TPMI_ALG_SYM algorithm;
- TPMU_SYM_KEY_BITS keyBits;
- TPMU_SYM_MODE mode;
+ TPMI_ALG_SYM algorithm;
+ TPMU_SYM_KEY_BITS keyBits;
+ TPMU_SYM_MODE mode;
} TPMT_SYM_DEF;
// Table 126 - TPMT_SYM_DEF_OBJECT Structure
typedef struct {
- TPMI_ALG_SYM_OBJECT algorithm;
- TPMU_SYM_KEY_BITS keyBits;
- TPMU_SYM_MODE mode;
+ TPMI_ALG_SYM_OBJECT algorithm;
+ TPMU_SYM_KEY_BITS keyBits;
+ TPMU_SYM_MODE mode;
} TPMT_SYM_DEF_OBJECT;
// Table 127 - TPM2B_SYM_KEY Structure
typedef struct {
- UINT16 size;
- BYTE buffer[MAX_SYM_KEY_BYTES];
+ UINT16 size;
+ BYTE buffer[MAX_SYM_KEY_BYTES];
} TPM2B_SYM_KEY;
// Table 128 - TPMS_SYMCIPHER_PARMS Structure
typedef struct {
- TPMT_SYM_DEF_OBJECT sym;
+ TPMT_SYM_DEF_OBJECT sym;
} TPMS_SYMCIPHER_PARMS;
// Table 129 - TPM2B_SENSITIVE_DATA Structure
typedef struct {
- UINT16 size;
- BYTE buffer[MAX_SYM_DATA];
+ UINT16 size;
+ BYTE buffer[MAX_SYM_DATA];
} TPM2B_SENSITIVE_DATA;
// Table 130 - TPMS_SENSITIVE_CREATE Structure
typedef struct {
- TPM2B_AUTH userAuth;
- TPM2B_SENSITIVE_DATA data;
+ TPM2B_AUTH userAuth;
+ TPM2B_SENSITIVE_DATA data;
} TPMS_SENSITIVE_CREATE;
// Table 131 - TPM2B_SENSITIVE_CREATE Structure
typedef struct {
- UINT16 size;
- TPMS_SENSITIVE_CREATE sensitive;
+ UINT16 size;
+ TPMS_SENSITIVE_CREATE sensitive;
} TPM2B_SENSITIVE_CREATE;
// Table 132 - TPMS_SCHEME_SIGHASH Structure
typedef struct {
- TPMI_ALG_HASH hashAlg;
+ TPMI_ALG_HASH hashAlg;
} TPMS_SCHEME_SIGHASH;
// Table 133 - TPMI_ALG_KEYEDHASH_SCHEME Type
@@ -1314,20 +1313,20 @@ typedef TPMS_SCHEME_SIGHASH TPMS_SCHEME_HMAC;
// Table 135 - TPMS_SCHEME_XOR Structure
typedef struct {
- TPMI_ALG_HASH hashAlg;
- TPMI_ALG_KDF kdf;
+ TPMI_ALG_HASH hashAlg;
+ TPMI_ALG_KDF kdf;
} TPMS_SCHEME_XOR;
// Table 136 - TPMU_SCHEME_KEYEDHASH Union
typedef union {
- TPMS_SCHEME_HMAC hmac;
+ TPMS_SCHEME_HMAC hmac;
TPMS_SCHEME_XOR xor;
} TPMU_SCHEME_KEYEDHASH;
// Table 137 - TPMT_KEYEDHASH_SCHEME Structure
typedef struct {
- TPMI_ALG_KEYEDHASH_SCHEME scheme;
- TPMU_SCHEME_KEYEDHASH details;
+ TPMI_ALG_KEYEDHASH_SCHEME scheme;
+ TPMU_SCHEME_KEYEDHASH details;
} TPMT_KEYEDHASH_SCHEME;
// Table 138 - RSA_SIG_SCHEMES Types
@@ -1341,69 +1340,69 @@ typedef TPMS_SCHEME_SIGHASH TPMS_SCHEME_ECSCHNORR;
// Table 140 - TPMS_SCHEME_ECDAA Structure
typedef struct {
- TPMI_ALG_HASH hashAlg;
- UINT16 count;
+ TPMI_ALG_HASH hashAlg;
+ UINT16 count;
} TPMS_SCHEME_ECDAA;
// Table 141 - TPMU_SIG_SCHEME Union
typedef union {
- TPMS_SCHEME_RSASSA rsassa;
- TPMS_SCHEME_RSAPSS rsapss;
- TPMS_SCHEME_ECDSA ecdsa;
- TPMS_SCHEME_ECDAA ecdaa;
- TPMS_SCHEME_ECSCHNORR ecSchnorr;
- TPMS_SCHEME_HMAC hmac;
- TPMS_SCHEME_SIGHASH any;
+ TPMS_SCHEME_RSASSA rsassa;
+ TPMS_SCHEME_RSAPSS rsapss;
+ TPMS_SCHEME_ECDSA ecdsa;
+ TPMS_SCHEME_ECDAA ecdaa;
+ TPMS_SCHEME_ECSCHNORR ecSchnorr;
+ TPMS_SCHEME_HMAC hmac;
+ TPMS_SCHEME_SIGHASH any;
} TPMU_SIG_SCHEME;
// Table 142 - TPMT_SIG_SCHEME Structure
typedef struct {
- TPMI_ALG_SIG_SCHEME scheme;
- TPMU_SIG_SCHEME details;
+ TPMI_ALG_SIG_SCHEME scheme;
+ TPMU_SIG_SCHEME details;
} TPMT_SIG_SCHEME;
// Table 143 - TPMS_SCHEME_OAEP Structure
typedef struct {
- TPMI_ALG_HASH hashAlg;
+ TPMI_ALG_HASH hashAlg;
} TPMS_SCHEME_OAEP;
// Table 144 - TPMS_SCHEME_ECDH Structure
typedef struct {
- TPMI_ALG_HASH hashAlg;
+ TPMI_ALG_HASH hashAlg;
} TPMS_SCHEME_ECDH;
// Table 145 - TPMS_SCHEME_MGF1 Structure
typedef struct {
- TPMI_ALG_HASH hashAlg;
+ TPMI_ALG_HASH hashAlg;
} TPMS_SCHEME_MGF1;
// Table 146 - TPMS_SCHEME_KDF1_SP800_56a Structure
typedef struct {
- TPMI_ALG_HASH hashAlg;
+ TPMI_ALG_HASH hashAlg;
} TPMS_SCHEME_KDF1_SP800_56a;
// Table 147 - TPMS_SCHEME_KDF2 Structure
typedef struct {
- TPMI_ALG_HASH hashAlg;
+ TPMI_ALG_HASH hashAlg;
} TPMS_SCHEME_KDF2;
// Table 148 - TPMS_SCHEME_KDF1_SP800_108 Structure
typedef struct {
- TPMI_ALG_HASH hashAlg;
+ TPMI_ALG_HASH hashAlg;
} TPMS_SCHEME_KDF1_SP800_108;
// Table 149 - TPMU_KDF_SCHEME Union
typedef union {
- TPMS_SCHEME_MGF1 mgf1;
- TPMS_SCHEME_KDF1_SP800_56a kdf1_SP800_56a;
- TPMS_SCHEME_KDF2 kdf2;
- TPMS_SCHEME_KDF1_SP800_108 kdf1_sp800_108;
+ TPMS_SCHEME_MGF1 mgf1;
+ TPMS_SCHEME_KDF1_SP800_56a kdf1_SP800_56a;
+ TPMS_SCHEME_KDF2 kdf2;
+ TPMS_SCHEME_KDF1_SP800_108 kdf1_sp800_108;
} TPMU_KDF_SCHEME;
// Table 150 - TPMT_KDF_SCHEME Structure
typedef struct {
- TPMI_ALG_KDF scheme;
- TPMU_KDF_SCHEME details;
+ TPMI_ALG_KDF scheme;
+ TPMU_KDF_SCHEME details;
} TPMT_KDF_SCHEME;
// Table 151 - TPMI_ALG_ASYM_SCHEME Type
@@ -1411,19 +1410,19 @@ typedef TPM_ALG_ID TPMI_ALG_ASYM_SCHEME;
// Table 152 - TPMU_ASYM_SCHEME Union
typedef union {
- TPMS_SCHEME_RSASSA rsassa;
- TPMS_SCHEME_RSAPSS rsapss;
- TPMS_SCHEME_OAEP oaep;
- TPMS_SCHEME_ECDSA ecdsa;
- TPMS_SCHEME_ECDAA ecdaa;
- TPMS_SCHEME_ECSCHNORR ecSchnorr;
- TPMS_SCHEME_SIGHASH anySig;
+ TPMS_SCHEME_RSASSA rsassa;
+ TPMS_SCHEME_RSAPSS rsapss;
+ TPMS_SCHEME_OAEP oaep;
+ TPMS_SCHEME_ECDSA ecdsa;
+ TPMS_SCHEME_ECDAA ecdaa;
+ TPMS_SCHEME_ECSCHNORR ecSchnorr;
+ TPMS_SCHEME_SIGHASH anySig;
} TPMU_ASYM_SCHEME;
// Table 153 - TPMT_ASYM_SCHEME Structure
typedef struct {
- TPMI_ALG_ASYM_SCHEME scheme;
- TPMU_ASYM_SCHEME details;
+ TPMI_ALG_ASYM_SCHEME scheme;
+ TPMU_ASYM_SCHEME details;
} TPMT_ASYM_SCHEME;
// Table 154 - TPMI_ALG_RSA_SCHEME Type
@@ -1431,8 +1430,8 @@ typedef TPM_ALG_ID TPMI_ALG_RSA_SCHEME;
// Table 155 - TPMT_RSA_SCHEME Structure
typedef struct {
- TPMI_ALG_RSA_SCHEME scheme;
- TPMU_ASYM_SCHEME details;
+ TPMI_ALG_RSA_SCHEME scheme;
+ TPMU_ASYM_SCHEME details;
} TPMT_RSA_SCHEME;
// Table 156 - TPMI_ALG_RSA_DECRYPT Type
@@ -1440,14 +1439,14 @@ typedef TPM_ALG_ID TPMI_ALG_RSA_DECRYPT;
// Table 157 - TPMT_RSA_DECRYPT Structure
typedef struct {
- TPMI_ALG_RSA_DECRYPT scheme;
- TPMU_ASYM_SCHEME details;
+ TPMI_ALG_RSA_DECRYPT scheme;
+ TPMU_ASYM_SCHEME details;
} TPMT_RSA_DECRYPT;
// Table 158 - TPM2B_PUBLIC_KEY_RSA Structure
typedef struct {
- UINT16 size;
- BYTE buffer[MAX_RSA_KEY_BYTES];
+ UINT16 size;
+ BYTE buffer[MAX_RSA_KEY_BYTES];
} TPM2B_PUBLIC_KEY_RSA;
// Table 159 - TPMI_RSA_KEY_BITS Type
@@ -1455,26 +1454,26 @@ typedef TPM_KEY_BITS TPMI_RSA_KEY_BITS;
// Table 160 - TPM2B_PRIVATE_KEY_RSA Structure
typedef struct {
- UINT16 size;
- BYTE buffer[MAX_RSA_KEY_BYTES/2];
+ UINT16 size;
+ BYTE buffer[MAX_RSA_KEY_BYTES/2];
} TPM2B_PRIVATE_KEY_RSA;
// Table 161 - TPM2B_ECC_PARAMETER Structure
typedef struct {
- UINT16 size;
- BYTE buffer[MAX_ECC_KEY_BYTES];
+ UINT16 size;
+ BYTE buffer[MAX_ECC_KEY_BYTES];
} TPM2B_ECC_PARAMETER;
// Table 162 - TPMS_ECC_POINT Structure
typedef struct {
- TPM2B_ECC_PARAMETER x;
- TPM2B_ECC_PARAMETER y;
+ TPM2B_ECC_PARAMETER x;
+ TPM2B_ECC_PARAMETER y;
} TPMS_ECC_POINT;
// Table 163 -- TPM2B_ECC_POINT Structure
typedef struct {
- UINT16 size;
- TPMS_ECC_POINT point;
+ UINT16 size;
+ TPMS_ECC_POINT point;
} TPM2B_ECC_POINT;
// Table 164 - TPMI_ALG_ECC_SCHEME Type
@@ -1485,74 +1484,74 @@ typedef TPM_ECC_CURVE TPMI_ECC_CURVE;
// Table 166 - TPMT_ECC_SCHEME Structure
typedef struct {
- TPMI_ALG_ECC_SCHEME scheme;
- TPMU_SIG_SCHEME details;
+ TPMI_ALG_ECC_SCHEME scheme;
+ TPMU_SIG_SCHEME details;
} TPMT_ECC_SCHEME;
// Table 167 - TPMS_ALGORITHM_DETAIL_ECC Structure
typedef struct {
- TPM_ECC_CURVE curveID;
- UINT16 keySize;
- TPMT_KDF_SCHEME kdf;
- TPMT_ECC_SCHEME sign;
- TPM2B_ECC_PARAMETER p;
- TPM2B_ECC_PARAMETER a;
- TPM2B_ECC_PARAMETER b;
- TPM2B_ECC_PARAMETER gX;
- TPM2B_ECC_PARAMETER gY;
- TPM2B_ECC_PARAMETER n;
- TPM2B_ECC_PARAMETER h;
+ TPM_ECC_CURVE curveID;
+ UINT16 keySize;
+ TPMT_KDF_SCHEME kdf;
+ TPMT_ECC_SCHEME sign;
+ TPM2B_ECC_PARAMETER p;
+ TPM2B_ECC_PARAMETER a;
+ TPM2B_ECC_PARAMETER b;
+ TPM2B_ECC_PARAMETER gX;
+ TPM2B_ECC_PARAMETER gY;
+ TPM2B_ECC_PARAMETER n;
+ TPM2B_ECC_PARAMETER h;
} TPMS_ALGORITHM_DETAIL_ECC;
// Table 168 - TPMS_SIGNATURE_RSASSA Structure
typedef struct {
- TPMI_ALG_HASH hash;
- TPM2B_PUBLIC_KEY_RSA sig;
+ TPMI_ALG_HASH hash;
+ TPM2B_PUBLIC_KEY_RSA sig;
} TPMS_SIGNATURE_RSASSA;
// Table 169 - TPMS_SIGNATURE_RSAPSS Structure
typedef struct {
- TPMI_ALG_HASH hash;
- TPM2B_PUBLIC_KEY_RSA sig;
+ TPMI_ALG_HASH hash;
+ TPM2B_PUBLIC_KEY_RSA sig;
} TPMS_SIGNATURE_RSAPSS;
// Table 170 - TPMS_SIGNATURE_ECDSA Structure
typedef struct {
- TPMI_ALG_HASH hash;
- TPM2B_ECC_PARAMETER signatureR;
- TPM2B_ECC_PARAMETER signatureS;
+ TPMI_ALG_HASH hash;
+ TPM2B_ECC_PARAMETER signatureR;
+ TPM2B_ECC_PARAMETER signatureS;
} TPMS_SIGNATURE_ECDSA;
// Table 171 - TPMU_SIGNATURE Union
typedef union {
- TPMS_SIGNATURE_RSASSA rsassa;
- TPMS_SIGNATURE_RSAPSS rsapss;
- TPMS_SIGNATURE_ECDSA ecdsa;
- TPMS_SIGNATURE_ECDSA sm2;
- TPMS_SIGNATURE_ECDSA ecdaa;
- TPMS_SIGNATURE_ECDSA ecschnorr;
- TPMT_HA hmac;
- TPMS_SCHEME_SIGHASH any;
+ TPMS_SIGNATURE_RSASSA rsassa;
+ TPMS_SIGNATURE_RSAPSS rsapss;
+ TPMS_SIGNATURE_ECDSA ecdsa;
+ TPMS_SIGNATURE_ECDSA sm2;
+ TPMS_SIGNATURE_ECDSA ecdaa;
+ TPMS_SIGNATURE_ECDSA ecschnorr;
+ TPMT_HA hmac;
+ TPMS_SCHEME_SIGHASH any;
} TPMU_SIGNATURE;
// Table 172 - TPMT_SIGNATURE Structure
typedef struct {
- TPMI_ALG_SIG_SCHEME sigAlg;
- TPMU_SIGNATURE signature;
+ TPMI_ALG_SIG_SCHEME sigAlg;
+ TPMU_SIGNATURE signature;
} TPMT_SIGNATURE;
// Table 173 - TPMU_ENCRYPTED_SECRET Union
typedef union {
- BYTE ecc[sizeof(TPMS_ECC_POINT)];
- BYTE rsa[MAX_RSA_KEY_BYTES];
- BYTE symmetric[sizeof(TPM2B_DIGEST)];
- BYTE keyedHash[sizeof(TPM2B_DIGEST)];
+ BYTE ecc[sizeof (TPMS_ECC_POINT)];
+ BYTE rsa[MAX_RSA_KEY_BYTES];
+ BYTE symmetric[sizeof (TPM2B_DIGEST)];
+ BYTE keyedHash[sizeof (TPM2B_DIGEST)];
} TPMU_ENCRYPTED_SECRET;
// Table 174 - TPM2B_ENCRYPTED_SECRET Structure
typedef struct {
- UINT16 size;
- BYTE secret[sizeof(TPMU_ENCRYPTED_SECRET)];
+ UINT16 size;
+ BYTE secret[sizeof (TPMU_ENCRYPTED_SECRET)];
} TPM2B_ENCRYPTED_SECRET;
// 12 Key/Object Complex
@@ -1562,122 +1561,122 @@ typedef TPM_ALG_ID TPMI_ALG_PUBLIC;
// Table 176 - TPMU_PUBLIC_ID Union
typedef union {
- TPM2B_DIGEST keyedHash;
- TPM2B_DIGEST sym;
- TPM2B_PUBLIC_KEY_RSA rsa;
- TPMS_ECC_POINT ecc;
+ TPM2B_DIGEST keyedHash;
+ TPM2B_DIGEST sym;
+ TPM2B_PUBLIC_KEY_RSA rsa;
+ TPMS_ECC_POINT ecc;
} TPMU_PUBLIC_ID;
// Table 177 - TPMS_KEYEDHASH_PARMS Structure
typedef struct {
- TPMT_KEYEDHASH_SCHEME scheme;
+ TPMT_KEYEDHASH_SCHEME scheme;
} TPMS_KEYEDHASH_PARMS;
// Table 178 - TPMS_ASYM_PARMS Structure
typedef struct {
- TPMT_SYM_DEF_OBJECT symmetric;
- TPMT_ASYM_SCHEME scheme;
+ TPMT_SYM_DEF_OBJECT symmetric;
+ TPMT_ASYM_SCHEME scheme;
} TPMS_ASYM_PARMS;
// Table 179 - TPMS_RSA_PARMS Structure
typedef struct {
- TPMT_SYM_DEF_OBJECT symmetric;
- TPMT_RSA_SCHEME scheme;
- TPMI_RSA_KEY_BITS keyBits;
- UINT32 exponent;
+ TPMT_SYM_DEF_OBJECT symmetric;
+ TPMT_RSA_SCHEME scheme;
+ TPMI_RSA_KEY_BITS keyBits;
+ UINT32 exponent;
} TPMS_RSA_PARMS;
// Table 180 - TPMS_ECC_PARMS Structure
typedef struct {
- TPMT_SYM_DEF_OBJECT symmetric;
- TPMT_ECC_SCHEME scheme;
- TPMI_ECC_CURVE curveID;
- TPMT_KDF_SCHEME kdf;
+ TPMT_SYM_DEF_OBJECT symmetric;
+ TPMT_ECC_SCHEME scheme;
+ TPMI_ECC_CURVE curveID;
+ TPMT_KDF_SCHEME kdf;
} TPMS_ECC_PARMS;
// Table 181 - TPMU_PUBLIC_PARMS Union
typedef union {
- TPMS_KEYEDHASH_PARMS keyedHashDetail;
- TPMT_SYM_DEF_OBJECT symDetail;
- TPMS_RSA_PARMS rsaDetail;
- TPMS_ECC_PARMS eccDetail;
- TPMS_ASYM_PARMS asymDetail;
+ TPMS_KEYEDHASH_PARMS keyedHashDetail;
+ TPMT_SYM_DEF_OBJECT symDetail;
+ TPMS_RSA_PARMS rsaDetail;
+ TPMS_ECC_PARMS eccDetail;
+ TPMS_ASYM_PARMS asymDetail;
} TPMU_PUBLIC_PARMS;
// Table 182 - TPMT_PUBLIC_PARMS Structure
typedef struct {
- TPMI_ALG_PUBLIC type;
- TPMU_PUBLIC_PARMS parameters;
+ TPMI_ALG_PUBLIC type;
+ TPMU_PUBLIC_PARMS parameters;
} TPMT_PUBLIC_PARMS;
// Table 183 - TPMT_PUBLIC Structure
typedef struct {
- TPMI_ALG_PUBLIC type;
- TPMI_ALG_HASH nameAlg;
- TPMA_OBJECT objectAttributes;
- TPM2B_DIGEST authPolicy;
- TPMU_PUBLIC_PARMS parameters;
- TPMU_PUBLIC_ID unique;
+ TPMI_ALG_PUBLIC type;
+ TPMI_ALG_HASH nameAlg;
+ TPMA_OBJECT objectAttributes;
+ TPM2B_DIGEST authPolicy;
+ TPMU_PUBLIC_PARMS parameters;
+ TPMU_PUBLIC_ID unique;
} TPMT_PUBLIC;
// Table 184 - TPM2B_PUBLIC Structure
typedef struct {
- UINT16 size;
- TPMT_PUBLIC publicArea;
+ UINT16 size;
+ TPMT_PUBLIC publicArea;
} TPM2B_PUBLIC;
// Table 185 - TPM2B_PRIVATE_VENDOR_SPECIFIC Structure
typedef struct {
- UINT16 size;
- BYTE buffer[PRIVATE_VENDOR_SPECIFIC_BYTES];
+ UINT16 size;
+ BYTE buffer[PRIVATE_VENDOR_SPECIFIC_BYTES];
} TPM2B_PRIVATE_VENDOR_SPECIFIC;
// Table 186 - TPMU_SENSITIVE_COMPOSITE Union
typedef union {
- TPM2B_PRIVATE_KEY_RSA rsa;
- TPM2B_ECC_PARAMETER ecc;
- TPM2B_SENSITIVE_DATA bits;
- TPM2B_SYM_KEY sym;
- TPM2B_PRIVATE_VENDOR_SPECIFIC any;
+ TPM2B_PRIVATE_KEY_RSA rsa;
+ TPM2B_ECC_PARAMETER ecc;
+ TPM2B_SENSITIVE_DATA bits;
+ TPM2B_SYM_KEY sym;
+ TPM2B_PRIVATE_VENDOR_SPECIFIC any;
} TPMU_SENSITIVE_COMPOSITE;
// Table 187 - TPMT_SENSITIVE Structure
typedef struct {
- TPMI_ALG_PUBLIC sensitiveType;
- TPM2B_AUTH authValue;
- TPM2B_DIGEST seedValue;
- TPMU_SENSITIVE_COMPOSITE sensitive;
+ TPMI_ALG_PUBLIC sensitiveType;
+ TPM2B_AUTH authValue;
+ TPM2B_DIGEST seedValue;
+ TPMU_SENSITIVE_COMPOSITE sensitive;
} TPMT_SENSITIVE;
// Table 188 - TPM2B_SENSITIVE Structure
typedef struct {
- UINT16 size;
- TPMT_SENSITIVE sensitiveArea;
+ UINT16 size;
+ TPMT_SENSITIVE sensitiveArea;
} TPM2B_SENSITIVE;
// Table 189 - _PRIVATE Structure
typedef struct {
- TPM2B_DIGEST integrityOuter;
- TPM2B_DIGEST integrityInner;
- TPMT_SENSITIVE sensitive;
+ TPM2B_DIGEST integrityOuter;
+ TPM2B_DIGEST integrityInner;
+ TPMT_SENSITIVE sensitive;
} _PRIVATE;
// Table 190 - TPM2B_PRIVATE Structure
typedef struct {
- UINT16 size;
- BYTE buffer[sizeof(_PRIVATE)];
+ UINT16 size;
+ BYTE buffer[sizeof (_PRIVATE)];
} TPM2B_PRIVATE;
// Table 191 - _ID_OBJECT Structure
typedef struct {
- TPM2B_DIGEST integrityHMAC;
- TPM2B_DIGEST encIdentity;
+ TPM2B_DIGEST integrityHMAC;
+ TPM2B_DIGEST encIdentity;
} _ID_OBJECT;
// Table 192 - TPM2B_ID_OBJECT Structure
typedef struct {
- UINT16 size;
- BYTE credential[sizeof(_ID_OBJECT)];
+ UINT16 size;
+ BYTE credential[sizeof (_ID_OBJECT)];
} TPM2B_ID_OBJECT;
// 13 NV Storage Structures
@@ -1686,118 +1685,117 @@ typedef struct {
//
// NOTE: Comment here to resolve conflict
//
-//typedef struct {
+// typedef struct {
// UINT32 index : 22;
// UINT32 space : 2;
// UINT32 RH_NV : 8;
-//} TPM_NV_INDEX;
+// } TPM_NV_INDEX;
// Table 195 - TPMA_NV Bits
typedef struct {
- UINT32 TPMA_NV_PPWRITE : 1;
- UINT32 TPMA_NV_OWNERWRITE : 1;
- UINT32 TPMA_NV_AUTHWRITE : 1;
- UINT32 TPMA_NV_POLICYWRITE : 1;
- UINT32 TPMA_NV_COUNTER : 1;
- UINT32 TPMA_NV_BITS : 1;
- UINT32 TPMA_NV_EXTEND : 1;
- UINT32 reserved7_9 : 3;
- UINT32 TPMA_NV_POLICY_DELETE : 1;
- UINT32 TPMA_NV_WRITELOCKED : 1;
- UINT32 TPMA_NV_WRITEALL : 1;
- UINT32 TPMA_NV_WRITEDEFINE : 1;
- UINT32 TPMA_NV_WRITE_STCLEAR : 1;
- UINT32 TPMA_NV_GLOBALLOCK : 1;
- UINT32 TPMA_NV_PPREAD : 1;
- UINT32 TPMA_NV_OWNERREAD : 1;
- UINT32 TPMA_NV_AUTHREAD : 1;
- UINT32 TPMA_NV_POLICYREAD : 1;
- UINT32 reserved20_24 : 5;
- UINT32 TPMA_NV_NO_DA : 1;
- UINT32 TPMA_NV_ORDERLY : 1;
- UINT32 TPMA_NV_CLEAR_STCLEAR : 1;
- UINT32 TPMA_NV_READLOCKED : 1;
- UINT32 TPMA_NV_WRITTEN : 1;
- UINT32 TPMA_NV_PLATFORMCREATE : 1;
- UINT32 TPMA_NV_READ_STCLEAR : 1;
+ UINT32 TPMA_NV_PPWRITE : 1;
+ UINT32 TPMA_NV_OWNERWRITE : 1;
+ UINT32 TPMA_NV_AUTHWRITE : 1;
+ UINT32 TPMA_NV_POLICYWRITE : 1;
+ UINT32 TPMA_NV_COUNTER : 1;
+ UINT32 TPMA_NV_BITS : 1;
+ UINT32 TPMA_NV_EXTEND : 1;
+ UINT32 reserved7_9 : 3;
+ UINT32 TPMA_NV_POLICY_DELETE : 1;
+ UINT32 TPMA_NV_WRITELOCKED : 1;
+ UINT32 TPMA_NV_WRITEALL : 1;
+ UINT32 TPMA_NV_WRITEDEFINE : 1;
+ UINT32 TPMA_NV_WRITE_STCLEAR : 1;
+ UINT32 TPMA_NV_GLOBALLOCK : 1;
+ UINT32 TPMA_NV_PPREAD : 1;
+ UINT32 TPMA_NV_OWNERREAD : 1;
+ UINT32 TPMA_NV_AUTHREAD : 1;
+ UINT32 TPMA_NV_POLICYREAD : 1;
+ UINT32 reserved20_24 : 5;
+ UINT32 TPMA_NV_NO_DA : 1;
+ UINT32 TPMA_NV_ORDERLY : 1;
+ UINT32 TPMA_NV_CLEAR_STCLEAR : 1;
+ UINT32 TPMA_NV_READLOCKED : 1;
+ UINT32 TPMA_NV_WRITTEN : 1;
+ UINT32 TPMA_NV_PLATFORMCREATE : 1;
+ UINT32 TPMA_NV_READ_STCLEAR : 1;
} TPMA_NV;
// Table 196 - TPMS_NV_PUBLIC Structure
typedef struct {
- TPMI_RH_NV_INDEX nvIndex;
- TPMI_ALG_HASH nameAlg;
- TPMA_NV attributes;
- TPM2B_DIGEST authPolicy;
- UINT16 dataSize;
+ TPMI_RH_NV_INDEX nvIndex;
+ TPMI_ALG_HASH nameAlg;
+ TPMA_NV attributes;
+ TPM2B_DIGEST authPolicy;
+ UINT16 dataSize;
} TPMS_NV_PUBLIC;
// Table 197 - TPM2B_NV_PUBLIC Structure
typedef struct {
- UINT16 size;
- TPMS_NV_PUBLIC nvPublic;
+ UINT16 size;
+ TPMS_NV_PUBLIC nvPublic;
} TPM2B_NV_PUBLIC;
// 14 Context Data
// Table 198 - TPM2B_CONTEXT_SENSITIVE Structure
typedef struct {
- UINT16 size;
- BYTE buffer[MAX_CONTEXT_SIZE];
+ UINT16 size;
+ BYTE buffer[MAX_CONTEXT_SIZE];
} TPM2B_CONTEXT_SENSITIVE;
// Table 199 - TPMS_CONTEXT_DATA Structure
typedef struct {
- TPM2B_DIGEST integrity;
- TPM2B_CONTEXT_SENSITIVE encrypted;
+ TPM2B_DIGEST integrity;
+ TPM2B_CONTEXT_SENSITIVE encrypted;
} TPMS_CONTEXT_DATA;
// Table 200 - TPM2B_CONTEXT_DATA Structure
typedef struct {
- UINT16 size;
- BYTE buffer[sizeof(TPMS_CONTEXT_DATA)];
+ UINT16 size;
+ BYTE buffer[sizeof (TPMS_CONTEXT_DATA)];
} TPM2B_CONTEXT_DATA;
// Table 201 - TPMS_CONTEXT Structure
typedef struct {
- UINT64 sequence;
- TPMI_DH_CONTEXT savedHandle;
- TPMI_RH_HIERARCHY hierarchy;
- TPM2B_CONTEXT_DATA contextBlob;
+ UINT64 sequence;
+ TPMI_DH_CONTEXT savedHandle;
+ TPMI_RH_HIERARCHY hierarchy;
+ TPM2B_CONTEXT_DATA contextBlob;
} TPMS_CONTEXT;
// 15 Creation Data
// Table 203 - TPMS_CREATION_DATA Structure
typedef struct {
- TPML_PCR_SELECTION pcrSelect;
- TPM2B_DIGEST pcrDigest;
- TPMA_LOCALITY locality;
- TPM_ALG_ID parentNameAlg;
- TPM2B_NAME parentName;
- TPM2B_NAME parentQualifiedName;
- TPM2B_DATA outsideInfo;
+ TPML_PCR_SELECTION pcrSelect;
+ TPM2B_DIGEST pcrDigest;
+ TPMA_LOCALITY locality;
+ TPM_ALG_ID parentNameAlg;
+ TPM2B_NAME parentName;
+ TPM2B_NAME parentQualifiedName;
+ TPM2B_DATA outsideInfo;
} TPMS_CREATION_DATA;
// Table 204 - TPM2B_CREATION_DATA Structure
typedef struct {
- UINT16 size;
- TPMS_CREATION_DATA creationData;
+ UINT16 size;
+ TPMS_CREATION_DATA creationData;
} TPM2B_CREATION_DATA;
-
//
// Command Header
//
typedef struct {
- TPM_ST tag;
- UINT32 paramSize;
- TPM_CC commandCode;
+ TPM_ST tag;
+ UINT32 paramSize;
+ TPM_CC commandCode;
} TPM2_COMMAND_HEADER;
typedef struct {
- TPM_ST tag;
- UINT32 paramSize;
- TPM_RC responseCode;
+ TPM_ST tag;
+ UINT32 paramSize;
+ TPM_RC responseCode;
} TPM2_RESPONSE_HEADER;
#pragma pack ()
@@ -1805,10 +1803,10 @@ typedef struct {
//
// TCG Algorithm Registry
//
-#define HASH_ALG_SHA1 0x00000001
-#define HASH_ALG_SHA256 0x00000002
-#define HASH_ALG_SHA384 0x00000004
-#define HASH_ALG_SHA512 0x00000008
-#define HASH_ALG_SM3_256 0x00000010
+#define HASH_ALG_SHA1 0x00000001
+#define HASH_ALG_SHA256 0x00000002
+#define HASH_ALG_SHA384 0x00000004
+#define HASH_ALG_SHA512 0x00000008
+#define HASH_ALG_SM3_256 0x00000010
#endif
diff --git a/MdePkg/Include/IndustryStandard/Tpm2Acpi.h b/MdePkg/Include/IndustryStandard/Tpm2Acpi.h
index 7bfde940..c469e1df 100755
--- a/MdePkg/Include/IndustryStandard/Tpm2Acpi.h
+++ b/MdePkg/Include/IndustryStandard/Tpm2Acpi.h
@@ -19,34 +19,34 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define EFI_TPM2_ACPI_TABLE_REVISION EFI_TPM2_ACPI_TABLE_REVISION_4
typedef struct {
- EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
// Flags field is replaced in version 4 and above
// BIT0~15: PlatformClass This field is only valid for version 4 and above
// BIT16~31: Reserved
- UINT32 Flags;
- UINT64 AddressOfControlArea;
- UINT32 StartMethod;
- UINT8 PlatformSpecificParameters[12];
- UINT32 LogAreaMinimumLen;
- UINT64 LogAreaStartAddress;
+ UINT32 Flags;
+ UINT64 AddressOfControlArea;
+ UINT32 StartMethod;
+ UINT8 PlatformSpecificParameters[12];
+ UINT32 LogAreaMinimumLen;
+ UINT64 LogAreaStartAddress;
} EFI_TPM2_ACPI_TABLE;
-#define EFI_TPM2_ACPI_TABLE_START_METHOD_ACPI 2
-#define EFI_TPM2_ACPI_TABLE_START_METHOD_TIS 6
-#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE 7
-#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE_WITH_ACPI 8
-#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE_WITH_SMC 11
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_ACPI 2
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_TIS 6
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE 7
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE_WITH_ACPI 8
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE_WITH_SMC 11
typedef struct {
- UINT32 Reserved;
- UINT32 Error;
- UINT32 Cancel;
- UINT32 Start;
- UINT64 InterruptControl;
- UINT32 CommandSize;
- UINT64 Command;
- UINT32 ResponseSize;
- UINT64 Response;
+ UINT32 Reserved;
+ UINT32 Error;
+ UINT32 Cancel;
+ UINT32 Start;
+ UINT64 InterruptControl;
+ UINT32 CommandSize;
+ UINT64 Command;
+ UINT32 ResponseSize;
+ UINT64 Response;
} EFI_TPM2_ACPI_CONTROL_AREA;
//
@@ -54,11 +54,11 @@ typedef struct {
// Refer to Table 9: Start Method Specific Parameters for ARM SMC
//
typedef struct {
- UINT32 Interrupt;
- UINT8 Flags;
- UINT8 OperationFlags;
- UINT8 Reserved[2];
- UINT32 SmcFunctionId;
+ UINT32 Interrupt;
+ UINT8 Flags;
+ UINT8 OperationFlags;
+ UINT8 Reserved[2];
+ UINT32 SmcFunctionId;
} EFI_TPM2_ACPI_START_METHOD_SPECIFIC_PARAMETERS_ARM_SMC;
#pragma pack ()
diff --git a/MdePkg/Include/IndustryStandard/TpmPtp.h b/MdePkg/Include/IndustryStandard/TpmPtp.h
index 4481a089..1846b8c5 100644
--- a/MdePkg/Include/IndustryStandard/TpmPtp.h
+++ b/MdePkg/Include/IndustryStandard/TpmPtp.h
@@ -26,66 +26,66 @@ typedef struct {
///
/// Used to gain ownership for this particular port.
///
- UINT8 Access; // 0
- UINT8 Reserved1[7]; // 1
+ UINT8 Access; // 0
+ UINT8 Reserved1[7]; // 1
///
/// Controls interrupts.
///
- UINT32 IntEnable; // 8
+ UINT32 IntEnable; // 8
///
/// SIRQ vector to be used by the TPM.
///
- UINT8 IntVector; // 0ch
- UINT8 Reserved2[3]; // 0dh
+ UINT8 IntVector; // 0ch
+ UINT8 Reserved2[3]; // 0dh
///
/// What caused interrupt.
///
- UINT32 IntSts; // 10h
+ UINT32 IntSts; // 10h
///
/// Shows which interrupts are supported by that particular TPM.
///
- UINT32 InterfaceCapability;// 14h
+ UINT32 InterfaceCapability; // 14h
///
/// Status Register. Provides status of the TPM.
///
- UINT8 Status; // 18h
+ UINT8 Status; // 18h
///
/// Number of consecutive writes that can be done to the TPM.
///
- UINT16 BurstCount; // 19h
+ UINT16 BurstCount; // 19h
///
/// Additional Status Register.
///
- UINT8 StatusEx; // 1Bh
- UINT8 Reserved3[8];
+ UINT8 StatusEx; // 1Bh
+ UINT8 Reserved3[8];
///
/// Read or write FIFO, depending on transaction.
///
- UINT32 DataFifo; // 24h
- UINT8 Reserved4[8]; // 28h
+ UINT32 DataFifo; // 24h
+ UINT8 Reserved4[8]; // 28h
///
/// Used to identify the Interface types supported by the TPM.
///
- UINT32 InterfaceId; // 30h
- UINT8 Reserved5[0x4c]; // 34h
+ UINT32 InterfaceId; // 30h
+ UINT8 Reserved5[0x4c]; // 34h
///
/// Extended ReadFIFO or WriteFIFO, depending on the current bus cycle (read or write)
///
- UINT32 XDataFifo; // 80h
- UINT8 Reserved6[0xe7c]; // 84h
+ UINT32 XDataFifo; // 80h
+ UINT8 Reserved6[0xe7c]; // 84h
///
/// Vendor ID
///
- UINT16 Vid; // 0f00h
+ UINT16 Vid; // 0f00h
///
/// Device ID
///
- UINT16 Did; // 0f02h
+ UINT16 Did; // 0f02h
///
/// Revision ID
///
- UINT8 Rid; // 0f04h
- UINT8 Reserved[0xfb]; // 0f05h
+ UINT8 Rid; // 0f04h
+ UINT8 Reserved[0xfb]; // 0f05h
} PTP_FIFO_REGISTERS;
//
@@ -96,27 +96,27 @@ typedef struct {
//
// Define pointer types used to access TIS registers on PC
//
-typedef PTP_FIFO_REGISTERS *PTP_FIFO_REGISTERS_PTR;
+typedef PTP_FIFO_REGISTERS *PTP_FIFO_REGISTERS_PTR;
//
// Define bits of FIFO Interface Identifier Register
//
typedef union {
struct {
- UINT32 InterfaceType:4;
- UINT32 InterfaceVersion:4;
- UINT32 CapLocality:1;
- UINT32 Reserved1:2;
- UINT32 CapDataXferSizeSupport:2;
- UINT32 CapFIFO:1;
- UINT32 CapCRB:1;
- UINT32 CapIFRes:2;
- UINT32 InterfaceSelector:2;
- UINT32 IntfSelLock:1;
- UINT32 Reserved2:4;
- UINT32 Reserved3:8;
+ UINT32 InterfaceType : 4;
+ UINT32 InterfaceVersion : 4;
+ UINT32 CapLocality : 1;
+ UINT32 Reserved1 : 2;
+ UINT32 CapDataXferSizeSupport : 2;
+ UINT32 CapFIFO : 1;
+ UINT32 CapCRB : 1;
+ UINT32 CapIFRes : 2;
+ UINT32 InterfaceSelector : 2;
+ UINT32 IntfSelLock : 1;
+ UINT32 Reserved2 : 4;
+ UINT32 Reserved3 : 8;
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PTP_FIFO_INTERFACE_IDENTIFIER;
//
@@ -124,21 +124,21 @@ typedef union {
//
typedef union {
struct {
- UINT32 DataAvailIntSupport:1;
- UINT32 StsValidIntSupport:1;
- UINT32 LocalityChangeIntSupport:1;
- UINT32 InterruptLevelHigh:1;
- UINT32 InterruptLevelLow:1;
- UINT32 InterruptEdgeRising:1;
- UINT32 InterruptEdgeFalling:1;
- UINT32 CommandReadyIntSupport:1;
- UINT32 BurstCountStatic:1;
- UINT32 DataTransferSizeSupport:2;
- UINT32 Reserved:17;
- UINT32 InterfaceVersion:3;
- UINT32 Reserved2:1;
+ UINT32 DataAvailIntSupport : 1;
+ UINT32 StsValidIntSupport : 1;
+ UINT32 LocalityChangeIntSupport : 1;
+ UINT32 InterruptLevelHigh : 1;
+ UINT32 InterruptLevelLow : 1;
+ UINT32 InterruptEdgeRising : 1;
+ UINT32 InterruptEdgeFalling : 1;
+ UINT32 CommandReadyIntSupport : 1;
+ UINT32 BurstCountStatic : 1;
+ UINT32 DataTransferSizeSupport : 2;
+ UINT32 Reserved : 17;
+ UINT32 InterfaceVersion : 3;
+ UINT32 Reserved2 : 1;
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PTP_FIFO_INTERFACE_CAPABILITY;
///
@@ -148,7 +148,6 @@ typedef union {
#define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_13 0x2
#define INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP 0x3
-
//
// Define bits of ACCESS and STATUS registers
//
@@ -156,80 +155,79 @@ typedef union {
///
/// This bit is a 1 to indicate that the other bits in this register are valid.
///
-#define PTP_FIFO_VALID BIT7
+#define PTP_FIFO_VALID BIT7
///
/// Indicate that this locality is active.
///
-#define PTP_FIFO_ACC_ACTIVE BIT5
+#define PTP_FIFO_ACC_ACTIVE BIT5
///
/// Set to 1 to indicate that this locality had the TPM taken away while
/// this locality had the TIS_PC_ACC_ACTIVE bit set.
///
-#define PTP_FIFO_ACC_SEIZED BIT4
+#define PTP_FIFO_ACC_SEIZED BIT4
///
/// Set to 1 to indicate that TPM MUST reset the
/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
/// locality that is writing this bit.
///
-#define PTP_FIFO_ACC_SEIZE BIT3
+#define PTP_FIFO_ACC_SEIZE BIT3
///
/// When this bit is 1, another locality is requesting usage of the TPM.
///
-#define PTP_FIFO_ACC_PENDIND BIT2
+#define PTP_FIFO_ACC_PENDIND BIT2
///
/// Set to 1 to indicate that this locality is requesting to use TPM.
///
-#define PTP_FIFO_ACC_RQUUSE BIT1
+#define PTP_FIFO_ACC_RQUUSE BIT1
///
/// A value of 1 indicates that a T/OS has not been established on the platform
///
-#define PTP_FIFO_ACC_ESTABLISH BIT0
+#define PTP_FIFO_ACC_ESTABLISH BIT0
///
/// This field indicates that STS_DATA and STS_EXPECT are valid
///
-#define PTP_FIFO_STS_VALID BIT7
+#define PTP_FIFO_STS_VALID BIT7
///
/// When this bit is 1, TPM is in the Ready state,
/// indicating it is ready to receive a new command.
///
-#define PTP_FIFO_STS_READY BIT6
+#define PTP_FIFO_STS_READY BIT6
///
/// Write a 1 to this bit to cause the TPM to execute that command.
///
-#define PTP_FIFO_STS_GO BIT5
+#define PTP_FIFO_STS_GO BIT5
///
/// This bit indicates that the TPM has data available as a response.
///
-#define PTP_FIFO_STS_DATA BIT4
+#define PTP_FIFO_STS_DATA BIT4
///
/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
///
-#define PTP_FIFO_STS_EXPECT BIT3
+#define PTP_FIFO_STS_EXPECT BIT3
///
/// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.
///
-#define PTP_FIFO_STS_SELFTEST_DONE BIT2
+#define PTP_FIFO_STS_SELFTEST_DONE BIT2
///
/// Writes a 1 to this bit to force the TPM to re-send the response.
///
-#define PTP_FIFO_STS_RETRY BIT1
+#define PTP_FIFO_STS_RETRY BIT1
///
/// TPM Family Identifier.
/// 00: TPM 1.2 Family
/// 01: TPM 2.0 Family
///
-#define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 | BIT3)
-#define PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET (2)
-#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM12 (0)
-#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20 (BIT2)
+#define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 | BIT3)
+#define PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET (2)
+#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM12 (0)
+#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20 (BIT2)
///
/// A write of 1 after tpmGo and before dataAvail aborts the currently executing command, resulting in a response of TPM_RC_CANCELLED.
/// A write of 1 after dataAvail and before tpmGo is ignored by the TPM.
///
-#define PTP_FIFO_STS_EX_CANCEL BIT0
-
+#define PTP_FIFO_STS_EX_CANCEL BIT0
//
// PTP CRB definition
@@ -247,103 +245,103 @@ typedef struct {
///
/// Used to determine current state of Locality of the TPM.
///
- UINT32 LocalityState; // 0
- UINT8 Reserved1[4]; // 4
+ UINT32 LocalityState; // 0
+ UINT8 Reserved1[4]; // 4
///
/// Used to gain control of the TPM by this Locality.
///
- UINT32 LocalityControl; // 8
+ UINT32 LocalityControl; // 8
///
/// Used to determine whether Locality has been granted or Seized.
///
- UINT32 LocalityStatus; // 0ch
- UINT8 Reserved2[0x20]; // 10h
+ UINT32 LocalityStatus; // 0ch
+ UINT8 Reserved2[0x20]; // 10h
///
/// Used to identify the Interface types supported by the TPM.
///
- UINT32 InterfaceId; // 30h
+ UINT32 InterfaceId; // 30h
///
/// Vendor ID
///
- UINT16 Vid; // 34h
+ UINT16 Vid; // 34h
///
/// Device ID
///
- UINT16 Did; // 36h
+ UINT16 Did; // 36h
///
/// Optional Register used in low memory environments prior to CRB_DATA_BUFFER availability.
///
- UINT64 CrbControlExtension; // 38h
+ UINT64 CrbControlExtension; // 38h
///
/// Register used to initiate transactions for the CRB interface.
///
- UINT32 CrbControlRequest; // 40h
+ UINT32 CrbControlRequest; // 40h
///
/// Register used by the TPM to provide status of the CRB interface.
///
- UINT32 CrbControlStatus; // 44h
+ UINT32 CrbControlStatus; // 44h
///
/// Register used by software to cancel command processing.
///
- UINT32 CrbControlCancel; // 48h
+ UINT32 CrbControlCancel; // 48h
///
/// Register used to indicate presence of command or response data in the CRB buffer.
///
- UINT32 CrbControlStart; // 4Ch
+ UINT32 CrbControlStart; // 4Ch
///
/// Register used to configure and respond to interrupts.
///
- UINT32 CrbInterruptEnable; // 50h
- UINT32 CrbInterruptStatus; // 54h
+ UINT32 CrbInterruptEnable; // 50h
+ UINT32 CrbInterruptStatus; // 54h
///
/// Size of the Command buffer.
///
- UINT32 CrbControlCommandSize; // 58h
+ UINT32 CrbControlCommandSize; // 58h
///
/// Command buffer start address
///
- UINT32 CrbControlCommandAddressLow; // 5Ch
- UINT32 CrbControlCommandAddressHigh; // 60h
+ UINT32 CrbControlCommandAddressLow; // 5Ch
+ UINT32 CrbControlCommandAddressHigh; // 60h
///
/// Size of the Response buffer
///
- UINT32 CrbControlResponseSize; // 64h
+ UINT32 CrbControlResponseSize; // 64h
///
/// Address of the start of the Response buffer
///
- UINT64 CrbControlResponseAddrss; // 68h
- UINT8 Reserved4[0x10]; // 70h
+ UINT64 CrbControlResponseAddrss; // 68h
+ UINT8 Reserved4[0x10]; // 70h
///
/// Command/Response Data may be defined as large as 3968 (0xF80).
///
- UINT8 CrbDataBuffer[0xF80]; // 80h
+ UINT8 CrbDataBuffer[0xF80]; // 80h
} PTP_CRB_REGISTERS;
//
// Define pointer types used to access CRB registers on PTP
//
-typedef PTP_CRB_REGISTERS *PTP_CRB_REGISTERS_PTR;
+typedef PTP_CRB_REGISTERS *PTP_CRB_REGISTERS_PTR;
//
// Define bits of CRB Interface Identifier Register
//
typedef union {
struct {
- UINT32 InterfaceType:4;
- UINT32 InterfaceVersion:4;
- UINT32 CapLocality:1;
- UINT32 CapCRBIdleBypass:1;
- UINT32 Reserved1:1;
- UINT32 CapDataXferSizeSupport:2;
- UINT32 CapFIFO:1;
- UINT32 CapCRB:1;
- UINT32 CapIFRes:2;
- UINT32 InterfaceSelector:2;
- UINT32 IntfSelLock:1;
- UINT32 Reserved2:4;
- UINT32 Rid:8;
+ UINT32 InterfaceType : 4;
+ UINT32 InterfaceVersion : 4;
+ UINT32 CapLocality : 1;
+ UINT32 CapCRBIdleBypass : 1;
+ UINT32 Reserved1 : 1;
+ UINT32 CapDataXferSizeSupport : 2;
+ UINT32 CapFIFO : 1;
+ UINT32 CapCRB : 1;
+ UINT32 CapIFRes : 2;
+ UINT32 InterfaceSelector : 2;
+ UINT32 IntfSelLock : 1;
+ UINT32 Reserved2 : 4;
+ UINT32 Rid : 8;
} Bits;
- UINT32 Uint32;
+ UINT32 Uint32;
} PTP_CRB_INTERFACE_IDENTIFIER;
///
@@ -372,7 +370,7 @@ typedef union {
///
/// This bit indicates whether all other bits of this register contain valid values, if it is a 1.
///
-#define PTP_CRB_LOCALITY_STATE_TPM_REG_VALID_STATUS BIT7
+#define PTP_CRB_LOCALITY_STATE_TPM_REG_VALID_STATUS BIT7
///
/// 000 - Locality 0
@@ -381,24 +379,24 @@ typedef union {
/// 011 - Locality 3
/// 100 - Locality 4
///
-#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 | BIT3 | BIT4)
-#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_0 (0)
-#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1 (BIT2)
-#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_2 (BIT3)
-#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 | BIT3)
-#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_4 (BIT4)
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 | BIT3 | BIT4)
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_0 (0)
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1 (BIT2)
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_2 (BIT3)
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 | BIT3)
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_4 (BIT4)
///
/// A 0 indicates to the host that no locality is assigned.
/// A 1 indicates a locality has been assigned.
///
-#define PTP_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED BIT1
+#define PTP_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED BIT1
///
/// The TPM clears this bit to 0 upon receipt of _TPM_Hash_End
/// The TPM sets this bit to a 1 when the TPM_LOC_CTRL_x.resetEstablishment field is set to 1.
///
-#define PTP_CRB_LOCALITY_STATE_TPM_ESTABLISHED BIT0
+#define PTP_CRB_LOCALITY_STATE_TPM_ESTABLISHED BIT0
//
// Define bits of Locality Control Register
@@ -412,17 +410,17 @@ typedef union {
///
/// Writes (1): The TPM gives control of the TPM to the locality setting this bit if it is the higher priority locality.
///
-#define PTP_CRB_LOCALITY_CONTROL_SEIZE BIT2
+#define PTP_CRB_LOCALITY_CONTROL_SEIZE BIT2
///
/// Writes (1): The active Locality is done with the TPM.
///
-#define PTP_CRB_LOCALITY_CONTROL_RELINQUISH BIT1
+#define PTP_CRB_LOCALITY_CONTROL_RELINQUISH BIT1
///
/// Writes (1): Interrupt the TPM and generate a locality arbitration algorithm.
///
-#define PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS BIT0
+#define PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS BIT0
//
// Define bits of Locality Status Register
@@ -432,13 +430,13 @@ typedef union {
/// 0: A higher locality has not initiated a Seize arbitration process.
/// 1: A higher locality has Seized the TPM from this locality.
///
-#define PTP_CRB_LOCALITY_STATUS_BEEN_SEIZED BIT1
+#define PTP_CRB_LOCALITY_STATUS_BEEN_SEIZED BIT1
///
/// 0: Locality has not been granted to the TPM.
/// 1: Locality has been granted access to the TPM
///
-#define PTP_CRB_LOCALITY_STATUS_GRANTED BIT0
+#define PTP_CRB_LOCALITY_STATUS_GRANTED BIT0
//
// Define bits of CRB Control Area Request Register
@@ -450,7 +448,7 @@ typedef union {
/// 0: Cleared to 0 by TPM to acknowledge the request when TPM enters Idle state.
/// TPM SHALL complete this transition within TIMEOUT_C.
///
-#define PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE BIT1
+#define PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE BIT1
///
/// Used by Software to request the TPM transition to the Ready State.
@@ -458,7 +456,7 @@ typedef union {
/// 0: Cleared to 0 by TPM to acknowledge the request.
/// TPM SHALL complete this transition within TIMEOUT_C.
///
-#define PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY BIT0
+#define PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY BIT0
//
// Define bits of CRB Control Area Status Register
@@ -470,14 +468,14 @@ typedef union {
/// 0: Cleared by TPM on receipt of TPM_CRB_CTRL_REQ_x.cmdReady when TPM transitions to the Ready State.
/// SHALL be cleared by TIMEOUT_C.
///
-#define PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE BIT1
+#define PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE BIT1
///
/// Used by the TPM to indicate current status.
/// 1: Set by TPM to indicate a FATAL Error
/// 0: Indicates TPM is operational
///
-#define PTP_CRB_CONTROL_AREA_STATUS_TPM_STATUS BIT0
+#define PTP_CRB_CONTROL_AREA_STATUS_TPM_STATUS BIT0
//
// Define bits of CRB Control Cancel Register
@@ -488,7 +486,7 @@ typedef union {
/// Writes (0000 0001h): Cancel a command
/// Writes (0000 0000h): Clears field when command has been cancelled
///
-#define PTP_CRB_CONTROL_CANCEL BIT0
+#define PTP_CRB_CONTROL_CANCEL BIT0
//
// Define bits of CRB Control Start Register
@@ -499,7 +497,7 @@ typedef union {
/// Writes (0000 0001h): TPM transitions to Command Execution
/// Writes (0000 0000h): TPM clears this field and transitions to Command Completion
///
-#define PTP_CRB_CONTROL_START BIT0
+#define PTP_CRB_CONTROL_START BIT0
//
// Restore original structure alignment
@@ -509,9 +507,9 @@ typedef union {
//
// Default TimeOut value
//
-#define PTP_TIMEOUT_A (750 * 1000) // 750ms
-#define PTP_TIMEOUT_B (2000 * 1000) // 2s
-#define PTP_TIMEOUT_C (200 * 1000) // 200ms
-#define PTP_TIMEOUT_D (30 * 1000) // 30ms
+#define PTP_TIMEOUT_A (750 * 1000) // 750ms
+#define PTP_TIMEOUT_B (2000 * 1000) // 2s
+#define PTP_TIMEOUT_C (200 * 1000) // 200ms
+#define PTP_TIMEOUT_D (30 * 1000) // 30ms
#endif
diff --git a/MdePkg/Include/IndustryStandard/TpmTis.h b/MdePkg/Include/IndustryStandard/TpmTis.h
index 85c2969c..cf98268f 100644
--- a/MdePkg/Include/IndustryStandard/TpmTis.h
+++ b/MdePkg/Include/IndustryStandard/TpmTis.h
@@ -22,72 +22,72 @@ typedef struct {
///
/// Used to gain ownership for this particular port.
///
- UINT8 Access; // 0
- UINT8 Reserved1[7]; // 1
+ UINT8 Access; // 0
+ UINT8 Reserved1[7]; // 1
///
/// Controls interrupts.
///
- UINT32 IntEnable; // 8
+ UINT32 IntEnable; // 8
///
/// SIRQ vector to be used by the TPM.
///
- UINT8 IntVector; // 0ch
- UINT8 Reserved2[3]; // 0dh
+ UINT8 IntVector; // 0ch
+ UINT8 Reserved2[3]; // 0dh
///
/// What caused interrupt.
///
- UINT32 IntSts; // 10h
+ UINT32 IntSts; // 10h
///
/// Shows which interrupts are supported by that particular TPM.
///
- UINT32 IntfCapability; // 14h
+ UINT32 IntfCapability; // 14h
///
/// Status Register. Provides status of the TPM.
///
- UINT8 Status; // 18h
+ UINT8 Status; // 18h
///
/// Number of consecutive writes that can be done to the TPM.
///
- UINT16 BurstCount; // 19h
- UINT8 Reserved3[9];
+ UINT16 BurstCount; // 19h
+ UINT8 Reserved3[9];
///
/// Read or write FIFO, depending on transaction.
///
- UINT32 DataFifo; // 24h
- UINT8 Reserved4[0xed8]; // 28h
+ UINT32 DataFifo; // 24h
+ UINT8 Reserved4[0xed8]; // 28h
///
/// Vendor ID
///
- UINT16 Vid; // 0f00h
+ UINT16 Vid; // 0f00h
///
/// Device ID
///
- UINT16 Did; // 0f02h
+ UINT16 Did; // 0f02h
///
/// Revision ID
///
- UINT8 Rid; // 0f04h
- UINT8 Reserved[0x7b]; // 0f05h
+ UINT8 Rid; // 0f04h
+ UINT8 Reserved[0x7b]; // 0f05h
///
/// Alias to I/O legacy space.
///
- UINT32 LegacyAddress1; // 0f80h
+ UINT32 LegacyAddress1; // 0f80h
///
/// Additional 8 bits for I/O legacy space extension.
///
- UINT32 LegacyAddress1Ex; // 0f84h
+ UINT32 LegacyAddress1Ex; // 0f84h
///
/// Alias to second I/O legacy space.
///
- UINT32 LegacyAddress2; // 0f88h
+ UINT32 LegacyAddress2; // 0f88h
///
/// Additional 8 bits for second I/O legacy space extension.
///
- UINT32 LegacyAddress2Ex; // 0f8ch
+ UINT32 LegacyAddress2Ex; // 0f8ch
///
/// Vendor-defined configuration registers.
///
- UINT8 VendorDefined[0x70];// 0f90h
+ UINT8 VendorDefined[0x70]; // 0f90h
} TIS_PC_REGISTERS;
//
@@ -98,7 +98,7 @@ typedef struct {
//
// Define pointer types used to access TIS registers on PC
//
-typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;
+typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;
//
// Define bits of ACCESS and STATUS registers
@@ -107,75 +107,75 @@ typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;
///
/// This bit is a 1 to indicate that the other bits in this register are valid.
///
-#define TIS_PC_VALID BIT7
+#define TIS_PC_VALID BIT7
///
/// Indicate that this locality is active.
///
-#define TIS_PC_ACC_ACTIVE BIT5
+#define TIS_PC_ACC_ACTIVE BIT5
///
/// Set to 1 to indicate that this locality had the TPM taken away while
/// this locality had the TIS_PC_ACC_ACTIVE bit set.
///
-#define TIS_PC_ACC_SEIZED BIT4
+#define TIS_PC_ACC_SEIZED BIT4
///
/// Set to 1 to indicate that TPM MUST reset the
/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
/// locality that is writing this bit.
///
-#define TIS_PC_ACC_SEIZE BIT3
+#define TIS_PC_ACC_SEIZE BIT3
///
/// When this bit is 1, another locality is requesting usage of the TPM.
///
-#define TIS_PC_ACC_PENDIND BIT2
+#define TIS_PC_ACC_PENDIND BIT2
///
/// Set to 1 to indicate that this locality is requesting to use TPM.
///
-#define TIS_PC_ACC_RQUUSE BIT1
+#define TIS_PC_ACC_RQUUSE BIT1
///
/// A value of 1 indicates that a T/OS has not been established on the platform
///
-#define TIS_PC_ACC_ESTABLISH BIT0
+#define TIS_PC_ACC_ESTABLISH BIT0
///
/// Write a 1 to this bit to notify TPM to cancel currently executing command
///
-#define TIS_PC_STS_CANCEL BIT24
+#define TIS_PC_STS_CANCEL BIT24
///
/// This field indicates that STS_DATA and STS_EXPECT are valid
///
-#define TIS_PC_STS_VALID BIT7
+#define TIS_PC_STS_VALID BIT7
///
/// When this bit is 1, TPM is in the Ready state,
/// indicating it is ready to receive a new command.
///
-#define TIS_PC_STS_READY BIT6
+#define TIS_PC_STS_READY BIT6
///
/// Write a 1 to this bit to cause the TPM to execute that command.
///
-#define TIS_PC_STS_GO BIT5
+#define TIS_PC_STS_GO BIT5
///
/// This bit indicates that the TPM has data available as a response.
///
-#define TIS_PC_STS_DATA BIT4
+#define TIS_PC_STS_DATA BIT4
///
/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
///
-#define TIS_PC_STS_EXPECT BIT3
+#define TIS_PC_STS_EXPECT BIT3
///
/// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.
///
-#define TIS_PC_STS_SELFTEST_DONE BIT2
+#define TIS_PC_STS_SELFTEST_DONE BIT2
///
/// Writes a 1 to this bit to force the TPM to re-send the response.
///
-#define TIS_PC_STS_RETRY BIT1
+#define TIS_PC_STS_RETRY BIT1
//
// Default TimeOut value
//
-#define TIS_TIMEOUT_A (750 * 1000) // 750ms
-#define TIS_TIMEOUT_B (2000 * 1000) // 2s
-#define TIS_TIMEOUT_C (750 * 1000) // 750ms
-#define TIS_TIMEOUT_D (750 * 1000) // 750ms
+#define TIS_TIMEOUT_A (750 * 1000) // 750ms
+#define TIS_TIMEOUT_B (2000 * 1000) // 2s
+#define TIS_TIMEOUT_C (750 * 1000) // 750ms
+#define TIS_TIMEOUT_D (750 * 1000) // 750ms
#endif
diff --git a/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h b/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h
index b2684806..77866bb2 100644
--- a/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h
+++ b/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h
@@ -10,9 +10,9 @@
#ifndef __UEFI_TCG_PLATFORM_H__
#define __UEFI_TCG_PLATFORM_H__
-#include
#include
#include
+#include
//
// Standard event types
@@ -37,22 +37,22 @@
//
// EFI specific event types
//
-#define EV_EFI_EVENT_BASE ((TCG_EVENTTYPE) 0x80000000)
-#define EV_EFI_VARIABLE_DRIVER_CONFIG (EV_EFI_EVENT_BASE + 1)
-#define EV_EFI_VARIABLE_BOOT (EV_EFI_EVENT_BASE + 2)
-#define EV_EFI_BOOT_SERVICES_APPLICATION (EV_EFI_EVENT_BASE + 3)
-#define EV_EFI_BOOT_SERVICES_DRIVER (EV_EFI_EVENT_BASE + 4)
-#define EV_EFI_RUNTIME_SERVICES_DRIVER (EV_EFI_EVENT_BASE + 5)
-#define EV_EFI_GPT_EVENT (EV_EFI_EVENT_BASE + 6)
-#define EV_EFI_ACTION (EV_EFI_EVENT_BASE + 7)
-#define EV_EFI_PLATFORM_FIRMWARE_BLOB (EV_EFI_EVENT_BASE + 8)
-#define EV_EFI_HANDOFF_TABLES (EV_EFI_EVENT_BASE + 9)
-#define EV_EFI_PLATFORM_FIRMWARE_BLOB2 (EV_EFI_EVENT_BASE + 0xA)
-#define EV_EFI_HANDOFF_TABLES2 (EV_EFI_EVENT_BASE + 0xB)
-#define EV_EFI_HCRTM_EVENT (EV_EFI_EVENT_BASE + 0x10)
-#define EV_EFI_VARIABLE_AUTHORITY (EV_EFI_EVENT_BASE + 0xE0)
-#define EV_EFI_SPDM_FIRMWARE_BLOB (EV_EFI_EVENT_BASE + 0xE1)
-#define EV_EFI_SPDM_FIRMWARE_CONFIG (EV_EFI_EVENT_BASE + 0xE2)
+#define EV_EFI_EVENT_BASE ((TCG_EVENTTYPE) 0x80000000)
+#define EV_EFI_VARIABLE_DRIVER_CONFIG (EV_EFI_EVENT_BASE + 1)
+#define EV_EFI_VARIABLE_BOOT (EV_EFI_EVENT_BASE + 2)
+#define EV_EFI_BOOT_SERVICES_APPLICATION (EV_EFI_EVENT_BASE + 3)
+#define EV_EFI_BOOT_SERVICES_DRIVER (EV_EFI_EVENT_BASE + 4)
+#define EV_EFI_RUNTIME_SERVICES_DRIVER (EV_EFI_EVENT_BASE + 5)
+#define EV_EFI_GPT_EVENT (EV_EFI_EVENT_BASE + 6)
+#define EV_EFI_ACTION (EV_EFI_EVENT_BASE + 7)
+#define EV_EFI_PLATFORM_FIRMWARE_BLOB (EV_EFI_EVENT_BASE + 8)
+#define EV_EFI_HANDOFF_TABLES (EV_EFI_EVENT_BASE + 9)
+#define EV_EFI_PLATFORM_FIRMWARE_BLOB2 (EV_EFI_EVENT_BASE + 0xA)
+#define EV_EFI_HANDOFF_TABLES2 (EV_EFI_EVENT_BASE + 0xB)
+#define EV_EFI_HCRTM_EVENT (EV_EFI_EVENT_BASE + 0x10)
+#define EV_EFI_VARIABLE_AUTHORITY (EV_EFI_EVENT_BASE + 0xE0)
+#define EV_EFI_SPDM_FIRMWARE_BLOB (EV_EFI_EVENT_BASE + 0xE1)
+#define EV_EFI_SPDM_FIRMWARE_CONFIG (EV_EFI_EVENT_BASE + 0xE2)
#define EFI_CALLING_EFI_APPLICATION \
"Calling EFI Application from Boot Option"
@@ -65,24 +65,23 @@
#define EFI_EXIT_BOOT_SERVICES_SUCCEEDED \
"Exit Boot Services Returned with Success"
+#define EV_POSTCODE_INFO_POST_CODE "POST CODE"
+#define POST_CODE_STR_LEN (sizeof(EV_POSTCODE_INFO_POST_CODE) - 1)
-#define EV_POSTCODE_INFO_POST_CODE "POST CODE"
-#define POST_CODE_STR_LEN (sizeof(EV_POSTCODE_INFO_POST_CODE) - 1)
+#define EV_POSTCODE_INFO_SMM_CODE "SMM CODE"
+#define SMM_CODE_STR_LEN (sizeof(EV_POSTCODE_INFO_SMM_CODE) - 1)
-#define EV_POSTCODE_INFO_SMM_CODE "SMM CODE"
-#define SMM_CODE_STR_LEN (sizeof(EV_POSTCODE_INFO_SMM_CODE) - 1)
+#define EV_POSTCODE_INFO_ACPI_DATA "ACPI DATA"
+#define ACPI_DATA_LEN (sizeof(EV_POSTCODE_INFO_ACPI_DATA) - 1)
-#define EV_POSTCODE_INFO_ACPI_DATA "ACPI DATA"
-#define ACPI_DATA_LEN (sizeof(EV_POSTCODE_INFO_ACPI_DATA) - 1)
+#define EV_POSTCODE_INFO_BIS_CODE "BIS CODE"
+#define BIS_CODE_LEN (sizeof(EV_POSTCODE_INFO_BIS_CODE) - 1)
-#define EV_POSTCODE_INFO_BIS_CODE "BIS CODE"
-#define BIS_CODE_LEN (sizeof(EV_POSTCODE_INFO_BIS_CODE) - 1)
+#define EV_POSTCODE_INFO_UEFI_PI "UEFI PI"
+#define UEFI_PI_LEN (sizeof(EV_POSTCODE_INFO_UEFI_PI) - 1)
-#define EV_POSTCODE_INFO_UEFI_PI "UEFI PI"
-#define UEFI_PI_LEN (sizeof(EV_POSTCODE_INFO_UEFI_PI) - 1)
-
-#define EV_POSTCODE_INFO_OPROM "Embedded Option ROM"
-#define OPROM_LEN (sizeof(EV_POSTCODE_INFO_OPROM) - 1)
+#define EV_POSTCODE_INFO_OPROM "Embedded Option ROM"
+#define OPROM_LEN (sizeof(EV_POSTCODE_INFO_OPROM) - 1)
#define EV_POSTCODE_INFO_EMBEDDED_UEFI_DRIVER "Embedded UEFI Driver"
#define EMBEDDED_UEFI_DRIVER_LEN (sizeof(EV_POSTCODE_INFO_EMBEDDED_UEFI_DRIVER) - 1)
@@ -95,30 +94,30 @@
//
#pragma pack (1)
-typedef UINT32 TCG_EVENTTYPE;
-typedef TPM_PCRINDEX TCG_PCRINDEX;
-typedef TPM_DIGEST TCG_DIGEST;
+typedef UINT32 TCG_EVENTTYPE;
+typedef TPM_PCRINDEX TCG_PCRINDEX;
+typedef TPM_DIGEST TCG_DIGEST;
///
/// Event Log Entry Structure Definition
///
typedef struct tdTCG_PCR_EVENT {
- TCG_PCRINDEX PCRIndex; ///< PCRIndex event extended to
- TCG_EVENTTYPE EventType; ///< TCG EFI event type
- TCG_DIGEST Digest; ///< Value extended into PCRIndex
- UINT32 EventSize; ///< Size of the event data
- UINT8 Event[1]; ///< The event data
+ TCG_PCRINDEX PCRIndex; ///< PCRIndex event extended to
+ TCG_EVENTTYPE EventType; ///< TCG EFI event type
+ TCG_DIGEST Digest; ///< Value extended into PCRIndex
+ UINT32 EventSize; ///< Size of the event data
+ UINT8 Event[1]; ///< The event data
} TCG_PCR_EVENT;
-#define TSS_EVENT_DATA_MAX_SIZE 256
+#define TSS_EVENT_DATA_MAX_SIZE 256
///
/// TCG_PCR_EVENT_HDR
///
typedef struct tdTCG_PCR_EVENT_HDR {
- TCG_PCRINDEX PCRIndex;
- TCG_EVENTTYPE EventType;
- TCG_DIGEST Digest;
- UINT32 EventSize;
+ TCG_PCRINDEX PCRIndex;
+ TCG_EVENTTYPE EventType;
+ TCG_DIGEST Digest;
+ UINT32 EventSize;
} TCG_PCR_EVENT_HDR;
///
@@ -128,8 +127,8 @@ typedef struct tdTCG_PCR_EVENT_HDR {
/// because PEI is 32-bit while DXE is 64-bit on x64 platforms
///
typedef struct tdEFI_PLATFORM_FIRMWARE_BLOB {
- EFI_PHYSICAL_ADDRESS BlobBase;
- UINT64 BlobLength;
+ EFI_PHYSICAL_ADDRESS BlobBase;
+ UINT64 BlobLength;
} EFI_PLATFORM_FIRMWARE_BLOB;
///
@@ -139,8 +138,8 @@ typedef struct tdEFI_PLATFORM_FIRMWARE_BLOB {
/// event to facilitate the measurement of firmware volume.
///
typedef struct tdUEFI_PLATFORM_FIRMWARE_BLOB {
- EFI_PHYSICAL_ADDRESS BlobBase;
- UINT64 BlobLength;
+ EFI_PHYSICAL_ADDRESS BlobBase;
+ UINT64 BlobLength;
} UEFI_PLATFORM_FIRMWARE_BLOB;
///
@@ -150,10 +149,10 @@ typedef struct tdUEFI_PLATFORM_FIRMWARE_BLOB {
/// event to facilitate the measurement of firmware volume.
///
typedef struct tdUEFI_PLATFORM_FIRMWARE_BLOB2 {
- UINT8 BlobDescriptionSize;
-//UINT8 BlobDescription[BlobDescriptionSize];
-//EFI_PHYSICAL_ADDRESS BlobBase;
-//UINT64 BlobLength;
+ UINT8 BlobDescriptionSize;
+ // UINT8 BlobDescription[BlobDescriptionSize];
+ // EFI_PHYSICAL_ADDRESS BlobBase;
+ // UINT64 BlobLength;
} UEFI_PLATFORM_FIRMWARE_BLOB2;
///
@@ -163,11 +162,11 @@ typedef struct tdUEFI_PLATFORM_FIRMWARE_BLOB2 {
/// EV_EFI_BOOT_SERVICES_DRIVER and EV_EFI_RUNTIME_SERVICES_DRIVER
///
typedef struct tdEFI_IMAGE_LOAD_EVENT {
- EFI_PHYSICAL_ADDRESS ImageLocationInMemory;
- UINTN ImageLengthInMemory;
- UINTN ImageLinkTimeAddress;
- UINTN LengthOfDevicePath;
- EFI_DEVICE_PATH_PROTOCOL DevicePath[1];
+ EFI_PHYSICAL_ADDRESS ImageLocationInMemory;
+ UINTN ImageLengthInMemory;
+ UINTN ImageLinkTimeAddress;
+ UINTN LengthOfDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL DevicePath[1];
} EFI_IMAGE_LOAD_EVENT;
///
@@ -177,11 +176,11 @@ typedef struct tdEFI_IMAGE_LOAD_EVENT {
/// EV_EFI_BOOT_SERVICES_DRIVER and EV_EFI_RUNTIME_SERVICES_DRIVER
///
typedef struct tdUEFI_IMAGE_LOAD_EVENT {
- EFI_PHYSICAL_ADDRESS ImageLocationInMemory;
- UINT64 ImageLengthInMemory;
- UINT64 ImageLinkTimeAddress;
- UINT64 LengthOfDevicePath;
- EFI_DEVICE_PATH_PROTOCOL DevicePath[1];
+ EFI_PHYSICAL_ADDRESS ImageLocationInMemory;
+ UINT64 ImageLengthInMemory;
+ UINT64 ImageLinkTimeAddress;
+ UINT64 LengthOfDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL DevicePath[1];
} UEFI_IMAGE_LOAD_EVENT;
///
@@ -191,8 +190,8 @@ typedef struct tdUEFI_IMAGE_LOAD_EVENT {
/// the measurement of given configuration tables.
///
typedef struct tdEFI_HANDOFF_TABLE_POINTERS {
- UINTN NumberOfTables;
- EFI_CONFIGURATION_TABLE TableEntry[1];
+ UINTN NumberOfTables;
+ EFI_CONFIGURATION_TABLE TableEntry[1];
} EFI_HANDOFF_TABLE_POINTERS;
///
@@ -202,8 +201,8 @@ typedef struct tdEFI_HANDOFF_TABLE_POINTERS {
/// the measurement of given configuration tables.
///
typedef struct tdUEFI_HANDOFF_TABLE_POINTERS {
- UINT64 NumberOfTables;
- EFI_CONFIGURATION_TABLE TableEntry[1];
+ UINT64 NumberOfTables;
+ EFI_CONFIGURATION_TABLE TableEntry[1];
} UEFI_HANDOFF_TABLE_POINTERS;
///
@@ -213,10 +212,10 @@ typedef struct tdUEFI_HANDOFF_TABLE_POINTERS {
/// the measurement of given configuration tables.
///
typedef struct tdUEFI_HANDOFF_TABLE_POINTERS2 {
- UINT8 TableDescriptionSize;
-//UINT8 TableDescription[TableDescriptionSize];
-//UINT64 NumberOfTables;
-//EFI_CONFIGURATION_TABLE TableEntry[1];
+ UINT8 TableDescriptionSize;
+ // UINT8 TableDescription[TableDescriptionSize];
+ // UINT64 NumberOfTables;
+ // EFI_CONFIGURATION_TABLE TableEntry[1];
} UEFI_HANDOFF_TABLE_POINTERS2;
///
@@ -228,11 +227,11 @@ typedef struct tdUEFI_HANDOFF_TABLE_POINTERS2 {
/// This is defined in TCG EFI Platform Spec for TPM1.1 or 1.2 V1.22
///
typedef struct tdEFI_VARIABLE_DATA {
- EFI_GUID VariableName;
- UINTN UnicodeNameLength;
- UINTN VariableDataLength;
- CHAR16 UnicodeName[1];
- INT8 VariableData[1]; ///< Driver or platform-specific data
+ EFI_GUID VariableName;
+ UINTN UnicodeNameLength;
+ UINTN VariableDataLength;
+ CHAR16 UnicodeName[1];
+ INT8 VariableData[1]; ///< Driver or platform-specific data
} EFI_VARIABLE_DATA;
///
@@ -244,38 +243,38 @@ typedef struct tdEFI_VARIABLE_DATA {
/// This is defined in TCG PC Client Firmware Profile Spec 00.21
///
typedef struct tdUEFI_VARIABLE_DATA {
- EFI_GUID VariableName;
- UINT64 UnicodeNameLength;
- UINT64 VariableDataLength;
- CHAR16 UnicodeName[1];
- INT8 VariableData[1]; ///< Driver or platform-specific data
+ EFI_GUID VariableName;
+ UINT64 UnicodeNameLength;
+ UINT64 VariableDataLength;
+ CHAR16 UnicodeName[1];
+ INT8 VariableData[1]; ///< Driver or platform-specific data
} UEFI_VARIABLE_DATA;
//
// For TrEE1.0 compatibility
//
typedef struct {
- EFI_GUID VariableName;
- UINT64 UnicodeNameLength; // The TCG Definition used UINTN
- UINT64 VariableDataLength; // The TCG Definition used UINTN
- CHAR16 UnicodeName[1];
- INT8 VariableData[1];
+ EFI_GUID VariableName;
+ UINT64 UnicodeNameLength; // The TCG Definition used UINTN
+ UINT64 VariableDataLength; // The TCG Definition used UINTN
+ CHAR16 UnicodeName[1];
+ INT8 VariableData[1];
} EFI_VARIABLE_DATA_TREE;
typedef struct tdEFI_GPT_DATA {
- EFI_PARTITION_TABLE_HEADER EfiPartitionHeader;
- UINTN NumberOfPartitions;
- EFI_PARTITION_ENTRY Partitions[1];
+ EFI_PARTITION_TABLE_HEADER EfiPartitionHeader;
+ UINTN NumberOfPartitions;
+ EFI_PARTITION_ENTRY Partitions[1];
} EFI_GPT_DATA;
typedef struct tdUEFI_GPT_DATA {
- EFI_PARTITION_TABLE_HEADER EfiPartitionHeader;
- UINT64 NumberOfPartitions;
- EFI_PARTITION_ENTRY Partitions[1];
+ EFI_PARTITION_TABLE_HEADER EfiPartitionHeader;
+ UINT64 NumberOfPartitions;
+ EFI_PARTITION_ENTRY Partitions[1];
} UEFI_GPT_DATA;
-#define TCG_DEVICE_SECURITY_EVENT_DATA_SIGNATURE "SPDM Device Sec"
-#define TCG_DEVICE_SECURITY_EVENT_DATA_VERSION 1
+#define TCG_DEVICE_SECURITY_EVENT_DATA_SIGNATURE "SPDM Device Sec"
+#define TCG_DEVICE_SECURITY_EVENT_DATA_VERSION 1
#define TCG_DEVICE_SECURITY_EVENT_DATA_DEVICE_TYPE_NULL 0
#define TCG_DEVICE_SECURITY_EVENT_DATA_DEVICE_TYPE_PCI 1
@@ -287,12 +286,12 @@ typedef struct tdUEFI_GPT_DATA {
/// used in EV_EFI_SPDM_FIRMWARE_BLOB and EV_EFI_SPDM_FIRMWARE_CONFIG.
///
typedef struct {
- UINT8 Signature[16];
- UINT16 Version;
- UINT16 Length;
- UINT32 SpdmHashAlgo;
- UINT32 DeviceType;
-//SPDM_MEASUREMENT_BLOCK SpdmMeasurementBlock;
+ UINT8 Signature[16];
+ UINT16 Version;
+ UINT16 Length;
+ UINT32 SpdmHashAlgo;
+ UINT32 DeviceType;
+ // SPDM_MEASUREMENT_BLOCK SpdmMeasurementBlock;
} TCG_DEVICE_SECURITY_EVENT_DATA_HEADER;
#define TCG_DEVICE_SECURITY_EVENT_DATA_PCI_CONTEXT_VERSION 0
@@ -303,14 +302,14 @@ typedef struct {
/// used in EV_EFI_SPDM_FIRMWARE_BLOB and EV_EFI_SPDM_FIRMWARE_CONFIG.
///
typedef struct {
- UINT16 Version;
- UINT16 Length;
- UINT16 VendorId;
- UINT16 DeviceId;
- UINT8 RevisionID;
- UINT8 ClassCode[3];
- UINT16 SubsystemVendorID;
- UINT16 SubsystemID;
+ UINT16 Version;
+ UINT16 Length;
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT8 RevisionID;
+ UINT8 ClassCode[3];
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemID;
} TCG_DEVICE_SECURITY_EVENT_DATA_PCI_CONTEXT;
#define TCG_DEVICE_SECURITY_EVENT_DATA_USB_CONTEXT_VERSION 0
@@ -321,33 +320,33 @@ typedef struct {
/// used in EV_EFI_SPDM_FIRMWARE_BLOB and EV_EFI_SPDM_FIRMWARE_CONFIG.
///
typedef struct {
- UINT16 Version;
- UINT16 Length;
-//UINT8 DeviceDescriptor[DescLen];
-//UINT8 BodDescriptor[DescLen];
-//UINT8 ConfigurationDescriptor[DescLen][NumOfConfiguration];
+ UINT16 Version;
+ UINT16 Length;
+ // UINT8 DeviceDescriptor[DescLen];
+ // UINT8 BodDescriptor[DescLen];
+ // UINT8 ConfigurationDescriptor[DescLen][NumOfConfiguration];
} TCG_DEVICE_SECURITY_EVENT_DATA_USB_CONTEXT;
//
// Crypto Agile Log Entry Format
//
typedef struct tdTCG_PCR_EVENT2 {
- TCG_PCRINDEX PCRIndex;
- TCG_EVENTTYPE EventType;
- TPML_DIGEST_VALUES Digest;
- UINT32 EventSize;
- UINT8 Event[1];
+ TCG_PCRINDEX PCRIndex;
+ TCG_EVENTTYPE EventType;
+ TPML_DIGEST_VALUES Digest;
+ UINT32 EventSize;
+ UINT8 Event[1];
} TCG_PCR_EVENT2;
//
// TCG PCR Event2 Header
// Follow TCG EFI Protocol Spec 5.2 Crypto Agile Log Entry Format
//
-typedef struct tdTCG_PCR_EVENT2_HDR{
- TCG_PCRINDEX PCRIndex;
- TCG_EVENTTYPE EventType;
- TPML_DIGEST_VALUES Digests;
- UINT32 EventSize;
+typedef struct tdTCG_PCR_EVENT2_HDR {
+ TCG_PCRINDEX PCRIndex;
+ TCG_EVENTTYPE EventType;
+ TPML_DIGEST_VALUES Digests;
+ UINT32 EventSize;
} TCG_PCR_EVENT2_HDR;
//
@@ -357,19 +356,19 @@ typedef struct {
//
// TCG defined hashing algorithm ID.
//
- UINT16 algorithmId;
+ UINT16 algorithmId;
//
// The size of the digest for the respective hashing algorithm.
//
- UINT16 digestSize;
+ UINT16 digestSize;
} TCG_EfiSpecIdEventAlgorithmSize;
-#define TCG_EfiSpecIDEventStruct_SIGNATURE_02 "Spec ID Event02"
-#define TCG_EfiSpecIDEventStruct_SIGNATURE_03 "Spec ID Event03"
+#define TCG_EfiSpecIDEventStruct_SIGNATURE_02 "Spec ID Event02"
+#define TCG_EfiSpecIDEventStruct_SIGNATURE_03 "Spec ID Event03"
-#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MAJOR_TPM12 1
-#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MINOR_TPM12 2
-#define TCG_EfiSpecIDEventStruct_SPEC_ERRATA_TPM12 2
+#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MAJOR_TPM12 1
+#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MINOR_TPM12 2
+#define TCG_EfiSpecIDEventStruct_SPEC_ERRATA_TPM12 2
#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MAJOR_TPM2 2
#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MINOR_TPM2 0
@@ -377,124 +376,120 @@ typedef struct {
#define TCG_EfiSpecIDEventStruct_SPEC_ERRATA_TPM2_REV_105 105
typedef struct {
- UINT8 signature[16];
+ UINT8 signature[16];
//
// The value for the Platform Class.
// The enumeration is defined in the TCG ACPI Specification Client Common Header.
//
- UINT32 platformClass;
+ UINT32 platformClass;
//
// The TCG EFI Platform Specification minor version number this BIOS supports.
// Any BIOS supporting version (1.22) MUST set this value to 02h.
// Any BIOS supporting version (2.0) SHALL set this value to 0x00.
//
- UINT8 specVersionMinor;
+ UINT8 specVersionMinor;
//
// The TCG EFI Platform Specification major version number this BIOS supports.
// Any BIOS supporting version (1.22) MUST set this value to 01h.
// Any BIOS supporting version (2.0) SHALL set this value to 0x02.
//
- UINT8 specVersionMajor;
+ UINT8 specVersionMajor;
//
// The TCG EFI Platform Specification errata for this specification this BIOS supports.
// Any BIOS supporting version and errata (1.22) MUST set this value to 02h.
// Any BIOS supporting version and errata (2.0) SHALL set this value to 0x00.
//
- UINT8 specErrata;
+ UINT8 specErrata;
//
// Specifies the size of the UINTN fields used in various data structures used in this specification.
// 0x01 indicates UINT32 and 0x02 indicates UINT64.
//
- UINT8 uintnSize;
+ UINT8 uintnSize;
//
// This field is added in "Spec ID Event03".
// The number of hashing algorithms used in this event log (except the first event).
// All events in this event log use all hashing algorithms defined here.
//
-//UINT32 numberOfAlgorithms;
+ // UINT32 numberOfAlgorithms;
//
// This field is added in "Spec ID Event03".
// An array of size numberOfAlgorithms of value pairs.
//
-//TCG_EfiSpecIdEventAlgorithmSize digestSize[numberOfAlgorithms];
+ // TCG_EfiSpecIdEventAlgorithmSize digestSize[numberOfAlgorithms];
//
// Size in bytes of the VendorInfo field.
// Maximum value SHALL be FFh bytes.
//
-//UINT8 vendorInfoSize;
+ // UINT8 vendorInfoSize;
//
// Provided for use by the BIOS implementer.
// The value might be used, for example, to provide more detailed information about the specific BIOS such as BIOS revision numbers, etc.
// The values within this field are not standardized and are implementer-specific.
// Platform-specific or -unique information SHALL NOT be provided in this field.
//
-//UINT8 vendorInfo[vendorInfoSize];
+ // UINT8 vendorInfo[vendorInfoSize];
} TCG_EfiSpecIDEventStruct;
typedef struct tdTCG_PCClientTaggedEvent {
- UINT32 taggedEventID;
- UINT32 taggedEventDataSize;
-//UINT8 taggedEventData[taggedEventDataSize];
+ UINT32 taggedEventID;
+ UINT32 taggedEventDataSize;
+ // UINT8 taggedEventData[taggedEventDataSize];
} TCG_PCClientTaggedEvent;
-#define TCG_Sp800_155_PlatformId_Event_SIGNATURE "SP800-155 Event"
-#define TCG_Sp800_155_PlatformId_Event2_SIGNATURE "SP800-155 Event2"
+#define TCG_Sp800_155_PlatformId_Event_SIGNATURE "SP800-155 Event"
+#define TCG_Sp800_155_PlatformId_Event2_SIGNATURE "SP800-155 Event2"
typedef struct tdTCG_Sp800_155_PlatformId_Event2 {
- UINT8 Signature[16];
+ UINT8 Signature[16];
//
// Where Vendor ID is an integer defined
// at http://www.iana.org/assignments/enterprisenumbers
//
- UINT32 VendorId;
+ UINT32 VendorId;
//
// 16-byte identifier of a given platform's static configuration of code
//
- EFI_GUID ReferenceManifestGuid;
+ EFI_GUID ReferenceManifestGuid;
//
// Below structure is newly added in TCG_Sp800_155_PlatformId_Event2.
//
-//UINT8 PlatformManufacturerStrSize;
-//UINT8 PlatformManufacturerStr[PlatformManufacturerStrSize];
-//UINT8 PlatformModelSize;
-//UINT8 PlatformModel[PlatformModelSize];
-//UINT8 PlatformVersionSize;
-//UINT8 PlatformVersion[PlatformVersionSize];
-//UINT8 PlatformModelSize;
-//UINT8 PlatformModel[PlatformModelSize];
-//UINT8 FirmwareManufacturerStrSize;
-//UINT8 FirmwareManufacturerStr[FirmwareManufacturerStrSize];
-//UINT32 FirmwareManufacturerId;
-//UINT8 FirmwareVersion;
-//UINT8 FirmwareVersion[FirmwareVersionSize]];
+ // UINT8 PlatformManufacturerStrSize;
+ // UINT8 PlatformManufacturerStr[PlatformManufacturerStrSize];
+ // UINT8 PlatformModelSize;
+ // UINT8 PlatformModel[PlatformModelSize];
+ // UINT8 PlatformVersionSize;
+ // UINT8 PlatformVersion[PlatformVersionSize];
+ // UINT8 PlatformModelSize;
+ // UINT8 PlatformModel[PlatformModelSize];
+ // UINT8 FirmwareManufacturerStrSize;
+ // UINT8 FirmwareManufacturerStr[FirmwareManufacturerStrSize];
+ // UINT32 FirmwareManufacturerId;
+ // UINT8 FirmwareVersion;
+ // UINT8 FirmwareVersion[FirmwareVersionSize]];
} TCG_Sp800_155_PlatformId_Event2;
-#define TCG_EfiStartupLocalityEvent_SIGNATURE "StartupLocality"
-
+#define TCG_EfiStartupLocalityEvent_SIGNATURE "StartupLocality"
//
// The Locality Indicator which sent the TPM2_Startup command
//
-#define LOCALITY_0_INDICATOR 0x00
-#define LOCALITY_3_INDICATOR 0x03
+#define LOCALITY_0_INDICATOR 0x00
+#define LOCALITY_3_INDICATOR 0x03
//
// Startup Locality Event
//
-typedef struct tdTCG_EfiStartupLocalityEvent{
- UINT8 Signature[16];
+typedef struct tdTCG_EfiStartupLocalityEvent {
+ UINT8 Signature[16];
//
// The Locality Indicator which sent the TPM2_Startup command
//
- UINT8 StartupLocality;
+ UINT8 StartupLocality;
} TCG_EfiStartupLocalityEvent;
-
//
// Restore original structure alignment
//
#pragma pack ()
#endif
-
-
diff --git a/MdePkg/Include/IndustryStandard/Usb.h b/MdePkg/Include/IndustryStandard/Usb.h
index e7c02e5a..3a096d91 100644
--- a/MdePkg/Include/IndustryStandard/Usb.h
+++ b/MdePkg/Include/IndustryStandard/Usb.h
@@ -16,52 +16,52 @@
//
// Usb mass storage class code
//
-#define USB_MASS_STORE_CLASS 0x08
+#define USB_MASS_STORE_CLASS 0x08
//
// Usb mass storage subclass code, specify the command set used.
//
-#define USB_MASS_STORE_RBC 0x01 ///< Reduced Block Commands
-#define USB_MASS_STORE_8020I 0x02 ///< SFF-8020i, typically a CD/DVD device
-#define USB_MASS_STORE_QIC 0x03 ///< Typically a tape device
-#define USB_MASS_STORE_UFI 0x04 ///< Typically a floppy disk driver device
-#define USB_MASS_STORE_8070I 0x05 ///< SFF-8070i, typically a floppy disk driver device.
-#define USB_MASS_STORE_SCSI 0x06 ///< SCSI transparent command set
+#define USB_MASS_STORE_RBC 0x01 ///< Reduced Block Commands
+#define USB_MASS_STORE_8020I 0x02 ///< SFF-8020i, typically a CD/DVD device
+#define USB_MASS_STORE_QIC 0x03 ///< Typically a tape device
+#define USB_MASS_STORE_UFI 0x04 ///< Typically a floppy disk driver device
+#define USB_MASS_STORE_8070I 0x05 ///< SFF-8070i, typically a floppy disk driver device.
+#define USB_MASS_STORE_SCSI 0x06 ///< SCSI transparent command set
//
// Usb mass storage protocol code, specify the transport protocol
//
-#define USB_MASS_STORE_CBI0 0x00 ///< CBI protocol with command completion interrupt
-#define USB_MASS_STORE_CBI1 0x01 ///< CBI protocol without command completion interrupt
-#define USB_MASS_STORE_BOT 0x50 ///< Bulk-Only Transport
+#define USB_MASS_STORE_CBI0 0x00 ///< CBI protocol with command completion interrupt
+#define USB_MASS_STORE_CBI1 0x01 ///< CBI protocol without command completion interrupt
+#define USB_MASS_STORE_BOT 0x50 ///< Bulk-Only Transport
//
// Standard device request and request type
// USB 2.0 spec, Section 9.4
//
-#define USB_DEV_GET_STATUS 0x00
-#define USB_DEV_GET_STATUS_REQ_TYPE_D 0x80 // Receiver : Device
-#define USB_DEV_GET_STATUS_REQ_TYPE_I 0x81 // Receiver : Interface
-#define USB_DEV_GET_STATUS_REQ_TYPE_E 0x82 // Receiver : Endpoint
+#define USB_DEV_GET_STATUS 0x00
+#define USB_DEV_GET_STATUS_REQ_TYPE_D 0x80 // Receiver : Device
+#define USB_DEV_GET_STATUS_REQ_TYPE_I 0x81 // Receiver : Interface
+#define USB_DEV_GET_STATUS_REQ_TYPE_E 0x82 // Receiver : Endpoint
-#define USB_DEV_CLEAR_FEATURE 0x01
-#define USB_DEV_CLEAR_FEATURE_REQ_TYPE_D 0x00 // Receiver : Device
-#define USB_DEV_CLEAR_FEATURE_REQ_TYPE_I 0x01 // Receiver : Interface
-#define USB_DEV_CLEAR_FEATURE_REQ_TYPE_E 0x02 // Receiver : Endpoint
+#define USB_DEV_CLEAR_FEATURE 0x01
+#define USB_DEV_CLEAR_FEATURE_REQ_TYPE_D 0x00 // Receiver : Device
+#define USB_DEV_CLEAR_FEATURE_REQ_TYPE_I 0x01 // Receiver : Interface
+#define USB_DEV_CLEAR_FEATURE_REQ_TYPE_E 0x02 // Receiver : Endpoint
-#define USB_DEV_SET_FEATURE 0x03
-#define USB_DEV_SET_FEATURE_REQ_TYPE_D 0x00 // Receiver : Device
-#define USB_DEV_SET_FEATURE_REQ_TYPE_I 0x01 // Receiver : Interface
-#define USB_DEV_SET_FEATURE_REQ_TYPE_E 0x02 // Receiver : Endpoint
+#define USB_DEV_SET_FEATURE 0x03
+#define USB_DEV_SET_FEATURE_REQ_TYPE_D 0x00 // Receiver : Device
+#define USB_DEV_SET_FEATURE_REQ_TYPE_I 0x01 // Receiver : Interface
+#define USB_DEV_SET_FEATURE_REQ_TYPE_E 0x02 // Receiver : Endpoint
-#define USB_DEV_SET_ADDRESS 0x05
-#define USB_DEV_SET_ADDRESS_REQ_TYPE 0x00
+#define USB_DEV_SET_ADDRESS 0x05
+#define USB_DEV_SET_ADDRESS_REQ_TYPE 0x00
-#define USB_DEV_GET_DESCRIPTOR 0x06
-#define USB_DEV_GET_DESCRIPTOR_REQ_TYPE 0x80
+#define USB_DEV_GET_DESCRIPTOR 0x06
+#define USB_DEV_GET_DESCRIPTOR_REQ_TYPE 0x80
-#define USB_DEV_SET_DESCRIPTOR 0x07
-#define USB_DEV_SET_DESCRIPTOR_REQ_TYPE 0x00
+#define USB_DEV_SET_DESCRIPTOR 0x07
+#define USB_DEV_SET_DESCRIPTOR_REQ_TYPE 0x00
#define USB_DEV_GET_CONFIGURATION 0x08
#define USB_DEV_GET_CONFIGURATION_REQ_TYPE 0x80
@@ -69,15 +69,14 @@
#define USB_DEV_SET_CONFIGURATION 0x09
#define USB_DEV_SET_CONFIGURATION_REQ_TYPE 0x00
-#define USB_DEV_GET_INTERFACE 0x0A
-#define USB_DEV_GET_INTERFACE_REQ_TYPE 0x81
+#define USB_DEV_GET_INTERFACE 0x0A
+#define USB_DEV_GET_INTERFACE_REQ_TYPE 0x81
-#define USB_DEV_SET_INTERFACE 0x0B
-#define USB_DEV_SET_INTERFACE_REQ_TYPE 0x01
-
-#define USB_DEV_SYNCH_FRAME 0x0C
-#define USB_DEV_SYNCH_FRAME_REQ_TYPE 0x82
+#define USB_DEV_SET_INTERFACE 0x0B
+#define USB_DEV_SET_INTERFACE_REQ_TYPE 0x01
+#define USB_DEV_SYNCH_FRAME 0x0C
+#define USB_DEV_SYNCH_FRAME_REQ_TYPE 0x82
//
// USB standard descriptors and reqeust
@@ -89,11 +88,11 @@
/// USB 2.0 spec, Section 9.3
///
typedef struct {
- UINT8 RequestType;
- UINT8 Request;
- UINT16 Value;
- UINT16 Index;
- UINT16 Length;
+ UINT8 RequestType;
+ UINT8 Request;
+ UINT16 Value;
+ UINT16 Index;
+ UINT16 Length;
} USB_DEVICE_REQUEST;
///
@@ -101,20 +100,20 @@ typedef struct {
/// USB 2.0 spec, Section 9.6.1
///
typedef struct {
- UINT8 Length;
- UINT8 DescriptorType;
- UINT16 BcdUSB;
- UINT8 DeviceClass;
- UINT8 DeviceSubClass;
- UINT8 DeviceProtocol;
- UINT8 MaxPacketSize0;
- UINT16 IdVendor;
- UINT16 IdProduct;
- UINT16 BcdDevice;
- UINT8 StrManufacturer;
- UINT8 StrProduct;
- UINT8 StrSerialNumber;
- UINT8 NumConfigurations;
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT16 BcdUSB;
+ UINT8 DeviceClass;
+ UINT8 DeviceSubClass;
+ UINT8 DeviceProtocol;
+ UINT8 MaxPacketSize0;
+ UINT16 IdVendor;
+ UINT16 IdProduct;
+ UINT16 BcdDevice;
+ UINT8 StrManufacturer;
+ UINT8 StrProduct;
+ UINT8 StrSerialNumber;
+ UINT8 NumConfigurations;
} USB_DEVICE_DESCRIPTOR;
///
@@ -122,14 +121,14 @@ typedef struct {
/// USB 2.0 spec, Section 9.6.3
///
typedef struct {
- UINT8 Length;
- UINT8 DescriptorType;
- UINT16 TotalLength;
- UINT8 NumInterfaces;
- UINT8 ConfigurationValue;
- UINT8 Configuration;
- UINT8 Attributes;
- UINT8 MaxPower;
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT16 TotalLength;
+ UINT8 NumInterfaces;
+ UINT8 ConfigurationValue;
+ UINT8 Configuration;
+ UINT8 Attributes;
+ UINT8 MaxPower;
} USB_CONFIG_DESCRIPTOR;
///
@@ -137,15 +136,15 @@ typedef struct {
/// USB 2.0 spec, Section 9.6.5
///
typedef struct {
- UINT8 Length;
- UINT8 DescriptorType;
- UINT8 InterfaceNumber;
- UINT8 AlternateSetting;
- UINT8 NumEndpoints;
- UINT8 InterfaceClass;
- UINT8 InterfaceSubClass;
- UINT8 InterfaceProtocol;
- UINT8 Interface;
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT8 InterfaceNumber;
+ UINT8 AlternateSetting;
+ UINT8 NumEndpoints;
+ UINT8 InterfaceClass;
+ UINT8 InterfaceSubClass;
+ UINT8 InterfaceProtocol;
+ UINT8 Interface;
} USB_INTERFACE_DESCRIPTOR;
///
@@ -153,12 +152,12 @@ typedef struct {
/// USB 2.0 spec, Section 9.6.6
///
typedef struct {
- UINT8 Length;
- UINT8 DescriptorType;
- UINT8 EndpointAddress;
- UINT8 Attributes;
- UINT16 MaxPacketSize;
- UINT8 Interval;
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT8 EndpointAddress;
+ UINT8 Attributes;
+ UINT16 MaxPacketSize;
+ UINT8 Interval;
} USB_ENDPOINT_DESCRIPTOR;
///
@@ -166,45 +165,44 @@ typedef struct {
/// USB 2.0 spec, Section 9.6.7
///
typedef struct {
- UINT8 Length;
- UINT8 DescriptorType;
- CHAR16 String[1];
+ UINT8 Length;
+ UINT8 DescriptorType;
+ CHAR16 String[1];
} EFI_USB_STRING_DESCRIPTOR;
#pragma pack()
-
typedef enum {
//
// USB request type
//
- USB_REQ_TYPE_STANDARD = (0x00 << 5),
- USB_REQ_TYPE_CLASS = (0x01 << 5),
- USB_REQ_TYPE_VENDOR = (0x02 << 5),
+ USB_REQ_TYPE_STANDARD = (0x00 << 5),
+ USB_REQ_TYPE_CLASS = (0x01 << 5),
+ USB_REQ_TYPE_VENDOR = (0x02 << 5),
//
// Standard control transfer request type, or the value
// to fill in EFI_USB_DEVICE_REQUEST.Request
//
- USB_REQ_GET_STATUS = 0x00,
- USB_REQ_CLEAR_FEATURE = 0x01,
- USB_REQ_SET_FEATURE = 0x03,
- USB_REQ_SET_ADDRESS = 0x05,
- USB_REQ_GET_DESCRIPTOR = 0x06,
- USB_REQ_SET_DESCRIPTOR = 0x07,
- USB_REQ_GET_CONFIG = 0x08,
- USB_REQ_SET_CONFIG = 0x09,
- USB_REQ_GET_INTERFACE = 0x0A,
- USB_REQ_SET_INTERFACE = 0x0B,
- USB_REQ_SYNCH_FRAME = 0x0C,
+ USB_REQ_GET_STATUS = 0x00,
+ USB_REQ_CLEAR_FEATURE = 0x01,
+ USB_REQ_SET_FEATURE = 0x03,
+ USB_REQ_SET_ADDRESS = 0x05,
+ USB_REQ_GET_DESCRIPTOR = 0x06,
+ USB_REQ_SET_DESCRIPTOR = 0x07,
+ USB_REQ_GET_CONFIG = 0x08,
+ USB_REQ_SET_CONFIG = 0x09,
+ USB_REQ_GET_INTERFACE = 0x0A,
+ USB_REQ_SET_INTERFACE = 0x0B,
+ USB_REQ_SYNCH_FRAME = 0x0C,
//
// Usb control transfer target
//
- USB_TARGET_DEVICE = 0,
- USB_TARGET_INTERFACE = 0x01,
- USB_TARGET_ENDPOINT = 0x02,
- USB_TARGET_OTHER = 0x03,
+ USB_TARGET_DEVICE = 0,
+ USB_TARGET_INTERFACE = 0x01,
+ USB_TARGET_ENDPOINT = 0x02,
+ USB_TARGET_OTHER = 0x03,
//
// USB Descriptor types
@@ -225,21 +223,20 @@ typedef enum {
//
// USB endpoint types: 00: control, 01: isochronous, 10: bulk, 11: interrupt
//
- USB_ENDPOINT_CONTROL = 0x00,
- USB_ENDPOINT_ISO = 0x01,
- USB_ENDPOINT_BULK = 0x02,
- USB_ENDPOINT_INTERRUPT = 0x03,
+ USB_ENDPOINT_CONTROL = 0x00,
+ USB_ENDPOINT_ISO = 0x01,
+ USB_ENDPOINT_BULK = 0x02,
+ USB_ENDPOINT_INTERRUPT = 0x03,
- USB_ENDPOINT_TYPE_MASK = 0x03,
- USB_ENDPOINT_DIR_IN = 0x80,
+ USB_ENDPOINT_TYPE_MASK = 0x03,
+ USB_ENDPOINT_DIR_IN = 0x80,
//
- //Use 200 ms to increase the error handling response time
+ // Use 200 ms to increase the error handling response time
//
EFI_USB_INTERRUPT_DELAY = 2000000
} USB_TYPES_DEFINITION;
-
//
// HID constants definition, see Device Class Definition
// for Human Interface Devices (HID) rev1.11
@@ -253,19 +250,19 @@ typedef enum {
//
// HID specific requests.
//
-#define USB_HID_CLASS_GET_REQ_TYPE 0xa1
-#define USB_HID_CLASS_SET_REQ_TYPE 0x21
+#define USB_HID_CLASS_GET_REQ_TYPE 0xa1
+#define USB_HID_CLASS_SET_REQ_TYPE 0x21
//
// HID report item format
//
-#define HID_ITEM_FORMAT_SHORT 0
-#define HID_ITEM_FORMAT_LONG 1
+#define HID_ITEM_FORMAT_SHORT 0
+#define HID_ITEM_FORMAT_LONG 1
//
// Special tag indicating long items
//
-#define HID_ITEM_TAG_LONG 15
+#define HID_ITEM_TAG_LONG 15
//
// HID report descriptor item type (prefix bit 2,3)
@@ -287,15 +284,15 @@ typedef enum {
//
// HID report descriptor main item contents
//
-#define HID_MAIN_ITEM_CONSTANT 0x001
-#define HID_MAIN_ITEM_VARIABLE 0x002
-#define HID_MAIN_ITEM_RELATIVE 0x004
-#define HID_MAIN_ITEM_WRAP 0x008
-#define HID_MAIN_ITEM_NONLINEAR 0x010
-#define HID_MAIN_ITEM_NO_PREFERRED 0x020
-#define HID_MAIN_ITEM_NULL_STATE 0x040
-#define HID_MAIN_ITEM_VOLATILE 0x080
-#define HID_MAIN_ITEM_BUFFERED_BYTE 0x100
+#define HID_MAIN_ITEM_CONSTANT 0x001
+#define HID_MAIN_ITEM_VARIABLE 0x002
+#define HID_MAIN_ITEM_RELATIVE 0x004
+#define HID_MAIN_ITEM_WRAP 0x008
+#define HID_MAIN_ITEM_NONLINEAR 0x010
+#define HID_MAIN_ITEM_NO_PREFERRED 0x020
+#define HID_MAIN_ITEM_NULL_STATE 0x040
+#define HID_MAIN_ITEM_VOLATILE 0x080
+#define HID_MAIN_ITEM_BUFFERED_BYTE 0x100
//
// HID report descriptor collection item types
@@ -323,16 +320,16 @@ typedef enum {
//
// HID report descriptor local item tags
//
-#define HID_LOCAL_ITEM_TAG_USAGE 0
-#define HID_LOCAL_ITEM_TAG_USAGE_MINIMUM 1
-#define HID_LOCAL_ITEM_TAG_USAGE_MAXIMUM 2
-#define HID_LOCAL_ITEM_TAG_DESIGNATOR_INDEX 3
-#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MINIMUM 4
-#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MAXIMUM 5
-#define HID_LOCAL_ITEM_TAG_STRING_INDEX 7
-#define HID_LOCAL_ITEM_TAG_STRING_MINIMUM 8
-#define HID_LOCAL_ITEM_TAG_STRING_MAXIMUM 9
-#define HID_LOCAL_ITEM_TAG_DELIMITER 10
+#define HID_LOCAL_ITEM_TAG_USAGE 0
+#define HID_LOCAL_ITEM_TAG_USAGE_MINIMUM 1
+#define HID_LOCAL_ITEM_TAG_USAGE_MAXIMUM 2
+#define HID_LOCAL_ITEM_TAG_DESIGNATOR_INDEX 3
+#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MINIMUM 4
+#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MAXIMUM 5
+#define HID_LOCAL_ITEM_TAG_STRING_INDEX 7
+#define HID_LOCAL_ITEM_TAG_STRING_MINIMUM 8
+#define HID_LOCAL_ITEM_TAG_STRING_MAXIMUM 9
+#define HID_LOCAL_ITEM_TAG_DELIMITER 10
//
// HID report types
@@ -357,8 +354,8 @@ typedef enum {
/// HID 1.1, section 6.2.1
///
typedef struct hid_class_descriptor {
- UINT8 DescriptorType;
- UINT16 DescriptorLength;
+ UINT8 DescriptorType;
+ UINT16 DescriptorLength;
} EFI_USB_HID_CLASS_DESCRIPTOR;
///
@@ -367,12 +364,12 @@ typedef struct hid_class_descriptor {
/// HID 1.1, section 6.2.1
///
typedef struct hid_descriptor {
- UINT8 Length;
- UINT8 DescriptorType;
- UINT16 BcdHID;
- UINT8 CountryCode;
- UINT8 NumDescriptors;
- EFI_USB_HID_CLASS_DESCRIPTOR HidClassDesc[1];
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT16 BcdHID;
+ UINT8 CountryCode;
+ UINT8 NumDescriptors;
+ EFI_USB_HID_CLASS_DESCRIPTOR HidClassDesc[1];
} EFI_USB_HID_DESCRIPTOR;
#pragma pack()
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 9eb6ff93..7d020048 100755
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -6,6 +6,7 @@ Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
Copyright (c) Microsoft Corporation.
Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -22,16 +23,16 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
/// The IA-32 architecture context buffer used by SetJump() and LongJump().
///
typedef struct {
- UINT32 Ebx;
- UINT32 Esi;
- UINT32 Edi;
- UINT32 Ebp;
- UINT32 Esp;
- UINT32 Eip;
- UINT32 Ssp;
+ UINT32 Ebx;
+ UINT32 Esi;
+ UINT32 Edi;
+ UINT32 Ebp;
+ UINT32 Esp;
+ UINT32 Eip;
+ UINT32 Ssp;
} BASE_LIBRARY_JUMP_BUFFER;
-#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4
#endif // defined (MDE_CPU_IA32)
@@ -40,22 +41,22 @@ typedef struct {
/// The x64 architecture context buffer used by SetJump() and LongJump().
///
typedef struct {
- UINT64 Rbx;
- UINT64 Rsp;
- UINT64 Rbp;
- UINT64 Rdi;
- UINT64 Rsi;
- UINT64 R12;
- UINT64 R13;
- UINT64 R14;
- UINT64 R15;
- UINT64 Rip;
- UINT64 MxCsr;
- UINT8 XmmBuffer[160]; ///< XMM6-XMM15.
- UINT64 Ssp;
+ UINT64 Rbx;
+ UINT64 Rsp;
+ UINT64 Rbp;
+ UINT64 Rdi;
+ UINT64 Rsi;
+ UINT64 R12;
+ UINT64 R13;
+ UINT64 R14;
+ UINT64 R15;
+ UINT64 Rip;
+ UINT64 MxCsr;
+ UINT8 XmmBuffer[160]; ///< XMM6-XMM15.
+ UINT64 Ssp;
} BASE_LIBRARY_JUMP_BUFFER;
-#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
#endif // defined (MDE_CPU_X64)
@@ -64,14 +65,14 @@ typedef struct {
/// The EBC context buffer used by SetJump() and LongJump().
///
typedef struct {
- UINT64 R0;
- UINT64 R1;
- UINT64 R2;
- UINT64 R3;
- UINT64 IP;
+ UINT64 R0;
+ UINT64 R1;
+ UINT64 R2;
+ UINT64 R3;
+ UINT64 IP;
} BASE_LIBRARY_JUMP_BUFFER;
-#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
#endif // defined (MDE_CPU_EBC)
@@ -91,9 +92,9 @@ typedef struct {
UINT32 R14;
} BASE_LIBRARY_JUMP_BUFFER;
-#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4
-#endif // defined (MDE_CPU_ARM)
+#endif // defined (MDE_CPU_ARM)
#if defined (MDE_CPU_AARCH64)
typedef struct {
@@ -123,40 +124,117 @@ typedef struct {
UINT64 D15;
} BASE_LIBRARY_JUMP_BUFFER;
-#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
-#endif // defined (MDE_CPU_AARCH64)
+#endif // defined (MDE_CPU_AARCH64)
#if defined (MDE_CPU_RISCV64)
///
/// The RISC-V architecture context buffer used by SetJump() and LongJump().
///
typedef struct {
- UINT64 RA;
- UINT64 S0;
- UINT64 S1;
- UINT64 S2;
- UINT64 S3;
- UINT64 S4;
- UINT64 S5;
- UINT64 S6;
- UINT64 S7;
- UINT64 S8;
- UINT64 S9;
- UINT64 S10;
- UINT64 S11;
- UINT64 SP;
+ UINT64 RA;
+ UINT64 S0;
+ UINT64 S1;
+ UINT64 S2;
+ UINT64 S3;
+ UINT64 S4;
+ UINT64 S5;
+ UINT64 S6;
+ UINT64 S7;
+ UINT64 S8;
+ UINT64 S9;
+ UINT64 S10;
+ UINT64 S11;
+ UINT64 SP;
} BASE_LIBRARY_JUMP_BUFFER;
-#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
+
+VOID
+RiscVSetSupervisorScratch (
+ IN UINT64
+ );
+
+UINT64
+RiscVGetSupervisorScratch (
+ VOID
+ );
+
+VOID
+RiscVSetSupervisorStvec (
+ IN UINT64
+ );
+
+UINT64
+RiscVGetSupervisorStvec (
+ VOID
+ );
+
+UINT64
+RiscVGetSupervisorTrapCause (
+ VOID
+ );
+
+VOID
+RiscVSetSupervisorAddressTranslationRegister (
+ IN UINT64
+ );
+
+UINT64
+RiscVGetSupervisorAddressTranslationRegister (
+ VOID
+ );
+
+UINT64
+RiscVReadTimer (
+ VOID
+ );
+
+VOID
+RiscVEnableTimerInterrupt (
+ VOID
+ );
+
+VOID
+RiscVDisableTimerInterrupt (
+ VOID
+ );
+
+VOID
+RiscVClearPendingTimerInterrupt (
+ VOID
+ );
#endif // defined (MDE_CPU_RISCV64)
+#if defined (MDE_CPU_LOONGARCH64)
+///
+/// The LoongArch architecture context buffer used by SetJump() and LongJump()
+///
+typedef struct {
+ UINT64 S0;
+ UINT64 S1;
+ UINT64 S2;
+ UINT64 S3;
+ UINT64 S4;
+ UINT64 S5;
+ UINT64 S6;
+ UINT64 S7;
+ UINT64 S8;
+ UINT64 SP;
+ UINT64 FP;
+ UINT64 RA;
+} BASE_LIBRARY_JUMP_BUFFER;
+
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
+
+#endif // defined (MDE_CPU_LOONGARCH64)
+
//
// String Services
//
-
/**
Returns the length of a Null-terminated Unicode string.
@@ -176,8 +254,8 @@ typedef struct {
UINTN
EFIAPI
StrnLenS (
- IN CONST CHAR16 *String,
- IN UINTN MaxSize
+ IN CONST CHAR16 *String,
+ IN UINTN MaxSize
);
/**
@@ -204,8 +282,8 @@ StrnLenS (
UINTN
EFIAPI
StrnSizeS (
- IN CONST CHAR16 *String,
- IN UINTN MaxSize
+ IN CONST CHAR16 *String,
+ IN UINTN MaxSize
);
/**
@@ -237,9 +315,9 @@ StrnSizeS (
RETURN_STATUS
EFIAPI
StrCpyS (
- OUT CHAR16 *Destination,
- IN UINTN DestMax,
- IN CONST CHAR16 *Source
+ OUT CHAR16 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR16 *Source
);
/**
@@ -274,10 +352,10 @@ StrCpyS (
RETURN_STATUS
EFIAPI
StrnCpyS (
- OUT CHAR16 *Destination,
- IN UINTN DestMax,
- IN CONST CHAR16 *Source,
- IN UINTN Length
+ OUT CHAR16 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR16 *Source,
+ IN UINTN Length
);
/**
@@ -312,9 +390,9 @@ StrnCpyS (
RETURN_STATUS
EFIAPI
StrCatS (
- IN OUT CHAR16 *Destination,
- IN UINTN DestMax,
- IN CONST CHAR16 *Source
+ IN OUT CHAR16 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR16 *Source
);
/**
@@ -352,10 +430,10 @@ StrCatS (
RETURN_STATUS
EFIAPI
StrnCatS (
- IN OUT CHAR16 *Destination,
- IN UINTN DestMax,
- IN CONST CHAR16 *Source,
- IN UINTN Length
+ IN OUT CHAR16 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR16 *Source,
+ IN UINTN Length
);
/**
@@ -404,9 +482,9 @@ StrnCatS (
RETURN_STATUS
EFIAPI
StrDecimalToUintnS (
- IN CONST CHAR16 *String,
- OUT CHAR16 **EndPointer, OPTIONAL
- OUT UINTN *Data
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer OPTIONAL,
+ OUT UINTN *Data
);
/**
@@ -455,9 +533,9 @@ StrDecimalToUintnS (
RETURN_STATUS
EFIAPI
StrDecimalToUint64S (
- IN CONST CHAR16 *String,
- OUT CHAR16 **EndPointer, OPTIONAL
- OUT UINT64 *Data
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer OPTIONAL,
+ OUT UINT64 *Data
);
/**
@@ -511,9 +589,9 @@ StrDecimalToUint64S (
RETURN_STATUS
EFIAPI
StrHexToUintnS (
- IN CONST CHAR16 *String,
- OUT CHAR16 **EndPointer, OPTIONAL
- OUT UINTN *Data
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer OPTIONAL,
+ OUT UINTN *Data
);
/**
@@ -567,9 +645,9 @@ StrHexToUintnS (
RETURN_STATUS
EFIAPI
StrHexToUint64S (
- IN CONST CHAR16 *String,
- OUT CHAR16 **EndPointer, OPTIONAL
- OUT UINT64 *Data
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer OPTIONAL,
+ OUT UINT64 *Data
);
/**
@@ -589,8 +667,8 @@ StrHexToUint64S (
UINTN
EFIAPI
AsciiStrnLenS (
- IN CONST CHAR8 *String,
- IN UINTN MaxSize
+ IN CONST CHAR8 *String,
+ IN UINTN MaxSize
);
/**
@@ -615,8 +693,8 @@ AsciiStrnLenS (
UINTN
EFIAPI
AsciiStrnSizeS (
- IN CONST CHAR8 *String,
- IN UINTN MaxSize
+ IN CONST CHAR8 *String,
+ IN UINTN MaxSize
);
/**
@@ -801,9 +879,9 @@ AsciiStrnCatS (
RETURN_STATUS
EFIAPI
AsciiStrDecimalToUintnS (
- IN CONST CHAR8 *String,
- OUT CHAR8 **EndPointer, OPTIONAL
- OUT UINTN *Data
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer OPTIONAL,
+ OUT UINTN *Data
);
/**
@@ -850,9 +928,9 @@ AsciiStrDecimalToUintnS (
RETURN_STATUS
EFIAPI
AsciiStrDecimalToUint64S (
- IN CONST CHAR8 *String,
- OUT CHAR8 **EndPointer, OPTIONAL
- OUT UINT64 *Data
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer OPTIONAL,
+ OUT UINT64 *Data
);
/**
@@ -903,9 +981,9 @@ AsciiStrDecimalToUint64S (
RETURN_STATUS
EFIAPI
AsciiStrHexToUintnS (
- IN CONST CHAR8 *String,
- OUT CHAR8 **EndPointer, OPTIONAL
- OUT UINTN *Data
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer OPTIONAL,
+ OUT UINTN *Data
);
/**
@@ -956,12 +1034,11 @@ AsciiStrHexToUintnS (
RETURN_STATUS
EFIAPI
AsciiStrHexToUint64S (
- IN CONST CHAR8 *String,
- OUT CHAR8 **EndPointer, OPTIONAL
- OUT UINT64 *Data
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer OPTIONAL,
+ OUT UINT64 *Data
);
-
/**
Returns the length of a Null-terminated Unicode string.
@@ -982,10 +1059,9 @@ AsciiStrHexToUint64S (
UINTN
EFIAPI
StrLen (
- IN CONST CHAR16 *String
+ IN CONST CHAR16 *String
);
-
/**
Returns the size of a Null-terminated Unicode string in bytes, including the
Null terminator.
@@ -1007,10 +1083,9 @@ StrLen (
UINTN
EFIAPI
StrSize (
- IN CONST CHAR16 *String
+ IN CONST CHAR16 *String
);
-
/**
Compares two Null-terminated Unicode strings, and returns the difference
between the first mismatched Unicode characters.
@@ -1042,11 +1117,10 @@ StrSize (
INTN
EFIAPI
StrCmp (
- IN CONST CHAR16 *FirstString,
- IN CONST CHAR16 *SecondString
+ IN CONST CHAR16 *FirstString,
+ IN CONST CHAR16 *SecondString
);
-
/**
Compares up to a specified length the contents of two Null-terminated Unicode strings,
and returns the difference between the first mismatched Unicode characters.
@@ -1082,12 +1156,11 @@ StrCmp (
INTN
EFIAPI
StrnCmp (
- IN CONST CHAR16 *FirstString,
- IN CONST CHAR16 *SecondString,
- IN UINTN Length
+ IN CONST CHAR16 *FirstString,
+ IN CONST CHAR16 *SecondString,
+ IN UINTN Length
);
-
/**
Returns the first occurrence of a Null-terminated Unicode sub-string
in a Null-terminated Unicode string.
@@ -1116,8 +1189,8 @@ StrnCmp (
CHAR16 *
EFIAPI
StrStr (
- IN CONST CHAR16 *String,
- IN CONST CHAR16 *SearchString
+ IN CONST CHAR16 *String,
+ IN CONST CHAR16 *SearchString
);
/**
@@ -1157,7 +1230,7 @@ StrStr (
UINTN
EFIAPI
StrDecimalToUintn (
- IN CONST CHAR16 *String
+ IN CONST CHAR16 *String
);
/**
@@ -1197,10 +1270,9 @@ StrDecimalToUintn (
UINT64
EFIAPI
StrDecimalToUint64 (
- IN CONST CHAR16 *String
+ IN CONST CHAR16 *String
);
-
/**
Convert a Null-terminated Unicode hexadecimal string to a value of type UINTN.
@@ -1239,10 +1311,9 @@ StrDecimalToUint64 (
UINTN
EFIAPI
StrHexToUintn (
- IN CONST CHAR16 *String
+ IN CONST CHAR16 *String
);
-
/**
Convert a Null-terminated Unicode hexadecimal string to a value of type UINT64.
@@ -1281,7 +1352,7 @@ StrHexToUintn (
UINT64
EFIAPI
StrHexToUint64 (
- IN CONST CHAR16 *String
+ IN CONST CHAR16 *String
);
/**
@@ -1337,10 +1408,10 @@ StrHexToUint64 (
RETURN_STATUS
EFIAPI
StrToIpv6Address (
- IN CONST CHAR16 *String,
- OUT CHAR16 **EndPointer, OPTIONAL
- OUT IPv6_ADDRESS *Address,
- OUT UINT8 *PrefixLength OPTIONAL
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer OPTIONAL,
+ OUT IPv6_ADDRESS *Address,
+ OUT UINT8 *PrefixLength OPTIONAL
);
/**
@@ -1387,10 +1458,10 @@ StrToIpv6Address (
RETURN_STATUS
EFIAPI
StrToIpv4Address (
- IN CONST CHAR16 *String,
- OUT CHAR16 **EndPointer, OPTIONAL
- OUT IPv4_ADDRESS *Address,
- OUT UINT8 *PrefixLength OPTIONAL
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer OPTIONAL,
+ OUT IPv4_ADDRESS *Address,
+ OUT UINT8 *PrefixLength OPTIONAL
);
#define GUID_STRING_LENGTH 36
@@ -1440,8 +1511,8 @@ StrToIpv4Address (
RETURN_STATUS
EFIAPI
StrToGuid (
- IN CONST CHAR16 *String,
- OUT GUID *Guid
+ IN CONST CHAR16 *String,
+ OUT GUID *Guid
);
/**
@@ -1480,13 +1551,12 @@ StrToGuid (
RETURN_STATUS
EFIAPI
StrHexToBytes (
- IN CONST CHAR16 *String,
- IN UINTN Length,
- OUT UINT8 *Buffer,
- IN UINTN MaxBufferSize
+ IN CONST CHAR16 *String,
+ IN UINTN Length,
+ OUT UINT8 *Buffer,
+ IN UINTN MaxBufferSize
);
-
/**
Convert a Null-terminated Unicode string to a Null-terminated
ASCII string.
@@ -1530,9 +1600,9 @@ StrHexToBytes (
RETURN_STATUS
EFIAPI
UnicodeStrToAsciiStrS (
- IN CONST CHAR16 *Source,
- OUT CHAR8 *Destination,
- IN UINTN DestMax
+ IN CONST CHAR16 *Source,
+ OUT CHAR8 *Destination,
+ IN UINTN DestMax
);
/**
@@ -1581,14 +1651,13 @@ UnicodeStrToAsciiStrS (
RETURN_STATUS
EFIAPI
UnicodeStrnToAsciiStrS (
- IN CONST CHAR16 *Source,
- IN UINTN Length,
- OUT CHAR8 *Destination,
- IN UINTN DestMax,
- OUT UINTN *DestinationLength
+ IN CONST CHAR16 *Source,
+ IN UINTN Length,
+ OUT CHAR8 *Destination,
+ IN UINTN DestMax,
+ OUT UINTN *DestinationLength
);
-
/**
Returns the length of a Null-terminated ASCII string.
@@ -1609,10 +1678,9 @@ UnicodeStrnToAsciiStrS (
UINTN
EFIAPI
AsciiStrLen (
- IN CONST CHAR8 *String
+ IN CONST CHAR8 *String
);
-
/**
Returns the size of a Null-terminated ASCII string in bytes, including the
Null terminator.
@@ -1633,10 +1701,9 @@ AsciiStrLen (
UINTN
EFIAPI
AsciiStrSize (
- IN CONST CHAR8 *String
+ IN CONST CHAR8 *String
);
-
/**
Compares two Null-terminated ASCII strings, and returns the difference
between the first mismatched ASCII characters.
@@ -1666,11 +1733,10 @@ AsciiStrSize (
INTN
EFIAPI
AsciiStrCmp (
- IN CONST CHAR8 *FirstString,
- IN CONST CHAR8 *SecondString
+ IN CONST CHAR8 *FirstString,
+ IN CONST CHAR8 *SecondString
);
-
/**
Performs a case insensitive comparison of two Null-terminated ASCII strings,
and returns the difference between the first mismatched ASCII characters.
@@ -1703,11 +1769,10 @@ AsciiStrCmp (
INTN
EFIAPI
AsciiStriCmp (
- IN CONST CHAR8 *FirstString,
- IN CONST CHAR8 *SecondString
+ IN CONST CHAR8 *FirstString,
+ IN CONST CHAR8 *SecondString
);
-
/**
Compares two Null-terminated ASCII strings with maximum lengths, and returns
the difference between the first mismatched ASCII characters.
@@ -1741,12 +1806,11 @@ AsciiStriCmp (
INTN
EFIAPI
AsciiStrnCmp (
- IN CONST CHAR8 *FirstString,
- IN CONST CHAR8 *SecondString,
- IN UINTN Length
+ IN CONST CHAR8 *FirstString,
+ IN CONST CHAR8 *SecondString,
+ IN UINTN Length
);
-
/**
Returns the first occurrence of a Null-terminated ASCII sub-string
in a Null-terminated ASCII string.
@@ -1774,11 +1838,10 @@ AsciiStrnCmp (
CHAR8 *
EFIAPI
AsciiStrStr (
- IN CONST CHAR8 *String,
- IN CONST CHAR8 *SearchString
+ IN CONST CHAR8 *String,
+ IN CONST CHAR8 *SearchString
);
-
/**
Convert a Null-terminated ASCII decimal string to a value of type
UINTN.
@@ -1812,10 +1875,9 @@ AsciiStrStr (
UINTN
EFIAPI
AsciiStrDecimalToUintn (
- IN CONST CHAR8 *String
+ IN CONST CHAR8 *String
);
-
/**
Convert a Null-terminated ASCII decimal string to a value of type
UINT64.
@@ -1849,10 +1911,9 @@ AsciiStrDecimalToUintn (
UINT64
EFIAPI
AsciiStrDecimalToUint64 (
- IN CONST CHAR8 *String
+ IN CONST CHAR8 *String
);
-
/**
Convert a Null-terminated ASCII hexadecimal string to a value of type UINTN.
@@ -1890,10 +1951,9 @@ AsciiStrDecimalToUint64 (
UINTN
EFIAPI
AsciiStrHexToUintn (
- IN CONST CHAR8 *String
+ IN CONST CHAR8 *String
);
-
/**
Convert a Null-terminated ASCII hexadecimal string to a value of type UINT64.
@@ -1931,7 +1991,7 @@ AsciiStrHexToUintn (
UINT64
EFIAPI
AsciiStrHexToUint64 (
- IN CONST CHAR8 *String
+ IN CONST CHAR8 *String
);
/**
@@ -1985,10 +2045,10 @@ AsciiStrHexToUint64 (
RETURN_STATUS
EFIAPI
AsciiStrToIpv6Address (
- IN CONST CHAR8 *String,
- OUT CHAR8 **EndPointer, OPTIONAL
- OUT IPv6_ADDRESS *Address,
- OUT UINT8 *PrefixLength OPTIONAL
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer OPTIONAL,
+ OUT IPv6_ADDRESS *Address,
+ OUT UINT8 *PrefixLength OPTIONAL
);
/**
@@ -2033,10 +2093,10 @@ AsciiStrToIpv6Address (
RETURN_STATUS
EFIAPI
AsciiStrToIpv4Address (
- IN CONST CHAR8 *String,
- OUT CHAR8 **EndPointer, OPTIONAL
- OUT IPv4_ADDRESS *Address,
- OUT UINT8 *PrefixLength OPTIONAL
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer OPTIONAL,
+ OUT IPv4_ADDRESS *Address,
+ OUT UINT8 *PrefixLength OPTIONAL
);
/**
@@ -2082,8 +2142,8 @@ AsciiStrToIpv4Address (
RETURN_STATUS
EFIAPI
AsciiStrToGuid (
- IN CONST CHAR8 *String,
- OUT GUID *Guid
+ IN CONST CHAR8 *String,
+ OUT GUID *Guid
);
/**
@@ -2120,13 +2180,12 @@ AsciiStrToGuid (
RETURN_STATUS
EFIAPI
AsciiStrHexToBytes (
- IN CONST CHAR8 *String,
- IN UINTN Length,
- OUT UINT8 *Buffer,
- IN UINTN MaxBufferSize
+ IN CONST CHAR8 *String,
+ IN UINTN Length,
+ OUT UINT8 *Buffer,
+ IN UINTN MaxBufferSize
);
-
/**
Convert one Null-terminated ASCII string to a Null-terminated
Unicode string.
@@ -2166,9 +2225,9 @@ AsciiStrHexToBytes (
RETURN_STATUS
EFIAPI
AsciiStrToUnicodeStrS (
- IN CONST CHAR8 *Source,
- OUT CHAR16 *Destination,
- IN UINTN DestMax
+ IN CONST CHAR8 *Source,
+ OUT CHAR16 *Destination,
+ IN UINTN DestMax
);
/**
@@ -2216,11 +2275,11 @@ AsciiStrToUnicodeStrS (
RETURN_STATUS
EFIAPI
AsciiStrnToUnicodeStrS (
- IN CONST CHAR8 *Source,
- IN UINTN Length,
- OUT CHAR16 *Destination,
- IN UINTN DestMax,
- OUT UINTN *DestinationLength
+ IN CONST CHAR8 *Source,
+ IN UINTN Length,
+ OUT CHAR16 *Destination,
+ IN UINTN DestMax,
+ OUT UINTN *DestinationLength
);
/**
@@ -2241,7 +2300,7 @@ AsciiStrnToUnicodeStrS (
CHAR16
EFIAPI
CharToUpper (
- IN CHAR16 Char
+ IN CHAR16 Char
);
/**
@@ -2260,7 +2319,7 @@ CharToUpper (
CHAR8
EFIAPI
AsciiCharToUpper (
- IN CHAR8 Chr
+ IN CHAR8 Chr
);
/**
@@ -2286,7 +2345,7 @@ RETURN_STATUS
EFIAPI
Base64Encode (
IN CONST UINT8 *Source,
- IN UINTN SourceLength,
+ IN UINTN SourceLength,
OUT CHAR8 *Destination OPTIONAL,
IN OUT UINTN *DestinationSize
);
@@ -2376,10 +2435,10 @@ Base64Encode (
RETURN_STATUS
EFIAPI
Base64Decode (
- IN CONST CHAR8 *Source OPTIONAL,
- IN UINTN SourceSize,
- OUT UINT8 *Destination OPTIONAL,
- IN OUT UINTN *DestinationSize
+ IN CONST CHAR8 *Source OPTIONAL,
+ IN UINTN SourceSize,
+ OUT UINT8 *Destination OPTIONAL,
+ IN OUT UINTN *DestinationSize
);
/**
@@ -2398,10 +2457,9 @@ Base64Decode (
UINT8
EFIAPI
DecimalToBcd8 (
- IN UINT8 Value
+ IN UINT8 Value
);
-
/**
Converts an 8-bit BCD value to an 8-bit value.
@@ -2419,7 +2477,7 @@ DecimalToBcd8 (
UINT8
EFIAPI
BcdToDecimal8 (
- IN UINT8 Value
+ IN UINT8 Value
);
//
@@ -2436,8 +2494,8 @@ BcdToDecimal8 (
**/
BOOLEAN
EFIAPI
-PathRemoveLastItem(
- IN OUT CHAR16 *Path
+PathRemoveLastItem (
+ IN OUT CHAR16 *Path
);
/**
@@ -2453,10 +2511,10 @@ PathRemoveLastItem(
@return Returns Path, otherwise returns NULL to indicate that an error has occurred.
**/
-CHAR16*
+CHAR16 *
EFIAPI
-PathCleanUpDirectories(
- IN CHAR16 *Path
+PathCleanUpDirectories (
+ IN CHAR16 *Path
);
//
@@ -2528,11 +2586,10 @@ PathCleanUpDirectories(
BOOLEAN
EFIAPI
IsNodeInList (
- IN CONST LIST_ENTRY *FirstEntry,
- IN CONST LIST_ENTRY *SecondEntry
+ IN CONST LIST_ENTRY *FirstEntry,
+ IN CONST LIST_ENTRY *SecondEntry
);
-
/**
Initializes the head node of a doubly linked list, and returns the pointer to
the head node of the doubly linked list.
@@ -2552,10 +2609,9 @@ IsNodeInList (
LIST_ENTRY *
EFIAPI
InitializeListHead (
- IN OUT LIST_ENTRY *ListHead
+ IN OUT LIST_ENTRY *ListHead
);
-
/**
Adds a node to the beginning of a doubly linked list, and returns the pointer
to the head node of the doubly linked list.
@@ -2581,11 +2637,10 @@ InitializeListHead (
LIST_ENTRY *
EFIAPI
InsertHeadList (
- IN OUT LIST_ENTRY *ListHead,
- IN OUT LIST_ENTRY *Entry
+ IN OUT LIST_ENTRY *ListHead,
+ IN OUT LIST_ENTRY *Entry
);
-
/**
Adds a node to the end of a doubly linked list, and returns the pointer to
the head node of the doubly linked list.
@@ -2611,11 +2666,10 @@ InsertHeadList (
LIST_ENTRY *
EFIAPI
InsertTailList (
- IN OUT LIST_ENTRY *ListHead,
- IN OUT LIST_ENTRY *Entry
+ IN OUT LIST_ENTRY *ListHead,
+ IN OUT LIST_ENTRY *Entry
);
-
/**
Retrieves the first node of a doubly linked list.
@@ -2639,10 +2693,9 @@ InsertTailList (
LIST_ENTRY *
EFIAPI
GetFirstNode (
- IN CONST LIST_ENTRY *List
+ IN CONST LIST_ENTRY *List
);
-
/**
Retrieves the next node of a doubly linked list.
@@ -2667,11 +2720,10 @@ GetFirstNode (
LIST_ENTRY *
EFIAPI
GetNextNode (
- IN CONST LIST_ENTRY *List,
- IN CONST LIST_ENTRY *Node
+ IN CONST LIST_ENTRY *List,
+ IN CONST LIST_ENTRY *Node
);
-
/**
Retrieves the previous node of a doubly linked list.
@@ -2696,11 +2748,10 @@ GetNextNode (
LIST_ENTRY *
EFIAPI
GetPreviousNode (
- IN CONST LIST_ENTRY *List,
- IN CONST LIST_ENTRY *Node
+ IN CONST LIST_ENTRY *List,
+ IN CONST LIST_ENTRY *Node
);
-
/**
Checks to see if a doubly linked list is empty or not.
@@ -2723,10 +2774,9 @@ GetPreviousNode (
BOOLEAN
EFIAPI
IsListEmpty (
- IN CONST LIST_ENTRY *ListHead
+ IN CONST LIST_ENTRY *ListHead
);
-
/**
Determines if a node in a doubly linked list is the head node of a the same
doubly linked list. This function is typically used to terminate a loop that
@@ -2756,11 +2806,10 @@ IsListEmpty (
BOOLEAN
EFIAPI
IsNull (
- IN CONST LIST_ENTRY *List,
- IN CONST LIST_ENTRY *Node
+ IN CONST LIST_ENTRY *List,
+ IN CONST LIST_ENTRY *Node
);
-
/**
Determines if a node the last node in a doubly linked list.
@@ -2787,11 +2836,10 @@ IsNull (
BOOLEAN
EFIAPI
IsNodeAtEnd (
- IN CONST LIST_ENTRY *List,
- IN CONST LIST_ENTRY *Node
+ IN CONST LIST_ENTRY *List,
+ IN CONST LIST_ENTRY *Node
);
-
/**
Swaps the location of two nodes in a doubly linked list, and returns the
first node after the swap.
@@ -2821,11 +2869,10 @@ IsNodeAtEnd (
LIST_ENTRY *
EFIAPI
SwapListEntries (
- IN OUT LIST_ENTRY *FirstEntry,
- IN OUT LIST_ENTRY *SecondEntry
+ IN OUT LIST_ENTRY *FirstEntry,
+ IN OUT LIST_ENTRY *SecondEntry
);
-
/**
Removes a node from a doubly linked list, and returns the node that follows
the removed node.
@@ -2850,12 +2897,13 @@ SwapListEntries (
LIST_ENTRY *
EFIAPI
RemoveEntryList (
- IN CONST LIST_ENTRY *Entry
+ IN CONST LIST_ENTRY *Entry
);
//
// Math Services
//
+
/**
Prototype for comparison function for any two element types.
@@ -2899,11 +2947,11 @@ INTN
VOID
EFIAPI
QuickSort (
- IN OUT VOID *BufferToSort,
- IN CONST UINTN Count,
- IN CONST UINTN ElementSize,
- IN BASE_SORT_COMPARE CompareFunction,
- OUT VOID *BufferOneElement
+ IN OUT VOID *BufferToSort,
+ IN CONST UINTN Count,
+ IN CONST UINTN ElementSize,
+ IN BASE_SORT_COMPARE CompareFunction,
+ OUT VOID *BufferOneElement
);
/**
@@ -2924,11 +2972,10 @@ QuickSort (
UINT64
EFIAPI
LShiftU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
);
-
/**
Shifts a 64-bit integer right between 0 and 63 bits. This high bits are
filled with zeros. The shifted value is returned.
@@ -2947,11 +2994,10 @@ LShiftU64 (
UINT64
EFIAPI
RShiftU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
);
-
/**
Shifts a 64-bit integer right between 0 and 63 bits. The high bits are filled
with original integer's bit 63. The shifted value is returned.
@@ -2970,11 +3016,10 @@ RShiftU64 (
UINT64
EFIAPI
ARShiftU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
);
-
/**
Rotates a 32-bit integer left between 0 and 31 bits, filling the low bits
with the high bits that were rotated.
@@ -2994,11 +3039,10 @@ ARShiftU64 (
UINT32
EFIAPI
LRotU32 (
- IN UINT32 Operand,
- IN UINTN Count
+ IN UINT32 Operand,
+ IN UINTN Count
);
-
/**
Rotates a 32-bit integer right between 0 and 31 bits, filling the high bits
with the low bits that were rotated.
@@ -3018,11 +3062,10 @@ LRotU32 (
UINT32
EFIAPI
RRotU32 (
- IN UINT32 Operand,
- IN UINTN Count
+ IN UINT32 Operand,
+ IN UINTN Count
);
-
/**
Rotates a 64-bit integer left between 0 and 63 bits, filling the low bits
with the high bits that were rotated.
@@ -3042,11 +3085,10 @@ RRotU32 (
UINT64
EFIAPI
LRotU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
);
-
/**
Rotates a 64-bit integer right between 0 and 63 bits, filling the high bits
with the high low bits that were rotated.
@@ -3066,11 +3108,10 @@ LRotU64 (
UINT64
EFIAPI
RRotU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
);
-
/**
Returns the bit position of the lowest bit set in a 32-bit value.
@@ -3087,10 +3128,9 @@ RRotU64 (
INTN
EFIAPI
LowBitSet32 (
- IN UINT32 Operand
+ IN UINT32 Operand
);
-
/**
Returns the bit position of the lowest bit set in a 64-bit value.
@@ -3108,10 +3148,9 @@ LowBitSet32 (
INTN
EFIAPI
LowBitSet64 (
- IN UINT64 Operand
+ IN UINT64 Operand
);
-
/**
Returns the bit position of the highest bit set in a 32-bit value. Equivalent
to log2(x).
@@ -3129,10 +3168,9 @@ LowBitSet64 (
INTN
EFIAPI
HighBitSet32 (
- IN UINT32 Operand
+ IN UINT32 Operand
);
-
/**
Returns the bit position of the highest bit set in a 64-bit value. Equivalent
to log2(x).
@@ -3150,10 +3188,9 @@ HighBitSet32 (
INTN
EFIAPI
HighBitSet64 (
- IN UINT64 Operand
+ IN UINT64 Operand
);
-
/**
Returns the value of the highest bit set in a 32-bit value. Equivalent to
1 << log2(x).
@@ -3170,10 +3207,9 @@ HighBitSet64 (
UINT32
EFIAPI
GetPowerOfTwo32 (
- IN UINT32 Operand
+ IN UINT32 Operand
);
-
/**
Returns the value of the highest bit set in a 64-bit value. Equivalent to
1 << log2(x).
@@ -3190,10 +3226,9 @@ GetPowerOfTwo32 (
UINT64
EFIAPI
GetPowerOfTwo64 (
- IN UINT64 Operand
+ IN UINT64 Operand
);
-
/**
Switches the endianness of a 16-bit integer.
@@ -3209,10 +3244,9 @@ GetPowerOfTwo64 (
UINT16
EFIAPI
SwapBytes16 (
- IN UINT16 Value
+ IN UINT16 Value
);
-
/**
Switches the endianness of a 32-bit integer.
@@ -3228,10 +3262,9 @@ SwapBytes16 (
UINT32
EFIAPI
SwapBytes32 (
- IN UINT32 Value
+ IN UINT32 Value
);
-
/**
Switches the endianness of a 64-bit integer.
@@ -3247,10 +3280,9 @@ SwapBytes32 (
UINT64
EFIAPI
SwapBytes64 (
- IN UINT64 Value
+ IN UINT64 Value
);
-
/**
Multiples a 64-bit unsigned integer by a 32-bit unsigned integer and
generates a 64-bit unsigned result.
@@ -3268,11 +3300,10 @@ SwapBytes64 (
UINT64
EFIAPI
MultU64x32 (
- IN UINT64 Multiplicand,
- IN UINT32 Multiplier
+ IN UINT64 Multiplicand,
+ IN UINT32 Multiplier
);
-
/**
Multiples a 64-bit unsigned integer by a 64-bit unsigned integer and
generates a 64-bit unsigned result.
@@ -3290,11 +3321,10 @@ MultU64x32 (
UINT64
EFIAPI
MultU64x64 (
- IN UINT64 Multiplicand,
- IN UINT64 Multiplier
+ IN UINT64 Multiplicand,
+ IN UINT64 Multiplier
);
-
/**
Multiples a 64-bit signed integer by a 64-bit signed integer and generates a
64-bit signed result.
@@ -3312,11 +3342,10 @@ MultU64x64 (
INT64
EFIAPI
MultS64x64 (
- IN INT64 Multiplicand,
- IN INT64 Multiplier
+ IN INT64 Multiplicand,
+ IN INT64 Multiplier
);
-
/**
Divides a 64-bit unsigned integer by a 32-bit unsigned integer and generates
a 64-bit unsigned result.
@@ -3336,11 +3365,10 @@ MultS64x64 (
UINT64
EFIAPI
DivU64x32 (
- IN UINT64 Dividend,
- IN UINT32 Divisor
+ IN UINT64 Dividend,
+ IN UINT32 Divisor
);
-
/**
Divides a 64-bit unsigned integer by a 32-bit unsigned integer and generates
a 32-bit unsigned remainder.
@@ -3360,11 +3388,10 @@ DivU64x32 (
UINT32
EFIAPI
ModU64x32 (
- IN UINT64 Dividend,
- IN UINT32 Divisor
+ IN UINT64 Dividend,
+ IN UINT32 Divisor
);
-
/**
Divides a 64-bit unsigned integer by a 32-bit unsigned integer and generates
a 64-bit unsigned result and an optional 32-bit unsigned remainder.
@@ -3387,12 +3414,11 @@ ModU64x32 (
UINT64
EFIAPI
DivU64x32Remainder (
- IN UINT64 Dividend,
- IN UINT32 Divisor,
- OUT UINT32 *Remainder OPTIONAL
+ IN UINT64 Dividend,
+ IN UINT32 Divisor,
+ OUT UINT32 *Remainder OPTIONAL
);
-
/**
Divides a 64-bit unsigned integer by a 64-bit unsigned integer and generates
a 64-bit unsigned result and an optional 64-bit unsigned remainder.
@@ -3415,12 +3441,11 @@ DivU64x32Remainder (
UINT64
EFIAPI
DivU64x64Remainder (
- IN UINT64 Dividend,
- IN UINT64 Divisor,
- OUT UINT64 *Remainder OPTIONAL
+ IN UINT64 Dividend,
+ IN UINT64 Divisor,
+ OUT UINT64 *Remainder OPTIONAL
);
-
/**
Divides a 64-bit signed integer by a 64-bit signed integer and generates a
64-bit signed result and a optional 64-bit signed remainder.
@@ -3447,12 +3472,11 @@ DivU64x64Remainder (
INT64
EFIAPI
DivS64x64Remainder (
- IN INT64 Dividend,
- IN INT64 Divisor,
- OUT INT64 *Remainder OPTIONAL
+ IN INT64 Dividend,
+ IN INT64 Divisor,
+ OUT INT64 *Remainder OPTIONAL
);
-
/**
Reads a 16-bit value from memory that may be unaligned.
@@ -3469,10 +3493,9 @@ DivS64x64Remainder (
UINT16
EFIAPI
ReadUnaligned16 (
- IN CONST UINT16 *Buffer
+ IN CONST UINT16 *Buffer
);
-
/**
Writes a 16-bit value to memory that may be unaligned.
@@ -3491,11 +3514,10 @@ ReadUnaligned16 (
UINT16
EFIAPI
WriteUnaligned16 (
- OUT UINT16 *Buffer,
- IN UINT16 Value
+ OUT UINT16 *Buffer,
+ IN UINT16 Value
);
-
/**
Reads a 24-bit value from memory that may be unaligned.
@@ -3512,10 +3534,9 @@ WriteUnaligned16 (
UINT32
EFIAPI
ReadUnaligned24 (
- IN CONST UINT32 *Buffer
+ IN CONST UINT32 *Buffer
);
-
/**
Writes a 24-bit value to memory that may be unaligned.
@@ -3534,11 +3555,10 @@ ReadUnaligned24 (
UINT32
EFIAPI
WriteUnaligned24 (
- OUT UINT32 *Buffer,
- IN UINT32 Value
+ OUT UINT32 *Buffer,
+ IN UINT32 Value
);
-
/**
Reads a 32-bit value from memory that may be unaligned.
@@ -3555,10 +3575,9 @@ WriteUnaligned24 (
UINT32
EFIAPI
ReadUnaligned32 (
- IN CONST UINT32 *Buffer
+ IN CONST UINT32 *Buffer
);
-
/**
Writes a 32-bit value to memory that may be unaligned.
@@ -3577,11 +3596,10 @@ ReadUnaligned32 (
UINT32
EFIAPI
WriteUnaligned32 (
- OUT UINT32 *Buffer,
- IN UINT32 Value
+ OUT UINT32 *Buffer,
+ IN UINT32 Value
);
-
/**
Reads a 64-bit value from memory that may be unaligned.
@@ -3598,10 +3616,9 @@ WriteUnaligned32 (
UINT64
EFIAPI
ReadUnaligned64 (
- IN CONST UINT64 *Buffer
+ IN CONST UINT64 *Buffer
);
-
/**
Writes a 64-bit value to memory that may be unaligned.
@@ -3620,11 +3637,10 @@ ReadUnaligned64 (
UINT64
EFIAPI
WriteUnaligned64 (
- OUT UINT64 *Buffer,
- IN UINT64 Value
+ OUT UINT64 *Buffer,
+ IN UINT64 Value
);
-
//
// Bit Field Functions
//
@@ -3651,12 +3667,11 @@ WriteUnaligned64 (
UINT8
EFIAPI
BitFieldRead8 (
- IN UINT8 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT8 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
-
/**
Writes a bit field to an 8-bit value, and returns the result.
@@ -3683,13 +3698,12 @@ BitFieldRead8 (
UINT8
EFIAPI
BitFieldWrite8 (
- IN UINT8 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 Value
+ IN UINT8 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
);
-
/**
Reads a bit field from an 8-bit value, performs a bitwise OR, and returns the
result.
@@ -3717,13 +3731,12 @@ BitFieldWrite8 (
UINT8
EFIAPI
BitFieldOr8 (
- IN UINT8 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 OrData
+ IN UINT8 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
);
-
/**
Reads a bit field from an 8-bit value, performs a bitwise AND, and returns
the result.
@@ -3751,13 +3764,12 @@ BitFieldOr8 (
UINT8
EFIAPI
BitFieldAnd8 (
- IN UINT8 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData
+ IN UINT8 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
);
-
/**
Reads a bit field from an 8-bit value, performs a bitwise AND followed by a
bitwise OR, and returns the result.
@@ -3788,14 +3800,13 @@ BitFieldAnd8 (
UINT8
EFIAPI
BitFieldAndThenOr8 (
- IN UINT8 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINT8 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
);
-
/**
Returns a bit field from a 16-bit value.
@@ -3818,12 +3829,11 @@ BitFieldAndThenOr8 (
UINT16
EFIAPI
BitFieldRead16 (
- IN UINT16 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT16 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
-
/**
Writes a bit field to a 16-bit value, and returns the result.
@@ -3850,13 +3860,12 @@ BitFieldRead16 (
UINT16
EFIAPI
BitFieldWrite16 (
- IN UINT16 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 Value
+ IN UINT16 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
);
-
/**
Reads a bit field from a 16-bit value, performs a bitwise OR, and returns the
result.
@@ -3884,13 +3893,12 @@ BitFieldWrite16 (
UINT16
EFIAPI
BitFieldOr16 (
- IN UINT16 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 OrData
+ IN UINT16 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
);
-
/**
Reads a bit field from a 16-bit value, performs a bitwise AND, and returns
the result.
@@ -3918,13 +3926,12 @@ BitFieldOr16 (
UINT16
EFIAPI
BitFieldAnd16 (
- IN UINT16 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData
+ IN UINT16 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
);
-
/**
Reads a bit field from a 16-bit value, performs a bitwise AND followed by a
bitwise OR, and returns the result.
@@ -3955,14 +3962,13 @@ BitFieldAnd16 (
UINT16
EFIAPI
BitFieldAndThenOr16 (
- IN UINT16 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINT16 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
);
-
/**
Returns a bit field from a 32-bit value.
@@ -3985,12 +3991,11 @@ BitFieldAndThenOr16 (
UINT32
EFIAPI
BitFieldRead32 (
- IN UINT32 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
-
/**
Writes a bit field to a 32-bit value, and returns the result.
@@ -4017,13 +4022,12 @@ BitFieldRead32 (
UINT32
EFIAPI
BitFieldWrite32 (
- IN UINT32 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
);
-
/**
Reads a bit field from a 32-bit value, performs a bitwise OR, and returns the
result.
@@ -4051,13 +4055,12 @@ BitFieldWrite32 (
UINT32
EFIAPI
BitFieldOr32 (
- IN UINT32 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
);
-
/**
Reads a bit field from a 32-bit value, performs a bitwise AND, and returns
the result.
@@ -4085,13 +4088,12 @@ BitFieldOr32 (
UINT32
EFIAPI
BitFieldAnd32 (
- IN UINT32 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
);
-
/**
Reads a bit field from a 32-bit value, performs a bitwise AND followed by a
bitwise OR, and returns the result.
@@ -4122,14 +4124,13 @@ BitFieldAnd32 (
UINT32
EFIAPI
BitFieldAndThenOr32 (
- IN UINT32 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
);
-
/**
Returns a bit field from a 64-bit value.
@@ -4152,12 +4153,11 @@ BitFieldAndThenOr32 (
UINT64
EFIAPI
BitFieldRead64 (
- IN UINT64 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
-
/**
Writes a bit field to a 64-bit value, and returns the result.
@@ -4184,13 +4184,12 @@ BitFieldRead64 (
UINT64
EFIAPI
BitFieldWrite64 (
- IN UINT64 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 Value
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 Value
);
-
/**
Reads a bit field from a 64-bit value, performs a bitwise OR, and returns the
result.
@@ -4218,13 +4217,12 @@ BitFieldWrite64 (
UINT64
EFIAPI
BitFieldOr64 (
- IN UINT64 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 OrData
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 OrData
);
-
/**
Reads a bit field from a 64-bit value, performs a bitwise AND, and returns
the result.
@@ -4252,13 +4250,12 @@ BitFieldOr64 (
UINT64
EFIAPI
BitFieldAnd64 (
- IN UINT64 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 AndData
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData
);
-
/**
Reads a bit field from a 64-bit value, performs a bitwise AND followed by a
bitwise OR, and returns the result.
@@ -4289,11 +4286,11 @@ BitFieldAnd64 (
UINT64
EFIAPI
BitFieldAndThenOr64 (
- IN UINT64 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 AndData,
- IN UINT64 OrData
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData,
+ IN UINT64 OrData
);
/**
@@ -4319,9 +4316,9 @@ BitFieldAndThenOr64 (
UINT8
EFIAPI
BitFieldCountOnes32 (
- IN UINT32 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
/**
@@ -4347,9 +4344,9 @@ BitFieldCountOnes32 (
UINT8
EFIAPI
BitFieldCountOnes64 (
- IN UINT64 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
//
@@ -4377,11 +4374,10 @@ BitFieldCountOnes64 (
UINT8
EFIAPI
CalculateSum8 (
- IN CONST UINT8 *Buffer,
- IN UINTN Length
+ IN CONST UINT8 *Buffer,
+ IN UINTN Length
);
-
/**
Returns the two's complement checksum of all elements in a buffer
of 8-bit values.
@@ -4403,11 +4399,10 @@ CalculateSum8 (
UINT8
EFIAPI
CalculateCheckSum8 (
- IN CONST UINT8 *Buffer,
- IN UINTN Length
+ IN CONST UINT8 *Buffer,
+ IN UINTN Length
);
-
/**
Returns the sum of all elements in a buffer of 16-bit values. During
calculation, the carry bits are dropped.
@@ -4430,11 +4425,10 @@ CalculateCheckSum8 (
UINT16
EFIAPI
CalculateSum16 (
- IN CONST UINT16 *Buffer,
- IN UINTN Length
+ IN CONST UINT16 *Buffer,
+ IN UINTN Length
);
-
/**
Returns the two's complement checksum of all elements in a buffer of
16-bit values.
@@ -4458,11 +4452,10 @@ CalculateSum16 (
UINT16
EFIAPI
CalculateCheckSum16 (
- IN CONST UINT16 *Buffer,
- IN UINTN Length
+ IN CONST UINT16 *Buffer,
+ IN UINTN Length
);
-
/**
Returns the sum of all elements in a buffer of 32-bit values. During
calculation, the carry bits are dropped.
@@ -4485,11 +4478,10 @@ CalculateCheckSum16 (
UINT32
EFIAPI
CalculateSum32 (
- IN CONST UINT32 *Buffer,
- IN UINTN Length
+ IN CONST UINT32 *Buffer,
+ IN UINTN Length
);
-
/**
Returns the two's complement checksum of all elements in a buffer of
32-bit values.
@@ -4513,11 +4505,10 @@ CalculateSum32 (
UINT32
EFIAPI
CalculateCheckSum32 (
- IN CONST UINT32 *Buffer,
- IN UINTN Length
+ IN CONST UINT32 *Buffer,
+ IN UINTN Length
);
-
/**
Returns the sum of all elements in a buffer of 64-bit values. During
calculation, the carry bits are dropped.
@@ -4540,11 +4531,10 @@ CalculateCheckSum32 (
UINT64
EFIAPI
CalculateSum64 (
- IN CONST UINT64 *Buffer,
- IN UINTN Length
+ IN CONST UINT64 *Buffer,
+ IN UINTN Length
);
-
/**
Returns the two's complement checksum of all elements in a buffer of
64-bit values.
@@ -4568,8 +4558,8 @@ CalculateSum64 (
UINT64
EFIAPI
CalculateCheckSum64 (
- IN CONST UINT64 *Buffer,
- IN UINTN Length
+ IN CONST UINT64 *Buffer,
+ IN UINTN Length
);
/**
@@ -4587,9 +4577,43 @@ CalculateCheckSum64 (
**/
UINT32
EFIAPI
-CalculateCrc32(
- IN VOID *Buffer,
- IN UINTN Length
+CalculateCrc32 (
+ IN VOID *Buffer,
+ IN UINTN Length
+ );
+
+/**
+ Calculates the CRC16-ANSI checksum of the given buffer.
+
+ @param[in] Buffer Pointer to the buffer.
+ @param[in] Length Length of the buffer, in bytes.
+ @param[in] InitialValue Initial value of the CRC.
+
+ @return The CRC16-ANSI checksum.
+**/
+UINT16
+EFIAPI
+CalculateCrc16Ansi (
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN UINT16 InitialValue
+ );
+
+/**
+ Calculates the CRC32c checksum of the given buffer.
+
+ @param[in] Buffer Pointer to the buffer.
+ @param[in] Length Length of the buffer, in bytes.
+ @param[in] InitialValue Initial value of the CRC.
+
+ @return The CRC32c checksum.
+**/
+UINT32
+EFIAPI
+CalculateCrc32c (
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN UINT32 InitialValue
);
//
@@ -4601,16 +4625,14 @@ CalculateCrc32(
@param Context1 Context1 parameter passed into SwitchStack().
@param Context2 Context2 parameter passed into SwitchStack().
-
**/
typedef
VOID
(EFIAPI *SWITCH_STACK_ENTRY_POINT)(
- IN VOID *Context1, OPTIONAL
+ IN VOID *Context1 OPTIONAL,
IN VOID *Context2 OPTIONAL
);
-
/**
Used to serialize load and store operations.
@@ -4624,7 +4646,6 @@ MemoryFence (
VOID
);
-
/**
Saves the current CPU context that can be restored with a call to LongJump()
and returns 0.
@@ -4653,7 +4674,6 @@ SetJump (
OUT BASE_LIBRARY_JUMP_BUFFER *JumpBuffer
);
-
/**
Restores the CPU context that was saved with SetJump().
@@ -4677,7 +4697,6 @@ LongJump (
IN UINTN Value
);
-
/**
Enables CPU interrupts.
@@ -4688,7 +4707,6 @@ EnableInterrupts (
VOID
);
-
/**
Disables CPU interrupts.
@@ -4699,7 +4717,6 @@ DisableInterrupts (
VOID
);
-
/**
Disables CPU interrupts and returns the interrupt state prior to the disable
operation.
@@ -4714,7 +4731,6 @@ SaveAndDisableInterrupts (
VOID
);
-
/**
Enables CPU interrupts for the smallest window required to capture any
pending interrupts.
@@ -4726,7 +4742,6 @@ EnableDisableInterrupts (
VOID
);
-
/**
Retrieves the current CPU interrupt state.
@@ -4743,7 +4758,6 @@ GetInterruptState (
VOID
);
-
/**
Set the current CPU interrupt state.
@@ -4761,10 +4775,9 @@ GetInterruptState (
BOOLEAN
EFIAPI
SetInterruptState (
- IN BOOLEAN InterruptState
+ IN BOOLEAN InterruptState
);
-
/**
Requests CPU to pause for a short period of time.
@@ -4778,7 +4791,6 @@ CpuPause (
VOID
);
-
/**
Transfers control to a function starting with a new stack.
@@ -4812,13 +4824,12 @@ VOID
EFIAPI
SwitchStack (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
- IN VOID *Context1, OPTIONAL
- IN VOID *Context2, OPTIONAL
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL,
IN VOID *NewStack,
...
);
-
/**
Generates a breakpoint on the CPU.
@@ -4832,7 +4843,6 @@ CpuBreakpoint (
VOID
);
-
/**
Executes an infinite loop.
@@ -4848,7 +4858,6 @@ CpuDeadLoop (
VOID
);
-
/**
Uses as a barrier to stop speculative execution.
@@ -4862,6 +4871,72 @@ SpeculationBarrier (
VOID
);
+#if defined (MDE_CPU_X64) || defined (MDE_CPU_IA32)
+
+/**
+ The TDCALL instruction causes a VM exit to the Intel TDX module. It is
+ used to call guest-side Intel TDX functions, either local or a TD exit
+ to the host VMM, as selected by Leaf.
+
+ @param[in] Leaf Leaf number of TDCALL instruction
+ @param[in] Arg1 Arg1
+ @param[in] Arg2 Arg2
+ @param[in] Arg3 Arg3
+ @param[in,out] Results Returned result of the Leaf function
+
+ @return 0 A successful call
+ @return Other See individual leaf functions
+**/
+UINTN
+EFIAPI
+TdCall (
+ IN UINT64 Leaf,
+ IN UINT64 Arg1,
+ IN UINT64 Arg2,
+ IN UINT64 Arg3,
+ IN OUT VOID *Results
+ );
+
+/**
+ TDVMALL is a leaf function 0 for TDCALL. It helps invoke services from the
+ host VMM to pass/receive information.
+
+ @param[in] Leaf Number of sub-functions
+ @param[in] Arg1 Arg1
+ @param[in] Arg2 Arg2
+ @param[in] Arg3 Arg3
+ @param[in] Arg4 Arg4
+ @param[in,out] Results Returned result of the sub-function
+
+ @return 0 A successful call
+ @return Other See individual sub-functions
+
+**/
+UINTN
+EFIAPI
+TdVmCall (
+ IN UINT64 Leaf,
+ IN UINT64 Arg1,
+ IN UINT64 Arg2,
+ IN UINT64 Arg3,
+ IN UINT64 Arg4,
+ IN OUT VOID *Results
+ );
+
+/**
+ Probe if TD is enabled.
+
+ @return TRUE TD is enabled.
+ @return FALSE TD is not enabled.
+**/
+BOOLEAN
+EFIAPI
+TdIsEnabled (
+ VOID
+ );
+
+#endif
+
#if defined (MDE_CPU_X64)
//
// The page size for the PVALIDATE instruction
@@ -4874,14 +4949,14 @@ typedef enum {
//
// PVALIDATE Return Code.
//
-#define PVALIDATE_RET_SUCCESS 0
-#define PVALIDATE_RET_FAIL_INPUT 1
-#define PVALIDATE_RET_SIZE_MISMATCH 6
+#define PVALIDATE_RET_SUCCESS 0
+#define PVALIDATE_RET_FAIL_INPUT 1
+#define PVALIDATE_RET_SIZE_MISMATCH 6
//
// The PVALIDATE instruction did not make any changes to the RMP entry.
//
-#define PVALIDATE_RET_NO_RMPUPDATE 255
+#define PVALIDATE_RET_NO_RMPUPDATE 255
/**
Execute a PVALIDATE instruction to validate or to rescinds validation of a guest
@@ -4906,9 +4981,9 @@ typedef enum {
UINT32
EFIAPI
AsmPvalidate (
- IN PVALIDATE_PAGE_SIZE PageSize,
- IN BOOLEAN Validate,
- IN PHYSICAL_ADDRESS Address
+ IN PVALIDATE_PAGE_SIZE PageSize,
+ IN BOOLEAN Validate,
+ IN PHYSICAL_ADDRESS Address
);
//
@@ -4941,12 +5016,12 @@ AsmPvalidate (
UINT32
EFIAPI
AsmRmpAdjust (
- IN UINT64 Rax,
- IN UINT64 Rcx,
- IN UINT64 Rdx
+ IN UINT64 Rax,
+ IN UINT64 Rcx,
+ IN UINT64 Rdx
);
-#endif
+#endif
#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
///
@@ -4955,21 +5030,21 @@ AsmRmpAdjust (
///
typedef union {
struct {
- UINT32 CF:1; ///< Carry Flag.
- UINT32 Reserved_0:1; ///< Reserved.
- UINT32 PF:1; ///< Parity Flag.
- UINT32 Reserved_1:1; ///< Reserved.
- UINT32 AF:1; ///< Auxiliary Carry Flag.
- UINT32 Reserved_2:1; ///< Reserved.
- UINT32 ZF:1; ///< Zero Flag.
- UINT32 SF:1; ///< Sign Flag.
- UINT32 TF:1; ///< Trap Flag.
- UINT32 IF:1; ///< Interrupt Enable Flag.
- UINT32 DF:1; ///< Direction Flag.
- UINT32 OF:1; ///< Overflow Flag.
- UINT32 IOPL:2; ///< I/O Privilege Level.
- UINT32 NT:1; ///< Nested Task.
- UINT32 Reserved_3:1; ///< Reserved.
+ UINT32 CF : 1; ///< Carry Flag.
+ UINT32 Reserved_0 : 1; ///< Reserved.
+ UINT32 PF : 1; ///< Parity Flag.
+ UINT32 Reserved_1 : 1; ///< Reserved.
+ UINT32 AF : 1; ///< Auxiliary Carry Flag.
+ UINT32 Reserved_2 : 1; ///< Reserved.
+ UINT32 ZF : 1; ///< Zero Flag.
+ UINT32 SF : 1; ///< Sign Flag.
+ UINT32 TF : 1; ///< Trap Flag.
+ UINT32 IF : 1; ///< Interrupt Enable Flag.
+ UINT32 DF : 1; ///< Direction Flag.
+ UINT32 OF : 1; ///< Overflow Flag.
+ UINT32 IOPL : 2; ///< I/O Privilege Level.
+ UINT32 NT : 1; ///< Nested Task.
+ UINT32 Reserved_3 : 1; ///< Reserved.
} Bits;
UINT16 Uint16;
} IA32_FLAGS16;
@@ -4981,30 +5056,30 @@ typedef union {
///
typedef union {
struct {
- UINT32 CF:1; ///< Carry Flag.
- UINT32 Reserved_0:1; ///< Reserved.
- UINT32 PF:1; ///< Parity Flag.
- UINT32 Reserved_1:1; ///< Reserved.
- UINT32 AF:1; ///< Auxiliary Carry Flag.
- UINT32 Reserved_2:1; ///< Reserved.
- UINT32 ZF:1; ///< Zero Flag.
- UINT32 SF:1; ///< Sign Flag.
- UINT32 TF:1; ///< Trap Flag.
- UINT32 IF:1; ///< Interrupt Enable Flag.
- UINT32 DF:1; ///< Direction Flag.
- UINT32 OF:1; ///< Overflow Flag.
- UINT32 IOPL:2; ///< I/O Privilege Level.
- UINT32 NT:1; ///< Nested Task.
- UINT32 Reserved_3:1; ///< Reserved.
- UINT32 RF:1; ///< Resume Flag.
- UINT32 VM:1; ///< Virtual 8086 Mode.
- UINT32 AC:1; ///< Alignment Check.
- UINT32 VIF:1; ///< Virtual Interrupt Flag.
- UINT32 VIP:1; ///< Virtual Interrupt Pending.
- UINT32 ID:1; ///< ID Flag.
- UINT32 Reserved_4:10; ///< Reserved.
+ UINT32 CF : 1; ///< Carry Flag.
+ UINT32 Reserved_0 : 1; ///< Reserved.
+ UINT32 PF : 1; ///< Parity Flag.
+ UINT32 Reserved_1 : 1; ///< Reserved.
+ UINT32 AF : 1; ///< Auxiliary Carry Flag.
+ UINT32 Reserved_2 : 1; ///< Reserved.
+ UINT32 ZF : 1; ///< Zero Flag.
+ UINT32 SF : 1; ///< Sign Flag.
+ UINT32 TF : 1; ///< Trap Flag.
+ UINT32 IF : 1; ///< Interrupt Enable Flag.
+ UINT32 DF : 1; ///< Direction Flag.
+ UINT32 OF : 1; ///< Overflow Flag.
+ UINT32 IOPL : 2; ///< I/O Privilege Level.
+ UINT32 NT : 1; ///< Nested Task.
+ UINT32 Reserved_3 : 1; ///< Reserved.
+ UINT32 RF : 1; ///< Resume Flag.
+ UINT32 VM : 1; ///< Virtual 8086 Mode.
+ UINT32 AC : 1; ///< Alignment Check.
+ UINT32 VIF : 1; ///< Virtual Interrupt Flag.
+ UINT32 VIP : 1; ///< Virtual Interrupt Pending.
+ UINT32 ID : 1; ///< ID Flag.
+ UINT32 Reserved_4 : 10; ///< Reserved.
} Bits;
- UINTN UintN;
+ UINTN UintN;
} IA32_EFLAGS32;
///
@@ -5014,22 +5089,22 @@ typedef union {
///
typedef union {
struct {
- UINT32 PE:1; ///< Protection Enable.
- UINT32 MP:1; ///< Monitor Coprocessor.
- UINT32 EM:1; ///< Emulation.
- UINT32 TS:1; ///< Task Switched.
- UINT32 ET:1; ///< Extension Type.
- UINT32 NE:1; ///< Numeric Error.
- UINT32 Reserved_0:10; ///< Reserved.
- UINT32 WP:1; ///< Write Protect.
- UINT32 Reserved_1:1; ///< Reserved.
- UINT32 AM:1; ///< Alignment Mask.
- UINT32 Reserved_2:10; ///< Reserved.
- UINT32 NW:1; ///< Mot Write-through.
- UINT32 CD:1; ///< Cache Disable.
- UINT32 PG:1; ///< Paging.
+ UINT32 PE : 1; ///< Protection Enable.
+ UINT32 MP : 1; ///< Monitor Coprocessor.
+ UINT32 EM : 1; ///< Emulation.
+ UINT32 TS : 1; ///< Task Switched.
+ UINT32 ET : 1; ///< Extension Type.
+ UINT32 NE : 1; ///< Numeric Error.
+ UINT32 Reserved_0 : 10; ///< Reserved.
+ UINT32 WP : 1; ///< Write Protect.
+ UINT32 Reserved_1 : 1; ///< Reserved.
+ UINT32 AM : 1; ///< Alignment Mask.
+ UINT32 Reserved_2 : 10; ///< Reserved.
+ UINT32 NW : 1; ///< Mot Write-through.
+ UINT32 CD : 1; ///< Cache Disable.
+ UINT32 PG : 1; ///< Paging.
} Bits;
- UINTN UintN;
+ UINTN UintN;
} IA32_CR0;
///
@@ -5039,36 +5114,36 @@ typedef union {
///
typedef union {
struct {
- UINT32 VME:1; ///< Virtual-8086 Mode Extensions.
- UINT32 PVI:1; ///< Protected-Mode Virtual Interrupts.
- UINT32 TSD:1; ///< Time Stamp Disable.
- UINT32 DE:1; ///< Debugging Extensions.
- UINT32 PSE:1; ///< Page Size Extensions.
- UINT32 PAE:1; ///< Physical Address Extension.
- UINT32 MCE:1; ///< Machine Check Enable.
- UINT32 PGE:1; ///< Page Global Enable.
- UINT32 PCE:1; ///< Performance Monitoring Counter
- ///< Enable.
- UINT32 OSFXSR:1; ///< Operating System Support for
- ///< FXSAVE and FXRSTOR instructions
- UINT32 OSXMMEXCPT:1; ///< Operating System Support for
- ///< Unmasked SIMD Floating Point
- ///< Exceptions.
- UINT32 UMIP:1; ///< User-Mode Instruction Prevention.
- UINT32 LA57:1; ///< Linear Address 57bit.
- UINT32 VMXE:1; ///< VMX Enable.
- UINT32 SMXE:1; ///< SMX Enable.
- UINT32 Reserved_3:1; ///< Reserved.
- UINT32 FSGSBASE:1; ///< FSGSBASE Enable.
- UINT32 PCIDE:1; ///< PCID Enable.
- UINT32 OSXSAVE:1; ///< XSAVE and Processor Extended States Enable.
- UINT32 Reserved_4:1; ///< Reserved.
- UINT32 SMEP:1; ///< SMEP Enable.
- UINT32 SMAP:1; ///< SMAP Enable.
- UINT32 PKE:1; ///< Protection-Key Enable.
- UINT32 Reserved_5:9; ///< Reserved.
+ UINT32 VME : 1; ///< Virtual-8086 Mode Extensions.
+ UINT32 PVI : 1; ///< Protected-Mode Virtual Interrupts.
+ UINT32 TSD : 1; ///< Time Stamp Disable.
+ UINT32 DE : 1; ///< Debugging Extensions.
+ UINT32 PSE : 1; ///< Page Size Extensions.
+ UINT32 PAE : 1; ///< Physical Address Extension.
+ UINT32 MCE : 1; ///< Machine Check Enable.
+ UINT32 PGE : 1; ///< Page Global Enable.
+ UINT32 PCE : 1; ///< Performance Monitoring Counter
+ ///< Enable.
+ UINT32 OSFXSR : 1; ///< Operating System Support for
+ ///< FXSAVE and FXRSTOR instructions
+ UINT32 OSXMMEXCPT : 1; ///< Operating System Support for
+ ///< Unmasked SIMD Floating Point
+ ///< Exceptions.
+ UINT32 UMIP : 1; ///< User-Mode Instruction Prevention.
+ UINT32 LA57 : 1; ///< Linear Address 57bit.
+ UINT32 VMXE : 1; ///< VMX Enable.
+ UINT32 SMXE : 1; ///< SMX Enable.
+ UINT32 Reserved_3 : 1; ///< Reserved.
+ UINT32 FSGSBASE : 1; ///< FSGSBASE Enable.
+ UINT32 PCIDE : 1; ///< PCID Enable.
+ UINT32 OSXSAVE : 1; ///< XSAVE and Processor Extended States Enable.
+ UINT32 Reserved_4 : 1; ///< Reserved.
+ UINT32 SMEP : 1; ///< SMEP Enable.
+ UINT32 SMAP : 1; ///< SMAP Enable.
+ UINT32 PKE : 1; ///< Protection-Key Enable.
+ UINT32 Reserved_5 : 9; ///< Reserved.
} Bits;
- UINTN UintN;
+ UINTN UintN;
} IA32_CR4;
///
@@ -5076,32 +5151,32 @@ typedef union {
///
typedef union {
struct {
- UINT32 LimitLow:16;
- UINT32 BaseLow:16;
- UINT32 BaseMid:8;
- UINT32 Type:4;
- UINT32 S:1;
- UINT32 DPL:2;
- UINT32 P:1;
- UINT32 LimitHigh:4;
- UINT32 AVL:1;
- UINT32 L:1;
- UINT32 DB:1;
- UINT32 G:1;
- UINT32 BaseHigh:8;
+ UINT32 LimitLow : 16;
+ UINT32 BaseLow : 16;
+ UINT32 BaseMid : 8;
+ UINT32 Type : 4;
+ UINT32 S : 1;
+ UINT32 DPL : 2;
+ UINT32 P : 1;
+ UINT32 LimitHigh : 4;
+ UINT32 AVL : 1;
+ UINT32 L : 1;
+ UINT32 DB : 1;
+ UINT32 G : 1;
+ UINT32 BaseHigh : 8;
} Bits;
- UINT64 Uint64;
+ UINT64 Uint64;
} IA32_SEGMENT_DESCRIPTOR;
///
/// Byte packed structure for an IDTR, GDTR, LDTR descriptor.
///
-#pragma pack (1)
+ #pragma pack (1)
typedef struct {
- UINT16 Limit;
- UINTN Base;
+ UINT16 Limit;
+ UINTN Base;
} IA32_DESCRIPTOR;
-#pragma pack ()
+ #pragma pack ()
#define IA32_IDT_GATE_TYPE_TASK 0x85
#define IA32_IDT_GATE_TYPE_INTERRUPT_16 0x86
@@ -5109,25 +5184,25 @@ typedef struct {
#define IA32_IDT_GATE_TYPE_INTERRUPT_32 0x8E
#define IA32_IDT_GATE_TYPE_TRAP_32 0x8F
-#define IA32_GDT_TYPE_TSS 0x9
-#define IA32_GDT_ALIGNMENT 8
+#define IA32_GDT_TYPE_TSS 0x9
+#define IA32_GDT_ALIGNMENT 8
-#if defined (MDE_CPU_IA32)
+ #if defined (MDE_CPU_IA32)
///
/// Byte packed structure for an IA-32 Interrupt Gate Descriptor.
///
typedef union {
struct {
- UINT32 OffsetLow:16; ///< Offset bits 15..0.
- UINT32 Selector:16; ///< Selector.
- UINT32 Reserved_0:8; ///< Reserved.
- UINT32 GateType:8; ///< Gate Type. See #defines above.
- UINT32 OffsetHigh:16; ///< Offset bits 31..16.
+ UINT32 OffsetLow : 16; ///< Offset bits 15..0.
+ UINT32 Selector : 16; ///< Selector.
+ UINT32 Reserved_0 : 8; ///< Reserved.
+ UINT32 GateType : 8; ///< Gate Type. See #defines above.
+ UINT32 OffsetHigh : 16; ///< Offset bits 31..16.
} Bits;
- UINT64 Uint64;
+ UINT64 Uint64;
} IA32_IDT_GATE_DESCRIPTOR;
-#pragma pack (1)
+ #pragma pack (1)
//
// IA32 Task-State Segment Definition
//
@@ -5174,46 +5249,46 @@ typedef struct {
typedef union {
struct {
- UINT32 LimitLow:16; ///< Segment Limit 15..00
- UINT32 BaseLow:16; ///< Base Address 15..00
- UINT32 BaseMid:8; ///< Base Address 23..16
- UINT32 Type:4; ///< Type (1 0 B 1)
- UINT32 Reserved_43:1; ///< 0
- UINT32 DPL:2; ///< Descriptor Privilege Level
- UINT32 P:1; ///< Segment Present
- UINT32 LimitHigh:4; ///< Segment Limit 19..16
- UINT32 AVL:1; ///< Available for use by system software
- UINT32 Reserved_52:2; ///< 0 0
- UINT32 G:1; ///< Granularity
- UINT32 BaseHigh:8; ///< Base Address 31..24
+ UINT32 LimitLow : 16; ///< Segment Limit 15..00
+ UINT32 BaseLow : 16; ///< Base Address 15..00
+ UINT32 BaseMid : 8; ///< Base Address 23..16
+ UINT32 Type : 4; ///< Type (1 0 B 1)
+ UINT32 Reserved_43 : 1; ///< 0
+ UINT32 DPL : 2; ///< Descriptor Privilege Level
+ UINT32 P : 1; ///< Segment Present
+ UINT32 LimitHigh : 4; ///< Segment Limit 19..16
+ UINT32 AVL : 1; ///< Available for use by system software
+ UINT32 Reserved_52 : 2; ///< 0 0
+ UINT32 G : 1; ///< Granularity
+ UINT32 BaseHigh : 8; ///< Base Address 31..24
} Bits;
- UINT64 Uint64;
+ UINT64 Uint64;
} IA32_TSS_DESCRIPTOR;
-#pragma pack ()
+ #pragma pack ()
-#endif // defined (MDE_CPU_IA32)
+ #endif // defined (MDE_CPU_IA32)
-#if defined (MDE_CPU_X64)
+ #if defined (MDE_CPU_X64)
///
/// Byte packed structure for an x64 Interrupt Gate Descriptor.
///
typedef union {
struct {
- UINT32 OffsetLow:16; ///< Offset bits 15..0.
- UINT32 Selector:16; ///< Selector.
- UINT32 Reserved_0:8; ///< Reserved.
- UINT32 GateType:8; ///< Gate Type. See #defines above.
- UINT32 OffsetHigh:16; ///< Offset bits 31..16.
- UINT32 OffsetUpper:32; ///< Offset bits 63..32.
- UINT32 Reserved_1:32; ///< Reserved.
+ UINT32 OffsetLow : 16; ///< Offset bits 15..0.
+ UINT32 Selector : 16; ///< Selector.
+ UINT32 Reserved_0 : 8; ///< Reserved.
+ UINT32 GateType : 8; ///< Gate Type. See #defines above.
+ UINT32 OffsetHigh : 16; ///< Offset bits 31..16.
+ UINT32 OffsetUpper : 32; ///< Offset bits 63..32.
+ UINT32 Reserved_1 : 32; ///< Reserved.
} Bits;
struct {
- UINT64 Uint64;
- UINT64 Uint64_1;
+ UINT64 Uint64;
+ UINT64 Uint64_1;
} Uint128;
} IA32_IDT_GATE_DESCRIPTOR;
-#pragma pack (1)
+ #pragma pack (1)
//
// IA32 Task-State Segment Definition
//
@@ -5231,116 +5306,116 @@ typedef struct {
typedef union {
struct {
- UINT32 LimitLow:16; ///< Segment Limit 15..00
- UINT32 BaseLow:16; ///< Base Address 15..00
- UINT32 BaseMidl:8; ///< Base Address 23..16
- UINT32 Type:4; ///< Type (1 0 B 1)
- UINT32 Reserved_43:1; ///< 0
- UINT32 DPL:2; ///< Descriptor Privilege Level
- UINT32 P:1; ///< Segment Present
- UINT32 LimitHigh:4; ///< Segment Limit 19..16
- UINT32 AVL:1; ///< Available for use by system software
- UINT32 Reserved_52:2; ///< 0 0
- UINT32 G:1; ///< Granularity
- UINT32 BaseMidh:8; ///< Base Address 31..24
- UINT32 BaseHigh:32; ///< Base Address 63..32
- UINT32 Reserved_96:32; ///< Reserved
+ UINT32 LimitLow : 16; ///< Segment Limit 15..00
+ UINT32 BaseLow : 16; ///< Base Address 15..00
+ UINT32 BaseMidl : 8; ///< Base Address 23..16
+ UINT32 Type : 4; ///< Type (1 0 B 1)
+ UINT32 Reserved_43 : 1; ///< 0
+ UINT32 DPL : 2; ///< Descriptor Privilege Level
+ UINT32 P : 1; ///< Segment Present
+ UINT32 LimitHigh : 4; ///< Segment Limit 19..16
+ UINT32 AVL : 1; ///< Available for use by system software
+ UINT32 Reserved_52 : 2; ///< 0 0
+ UINT32 G : 1; ///< Granularity
+ UINT32 BaseMidh : 8; ///< Base Address 31..24
+ UINT32 BaseHigh : 32; ///< Base Address 63..32
+ UINT32 Reserved_96 : 32; ///< Reserved
} Bits;
struct {
- UINT64 Uint64;
- UINT64 Uint64_1;
+ UINT64 Uint64;
+ UINT64 Uint64_1;
} Uint128;
} IA32_TSS_DESCRIPTOR;
-#pragma pack ()
+ #pragma pack ()
-#endif // defined (MDE_CPU_X64)
+ #endif // defined (MDE_CPU_X64)
///
/// Byte packed structure for an FP/SSE/SSE2 context.
///
typedef struct {
- UINT8 Buffer[512];
+ UINT8 Buffer[512];
} IA32_FX_BUFFER;
///
/// Structures for the 16-bit real mode thunks.
///
typedef struct {
- UINT32 Reserved1;
- UINT32 Reserved2;
- UINT32 Reserved3;
- UINT32 Reserved4;
- UINT8 BL;
- UINT8 BH;
- UINT16 Reserved5;
- UINT8 DL;
- UINT8 DH;
- UINT16 Reserved6;
- UINT8 CL;
- UINT8 CH;
- UINT16 Reserved7;
- UINT8 AL;
- UINT8 AH;
- UINT16 Reserved8;
+ UINT32 Reserved1;
+ UINT32 Reserved2;
+ UINT32 Reserved3;
+ UINT32 Reserved4;
+ UINT8 BL;
+ UINT8 BH;
+ UINT16 Reserved5;
+ UINT8 DL;
+ UINT8 DH;
+ UINT16 Reserved6;
+ UINT8 CL;
+ UINT8 CH;
+ UINT16 Reserved7;
+ UINT8 AL;
+ UINT8 AH;
+ UINT16 Reserved8;
} IA32_BYTE_REGS;
typedef struct {
- UINT16 DI;
- UINT16 Reserved1;
- UINT16 SI;
- UINT16 Reserved2;
- UINT16 BP;
- UINT16 Reserved3;
- UINT16 SP;
- UINT16 Reserved4;
- UINT16 BX;
- UINT16 Reserved5;
- UINT16 DX;
- UINT16 Reserved6;
- UINT16 CX;
- UINT16 Reserved7;
- UINT16 AX;
- UINT16 Reserved8;
+ UINT16 DI;
+ UINT16 Reserved1;
+ UINT16 SI;
+ UINT16 Reserved2;
+ UINT16 BP;
+ UINT16 Reserved3;
+ UINT16 SP;
+ UINT16 Reserved4;
+ UINT16 BX;
+ UINT16 Reserved5;
+ UINT16 DX;
+ UINT16 Reserved6;
+ UINT16 CX;
+ UINT16 Reserved7;
+ UINT16 AX;
+ UINT16 Reserved8;
} IA32_WORD_REGS;
typedef struct {
- UINT32 EDI;
- UINT32 ESI;
- UINT32 EBP;
- UINT32 ESP;
- UINT32 EBX;
- UINT32 EDX;
- UINT32 ECX;
- UINT32 EAX;
- UINT16 DS;
- UINT16 ES;
- UINT16 FS;
- UINT16 GS;
- IA32_EFLAGS32 EFLAGS;
- UINT32 Eip;
- UINT16 CS;
- UINT16 SS;
+ UINT32 EDI;
+ UINT32 ESI;
+ UINT32 EBP;
+ UINT32 ESP;
+ UINT32 EBX;
+ UINT32 EDX;
+ UINT32 ECX;
+ UINT32 EAX;
+ UINT16 DS;
+ UINT16 ES;
+ UINT16 FS;
+ UINT16 GS;
+ IA32_EFLAGS32 EFLAGS;
+ UINT32 Eip;
+ UINT16 CS;
+ UINT16 SS;
} IA32_DWORD_REGS;
typedef union {
- IA32_DWORD_REGS E;
- IA32_WORD_REGS X;
- IA32_BYTE_REGS H;
+ IA32_DWORD_REGS E;
+ IA32_WORD_REGS X;
+ IA32_BYTE_REGS H;
} IA32_REGISTER_SET;
///
/// Byte packed structure for an 16-bit real mode thunks.
///
typedef struct {
- IA32_REGISTER_SET *RealModeState;
- VOID *RealModeBuffer;
- UINT32 RealModeBufferSize;
- UINT32 ThunkAttributes;
+ IA32_REGISTER_SET *RealModeState;
+ VOID *RealModeBuffer;
+ UINT32 RealModeBufferSize;
+ UINT32 ThunkAttributes;
} THUNK_CONTEXT;
-#define THUNK_ATTRIBUTE_BIG_REAL_MODE 0x00000001
-#define THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 0x00000002
-#define THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL 0x00000004
+#define THUNK_ATTRIBUTE_BIG_REAL_MODE 0x00000001
+#define THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 0x00000002
+#define THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL 0x00000004
///
/// Type definition for representing labels in NASM source code that allow for
@@ -5354,7 +5429,9 @@ typedef struct {
/// edk2 coding style for function (or pointer-to-function) typedefs. The VOID
/// return type and the VOID argument list are merely artifacts.
///
-typedef VOID (X86_ASSEMBLY_PATCH_LABEL) (VOID);
+typedef VOID (X86_ASSEMBLY_PATCH_LABEL) (
+ VOID
+ );
/**
Retrieves CPUID information.
@@ -5384,14 +5461,13 @@ typedef VOID (X86_ASSEMBLY_PATCH_LABEL) (VOID);
UINT32
EFIAPI
AsmCpuid (
- IN UINT32 Index,
- OUT UINT32 *Eax, OPTIONAL
- OUT UINT32 *Ebx, OPTIONAL
- OUT UINT32 *Ecx, OPTIONAL
- OUT UINT32 *Edx OPTIONAL
+ IN UINT32 Index,
+ OUT UINT32 *Eax OPTIONAL,
+ OUT UINT32 *Ebx OPTIONAL,
+ OUT UINT32 *Ecx OPTIONAL,
+ OUT UINT32 *Edx OPTIONAL
);
-
/**
Retrieves CPUID information using an extended leaf identifier.
@@ -5427,15 +5503,14 @@ AsmCpuid (
UINT32
EFIAPI
AsmCpuidEx (
- IN UINT32 Index,
- IN UINT32 SubIndex,
- OUT UINT32 *Eax, OPTIONAL
- OUT UINT32 *Ebx, OPTIONAL
- OUT UINT32 *Ecx, OPTIONAL
- OUT UINT32 *Edx OPTIONAL
+ IN UINT32 Index,
+ IN UINT32 SubIndex,
+ OUT UINT32 *Eax OPTIONAL,
+ OUT UINT32 *Ebx OPTIONAL,
+ OUT UINT32 *Ecx OPTIONAL,
+ OUT UINT32 *Edx OPTIONAL
);
-
/**
Set CD bit and clear NW bit of CR0 followed by a WBINVD.
@@ -5449,7 +5524,6 @@ AsmDisableCache (
VOID
);
-
/**
Perform a WBINVD and clear both the CD and NW bits of CR0.
@@ -5463,7 +5537,6 @@ AsmEnableCache (
VOID
);
-
/**
Returns the lower 32-bits of a Machine Specific Register(MSR).
@@ -5481,10 +5554,9 @@ AsmEnableCache (
UINT32
EFIAPI
AsmReadMsr32 (
- IN UINT32 Index
+ IN UINT32 Index
);
-
/**
Writes a 32-bit value to a Machine Specific Register(MSR), and returns the value.
The upper 32-bits of the MSR are set to zero.
@@ -5505,11 +5577,10 @@ AsmReadMsr32 (
UINT32
EFIAPI
AsmWriteMsr32 (
- IN UINT32 Index,
- IN UINT32 Value
+ IN UINT32 Index,
+ IN UINT32 Value
);
-
/**
Reads a 64-bit MSR, performs a bitwise OR on the lower 32-bits, and
writes the result back to the 64-bit MSR.
@@ -5532,11 +5603,10 @@ AsmWriteMsr32 (
UINT32
EFIAPI
AsmMsrOr32 (
- IN UINT32 Index,
- IN UINT32 OrData
+ IN UINT32 Index,
+ IN UINT32 OrData
);
-
/**
Reads a 64-bit MSR, performs a bitwise AND on the lower 32-bits, and writes
the result back to the 64-bit MSR.
@@ -5559,11 +5629,10 @@ AsmMsrOr32 (
UINT32
EFIAPI
AsmMsrAnd32 (
- IN UINT32 Index,
- IN UINT32 AndData
+ IN UINT32 Index,
+ IN UINT32 AndData
);
-
/**
Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise OR
on the lower 32-bits, and writes the result back to the 64-bit MSR.
@@ -5589,12 +5658,11 @@ AsmMsrAnd32 (
UINT32
EFIAPI
AsmMsrAndThenOr32 (
- IN UINT32 Index,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINT32 Index,
+ IN UINT32 AndData,
+ IN UINT32 OrData
);
-
/**
Reads a bit field of an MSR.
@@ -5620,12 +5688,11 @@ AsmMsrAndThenOr32 (
UINT32
EFIAPI
AsmMsrBitFieldRead32 (
- IN UINT32 Index,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
-
/**
Writes a bit field to an MSR.
@@ -5654,13 +5721,12 @@ AsmMsrBitFieldRead32 (
UINT32
EFIAPI
AsmMsrBitFieldWrite32 (
- IN UINT32 Index,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
);
-
/**
Reads a bit field in a 64-bit MSR, performs a bitwise OR, and writes the
result back to the bit field in the 64-bit MSR.
@@ -5691,13 +5757,12 @@ AsmMsrBitFieldWrite32 (
UINT32
EFIAPI
AsmMsrBitFieldOr32 (
- IN UINT32 Index,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
);
-
/**
Reads a bit field in a 64-bit MSR, performs a bitwise AND, and writes the
result back to the bit field in the 64-bit MSR.
@@ -5728,13 +5793,12 @@ AsmMsrBitFieldOr32 (
UINT32
EFIAPI
AsmMsrBitFieldAnd32 (
- IN UINT32 Index,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
);
-
/**
Reads a bit field in a 64-bit MSR, performs a bitwise AND followed by a
bitwise OR, and writes the result back to the bit field in the
@@ -5769,14 +5833,13 @@ AsmMsrBitFieldAnd32 (
UINT32
EFIAPI
AsmMsrBitFieldAndThenOr32 (
- IN UINT32 Index,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
);
-
/**
Returns a 64-bit Machine Specific Register(MSR).
@@ -5794,10 +5857,9 @@ AsmMsrBitFieldAndThenOr32 (
UINT64
EFIAPI
AsmReadMsr64 (
- IN UINT32 Index
+ IN UINT32 Index
);
-
/**
Writes a 64-bit value to a Machine Specific Register(MSR), and returns the
value.
@@ -5818,11 +5880,10 @@ AsmReadMsr64 (
UINT64
EFIAPI
AsmWriteMsr64 (
- IN UINT32 Index,
- IN UINT64 Value
+ IN UINT32 Index,
+ IN UINT64 Value
);
-
/**
Reads a 64-bit MSR, performs a bitwise OR, and writes the result
back to the 64-bit MSR.
@@ -5844,11 +5905,10 @@ AsmWriteMsr64 (
UINT64
EFIAPI
AsmMsrOr64 (
- IN UINT32 Index,
- IN UINT64 OrData
+ IN UINT32 Index,
+ IN UINT64 OrData
);
-
/**
Reads a 64-bit MSR, performs a bitwise AND, and writes the result back to the
64-bit MSR.
@@ -5870,11 +5930,10 @@ AsmMsrOr64 (
UINT64
EFIAPI
AsmMsrAnd64 (
- IN UINT32 Index,
- IN UINT64 AndData
+ IN UINT32 Index,
+ IN UINT64 AndData
);
-
/**
Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise
OR, and writes the result back to the 64-bit MSR.
@@ -5899,12 +5958,11 @@ AsmMsrAnd64 (
UINT64
EFIAPI
AsmMsrAndThenOr64 (
- IN UINT32 Index,
- IN UINT64 AndData,
- IN UINT64 OrData
+ IN UINT32 Index,
+ IN UINT64 AndData,
+ IN UINT64 OrData
);
-
/**
Reads a bit field of an MSR.
@@ -5930,12 +5988,11 @@ AsmMsrAndThenOr64 (
UINT64
EFIAPI
AsmMsrBitFieldRead64 (
- IN UINT32 Index,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
-
/**
Writes a bit field to an MSR.
@@ -5963,13 +6020,12 @@ AsmMsrBitFieldRead64 (
UINT64
EFIAPI
AsmMsrBitFieldWrite64 (
- IN UINT32 Index,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 Value
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 Value
);
-
/**
Reads a bit field in a 64-bit MSR, performs a bitwise OR, and
writes the result back to the bit field in the 64-bit MSR.
@@ -6000,13 +6056,12 @@ AsmMsrBitFieldWrite64 (
UINT64
EFIAPI
AsmMsrBitFieldOr64 (
- IN UINT32 Index,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 OrData
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 OrData
);
-
/**
Reads a bit field in a 64-bit MSR, performs a bitwise AND, and writes the
result back to the bit field in the 64-bit MSR.
@@ -6037,13 +6092,12 @@ AsmMsrBitFieldOr64 (
UINT64
EFIAPI
AsmMsrBitFieldAnd64 (
- IN UINT32 Index,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 AndData
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData
);
-
/**
Reads a bit field in a 64-bit MSR, performs a bitwise AND followed by a
bitwise OR, and writes the result back to the bit field in the
@@ -6077,14 +6131,13 @@ AsmMsrBitFieldAnd64 (
UINT64
EFIAPI
AsmMsrBitFieldAndThenOr64 (
- IN UINT32 Index,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 AndData,
- IN UINT64 OrData
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData,
+ IN UINT64 OrData
);
-
/**
Reads the current value of the EFLAGS register.
@@ -6101,7 +6154,6 @@ AsmReadEflags (
VOID
);
-
/**
Reads the current value of the Control Register 0 (CR0).
@@ -6118,7 +6170,6 @@ AsmReadCr0 (
VOID
);
-
/**
Reads the current value of the Control Register 2 (CR2).
@@ -6135,7 +6186,6 @@ AsmReadCr2 (
VOID
);
-
/**
Reads the current value of the Control Register 3 (CR3).
@@ -6152,7 +6202,6 @@ AsmReadCr3 (
VOID
);
-
/**
Reads the current value of the Control Register 4 (CR4).
@@ -6169,7 +6218,6 @@ AsmReadCr4 (
VOID
);
-
/**
Writes a value to Control Register 0 (CR0).
@@ -6187,7 +6235,6 @@ AsmWriteCr0 (
UINTN Cr0
);
-
/**
Writes a value to Control Register 2 (CR2).
@@ -6205,7 +6252,6 @@ AsmWriteCr2 (
UINTN Cr2
);
-
/**
Writes a value to Control Register 3 (CR3).
@@ -6223,7 +6269,6 @@ AsmWriteCr3 (
UINTN Cr3
);
-
/**
Writes a value to Control Register 4 (CR4).
@@ -6241,7 +6286,6 @@ AsmWriteCr4 (
UINTN Cr4
);
-
/**
Reads the current value of Debug Register 0 (DR0).
@@ -6258,7 +6302,6 @@ AsmReadDr0 (
VOID
);
-
/**
Reads the current value of Debug Register 1 (DR1).
@@ -6275,7 +6318,6 @@ AsmReadDr1 (
VOID
);
-
/**
Reads the current value of Debug Register 2 (DR2).
@@ -6292,7 +6334,6 @@ AsmReadDr2 (
VOID
);
-
/**
Reads the current value of Debug Register 3 (DR3).
@@ -6309,7 +6350,6 @@ AsmReadDr3 (
VOID
);
-
/**
Reads the current value of Debug Register 4 (DR4).
@@ -6326,7 +6366,6 @@ AsmReadDr4 (
VOID
);
-
/**
Reads the current value of Debug Register 5 (DR5).
@@ -6343,7 +6382,6 @@ AsmReadDr5 (
VOID
);
-
/**
Reads the current value of Debug Register 6 (DR6).
@@ -6360,7 +6398,6 @@ AsmReadDr6 (
VOID
);
-
/**
Reads the current value of Debug Register 7 (DR7).
@@ -6377,7 +6414,6 @@ AsmReadDr7 (
VOID
);
-
/**
Writes a value to Debug Register 0 (DR0).
@@ -6395,7 +6431,6 @@ AsmWriteDr0 (
UINTN Dr0
);
-
/**
Writes a value to Debug Register 1 (DR1).
@@ -6413,7 +6448,6 @@ AsmWriteDr1 (
UINTN Dr1
);
-
/**
Writes a value to Debug Register 2 (DR2).
@@ -6431,7 +6465,6 @@ AsmWriteDr2 (
UINTN Dr2
);
-
/**
Writes a value to Debug Register 3 (DR3).
@@ -6449,7 +6482,6 @@ AsmWriteDr3 (
UINTN Dr3
);
-
/**
Writes a value to Debug Register 4 (DR4).
@@ -6467,7 +6499,6 @@ AsmWriteDr4 (
UINTN Dr4
);
-
/**
Writes a value to Debug Register 5 (DR5).
@@ -6485,7 +6516,6 @@ AsmWriteDr5 (
UINTN Dr5
);
-
/**
Writes a value to Debug Register 6 (DR6).
@@ -6503,7 +6533,6 @@ AsmWriteDr6 (
UINTN Dr6
);
-
/**
Writes a value to Debug Register 7 (DR7).
@@ -6521,7 +6550,6 @@ AsmWriteDr7 (
UINTN Dr7
);
-
/**
Reads the current value of Code Segment Register (CS).
@@ -6537,7 +6565,6 @@ AsmReadCs (
VOID
);
-
/**
Reads the current value of Data Segment Register (DS).
@@ -6553,7 +6580,6 @@ AsmReadDs (
VOID
);
-
/**
Reads the current value of Extra Segment Register (ES).
@@ -6569,7 +6595,6 @@ AsmReadEs (
VOID
);
-
/**
Reads the current value of FS Data Segment Register (FS).
@@ -6585,7 +6610,6 @@ AsmReadFs (
VOID
);
-
/**
Reads the current value of GS Data Segment Register (GS).
@@ -6601,7 +6625,6 @@ AsmReadGs (
VOID
);
-
/**
Reads the current value of Stack Segment Register (SS).
@@ -6617,7 +6640,6 @@ AsmReadSs (
VOID
);
-
/**
Reads the current value of Task Register (TR).
@@ -6633,7 +6655,6 @@ AsmReadTr (
VOID
);
-
/**
Reads the current Global Descriptor Table Register(GDTR) descriptor.
@@ -6648,10 +6669,9 @@ AsmReadTr (
VOID
EFIAPI
AsmReadGdtr (
- OUT IA32_DESCRIPTOR *Gdtr
+ OUT IA32_DESCRIPTOR *Gdtr
);
-
/**
Writes the current Global Descriptor Table Register (GDTR) descriptor.
@@ -6666,10 +6686,9 @@ AsmReadGdtr (
VOID
EFIAPI
AsmWriteGdtr (
- IN CONST IA32_DESCRIPTOR *Gdtr
+ IN CONST IA32_DESCRIPTOR *Gdtr
);
-
/**
Reads the current Interrupt Descriptor Table Register(IDTR) descriptor.
@@ -6684,10 +6703,9 @@ AsmWriteGdtr (
VOID
EFIAPI
AsmReadIdtr (
- OUT IA32_DESCRIPTOR *Idtr
+ OUT IA32_DESCRIPTOR *Idtr
);
-
/**
Writes the current Interrupt Descriptor Table Register(IDTR) descriptor.
@@ -6702,10 +6720,9 @@ AsmReadIdtr (
VOID
EFIAPI
AsmWriteIdtr (
- IN CONST IA32_DESCRIPTOR *Idtr
+ IN CONST IA32_DESCRIPTOR *Idtr
);
-
/**
Reads the current Local Descriptor Table Register(LDTR) selector.
@@ -6721,7 +6738,6 @@ AsmReadLdtr (
VOID
);
-
/**
Writes the current Local Descriptor Table Register (LDTR) selector.
@@ -6734,10 +6750,9 @@ AsmReadLdtr (
VOID
EFIAPI
AsmWriteLdtr (
- IN UINT16 Ldtr
+ IN UINT16 Ldtr
);
-
/**
Save the current floating point/SSE/SSE2 context to a buffer.
@@ -6754,10 +6769,9 @@ AsmWriteLdtr (
VOID
EFIAPI
AsmFxSave (
- OUT IA32_FX_BUFFER *Buffer
+ OUT IA32_FX_BUFFER *Buffer
);
-
/**
Restores the current floating point/SSE/SSE2 context from a buffer.
@@ -6775,10 +6789,9 @@ AsmFxSave (
VOID
EFIAPI
AsmFxRestore (
- IN CONST IA32_FX_BUFFER *Buffer
+ IN CONST IA32_FX_BUFFER *Buffer
);
-
/**
Reads the current value of 64-bit MMX Register #0 (MM0).
@@ -6794,7 +6807,6 @@ AsmReadMm0 (
VOID
);
-
/**
Reads the current value of 64-bit MMX Register #1 (MM1).
@@ -6810,7 +6822,6 @@ AsmReadMm1 (
VOID
);
-
/**
Reads the current value of 64-bit MMX Register #2 (MM2).
@@ -6826,7 +6837,6 @@ AsmReadMm2 (
VOID
);
-
/**
Reads the current value of 64-bit MMX Register #3 (MM3).
@@ -6842,7 +6852,6 @@ AsmReadMm3 (
VOID
);
-
/**
Reads the current value of 64-bit MMX Register #4 (MM4).
@@ -6858,7 +6867,6 @@ AsmReadMm4 (
VOID
);
-
/**
Reads the current value of 64-bit MMX Register #5 (MM5).
@@ -6874,7 +6882,6 @@ AsmReadMm5 (
VOID
);
-
/**
Reads the current value of 64-bit MMX Register #6 (MM6).
@@ -6890,7 +6897,6 @@ AsmReadMm6 (
VOID
);
-
/**
Reads the current value of 64-bit MMX Register #7 (MM7).
@@ -6906,7 +6912,6 @@ AsmReadMm7 (
VOID
);
-
/**
Writes the current value of 64-bit MMX Register #0 (MM0).
@@ -6919,10 +6924,9 @@ AsmReadMm7 (
VOID
EFIAPI
AsmWriteMm0 (
- IN UINT64 Value
+ IN UINT64 Value
);
-
/**
Writes the current value of 64-bit MMX Register #1 (MM1).
@@ -6935,10 +6939,9 @@ AsmWriteMm0 (
VOID
EFIAPI
AsmWriteMm1 (
- IN UINT64 Value
+ IN UINT64 Value
);
-
/**
Writes the current value of 64-bit MMX Register #2 (MM2).
@@ -6951,10 +6954,9 @@ AsmWriteMm1 (
VOID
EFIAPI
AsmWriteMm2 (
- IN UINT64 Value
+ IN UINT64 Value
);
-
/**
Writes the current value of 64-bit MMX Register #3 (MM3).
@@ -6967,10 +6969,9 @@ AsmWriteMm2 (
VOID
EFIAPI
AsmWriteMm3 (
- IN UINT64 Value
+ IN UINT64 Value
);
-
/**
Writes the current value of 64-bit MMX Register #4 (MM4).
@@ -6983,10 +6984,9 @@ AsmWriteMm3 (
VOID
EFIAPI
AsmWriteMm4 (
- IN UINT64 Value
+ IN UINT64 Value
);
-
/**
Writes the current value of 64-bit MMX Register #5 (MM5).
@@ -6999,10 +6999,9 @@ AsmWriteMm4 (
VOID
EFIAPI
AsmWriteMm5 (
- IN UINT64 Value
+ IN UINT64 Value
);
-
/**
Writes the current value of 64-bit MMX Register #6 (MM6).
@@ -7015,10 +7014,9 @@ AsmWriteMm5 (
VOID
EFIAPI
AsmWriteMm6 (
- IN UINT64 Value
+ IN UINT64 Value
);
-
/**
Writes the current value of 64-bit MMX Register #7 (MM7).
@@ -7031,10 +7029,9 @@ AsmWriteMm6 (
VOID
EFIAPI
AsmWriteMm7 (
- IN UINT64 Value
+ IN UINT64 Value
);
-
/**
Reads the current value of Time Stamp Counter (TSC).
@@ -7050,7 +7047,6 @@ AsmReadTsc (
VOID
);
-
/**
Reads the current value of a Performance Counter (PMC).
@@ -7065,10 +7061,9 @@ AsmReadTsc (
UINT64
EFIAPI
AsmReadPmc (
- IN UINT32 Index
+ IN UINT32 Index
);
-
/**
Sets up a monitor buffer that is used by AsmMwait().
@@ -7088,12 +7083,11 @@ AsmReadPmc (
UINTN
EFIAPI
AsmMonitor (
- IN UINTN Eax,
- IN UINTN Ecx,
- IN UINTN Edx
+ IN UINTN Eax,
+ IN UINTN Ecx,
+ IN UINTN Edx
);
-
/**
Executes an MWAIT instruction.
@@ -7111,11 +7105,10 @@ AsmMonitor (
UINTN
EFIAPI
AsmMwait (
- IN UINTN Eax,
- IN UINTN Ecx
+ IN UINTN Eax,
+ IN UINTN Ecx
);
-
/**
Executes a WBINVD instruction.
@@ -7129,7 +7122,6 @@ AsmWbinvd (
VOID
);
-
/**
Executes a INVD instruction.
@@ -7143,7 +7135,6 @@ AsmInvd (
VOID
);
-
/**
Flushes a cache line from all the instruction and data caches within the
coherency domain of the CPU.
@@ -7162,10 +7153,9 @@ AsmInvd (
VOID *
EFIAPI
AsmFlushCacheLine (
- IN VOID *LinearAddress
+ IN VOID *LinearAddress
);
-
/**
Enables the 32-bit paging mode on the CPU.
@@ -7207,12 +7197,11 @@ VOID
EFIAPI
AsmEnablePaging32 (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
- IN VOID *Context1, OPTIONAL
- IN VOID *Context2, OPTIONAL
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL,
IN VOID *NewStack
);
-
/**
Disables the 32-bit paging mode on the CPU.
@@ -7251,12 +7240,11 @@ VOID
EFIAPI
AsmDisablePaging32 (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
- IN VOID *Context1, OPTIONAL
- IN VOID *Context2, OPTIONAL
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL,
IN VOID *NewStack
);
-
/**
Enables the 64-bit paging mode on the CPU.
@@ -7292,14 +7280,13 @@ AsmDisablePaging32 (
VOID
EFIAPI
AsmEnablePaging64 (
- IN UINT16 Cs,
- IN UINT64 EntryPoint,
- IN UINT64 Context1, OPTIONAL
- IN UINT64 Context2, OPTIONAL
- IN UINT64 NewStack
+ IN UINT16 Cs,
+ IN UINT64 EntryPoint,
+ IN UINT64 Context1 OPTIONAL,
+ IN UINT64 Context2 OPTIONAL,
+ IN UINT64 NewStack
);
-
/**
Disables the 64-bit paging mode on the CPU.
@@ -7333,14 +7320,13 @@ AsmEnablePaging64 (
VOID
EFIAPI
AsmDisablePaging64 (
- IN UINT16 Cs,
- IN UINT32 EntryPoint,
- IN UINT32 Context1, OPTIONAL
- IN UINT32 Context2, OPTIONAL
- IN UINT32 NewStack
+ IN UINT16 Cs,
+ IN UINT32 EntryPoint,
+ IN UINT32 Context1 OPTIONAL,
+ IN UINT32 Context2 OPTIONAL,
+ IN UINT32 NewStack
);
-
//
// 16-bit thunking services
//
@@ -7369,11 +7355,10 @@ AsmDisablePaging64 (
VOID
EFIAPI
AsmGetThunk16Properties (
- OUT UINT32 *RealModeBufferSize,
- OUT UINT32 *ExtraStackSize
+ OUT UINT32 *RealModeBufferSize,
+ OUT UINT32 *ExtraStackSize
);
-
/**
Prepares all structures a code required to use AsmThunk16().
@@ -7391,10 +7376,9 @@ AsmGetThunk16Properties (
VOID
EFIAPI
AsmPrepareThunk16 (
- IN OUT THUNK_CONTEXT *ThunkContext
+ IN OUT THUNK_CONTEXT *ThunkContext
);
-
/**
Transfers control to a 16-bit real mode entry point and returns the results.
@@ -7451,10 +7435,9 @@ AsmPrepareThunk16 (
VOID
EFIAPI
AsmThunk16 (
- IN OUT THUNK_CONTEXT *ThunkContext
+ IN OUT THUNK_CONTEXT *ThunkContext
);
-
/**
Prepares all structures and code for a 16-bit real mode thunk, transfers
control to a 16-bit real mode entry point, and returns the results.
@@ -7478,7 +7461,7 @@ AsmThunk16 (
VOID
EFIAPI
AsmPrepareAndThunk16 (
- IN OUT THUNK_CONTEXT *ThunkContext
+ IN OUT THUNK_CONTEXT *ThunkContext
);
/**
@@ -7495,7 +7478,7 @@ AsmPrepareAndThunk16 (
BOOLEAN
EFIAPI
AsmRdRand16 (
- OUT UINT16 *Rand
+ OUT UINT16 *Rand
);
/**
@@ -7512,7 +7495,7 @@ AsmRdRand16 (
BOOLEAN
EFIAPI
AsmRdRand32 (
- OUT UINT32 *Rand
+ OUT UINT32 *Rand
);
/**
@@ -7529,7 +7512,7 @@ AsmRdRand32 (
BOOLEAN
EFIAPI
AsmRdRand64 (
- OUT UINT64 *Rand
+ OUT UINT64 *Rand
);
/**
@@ -7540,7 +7523,7 @@ AsmRdRand64 (
VOID
EFIAPI
AsmWriteTr (
- IN UINT16 Selector
+ IN UINT16 Selector
);
/**
@@ -7609,7 +7592,6 @@ AsmVmgExit (
VOID
);
-
/**
Patch the immediate operand of an IA32 or X64 instruction such that the byte,
word, dword or qword operand is encoded at the end of the instruction's
@@ -7647,9 +7629,9 @@ AsmVmgExit (
VOID
EFIAPI
PatchInstructionX86 (
- OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
- IN UINT64 PatchValue,
- IN UINTN ValueSize
+ OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
+ IN UINT64 PatchValue,
+ IN UINTN ValueSize
);
#endif // defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
diff --git a/MdePkg/Include/Library/DebugLib.h b/MdePkg/Include/Library/DebugLib.h
index b3bcc523..128667fa 100644
--- a/MdePkg/Include/Library/DebugLib.h
+++ b/MdePkg/Include/Library/DebugLib.h
@@ -29,26 +29,28 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// Declare bits for PcdDebugPrintErrorLevel and the ErrorLevel parameter of DebugPrint()
//
-#define DEBUG_INIT 0x00000001 // Initialization
-#define DEBUG_WARN 0x00000002 // Warnings
-#define DEBUG_LOAD 0x00000004 // Load events
-#define DEBUG_FS 0x00000008 // EFI File system
-#define DEBUG_POOL 0x00000010 // Alloc & Free (pool)
-#define DEBUG_PAGE 0x00000020 // Alloc & Free (page)
-#define DEBUG_INFO 0x00000040 // Informational debug messages
-#define DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers
-#define DEBUG_VARIABLE 0x00000100 // Variable
-#define DEBUG_BM 0x00000400 // Boot Manager
-#define DEBUG_BLKIO 0x00001000 // BlkIo Driver
-#define DEBUG_NET 0x00004000 // Network Io Driver
-#define DEBUG_UNDI 0x00010000 // UNDI Driver
-#define DEBUG_LOADFILE 0x00020000 // LoadFile
-#define DEBUG_EVENT 0x00080000 // Event messages
-#define DEBUG_GCD 0x00100000 // Global Coherency Database changes
-#define DEBUG_CACHE 0x00200000 // Memory range cachability changes
-#define DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may
- // significantly impact boot performance
-#define DEBUG_ERROR 0x80000000 // Error
+#define DEBUG_INIT 0x00000001 // Initialization
+#define DEBUG_WARN 0x00000002 // Warnings
+#define DEBUG_LOAD 0x00000004 // Load events
+#define DEBUG_FS 0x00000008 // EFI File system
+#define DEBUG_POOL 0x00000010 // Alloc & Free (pool)
+#define DEBUG_PAGE 0x00000020 // Alloc & Free (page)
+#define DEBUG_INFO 0x00000040 // Informational debug messages
+#define DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers
+#define DEBUG_VARIABLE 0x00000100 // Variable
+#define DEBUG_BM 0x00000400 // Boot Manager
+#define DEBUG_BLKIO 0x00001000 // BlkIo Driver
+#define DEBUG_NET 0x00004000 // Network Io Driver
+#define DEBUG_UNDI 0x00010000 // UNDI Driver
+#define DEBUG_LOADFILE 0x00020000 // LoadFile
+#define DEBUG_EVENT 0x00080000 // Event messages
+#define DEBUG_GCD 0x00100000 // Global Coherency Database changes
+#define DEBUG_CACHE 0x00200000 // Memory range cachability changes
+#define DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may
+ // significantly impact boot performance
+#define DEBUG_MANAGEABILITY 0x00800000 // Detailed debug and payload message of manageability
+ // related modules, such Redfish, IPMI, MCTP and etc.
+#define DEBUG_ERROR 0x80000000 // Error
//
// Aliases of debug message mask bits
@@ -129,7 +131,6 @@ DebugPrint (
...
);
-
/**
Prints a debug message to the debug output device if the specified
error level is enabled.
@@ -148,12 +149,11 @@ DebugPrint (
VOID
EFIAPI
DebugVPrint (
- IN UINTN ErrorLevel,
- IN CONST CHAR8 *Format,
- IN VA_LIST VaListMarker
+ IN UINTN ErrorLevel,
+ IN CONST CHAR8 *Format,
+ IN VA_LIST VaListMarker
);
-
/**
Prints a debug message to the debug output device if the specified
error level is enabled.
@@ -174,12 +174,11 @@ DebugVPrint (
VOID
EFIAPI
DebugBPrint (
- IN UINTN ErrorLevel,
- IN CONST CHAR8 *Format,
- IN BASE_LIST BaseListMarker
+ IN UINTN ErrorLevel,
+ IN CONST CHAR8 *Format,
+ IN BASE_LIST BaseListMarker
);
-
/**
Prints an assert message containing a filename, line number, and description.
This may be followed by a breakpoint or a dead loop.
@@ -209,7 +208,6 @@ DebugAssert (
IN CONST CHAR8 *Description
);
-
/**
Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.
@@ -232,7 +230,6 @@ DebugClearMemory (
IN UINTN Length
);
-
/**
Returns TRUE if ASSERT() macros are enabled.
@@ -249,7 +246,6 @@ DebugAssertEnabled (
VOID
);
-
/**
Returns TRUE if DEBUG() macros are enabled.
@@ -266,7 +262,6 @@ DebugPrintEnabled (
VOID
);
-
/**
Returns TRUE if DEBUG_CODE() macros are enabled.
@@ -283,7 +278,6 @@ DebugCodeEnabled (
VOID
);
-
/**
Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.
@@ -312,7 +306,7 @@ DebugClearMemoryEnabled (
BOOLEAN
EFIAPI
DebugPrintLevelEnabled (
- IN CONST UINTN ErrorLevel
+ IN CONST UINTN ErrorLevel
);
/**
@@ -324,13 +318,45 @@ DebugPrintLevelEnabled (
@param Expression Boolean expression that evaluated to FALSE
**/
-#if defined(__KLOCWORK__) || defined(__COVERITY__)
- #define _ASSERT(Expression) do { if (!(Expression)) abort(); } while (0)
-#else
- #ifdef LITE_PRINT
- #define _ASSERT(Expression) DebugAssert (gEfiCallerBaseName, __LINE__, "")
+#if defined (EDKII_UNIT_TEST_FRAMEWORK_ENABLED)
+
+/**
+ Unit test library replacement for DebugAssert() in DebugLib.
+
+ If FileName is NULL, then a string of "(NULL) Filename" is printed.
+ If Description is NULL, then a string of "(NULL) Description" is printed.
+
+ @param FileName The pointer to the name of the source file that generated the assert condition.
+ @param LineNumber The line number in the source file that generated the assert condition
+ @param Description The pointer to the description of the assert condition.
+
+**/
+VOID
+EFIAPI
+UnitTestDebugAssert (
+ IN CONST CHAR8 *FileName,
+ IN UINTN LineNumber,
+ IN CONST CHAR8 *Description
+ );
+
+ #if defined (_ASSERT)
+ #undef _ASSERT
+ #endif
+ #if defined(__KLOCWORK__) || defined(__COVERITY__)
+ #define ASSERT(Expression) _ASSERT (Expression)
+ #elif defined (__clang__) && defined (__FILE_NAME__)
+ #define _ASSERT(Expression) UnitTestDebugAssert (__FILE_NAME__, DEBUG_LINE_NUMBER, DEBUG_EXPRESSION_STRING (Expression))
#else
- #define _ASSERT(Expression) DebugAssert (__FILE__, __LINE__, #Expression)
+ #define _ASSERT(Expression) UnitTestDebugAssert (__FILE__, DEBUG_LINE_NUMBER, DEBUG_EXPRESSION_STRING (Expression))
+ #endif
+#else
+
+ #if defined(__KLOCWORK__) || defined(__COVERITY__)
+ #define ASSERT(Expression) _ASSERT (Expression)
+ #elif defined (__clang__) && defined (__FILE_NAME__)
+ #define _ASSERT(Expression) DebugAssert (__FILE_NAME__, DEBUG_LINE_NUMBER, DEBUG_EXPRESSION_STRING (Expression))
+ #else
+ #define _ASSERT(Expression) DebugAssert (__FILE__, DEBUG_LINE_NUMBER, DEBUG_EXPRESSION_STRING (Expression))
#endif
#endif
@@ -347,16 +373,16 @@ DebugPrintLevelEnabled (
**/
-#if !defined(MDE_CPU_EBC) && (!defined (_MSC_VER) || _MSC_VER > 1400)
- #define _DEBUG_PRINT(PrintLevel, ...) \
+#if !defined (MDE_CPU_EBC) && (!defined (_MSC_VER) || _MSC_VER > 1400)
+#define _DEBUG_PRINT(PrintLevel, ...) \
do { \
if (DebugPrintLevelEnabled (PrintLevel)) { \
DebugPrint (PrintLevel, ##__VA_ARGS__); \
} \
} while (FALSE)
- #define _DEBUG(Expression) _DEBUG_PRINT Expression
+#define _DEBUG(Expression) _DEBUG_PRINT Expression
#else
-#define _DEBUG(Expression) DebugPrint Expression
+#define _DEBUG(Expression) DebugPrint Expression
#endif
/**
@@ -371,22 +397,18 @@ DebugPrintLevelEnabled (
@param Expression Boolean expression.
**/
-#if defined(__KLOCWORK__) || defined(__COVERITY__)
- #define ASSERT(Expression) _ASSERT (Expression)
+#if !defined (MDEPKG_NDEBUG)
+#define ASSERT(Expression) \
+ do { \
+ if (DebugAssertEnabled ()) { \
+ if (!(Expression)) { \
+ _ASSERT (Expression); \
+ ANALYZER_UNREACHABLE (); \
+ } \
+ } \
+ } while (FALSE)
#else
- #if !defined(MDEPKG_NDEBUG)
- #define ASSERT(Expression) \
- do { \
- if (DebugAssertEnabled ()) { \
- if (!(Expression)) { \
- _ASSERT (Expression); \
- ANALYZER_UNREACHABLE (); \
- } \
- } \
- } while (FALSE)
- #else
- #define ASSERT(Expression)
- #endif
+#define ASSERT(Expression)
#endif
/**
@@ -401,15 +423,15 @@ DebugPrintLevelEnabled (
**/
-#if !defined(MDEPKG_NDEBUG)
- #define DEBUG(Expression) \
+#if !defined (MDEPKG_NDEBUG)
+#define DEBUG(Expression) \
do { \
if (DebugPrintEnabled ()) { \
_DEBUG (Expression); \
} \
} while (FALSE)
#else
- #define DEBUG(Expression)
+#define DEBUG(Expression)
#endif
/**
@@ -424,8 +446,8 @@ DebugPrintLevelEnabled (
@param StatusParameter EFI_STATUS value to evaluate.
**/
-#if !defined(MDEPKG_NDEBUG)
- #define ASSERT_EFI_ERROR(StatusParameter) \
+#if !defined (MDEPKG_NDEBUG)
+#define ASSERT_EFI_ERROR(StatusParameter) \
do { \
if (DebugAssertEnabled ()) { \
if (EFI_ERROR (StatusParameter)) { \
@@ -435,7 +457,7 @@ DebugPrintLevelEnabled (
} \
} while (FALSE)
#else
- #define ASSERT_EFI_ERROR(StatusParameter)
+#define ASSERT_EFI_ERROR(StatusParameter)
#endif
/**
@@ -450,8 +472,8 @@ DebugPrintLevelEnabled (
@param StatusParameter RETURN_STATUS value to evaluate.
**/
-#if !defined(MDEPKG_NDEBUG)
- #define ASSERT_RETURN_ERROR(StatusParameter) \
+#if !defined (MDEPKG_NDEBUG)
+#define ASSERT_RETURN_ERROR(StatusParameter) \
do { \
if (DebugAssertEnabled ()) { \
if (RETURN_ERROR (StatusParameter)) { \
@@ -462,7 +484,7 @@ DebugPrintLevelEnabled (
} \
} while (FALSE)
#else
- #define ASSERT_RETURN_ERROR(StatusParameter)
+#define ASSERT_RETURN_ERROR(StatusParameter)
#endif
/**
@@ -487,8 +509,8 @@ DebugPrintLevelEnabled (
@param Guid The pointer to a protocol GUID.
**/
-#if !defined(MDEPKG_NDEBUG)
- #define ASSERT_PROTOCOL_ALREADY_INSTALLED(Handle, Guid) \
+#if !defined (MDEPKG_NDEBUG)
+#define ASSERT_PROTOCOL_ALREADY_INSTALLED(Handle, Guid) \
do { \
if (DebugAssertEnabled ()) { \
VOID *Instance; \
@@ -505,7 +527,7 @@ DebugPrintLevelEnabled (
} \
} while (FALSE)
#else
- #define ASSERT_PROTOCOL_ALREADY_INSTALLED(Handle, Guid)
+#define ASSERT_PROTOCOL_ALREADY_INSTALLED(Handle, Guid)
#endif
/**
@@ -519,7 +541,6 @@ DebugPrintLevelEnabled (
**/
#define DEBUG_CODE_BEGIN() do { if (DebugCodeEnabled ()) { UINT8 __DebugCodeLocal
-
/**
The macro that marks the end of debug source code.
@@ -529,8 +550,7 @@ DebugPrintLevelEnabled (
are not included in a module.
**/
-#define DEBUG_CODE_END() __DebugCodeLocal = 0; __DebugCodeLocal++; } } while (FALSE)
-
+#define DEBUG_CODE_END() __DebugCodeLocal = 0; __DebugCodeLocal++; } } while (FALSE)
/**
The macro that declares a section of debug source code.
@@ -545,7 +565,6 @@ DebugPrintLevelEnabled (
Expression \
DEBUG_CODE_END ()
-
/**
The macro that calls DebugClearMemory() to clear a buffer to a default value.
@@ -563,7 +582,6 @@ DebugPrintLevelEnabled (
} \
} while (FALSE)
-
/**
Macro that calls DebugAssert() if the containing record does not have a
matching signature. If the signatures matches, then a pointer to the data
@@ -608,16 +626,14 @@ DebugPrintLevelEnabled (
**/
#if defined(__KLOCWORK__) || defined(__COVERITY__)
#define CR(Record, TYPE, Field, TestSignature) BASE_CR(Record, TYPE, Field)
+#elif !defined (MDEPKG_NDEBUG)
+ #define CR(Record, TYPE, Field, TestSignature) \
+ (DebugAssertEnabled () && (BASE_CR (Record, TYPE, Field)->Signature != TestSignature)) ? \
+ (TYPE *) (_ASSERT (CR has Bad Signature), Record) : \
+ BASE_CR (Record, TYPE, Field)
#else
- #if !defined(MDEPKG_NDEBUG)
- #define CR(Record, TYPE, Field, TestSignature) \
- (DebugAssertEnabled () && (BASE_CR (Record, TYPE, Field)->Signature != TestSignature)) ? \
- (TYPE *) (_ASSERT (CR has Bad Signature), Record) : \
- BASE_CR(Record, TYPE, Field)
- #else
- #define CR(Record, TYPE, Field, TestSignature) \
- BASE_CR(Record, TYPE, Field)
- #endif
+ #define CR(Record, TYPE, Field, TestSignature) \
+ BASE_CR (Record, TYPE, Field)
#endif
#endif
diff --git a/MdePkg/Include/Library/DebugPrintErrorLevelLib.h b/MdePkg/Include/Library/DebugPrintErrorLevelLib.h
index f57097f8..bddf2252 100644
--- a/MdePkg/Include/Library/DebugPrintErrorLevelLib.h
+++ b/MdePkg/Include/Library/DebugPrintErrorLevelLib.h
@@ -5,6 +5,7 @@
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
+
#ifndef _DEBUG_PRINT_ERROR_LEVEL_LIB_H_
#define _DEBUG_PRINT_ERROR_LEVEL_LIB_H_
@@ -34,4 +35,5 @@ EFIAPI
SetDebugPrintErrorLevel (
UINT32 ErrorLevel
);
+
#endif
diff --git a/MdePkg/Include/Library/HobLib.h b/MdePkg/Include/Library/HobLib.h
index b1adb527..da8a905d 100644
--- a/MdePkg/Include/Library/HobLib.h
+++ b/MdePkg/Include/Library/HobLib.h
@@ -58,8 +58,8 @@ GetHobList (
VOID *
EFIAPI
GetNextHob (
- IN UINT16 Type,
- IN CONST VOID *HobStart
+ IN UINT16 Type,
+ IN CONST VOID *HobStart
);
/**
@@ -78,7 +78,7 @@ GetNextHob (
VOID *
EFIAPI
GetFirstHob (
- IN UINT16 Type
+ IN UINT16 Type
);
/**
@@ -106,8 +106,8 @@ GetFirstHob (
VOID *
EFIAPI
GetNextGuidHob (
- IN CONST EFI_GUID *Guid,
- IN CONST VOID *HobStart
+ IN CONST EFI_GUID *Guid,
+ IN CONST VOID *HobStart
);
/**
@@ -131,7 +131,7 @@ GetNextGuidHob (
VOID *
EFIAPI
GetFirstGuidHob (
- IN CONST EFI_GUID *Guid
+ IN CONST EFI_GUID *Guid
);
/**
@@ -172,10 +172,10 @@ GetBootModeHob (
VOID
EFIAPI
BuildModuleHob (
- IN CONST EFI_GUID *ModuleName,
- IN EFI_PHYSICAL_ADDRESS MemoryAllocationModule,
- IN UINT64 ModuleLength,
- IN EFI_PHYSICAL_ADDRESS EntryPoint
+ IN CONST EFI_GUID *ModuleName,
+ IN EFI_PHYSICAL_ADDRESS MemoryAllocationModule,
+ IN UINT64 ModuleLength,
+ IN EFI_PHYSICAL_ADDRESS EntryPoint
);
/**
@@ -253,8 +253,8 @@ BuildResourceDescriptorHob (
VOID *
EFIAPI
BuildGuidHob (
- IN CONST EFI_GUID *Guid,
- IN UINTN DataLength
+ IN CONST EFI_GUID *Guid,
+ IN UINTN DataLength
);
/**
@@ -285,9 +285,9 @@ BuildGuidHob (
VOID *
EFIAPI
BuildGuidDataHob (
- IN CONST EFI_GUID *Guid,
- IN VOID *Data,
- IN UINTN DataLength
+ IN CONST EFI_GUID *Guid,
+ IN VOID *Data,
+ IN UINTN DataLength
);
/**
@@ -307,8 +307,8 @@ BuildGuidDataHob (
VOID
EFIAPI
BuildFvHob (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
);
/**
@@ -330,10 +330,10 @@ BuildFvHob (
VOID
EFIAPI
BuildFv2Hob (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN CONST EFI_GUID *FvName,
- IN CONST EFI_GUID *FileName
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN CONST EFI_GUID *FvName,
+ IN CONST EFI_GUID *FileName
);
/**
@@ -360,12 +360,12 @@ BuildFv2Hob (
VOID
EFIAPI
BuildFv3Hob (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT32 AuthenticationStatus,
- IN BOOLEAN ExtractedFv,
- IN CONST EFI_GUID *FvName, OPTIONAL
- IN CONST EFI_GUID *FileName OPTIONAL
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT32 AuthenticationStatus,
+ IN BOOLEAN ExtractedFv,
+ IN CONST EFI_GUID *FvName OPTIONAL,
+ IN CONST EFI_GUID *FileName OPTIONAL
);
/**
@@ -385,8 +385,8 @@ BuildFv3Hob (
VOID
EFIAPI
BuildCvHob (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
);
/**
@@ -405,8 +405,8 @@ BuildCvHob (
VOID
EFIAPI
BuildCpuHob (
- IN UINT8 SizeOfMemorySpace,
- IN UINT8 SizeOfIoSpace
+ IN UINT8 SizeOfMemorySpace,
+ IN UINT8 SizeOfIoSpace
);
/**
@@ -425,8 +425,8 @@ BuildCpuHob (
VOID
EFIAPI
BuildStackHob (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
);
/**
@@ -446,9 +446,9 @@ BuildStackHob (
VOID
EFIAPI
BuildBspStoreHob (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN EFI_MEMORY_TYPE MemoryType
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN EFI_MEMORY_TYPE MemoryType
);
/**
@@ -468,9 +468,9 @@ BuildBspStoreHob (
VOID
EFIAPI
BuildMemoryAllocationHob (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN EFI_MEMORY_TYPE MemoryType
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN EFI_MEMORY_TYPE MemoryType
);
/**
diff --git a/MdePkg/Include/Library/IoLib.h b/MdePkg/Include/Library/IoLib.h
index d0ffe98e..18e20df9 100644
--- a/MdePkg/Include/Library/IoLib.h
+++ b/MdePkg/Include/Library/IoLib.h
@@ -26,7 +26,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
-#define IO_LIB_ADDRESS(Segment,Port) \
+#define IO_LIB_ADDRESS(Segment, Port) \
( ((Port) & 0xffff) | (((Segment) & 0xffff) << 16) )
/**
@@ -46,7 +46,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
UINT8
EFIAPI
IoRead8 (
- IN UINTN Port
+ IN UINTN Port
);
/**
@@ -67,8 +67,8 @@ IoRead8 (
UINT8
EFIAPI
IoWrite8 (
- IN UINTN Port,
- IN UINT8 Value
+ IN UINTN Port,
+ IN UINT8 Value
);
/**
@@ -91,9 +91,9 @@ IoWrite8 (
VOID
EFIAPI
IoReadFifo8 (
- IN UINTN Port,
- IN UINTN Count,
- OUT VOID *Buffer
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
);
/**
@@ -116,9 +116,9 @@ IoReadFifo8 (
VOID
EFIAPI
IoWriteFifo8 (
- IN UINTN Port,
- IN UINTN Count,
- IN VOID *Buffer
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
);
/**
@@ -142,8 +142,8 @@ IoWriteFifo8 (
UINT8
EFIAPI
IoOr8 (
- IN UINTN Port,
- IN UINT8 OrData
+ IN UINTN Port,
+ IN UINT8 OrData
);
/**
@@ -167,8 +167,8 @@ IoOr8 (
UINT8
EFIAPI
IoAnd8 (
- IN UINTN Port,
- IN UINT8 AndData
+ IN UINTN Port,
+ IN UINT8 AndData
);
/**
@@ -194,9 +194,9 @@ IoAnd8 (
UINT8
EFIAPI
IoAndThenOr8 (
- IN UINTN Port,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINTN Port,
+ IN UINT8 AndData,
+ IN UINT8 OrData
);
/**
@@ -222,9 +222,9 @@ IoAndThenOr8 (
UINT8
EFIAPI
IoBitFieldRead8 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
/**
@@ -253,10 +253,10 @@ IoBitFieldRead8 (
UINT8
EFIAPI
IoBitFieldWrite8 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 Value
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
);
/**
@@ -288,10 +288,10 @@ IoBitFieldWrite8 (
UINT8
EFIAPI
IoBitFieldOr8 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 OrData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
);
/**
@@ -323,10 +323,10 @@ IoBitFieldOr8 (
UINT8
EFIAPI
IoBitFieldAnd8 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
);
/**
@@ -362,11 +362,11 @@ IoBitFieldAnd8 (
UINT8
EFIAPI
IoBitFieldAndThenOr8 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
);
/**
@@ -387,7 +387,7 @@ IoBitFieldAndThenOr8 (
UINT16
EFIAPI
IoRead16 (
- IN UINTN Port
+ IN UINTN Port
);
/**
@@ -409,8 +409,8 @@ IoRead16 (
UINT16
EFIAPI
IoWrite16 (
- IN UINTN Port,
- IN UINT16 Value
+ IN UINTN Port,
+ IN UINT16 Value
);
/**
@@ -433,9 +433,9 @@ IoWrite16 (
VOID
EFIAPI
IoReadFifo16 (
- IN UINTN Port,
- IN UINTN Count,
- OUT VOID *Buffer
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
);
/**
@@ -458,9 +458,9 @@ IoReadFifo16 (
VOID
EFIAPI
IoWriteFifo16 (
- IN UINTN Port,
- IN UINTN Count,
- IN VOID *Buffer
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
);
/**
@@ -485,8 +485,8 @@ IoWriteFifo16 (
UINT16
EFIAPI
IoOr16 (
- IN UINTN Port,
- IN UINT16 OrData
+ IN UINTN Port,
+ IN UINT16 OrData
);
/**
@@ -511,8 +511,8 @@ IoOr16 (
UINT16
EFIAPI
IoAnd16 (
- IN UINTN Port,
- IN UINT16 AndData
+ IN UINTN Port,
+ IN UINT16 AndData
);
/**
@@ -539,9 +539,9 @@ IoAnd16 (
UINT16
EFIAPI
IoAndThenOr16 (
- IN UINTN Port,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINTN Port,
+ IN UINT16 AndData,
+ IN UINT16 OrData
);
/**
@@ -568,9 +568,9 @@ IoAndThenOr16 (
UINT16
EFIAPI
IoBitFieldRead16 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
/**
@@ -601,10 +601,10 @@ IoBitFieldRead16 (
UINT16
EFIAPI
IoBitFieldWrite16 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 Value
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
);
/**
@@ -637,10 +637,10 @@ IoBitFieldWrite16 (
UINT16
EFIAPI
IoBitFieldOr16 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 OrData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
);
/**
@@ -673,10 +673,10 @@ IoBitFieldOr16 (
UINT16
EFIAPI
IoBitFieldAnd16 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
);
/**
@@ -713,11 +713,11 @@ IoBitFieldAnd16 (
UINT16
EFIAPI
IoBitFieldAndThenOr16 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
);
/**
@@ -738,7 +738,7 @@ IoBitFieldAndThenOr16 (
UINT32
EFIAPI
IoRead32 (
- IN UINTN Port
+ IN UINTN Port
);
/**
@@ -760,8 +760,8 @@ IoRead32 (
UINT32
EFIAPI
IoWrite32 (
- IN UINTN Port,
- IN UINT32 Value
+ IN UINTN Port,
+ IN UINT32 Value
);
/**
@@ -784,9 +784,9 @@ IoWrite32 (
VOID
EFIAPI
IoReadFifo32 (
- IN UINTN Port,
- IN UINTN Count,
- OUT VOID *Buffer
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
);
/**
@@ -809,9 +809,9 @@ IoReadFifo32 (
VOID
EFIAPI
IoWriteFifo32 (
- IN UINTN Port,
- IN UINTN Count,
- IN VOID *Buffer
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
);
/**
@@ -836,8 +836,8 @@ IoWriteFifo32 (
UINT32
EFIAPI
IoOr32 (
- IN UINTN Port,
- IN UINT32 OrData
+ IN UINTN Port,
+ IN UINT32 OrData
);
/**
@@ -862,8 +862,8 @@ IoOr32 (
UINT32
EFIAPI
IoAnd32 (
- IN UINTN Port,
- IN UINT32 AndData
+ IN UINTN Port,
+ IN UINT32 AndData
);
/**
@@ -890,9 +890,9 @@ IoAnd32 (
UINT32
EFIAPI
IoAndThenOr32 (
- IN UINTN Port,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINTN Port,
+ IN UINT32 AndData,
+ IN UINT32 OrData
);
/**
@@ -919,9 +919,9 @@ IoAndThenOr32 (
UINT32
EFIAPI
IoBitFieldRead32 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
/**
@@ -952,10 +952,10 @@ IoBitFieldRead32 (
UINT32
EFIAPI
IoBitFieldWrite32 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
);
/**
@@ -988,10 +988,10 @@ IoBitFieldWrite32 (
UINT32
EFIAPI
IoBitFieldOr32 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
);
/**
@@ -1024,10 +1024,10 @@ IoBitFieldOr32 (
UINT32
EFIAPI
IoBitFieldAnd32 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
);
/**
@@ -1064,11 +1064,11 @@ IoBitFieldAnd32 (
UINT32
EFIAPI
IoBitFieldAndThenOr32 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
);
/**
@@ -1089,7 +1089,7 @@ IoBitFieldAndThenOr32 (
UINT64
EFIAPI
IoRead64 (
- IN UINTN Port
+ IN UINTN Port
);
/**
@@ -1111,8 +1111,8 @@ IoRead64 (
UINT64
EFIAPI
IoWrite64 (
- IN UINTN Port,
- IN UINT64 Value
+ IN UINTN Port,
+ IN UINT64 Value
);
/**
@@ -1137,8 +1137,8 @@ IoWrite64 (
UINT64
EFIAPI
IoOr64 (
- IN UINTN Port,
- IN UINT64 OrData
+ IN UINTN Port,
+ IN UINT64 OrData
);
/**
@@ -1163,8 +1163,8 @@ IoOr64 (
UINT64
EFIAPI
IoAnd64 (
- IN UINTN Port,
- IN UINT64 AndData
+ IN UINTN Port,
+ IN UINT64 AndData
);
/**
@@ -1191,9 +1191,9 @@ IoAnd64 (
UINT64
EFIAPI
IoAndThenOr64 (
- IN UINTN Port,
- IN UINT64 AndData,
- IN UINT64 OrData
+ IN UINTN Port,
+ IN UINT64 AndData,
+ IN UINT64 OrData
);
/**
@@ -1220,9 +1220,9 @@ IoAndThenOr64 (
UINT64
EFIAPI
IoBitFieldRead64 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
/**
@@ -1253,10 +1253,10 @@ IoBitFieldRead64 (
UINT64
EFIAPI
IoBitFieldWrite64 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 Value
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 Value
);
/**
@@ -1289,10 +1289,10 @@ IoBitFieldWrite64 (
UINT64
EFIAPI
IoBitFieldOr64 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 OrData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 OrData
);
/**
@@ -1325,10 +1325,10 @@ IoBitFieldOr64 (
UINT64
EFIAPI
IoBitFieldAnd64 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 AndData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData
);
/**
@@ -1365,11 +1365,11 @@ IoBitFieldAnd64 (
UINT64
EFIAPI
IoBitFieldAndThenOr64 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 AndData,
- IN UINT64 OrData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData,
+ IN UINT64 OrData
);
/**
@@ -1389,7 +1389,7 @@ IoBitFieldAndThenOr64 (
UINT8
EFIAPI
MmioRead8 (
- IN UINTN Address
+ IN UINTN Address
);
/**
@@ -1410,8 +1410,8 @@ MmioRead8 (
UINT8
EFIAPI
MmioWrite8 (
- IN UINTN Address,
- IN UINT8 Value
+ IN UINTN Address,
+ IN UINT8 Value
);
/**
@@ -1435,8 +1435,8 @@ MmioWrite8 (
UINT8
EFIAPI
MmioOr8 (
- IN UINTN Address,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINT8 OrData
);
/**
@@ -1460,8 +1460,8 @@ MmioOr8 (
UINT8
EFIAPI
MmioAnd8 (
- IN UINTN Address,
- IN UINT8 AndData
+ IN UINTN Address,
+ IN UINT8 AndData
);
/**
@@ -1488,9 +1488,9 @@ MmioAnd8 (
UINT8
EFIAPI
MmioAndThenOr8 (
- IN UINTN Address,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
);
/**
@@ -1516,9 +1516,9 @@ MmioAndThenOr8 (
UINT8
EFIAPI
MmioBitFieldRead8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
/**
@@ -1547,10 +1547,10 @@ MmioBitFieldRead8 (
UINT8
EFIAPI
MmioBitFieldWrite8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
);
/**
@@ -1583,10 +1583,10 @@ MmioBitFieldWrite8 (
UINT8
EFIAPI
MmioBitFieldOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
);
/**
@@ -1619,10 +1619,10 @@ MmioBitFieldOr8 (
UINT8
EFIAPI
MmioBitFieldAnd8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
);
/**
@@ -1658,11 +1658,11 @@ MmioBitFieldAnd8 (
UINT8
EFIAPI
MmioBitFieldAndThenOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
);
/**
@@ -1683,7 +1683,7 @@ MmioBitFieldAndThenOr8 (
UINT16
EFIAPI
MmioRead16 (
- IN UINTN Address
+ IN UINTN Address
);
/**
@@ -1705,8 +1705,8 @@ MmioRead16 (
UINT16
EFIAPI
MmioWrite16 (
- IN UINTN Address,
- IN UINT16 Value
+ IN UINTN Address,
+ IN UINT16 Value
);
/**
@@ -1731,8 +1731,8 @@ MmioWrite16 (
UINT16
EFIAPI
MmioOr16 (
- IN UINTN Address,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINT16 OrData
);
/**
@@ -1757,8 +1757,8 @@ MmioOr16 (
UINT16
EFIAPI
MmioAnd16 (
- IN UINTN Address,
- IN UINT16 AndData
+ IN UINTN Address,
+ IN UINT16 AndData
);
/**
@@ -1785,9 +1785,9 @@ MmioAnd16 (
UINT16
EFIAPI
MmioAndThenOr16 (
- IN UINTN Address,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
);
/**
@@ -1814,9 +1814,9 @@ MmioAndThenOr16 (
UINT16
EFIAPI
MmioBitFieldRead16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
/**
@@ -1846,10 +1846,10 @@ MmioBitFieldRead16 (
UINT16
EFIAPI
MmioBitFieldWrite16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
);
/**
@@ -1883,10 +1883,10 @@ MmioBitFieldWrite16 (
UINT16
EFIAPI
MmioBitFieldOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
);
/**
@@ -1920,10 +1920,10 @@ MmioBitFieldOr16 (
UINT16
EFIAPI
MmioBitFieldAnd16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
);
/**
@@ -1960,11 +1960,11 @@ MmioBitFieldAnd16 (
UINT16
EFIAPI
MmioBitFieldAndThenOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
);
/**
@@ -1985,7 +1985,7 @@ MmioBitFieldAndThenOr16 (
UINT32
EFIAPI
MmioRead32 (
- IN UINTN Address
+ IN UINTN Address
);
/**
@@ -2007,8 +2007,8 @@ MmioRead32 (
UINT32
EFIAPI
MmioWrite32 (
- IN UINTN Address,
- IN UINT32 Value
+ IN UINTN Address,
+ IN UINT32 Value
);
/**
@@ -2033,8 +2033,8 @@ MmioWrite32 (
UINT32
EFIAPI
MmioOr32 (
- IN UINTN Address,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINT32 OrData
);
/**
@@ -2059,8 +2059,8 @@ MmioOr32 (
UINT32
EFIAPI
MmioAnd32 (
- IN UINTN Address,
- IN UINT32 AndData
+ IN UINTN Address,
+ IN UINT32 AndData
);
/**
@@ -2087,9 +2087,9 @@ MmioAnd32 (
UINT32
EFIAPI
MmioAndThenOr32 (
- IN UINTN Address,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
);
/**
@@ -2116,9 +2116,9 @@ MmioAndThenOr32 (
UINT32
EFIAPI
MmioBitFieldRead32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
/**
@@ -2148,10 +2148,10 @@ MmioBitFieldRead32 (
UINT32
EFIAPI
MmioBitFieldWrite32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
);
/**
@@ -2185,10 +2185,10 @@ MmioBitFieldWrite32 (
UINT32
EFIAPI
MmioBitFieldOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
);
/**
@@ -2222,10 +2222,10 @@ MmioBitFieldOr32 (
UINT32
EFIAPI
MmioBitFieldAnd32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
);
/**
@@ -2262,11 +2262,11 @@ MmioBitFieldAnd32 (
UINT32
EFIAPI
MmioBitFieldAndThenOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
);
/**
@@ -2287,7 +2287,7 @@ MmioBitFieldAndThenOr32 (
UINT64
EFIAPI
MmioRead64 (
- IN UINTN Address
+ IN UINTN Address
);
/**
@@ -2307,8 +2307,8 @@ MmioRead64 (
UINT64
EFIAPI
MmioWrite64 (
- IN UINTN Address,
- IN UINT64 Value
+ IN UINTN Address,
+ IN UINT64 Value
);
/**
@@ -2333,8 +2333,8 @@ MmioWrite64 (
UINT64
EFIAPI
MmioOr64 (
- IN UINTN Address,
- IN UINT64 OrData
+ IN UINTN Address,
+ IN UINT64 OrData
);
/**
@@ -2359,8 +2359,8 @@ MmioOr64 (
UINT64
EFIAPI
MmioAnd64 (
- IN UINTN Address,
- IN UINT64 AndData
+ IN UINTN Address,
+ IN UINT64 AndData
);
/**
@@ -2387,9 +2387,9 @@ MmioAnd64 (
UINT64
EFIAPI
MmioAndThenOr64 (
- IN UINTN Address,
- IN UINT64 AndData,
- IN UINT64 OrData
+ IN UINTN Address,
+ IN UINT64 AndData,
+ IN UINT64 OrData
);
/**
@@ -2416,9 +2416,9 @@ MmioAndThenOr64 (
UINT64
EFIAPI
MmioBitFieldRead64 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
/**
@@ -2448,10 +2448,10 @@ MmioBitFieldRead64 (
UINT64
EFIAPI
MmioBitFieldWrite64 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 Value
);
/**
@@ -2485,10 +2485,10 @@ MmioBitFieldWrite64 (
UINT64
EFIAPI
MmioBitFieldOr64 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 OrData
);
/**
@@ -2522,10 +2522,10 @@ MmioBitFieldOr64 (
UINT64
EFIAPI
MmioBitFieldAnd64 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData
);
/**
@@ -2562,11 +2562,11 @@ MmioBitFieldAnd64 (
UINT64
EFIAPI
MmioBitFieldAndThenOr64 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 AndData,
- IN UINT64 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData,
+ IN UINT64 OrData
);
/**
@@ -2590,9 +2590,9 @@ MmioBitFieldAndThenOr64 (
UINT8 *
EFIAPI
MmioReadBuffer8 (
- IN UINTN StartAddress,
- IN UINTN Length,
- OUT UINT8 *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ OUT UINT8 *Buffer
);
/**
@@ -2620,9 +2620,9 @@ MmioReadBuffer8 (
UINT16 *
EFIAPI
MmioReadBuffer16 (
- IN UINTN StartAddress,
- IN UINTN Length,
- OUT UINT16 *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ OUT UINT16 *Buffer
);
/**
@@ -2650,9 +2650,9 @@ MmioReadBuffer16 (
UINT32 *
EFIAPI
MmioReadBuffer32 (
- IN UINTN StartAddress,
- IN UINTN Length,
- OUT UINT32 *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ OUT UINT32 *Buffer
);
/**
@@ -2680,9 +2680,9 @@ MmioReadBuffer32 (
UINT64 *
EFIAPI
MmioReadBuffer64 (
- IN UINTN StartAddress,
- IN UINTN Length,
- OUT UINT64 *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ OUT UINT64 *Buffer
);
/**
@@ -2706,9 +2706,9 @@ MmioReadBuffer64 (
UINT8 *
EFIAPI
MmioWriteBuffer8 (
- IN UINTN StartAddress,
- IN UINTN Length,
- IN CONST UINT8 *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ IN CONST UINT8 *Buffer
);
/**
@@ -2737,9 +2737,9 @@ MmioWriteBuffer8 (
UINT16 *
EFIAPI
MmioWriteBuffer16 (
- IN UINTN StartAddress,
- IN UINTN Length,
- IN CONST UINT16 *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ IN CONST UINT16 *Buffer
);
/**
@@ -2768,9 +2768,9 @@ MmioWriteBuffer16 (
UINT32 *
EFIAPI
MmioWriteBuffer32 (
- IN UINTN StartAddress,
- IN UINTN Length,
- IN CONST UINT32 *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ IN CONST UINT32 *Buffer
);
/**
@@ -2799,11 +2799,9 @@ MmioWriteBuffer32 (
UINT64 *
EFIAPI
MmioWriteBuffer64 (
- IN UINTN StartAddress,
- IN UINTN Length,
- IN CONST UINT64 *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ IN CONST UINT64 *Buffer
);
-
#endif
-
diff --git a/MdePkg/Include/Library/MemoryAllocationLib.h b/MdePkg/Include/Library/MemoryAllocationLib.h
index 14efb568..fd364336 100644
--- a/MdePkg/Include/Library/MemoryAllocationLib.h
+++ b/MdePkg/Include/Library/MemoryAllocationLib.h
@@ -481,7 +481,7 @@ ReallocateReservedPool (
VOID
EFIAPI
FreePool (
- IN VOID *Buffer
+ IN VOID *Buffer
);
#endif
diff --git a/MdePkg/Include/Library/PcdLib.h b/MdePkg/Include/Library/PcdLib.h
index 9a8cb70c..27f2e5a5 100644
--- a/MdePkg/Include/Library/PcdLib.h
+++ b/MdePkg/Include/Library/PcdLib.h
@@ -22,7 +22,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef __PCD_LIB_H__
#define __PCD_LIB_H__
-
/**
Retrieves a token number based on a token name.
@@ -34,8 +33,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return The token number associated with the PCD.
**/
-#define PcdToken(TokenName) _PCD_TOKEN_##TokenName
-
+#define PcdToken(TokenName) _PCD_TOKEN_##TokenName
/**
Retrieves a Boolean PCD feature flag based on a token name.
@@ -49,8 +47,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return Boolean value for the PCD feature flag.
**/
-#define FeaturePcdGet(TokenName) _PCD_GET_MODE_BOOL_##TokenName
-
+#define FeaturePcdGet(TokenName) _PCD_GET_MODE_BOOL_##TokenName
/**
Retrieves an 8-bit fixed PCD token value based on a token name.
@@ -64,8 +61,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return 8-bit value for the token specified by TokenName.
**/
-#define FixedPcdGet8(TokenName) _PCD_VALUE_##TokenName
-
+#define FixedPcdGet8(TokenName) _PCD_VALUE_##TokenName
/**
Retrieves a 16-bit fixed PCD token value based on a token name.
@@ -79,8 +75,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return 16-bit value for the token specified by TokenName.
**/
-#define FixedPcdGet16(TokenName) _PCD_VALUE_##TokenName
-
+#define FixedPcdGet16(TokenName) _PCD_VALUE_##TokenName
/**
Retrieves a 32-bit fixed PCD token value based on a token name.
@@ -94,8 +89,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return 32-bit value for the token specified by TokenName.
**/
-#define FixedPcdGet32(TokenName) _PCD_VALUE_##TokenName
-
+#define FixedPcdGet32(TokenName) _PCD_VALUE_##TokenName
/**
Retrieves a 64-bit fixed PCD token value based on a token name.
@@ -109,8 +103,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return 64-bit value for the token specified by TokenName.
**/
-#define FixedPcdGet64(TokenName) _PCD_VALUE_##TokenName
-
+#define FixedPcdGet64(TokenName) _PCD_VALUE_##TokenName
/**
Retrieves a Boolean fixed PCD token value based on a token name.
@@ -124,8 +117,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return The Boolean value for the token.
**/
-#define FixedPcdGetBool(TokenName) _PCD_VALUE_##TokenName
-
+#define FixedPcdGetBool(TokenName) _PCD_VALUE_##TokenName
/**
Retrieves a pointer to a fixed PCD token buffer based on a token name.
@@ -139,8 +131,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return A pointer to the buffer.
**/
-#define FixedPcdGetPtr(TokenName) ((VOID *)_PCD_VALUE_##TokenName)
-
+#define FixedPcdGetPtr(TokenName) ((VOID *)_PCD_VALUE_##TokenName)
/**
Retrieves an 8-bit binary patchable PCD token value based on a token name.
@@ -154,7 +145,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return An 8-bit binary patchable PCD token value.
**/
-#define PatchPcdGet8(TokenName) _gPcd_BinaryPatch_##TokenName
+#define PatchPcdGet8(TokenName) _gPcd_BinaryPatch_##TokenName
/**
Retrieves a 16-bit binary patchable PCD token value based on a token name.
@@ -168,8 +159,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return A 16-bit binary patchable PCD token value.
**/
-#define PatchPcdGet16(TokenName) _gPcd_BinaryPatch_##TokenName
-
+#define PatchPcdGet16(TokenName) _gPcd_BinaryPatch_##TokenName
/**
Retrieves a 32-bit binary patchable PCD token value based on a token name.
@@ -183,8 +173,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return A 32-bit binary patchable PCD token value.
**/
-#define PatchPcdGet32(TokenName) _gPcd_BinaryPatch_##TokenName
-
+#define PatchPcdGet32(TokenName) _gPcd_BinaryPatch_##TokenName
/**
Retrieves a 64-bit binary patchable PCD token value based on a token name.
@@ -198,8 +187,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return A 64-bit binary patchable PCD token value.
**/
-#define PatchPcdGet64(TokenName) _gPcd_BinaryPatch_##TokenName
-
+#define PatchPcdGet64(TokenName) _gPcd_BinaryPatch_##TokenName
/**
Retrieves a Boolean binary patchable PCD token value based on a token name.
@@ -213,8 +201,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return The Boolean value for the token.
**/
-#define PatchPcdGetBool(TokenName) _gPcd_BinaryPatch_##TokenName
-
+#define PatchPcdGetBool(TokenName) _gPcd_BinaryPatch_##TokenName
/**
Retrieves a pointer to a binary patchable PCD token buffer based on a token name.
@@ -228,8 +215,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return A pointer to the buffer for the token.
**/
-#define PatchPcdGetPtr(TokenName) ((VOID *)_gPcd_BinaryPatch_##TokenName)
-
+#define PatchPcdGetPtr(TokenName) ((VOID *)_gPcd_BinaryPatch_##TokenName)
/**
Sets an 8-bit binary patchable PCD token value based on a token name.
@@ -244,8 +230,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return Return the Value that was set.
**/
-#define PatchPcdSet8(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))
-
+#define PatchPcdSet8(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))
/**
Sets a 16-bit binary patchable PCD token value based on a token name.
@@ -260,8 +245,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return Return the Value that was set.
**/
-#define PatchPcdSet16(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))
-
+#define PatchPcdSet16(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))
/**
Sets a 32-bit binary patchable PCD token value based on a token name.
@@ -276,8 +260,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return Return the Value that was set.
**/
-#define PatchPcdSet32(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))
-
+#define PatchPcdSet32(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))
/**
Sets a 64-bit binary patchable PCD token value based on a token name.
@@ -292,8 +275,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return Return the Value that was set.
**/
-#define PatchPcdSet64(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))
-
+#define PatchPcdSet64(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))
/**
Sets a Boolean binary patchable PCD token value based on a token name.
@@ -308,8 +290,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return Return the Value that was set.
**/
-#define PatchPcdSetBool(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))
-
+#define PatchPcdSetBool(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))
/**
Sets a pointer to a binary patchable PCD token buffer based on a token name.
@@ -340,6 +321,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
(Size), \
(Buffer) \
)
+
/**
Retrieves an 8-bit PCD token value based on a token name.
@@ -351,8 +333,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return 8-bit value for the token specified by TokenName.
**/
-#define PcdGet8(TokenName) _PCD_GET_MODE_8_##TokenName
-
+#define PcdGet8(TokenName) _PCD_GET_MODE_8_##TokenName
/**
Retrieves a 16-bit PCD token value based on a token name.
@@ -365,8 +346,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return 16-bit value for the token specified by TokenName.
**/
-#define PcdGet16(TokenName) _PCD_GET_MODE_16_##TokenName
-
+#define PcdGet16(TokenName) _PCD_GET_MODE_16_##TokenName
/**
Retrieves a 32-bit PCD token value based on a token name.
@@ -379,8 +359,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return 32-bit value for the token specified by TokenName.
**/
-#define PcdGet32(TokenName) _PCD_GET_MODE_32_##TokenName
-
+#define PcdGet32(TokenName) _PCD_GET_MODE_32_##TokenName
/**
Retrieves a 64-bit PCD token value based on a token name.
@@ -393,8 +372,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return 64-bit value for the token specified by TokenName.
**/
-#define PcdGet64(TokenName) _PCD_GET_MODE_64_##TokenName
-
+#define PcdGet64(TokenName) _PCD_GET_MODE_64_##TokenName
/**
Retrieves a pointer to a PCD token buffer based on a token name.
@@ -407,8 +385,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return A pointer to the buffer.
**/
-#define PcdGetPtr(TokenName) _PCD_GET_MODE_PTR_##TokenName
-
+#define PcdGetPtr(TokenName) _PCD_GET_MODE_PTR_##TokenName
/**
Retrieves a Boolean PCD token value based on a token name.
@@ -421,8 +398,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return A Boolean PCD token value.
**/
-#define PcdGetBool(TokenName) _PCD_GET_MODE_BOOL_##TokenName
-
+#define PcdGetBool(TokenName) _PCD_GET_MODE_BOOL_##TokenName
/**
Retrieves the size of a fixed PCD token based on a token name.
@@ -435,8 +411,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return Return the size
**/
-#define FixedPcdGetSize(TokenName) _PCD_SIZE_##TokenName
-
+#define FixedPcdGetSize(TokenName) _PCD_SIZE_##TokenName
/**
Retrieves the size of a binary patchable PCD token based on a token name.
@@ -449,8 +424,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return Return the size
**/
-#define PatchPcdGetSize(TokenName) _gPcd_BinaryPatch_Size_##TokenName
-
+#define PatchPcdGetSize(TokenName) _gPcd_BinaryPatch_Size_##TokenName
/**
Retrieves the size of the PCD token based on a token name.
@@ -463,8 +437,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return Return the size
**/
-#define PcdGetSize(TokenName) _PCD_GET_MODE_SIZE_##TokenName
-
+#define PcdGetSize(TokenName) _PCD_GET_MODE_SIZE_##TokenName
/**
Retrieve the size of a given PCD token.
@@ -479,7 +452,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return Return the size.
**/
-#define PcdGetExSize(Guid, TokenName) LibPcdGetExSize ((Guid), PcdTokenEx(Guid,TokenName))
+#define PcdGetExSize(Guid, TokenName) LibPcdGetExSize ((Guid), PcdTokenEx(Guid,TokenName))
/**
Sets a 8-bit PCD token value based on a token name.
@@ -493,7 +466,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return The status of the set operation.
**/
-#define PcdSet8S(TokenName, Value) _PCD_SET_MODE_8_S_##TokenName ((Value))
+#define PcdSet8S(TokenName, Value) _PCD_SET_MODE_8_S_##TokenName ((Value))
/**
Sets a 16-bit PCD token value based on a token name.
@@ -507,7 +480,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return The status of the set operation.
**/
-#define PcdSet16S(TokenName, Value) _PCD_SET_MODE_16_S_##TokenName ((Value))
+#define PcdSet16S(TokenName, Value) _PCD_SET_MODE_16_S_##TokenName ((Value))
/**
Sets a 32-bit PCD token value based on a token name.
@@ -521,7 +494,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return The status of the set operation.
**/
-#define PcdSet32S(TokenName, Value) _PCD_SET_MODE_32_S_##TokenName ((Value))
+#define PcdSet32S(TokenName, Value) _PCD_SET_MODE_32_S_##TokenName ((Value))
/**
Sets a 64-bit PCD token value based on a token name.
@@ -535,7 +508,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return The status of the set operation.
**/
-#define PcdSet64S(TokenName, Value) _PCD_SET_MODE_64_S_##TokenName ((Value))
+#define PcdSet64S(TokenName, Value) _PCD_SET_MODE_64_S_##TokenName ((Value))
/**
Sets a pointer to a PCD token buffer based on a token name.
@@ -561,8 +534,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define PcdSetPtrS(TokenName, SizeOfBuffer, Buffer) \
_PCD_SET_MODE_PTR_S_##TokenName ((SizeOfBuffer), (Buffer))
-
-
/**
Sets a boolean PCD token value based on a token name.
@@ -575,7 +546,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return The status of the set operation.
**/
-#define PcdSetBoolS(TokenName, Value) _PCD_SET_MODE_BOOL_S_##TokenName ((Value))
+#define PcdSetBoolS(TokenName, Value) _PCD_SET_MODE_BOOL_S_##TokenName ((Value))
/**
Retrieves a token number based on a GUID and a token name.
@@ -590,7 +561,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return Return the token number.
**/
-#define PcdTokenEx(Guid,TokenName) _PCD_TOKEN_EX_##TokenName(Guid)
+#define PcdTokenEx(Guid, TokenName) _PCD_TOKEN_EX_##TokenName(Guid)
/**
Retrieves an 8-bit PCD token value based on a GUID and a token name.
@@ -608,7 +579,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return An 8-bit PCD token value.
**/
-#define PcdGetEx8(Guid, TokenName) LibPcdGetEx8 ((Guid), PcdTokenEx(Guid,TokenName))
+#define PcdGetEx8(Guid, TokenName) LibPcdGetEx8 ((Guid), PcdTokenEx(Guid,TokenName))
/**
Retrieves a 16-bit PCD token value based on a GUID and a token name.
@@ -626,8 +597,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return A 16-bit PCD token value.
**/
-#define PcdGetEx16(Guid, TokenName) LibPcdGetEx16 ((Guid), PcdTokenEx(Guid,TokenName))
-
+#define PcdGetEx16(Guid, TokenName) LibPcdGetEx16 ((Guid), PcdTokenEx(Guid,TokenName))
/**
Retrieves a 32-bit PCD token value based on a GUID and a token name.
@@ -645,8 +615,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return A 32-bit PCD token value.
**/
-#define PcdGetEx32(Guid, TokenName) LibPcdGetEx32 ((Guid), PcdTokenEx(Guid,TokenName))
-
+#define PcdGetEx32(Guid, TokenName) LibPcdGetEx32 ((Guid), PcdTokenEx(Guid,TokenName))
/**
Retrieves a 64-bit PCD token value based on a GUID and a token name.
@@ -664,8 +633,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return A 64-bit PCD token value.
**/
-#define PcdGetEx64(Guid, TokenName) LibPcdGetEx64 ((Guid), PcdTokenEx(Guid,TokenName))
-
+#define PcdGetEx64(Guid, TokenName) LibPcdGetEx64 ((Guid), PcdTokenEx(Guid,TokenName))
/**
Retrieves a pointer to a PCD token buffer based on a GUID and a token name.
@@ -683,8 +651,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return A pointer to a PCD token buffer.
**/
-#define PcdGetExPtr(Guid, TokenName) LibPcdGetExPtr ((Guid), PcdTokenEx(Guid,TokenName))
-
+#define PcdGetExPtr(Guid, TokenName) LibPcdGetExPtr ((Guid), PcdTokenEx(Guid,TokenName))
/**
Retrieves a Boolean PCD token value based on a GUID and a token name.
@@ -702,9 +669,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return A Boolean PCD token value.
**/
-#define PcdGetExBool(Guid, TokenName) LibPcdGetExBool ((Guid), PcdTokenEx(Guid,TokenName))
-
-
+#define PcdGetExBool(Guid, TokenName) LibPcdGetExBool ((Guid), PcdTokenEx(Guid,TokenName))
/**
Sets an 8-bit PCD token value based on a GUID and a token name.
@@ -723,7 +688,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return The status of the set operation.
**/
-#define PcdSetEx8S(Guid, TokenName, Value) LibPcdSetEx8S ((Guid), PcdTokenEx(Guid,TokenName), (Value))
+#define PcdSetEx8S(Guid, TokenName, Value) LibPcdSetEx8S ((Guid), PcdTokenEx(Guid,TokenName), (Value))
/**
Sets an 16-bit PCD token value based on a GUID and a token name.
@@ -742,7 +707,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return The status of the set operation.
**/
-#define PcdSetEx16S(Guid, TokenName, Value) LibPcdSetEx16S ((Guid), PcdTokenEx(Guid,TokenName), (Value))
+#define PcdSetEx16S(Guid, TokenName, Value) LibPcdSetEx16S ((Guid), PcdTokenEx(Guid,TokenName), (Value))
/**
Sets an 32-bit PCD token value based on a GUID and a token name.
@@ -761,7 +726,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return The status of the set operation.
**/
-#define PcdSetEx32S(Guid, TokenName, Value) LibPcdSetEx32S ((Guid), PcdTokenEx(Guid,TokenName), (Value))
+#define PcdSetEx32S(Guid, TokenName, Value) LibPcdSetEx32S ((Guid), PcdTokenEx(Guid,TokenName), (Value))
/**
Sets an 64-bit PCD token value based on a GUID and a token name.
@@ -780,7 +745,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return The status of the set operation.
**/
-#define PcdSetEx64S(Guid, TokenName, Value) LibPcdSetEx64S ((Guid), PcdTokenEx(Guid,TokenName), (Value))
+#define PcdSetEx64S(Guid, TokenName, Value) LibPcdSetEx64S ((Guid), PcdTokenEx(Guid,TokenName), (Value))
/**
Sets a pointer to a PCD token buffer based on a GUID and a token name.
@@ -810,7 +775,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define PcdSetExPtrS(Guid, TokenName, SizeOfBuffer, Buffer) \
LibPcdSetExPtrS ((Guid), PcdTokenEx(Guid,TokenName), (SizeOfBuffer), (Buffer))
-
/**
Sets an boolean PCD token value based on a GUID and a token name.
@@ -845,10 +809,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
UINTN
EFIAPI
LibPcdSetSku (
- IN UINTN SkuId
+ IN UINTN SkuId
);
-
/**
This function provides a means by which to retrieve a value for a given PCD token.
@@ -862,10 +825,9 @@ LibPcdSetSku (
UINT8
EFIAPI
LibPcdGet8 (
- IN UINTN TokenNumber
+ IN UINTN TokenNumber
);
-
/**
This function provides a means by which to retrieve a value for a given PCD token.
@@ -879,10 +841,9 @@ LibPcdGet8 (
UINT16
EFIAPI
LibPcdGet16 (
- IN UINTN TokenNumber
+ IN UINTN TokenNumber
);
-
/**
This function provides a means by which to retrieve a value for a given PCD token.
@@ -896,10 +857,9 @@ LibPcdGet16 (
UINT32
EFIAPI
LibPcdGet32 (
- IN UINTN TokenNumber
+ IN UINTN TokenNumber
);
-
/**
This function provides a means by which to retrieve a value for a given PCD token.
@@ -913,10 +873,9 @@ LibPcdGet32 (
UINT64
EFIAPI
LibPcdGet64 (
- IN UINTN TokenNumber
+ IN UINTN TokenNumber
);
-
/**
This function provides a means by which to retrieve a value for a given PCD token.
@@ -930,10 +889,9 @@ LibPcdGet64 (
VOID *
EFIAPI
LibPcdGetPtr (
- IN UINTN TokenNumber
+ IN UINTN TokenNumber
);
-
/**
This function provides a means by which to retrieve a value for a given PCD token.
@@ -947,10 +905,9 @@ LibPcdGetPtr (
BOOLEAN
EFIAPI
LibPcdGetBool (
- IN UINTN TokenNumber
+ IN UINTN TokenNumber
);
-
/**
This function provides a means by which to retrieve the size of a given PCD token.
@@ -962,10 +919,9 @@ LibPcdGetBool (
UINTN
EFIAPI
LibPcdGetSize (
- IN UINTN TokenNumber
+ IN UINTN TokenNumber
);
-
/**
This function provides a means by which to retrieve a value for a given PCD token.
@@ -983,11 +939,10 @@ LibPcdGetSize (
UINT8
EFIAPI
LibPcdGetEx8 (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber
);
-
/**
This function provides a means by which to retrieve a value for a given PCD token.
@@ -1005,11 +960,10 @@ LibPcdGetEx8 (
UINT16
EFIAPI
LibPcdGetEx16 (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber
);
-
/**
Returns the 32-bit value for the token specified by TokenNumber and Guid.
If Guid is NULL, then ASSERT().
@@ -1024,11 +978,10 @@ LibPcdGetEx16 (
UINT32
EFIAPI
LibPcdGetEx32 (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber
);
-
/**
This function provides a means by which to retrieve a value for a given PCD token.
@@ -1046,11 +999,10 @@ LibPcdGetEx32 (
UINT64
EFIAPI
LibPcdGetEx64 (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber
);
-
/**
This function provides a means by which to retrieve a value for a given PCD token.
@@ -1068,11 +1020,10 @@ LibPcdGetEx64 (
VOID *
EFIAPI
LibPcdGetExPtr (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber
);
-
/**
This function provides a means by which to retrieve a value for a given PCD token.
@@ -1090,11 +1041,10 @@ LibPcdGetExPtr (
BOOLEAN
EFIAPI
LibPcdGetExBool (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber
);
-
/**
This function provides a means by which to retrieve the size of a given PCD token.
@@ -1112,11 +1062,10 @@ LibPcdGetExBool (
UINTN
EFIAPI
LibPcdGetExSize (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber
);
-
/**
This function provides a means by which to set a value for a given PCD token.
@@ -1132,8 +1081,8 @@ LibPcdGetExSize (
RETURN_STATUS
EFIAPI
LibPcdSet8S (
- IN UINTN TokenNumber,
- IN UINT8 Value
+ IN UINTN TokenNumber,
+ IN UINT8 Value
);
/**
@@ -1151,8 +1100,8 @@ LibPcdSet8S (
RETURN_STATUS
EFIAPI
LibPcdSet16S (
- IN UINTN TokenNumber,
- IN UINT16 Value
+ IN UINTN TokenNumber,
+ IN UINT16 Value
);
/**
@@ -1170,8 +1119,8 @@ LibPcdSet16S (
RETURN_STATUS
EFIAPI
LibPcdSet32S (
- IN UINTN TokenNumber,
- IN UINT32 Value
+ IN UINTN TokenNumber,
+ IN UINT32 Value
);
/**
@@ -1189,8 +1138,8 @@ LibPcdSet32S (
RETURN_STATUS
EFIAPI
LibPcdSet64S (
- IN UINTN TokenNumber,
- IN UINT64 Value
+ IN UINTN TokenNumber,
+ IN UINT64 Value
);
/**
@@ -1218,9 +1167,9 @@ LibPcdSet64S (
RETURN_STATUS
EFIAPI
LibPcdSetPtrS (
- IN UINTN TokenNumber,
- IN OUT UINTN *SizeOfBuffer,
- IN CONST VOID *Buffer
+ IN UINTN TokenNumber,
+ IN OUT UINTN *SizeOfBuffer,
+ IN CONST VOID *Buffer
);
/**
@@ -1238,8 +1187,8 @@ LibPcdSetPtrS (
RETURN_STATUS
EFIAPI
LibPcdSetBoolS (
- IN UINTN TokenNumber,
- IN BOOLEAN Value
+ IN UINTN TokenNumber,
+ IN BOOLEAN Value
);
/**
@@ -1261,9 +1210,9 @@ LibPcdSetBoolS (
RETURN_STATUS
EFIAPI
LibPcdSetEx8S (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber,
- IN UINT8 Value
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber,
+ IN UINT8 Value
);
/**
@@ -1285,9 +1234,9 @@ LibPcdSetEx8S (
RETURN_STATUS
EFIAPI
LibPcdSetEx16S (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber,
- IN UINT16 Value
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber,
+ IN UINT16 Value
);
/**
@@ -1309,9 +1258,9 @@ LibPcdSetEx16S (
RETURN_STATUS
EFIAPI
LibPcdSetEx32S (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber,
- IN UINT32 Value
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber,
+ IN UINT32 Value
);
/**
@@ -1333,9 +1282,9 @@ LibPcdSetEx32S (
RETURN_STATUS
EFIAPI
LibPcdSetEx64S (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber,
- IN UINT64 Value
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber,
+ IN UINT64 Value
);
/**
@@ -1363,10 +1312,10 @@ LibPcdSetEx64S (
RETURN_STATUS
EFIAPI
LibPcdSetExPtrS (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber,
- IN OUT UINTN *SizeOfBuffer,
- IN VOID *Buffer
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber,
+ IN OUT UINTN *SizeOfBuffer,
+ IN VOID *Buffer
);
/**
@@ -1388,9 +1337,9 @@ LibPcdSetExPtrS (
RETURN_STATUS
EFIAPI
LibPcdSetExBoolS (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber,
- IN BOOLEAN Value
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber,
+ IN BOOLEAN Value
);
/**
@@ -1412,13 +1361,12 @@ LibPcdSetExBoolS (
typedef
VOID
(EFIAPI *PCD_CALLBACK)(
- IN CONST GUID *CallBackGuid, OPTIONAL
+ IN CONST GUID *CallBackGuid OPTIONAL,
IN UINTN CallBackToken,
IN OUT VOID *TokenData,
IN UINTN TokenDataSize
);
-
/**
Set up a notification function that is called when a specified token is set.
@@ -1438,12 +1386,11 @@ VOID
VOID
EFIAPI
LibPcdCallbackOnSet (
- IN CONST GUID *Guid, OPTIONAL
- IN UINTN TokenNumber,
- IN PCD_CALLBACK NotificationFunction
+ IN CONST GUID *Guid OPTIONAL,
+ IN UINTN TokenNumber,
+ IN PCD_CALLBACK NotificationFunction
);
-
/**
Disable a notification function that was established with LibPcdCallbackonSet().
@@ -1460,12 +1407,11 @@ LibPcdCallbackOnSet (
VOID
EFIAPI
LibPcdCancelCallback (
- IN CONST GUID *Guid, OPTIONAL
- IN UINTN TokenNumber,
- IN PCD_CALLBACK NotificationFunction
+ IN CONST GUID *Guid OPTIONAL,
+ IN UINTN TokenNumber,
+ IN PCD_CALLBACK NotificationFunction
);
-
/**
Retrieves the next token in a token space.
@@ -1488,12 +1434,10 @@ LibPcdCancelCallback (
UINTN
EFIAPI
LibPcdGetNextToken (
- IN CONST GUID *Guid, OPTIONAL
- IN UINTN TokenNumber
+ IN CONST GUID *Guid OPTIONAL,
+ IN UINTN TokenNumber
);
-
-
/**
Used to retrieve the list of available PCD token space GUIDs.
@@ -1513,7 +1457,6 @@ LibPcdGetNextTokenSpace (
IN CONST GUID *TokenSpaceGuid
);
-
/**
Sets a value of a patchable PCD entry that is type pointer.
@@ -1540,10 +1483,10 @@ LibPcdGetNextTokenSpace (
VOID *
EFIAPI
LibPatchPcdSetPtr (
- OUT VOID *PatchVariable,
- IN UINTN MaximumDatumSize,
- IN OUT UINTN *SizeOfBuffer,
- IN CONST VOID *Buffer
+ OUT VOID *PatchVariable,
+ IN UINTN MaximumDatumSize,
+ IN OUT UINTN *SizeOfBuffer,
+ IN CONST VOID *Buffer
);
/**
@@ -1572,10 +1515,10 @@ LibPatchPcdSetPtr (
RETURN_STATUS
EFIAPI
LibPatchPcdSetPtrS (
- OUT VOID *PatchVariable,
- IN UINTN MaximumDatumSize,
- IN OUT UINTN *SizeOfBuffer,
- IN CONST VOID *Buffer
+ OUT VOID *PatchVariable,
+ IN UINTN MaximumDatumSize,
+ IN OUT UINTN *SizeOfBuffer,
+ IN CONST VOID *Buffer
);
/**
@@ -1606,11 +1549,11 @@ LibPatchPcdSetPtrS (
VOID *
EFIAPI
LibPatchPcdSetPtrAndSize (
- OUT VOID *PatchVariable,
- OUT UINTN *SizeOfPatchVariable,
- IN UINTN MaximumDatumSize,
- IN OUT UINTN *SizeOfBuffer,
- IN CONST VOID *Buffer
+ OUT VOID *PatchVariable,
+ OUT UINTN *SizeOfPatchVariable,
+ IN UINTN MaximumDatumSize,
+ IN OUT UINTN *SizeOfBuffer,
+ IN CONST VOID *Buffer
);
/**
@@ -1641,11 +1584,11 @@ LibPatchPcdSetPtrAndSize (
RETURN_STATUS
EFIAPI
LibPatchPcdSetPtrAndSizeS (
- OUT VOID *PatchVariable,
- OUT UINTN *SizeOfPatchVariable,
- IN UINTN MaximumDatumSize,
- IN OUT UINTN *SizeOfBuffer,
- IN CONST VOID *Buffer
+ OUT VOID *PatchVariable,
+ OUT UINTN *SizeOfPatchVariable,
+ IN UINTN MaximumDatumSize,
+ IN OUT UINTN *SizeOfBuffer,
+ IN CONST VOID *Buffer
);
typedef enum {
@@ -1662,22 +1605,21 @@ typedef struct {
/// The returned information associated with the requested TokenNumber. If
/// TokenNumber is 0, then PcdType is set to PCD_TYPE_8.
///
- PCD_TYPE PcdType;
+ PCD_TYPE PcdType;
///
/// The size of the data in bytes associated with the TokenNumber specified. If
/// TokenNumber is 0, then PcdSize is set 0.
///
- UINTN PcdSize;
+ UINTN PcdSize;
///
/// The null-terminated ASCII string associated with a given token. If the
/// TokenNumber specified was 0, then this field corresponds to the null-terminated
/// ASCII string associated with the token's namespace Guid. If NULL, there is no
/// name associated with this request.
///
- CHAR8 *PcdName;
+ CHAR8 *PcdName;
} PCD_INFO;
-
/**
Retrieve additional information associated with a PCD token.
@@ -1693,8 +1635,8 @@ typedef struct {
VOID
EFIAPI
LibPcdGetInfo (
- IN UINTN TokenNumber,
- OUT PCD_INFO *PcdInfo
+ IN UINTN TokenNumber,
+ OUT PCD_INFO *PcdInfo
);
/**
@@ -1713,9 +1655,9 @@ LibPcdGetInfo (
VOID
EFIAPI
LibPcdGetInfoEx (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber,
- OUT PCD_INFO *PcdInfo
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber,
+ OUT PCD_INFO *PcdInfo
);
/**
diff --git a/MdePkg/Include/Library/PciCf8Lib.h b/MdePkg/Include/Library/PciCf8Lib.h
index 41324e5b..e730fe5d 100644
--- a/MdePkg/Include/Library/PciCf8Lib.h
+++ b/MdePkg/Include/Library/PciCf8Lib.h
@@ -13,7 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef __PCI_CF8_LIB_H__
#define __PCI_CF8_LIB_H__
-
/**
Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
address that can be passed to the PCI Library functions.
@@ -30,7 +29,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return The encode PCI address.
**/
-#define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \
+#define PCI_CF8_LIB_ADDRESS(Bus, Device, Function, Offset) \
(((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
/**
@@ -80,7 +79,7 @@ PciCf8RegisterForRuntimeAccess (
UINT8
EFIAPI
PciCf8Read8 (
- IN UINTN Address
+ IN UINTN Address
);
/**
@@ -103,8 +102,8 @@ PciCf8Read8 (
UINT8
EFIAPI
PciCf8Write8 (
- IN UINTN Address,
- IN UINT8 Value
+ IN UINTN Address,
+ IN UINT8 Value
);
/**
@@ -131,8 +130,8 @@ PciCf8Write8 (
UINT8
EFIAPI
PciCf8Or8 (
- IN UINTN Address,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINT8 OrData
);
/**
@@ -159,8 +158,8 @@ PciCf8Or8 (
UINT8
EFIAPI
PciCf8And8 (
- IN UINTN Address,
- IN UINT8 AndData
+ IN UINTN Address,
+ IN UINT8 AndData
);
/**
@@ -189,9 +188,9 @@ PciCf8And8 (
UINT8
EFIAPI
PciCf8AndThenOr8 (
- IN UINTN Address,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
);
/**
@@ -219,9 +218,9 @@ PciCf8AndThenOr8 (
UINT8
EFIAPI
PciCf8BitFieldRead8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
/**
@@ -252,10 +251,10 @@ PciCf8BitFieldRead8 (
UINT8
EFIAPI
PciCf8BitFieldWrite8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
);
/**
@@ -289,10 +288,10 @@ PciCf8BitFieldWrite8 (
UINT8
EFIAPI
PciCf8BitFieldOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
);
/**
@@ -326,10 +325,10 @@ PciCf8BitFieldOr8 (
UINT8
EFIAPI
PciCf8BitFieldAnd8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
);
/**
@@ -367,11 +366,11 @@ PciCf8BitFieldAnd8 (
UINT8
EFIAPI
PciCf8BitFieldAndThenOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
);
/**
@@ -394,7 +393,7 @@ PciCf8BitFieldAndThenOr8 (
UINT16
EFIAPI
PciCf8Read16 (
- IN UINTN Address
+ IN UINTN Address
);
/**
@@ -418,8 +417,8 @@ PciCf8Read16 (
UINT16
EFIAPI
PciCf8Write16 (
- IN UINTN Address,
- IN UINT16 Value
+ IN UINTN Address,
+ IN UINT16 Value
);
/**
@@ -447,8 +446,8 @@ PciCf8Write16 (
UINT16
EFIAPI
PciCf8Or16 (
- IN UINTN Address,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINT16 OrData
);
/**
@@ -476,8 +475,8 @@ PciCf8Or16 (
UINT16
EFIAPI
PciCf8And16 (
- IN UINTN Address,
- IN UINT16 AndData
+ IN UINTN Address,
+ IN UINT16 AndData
);
/**
@@ -507,9 +506,9 @@ PciCf8And16 (
UINT16
EFIAPI
PciCf8AndThenOr16 (
- IN UINTN Address,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
);
/**
@@ -538,9 +537,9 @@ PciCf8AndThenOr16 (
UINT16
EFIAPI
PciCf8BitFieldRead16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
/**
@@ -572,10 +571,10 @@ PciCf8BitFieldRead16 (
UINT16
EFIAPI
PciCf8BitFieldWrite16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
);
/**
@@ -610,10 +609,10 @@ PciCf8BitFieldWrite16 (
UINT16
EFIAPI
PciCf8BitFieldOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
);
/**
@@ -648,10 +647,10 @@ PciCf8BitFieldOr16 (
UINT16
EFIAPI
PciCf8BitFieldAnd16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
);
/**
@@ -690,11 +689,11 @@ PciCf8BitFieldAnd16 (
UINT16
EFIAPI
PciCf8BitFieldAndThenOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
);
/**
@@ -717,7 +716,7 @@ PciCf8BitFieldAndThenOr16 (
UINT32
EFIAPI
PciCf8Read32 (
- IN UINTN Address
+ IN UINTN Address
);
/**
@@ -741,8 +740,8 @@ PciCf8Read32 (
UINT32
EFIAPI
PciCf8Write32 (
- IN UINTN Address,
- IN UINT32 Value
+ IN UINTN Address,
+ IN UINT32 Value
);
/**
@@ -770,8 +769,8 @@ PciCf8Write32 (
UINT32
EFIAPI
PciCf8Or32 (
- IN UINTN Address,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINT32 OrData
);
/**
@@ -799,8 +798,8 @@ PciCf8Or32 (
UINT32
EFIAPI
PciCf8And32 (
- IN UINTN Address,
- IN UINT32 AndData
+ IN UINTN Address,
+ IN UINT32 AndData
);
/**
@@ -830,9 +829,9 @@ PciCf8And32 (
UINT32
EFIAPI
PciCf8AndThenOr32 (
- IN UINTN Address,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
);
/**
@@ -861,9 +860,9 @@ PciCf8AndThenOr32 (
UINT32
EFIAPI
PciCf8BitFieldRead32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
/**
@@ -895,10 +894,10 @@ PciCf8BitFieldRead32 (
UINT32
EFIAPI
PciCf8BitFieldWrite32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
);
/**
@@ -933,10 +932,10 @@ PciCf8BitFieldWrite32 (
UINT32
EFIAPI
PciCf8BitFieldOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
);
/**
@@ -971,10 +970,10 @@ PciCf8BitFieldOr32 (
UINT32
EFIAPI
PciCf8BitFieldAnd32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
);
/**
@@ -1013,11 +1012,11 @@ PciCf8BitFieldAnd32 (
UINT32
EFIAPI
PciCf8BitFieldAndThenOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
);
/**
@@ -1047,9 +1046,9 @@ PciCf8BitFieldAndThenOr32 (
UINTN
EFIAPI
PciCf8ReadBuffer (
- IN UINTN StartAddress,
- IN UINTN Size,
- OUT VOID *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
);
/**
@@ -1080,9 +1079,9 @@ PciCf8ReadBuffer (
UINTN
EFIAPI
PciCf8WriteBuffer (
- IN UINTN StartAddress,
- IN UINTN Size,
- IN VOID *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
);
#endif
diff --git a/MdePkg/Include/Library/PciExpressLib.h b/MdePkg/Include/Library/PciExpressLib.h
index 9d453c24..e30f40cb 100644
--- a/MdePkg/Include/Library/PciExpressLib.h
+++ b/MdePkg/Include/Library/PciExpressLib.h
@@ -32,7 +32,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return The encode PCI address.
**/
-#define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) PCI_ECAM_ADDRESS ((Bus), (Device), (Function), (Offset))
+#define PCI_EXPRESS_LIB_ADDRESS(Bus, Device, Function, Offset) PCI_ECAM_ADDRESS ((Bus), (Device), (Function), (Offset))
/**
Registers a PCI device so PCI configuration registers may be accessed after
@@ -80,7 +80,7 @@ PciExpressRegisterForRuntimeAccess (
UINT8
EFIAPI
PciExpressRead8 (
- IN UINTN Address
+ IN UINTN Address
);
/**
@@ -102,8 +102,8 @@ PciExpressRead8 (
UINT8
EFIAPI
PciExpressWrite8 (
- IN UINTN Address,
- IN UINT8 Value
+ IN UINTN Address,
+ IN UINT8 Value
);
/**
@@ -129,8 +129,8 @@ PciExpressWrite8 (
UINT8
EFIAPI
PciExpressOr8 (
- IN UINTN Address,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINT8 OrData
);
/**
@@ -156,8 +156,8 @@ PciExpressOr8 (
UINT8
EFIAPI
PciExpressAnd8 (
- IN UINTN Address,
- IN UINT8 AndData
+ IN UINTN Address,
+ IN UINT8 AndData
);
/**
@@ -185,9 +185,9 @@ PciExpressAnd8 (
UINT8
EFIAPI
PciExpressAndThenOr8 (
- IN UINTN Address,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
);
/**
@@ -214,9 +214,9 @@ PciExpressAndThenOr8 (
UINT8
EFIAPI
PciExpressBitFieldRead8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
/**
@@ -246,10 +246,10 @@ PciExpressBitFieldRead8 (
UINT8
EFIAPI
PciExpressBitFieldWrite8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
);
/**
@@ -282,10 +282,10 @@ PciExpressBitFieldWrite8 (
UINT8
EFIAPI
PciExpressBitFieldOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
);
/**
@@ -318,10 +318,10 @@ PciExpressBitFieldOr8 (
UINT8
EFIAPI
PciExpressBitFieldAnd8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
);
/**
@@ -358,11 +358,11 @@ PciExpressBitFieldAnd8 (
UINT8
EFIAPI
PciExpressBitFieldAndThenOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
);
/**
@@ -384,7 +384,7 @@ PciExpressBitFieldAndThenOr8 (
UINT16
EFIAPI
PciExpressRead16 (
- IN UINTN Address
+ IN UINTN Address
);
/**
@@ -407,8 +407,8 @@ PciExpressRead16 (
UINT16
EFIAPI
PciExpressWrite16 (
- IN UINTN Address,
- IN UINT16 Value
+ IN UINTN Address,
+ IN UINT16 Value
);
/**
@@ -435,8 +435,8 @@ PciExpressWrite16 (
UINT16
EFIAPI
PciExpressOr16 (
- IN UINTN Address,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINT16 OrData
);
/**
@@ -463,8 +463,8 @@ PciExpressOr16 (
UINT16
EFIAPI
PciExpressAnd16 (
- IN UINTN Address,
- IN UINT16 AndData
+ IN UINTN Address,
+ IN UINT16 AndData
);
/**
@@ -493,9 +493,9 @@ PciExpressAnd16 (
UINT16
EFIAPI
PciExpressAndThenOr16 (
- IN UINTN Address,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
);
/**
@@ -523,9 +523,9 @@ PciExpressAndThenOr16 (
UINT16
EFIAPI
PciExpressBitFieldRead16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
/**
@@ -556,10 +556,10 @@ PciExpressBitFieldRead16 (
UINT16
EFIAPI
PciExpressBitFieldWrite16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
);
/**
@@ -593,10 +593,10 @@ PciExpressBitFieldWrite16 (
UINT16
EFIAPI
PciExpressBitFieldOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
);
/**
@@ -630,10 +630,10 @@ PciExpressBitFieldOr16 (
UINT16
EFIAPI
PciExpressBitFieldAnd16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
);
/**
@@ -671,11 +671,11 @@ PciExpressBitFieldAnd16 (
UINT16
EFIAPI
PciExpressBitFieldAndThenOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
);
/**
@@ -697,7 +697,7 @@ PciExpressBitFieldAndThenOr16 (
UINT32
EFIAPI
PciExpressRead32 (
- IN UINTN Address
+ IN UINTN Address
);
/**
@@ -720,8 +720,8 @@ PciExpressRead32 (
UINT32
EFIAPI
PciExpressWrite32 (
- IN UINTN Address,
- IN UINT32 Value
+ IN UINTN Address,
+ IN UINT32 Value
);
/**
@@ -748,8 +748,8 @@ PciExpressWrite32 (
UINT32
EFIAPI
PciExpressOr32 (
- IN UINTN Address,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINT32 OrData
);
/**
@@ -776,8 +776,8 @@ PciExpressOr32 (
UINT32
EFIAPI
PciExpressAnd32 (
- IN UINTN Address,
- IN UINT32 AndData
+ IN UINTN Address,
+ IN UINT32 AndData
);
/**
@@ -806,9 +806,9 @@ PciExpressAnd32 (
UINT32
EFIAPI
PciExpressAndThenOr32 (
- IN UINTN Address,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
);
/**
@@ -836,9 +836,9 @@ PciExpressAndThenOr32 (
UINT32
EFIAPI
PciExpressBitFieldRead32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
/**
@@ -869,10 +869,10 @@ PciExpressBitFieldRead32 (
UINT32
EFIAPI
PciExpressBitFieldWrite32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
);
/**
@@ -906,10 +906,10 @@ PciExpressBitFieldWrite32 (
UINT32
EFIAPI
PciExpressBitFieldOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
);
/**
@@ -943,10 +943,10 @@ PciExpressBitFieldOr32 (
UINT32
EFIAPI
PciExpressBitFieldAnd32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
);
/**
@@ -984,11 +984,11 @@ PciExpressBitFieldAnd32 (
UINT32
EFIAPI
PciExpressBitFieldAndThenOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
);
/**
@@ -1017,9 +1017,9 @@ PciExpressBitFieldAndThenOr32 (
UINTN
EFIAPI
PciExpressReadBuffer (
- IN UINTN StartAddress,
- IN UINTN Size,
- OUT VOID *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
);
/**
@@ -1049,9 +1049,9 @@ PciExpressReadBuffer (
UINTN
EFIAPI
PciExpressWriteBuffer (
- IN UINTN StartAddress,
- IN UINTN Size,
- IN VOID *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
);
#endif
diff --git a/MdePkg/Include/Library/PciLib.h b/MdePkg/Include/Library/PciLib.h
index 1b3c13eb..5ced196d 100644
--- a/MdePkg/Include/Library/PciLib.h
+++ b/MdePkg/Include/Library/PciLib.h
@@ -31,7 +31,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return The encoded PCI address.
**/
-#define PCI_LIB_ADDRESS(Bus,Device,Function,Register) \
+#define PCI_LIB_ADDRESS(Bus, Device, Function, Register) \
(((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
/**
@@ -79,7 +79,7 @@ PciRegisterForRuntimeAccess (
UINT8
EFIAPI
PciRead8 (
- IN UINTN Address
+ IN UINTN Address
);
/**
@@ -101,8 +101,8 @@ PciRead8 (
UINT8
EFIAPI
PciWrite8 (
- IN UINTN Address,
- IN UINT8 Value
+ IN UINTN Address,
+ IN UINT8 Value
);
/**
@@ -128,8 +128,8 @@ PciWrite8 (
UINT8
EFIAPI
PciOr8 (
- IN UINTN Address,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINT8 OrData
);
/**
@@ -155,8 +155,8 @@ PciOr8 (
UINT8
EFIAPI
PciAnd8 (
- IN UINTN Address,
- IN UINT8 AndData
+ IN UINTN Address,
+ IN UINT8 AndData
);
/**
@@ -184,9 +184,9 @@ PciAnd8 (
UINT8
EFIAPI
PciAndThenOr8 (
- IN UINTN Address,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
);
/**
@@ -213,9 +213,9 @@ PciAndThenOr8 (
UINT8
EFIAPI
PciBitFieldRead8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
/**
@@ -245,10 +245,10 @@ PciBitFieldRead8 (
UINT8
EFIAPI
PciBitFieldWrite8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
);
/**
@@ -281,10 +281,10 @@ PciBitFieldWrite8 (
UINT8
EFIAPI
PciBitFieldOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
);
/**
@@ -317,10 +317,10 @@ PciBitFieldOr8 (
UINT8
EFIAPI
PciBitFieldAnd8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
);
/**
@@ -357,11 +357,11 @@ PciBitFieldAnd8 (
UINT8
EFIAPI
PciBitFieldAndThenOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
);
/**
@@ -383,7 +383,7 @@ PciBitFieldAndThenOr8 (
UINT16
EFIAPI
PciRead16 (
- IN UINTN Address
+ IN UINTN Address
);
/**
@@ -406,8 +406,8 @@ PciRead16 (
UINT16
EFIAPI
PciWrite16 (
- IN UINTN Address,
- IN UINT16 Value
+ IN UINTN Address,
+ IN UINT16 Value
);
/**
@@ -434,8 +434,8 @@ PciWrite16 (
UINT16
EFIAPI
PciOr16 (
- IN UINTN Address,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINT16 OrData
);
/**
@@ -462,8 +462,8 @@ PciOr16 (
UINT16
EFIAPI
PciAnd16 (
- IN UINTN Address,
- IN UINT16 AndData
+ IN UINTN Address,
+ IN UINT16 AndData
);
/**
@@ -492,9 +492,9 @@ PciAnd16 (
UINT16
EFIAPI
PciAndThenOr16 (
- IN UINTN Address,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
);
/**
@@ -522,9 +522,9 @@ PciAndThenOr16 (
UINT16
EFIAPI
PciBitFieldRead16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
/**
@@ -555,10 +555,10 @@ PciBitFieldRead16 (
UINT16
EFIAPI
PciBitFieldWrite16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
);
/**
@@ -592,10 +592,10 @@ PciBitFieldWrite16 (
UINT16
EFIAPI
PciBitFieldOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
);
/**
@@ -629,10 +629,10 @@ PciBitFieldOr16 (
UINT16
EFIAPI
PciBitFieldAnd16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
);
/**
@@ -670,11 +670,11 @@ PciBitFieldAnd16 (
UINT16
EFIAPI
PciBitFieldAndThenOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
);
/**
@@ -696,7 +696,7 @@ PciBitFieldAndThenOr16 (
UINT32
EFIAPI
PciRead32 (
- IN UINTN Address
+ IN UINTN Address
);
/**
@@ -719,8 +719,8 @@ PciRead32 (
UINT32
EFIAPI
PciWrite32 (
- IN UINTN Address,
- IN UINT32 Value
+ IN UINTN Address,
+ IN UINT32 Value
);
/**
@@ -747,8 +747,8 @@ PciWrite32 (
UINT32
EFIAPI
PciOr32 (
- IN UINTN Address,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINT32 OrData
);
/**
@@ -775,8 +775,8 @@ PciOr32 (
UINT32
EFIAPI
PciAnd32 (
- IN UINTN Address,
- IN UINT32 AndData
+ IN UINTN Address,
+ IN UINT32 AndData
);
/**
@@ -805,9 +805,9 @@ PciAnd32 (
UINT32
EFIAPI
PciAndThenOr32 (
- IN UINTN Address,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
);
/**
@@ -835,9 +835,9 @@ PciAndThenOr32 (
UINT32
EFIAPI
PciBitFieldRead32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
/**
@@ -868,10 +868,10 @@ PciBitFieldRead32 (
UINT32
EFIAPI
PciBitFieldWrite32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
);
/**
@@ -905,10 +905,10 @@ PciBitFieldWrite32 (
UINT32
EFIAPI
PciBitFieldOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
);
/**
@@ -942,10 +942,10 @@ PciBitFieldOr32 (
UINT32
EFIAPI
PciBitFieldAnd32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
);
/**
@@ -983,11 +983,11 @@ PciBitFieldAnd32 (
UINT32
EFIAPI
PciBitFieldAndThenOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
);
/**
@@ -1016,9 +1016,9 @@ PciBitFieldAndThenOr32 (
UINTN
EFIAPI
PciReadBuffer (
- IN UINTN StartAddress,
- IN UINTN Size,
- OUT VOID *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
);
/**
@@ -1048,9 +1048,9 @@ PciReadBuffer (
UINTN
EFIAPI
PciWriteBuffer (
- IN UINTN StartAddress,
- IN UINTN Size,
- IN VOID *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
);
#endif
diff --git a/MdePkg/Include/Library/PciSegmentLib.h b/MdePkg/Include/Library/PciSegmentLib.h
index 1054a7c4..09c910e1 100644
--- a/MdePkg/Include/Library/PciSegmentLib.h
+++ b/MdePkg/Include/Library/PciSegmentLib.h
@@ -31,7 +31,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef __PCI_SEGMENT_LIB__
#define __PCI_SEGMENT_LIB__
-
/**
Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,
and PCI Register to an address that can be passed to the PCI Segment Library functions.
@@ -49,7 +48,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@return The address that is compatible with the PCI Segment Library functions.
**/
-#define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \
+#define PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, Register) \
((Segment != 0) ? \
( ((Register) & 0xfff) | \
(((Function) & 0x07) << 12) | \
@@ -104,7 +103,7 @@ PciSegmentRegisterForRuntimeAccess (
UINT8
EFIAPI
PciSegmentRead8 (
- IN UINT64 Address
+ IN UINT64 Address
);
/**
@@ -124,8 +123,8 @@ PciSegmentRead8 (
UINT8
EFIAPI
PciSegmentWrite8 (
- IN UINT64 Address,
- IN UINT8 Value
+ IN UINT64 Address,
+ IN UINT8 Value
);
/**
@@ -148,8 +147,8 @@ PciSegmentWrite8 (
UINT8
EFIAPI
PciSegmentOr8 (
- IN UINT64 Address,
- IN UINT8 OrData
+ IN UINT64 Address,
+ IN UINT8 OrData
);
/**
@@ -171,8 +170,8 @@ PciSegmentOr8 (
UINT8
EFIAPI
PciSegmentAnd8 (
- IN UINT64 Address,
- IN UINT8 AndData
+ IN UINT64 Address,
+ IN UINT8 AndData
);
/**
@@ -198,9 +197,9 @@ PciSegmentAnd8 (
UINT8
EFIAPI
PciSegmentAndThenOr8 (
- IN UINT64 Address,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINT64 Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
);
/**
@@ -227,9 +226,9 @@ PciSegmentAndThenOr8 (
UINT8
EFIAPI
PciSegmentBitFieldRead8 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
/**
@@ -259,10 +258,10 @@ PciSegmentBitFieldRead8 (
UINT8
EFIAPI
PciSegmentBitFieldWrite8 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 Value
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
);
/**
@@ -295,10 +294,10 @@ PciSegmentBitFieldWrite8 (
UINT8
EFIAPI
PciSegmentBitFieldOr8 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 OrData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
);
/**
@@ -331,10 +330,10 @@ PciSegmentBitFieldOr8 (
UINT8
EFIAPI
PciSegmentBitFieldAnd8 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
);
/**
@@ -370,11 +369,11 @@ PciSegmentBitFieldAnd8 (
UINT8
EFIAPI
PciSegmentBitFieldAndThenOr8 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
);
/**
@@ -394,7 +393,7 @@ PciSegmentBitFieldAndThenOr8 (
UINT16
EFIAPI
PciSegmentRead16 (
- IN UINT64 Address
+ IN UINT64 Address
);
/**
@@ -415,8 +414,8 @@ PciSegmentRead16 (
UINT16
EFIAPI
PciSegmentWrite16 (
- IN UINT64 Address,
- IN UINT16 Value
+ IN UINT64 Address,
+ IN UINT16 Value
);
/**
@@ -442,8 +441,8 @@ PciSegmentWrite16 (
UINT16
EFIAPI
PciSegmentOr16 (
- IN UINT64 Address,
- IN UINT16 OrData
+ IN UINT64 Address,
+ IN UINT16 OrData
);
/**
@@ -467,8 +466,8 @@ PciSegmentOr16 (
UINT16
EFIAPI
PciSegmentAnd16 (
- IN UINT64 Address,
- IN UINT16 AndData
+ IN UINT64 Address,
+ IN UINT16 AndData
);
/**
@@ -495,9 +494,9 @@ PciSegmentAnd16 (
UINT16
EFIAPI
PciSegmentAndThenOr16 (
- IN UINT64 Address,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINT64 Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
);
/**
@@ -525,9 +524,9 @@ PciSegmentAndThenOr16 (
UINT16
EFIAPI
PciSegmentBitFieldRead16 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
/**
@@ -558,10 +557,10 @@ PciSegmentBitFieldRead16 (
UINT16
EFIAPI
PciSegmentBitFieldWrite16 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 Value
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
);
/**
@@ -595,10 +594,10 @@ PciSegmentBitFieldWrite16 (
UINT16
EFIAPI
PciSegmentBitFieldOr16 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 OrData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
);
/**
@@ -632,10 +631,10 @@ PciSegmentBitFieldOr16 (
UINT16
EFIAPI
PciSegmentBitFieldAnd16 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
);
/**
@@ -672,11 +671,11 @@ PciSegmentBitFieldAnd16 (
UINT16
EFIAPI
PciSegmentBitFieldAndThenOr16 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
);
/**
@@ -696,7 +695,7 @@ PciSegmentBitFieldAndThenOr16 (
UINT32
EFIAPI
PciSegmentRead32 (
- IN UINT64 Address
+ IN UINT64 Address
);
/**
@@ -717,8 +716,8 @@ PciSegmentRead32 (
UINT32
EFIAPI
PciSegmentWrite32 (
- IN UINT64 Address,
- IN UINT32 Value
+ IN UINT64 Address,
+ IN UINT32 Value
);
/**
@@ -742,8 +741,8 @@ PciSegmentWrite32 (
UINT32
EFIAPI
PciSegmentOr32 (
- IN UINT64 Address,
- IN UINT32 OrData
+ IN UINT64 Address,
+ IN UINT32 OrData
);
/**
@@ -767,8 +766,8 @@ PciSegmentOr32 (
UINT32
EFIAPI
PciSegmentAnd32 (
- IN UINT64 Address,
- IN UINT32 AndData
+ IN UINT64 Address,
+ IN UINT32 AndData
);
/**
@@ -795,9 +794,9 @@ PciSegmentAnd32 (
UINT32
EFIAPI
PciSegmentAndThenOr32 (
- IN UINT64 Address,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINT64 Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
);
/**
@@ -825,9 +824,9 @@ PciSegmentAndThenOr32 (
UINT32
EFIAPI
PciSegmentBitFieldRead32 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
/**
@@ -858,10 +857,10 @@ PciSegmentBitFieldRead32 (
UINT32
EFIAPI
PciSegmentBitFieldWrite32 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
);
/**
@@ -894,10 +893,10 @@ PciSegmentBitFieldWrite32 (
UINT32
EFIAPI
PciSegmentBitFieldOr32 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
);
/**
@@ -930,10 +929,10 @@ PciSegmentBitFieldOr32 (
UINT32
EFIAPI
PciSegmentBitFieldAnd32 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
);
/**
@@ -970,11 +969,11 @@ PciSegmentBitFieldAnd32 (
UINT32
EFIAPI
PciSegmentBitFieldAndThenOr32 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
);
/**
@@ -1003,9 +1002,9 @@ PciSegmentBitFieldAndThenOr32 (
UINTN
EFIAPI
PciSegmentReadBuffer (
- IN UINT64 StartAddress,
- IN UINTN Size,
- OUT VOID *Buffer
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
);
/**
@@ -1035,9 +1034,9 @@ PciSegmentReadBuffer (
UINTN
EFIAPI
PciSegmentWriteBuffer (
- IN UINT64 StartAddress,
- IN UINTN Size,
- IN VOID *Buffer
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
);
#endif
diff --git a/MdePkg/Include/Library/PrintLib.h b/MdePkg/Include/Library/PrintLib.h
index 59cd89cc..7ac92ecf 100644
--- a/MdePkg/Include/Library/PrintLib.h
+++ b/MdePkg/Include/Library/PrintLib.h
@@ -192,10 +192,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
/// Flags bitmask values use in UnicodeValueToString() and
/// AsciiValueToString()
///
-#define LEFT_JUSTIFY 0x01
-#define COMMA_TYPE 0x08
-#define PREFIX_ZERO 0x20
-#define RADIX_HEX 0x80
+#define LEFT_JUSTIFY 0x01
+#define COMMA_TYPE 0x08
+#define PREFIX_ZERO 0x20
+#define RADIX_HEX 0x80
/**
Produces a Null-terminated Unicode string in an output buffer based on
@@ -586,10 +586,10 @@ UnicodeValueToStringS (
UINTN
EFIAPI
AsciiVSPrint (
- OUT CHAR8 *StartOfBuffer,
- IN UINTN BufferSize,
- IN CONST CHAR8 *FormatString,
- IN VA_LIST Marker
+ OUT CHAR8 *StartOfBuffer,
+ IN UINTN BufferSize,
+ IN CONST CHAR8 *FormatString,
+ IN VA_LIST Marker
);
/**
@@ -630,10 +630,10 @@ AsciiVSPrint (
UINTN
EFIAPI
AsciiBSPrint (
- OUT CHAR8 *StartOfBuffer,
- IN UINTN BufferSize,
- IN CONST CHAR8 *FormatString,
- IN BASE_LIST Marker
+ OUT CHAR8 *StartOfBuffer,
+ IN UINTN BufferSize,
+ IN CONST CHAR8 *FormatString,
+ IN BASE_LIST Marker
);
/**
@@ -826,7 +826,6 @@ AsciiSPrintUnicodeFormat (
...
);
-
/**
Converts a decimal value to a Null-terminated Ascii string.
@@ -879,11 +878,11 @@ AsciiSPrintUnicodeFormat (
RETURN_STATUS
EFIAPI
AsciiValueToStringS (
- IN OUT CHAR8 *Buffer,
- IN UINTN BufferSize,
- IN UINTN Flags,
- IN INT64 Value,
- IN UINTN Width
+ IN OUT CHAR8 *Buffer,
+ IN UINTN BufferSize,
+ IN UINTN Flags,
+ IN INT64 Value,
+ IN UINTN Width
);
/**
@@ -906,7 +905,7 @@ AsciiValueToStringS (
UINTN
EFIAPI
SPrintLength (
- IN CONST CHAR16 *FormatString,
+ IN CONST CHAR16 *FormatString,
IN VA_LIST Marker
);
@@ -928,8 +927,8 @@ SPrintLength (
UINTN
EFIAPI
SPrintLengthAsciiFormat (
- IN CONST CHAR8 *FormatString,
- IN VA_LIST Marker
+ IN CONST CHAR8 *FormatString,
+ IN VA_LIST Marker
);
#endif
diff --git a/MdePkg/Include/Library/RegisterFilterLib.h b/MdePkg/Include/Library/RegisterFilterLib.h
index 5c28715a..e51d2180 100644
--- a/MdePkg/Include/Library/RegisterFilterLib.h
+++ b/MdePkg/Include/Library/RegisterFilterLib.h
@@ -35,9 +35,9 @@ typedef enum {
BOOLEAN
EFIAPI
FilterBeforeIoRead (
- IN FILTER_IO_WIDTH Width,
- IN UINTN Address,
- IN OUT VOID *Buffer
+ IN FILTER_IO_WIDTH Width,
+ IN UINTN Address,
+ IN OUT VOID *Buffer
);
/**
@@ -56,6 +56,7 @@ FilterAfterIoRead (
IN UINTN Address,
IN VOID *Buffer
);
+
/**
Filter IO Write operation before wirte IO port.
It is used to filter IO operation.
@@ -79,13 +80,13 @@ FilterBeforeIoWrite (
IN VOID *Buffer
);
- /**
- Trace IO Write operation after wirte IO port.
- It is used to trace IO operation.
+/**
+Trace IO Write operation after wirte IO port.
+It is used to trace IO operation.
- @param[in] Width Signifies the width of the I/O operation.
- @param[in] Address The base address of the I/O operation.
- @param[in] Buffer The source buffer from which to BeforeWrite data.
+@param[in] Width Signifies the width of the I/O operation.
+@param[in] Address The base address of the I/O operation.
+@param[in] Buffer The source buffer from which to BeforeWrite data.
**/
VOID
@@ -188,8 +189,8 @@ FilterAfterMmIoWrite (
BOOLEAN
EFIAPI
FilterBeforeMsrRead (
- IN UINT32 Index,
- IN OUT UINT64 *Value
+ IN UINT32 Index,
+ IN OUT UINT64 *Value
);
/**
@@ -202,8 +203,8 @@ FilterBeforeMsrRead (
VOID
EFIAPI
FilterAfterMsrRead (
- IN UINT32 Index,
- IN UINT64 *Value
+ IN UINT32 Index,
+ IN UINT64 *Value
);
/**
@@ -222,8 +223,8 @@ FilterAfterMsrRead (
BOOLEAN
EFIAPI
FilterBeforeMsrWrite (
- IN UINT32 Index,
- IN UINT64 *Value
+ IN UINT32 Index,
+ IN UINT64 *Value
);
/**
@@ -236,8 +237,8 @@ FilterBeforeMsrWrite (
VOID
EFIAPI
FilterAfterMsrWrite (
- IN UINT32 Index,
- IN UINT64 *Value
+ IN UINT32 Index,
+ IN UINT64 *Value
);
#endif // REGISTER_FILTER_LIB_H_
diff --git a/MdePkg/Include/Library/RngLib.h b/MdePkg/Include/Library/RngLib.h
index bed9d8e5..3be935c5 100644
--- a/MdePkg/Include/Library/RngLib.h
+++ b/MdePkg/Include/Library/RngLib.h
@@ -1,6 +1,7 @@
/** @file
Provides random number generator services.
+Copyright (c) 2023, Arm Limited. All rights reserved.
Copyright (c) 2015, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -23,7 +24,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
BOOLEAN
EFIAPI
GetRandomNumber16 (
- OUT UINT16 *Rand
+ OUT UINT16 *Rand
);
/**
@@ -40,7 +41,7 @@ GetRandomNumber16 (
BOOLEAN
EFIAPI
GetRandomNumber32 (
- OUT UINT32 *Rand
+ OUT UINT32 *Rand
);
/**
@@ -57,7 +58,7 @@ GetRandomNumber32 (
BOOLEAN
EFIAPI
GetRandomNumber64 (
- OUT UINT64 *Rand
+ OUT UINT64 *Rand
);
/**
@@ -74,7 +75,23 @@ GetRandomNumber64 (
BOOLEAN
EFIAPI
GetRandomNumber128 (
- OUT UINT64 *Rand
+ OUT UINT64 *Rand
);
-#endif // __RNG_LIB_H__
+/**
+ Get a GUID identifying the RNG algorithm implementation.
+
+ @param [out] RngGuid If success, contains the GUID identifying
+ the RNG algorithm implementation.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_UNSUPPORTED Not supported.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+**/
+EFI_STATUS
+EFIAPI
+GetRngGuid (
+ GUID *RngGuid
+ );
+
+#endif // __RNG_LIB_H__
diff --git a/MdePkg/Include/Library/SerialPortLib.h b/MdePkg/Include/Library/SerialPortLib.h
index 1cd57656..9b633c60 100644
--- a/MdePkg/Include/Library/SerialPortLib.h
+++ b/MdePkg/Include/Library/SerialPortLib.h
@@ -50,11 +50,10 @@ SerialPortInitialize (
UINTN
EFIAPI
SerialPortWrite (
- IN UINT8 *Buffer,
- IN UINTN NumberOfBytes
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
);
-
/**
Read data from serial device and save the datas in buffer.
@@ -74,8 +73,8 @@ SerialPortWrite (
UINTN
EFIAPI
SerialPortRead (
- OUT UINT8 *Buffer,
- IN UINTN NumberOfBytes
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
);
/**
@@ -108,7 +107,7 @@ SerialPortPoll (
RETURN_STATUS
EFIAPI
SerialPortSetControl (
- IN UINT32 Control
+ IN UINT32 Control
);
/**
@@ -124,7 +123,7 @@ SerialPortSetControl (
RETURN_STATUS
EFIAPI
SerialPortGetControl (
- OUT UINT32 *Control
+ OUT UINT32 *Control
);
/**
@@ -163,12 +162,12 @@ SerialPortGetControl (
RETURN_STATUS
EFIAPI
SerialPortSetAttributes (
- IN OUT UINT64 *BaudRate,
- IN OUT UINT32 *ReceiveFifoDepth,
- IN OUT UINT32 *Timeout,
- IN OUT EFI_PARITY_TYPE *Parity,
- IN OUT UINT8 *DataBits,
- IN OUT EFI_STOP_BITS_TYPE *StopBits
+ IN OUT UINT64 *BaudRate,
+ IN OUT UINT32 *ReceiveFifoDepth,
+ IN OUT UINT32 *Timeout,
+ IN OUT EFI_PARITY_TYPE *Parity,
+ IN OUT UINT8 *DataBits,
+ IN OUT EFI_STOP_BITS_TYPE *StopBits
);
#endif
diff --git a/MdePkg/Include/Library/SmbusLib.h b/MdePkg/Include/Library/SmbusLib.h
index 1d23b729..13adfb4f 100644
--- a/MdePkg/Include/Library/SmbusLib.h
+++ b/MdePkg/Include/Library/SmbusLib.h
@@ -24,7 +24,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@param Pec TRUE if Packet Error Checking is enabled. Otherwise FALSE.
**/
-#define SMBUS_LIB_ADDRESS(SlaveAddress,Command,Length,Pec) \
+#define SMBUS_LIB_ADDRESS(SlaveAddress, Command, Length, Pec) \
( ((Pec) ? BIT22: 0) | \
(((SlaveAddress) & 0x7f) << 1) | \
(((Command) & 0xff) << 8) | \
@@ -36,44 +36,35 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC
**/
-#define SMBUS_LIB_SLAVE_ADDRESS(SmBusAddress) (((SmBusAddress) >> 1) & 0x7f)
+#define SMBUS_LIB_SLAVE_ADDRESS(SmBusAddress) (((SmBusAddress) >> 1) & 0x7f)
/**
Macro that returns the SMBUS Command value from an SmBusAddress Parameter value.
@param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC
**/
-#define SMBUS_LIB_COMMAND(SmBusAddress) (((SmBusAddress) >> 8) & 0xff)
+#define SMBUS_LIB_COMMAND(SmBusAddress) (((SmBusAddress) >> 8) & 0xff)
/**
Macro that returns the SMBUS Data Length value from an SmBusAddress Parameter value.
@param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC
**/
-#define SMBUS_LIB_LENGTH(SmBusAddress) (((SmBusAddress) >> 16) & 0x3f)
+#define SMBUS_LIB_LENGTH(SmBusAddress) (((SmBusAddress) >> 16) & 0x3f)
/**
Macro that returns the SMBUS PEC value from an SmBusAddress Parameter value.
@param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC
**/
-#define SMBUS_LIB_PEC(SmBusAddress) ((BOOLEAN) (((SmBusAddress) & BIT22) != 0))
+#define SMBUS_LIB_PEC(SmBusAddress) ((BOOLEAN) (((SmBusAddress) & BIT22) != 0))
/**
Macro that returns the set of reserved bits from an SmBusAddress Parameter value.
@param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC
**/
-#define SMBUS_LIB_RESERVED(SmBusAddress) ((SmBusAddress) & ~(BIT23 - 2))
-
-/**
- Clear SmBus in use status
-**/
-VOID
-EFIAPI
-SmBusClearInUseStatus (
- VOID
- );
+#define SMBUS_LIB_RESERVED(SmBusAddress) ((SmBusAddress) & ~(BIT23 - 2))
/**
Executes an SMBUS quick read command.
@@ -102,8 +93,8 @@ SmBusClearInUseStatus (
VOID
EFIAPI
SmBusQuickRead (
- IN UINTN SmBusAddress,
- OUT RETURN_STATUS *Status OPTIONAL
+ IN UINTN SmBusAddress,
+ OUT RETURN_STATUS *Status OPTIONAL
);
/**
@@ -133,8 +124,8 @@ SmBusQuickRead (
VOID
EFIAPI
SmBusQuickWrite (
- IN UINTN SmBusAddress,
- OUT RETURN_STATUS *Status OPTIONAL
+ IN UINTN SmBusAddress,
+ OUT RETURN_STATUS *Status OPTIONAL
);
/**
@@ -496,5 +487,4 @@ SmBusBlockProcessCall (
OUT RETURN_STATUS *Status OPTIONAL
);
-
#endif
diff --git a/MdePkg/Include/Library/SynchronizationLib.h b/MdePkg/Include/Library/SynchronizationLib.h
index fc01b10c..07a98c23 100644
--- a/MdePkg/Include/Library/SynchronizationLib.h
+++ b/MdePkg/Include/Library/SynchronizationLib.h
@@ -12,8 +12,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
///
/// Definitions for SPIN_LOCK
///
-typedef volatile UINTN SPIN_LOCK;
-
+typedef volatile UINTN SPIN_LOCK;
/**
Retrieves the architecture-specific spin lock alignment requirements for
@@ -37,7 +36,6 @@ GetSpinLockProperties (
VOID
);
-
/**
Initializes a spin lock to the released state and returns the spin lock.
@@ -57,10 +55,9 @@ GetSpinLockProperties (
SPIN_LOCK *
EFIAPI
InitializeSpinLock (
- OUT SPIN_LOCK *SpinLock
+ OUT SPIN_LOCK *SpinLock
);
-
/**
Waits until a spin lock can be placed in the acquired state.
@@ -84,10 +81,9 @@ InitializeSpinLock (
SPIN_LOCK *
EFIAPI
AcquireSpinLock (
- IN OUT SPIN_LOCK *SpinLock
+ IN OUT SPIN_LOCK *SpinLock
);
-
/**
Attempts to place a spin lock in the acquired state.
@@ -108,10 +104,9 @@ AcquireSpinLock (
BOOLEAN
EFIAPI
AcquireSpinLockOrFail (
- IN OUT SPIN_LOCK *SpinLock
+ IN OUT SPIN_LOCK *SpinLock
);
-
/**
Releases a spin lock.
@@ -129,10 +124,9 @@ AcquireSpinLockOrFail (
SPIN_LOCK *
EFIAPI
ReleaseSpinLock (
- IN OUT SPIN_LOCK *SpinLock
+ IN OUT SPIN_LOCK *SpinLock
);
-
/**
Performs an atomic increment of a 32-bit unsigned integer.
@@ -150,10 +144,9 @@ ReleaseSpinLock (
UINT32
EFIAPI
InterlockedIncrement (
- IN volatile UINT32 *Value
+ IN volatile UINT32 *Value
);
-
/**
Performs an atomic decrement of a 32-bit unsigned integer.
@@ -171,10 +164,9 @@ InterlockedIncrement (
UINT32
EFIAPI
InterlockedDecrement (
- IN volatile UINT32 *Value
+ IN volatile UINT32 *Value
);
-
/**
Performs an atomic compare exchange operation on a 16-bit unsigned integer.
@@ -196,9 +188,9 @@ InterlockedDecrement (
UINT16
EFIAPI
InterlockedCompareExchange16 (
- IN OUT volatile UINT16 *Value,
- IN UINT16 CompareValue,
- IN UINT16 ExchangeValue
+ IN OUT volatile UINT16 *Value,
+ IN UINT16 CompareValue,
+ IN UINT16 ExchangeValue
);
/**
@@ -223,12 +215,11 @@ InterlockedCompareExchange16 (
UINT32
EFIAPI
InterlockedCompareExchange32 (
- IN OUT volatile UINT32 *Value,
- IN UINT32 CompareValue,
- IN UINT32 ExchangeValue
+ IN OUT volatile UINT32 *Value,
+ IN UINT32 CompareValue,
+ IN UINT32 ExchangeValue
);
-
/**
Performs an atomic compare exchange operation on a 64-bit unsigned integer.
@@ -250,12 +241,11 @@ InterlockedCompareExchange32 (
UINT64
EFIAPI
InterlockedCompareExchange64 (
- IN OUT volatile UINT64 *Value,
- IN UINT64 CompareValue,
- IN UINT64 ExchangeValue
+ IN OUT volatile UINT64 *Value,
+ IN UINT64 CompareValue,
+ IN UINT64 ExchangeValue
);
-
/**
Performs an atomic compare exchange operation on a pointer value.
@@ -277,11 +267,9 @@ InterlockedCompareExchange64 (
VOID *
EFIAPI
InterlockedCompareExchangePointer (
- IN OUT VOID * volatile *Value,
- IN VOID *CompareValue,
- IN VOID *ExchangeValue
+ IN OUT VOID *volatile *Value,
+ IN VOID *CompareValue,
+ IN VOID *ExchangeValue
);
#endif
-
-
diff --git a/MdePkg/Include/Library/TimerLib.h b/MdePkg/Include/Library/TimerLib.h
index a4c2d881..a853811e 100644
--- a/MdePkg/Include/Library/TimerLib.h
+++ b/MdePkg/Include/Library/TimerLib.h
@@ -22,7 +22,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
UINTN
EFIAPI
MicroSecondDelay (
- IN UINTN MicroSeconds
+ IN UINTN MicroSeconds
);
/**
@@ -38,7 +38,7 @@ MicroSecondDelay (
UINTN
EFIAPI
NanoSecondDelay (
- IN UINTN NanoSeconds
+ IN UINTN NanoSeconds
);
/**
@@ -84,8 +84,8 @@ GetPerformanceCounter (
UINT64
EFIAPI
GetPerformanceCounterProperties (
- OUT UINT64 *StartValue, OPTIONAL
- OUT UINT64 *EndValue OPTIONAL
+ OUT UINT64 *StartValue OPTIONAL,
+ OUT UINT64 *EndValue OPTIONAL
);
/**
@@ -102,7 +102,7 @@ GetPerformanceCounterProperties (
UINT64
EFIAPI
GetTimeInNanoSecond (
- IN UINT64 Ticks
+ IN UINT64 Ticks
);
#endif
diff --git a/MdePkg/Include/Pi/PiBootMode.h b/MdePkg/Include/Pi/PiBootMode.h
index 74b499a6..59a0557f 100644
--- a/MdePkg/Include/Pi/PiBootMode.h
+++ b/MdePkg/Include/Pi/PiBootMode.h
@@ -15,22 +15,22 @@
///
/// EFI boot mode
///
-typedef UINT32 EFI_BOOT_MODE;
+typedef UINT32 EFI_BOOT_MODE;
//
// 0x21 - 0xf..f are reserved.
//
-#define BOOT_WITH_FULL_CONFIGURATION 0x00
-#define BOOT_WITH_MINIMAL_CONFIGURATION 0x01
-#define BOOT_ASSUMING_NO_CONFIGURATION_CHANGES 0x02
-#define BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS 0x03
-#define BOOT_WITH_DEFAULT_SETTINGS 0x04
-#define BOOT_ON_S4_RESUME 0x05
-#define BOOT_ON_S5_RESUME 0x06
-#define BOOT_WITH_MFG_MODE_SETTINGS 0x07
-#define BOOT_ON_S2_RESUME 0x10
-#define BOOT_ON_S3_RESUME 0x11
-#define BOOT_ON_FLASH_UPDATE 0x12
-#define BOOT_IN_RECOVERY_MODE 0x20
+#define BOOT_WITH_FULL_CONFIGURATION 0x00
+#define BOOT_WITH_MINIMAL_CONFIGURATION 0x01
+#define BOOT_ASSUMING_NO_CONFIGURATION_CHANGES 0x02
+#define BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS 0x03
+#define BOOT_WITH_DEFAULT_SETTINGS 0x04
+#define BOOT_ON_S4_RESUME 0x05
+#define BOOT_ON_S5_RESUME 0x06
+#define BOOT_WITH_MFG_MODE_SETTINGS 0x07
+#define BOOT_ON_S2_RESUME 0x10
+#define BOOT_ON_S3_RESUME 0x11
+#define BOOT_ON_FLASH_UPDATE 0x12
+#define BOOT_IN_RECOVERY_MODE 0x20
#endif
diff --git a/MdePkg/Include/Pi/PiDependency.h b/MdePkg/Include/Pi/PiDependency.h
index 82d59175..8e6f53c5 100644
--- a/MdePkg/Include/Pi/PiDependency.h
+++ b/MdePkg/Include/Pi/PiDependency.h
@@ -8,6 +8,7 @@
PI Version 1.0
**/
+
#ifndef __PI_DEPENDENCY_H__
#define __PI_DEPENDENCY_H__
@@ -15,27 +16,26 @@
/// If present, this must be the first and only opcode,
/// EFI_DEP_BEFORE may be used by DXE and SMM drivers.
///
-#define EFI_DEP_BEFORE 0x00
+#define EFI_DEP_BEFORE 0x00
///
/// If present, this must be the first and only opcode,
/// EFI_DEP_AFTER may be used by DXE and SMM drivers.
///
-#define EFI_DEP_AFTER 0x01
-
-#define EFI_DEP_PUSH 0x02
-#define EFI_DEP_AND 0x03
-#define EFI_DEP_OR 0x04
-#define EFI_DEP_NOT 0x05
-#define EFI_DEP_TRUE 0x06
-#define EFI_DEP_FALSE 0x07
-#define EFI_DEP_END 0x08
+#define EFI_DEP_AFTER 0x01
+#define EFI_DEP_PUSH 0x02
+#define EFI_DEP_AND 0x03
+#define EFI_DEP_OR 0x04
+#define EFI_DEP_NOT 0x05
+#define EFI_DEP_TRUE 0x06
+#define EFI_DEP_FALSE 0x07
+#define EFI_DEP_END 0x08
///
/// If present, this must be the first opcode,
/// EFI_DEP_SOR is only used by DXE driver.
///
-#define EFI_DEP_SOR 0x09
+#define EFI_DEP_SOR 0x09
#endif
diff --git a/MdePkg/Include/Pi/PiFirmwareFile.h b/MdePkg/Include/Pi/PiFirmwareFile.h
index bfb8fe36..58d6ebf9 100644
--- a/MdePkg/Include/Pi/PiFirmwareFile.h
+++ b/MdePkg/Include/Pi/PiFirmwareFile.h
@@ -9,7 +9,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
-
#ifndef __PI_FIRMWARE_FILE_H__
#define __PI_FIRMWARE_FILE_H__
@@ -24,7 +23,7 @@ typedef union {
/// header. The State and IntegrityCheck.Checksum.File fields are assumed
/// to be zero and the checksum is calculated such that the entire header sums to zero.
///
- UINT8 Header;
+ UINT8 Header;
///
/// If the FFS_ATTRIB_CHECKSUM (see definition below) bit of the Attributes
/// field is set to one, the IntegrityCheck.Checksum.File field is an 8-bit
@@ -34,7 +33,7 @@ typedef union {
/// 0xAA. The IntegrityCheck.Checksum.File field is valid any time the
/// EFI_FILE_DATA_VALID bit is set in the State field.
///
- UINT8 File;
+ UINT8 File;
} Checksum;
///
/// This is the full 16 bits of the IntegrityCheck field.
@@ -48,47 +47,47 @@ typedef union {
///
#define FFS_FIXED_CHECKSUM 0xAA
-typedef UINT8 EFI_FV_FILETYPE;
-typedef UINT8 EFI_FFS_FILE_ATTRIBUTES;
-typedef UINT8 EFI_FFS_FILE_STATE;
+typedef UINT8 EFI_FV_FILETYPE;
+typedef UINT8 EFI_FFS_FILE_ATTRIBUTES;
+typedef UINT8 EFI_FFS_FILE_STATE;
///
/// File Types Definitions
///
-#define EFI_FV_FILETYPE_ALL 0x00
-#define EFI_FV_FILETYPE_RAW 0x01
-#define EFI_FV_FILETYPE_FREEFORM 0x02
-#define EFI_FV_FILETYPE_SECURITY_CORE 0x03
-#define EFI_FV_FILETYPE_PEI_CORE 0x04
-#define EFI_FV_FILETYPE_DXE_CORE 0x05
-#define EFI_FV_FILETYPE_PEIM 0x06
-#define EFI_FV_FILETYPE_DRIVER 0x07
-#define EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER 0x08
-#define EFI_FV_FILETYPE_APPLICATION 0x09
-#define EFI_FV_FILETYPE_MM 0x0A
-#define EFI_FV_FILETYPE_SMM EFI_FV_FILETYPE_MM
-#define EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE 0x0B
-#define EFI_FV_FILETYPE_COMBINED_MM_DXE 0x0C
-#define EFI_FV_FILETYPE_COMBINED_SMM_DXE EFI_FV_FILETYPE_COMBINED_MM_DXE
-#define EFI_FV_FILETYPE_MM_CORE 0x0D
-#define EFI_FV_FILETYPE_SMM_CORE EFI_FV_FILETYPE_MM_CORE
-#define EFI_FV_FILETYPE_MM_STANDALONE 0x0E
-#define EFI_FV_FILETYPE_MM_CORE_STANDALONE 0x0F
-#define EFI_FV_FILETYPE_OEM_MIN 0xc0
-#define EFI_FV_FILETYPE_OEM_MAX 0xdf
-#define EFI_FV_FILETYPE_DEBUG_MIN 0xe0
-#define EFI_FV_FILETYPE_DEBUG_MAX 0xef
-#define EFI_FV_FILETYPE_FFS_MIN 0xf0
-#define EFI_FV_FILETYPE_FFS_MAX 0xff
-#define EFI_FV_FILETYPE_FFS_PAD 0xf0
+#define EFI_FV_FILETYPE_ALL 0x00
+#define EFI_FV_FILETYPE_RAW 0x01
+#define EFI_FV_FILETYPE_FREEFORM 0x02
+#define EFI_FV_FILETYPE_SECURITY_CORE 0x03
+#define EFI_FV_FILETYPE_PEI_CORE 0x04
+#define EFI_FV_FILETYPE_DXE_CORE 0x05
+#define EFI_FV_FILETYPE_PEIM 0x06
+#define EFI_FV_FILETYPE_DRIVER 0x07
+#define EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER 0x08
+#define EFI_FV_FILETYPE_APPLICATION 0x09
+#define EFI_FV_FILETYPE_MM 0x0A
+#define EFI_FV_FILETYPE_SMM EFI_FV_FILETYPE_MM
+#define EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE 0x0B
+#define EFI_FV_FILETYPE_COMBINED_MM_DXE 0x0C
+#define EFI_FV_FILETYPE_COMBINED_SMM_DXE EFI_FV_FILETYPE_COMBINED_MM_DXE
+#define EFI_FV_FILETYPE_MM_CORE 0x0D
+#define EFI_FV_FILETYPE_SMM_CORE EFI_FV_FILETYPE_MM_CORE
+#define EFI_FV_FILETYPE_MM_STANDALONE 0x0E
+#define EFI_FV_FILETYPE_MM_CORE_STANDALONE 0x0F
+#define EFI_FV_FILETYPE_OEM_MIN 0xc0
+#define EFI_FV_FILETYPE_OEM_MAX 0xdf
+#define EFI_FV_FILETYPE_DEBUG_MIN 0xe0
+#define EFI_FV_FILETYPE_DEBUG_MAX 0xef
+#define EFI_FV_FILETYPE_FFS_MIN 0xf0
+#define EFI_FV_FILETYPE_FFS_MAX 0xff
+#define EFI_FV_FILETYPE_FFS_PAD 0xf0
///
/// FFS File Attributes.
///
-#define FFS_ATTRIB_LARGE_FILE 0x01
-#define FFS_ATTRIB_DATA_ALIGNMENT_2 0x02
-#define FFS_ATTRIB_FIXED 0x04
-#define FFS_ATTRIB_DATA_ALIGNMENT 0x38
-#define FFS_ATTRIB_CHECKSUM 0x40
+#define FFS_ATTRIB_LARGE_FILE 0x01
+#define FFS_ATTRIB_DATA_ALIGNMENT_2 0x02
+#define FFS_ATTRIB_FIXED 0x04
+#define FFS_ATTRIB_DATA_ALIGNMENT 0x38
+#define FFS_ATTRIB_CHECKSUM 0x40
///
/// FFS File State Bits.
@@ -100,7 +99,6 @@ typedef UINT8 EFI_FFS_FILE_STATE;
#define EFI_FILE_DELETED 0x10
#define EFI_FILE_HEADER_INVALID 0x20
-
///
/// Each file begins with the header that describe the
/// contents and state of the files.
@@ -109,27 +107,27 @@ typedef struct {
///
/// This GUID is the file name. It is used to uniquely identify the file.
///
- EFI_GUID Name;
+ EFI_GUID Name;
///
/// Used to verify the integrity of the file.
///
- EFI_FFS_INTEGRITY_CHECK IntegrityCheck;
+ EFI_FFS_INTEGRITY_CHECK IntegrityCheck;
///
/// Identifies the type of file.
///
- EFI_FV_FILETYPE Type;
+ EFI_FV_FILETYPE Type;
///
/// Declares various file attribute bits.
///
- EFI_FFS_FILE_ATTRIBUTES Attributes;
+ EFI_FFS_FILE_ATTRIBUTES Attributes;
///
/// The length of the file in bytes, including the FFS header.
///
- UINT8 Size[3];
+ UINT8 Size[3];
///
/// Used to track the state of the file throughout the life of the file from creation to deletion.
///
- EFI_FFS_FILE_STATE State;
+ EFI_FFS_FILE_STATE State;
} EFI_FFS_FILE_HEADER;
typedef struct {
@@ -138,22 +136,22 @@ typedef struct {
/// one instance of a file with the file name GUID of Name in any given firmware
/// volume, except if the file type is EFI_FV_FILETYPE_FFS_PAD.
///
- EFI_GUID Name;
+ EFI_GUID Name;
///
/// Used to verify the integrity of the file.
///
- EFI_FFS_INTEGRITY_CHECK IntegrityCheck;
+ EFI_FFS_INTEGRITY_CHECK IntegrityCheck;
///
/// Identifies the type of file.
///
- EFI_FV_FILETYPE Type;
+ EFI_FV_FILETYPE Type;
///
/// Declares various file attribute bits.
///
- EFI_FFS_FILE_ATTRIBUTES Attributes;
+ EFI_FFS_FILE_ATTRIBUTES Attributes;
///
/// The length of the file in bytes, including the FFS header.
@@ -162,18 +160,18 @@ typedef struct {
/// Size is not required to be a multiple of 8 bytes. Given a file F, the next file header is
/// located at the next 8-byte aligned firmware volume offset following the last byte of the file F.
///
- UINT8 Size[3];
+ UINT8 Size[3];
///
/// Used to track the state of the file throughout the life of the file from creation to deletion.
///
- EFI_FFS_FILE_STATE State;
+ EFI_FFS_FILE_STATE State;
///
/// If FFS_ATTRIB_LARGE_FILE is set in Attributes, then ExtendedSize exists and Size must be set to zero.
/// If FFS_ATTRIB_LARGE_FILE is not set then EFI_FFS_FILE_HEADER is used.
///
- UINT64 ExtendedSize;
+ UINT64 ExtendedSize;
} EFI_FFS_FILE_HEADER2;
#define IS_FFS_FILE2(FfsFileHeaderPtr) \
@@ -184,7 +182,7 @@ typedef struct {
/// FFS_FILE_SIZE() function-like macro below must not have side effects:
/// FfsFileHeaderPtr is evaluated multiple times.
///
-#define FFS_FILE_SIZE(FfsFileHeaderPtr) ((UINT32) ( \
+#define FFS_FILE_SIZE(FfsFileHeaderPtr) ((UINT32) (\
(((EFI_FFS_FILE_HEADER *) (UINTN) (FfsFileHeaderPtr))->Size[0] ) | \
(((EFI_FFS_FILE_HEADER *) (UINTN) (FfsFileHeaderPtr))->Size[1] << 8) | \
(((EFI_FFS_FILE_HEADER *) (UINTN) (FfsFileHeaderPtr))->Size[2] << 16)))
@@ -198,33 +196,33 @@ typedef UINT8 EFI_SECTION_TYPE;
/// Pseudo type. It is used as a wild card when retrieving sections.
/// The section type EFI_SECTION_ALL matches all section types.
///
-#define EFI_SECTION_ALL 0x00
+#define EFI_SECTION_ALL 0x00
///
/// Encapsulation section Type values.
///
-#define EFI_SECTION_COMPRESSION 0x01
+#define EFI_SECTION_COMPRESSION 0x01
-#define EFI_SECTION_GUID_DEFINED 0x02
+#define EFI_SECTION_GUID_DEFINED 0x02
-#define EFI_SECTION_DISPOSABLE 0x03
+#define EFI_SECTION_DISPOSABLE 0x03
///
/// Leaf section Type values.
///
-#define EFI_SECTION_PE32 0x10
-#define EFI_SECTION_PIC 0x11
-#define EFI_SECTION_TE 0x12
-#define EFI_SECTION_DXE_DEPEX 0x13
-#define EFI_SECTION_VERSION 0x14
-#define EFI_SECTION_USER_INTERFACE 0x15
-#define EFI_SECTION_COMPATIBILITY16 0x16
-#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17
-#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18
-#define EFI_SECTION_RAW 0x19
-#define EFI_SECTION_PEI_DEPEX 0x1B
-#define EFI_SECTION_MM_DEPEX 0x1C
-#define EFI_SECTION_SMM_DEPEX EFI_SECTION_MM_DEPEX
+#define EFI_SECTION_PE32 0x10
+#define EFI_SECTION_PIC 0x11
+#define EFI_SECTION_TE 0x12
+#define EFI_SECTION_DXE_DEPEX 0x13
+#define EFI_SECTION_VERSION 0x14
+#define EFI_SECTION_USER_INTERFACE 0x15
+#define EFI_SECTION_COMPATIBILITY16 0x16
+#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17
+#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18
+#define EFI_SECTION_RAW 0x19
+#define EFI_SECTION_PEI_DEPEX 0x1B
+#define EFI_SECTION_MM_DEPEX 0x1C
+#define EFI_SECTION_SMM_DEPEX EFI_SECTION_MM_DEPEX
///
/// Common section header.
@@ -234,8 +232,8 @@ typedef struct {
/// A 24-bit unsigned integer that contains the total size of the section in bytes,
/// including the EFI_COMMON_SECTION_HEADER.
///
- UINT8 Size[3];
- EFI_SECTION_TYPE Type;
+ UINT8 Size[3];
+ EFI_SECTION_TYPE Type;
///
/// Declares the section type.
///
@@ -246,15 +244,15 @@ typedef struct {
/// A 24-bit unsigned integer that contains the total size of the section in bytes,
/// including the EFI_COMMON_SECTION_HEADER.
///
- UINT8 Size[3];
+ UINT8 Size[3];
- EFI_SECTION_TYPE Type;
+ EFI_SECTION_TYPE Type;
///
/// If Size is 0xFFFFFF, then ExtendedSize contains the size of the section. If
/// Size is not equal to 0xFFFFFF, then this field does not exist.
///
- UINT32 ExtendedSize;
+ UINT32 ExtendedSize;
} EFI_COMMON_SECTION_HEADER2;
///
@@ -277,15 +275,15 @@ typedef struct {
///
/// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION.
///
- EFI_COMMON_SECTION_HEADER CommonHeader;
+ EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// The UINT32 that indicates the size of the section data after decompression.
///
- UINT32 UncompressedLength;
+ UINT32 UncompressedLength;
///
/// Indicates which compression algorithm is used.
///
- UINT8 CompressionType;
+ UINT8 CompressionType;
} EFI_COMPRESSION_SECTION;
typedef struct {
@@ -312,20 +310,20 @@ typedef struct {
/// order to conserve space. The contents of this section are implementation specific, but might contain
/// debug data or detailed integration instructions.
///
-typedef EFI_COMMON_SECTION_HEADER EFI_DISPOSABLE_SECTION;
-typedef EFI_COMMON_SECTION_HEADER2 EFI_DISPOSABLE_SECTION2;
+typedef EFI_COMMON_SECTION_HEADER EFI_DISPOSABLE_SECTION;
+typedef EFI_COMMON_SECTION_HEADER2 EFI_DISPOSABLE_SECTION2;
///
/// The leaf section which could be used to determine the dispatch order of DXEs.
///
-typedef EFI_COMMON_SECTION_HEADER EFI_DXE_DEPEX_SECTION;
-typedef EFI_COMMON_SECTION_HEADER2 EFI_DXE_DEPEX_SECTION2;
+typedef EFI_COMMON_SECTION_HEADER EFI_DXE_DEPEX_SECTION;
+typedef EFI_COMMON_SECTION_HEADER2 EFI_DXE_DEPEX_SECTION2;
///
/// The leaf section which contains a PI FV.
///
-typedef EFI_COMMON_SECTION_HEADER EFI_FIRMWARE_VOLUME_IMAGE_SECTION;
-typedef EFI_COMMON_SECTION_HEADER2 EFI_FIRMWARE_VOLUME_IMAGE_SECTION2;
+typedef EFI_COMMON_SECTION_HEADER EFI_FIRMWARE_VOLUME_IMAGE_SECTION;
+typedef EFI_COMMON_SECTION_HEADER2 EFI_FIRMWARE_VOLUME_IMAGE_SECTION2;
///
/// The leaf section which contains a single GUID.
@@ -334,11 +332,11 @@ typedef struct {
///
/// Common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID.
///
- EFI_COMMON_SECTION_HEADER CommonHeader;
+ EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// This GUID is defined by the creator of the file. It is a vendor-defined file type.
///
- EFI_GUID SubTypeGuid;
+ EFI_GUID SubTypeGuid;
} EFI_FREEFORM_SUBTYPE_GUID_SECTION;
typedef struct {
@@ -364,19 +362,19 @@ typedef struct {
///
/// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED.
///
- EFI_COMMON_SECTION_HEADER CommonHeader;
+ EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// The GUID that defines the format of the data that follows. It is a vendor-defined section type.
///
- EFI_GUID SectionDefinitionGuid;
+ EFI_GUID SectionDefinitionGuid;
///
/// Contains the offset in bytes from the beginning of the common header to the first byte of the data.
///
- UINT16 DataOffset;
+ UINT16 DataOffset;
///
/// The bit field that declares some specific characteristics of the section contents.
///
- UINT16 Attributes;
+ UINT16 Attributes;
} EFI_GUID_DEFINED_SECTION;
typedef struct {
@@ -401,14 +399,14 @@ typedef struct {
///
/// The leaf section which contains PE32+ image.
///
-typedef EFI_COMMON_SECTION_HEADER EFI_PE32_SECTION;
-typedef EFI_COMMON_SECTION_HEADER2 EFI_PE32_SECTION2;
+typedef EFI_COMMON_SECTION_HEADER EFI_PE32_SECTION;
+typedef EFI_COMMON_SECTION_HEADER2 EFI_PE32_SECTION2;
///
/// The leaf section used to determine the dispatch order of PEIMs.
///
-typedef EFI_COMMON_SECTION_HEADER EFI_PEI_DEPEX_SECTION;
-typedef EFI_COMMON_SECTION_HEADER2 EFI_PEI_DEPEX_SECTION2;
+typedef EFI_COMMON_SECTION_HEADER EFI_PEI_DEPEX_SECTION;
+typedef EFI_COMMON_SECTION_HEADER2 EFI_PEI_DEPEX_SECTION2;
///
/// A leaf section type that contains a position-independent-code (PIC) image.
@@ -419,20 +417,20 @@ typedef EFI_COMMON_SECTION_HEADER2 EFI_PEI_DEPEX_SECTION2;
/// execute correctly without performing any relocation or other fix-ups. EFI_PIC_SECTION2 must
/// be used if the section is 16MB or larger.
///
-typedef EFI_COMMON_SECTION_HEADER EFI_PIC_SECTION;
-typedef EFI_COMMON_SECTION_HEADER2 EFI_PIC_SECTION2;
+typedef EFI_COMMON_SECTION_HEADER EFI_PIC_SECTION;
+typedef EFI_COMMON_SECTION_HEADER2 EFI_PIC_SECTION2;
///
/// The leaf section which constains the position-independent-code image.
///
-typedef EFI_COMMON_SECTION_HEADER EFI_TE_SECTION;
-typedef EFI_COMMON_SECTION_HEADER2 EFI_TE_SECTION2;
+typedef EFI_COMMON_SECTION_HEADER EFI_TE_SECTION;
+typedef EFI_COMMON_SECTION_HEADER2 EFI_TE_SECTION2;
///
/// The leaf section which contains an array of zero or more bytes.
///
-typedef EFI_COMMON_SECTION_HEADER EFI_RAW_SECTION;
-typedef EFI_COMMON_SECTION_HEADER2 EFI_RAW_SECTION2;
+typedef EFI_COMMON_SECTION_HEADER EFI_RAW_SECTION;
+typedef EFI_COMMON_SECTION_HEADER2 EFI_RAW_SECTION2;
///
/// The SMM dependency expression section is a leaf section that contains a dependency expression that
@@ -442,7 +440,7 @@ typedef EFI_COMMON_SECTION_HEADER2 EFI_RAW_SECTION2;
/// The dependency expression may refer to protocols installed in either the UEFI or the SMM protocol
/// database. EFI_SMM_DEPEX_SECTION2 must be used if the section is 16MB or larger.
///
-typedef EFI_COMMON_SECTION_HEADER EFI_SMM_DEPEX_SECTION;
+typedef EFI_COMMON_SECTION_HEADER EFI_SMM_DEPEX_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_SMM_DEPEX_SECTION2;
///
@@ -450,12 +448,12 @@ typedef EFI_COMMON_SECTION_HEADER2 EFI_SMM_DEPEX_SECTION2;
/// is human readable file name.
///
typedef struct {
- EFI_COMMON_SECTION_HEADER CommonHeader;
+ EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// Array of unicode string.
///
- CHAR16 FileNameString[1];
+ CHAR16 FileNameString[1];
} EFI_USER_INTERFACE_SECTION;
typedef struct {
@@ -468,13 +466,13 @@ typedef struct {
/// an optional unicode string that represents the file revision.
///
typedef struct {
- EFI_COMMON_SECTION_HEADER CommonHeader;
- UINT16 BuildNumber;
+ EFI_COMMON_SECTION_HEADER CommonHeader;
+ UINT16 BuildNumber;
///
/// Array of unicode string.
///
- CHAR16 VersionString[1];
+ CHAR16 VersionString[1];
} EFI_VERSION_SECTION;
typedef struct {
@@ -492,7 +490,7 @@ typedef struct {
/// and IS_SECTION2() function-like macros below must not have side effects:
/// SectionHeaderPtr is evaluated multiple times.
///
-#define SECTION_SIZE(SectionHeaderPtr) ((UINT32) ( \
+#define SECTION_SIZE(SectionHeaderPtr) ((UINT32) (\
(((EFI_COMMON_SECTION_HEADER *) (UINTN) (SectionHeaderPtr))->Size[0] ) | \
(((EFI_COMMON_SECTION_HEADER *) (UINTN) (SectionHeaderPtr))->Size[1] << 8) | \
(((EFI_COMMON_SECTION_HEADER *) (UINTN) (SectionHeaderPtr))->Size[2] << 16)))
@@ -506,4 +504,3 @@ typedef struct {
#pragma pack()
#endif
-
diff --git a/MdePkg/Include/Pi/PiFirmwareVolume.h b/MdePkg/Include/Pi/PiFirmwareVolume.h
index ca13075b..0b038267 100644
--- a/MdePkg/Include/Pi/PiFirmwareVolume.h
+++ b/MdePkg/Include/Pi/PiFirmwareVolume.h
@@ -15,7 +15,7 @@
///
/// EFI_FV_FILE_ATTRIBUTES
///
-typedef UINT32 EFI_FV_FILE_ATTRIBUTES;
+typedef UINT32 EFI_FV_FILE_ATTRIBUTES;
//
// Value of EFI_FV_FILE_ATTRIBUTES.
@@ -27,70 +27,70 @@ typedef UINT32 EFI_FV_FILE_ATTRIBUTES;
///
/// type of EFI FVB attribute
///
-typedef UINT32 EFI_FVB_ATTRIBUTES_2;
+typedef UINT32 EFI_FVB_ATTRIBUTES_2;
//
// Attributes bit definitions
//
-#define EFI_FVB2_READ_DISABLED_CAP 0x00000001
-#define EFI_FVB2_READ_ENABLED_CAP 0x00000002
-#define EFI_FVB2_READ_STATUS 0x00000004
-#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008
-#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010
-#define EFI_FVB2_WRITE_STATUS 0x00000020
-#define EFI_FVB2_LOCK_CAP 0x00000040
-#define EFI_FVB2_LOCK_STATUS 0x00000080
-#define EFI_FVB2_STICKY_WRITE 0x00000200
-#define EFI_FVB2_MEMORY_MAPPED 0x00000400
-#define EFI_FVB2_ERASE_POLARITY 0x00000800
-#define EFI_FVB2_READ_LOCK_CAP 0x00001000
-#define EFI_FVB2_READ_LOCK_STATUS 0x00002000
-#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000
-#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000
-#define EFI_FVB2_ALIGNMENT 0x001F0000
-#define EFI_FVB2_ALIGNMENT_1 0x00000000
-#define EFI_FVB2_ALIGNMENT_2 0x00010000
-#define EFI_FVB2_ALIGNMENT_4 0x00020000
-#define EFI_FVB2_ALIGNMENT_8 0x00030000
-#define EFI_FVB2_ALIGNMENT_16 0x00040000
-#define EFI_FVB2_ALIGNMENT_32 0x00050000
-#define EFI_FVB2_ALIGNMENT_64 0x00060000
-#define EFI_FVB2_ALIGNMENT_128 0x00070000
-#define EFI_FVB2_ALIGNMENT_256 0x00080000
-#define EFI_FVB2_ALIGNMENT_512 0x00090000
-#define EFI_FVB2_ALIGNMENT_1K 0x000A0000
-#define EFI_FVB2_ALIGNMENT_2K 0x000B0000
-#define EFI_FVB2_ALIGNMENT_4K 0x000C0000
-#define EFI_FVB2_ALIGNMENT_8K 0x000D0000
-#define EFI_FVB2_ALIGNMENT_16K 0x000E0000
-#define EFI_FVB2_ALIGNMENT_32K 0x000F0000
-#define EFI_FVB2_ALIGNMENT_64K 0x00100000
-#define EFI_FVB2_ALIGNMENT_128K 0x00110000
-#define EFI_FVB2_ALIGNMENT_256K 0x00120000
-#define EFI_FVB2_ALIGNMENT_512K 0x00130000
-#define EFI_FVB2_ALIGNMENT_1M 0x00140000
-#define EFI_FVB2_ALIGNMENT_2M 0x00150000
-#define EFI_FVB2_ALIGNMENT_4M 0x00160000
-#define EFI_FVB2_ALIGNMENT_8M 0x00170000
-#define EFI_FVB2_ALIGNMENT_16M 0x00180000
-#define EFI_FVB2_ALIGNMENT_32M 0x00190000
-#define EFI_FVB2_ALIGNMENT_64M 0x001A0000
-#define EFI_FVB2_ALIGNMENT_128M 0x001B0000
-#define EFI_FVB2_ALIGNMENT_256M 0x001C0000
-#define EFI_FVB2_ALIGNMENT_512M 0x001D0000
-#define EFI_FVB2_ALIGNMENT_1G 0x001E0000
-#define EFI_FVB2_ALIGNMENT_2G 0x001F0000
-#define EFI_FVB2_WEAK_ALIGNMENT 0x80000000
+#define EFI_FVB2_READ_DISABLED_CAP 0x00000001
+#define EFI_FVB2_READ_ENABLED_CAP 0x00000002
+#define EFI_FVB2_READ_STATUS 0x00000004
+#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008
+#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010
+#define EFI_FVB2_WRITE_STATUS 0x00000020
+#define EFI_FVB2_LOCK_CAP 0x00000040
+#define EFI_FVB2_LOCK_STATUS 0x00000080
+#define EFI_FVB2_STICKY_WRITE 0x00000200
+#define EFI_FVB2_MEMORY_MAPPED 0x00000400
+#define EFI_FVB2_ERASE_POLARITY 0x00000800
+#define EFI_FVB2_READ_LOCK_CAP 0x00001000
+#define EFI_FVB2_READ_LOCK_STATUS 0x00002000
+#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000
+#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000
+#define EFI_FVB2_ALIGNMENT 0x001F0000
+#define EFI_FVB2_ALIGNMENT_1 0x00000000
+#define EFI_FVB2_ALIGNMENT_2 0x00010000
+#define EFI_FVB2_ALIGNMENT_4 0x00020000
+#define EFI_FVB2_ALIGNMENT_8 0x00030000
+#define EFI_FVB2_ALIGNMENT_16 0x00040000
+#define EFI_FVB2_ALIGNMENT_32 0x00050000
+#define EFI_FVB2_ALIGNMENT_64 0x00060000
+#define EFI_FVB2_ALIGNMENT_128 0x00070000
+#define EFI_FVB2_ALIGNMENT_256 0x00080000
+#define EFI_FVB2_ALIGNMENT_512 0x00090000
+#define EFI_FVB2_ALIGNMENT_1K 0x000A0000
+#define EFI_FVB2_ALIGNMENT_2K 0x000B0000
+#define EFI_FVB2_ALIGNMENT_4K 0x000C0000
+#define EFI_FVB2_ALIGNMENT_8K 0x000D0000
+#define EFI_FVB2_ALIGNMENT_16K 0x000E0000
+#define EFI_FVB2_ALIGNMENT_32K 0x000F0000
+#define EFI_FVB2_ALIGNMENT_64K 0x00100000
+#define EFI_FVB2_ALIGNMENT_128K 0x00110000
+#define EFI_FVB2_ALIGNMENT_256K 0x00120000
+#define EFI_FVB2_ALIGNMENT_512K 0x00130000
+#define EFI_FVB2_ALIGNMENT_1M 0x00140000
+#define EFI_FVB2_ALIGNMENT_2M 0x00150000
+#define EFI_FVB2_ALIGNMENT_4M 0x00160000
+#define EFI_FVB2_ALIGNMENT_8M 0x00170000
+#define EFI_FVB2_ALIGNMENT_16M 0x00180000
+#define EFI_FVB2_ALIGNMENT_32M 0x00190000
+#define EFI_FVB2_ALIGNMENT_64M 0x001A0000
+#define EFI_FVB2_ALIGNMENT_128M 0x001B0000
+#define EFI_FVB2_ALIGNMENT_256M 0x001C0000
+#define EFI_FVB2_ALIGNMENT_512M 0x001D0000
+#define EFI_FVB2_ALIGNMENT_1G 0x001E0000
+#define EFI_FVB2_ALIGNMENT_2G 0x001F0000
+#define EFI_FVB2_WEAK_ALIGNMENT 0x80000000
typedef struct {
///
/// The number of sequential blocks which are of the same size.
///
- UINT32 NumBlocks;
+ UINT32 NumBlocks;
///
/// The size of the blocks.
///
- UINT32 Length;
+ UINT32 Length;
} EFI_FV_BLOCK_MAP_ENTRY;
///
@@ -147,7 +147,7 @@ typedef struct {
EFI_FV_BLOCK_MAP_ENTRY BlockMap[1];
} EFI_FIRMWARE_VOLUME_HEADER;
-#define EFI_FVH_SIGNATURE SIGNATURE_32 ('_', 'F', 'V', 'H')
+#define EFI_FVH_SIGNATURE SIGNATURE_32 ('_', 'F', 'V', 'H')
///
/// Firmware Volume Header Revision definition
@@ -161,11 +161,11 @@ typedef struct {
///
/// Firmware volume name.
///
- EFI_GUID FvName;
+ EFI_GUID FvName;
///
/// Size of the rest of the extension header, including this structure.
///
- UINT32 ExtHeaderSize;
+ UINT32 ExtHeaderSize;
} EFI_FIRMWARE_VOLUME_EXT_HEADER;
///
@@ -190,12 +190,12 @@ typedef struct {
///
/// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE.
///
- EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;
+ EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;
///
/// A bit mask, one bit for each file type between 0xC0 (bit 0) and 0xDF (bit 31). If a bit
/// is '1', then the GUID entry exists in Types. If a bit is '0' then no GUID entry exists in Types.
///
- UINT32 TypeMask;
+ UINT32 TypeMask;
///
/// An array of GUIDs, each GUID representing an OEM file type.
///
@@ -203,7 +203,7 @@ typedef struct {
///
} EFI_FIRMWARE_VOLUME_EXT_ENTRY_OEM_TYPE;
-#define EFI_FV_EXT_TYPE_GUID_TYPE 0x0002
+#define EFI_FV_EXT_TYPE_GUID_TYPE 0x0002
///
/// This extension header EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE provides a vendor specific
@@ -213,11 +213,11 @@ typedef struct {
///
/// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE.
///
- EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;
+ EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;
///
/// Vendor-specific GUID.
///
- EFI_GUID FormatType;
+ EFI_GUID FormatType;
///
/// An arry of bytes of length Length.
///
@@ -225,7 +225,7 @@ typedef struct {
///
} EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE;
-#define EFI_FV_EXT_TYPE_USED_SIZE_TYPE 0x03
+#define EFI_FV_EXT_TYPE_USED_SIZE_TYPE 0x03
///
/// The EFI_FIRMWARE_VOLUME_EXT_ENTRY_USED_SIZE_TYPE can be used to find
@@ -235,13 +235,13 @@ typedef struct {
///
/// Standard extension entry, with the type EFI_FV_EXT_TYPE_USED_SIZE_TYPE.
///
- EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;
+ EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;
///
/// The number of bytes of the FV that are in uses. The remaining
/// EFI_FIRMWARE_VOLUME_HEADER FvLength minus UsedSize bytes in
/// the FV must contain the value implied by EFI_FVB2_ERASE_POLARITY.
///
- UINT32 UsedSize;
+ UINT32 UsedSize;
} EFI_FIRMWARE_VOLUME_EXT_ENTRY_USED_SIZE_TYPE;
#endif
diff --git a/MdePkg/Include/Pi/PiHob.h b/MdePkg/Include/Pi/PiHob.h
index b38b15ae..6c9095cc 100644
--- a/MdePkg/Include/Pi/PiHob.h
+++ b/MdePkg/Include/Pi/PiHob.h
@@ -48,11 +48,10 @@ typedef struct {
UINT32 Reserved;
} EFI_HOB_GENERIC_HEADER;
-
///
/// Value of version in EFI_HOB_HANDOFF_INFO_TABLE.
///
-#define EFI_HOB_HANDOFF_TABLE_VERSION 0x0009
+#define EFI_HOB_HANDOFF_TABLE_VERSION 0x0009
///
/// Contains general state information used by the HOB producer phase.
@@ -62,39 +61,39 @@ typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_HANDOFF.
///
- EFI_HOB_GENERIC_HEADER Header;
+ EFI_HOB_GENERIC_HEADER Header;
///
/// The version number pertaining to the PHIT HOB definition.
/// This value is four bytes in length to provide an 8-byte aligned entry
/// when it is combined with the 4-byte BootMode.
///
- UINT32 Version;
+ UINT32 Version;
///
/// The system boot mode as determined during the HOB producer phase.
///
- EFI_BOOT_MODE BootMode;
+ EFI_BOOT_MODE BootMode;
///
/// The highest address location of memory that is allocated for use by the HOB producer
/// phase. This address must be 4-KB aligned to meet page restrictions of UEFI.
///
- EFI_PHYSICAL_ADDRESS EfiMemoryTop;
+ EFI_PHYSICAL_ADDRESS EfiMemoryTop;
///
/// The lowest address location of memory that is allocated for use by the HOB producer phase.
///
- EFI_PHYSICAL_ADDRESS EfiMemoryBottom;
+ EFI_PHYSICAL_ADDRESS EfiMemoryBottom;
///
/// The highest address location of free memory that is currently available
/// for use by the HOB producer phase.
///
- EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop;
+ EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop;
///
/// The lowest address location of free memory that is available for use by the HOB producer phase.
///
- EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom;
+ EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom;
///
/// The end of the HOB list.
///
- EFI_PHYSICAL_ADDRESS EfiEndOfHobList;
+ EFI_PHYSICAL_ADDRESS EfiEndOfHobList;
} EFI_HOB_HANDOFF_INFO_TABLE;
///
@@ -110,31 +109,31 @@ typedef struct {
/// Type EFI_GUID is defined in InstallProtocolInterface() in the UEFI 2.0
/// specification.
///
- EFI_GUID Name;
+ EFI_GUID Name;
///
/// The base address of memory allocated by this HOB. Type
/// EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in the UEFI 2.0
/// specification.
///
- EFI_PHYSICAL_ADDRESS MemoryBaseAddress;
+ EFI_PHYSICAL_ADDRESS MemoryBaseAddress;
///
/// The length in bytes of memory allocated by this HOB.
///
- UINT64 MemoryLength;
+ UINT64 MemoryLength;
///
/// Defines the type of memory allocated by this HOB. The memory type definition
/// follows the EFI_MEMORY_TYPE definition. Type EFI_MEMORY_TYPE is defined
/// in AllocatePages() in the UEFI 2.0 specification.
///
- EFI_MEMORY_TYPE MemoryType;
+ EFI_MEMORY_TYPE MemoryType;
///
/// Padding for Itanium processor family
///
- UINT8 Reserved[4];
+ UINT8 Reserved[4];
} EFI_HOB_MEMORY_ALLOCATION_HEADER;
///
@@ -146,19 +145,18 @@ typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.
///
- EFI_HOB_GENERIC_HEADER Header;
+ EFI_HOB_GENERIC_HEADER Header;
///
/// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the
/// various attributes of the logical memory allocation.
///
- EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;
+ EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;
//
// Additional data pertaining to the "Name" Guid memory
// may go here.
//
} EFI_HOB_MEMORY_ALLOCATION;
-
///
/// Describes the memory stack that is produced by the HOB producer
/// phase and upon which all post-memory-installed executable
@@ -168,12 +166,12 @@ typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.
///
- EFI_HOB_GENERIC_HEADER Header;
+ EFI_HOB_GENERIC_HEADER Header;
///
/// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the
/// various attributes of the logical memory allocation.
///
- EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;
+ EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;
} EFI_HOB_MEMORY_ALLOCATION_STACK;
///
@@ -186,12 +184,12 @@ typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.
///
- EFI_HOB_GENERIC_HEADER Header;
+ EFI_HOB_GENERIC_HEADER Header;
///
/// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the
/// various attributes of the logical memory allocation.
///
- EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;
+ EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;
} EFI_HOB_MEMORY_ALLOCATION_BSP_STORE;
///
@@ -201,22 +199,22 @@ typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.
///
- EFI_HOB_GENERIC_HEADER Header;
+ EFI_HOB_GENERIC_HEADER Header;
///
/// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the
/// various attributes of the logical memory allocation.
///
- EFI_HOB_MEMORY_ALLOCATION_HEADER MemoryAllocationHeader;
+ EFI_HOB_MEMORY_ALLOCATION_HEADER MemoryAllocationHeader;
///
/// The GUID specifying the values of the firmware file system name
/// that contains the HOB consumer phase component.
///
- EFI_GUID ModuleName;
+ EFI_GUID ModuleName;
///
/// The address of the memory-mapped firmware volume
/// that contains the HOB consumer phase firmware file.
///
- EFI_PHYSICAL_ADDRESS EntryPoint;
+ EFI_PHYSICAL_ADDRESS EntryPoint;
} EFI_HOB_MEMORY_ALLOCATION_MODULE;
///
@@ -234,7 +232,16 @@ typedef UINT32 EFI_RESOURCE_TYPE;
#define EFI_RESOURCE_MEMORY_MAPPED_IO_PORT 0x00000004
#define EFI_RESOURCE_MEMORY_RESERVED 0x00000005
#define EFI_RESOURCE_IO_RESERVED 0x00000006
-#define EFI_RESOURCE_MAX_MEMORY_TYPE 0x00000007
+//
+// BZ3937_EFI_RESOURCE_MEMORY_UNACCEPTED is defined for unaccepted memory.
+// But this defitinion has not been officially in the PI spec. Base
+// on the code-first we define BZ3937_EFI_RESOURCE_MEMORY_UNACCEPTED at
+// MdeModulePkg/Include/Pi/PrePiHob.h and update EFI_RESOURCE_MAX_MEMORY_TYPE
+// to 8. After BZ3937_EFI_RESOURCE_MEMORY_UNACCEPTED is officially published
+// in PI spec, we will re-visit here.
+//
+// #define BZ3937_EFI_RESOURCE_MEMORY_UNACCEPTED 0x00000007
+#define EFI_RESOURCE_MAX_MEMORY_TYPE 0x00000008
///
/// A type of recount attribute type.
@@ -246,10 +253,10 @@ typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE;
//
// The following attributes are used to describe settings
//
-#define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001
-#define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002
-#define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004
-#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED 0x00000080
+#define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001
+#define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002
+#define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004
+#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED 0x00000080
//
// This is typically used as memory cacheability attribute today.
// NOTE: Since PI spec 1.4, please use EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTED
@@ -257,9 +264,9 @@ typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE;
// means Memory cacheability attribute: The memory supports being programmed with
// a writeprotected cacheable attribute.
//
-#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED 0x00000100
-#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED 0x00000200
-#define EFI_RESOURCE_ATTRIBUTE_PERSISTENT 0x00800000
+#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED 0x00000100
+#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED 0x00000200
+#define EFI_RESOURCE_ATTRIBUTE_PERSISTENT 0x00800000
//
// The rest of the attributes are used to describe capabilities
//
@@ -283,12 +290,12 @@ typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE;
// writes, and EFI_RESOURCE_ATTRIBUTE_WRITE_PROTEC TABLE means Memory cacheability attribute:
// The memory supports being programmed with a writeprotected cacheable attribute.
//
-#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTABLE 0x00200000
-#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTABLE 0x00400000
-#define EFI_RESOURCE_ATTRIBUTE_PERSISTABLE 0x01000000
+#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTABLE 0x00200000
+#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTABLE 0x00400000
+#define EFI_RESOURCE_ATTRIBUTE_PERSISTABLE 0x01000000
-#define EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTED 0x00040000
-#define EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTABLE 0x00080000
+#define EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTED 0x00040000
+#define EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTABLE 0x00080000
//
// Physical memory relative reliability attribute. This
@@ -296,7 +303,7 @@ typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE;
// memory in the system. If all memory has the same
// reliability, then this bit is not used.
//
-#define EFI_RESOURCE_ATTRIBUTE_MORE_RELIABLE 0x02000000
+#define EFI_RESOURCE_ATTRIBUTE_MORE_RELIABLE 0x02000000
///
/// Describes the resource properties of all fixed,
@@ -307,28 +314,28 @@ typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_RESOURCE_DESCRIPTOR.
///
- EFI_HOB_GENERIC_HEADER Header;
+ EFI_HOB_GENERIC_HEADER Header;
///
/// A GUID representing the owner of the resource. This GUID is used by HOB
/// consumer phase components to correlate device ownership of a resource.
///
- EFI_GUID Owner;
+ EFI_GUID Owner;
///
/// The resource type enumeration as defined by EFI_RESOURCE_TYPE.
///
- EFI_RESOURCE_TYPE ResourceType;
+ EFI_RESOURCE_TYPE ResourceType;
///
/// Resource attributes as defined by EFI_RESOURCE_ATTRIBUTE_TYPE.
///
- EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
///
/// The physical start address of the resource region.
///
- EFI_PHYSICAL_ADDRESS PhysicalStart;
+ EFI_PHYSICAL_ADDRESS PhysicalStart;
///
/// The number of bytes of the resource region.
///
- UINT64 ResourceLength;
+ UINT64 ResourceLength;
} EFI_HOB_RESOURCE_DESCRIPTOR;
///
@@ -339,11 +346,11 @@ typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_GUID_EXTENSION.
///
- EFI_HOB_GENERIC_HEADER Header;
+ EFI_HOB_GENERIC_HEADER Header;
///
/// A GUID that defines the contents of this HOB.
///
- EFI_GUID Name;
+ EFI_GUID Name;
//
// Guid specific data goes here
//
@@ -356,15 +363,15 @@ typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_FV.
///
- EFI_HOB_GENERIC_HEADER Header;
+ EFI_HOB_GENERIC_HEADER Header;
///
/// The physical memory-mapped base address of the firmware volume.
///
- EFI_PHYSICAL_ADDRESS BaseAddress;
+ EFI_PHYSICAL_ADDRESS BaseAddress;
///
/// The length in bytes of the firmware volume.
///
- UINT64 Length;
+ UINT64 Length;
} EFI_HOB_FIRMWARE_VOLUME;
///
@@ -375,23 +382,23 @@ typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_FV2.
///
- EFI_HOB_GENERIC_HEADER Header;
+ EFI_HOB_GENERIC_HEADER Header;
///
/// The physical memory-mapped base address of the firmware volume.
///
- EFI_PHYSICAL_ADDRESS BaseAddress;
+ EFI_PHYSICAL_ADDRESS BaseAddress;
///
/// The length in bytes of the firmware volume.
///
- UINT64 Length;
+ UINT64 Length;
///
/// The name of the firmware volume.
///
- EFI_GUID FvName;
+ EFI_GUID FvName;
///
/// The name of the firmware file that contained this firmware volume.
///
- EFI_GUID FileName;
+ EFI_GUID FileName;
} EFI_HOB_FIRMWARE_VOLUME2;
///
@@ -402,34 +409,34 @@ typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_FV3.
///
- EFI_HOB_GENERIC_HEADER Header;
+ EFI_HOB_GENERIC_HEADER Header;
///
/// The physical memory-mapped base address of the firmware volume.
///
- EFI_PHYSICAL_ADDRESS BaseAddress;
+ EFI_PHYSICAL_ADDRESS BaseAddress;
///
/// The length in bytes of the firmware volume.
///
- UINT64 Length;
+ UINT64 Length;
///
/// The authentication status.
///
- UINT32 AuthenticationStatus;
+ UINT32 AuthenticationStatus;
///
/// TRUE if the FV was extracted as a file within another firmware volume.
/// FALSE otherwise.
///
- BOOLEAN ExtractedFv;
+ BOOLEAN ExtractedFv;
///
/// The name of the firmware volume.
/// Valid only if IsExtractedFv is TRUE.
///
- EFI_GUID FvName;
+ EFI_GUID FvName;
///
/// The name of the firmware file that contained this firmware volume.
/// Valid only if IsExtractedFv is TRUE.
///
- EFI_GUID FileName;
+ EFI_GUID FileName;
} EFI_HOB_FIRMWARE_VOLUME3;
///
@@ -439,22 +446,21 @@ typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_CPU.
///
- EFI_HOB_GENERIC_HEADER Header;
+ EFI_HOB_GENERIC_HEADER Header;
///
/// Identifies the maximum physical memory addressability of the processor.
///
- UINT8 SizeOfMemorySpace;
+ UINT8 SizeOfMemorySpace;
///
/// Identifies the maximum physical I/O addressability of the processor.
///
- UINT8 SizeOfIoSpace;
+ UINT8 SizeOfIoSpace;
///
/// This field will always be set to zero.
///
- UINT8 Reserved[6];
+ UINT8 Reserved[6];
} EFI_HOB_CPU;
-
///
/// Describes pool memory allocations.
///
@@ -462,7 +468,7 @@ typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_POOL.
///
- EFI_HOB_GENERIC_HEADER Header;
+ EFI_HOB_GENERIC_HEADER Header;
} EFI_HOB_MEMORY_POOL;
///
@@ -476,37 +482,36 @@ typedef struct {
///
/// The HOB generic header where Header.HobType = EFI_HOB_TYPE_UEFI_CAPSULE.
///
- EFI_HOB_GENERIC_HEADER Header;
+ EFI_HOB_GENERIC_HEADER Header;
///
/// The physical memory-mapped base address of an UEFI capsule. This value is set to
/// point to the base of the contiguous memory of the UEFI capsule.
/// The length of the contiguous memory in bytes.
///
- EFI_PHYSICAL_ADDRESS BaseAddress;
- UINT64 Length;
+ EFI_PHYSICAL_ADDRESS BaseAddress;
+ UINT64 Length;
} EFI_HOB_UEFI_CAPSULE;
///
/// Union of all the possible HOB Types.
///
typedef union {
- EFI_HOB_GENERIC_HEADER *Header;
- EFI_HOB_HANDOFF_INFO_TABLE *HandoffInformationTable;
- EFI_HOB_MEMORY_ALLOCATION *MemoryAllocation;
- EFI_HOB_MEMORY_ALLOCATION_BSP_STORE *MemoryAllocationBspStore;
- EFI_HOB_MEMORY_ALLOCATION_STACK *MemoryAllocationStack;
- EFI_HOB_MEMORY_ALLOCATION_MODULE *MemoryAllocationModule;
- EFI_HOB_RESOURCE_DESCRIPTOR *ResourceDescriptor;
- EFI_HOB_GUID_TYPE *Guid;
- EFI_HOB_FIRMWARE_VOLUME *FirmwareVolume;
- EFI_HOB_FIRMWARE_VOLUME2 *FirmwareVolume2;
- EFI_HOB_FIRMWARE_VOLUME3 *FirmwareVolume3;
- EFI_HOB_CPU *Cpu;
- EFI_HOB_MEMORY_POOL *Pool;
- EFI_HOB_UEFI_CAPSULE *Capsule;
- UINT8 *Raw;
+ EFI_HOB_GENERIC_HEADER *Header;
+ EFI_HOB_HANDOFF_INFO_TABLE *HandoffInformationTable;
+ EFI_HOB_MEMORY_ALLOCATION *MemoryAllocation;
+ EFI_HOB_MEMORY_ALLOCATION_BSP_STORE *MemoryAllocationBspStore;
+ EFI_HOB_MEMORY_ALLOCATION_STACK *MemoryAllocationStack;
+ EFI_HOB_MEMORY_ALLOCATION_MODULE *MemoryAllocationModule;
+ EFI_HOB_RESOURCE_DESCRIPTOR *ResourceDescriptor;
+ EFI_HOB_GUID_TYPE *Guid;
+ EFI_HOB_FIRMWARE_VOLUME *FirmwareVolume;
+ EFI_HOB_FIRMWARE_VOLUME2 *FirmwareVolume2;
+ EFI_HOB_FIRMWARE_VOLUME3 *FirmwareVolume3;
+ EFI_HOB_CPU *Cpu;
+ EFI_HOB_MEMORY_POOL *Pool;
+ EFI_HOB_UEFI_CAPSULE *Capsule;
+ UINT8 *Raw;
} EFI_PEI_HOB_POINTERS;
-
#endif
diff --git a/MdePkg/Include/Pi/PiMultiPhase.h b/MdePkg/Include/Pi/PiMultiPhase.h
index 04624d46..bb01db16 100644
--- a/MdePkg/Include/Pi/PiMultiPhase.h
+++ b/MdePkg/Include/Pi/PiMultiPhase.h
@@ -44,26 +44,26 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
/// If this value is returned by an API, it means the capability is not yet
/// installed/available/ready to use.
///
-#define EFI_NOT_AVAILABLE_YET DXE_ERROR (2)
+#define EFI_NOT_AVAILABLE_YET DXE_ERROR (2)
///
/// Success and warning codes reserved for use by PI.
/// Supported 32-bit range is 0x20000000-0x3fffffff.
/// Supported 64-bit range is 0x2000000000000000-0x3fffffffffffffff.
///
-#define PI_ENCODE_WARNING(a) ((MAX_BIT >> 2) | (a))
+#define PI_ENCODE_WARNING(a) ((MAX_BIT >> 2) | (a))
///
/// Error codes reserved for use by PI.
/// Supported 32-bit range is 0xa0000000-0xbfffffff.
/// Supported 64-bit range is 0xa000000000000000-0xbfffffffffffffff.
///
-#define PI_ENCODE_ERROR(a) (MAX_BIT | (MAX_BIT >> 2) | (a))
+#define PI_ENCODE_ERROR(a) (MAX_BIT | (MAX_BIT >> 2) | (a))
///
/// Return status codes defined in SMM CIS.
///
-#define EFI_INTERRUPT_PENDING PI_ENCODE_ERROR (0)
+#define EFI_INTERRUPT_PENDING PI_ENCODE_ERROR (0)
#define EFI_WARN_INTERRUPT_SOURCE_PENDING PI_ENCODE_WARNING (0)
#define EFI_WARN_INTERRUPT_SOURCE_QUIESCED PI_ENCODE_WARNING (1)
@@ -81,27 +81,27 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
/// 1010 Image was signed, the signature was tested, and the signature failed the authentication test.
///
///@{
-#define EFI_AUTH_STATUS_PLATFORM_OVERRIDE 0x01
-#define EFI_AUTH_STATUS_IMAGE_SIGNED 0x02
-#define EFI_AUTH_STATUS_NOT_TESTED 0x04
-#define EFI_AUTH_STATUS_TEST_FAILED 0x08
-#define EFI_AUTH_STATUS_ALL 0x0f
+#define EFI_AUTH_STATUS_PLATFORM_OVERRIDE 0x01
+#define EFI_AUTH_STATUS_IMAGE_SIGNED 0x02
+#define EFI_AUTH_STATUS_NOT_TESTED 0x04
+#define EFI_AUTH_STATUS_TEST_FAILED 0x08
+#define EFI_AUTH_STATUS_ALL 0x0f
///@}
///
/// MMRAM states and capabilities
///
-#define EFI_MMRAM_OPEN 0x00000001
-#define EFI_MMRAM_CLOSED 0x00000002
-#define EFI_MMRAM_LOCKED 0x00000004
-#define EFI_CACHEABLE 0x00000008
-#define EFI_ALLOCATED 0x00000010
-#define EFI_NEEDS_TESTING 0x00000020
-#define EFI_NEEDS_ECC_INITIALIZATION 0x00000040
+#define EFI_MMRAM_OPEN 0x00000001
+#define EFI_MMRAM_CLOSED 0x00000002
+#define EFI_MMRAM_LOCKED 0x00000004
+#define EFI_CACHEABLE 0x00000008
+#define EFI_ALLOCATED 0x00000010
+#define EFI_NEEDS_TESTING 0x00000020
+#define EFI_NEEDS_ECC_INITIALIZATION 0x00000040
-#define EFI_SMRAM_OPEN EFI_MMRAM_OPEN
-#define EFI_SMRAM_CLOSED EFI_MMRAM_CLOSED
-#define EFI_SMRAM_LOCKED EFI_MMRAM_LOCKED
+#define EFI_SMRAM_OPEN EFI_MMRAM_OPEN
+#define EFI_SMRAM_CLOSED EFI_MMRAM_CLOSED
+#define EFI_SMRAM_LOCKED EFI_MMRAM_LOCKED
///
/// Structure describing a MMRAM region and its accessibility attributes.
@@ -112,26 +112,26 @@ typedef struct {
/// the same as seen by I/O-based agents, for example, but it may not be the address seen
/// by the processors.
///
- EFI_PHYSICAL_ADDRESS PhysicalStart;
+ EFI_PHYSICAL_ADDRESS PhysicalStart;
///
/// Designates the address of the MMRAM, as seen by software executing on the
/// processors. This address may or may not match PhysicalStart.
///
- EFI_PHYSICAL_ADDRESS CpuStart;
+ EFI_PHYSICAL_ADDRESS CpuStart;
///
/// Describes the number of bytes in the MMRAM region.
///
- UINT64 PhysicalSize;
+ UINT64 PhysicalSize;
///
/// Describes the accessibility attributes of the MMRAM. These attributes include the
/// hardware state (e.g., Open/Closed/Locked), capability (e.g., cacheable), logical
/// allocation (e.g., allocated), and pre-use initialization (e.g., needs testing/ECC
/// initialization).
///
- UINT64 RegionState;
+ UINT64 RegionState;
} EFI_MMRAM_DESCRIPTOR;
-typedef EFI_MMRAM_DESCRIPTOR EFI_SMRAM_DESCRIPTOR;
+typedef EFI_MMRAM_DESCRIPTOR EFI_SMRAM_DESCRIPTOR;
///
/// Structure describing a MMRAM region which cannot be used for the MMRAM heap.
@@ -163,19 +163,19 @@ typedef struct {
/// The returned information associated with the requested TokenNumber. If
/// TokenNumber is 0, then PcdType is set to EFI_PCD_TYPE_8.
///
- EFI_PCD_TYPE PcdType;
+ EFI_PCD_TYPE PcdType;
///
/// The size of the data in bytes associated with the TokenNumber specified. If
/// TokenNumber is 0, then PcdSize is set 0.
///
- UINTN PcdSize;
+ UINTN PcdSize;
///
/// The null-terminated ASCII string associated with a given token. If the
/// TokenNumber specified was 0, then this field corresponds to the null-terminated
/// ASCII string associated with the token's namespace Guid. If NULL, there is no
/// name associated with this request.
///
- CHAR8 *PcdName;
+ CHAR8 *PcdName;
} EFI_PCD_INFO;
/**
@@ -206,6 +206,6 @@ typedef
EFI_STATUS
(EFIAPI *EFI_AP_PROCEDURE2)(
IN VOID *ProcedureArgument
-);
+ );
#endif
diff --git a/MdePkg/Include/Pi/PiPeiCis.h b/MdePkg/Include/Pi/PiPeiCis.h
index 3f25f58c..7271ea95 100644
--- a/MdePkg/Include/Pi/PiPeiCis.h
+++ b/MdePkg/Include/Pi/PiPeiCis.h
@@ -18,28 +18,26 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
///
/// The handles of EFI FV.
///
-typedef VOID *EFI_PEI_FV_HANDLE;
+typedef VOID *EFI_PEI_FV_HANDLE;
///
/// The handles of EFI FFS.
///
-typedef VOID *EFI_PEI_FILE_HANDLE;
+typedef VOID *EFI_PEI_FILE_HANDLE;
///
/// Declare the forward reference data structure for EFI_PEI_SERVICE.
///
-typedef struct _EFI_PEI_SERVICES EFI_PEI_SERVICES;
+typedef struct _EFI_PEI_SERVICES EFI_PEI_SERVICES;
///
/// Declare the forward reference data structure for EFI_PEI_NOTIFY_DESCRIPTOR.
///
typedef struct _EFI_PEI_NOTIFY_DESCRIPTOR EFI_PEI_NOTIFY_DESCRIPTOR;
-
#include
#include
-
/**
The PEI Dispatcher will invoke each PEIM one time. During this pass, the PEI
Dispatcher will pass control to the PEIM at the AddressOfEntryPoint in the PE Header.
@@ -94,15 +92,15 @@ typedef struct {
/// This field is a set of flags describing the characteristics of this imported table entry.
/// All flags are defined as EFI_PEI_PPI_DESCRIPTOR_***, which can also be combined into one.
///
- UINTN Flags;
+ UINTN Flags;
///
/// The address of the EFI_GUID that names the interface.
///
- EFI_GUID *Guid;
+ EFI_GUID *Guid;
///
/// A pointer to the PPI. It contains the information necessary to install a service.
///
- VOID *Ppi;
+ VOID *Ppi;
} EFI_PEI_PPI_DESCRIPTOR;
///
@@ -113,15 +111,15 @@ struct _EFI_PEI_NOTIFY_DESCRIPTOR {
///
/// Details if the type of notification are callback or dispatch.
///
- UINTN Flags;
+ UINTN Flags;
///
/// The address of the EFI_GUID that names the interface.
///
- EFI_GUID *Guid;
+ EFI_GUID *Guid;
///
/// Address of the notification callback function itself within the PEIM.
///
- EFI_PEIM_NOTIFY_ENTRY_POINT Notify;
+ EFI_PEIM_NOTIFY_ENTRY_POINT Notify;
};
///
@@ -132,11 +130,11 @@ typedef union {
///
/// The typedef structure of the notification descriptor.
///
- EFI_PEI_NOTIFY_DESCRIPTOR Notify;
+ EFI_PEI_NOTIFY_DESCRIPTOR Notify;
///
/// The typedef structure of the PPI descriptor.
///
- EFI_PEI_PPI_DESCRIPTOR Ppi;
+ EFI_PEI_PPI_DESCRIPTOR Ppi;
} EFI_PEI_DESCRIPTOR;
/**
@@ -487,7 +485,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
-(EFIAPI *EFI_PEI_FREE_PAGES) (
+(EFIAPI *EFI_PEI_FREE_PAGES)(
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PHYSICAL_ADDRESS Memory,
IN UINTN Pages
@@ -619,7 +617,7 @@ EFI_STATUS
**/
typedef
VOID
-(EFIAPI *EFI_PEI_RESET2_SYSTEM) (
+(EFIAPI *EFI_PEI_RESET2_SYSTEM)(
IN EFI_RESET_TYPE ResetType,
IN EFI_STATUS ResetStatus,
IN UINTN DataSize,
@@ -661,25 +659,25 @@ typedef struct {
///
/// Name of the file.
///
- EFI_GUID FileName;
+ EFI_GUID FileName;
///
/// File type.
///
- EFI_FV_FILETYPE FileType;
+ EFI_FV_FILETYPE FileType;
///
/// Attributes of the file.
///
- EFI_FV_FILE_ATTRIBUTES FileAttributes;
+ EFI_FV_FILE_ATTRIBUTES FileAttributes;
///
/// Points to the file's data (not the header).
/// Not valid if EFI_FV_FILE_ATTRIB_MEMORY_MAPPED
/// is zero.
///
- VOID *Buffer;
+ VOID *Buffer;
///
/// Size of the file's data.
///
- UINT32 BufferSize;
+ UINT32 BufferSize;
} EFI_FV_FILE_INFO;
///
@@ -689,29 +687,29 @@ typedef struct {
///
/// Name of the file.
///
- EFI_GUID FileName;
+ EFI_GUID FileName;
///
/// File type.
///
- EFI_FV_FILETYPE FileType;
+ EFI_FV_FILETYPE FileType;
///
/// Attributes of the file.
///
- EFI_FV_FILE_ATTRIBUTES FileAttributes;
+ EFI_FV_FILE_ATTRIBUTES FileAttributes;
///
/// Points to the file's data (not the header).
/// Not valid if EFI_FV_FILE_ATTRIB_MEMORY_MAPPED
/// is zero.
///
- VOID *Buffer;
+ VOID *Buffer;
///
/// Size of the file's data.
///
- UINT32 BufferSize;
+ UINT32 BufferSize;
///
/// Authentication status for this file.
///
- UINT32 AuthenticationStatus;
+ UINT32 AuthenticationStatus;
} EFI_FV_FILE_INFO2;
/**
@@ -770,25 +768,25 @@ typedef struct {
///
/// Attributes of the firmware volume.
///
- EFI_FVB_ATTRIBUTES_2 FvAttributes;
+ EFI_FVB_ATTRIBUTES_2 FvAttributes;
///
/// Format of the firmware volume.
///
- EFI_GUID FvFormat;
+ EFI_GUID FvFormat;
///
/// Name of the firmware volume.
///
- EFI_GUID FvName;
+ EFI_GUID FvName;
///
/// Points to the first byte of the firmware
/// volume, if bit EFI_FVB_MEMORY_MAPPED is
/// set in FvAttributes.
///
- VOID *FvStart;
+ VOID *FvStart;
///
/// Size of the firmware volume.
///
- UINT64 FvSize;
+ UINT64 FvSize;
} EFI_FV_INFO;
/**
@@ -845,7 +843,6 @@ EFI_STATUS
IN EFI_PEI_FILE_HANDLE FileHandle
);
-
//
// PEI Specification Revision information
//
@@ -866,7 +863,7 @@ EFI_STATUS
/// #define ((PEI_SPECIFICATION_MAJOR_REVISION<<16) |(PEI_SPECIFICATION_MINOR_REVISION))
/// and it should be as follows:
///
-#define PEI_SERVICES_REVISION ((PEI_SPECIFICATION_MAJOR_REVISION<<16) | (PEI_SPECIFICATION_MINOR_REVISION))
+#define PEI_SERVICES_REVISION ((PEI_SPECIFICATION_MAJOR_REVISION<<16) | (PEI_SPECIFICATION_MINOR_REVISION))
///
/// EFI_PEI_SERVICES is a collection of functions whose implementation is provided by the PEI
@@ -881,75 +878,74 @@ struct _EFI_PEI_SERVICES {
///
/// The table header for the PEI Services Table.
///
- EFI_TABLE_HEADER Hdr;
+ EFI_TABLE_HEADER Hdr;
//
// PPI Functions
//
- EFI_PEI_INSTALL_PPI InstallPpi;
- EFI_PEI_REINSTALL_PPI ReInstallPpi;
- EFI_PEI_LOCATE_PPI LocatePpi;
- EFI_PEI_NOTIFY_PPI NotifyPpi;
+ EFI_PEI_INSTALL_PPI InstallPpi;
+ EFI_PEI_REINSTALL_PPI ReInstallPpi;
+ EFI_PEI_LOCATE_PPI LocatePpi;
+ EFI_PEI_NOTIFY_PPI NotifyPpi;
//
// Boot Mode Functions
//
- EFI_PEI_GET_BOOT_MODE GetBootMode;
- EFI_PEI_SET_BOOT_MODE SetBootMode;
+ EFI_PEI_GET_BOOT_MODE GetBootMode;
+ EFI_PEI_SET_BOOT_MODE SetBootMode;
//
// HOB Functions
//
- EFI_PEI_GET_HOB_LIST GetHobList;
- EFI_PEI_CREATE_HOB CreateHob;
+ EFI_PEI_GET_HOB_LIST GetHobList;
+ EFI_PEI_CREATE_HOB CreateHob;
//
// Firmware Volume Functions
//
- EFI_PEI_FFS_FIND_NEXT_VOLUME2 FfsFindNextVolume;
- EFI_PEI_FFS_FIND_NEXT_FILE2 FfsFindNextFile;
- EFI_PEI_FFS_FIND_SECTION_DATA2 FfsFindSectionData;
+ EFI_PEI_FFS_FIND_NEXT_VOLUME2 FfsFindNextVolume;
+ EFI_PEI_FFS_FIND_NEXT_FILE2 FfsFindNextFile;
+ EFI_PEI_FFS_FIND_SECTION_DATA2 FfsFindSectionData;
//
// PEI Memory Functions
//
- EFI_PEI_INSTALL_PEI_MEMORY InstallPeiMemory;
- EFI_PEI_ALLOCATE_PAGES AllocatePages;
- EFI_PEI_ALLOCATE_POOL AllocatePool;
- EFI_PEI_COPY_MEM CopyMem;
- EFI_PEI_SET_MEM SetMem;
+ EFI_PEI_INSTALL_PEI_MEMORY InstallPeiMemory;
+ EFI_PEI_ALLOCATE_PAGES AllocatePages;
+ EFI_PEI_ALLOCATE_POOL AllocatePool;
+ EFI_PEI_COPY_MEM CopyMem;
+ EFI_PEI_SET_MEM SetMem;
//
// Status Code
//
- EFI_PEI_REPORT_STATUS_CODE ReportStatusCode;
+ EFI_PEI_REPORT_STATUS_CODE ReportStatusCode;
//
// Reset
//
- EFI_PEI_RESET_SYSTEM ResetSystem;
+ EFI_PEI_RESET_SYSTEM ResetSystem;
//
// (the following interfaces are installed by publishing PEIM)
// I/O Abstractions
//
- EFI_PEI_CPU_IO_PPI *CpuIo;
- EFI_PEI_PCI_CFG2_PPI *PciCfg;
+ EFI_PEI_CPU_IO_PPI *CpuIo;
+ EFI_PEI_PCI_CFG2_PPI *PciCfg;
//
// Future Installed Services
//
- EFI_PEI_FFS_FIND_BY_NAME FfsFindFileByName;
- EFI_PEI_FFS_GET_FILE_INFO FfsGetFileInfo;
- EFI_PEI_FFS_GET_VOLUME_INFO FfsGetVolumeInfo;
- EFI_PEI_REGISTER_FOR_SHADOW RegisterForShadow;
- EFI_PEI_FFS_FIND_SECTION_DATA3 FindSectionData3;
- EFI_PEI_FFS_GET_FILE_INFO2 FfsGetFileInfo2;
- EFI_PEI_RESET2_SYSTEM ResetSystem2;
- EFI_PEI_FREE_PAGES FreePages;
+ EFI_PEI_FFS_FIND_BY_NAME FfsFindFileByName;
+ EFI_PEI_FFS_GET_FILE_INFO FfsGetFileInfo;
+ EFI_PEI_FFS_GET_VOLUME_INFO FfsGetVolumeInfo;
+ EFI_PEI_REGISTER_FOR_SHADOW RegisterForShadow;
+ EFI_PEI_FFS_FIND_SECTION_DATA3 FindSectionData3;
+ EFI_PEI_FFS_GET_FILE_INFO2 FfsGetFileInfo2;
+ EFI_PEI_RESET2_SYSTEM ResetSystem2;
+ EFI_PEI_FREE_PAGES FreePages;
};
-
///
/// EFI_SEC_PEI_HAND_OFF structure holds information about
/// PEI core's operating environment, such as the size of location of
@@ -959,29 +955,29 @@ typedef struct _EFI_SEC_PEI_HAND_OFF {
///
/// Size of the data structure.
///
- UINT16 DataSize;
+ UINT16 DataSize;
///
/// Points to the first byte of the boot firmware volume,
/// which the PEI Dispatcher should search for
/// PEI modules.
///
- VOID *BootFirmwareVolumeBase;
+ VOID *BootFirmwareVolumeBase;
///
/// Size of the boot firmware volume, in bytes.
///
- UINTN BootFirmwareVolumeSize;
+ UINTN BootFirmwareVolumeSize;
///
/// Points to the first byte of the temporary RAM.
///
- VOID *TemporaryRamBase;
+ VOID *TemporaryRamBase;
///
/// Size of the temporary RAM, in bytes.
///
- UINTN TemporaryRamSize;
+ UINTN TemporaryRamSize;
///
/// Points to the first byte of the temporary RAM
@@ -992,13 +988,13 @@ typedef struct _EFI_SEC_PEI_HAND_OFF {
/// overlap with the area reported by StackBase and
/// StackSize.
///
- VOID *PeiTemporaryRamBase;
+ VOID *PeiTemporaryRamBase;
///
/// The size of the available temporary RAM available for
/// use by the PEI Foundation, in bytes.
///
- UINTN PeiTemporaryRamSize;
+ UINTN PeiTemporaryRamSize;
///
/// Points to the first byte of the stack.
@@ -1006,15 +1002,14 @@ typedef struct _EFI_SEC_PEI_HAND_OFF {
/// TemporaryRamBase and TemporaryRamSize
/// or may be an entirely separate area.
///
- VOID *StackBase;
+ VOID *StackBase;
///
/// Size of the stack, in bytes.
///
- UINTN StackSize;
+ UINTN StackSize;
} EFI_SEC_PEI_HAND_OFF;
-
/**
The entry point of PEI Foundation.
@@ -1056,6 +1051,6 @@ VOID
(EFIAPI *EFI_PEI_CORE_ENTRY_POINT)(
IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,
IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList
-);
+ );
#endif
diff --git a/MdePkg/Include/Pi/PiS3BootScript.h b/MdePkg/Include/Pi/PiS3BootScript.h
index b1c4de28..4779556a 100644
--- a/MdePkg/Include/Pi/PiS3BootScript.h
+++ b/MdePkg/Include/Pi/PiS3BootScript.h
@@ -10,30 +10,30 @@
#ifndef _PI_S3_BOOT_SCRIPT_H_
#define _PI_S3_BOOT_SCRIPT_H_
-//*******************************************
+// *******************************************
// EFI Boot Script Opcode definitions
-//*******************************************
-#define EFI_BOOT_SCRIPT_IO_WRITE_OPCODE 0x00
-#define EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE 0x01
-#define EFI_BOOT_SCRIPT_MEM_WRITE_OPCODE 0x02
-#define EFI_BOOT_SCRIPT_MEM_READ_WRITE_OPCODE 0x03
-#define EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE 0x04
-#define EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE 0x05
-#define EFI_BOOT_SCRIPT_SMBUS_EXECUTE_OPCODE 0x06
-#define EFI_BOOT_SCRIPT_STALL_OPCODE 0x07
-#define EFI_BOOT_SCRIPT_DISPATCH_OPCODE 0x08
-#define EFI_BOOT_SCRIPT_DISPATCH_2_OPCODE 0x09
-#define EFI_BOOT_SCRIPT_INFORMATION_OPCODE 0x0A
-#define EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE 0x0B
-#define EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE_OPCODE 0x0C
-#define EFI_BOOT_SCRIPT_IO_POLL_OPCODE 0x0D
-#define EFI_BOOT_SCRIPT_MEM_POLL_OPCODE 0x0E
-#define EFI_BOOT_SCRIPT_PCI_CONFIG_POLL_OPCODE 0x0F
-#define EFI_BOOT_SCRIPT_PCI_CONFIG2_POLL_OPCODE 0x10
+// *******************************************
+#define EFI_BOOT_SCRIPT_IO_WRITE_OPCODE 0x00
+#define EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE 0x01
+#define EFI_BOOT_SCRIPT_MEM_WRITE_OPCODE 0x02
+#define EFI_BOOT_SCRIPT_MEM_READ_WRITE_OPCODE 0x03
+#define EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE 0x04
+#define EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE 0x05
+#define EFI_BOOT_SCRIPT_SMBUS_EXECUTE_OPCODE 0x06
+#define EFI_BOOT_SCRIPT_STALL_OPCODE 0x07
+#define EFI_BOOT_SCRIPT_DISPATCH_OPCODE 0x08
+#define EFI_BOOT_SCRIPT_DISPATCH_2_OPCODE 0x09
+#define EFI_BOOT_SCRIPT_INFORMATION_OPCODE 0x0A
+#define EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE 0x0B
+#define EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE_OPCODE 0x0C
+#define EFI_BOOT_SCRIPT_IO_POLL_OPCODE 0x0D
+#define EFI_BOOT_SCRIPT_MEM_POLL_OPCODE 0x0E
+#define EFI_BOOT_SCRIPT_PCI_CONFIG_POLL_OPCODE 0x0F
+#define EFI_BOOT_SCRIPT_PCI_CONFIG2_POLL_OPCODE 0x10
-//*******************************************
+// *******************************************
// EFI_BOOT_SCRIPT_WIDTH
-//*******************************************
+// *******************************************
typedef enum {
EfiBootScriptWidthUint8,
EfiBootScriptWidthUint16,
diff --git a/MdePkg/Include/Pi/PiStatusCode.h b/MdePkg/Include/Pi/PiStatusCode.h
index e484f202..2daa8887 100644
--- a/MdePkg/Include/Pi/PiStatusCode.h
+++ b/MdePkg/Include/Pi/PiStatusCode.h
@@ -21,7 +21,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
///
/// Status Code Type Definition.
///
-typedef UINT32 EFI_STATUS_CODE_TYPE;
+typedef UINT32 EFI_STATUS_CODE_TYPE;
///
/// A Status Code Type is made up of the code type and severity.
@@ -29,9 +29,9 @@ typedef UINT32 EFI_STATUS_CODE_TYPE;
/// reserved for use by this specification.
///
///@{
-#define EFI_STATUS_CODE_TYPE_MASK 0x000000FF
-#define EFI_STATUS_CODE_SEVERITY_MASK 0xFF000000
-#define EFI_STATUS_CODE_RESERVED_MASK 0x00FFFF00
+#define EFI_STATUS_CODE_TYPE_MASK 0x000000FF
+#define EFI_STATUS_CODE_SEVERITY_MASK 0xFF000000
+#define EFI_STATUS_CODE_RESERVED_MASK 0x00FFFF00
///@}
///
@@ -40,9 +40,9 @@ typedef UINT32 EFI_STATUS_CODE_TYPE;
/// this specification.
///
///@{
-#define EFI_PROGRESS_CODE 0x00000001
-#define EFI_ERROR_CODE 0x00000002
-#define EFI_DEBUG_CODE 0x00000003
+#define EFI_PROGRESS_CODE 0x00000001
+#define EFI_ERROR_CODE 0x00000002
+#define EFI_DEBUG_CODE 0x00000003
///@}
///
@@ -55,10 +55,10 @@ typedef UINT32 EFI_STATUS_CODE_TYPE;
/// the bad data could be consumed by other drivers.
///
///@{
-#define EFI_ERROR_MINOR 0x40000000
-#define EFI_ERROR_MAJOR 0x80000000
-#define EFI_ERROR_UNRECOVERED 0x90000000
-#define EFI_ERROR_UNCONTAINED 0xa0000000
+#define EFI_ERROR_MINOR 0x40000000
+#define EFI_ERROR_MAJOR 0x80000000
+#define EFI_ERROR_UNRECOVERED 0x90000000
+#define EFI_ERROR_UNCONTAINED 0xa0000000
///@}
///
@@ -85,15 +85,15 @@ typedef struct {
///
/// The size of the structure. This is specified to enable future expansion.
///
- UINT16 HeaderSize;
+ UINT16 HeaderSize;
///
/// The size of the data in bytes. This does not include the size of the header structure.
///
- UINT16 Size;
+ UINT16 Size;
///
/// The GUID defining the type of the data.
///
- EFI_GUID Type;
+ EFI_GUID Type;
} EFI_STATUS_CODE_DATA;
///
@@ -102,8 +102,8 @@ typedef struct {
/// - 0x1000-0x7FFF Subclass Specific.
/// - 0x8000-0xFFFF OEM specific.
///@{
-#define EFI_SUBCLASS_SPECIFIC 0x1000
-#define EFI_OEM_SPECIFIC 0x8000
+#define EFI_SUBCLASS_SPECIFIC 0x1000
+#define EFI_OEM_SPECIFIC 0x8000
///@}
///
@@ -133,13 +133,13 @@ typedef struct {
/// Values of 128-255 are reserved for OEM use.
///
///@{
-#define EFI_COMPUTING_UNIT_UNSPECIFIED (EFI_COMPUTING_UNIT | 0x00000000)
-#define EFI_COMPUTING_UNIT_HOST_PROCESSOR (EFI_COMPUTING_UNIT | 0x00010000)
-#define EFI_COMPUTING_UNIT_FIRMWARE_PROCESSOR (EFI_COMPUTING_UNIT | 0x00020000)
-#define EFI_COMPUTING_UNIT_IO_PROCESSOR (EFI_COMPUTING_UNIT | 0x00030000)
-#define EFI_COMPUTING_UNIT_CACHE (EFI_COMPUTING_UNIT | 0x00040000)
-#define EFI_COMPUTING_UNIT_MEMORY (EFI_COMPUTING_UNIT | 0x00050000)
-#define EFI_COMPUTING_UNIT_CHIPSET (EFI_COMPUTING_UNIT | 0x00060000)
+#define EFI_COMPUTING_UNIT_UNSPECIFIED (EFI_COMPUTING_UNIT | 0x00000000)
+#define EFI_COMPUTING_UNIT_HOST_PROCESSOR (EFI_COMPUTING_UNIT | 0x00010000)
+#define EFI_COMPUTING_UNIT_FIRMWARE_PROCESSOR (EFI_COMPUTING_UNIT | 0x00020000)
+#define EFI_COMPUTING_UNIT_IO_PROCESSOR (EFI_COMPUTING_UNIT | 0x00030000)
+#define EFI_COMPUTING_UNIT_CACHE (EFI_COMPUTING_UNIT | 0x00040000)
+#define EFI_COMPUTING_UNIT_MEMORY (EFI_COMPUTING_UNIT | 0x00050000)
+#define EFI_COMPUTING_UNIT_CHIPSET (EFI_COMPUTING_UNIT | 0x00060000)
///@}
///
@@ -158,15 +158,15 @@ typedef struct {
///
/// Computing Unit Host Processor Subclass Progress Code definitions.
///@{
-#define EFI_CU_HP_PC_POWER_ON_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000000)
-#define EFI_CU_HP_PC_CACHE_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000001)
-#define EFI_CU_HP_PC_RAM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000002)
-#define EFI_CU_HP_PC_MEMORY_CONTROLLER_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000003)
-#define EFI_CU_HP_PC_IO_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000004)
-#define EFI_CU_HP_PC_BSP_SELECT (EFI_SUBCLASS_SPECIFIC | 0x00000005)
-#define EFI_CU_HP_PC_BSP_RESELECT (EFI_SUBCLASS_SPECIFIC | 0x00000006)
-#define EFI_CU_HP_PC_AP_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000007)
-#define EFI_CU_HP_PC_SMM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000008)
+#define EFI_CU_HP_PC_POWER_ON_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_CU_HP_PC_CACHE_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_CU_HP_PC_RAM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_CU_HP_PC_MEMORY_CONTROLLER_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+#define EFI_CU_HP_PC_IO_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000004)
+#define EFI_CU_HP_PC_BSP_SELECT (EFI_SUBCLASS_SPECIFIC | 0x00000005)
+#define EFI_CU_HP_PC_BSP_RESELECT (EFI_SUBCLASS_SPECIFIC | 0x00000006)
+#define EFI_CU_HP_PC_AP_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000007)
+#define EFI_CU_HP_PC_SMM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000008)
///@}
//
@@ -181,8 +181,8 @@ typedef struct {
/// Computing Unit Cache Subclass Progress Code definitions.
///
///@{
-#define EFI_CU_CACHE_PC_PRESENCE_DETECT (EFI_SUBCLASS_SPECIFIC | 0x00000000)
-#define EFI_CU_CACHE_PC_CONFIGURATION (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_CU_CACHE_PC_PRESENCE_DETECT (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_CU_CACHE_PC_CONFIGURATION (EFI_SUBCLASS_SPECIFIC | 0x00000001)
///@}
///
@@ -205,52 +205,52 @@ typedef struct {
///
/// South Bridge initialization prior to memory detection.
///
-#define EFI_CHIPSET_PC_PEI_CAR_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000000)
+#define EFI_CHIPSET_PC_PEI_CAR_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000000)
///
/// North Bridge initialization prior to memory detection.
///
-#define EFI_CHIPSET_PC_PEI_CAR_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000001)
+#define EFI_CHIPSET_PC_PEI_CAR_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000001)
///
/// South Bridge initialization after memory detection.
///
-#define EFI_CHIPSET_PC_PEI_MEM_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000002)
+#define EFI_CHIPSET_PC_PEI_MEM_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000002)
///
/// North Bridge initialization after memory detection.
///
-#define EFI_CHIPSET_PC_PEI_MEM_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000003)
+#define EFI_CHIPSET_PC_PEI_MEM_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000003)
///
/// PCI Host Bridge DXE initialization.
///
-#define EFI_CHIPSET_PC_DXE_HB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000004)
+#define EFI_CHIPSET_PC_DXE_HB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000004)
///
/// North Bridge DXE initialization.
///
-#define EFI_CHIPSET_PC_DXE_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000005)
+#define EFI_CHIPSET_PC_DXE_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000005)
///
/// North Bridge specific SMM initialization in DXE.
///
-#define EFI_CHIPSET_PC_DXE_NB_SMM_INIT (EFI_SUBCLASS_SPECIFIC|0x00000006)
+#define EFI_CHIPSET_PC_DXE_NB_SMM_INIT (EFI_SUBCLASS_SPECIFIC|0x00000006)
///
/// Initialization of the South Bridge specific UEFI Runtime Services.
///
-#define EFI_CHIPSET_PC_DXE_SB_RT_INIT (EFI_SUBCLASS_SPECIFIC|0x00000007)
+#define EFI_CHIPSET_PC_DXE_SB_RT_INIT (EFI_SUBCLASS_SPECIFIC|0x00000007)
///
/// South Bridge DXE initialization
///
-#define EFI_CHIPSET_PC_DXE_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000008)
+#define EFI_CHIPSET_PC_DXE_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000008)
///
/// South Bridge specific SMM initialization in DXE.
///
-#define EFI_CHIPSET_PC_DXE_SB_SMM_INIT (EFI_SUBCLASS_SPECIFIC|0x00000009)
+#define EFI_CHIPSET_PC_DXE_SB_SMM_INIT (EFI_SUBCLASS_SPECIFIC|0x00000009)
///
/// Initialization of the South Bridge devices.
@@ -297,9 +297,9 @@ typedef struct {
/// Computing Unit Firmware Processor Subclass Error Code definitions.
///
///@{
-#define EFI_CU_FP_EC_HARD_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000000)
-#define EFI_CU_FP_EC_SOFT_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000001)
-#define EFI_CU_FP_EC_COMM_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_CU_FP_EC_HARD_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_CU_FP_EC_SOFT_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_CU_FP_EC_COMM_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000002)
///@}
//
@@ -310,27 +310,27 @@ typedef struct {
/// Computing Unit Cache Subclass Error Code definitions.
///
///@{
-#define EFI_CU_CACHE_EC_INVALID_TYPE (EFI_SUBCLASS_SPECIFIC | 0x00000000)
-#define EFI_CU_CACHE_EC_INVALID_SPEED (EFI_SUBCLASS_SPECIFIC | 0x00000001)
-#define EFI_CU_CACHE_EC_INVALID_SIZE (EFI_SUBCLASS_SPECIFIC | 0x00000002)
-#define EFI_CU_CACHE_EC_MISMATCH (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+#define EFI_CU_CACHE_EC_INVALID_TYPE (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_CU_CACHE_EC_INVALID_SPEED (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_CU_CACHE_EC_INVALID_SIZE (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_CU_CACHE_EC_MISMATCH (EFI_SUBCLASS_SPECIFIC | 0x00000003)
///@}
///
/// Computing Unit Memory Subclass Error Code definitions.
///
///@{
-#define EFI_CU_MEMORY_EC_INVALID_TYPE (EFI_SUBCLASS_SPECIFIC | 0x00000000)
-#define EFI_CU_MEMORY_EC_INVALID_SPEED (EFI_SUBCLASS_SPECIFIC | 0x00000001)
-#define EFI_CU_MEMORY_EC_CORRECTABLE (EFI_SUBCLASS_SPECIFIC | 0x00000002)
-#define EFI_CU_MEMORY_EC_UNCORRECTABLE (EFI_SUBCLASS_SPECIFIC | 0x00000003)
-#define EFI_CU_MEMORY_EC_SPD_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000004)
-#define EFI_CU_MEMORY_EC_INVALID_SIZE (EFI_SUBCLASS_SPECIFIC | 0x00000005)
-#define EFI_CU_MEMORY_EC_MISMATCH (EFI_SUBCLASS_SPECIFIC | 0x00000006)
-#define EFI_CU_MEMORY_EC_S3_RESUME_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000007)
-#define EFI_CU_MEMORY_EC_UPDATE_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000008)
-#define EFI_CU_MEMORY_EC_NONE_DETECTED (EFI_SUBCLASS_SPECIFIC | 0x00000009)
-#define EFI_CU_MEMORY_EC_NONE_USEFUL (EFI_SUBCLASS_SPECIFIC | 0x0000000A)
+#define EFI_CU_MEMORY_EC_INVALID_TYPE (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_CU_MEMORY_EC_INVALID_SPEED (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_CU_MEMORY_EC_CORRECTABLE (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_CU_MEMORY_EC_UNCORRECTABLE (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+#define EFI_CU_MEMORY_EC_SPD_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000004)
+#define EFI_CU_MEMORY_EC_INVALID_SIZE (EFI_SUBCLASS_SPECIFIC | 0x00000005)
+#define EFI_CU_MEMORY_EC_MISMATCH (EFI_SUBCLASS_SPECIFIC | 0x00000006)
+#define EFI_CU_MEMORY_EC_S3_RESUME_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000007)
+#define EFI_CU_MEMORY_EC_UPDATE_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000008)
+#define EFI_CU_MEMORY_EC_NONE_DETECTED (EFI_SUBCLASS_SPECIFIC | 0x00000009)
+#define EFI_CU_MEMORY_EC_NONE_USEFUL (EFI_SUBCLASS_SPECIFIC | 0x0000000A)
///@}
///
@@ -363,6 +363,7 @@ typedef struct {
#define EFI_PERIPHERAL_LCD_DEVICE (EFI_PERIPHERAL | 0x000B0000)
#define EFI_PERIPHERAL_NETWORK (EFI_PERIPHERAL | 0x000C0000)
#define EFI_PERIPHERAL_DOCKING (EFI_PERIPHERAL | 0x000D0000)
+#define EFI_PERIPHERAL_TPM (EFI_PERIPHERAL | 0x000E0000)
///@}
///
@@ -411,7 +412,7 @@ typedef struct {
/// Peripheral Class Serial Port Subclass Progress Code definitions.
///
///@{
-#define EFI_P_SERIAL_PORT_PC_CLEAR_BUFFER (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_P_SERIAL_PORT_PC_CLEAR_BUFFER (EFI_SUBCLASS_SPECIFIC | 0x00000000)
///@}
//
@@ -467,16 +468,16 @@ typedef struct {
/// Peripheral Class Keyboard Subclass Error Code definitions.
///
///@{
-#define EFI_P_KEYBOARD_EC_LOCKED (EFI_SUBCLASS_SPECIFIC | 0x00000000)
-#define EFI_P_KEYBOARD_EC_STUCK_KEY (EFI_SUBCLASS_SPECIFIC | 0x00000001)
-#define EFI_P_KEYBOARD_EC_BUFFER_FULL (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_P_KEYBOARD_EC_LOCKED (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_P_KEYBOARD_EC_STUCK_KEY (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_P_KEYBOARD_EC_BUFFER_FULL (EFI_SUBCLASS_SPECIFIC | 0x00000002)
///@}
///
/// Peripheral Class Mouse Subclass Error Code definitions.
///
///@{
-#define EFI_P_MOUSE_EC_LOCKED (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_P_MOUSE_EC_LOCKED (EFI_SUBCLASS_SPECIFIC | 0x00000000)
///@}
//
@@ -545,13 +546,13 @@ typedef struct {
/// These are shared by all subclasses.
///
///@{
-#define EFI_IOB_PC_INIT 0x00000000
-#define EFI_IOB_PC_RESET 0x00000001
-#define EFI_IOB_PC_DISABLE 0x00000002
-#define EFI_IOB_PC_DETECT 0x00000003
-#define EFI_IOB_PC_ENABLE 0x00000004
-#define EFI_IOB_PC_RECONFIG 0x00000005
-#define EFI_IOB_PC_HOTPLUG 0x00000006
+#define EFI_IOB_PC_INIT 0x00000000
+#define EFI_IOB_PC_RESET 0x00000001
+#define EFI_IOB_PC_DISABLE 0x00000002
+#define EFI_IOB_PC_DETECT 0x00000003
+#define EFI_IOB_PC_ENABLE 0x00000004
+#define EFI_IOB_PC_RECONFIG 0x00000005
+#define EFI_IOB_PC_HOTPLUG 0x00000006
///@}
//
@@ -639,8 +640,8 @@ typedef struct {
/// IO Bus Class PCI Subclass Error Code definitions.
///
///@{
-#define EFI_IOB_PCI_EC_PERR (EFI_SUBCLASS_SPECIFIC | 0x00000000)
-#define EFI_IOB_PCI_EC_SERR (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_IOB_PCI_EC_PERR (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_IOB_PCI_EC_SERR (EFI_SUBCLASS_SPECIFIC | 0x00000001)
///@}
//
@@ -742,8 +743,8 @@ typedef struct {
/// Software Class SEC Subclass Progress Code definitions.
///
///@{
-#define EFI_SW_SEC_PC_ENTRY_POINT (EFI_SUBCLASS_SPECIFIC | 0x00000000)
-#define EFI_SW_SEC_PC_HANDOFF_TO_NEXT (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_SW_SEC_PC_ENTRY_POINT (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_SW_SEC_PC_HANDOFF_TO_NEXT (EFI_SUBCLASS_SPECIFIC | 0x00000001)
///@}
///
@@ -784,16 +785,16 @@ typedef struct {
/// Software Class DXE BS Driver Subclass Progress Code definitions.
///
///@{
-#define EFI_SW_DXE_BS_PC_LEGACY_OPROM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000000)
-#define EFI_SW_DXE_BS_PC_READY_TO_BOOT_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000001)
-#define EFI_SW_DXE_BS_PC_LEGACY_BOOT_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000002)
-#define EFI_SW_DXE_BS_PC_EXIT_BOOT_SERVICES_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000003)
-#define EFI_SW_DXE_BS_PC_VIRTUAL_ADDRESS_CHANGE_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000004)
-#define EFI_SW_DXE_BS_PC_VARIABLE_SERVICES_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000005)
-#define EFI_SW_DXE_BS_PC_VARIABLE_RECLAIM (EFI_SUBCLASS_SPECIFIC | 0x00000006)
-#define EFI_SW_DXE_BS_PC_ATTEMPT_BOOT_ORDER_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000007)
-#define EFI_SW_DXE_BS_PC_CONFIG_RESET (EFI_SUBCLASS_SPECIFIC | 0x00000008)
-#define EFI_SW_DXE_BS_PC_CSM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000009)
+#define EFI_SW_DXE_BS_PC_LEGACY_OPROM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_SW_DXE_BS_PC_READY_TO_BOOT_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_SW_DXE_BS_PC_LEGACY_BOOT_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_SW_DXE_BS_PC_EXIT_BOOT_SERVICES_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+#define EFI_SW_DXE_BS_PC_VIRTUAL_ADDRESS_CHANGE_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000004)
+#define EFI_SW_DXE_BS_PC_VARIABLE_SERVICES_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000005)
+#define EFI_SW_DXE_BS_PC_VARIABLE_RECLAIM (EFI_SUBCLASS_SPECIFIC | 0x00000006)
+#define EFI_SW_DXE_BS_PC_ATTEMPT_BOOT_ORDER_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000007)
+#define EFI_SW_DXE_BS_PC_CONFIG_RESET (EFI_SUBCLASS_SPECIFIC | 0x00000008)
+#define EFI_SW_DXE_BS_PC_CSM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000009)
///@}
//
@@ -965,26 +966,27 @@ typedef struct {
/// These are shared by all subclasses.
///
///@{
-#define EFI_SW_EC_NON_SPECIFIC 0x00000000
-#define EFI_SW_EC_LOAD_ERROR 0x00000001
-#define EFI_SW_EC_INVALID_PARAMETER 0x00000002
-#define EFI_SW_EC_UNSUPPORTED 0x00000003
-#define EFI_SW_EC_INVALID_BUFFER 0x00000004
-#define EFI_SW_EC_OUT_OF_RESOURCES 0x00000005
-#define EFI_SW_EC_ABORTED 0x00000006
-#define EFI_SW_EC_ILLEGAL_SOFTWARE_STATE 0x00000007
-#define EFI_SW_EC_ILLEGAL_HARDWARE_STATE 0x00000008
-#define EFI_SW_EC_START_ERROR 0x00000009
-#define EFI_SW_EC_BAD_DATE_TIME 0x0000000A
-#define EFI_SW_EC_CFG_INVALID 0x0000000B
-#define EFI_SW_EC_CFG_CLR_REQUEST 0x0000000C
-#define EFI_SW_EC_CFG_DEFAULT 0x0000000D
-#define EFI_SW_EC_PWD_INVALID 0x0000000E
-#define EFI_SW_EC_PWD_CLR_REQUEST 0x0000000F
-#define EFI_SW_EC_PWD_CLEARED 0x00000010
-#define EFI_SW_EC_EVENT_LOG_FULL 0x00000011
-#define EFI_SW_EC_WRITE_PROTECTED 0x00000012
-#define EFI_SW_EC_FV_CORRUPTED 0x00000013
+#define EFI_SW_EC_NON_SPECIFIC 0x00000000
+#define EFI_SW_EC_LOAD_ERROR 0x00000001
+#define EFI_SW_EC_INVALID_PARAMETER 0x00000002
+#define EFI_SW_EC_UNSUPPORTED 0x00000003
+#define EFI_SW_EC_INVALID_BUFFER 0x00000004
+#define EFI_SW_EC_OUT_OF_RESOURCES 0x00000005
+#define EFI_SW_EC_ABORTED 0x00000006
+#define EFI_SW_EC_ILLEGAL_SOFTWARE_STATE 0x00000007
+#define EFI_SW_EC_ILLEGAL_HARDWARE_STATE 0x00000008
+#define EFI_SW_EC_START_ERROR 0x00000009
+#define EFI_SW_EC_BAD_DATE_TIME 0x0000000A
+#define EFI_SW_EC_CFG_INVALID 0x0000000B
+#define EFI_SW_EC_CFG_CLR_REQUEST 0x0000000C
+#define EFI_SW_EC_CFG_DEFAULT 0x0000000D
+#define EFI_SW_EC_PWD_INVALID 0x0000000E
+#define EFI_SW_EC_PWD_CLR_REQUEST 0x0000000F
+#define EFI_SW_EC_PWD_CLEARED 0x00000010
+#define EFI_SW_EC_EVENT_LOG_FULL 0x00000011
+#define EFI_SW_EC_WRITE_PROTECTED 0x00000012
+#define EFI_SW_EC_FV_CORRUPTED 0x00000013
+#define EFI_SW_EC_INCONSISTENT_MEMORY_MAP 0x00000014
///@}
//
@@ -1008,26 +1010,25 @@ typedef struct {
/// Software Class PEI Module Subclass Error Code definitions.
///
///@{
-#define EFI_SW_PEI_EC_NO_RECOVERY_CAPSULE (EFI_SUBCLASS_SPECIFIC | 0x00000000)
-#define EFI_SW_PEI_EC_INVALID_CAPSULE_DESCRIPTOR (EFI_SUBCLASS_SPECIFIC | 0x00000001)
-#define EFI_SW_PEI_EC_S3_RESUME_PPI_NOT_FOUND (EFI_SUBCLASS_SPECIFIC | 0x00000002)
-#define EFI_SW_PEI_EC_S3_BOOT_SCRIPT_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000003)
-#define EFI_SW_PEI_EC_S3_OS_WAKE_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000004)
-#define EFI_SW_PEI_EC_S3_RESUME_FAILED (EFI_SUBCLASS_SPECIFIC | 0x00000005)
-#define EFI_SW_PEI_EC_RECOVERY_PPI_NOT_FOUND (EFI_SUBCLASS_SPECIFIC | 0x00000006)
-#define EFI_SW_PEI_EC_RECOVERY_FAILED (EFI_SUBCLASS_SPECIFIC | 0x00000007)
-#define EFI_SW_PEI_EC_S3_RESUME_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000008)
-#define EFI_SW_PEI_EC_INVALID_CAPSULE (EFI_SUBCLASS_SPECIFIC | 0x00000009)
+#define EFI_SW_PEI_EC_NO_RECOVERY_CAPSULE (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_SW_PEI_EC_INVALID_CAPSULE_DESCRIPTOR (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_SW_PEI_EC_S3_RESUME_PPI_NOT_FOUND (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_SW_PEI_EC_S3_BOOT_SCRIPT_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+#define EFI_SW_PEI_EC_S3_OS_WAKE_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000004)
+#define EFI_SW_PEI_EC_S3_RESUME_FAILED (EFI_SUBCLASS_SPECIFIC | 0x00000005)
+#define EFI_SW_PEI_EC_RECOVERY_PPI_NOT_FOUND (EFI_SUBCLASS_SPECIFIC | 0x00000006)
+#define EFI_SW_PEI_EC_RECOVERY_FAILED (EFI_SUBCLASS_SPECIFIC | 0x00000007)
+#define EFI_SW_PEI_EC_S3_RESUME_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000008)
+#define EFI_SW_PEI_EC_INVALID_CAPSULE (EFI_SUBCLASS_SPECIFIC | 0x00000009)
///@}
///
/// Software Class DXE Foundation Subclass Error Code definitions.
///
///@{
-#define EFI_SW_DXE_CORE_EC_NO_ARCH (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_SW_DXE_CORE_EC_NO_ARCH (EFI_SUBCLASS_SPECIFIC | 0x00000000)
///@}
-
///
/// Software Class DXE Boot Service Driver Subclass Error Code definitions.
///
@@ -1147,20 +1148,20 @@ typedef struct {
/// Software Class EFI DXE Service Subclass Error Code definitions.
///
///@{
-#define EFI_SW_DXE_BS_PC_BEGIN_CONNECTING_DRIVERS (EFI_SUBCLASS_SPECIFIC | 0x00000005)
-#define EFI_SW_DXE_BS_PC_VERIFYING_PASSWORD (EFI_SUBCLASS_SPECIFIC | 0x00000006)
+#define EFI_SW_DXE_BS_PC_BEGIN_CONNECTING_DRIVERS (EFI_SUBCLASS_SPECIFIC | 0x00000005)
+#define EFI_SW_DXE_BS_PC_VERIFYING_PASSWORD (EFI_SUBCLASS_SPECIFIC | 0x00000006)
///@}
///
/// Software Class DXE RT Driver Subclass Progress Code definitions.
///
///@{
-#define EFI_SW_DXE_RT_PC_S0 (EFI_SUBCLASS_SPECIFIC | 0x00000000)
-#define EFI_SW_DXE_RT_PC_S1 (EFI_SUBCLASS_SPECIFIC | 0x00000001)
-#define EFI_SW_DXE_RT_PC_S2 (EFI_SUBCLASS_SPECIFIC | 0x00000002)
-#define EFI_SW_DXE_RT_PC_S3 (EFI_SUBCLASS_SPECIFIC | 0x00000003)
-#define EFI_SW_DXE_RT_PC_S4 (EFI_SUBCLASS_SPECIFIC | 0x00000004)
-#define EFI_SW_DXE_RT_PC_S5 (EFI_SUBCLASS_SPECIFIC | 0x00000005)
+#define EFI_SW_DXE_RT_PC_S0 (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_SW_DXE_RT_PC_S1 (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_SW_DXE_RT_PC_S2 (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_SW_DXE_RT_PC_S3 (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+#define EFI_SW_DXE_RT_PC_S4 (EFI_SUBCLASS_SPECIFIC | 0x00000004)
+#define EFI_SW_DXE_RT_PC_S5 (EFI_SUBCLASS_SPECIFIC | 0x00000005)
///@}
///
@@ -1169,23 +1170,23 @@ typedef struct {
/// definitions in the EFI specification.
///
///@{
-#define EFI_SW_EC_X64_DIVIDE_ERROR EXCEPT_X64_DIVIDE_ERROR
-#define EFI_SW_EC_X64_DEBUG EXCEPT_X64_DEBUG
-#define EFI_SW_EC_X64_NMI EXCEPT_X64_NMI
-#define EFI_SW_EC_X64_BREAKPOINT EXCEPT_X64_BREAKPOINT
-#define EFI_SW_EC_X64_OVERFLOW EXCEPT_X64_OVERFLOW
-#define EFI_SW_EC_X64_BOUND EXCEPT_X64_BOUND
-#define EFI_SW_EC_X64_INVALID_OPCODE EXCEPT_X64_INVALID_OPCODE
-#define EFI_SW_EC_X64_DOUBLE_FAULT EXCEPT_X64_DOUBLE_FAULT
-#define EFI_SW_EC_X64_INVALID_TSS EXCEPT_X64_INVALID_TSS
-#define EFI_SW_EC_X64_SEG_NOT_PRESENT EXCEPT_X64_SEG_NOT_PRESENT
-#define EFI_SW_EC_X64_STACK_FAULT EXCEPT_X64_STACK_FAULT
-#define EFI_SW_EC_X64_GP_FAULT EXCEPT_X64_GP_FAULT
-#define EFI_SW_EC_X64_PAGE_FAULT EXCEPT_X64_PAGE_FAULT
-#define EFI_SW_EC_X64_FP_ERROR EXCEPT_X64_FP_ERROR
-#define EFI_SW_EC_X64_ALIGNMENT_CHECK EXCEPT_X64_ALIGNMENT_CHECK
-#define EFI_SW_EC_X64_MACHINE_CHECK EXCEPT_X64_MACHINE_CHECK
-#define EFI_SW_EC_X64_SIMD EXCEPT_X64_SIMD
+#define EFI_SW_EC_X64_DIVIDE_ERROR EXCEPT_X64_DIVIDE_ERROR
+#define EFI_SW_EC_X64_DEBUG EXCEPT_X64_DEBUG
+#define EFI_SW_EC_X64_NMI EXCEPT_X64_NMI
+#define EFI_SW_EC_X64_BREAKPOINT EXCEPT_X64_BREAKPOINT
+#define EFI_SW_EC_X64_OVERFLOW EXCEPT_X64_OVERFLOW
+#define EFI_SW_EC_X64_BOUND EXCEPT_X64_BOUND
+#define EFI_SW_EC_X64_INVALID_OPCODE EXCEPT_X64_INVALID_OPCODE
+#define EFI_SW_EC_X64_DOUBLE_FAULT EXCEPT_X64_DOUBLE_FAULT
+#define EFI_SW_EC_X64_INVALID_TSS EXCEPT_X64_INVALID_TSS
+#define EFI_SW_EC_X64_SEG_NOT_PRESENT EXCEPT_X64_SEG_NOT_PRESENT
+#define EFI_SW_EC_X64_STACK_FAULT EXCEPT_X64_STACK_FAULT
+#define EFI_SW_EC_X64_GP_FAULT EXCEPT_X64_GP_FAULT
+#define EFI_SW_EC_X64_PAGE_FAULT EXCEPT_X64_PAGE_FAULT
+#define EFI_SW_EC_X64_FP_ERROR EXCEPT_X64_FP_ERROR
+#define EFI_SW_EC_X64_ALIGNMENT_CHECK EXCEPT_X64_ALIGNMENT_CHECK
+#define EFI_SW_EC_X64_MACHINE_CHECK EXCEPT_X64_MACHINE_CHECK
+#define EFI_SW_EC_X64_SIMD EXCEPT_X64_SIMD
///@}
///
@@ -1194,14 +1195,14 @@ typedef struct {
/// definitions in the EFI specification.
///
///@{
-#define EFI_SW_EC_ARM_RESET EXCEPT_ARM_RESET
-#define EFI_SW_EC_ARM_UNDEFINED_INSTRUCTION EXCEPT_ARM_UNDEFINED_INSTRUCTION
-#define EFI_SW_EC_ARM_SOFTWARE_INTERRUPT EXCEPT_ARM_SOFTWARE_INTERRUPT
-#define EFI_SW_EC_ARM_PREFETCH_ABORT EXCEPT_ARM_PREFETCH_ABORT
-#define EFI_SW_EC_ARM_DATA_ABORT EXCEPT_ARM_DATA_ABORT
-#define EFI_SW_EC_ARM_RESERVED EXCEPT_ARM_RESERVED
-#define EFI_SW_EC_ARM_IRQ EXCEPT_ARM_IRQ
-#define EFI_SW_EC_ARM_FIQ EXCEPT_ARM_FIQ
+#define EFI_SW_EC_ARM_RESET EXCEPT_ARM_RESET
+#define EFI_SW_EC_ARM_UNDEFINED_INSTRUCTION EXCEPT_ARM_UNDEFINED_INSTRUCTION
+#define EFI_SW_EC_ARM_SOFTWARE_INTERRUPT EXCEPT_ARM_SOFTWARE_INTERRUPT
+#define EFI_SW_EC_ARM_PREFETCH_ABORT EXCEPT_ARM_PREFETCH_ABORT
+#define EFI_SW_EC_ARM_DATA_ABORT EXCEPT_ARM_DATA_ABORT
+#define EFI_SW_EC_ARM_RESERVED EXCEPT_ARM_RESERVED
+#define EFI_SW_EC_ARM_IRQ EXCEPT_ARM_IRQ
+#define EFI_SW_EC_ARM_FIQ EXCEPT_ARM_FIQ
///@}
#endif
diff --git a/MdePkg/Include/PiPei.h b/MdePkg/Include/PiPei.h
index 277d8c85..eea9fa3e 100644
--- a/MdePkg/Include/PiPei.h
+++ b/MdePkg/Include/PiPei.h
@@ -18,4 +18,3 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include
#endif
-
diff --git a/MdePkg/Include/Ppi/BlockIo.h b/MdePkg/Include/Ppi/BlockIo.h
index 220c5ba1..4f3227db 100644
--- a/MdePkg/Include/Ppi/BlockIo.h
+++ b/MdePkg/Include/Ppi/BlockIo.h
@@ -33,24 +33,24 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
///
/// The forward declaration for EFI_PEI_RECOVERY_BLOCK_IO_PPI.
///
-typedef struct _EFI_PEI_RECOVERY_BLOCK_IO_PPI EFI_PEI_RECOVERY_BLOCK_IO_PPI;
+typedef struct _EFI_PEI_RECOVERY_BLOCK_IO_PPI EFI_PEI_RECOVERY_BLOCK_IO_PPI;
///
/// All blocks on the recovery device are addressed with a 64-bit Logical Block Address (LBA).
///
-typedef UINT64 EFI_PEI_LBA;
+typedef UINT64 EFI_PEI_LBA;
///
/// EFI_PEI_BLOCK_DEVICE_TYPE
///
typedef enum {
- LegacyFloppy = 0, ///< The recovery device is a floppy.
- IdeCDROM = 1, ///< The recovery device is an IDE CD-ROM
- IdeLS120 = 2, ///< The recovery device is an IDE LS-120
- UsbMassStorage= 3, ///< The recovery device is a USB Mass Storage device
- SD = 4, ///< The recovery device is a Secure Digital device
- EMMC = 5, ///< The recovery device is a eMMC device
- UfsDevice = 6, ///< The recovery device is a Universal Flash Storage device
+ LegacyFloppy = 0, ///< The recovery device is a floppy.
+ IdeCDROM = 1, ///< The recovery device is an IDE CD-ROM
+ IdeLS120 = 2, ///< The recovery device is an IDE LS-120
+ UsbMassStorage = 3, ///< The recovery device is a USB Mass Storage device
+ SD = 4, ///< The recovery device is a Secure Digital device
+ EMMC = 5, ///< The recovery device is a eMMC device
+ UfsDevice = 6, ///< The recovery device is a Universal Flash Storage device
MaxDeviceType
} EFI_PEI_BLOCK_DEVICE_TYPE;
@@ -68,20 +68,20 @@ typedef struct {
///
/// The type of media device being referenced by DeviceIndex.
///
- EFI_PEI_BLOCK_DEVICE_TYPE DeviceType;
+ EFI_PEI_BLOCK_DEVICE_TYPE DeviceType;
///
/// A flag that indicates if media is present. This flag is always set for
/// nonremovable media devices.
///
- BOOLEAN MediaPresent;
+ BOOLEAN MediaPresent;
///
/// The last logical block that the device supports.
///
- UINTN LastBlock;
+ UINTN LastBlock;
///
/// The size of a logical block in bytes.
///
- UINTN BlockSize;
+ UINTN BlockSize;
} EFI_PEI_BLOCK_IO_MEDIA;
/**
@@ -214,19 +214,19 @@ struct _EFI_PEI_RECOVERY_BLOCK_IO_PPI {
///
/// Gets the number of block I/O devices that the specific block driver manages.
///
- EFI_PEI_GET_NUMBER_BLOCK_DEVICES GetNumberOfBlockDevices;
+ EFI_PEI_GET_NUMBER_BLOCK_DEVICES GetNumberOfBlockDevices;
///
/// Gets the specified media information.
///
- EFI_PEI_GET_DEVICE_MEDIA_INFORMATION GetBlockDeviceMediaInfo;
+ EFI_PEI_GET_DEVICE_MEDIA_INFORMATION GetBlockDeviceMediaInfo;
///
/// Reads the requested number of blocks from the specified block device.
///
- EFI_PEI_READ_BLOCKS ReadBlocks;
+ EFI_PEI_READ_BLOCKS ReadBlocks;
};
-extern EFI_GUID gEfiPeiVirtualBlockIoPpiGuid;
+extern EFI_GUID gEfiPeiVirtualBlockIoPpiGuid;
#endif
diff --git a/MdePkg/Include/Ppi/CpuIo.h b/MdePkg/Include/Ppi/CpuIo.h
index fe700d38..3e31ae99 100644
--- a/MdePkg/Include/Ppi/CpuIo.h
+++ b/MdePkg/Include/Ppi/CpuIo.h
@@ -16,7 +16,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define EFI_PEI_CPU_IO_PPI_INSTALLED_GUID \
{ 0xe6af1f7b, 0xfc3f, 0x46da, {0xa8, 0x28, 0xa3, 0xb4, 0x57, 0xa4, 0x42, 0x82 } }
-typedef struct _EFI_PEI_CPU_IO_PPI EFI_PEI_CPU_IO_PPI;
+typedef struct _EFI_PEI_CPU_IO_PPI EFI_PEI_CPU_IO_PPI;
///
/// EFI_PEI_CPU_IO_PPI_WIDTH.
@@ -70,11 +70,11 @@ typedef struct {
///
/// This service provides the various modalities of memory and I/O read.
///
- EFI_PEI_CPU_IO_PPI_IO_MEM Read;
+ EFI_PEI_CPU_IO_PPI_IO_MEM Read;
///
/// This service provides the various modalities of memory and I/O write.
///
- EFI_PEI_CPU_IO_PPI_IO_MEM Write;
+ EFI_PEI_CPU_IO_PPI_IO_MEM Write;
} EFI_PEI_CPU_IO_PPI_ACCESS;
/**
@@ -390,33 +390,33 @@ struct _EFI_PEI_CPU_IO_PPI {
///
/// Collection of memory-access services.
///
- EFI_PEI_CPU_IO_PPI_ACCESS Mem;
+ EFI_PEI_CPU_IO_PPI_ACCESS Mem;
///
/// Collection of I/O-access services.
///
- EFI_PEI_CPU_IO_PPI_ACCESS Io;
+ EFI_PEI_CPU_IO_PPI_ACCESS Io;
- EFI_PEI_CPU_IO_PPI_IO_READ8 IoRead8;
- EFI_PEI_CPU_IO_PPI_IO_READ16 IoRead16;
- EFI_PEI_CPU_IO_PPI_IO_READ32 IoRead32;
- EFI_PEI_CPU_IO_PPI_IO_READ64 IoRead64;
+ EFI_PEI_CPU_IO_PPI_IO_READ8 IoRead8;
+ EFI_PEI_CPU_IO_PPI_IO_READ16 IoRead16;
+ EFI_PEI_CPU_IO_PPI_IO_READ32 IoRead32;
+ EFI_PEI_CPU_IO_PPI_IO_READ64 IoRead64;
- EFI_PEI_CPU_IO_PPI_IO_WRITE8 IoWrite8;
- EFI_PEI_CPU_IO_PPI_IO_WRITE16 IoWrite16;
- EFI_PEI_CPU_IO_PPI_IO_WRITE32 IoWrite32;
- EFI_PEI_CPU_IO_PPI_IO_WRITE64 IoWrite64;
+ EFI_PEI_CPU_IO_PPI_IO_WRITE8 IoWrite8;
+ EFI_PEI_CPU_IO_PPI_IO_WRITE16 IoWrite16;
+ EFI_PEI_CPU_IO_PPI_IO_WRITE32 IoWrite32;
+ EFI_PEI_CPU_IO_PPI_IO_WRITE64 IoWrite64;
- EFI_PEI_CPU_IO_PPI_MEM_READ8 MemRead8;
- EFI_PEI_CPU_IO_PPI_MEM_READ16 MemRead16;
- EFI_PEI_CPU_IO_PPI_MEM_READ32 MemRead32;
- EFI_PEI_CPU_IO_PPI_MEM_READ64 MemRead64;
+ EFI_PEI_CPU_IO_PPI_MEM_READ8 MemRead8;
+ EFI_PEI_CPU_IO_PPI_MEM_READ16 MemRead16;
+ EFI_PEI_CPU_IO_PPI_MEM_READ32 MemRead32;
+ EFI_PEI_CPU_IO_PPI_MEM_READ64 MemRead64;
- EFI_PEI_CPU_IO_PPI_MEM_WRITE8 MemWrite8;
- EFI_PEI_CPU_IO_PPI_MEM_WRITE16 MemWrite16;
- EFI_PEI_CPU_IO_PPI_MEM_WRITE32 MemWrite32;
- EFI_PEI_CPU_IO_PPI_MEM_WRITE64 MemWrite64;
+ EFI_PEI_CPU_IO_PPI_MEM_WRITE8 MemWrite8;
+ EFI_PEI_CPU_IO_PPI_MEM_WRITE16 MemWrite16;
+ EFI_PEI_CPU_IO_PPI_MEM_WRITE32 MemWrite32;
+ EFI_PEI_CPU_IO_PPI_MEM_WRITE64 MemWrite64;
};
-extern EFI_GUID gEfiPeiCpuIoPpiInstalledGuid;
+extern EFI_GUID gEfiPeiCpuIoPpiInstalledGuid;
#endif
diff --git a/MdePkg/Include/Ppi/PciCfg2.h b/MdePkg/Include/Ppi/PciCfg2.h
index 17b67a72..f5812c34 100644
--- a/MdePkg/Include/Ppi/PciCfg2.h
+++ b/MdePkg/Include/Ppi/PciCfg2.h
@@ -20,9 +20,9 @@
#define EFI_PEI_PCI_CFG2_PPI_GUID \
{ 0x57a449a, 0x1fdc, 0x4c06, { 0xbf, 0xc9, 0xf5, 0x3f, 0x6a, 0x99, 0xbb, 0x92 } }
-typedef struct _EFI_PEI_PCI_CFG2_PPI EFI_PEI_PCI_CFG2_PPI;
+typedef struct _EFI_PEI_PCI_CFG2_PPI EFI_PEI_PCI_CFG2_PPI;
-#define EFI_PEI_PCI_CFG_ADDRESS(bus,dev,func,reg) \
+#define EFI_PEI_PCI_CFG_ADDRESS(bus, dev, func, reg) \
(UINT64) ( \
(((UINTN) bus) << 24) | \
(((UINTN) dev) << 16) | \
@@ -36,7 +36,7 @@ typedef enum {
///
/// 8-bit access
///
- EfiPeiPciCfgWidthUint8 = 0,
+ EfiPeiPciCfgWidthUint8 = 0,
///
/// 16-bit access
///
@@ -60,26 +60,26 @@ typedef struct {
/// 8-bit register offset within the PCI configuration space for a given device's function
/// space.
///
- UINT8 Register;
+ UINT8 Register;
///
/// Only the 3 least-significant bits are used to encode one of 8 possible functions within a
/// given device.
///
- UINT8 Function;
+ UINT8 Function;
///
/// Only the 5 least-significant bits are used to encode one of 32 possible devices.
///
- UINT8 Device;
+ UINT8 Device;
///
/// 8-bit value to encode between 0 and 255 buses.
///
- UINT8 Bus;
+ UINT8 Bus;
///
/// Register number in PCI configuration space. If this field is zero, then Register is used
/// for the register number. If this field is non-zero, then Register is ignored and this field
/// is used for the register number.
///
- UINT32 ExtendedRegister;
+ UINT32 ExtendedRegister;
} EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS;
/**
@@ -114,8 +114,7 @@ EFI_STATUS
IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,
IN UINT64 Address,
IN OUT VOID *Buffer
-);
-
+ );
/**
Performs a read-modify-write operation on the contents
@@ -156,23 +155,22 @@ EFI_STATUS
IN UINT64 Address,
IN VOID *SetBits,
IN VOID *ClearBits
-);
+ );
///
/// The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI
/// controllers behind a PCI root bridge controller.
///
struct _EFI_PEI_PCI_CFG2_PPI {
- EFI_PEI_PCI_CFG2_PPI_IO Read;
- EFI_PEI_PCI_CFG2_PPI_IO Write;
- EFI_PEI_PCI_CFG2_PPI_RW Modify;
+ EFI_PEI_PCI_CFG2_PPI_IO Read;
+ EFI_PEI_PCI_CFG2_PPI_IO Write;
+ EFI_PEI_PCI_CFG2_PPI_RW Modify;
///
/// The PCI bus segment which the specified functions will access.
///
- UINT16 Segment;
+ UINT16 Segment;
};
-
-extern EFI_GUID gEfiPciCfg2PpiGuid;
+extern EFI_GUID gEfiPciCfg2PpiGuid;
#endif
diff --git a/MdePkg/Include/Protocol/BlockIo.h b/MdePkg/Include/Protocol/BlockIo.h
index 107ea920..d8fe6c2f 100644
--- a/MdePkg/Include/Protocol/BlockIo.h
+++ b/MdePkg/Include/Protocol/BlockIo.h
@@ -17,17 +17,17 @@
0x964e5b21, 0x6459, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \
}
-typedef struct _EFI_BLOCK_IO_PROTOCOL EFI_BLOCK_IO_PROTOCOL;
+typedef struct _EFI_BLOCK_IO_PROTOCOL EFI_BLOCK_IO_PROTOCOL;
///
/// Protocol GUID name defined in EFI1.1.
///
-#define BLOCK_IO_PROTOCOL EFI_BLOCK_IO_PROTOCOL_GUID
+#define BLOCK_IO_PROTOCOL EFI_BLOCK_IO_PROTOCOL_GUID
///
/// Protocol defined in EFI1.1.
///
-typedef EFI_BLOCK_IO_PROTOCOL EFI_BLOCK_IO;
+typedef EFI_BLOCK_IO_PROTOCOL EFI_BLOCK_IO;
/**
Reset the Block Device.
@@ -129,84 +129,84 @@ typedef struct {
///
/// The curent media Id. If the media changes, this value is changed.
///
- UINT32 MediaId;
+ UINT32 MediaId;
///
/// TRUE if the media is removable; otherwise, FALSE.
///
- BOOLEAN RemovableMedia;
+ BOOLEAN RemovableMedia;
///
/// TRUE if there is a media currently present in the device;
/// othersise, FALSE. THis field shows the media present status
/// as of the most recent ReadBlocks() or WriteBlocks() call.
///
- BOOLEAN MediaPresent;
+ BOOLEAN MediaPresent;
///
/// TRUE if LBA 0 is the first block of a partition; otherwise
/// FALSE. For media with only one partition this would be TRUE.
///
- BOOLEAN LogicalPartition;
+ BOOLEAN LogicalPartition;
///
/// TRUE if the media is marked read-only otherwise, FALSE.
/// This field shows the read-only status as of the most recent WriteBlocks () call.
///
- BOOLEAN ReadOnly;
+ BOOLEAN ReadOnly;
///
/// TRUE if the WriteBlock () function caches write data.
///
- BOOLEAN WriteCaching;
+ BOOLEAN WriteCaching;
///
/// The intrinsic block size of the device. If the media changes, then
/// this field is updated.
///
- UINT32 BlockSize;
+ UINT32 BlockSize;
///
/// Supplies the alignment requirement for any buffer to read or write block(s).
///
- UINT32 IoAlign;
+ UINT32 IoAlign;
///
/// The last logical block address on the device.
/// If the media changes, then this field is updated.
///
- EFI_LBA LastBlock;
+ EFI_LBA LastBlock;
///
/// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to
/// EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the first LBA is aligned to
/// a physical block boundary.
///
- EFI_LBA LowestAlignedLba;
+ EFI_LBA LowestAlignedLba;
///
/// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to
/// EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the number of logical blocks
/// per physical block.
///
- UINT32 LogicalBlocksPerPhysicalBlock;
+ UINT32 LogicalBlocksPerPhysicalBlock;
///
/// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to
/// EFI_BLOCK_IO_PROTOCOL_REVISION3. Returns the optimal transfer length
/// granularity as a number of logical blocks.
///
- UINT32 OptimalTransferLengthGranularity;
+ UINT32 OptimalTransferLengthGranularity;
} EFI_BLOCK_IO_MEDIA;
-#define EFI_BLOCK_IO_PROTOCOL_REVISION 0x00010000
-#define EFI_BLOCK_IO_PROTOCOL_REVISION2 0x00020001
-#define EFI_BLOCK_IO_PROTOCOL_REVISION3 0x0002001F
+#define EFI_BLOCK_IO_PROTOCOL_REVISION 0x00010000
+#define EFI_BLOCK_IO_PROTOCOL_REVISION2 0x00020001
+#define EFI_BLOCK_IO_PROTOCOL_REVISION3 0x0002001F
///
/// Revision defined in EFI1.1.
///
-#define EFI_BLOCK_IO_INTERFACE_REVISION EFI_BLOCK_IO_PROTOCOL_REVISION
+#define EFI_BLOCK_IO_INTERFACE_REVISION EFI_BLOCK_IO_PROTOCOL_REVISION
///
/// This protocol provides control over block devices.
@@ -217,19 +217,18 @@ struct _EFI_BLOCK_IO_PROTOCOL {
/// revisions must be backwards compatible. If a future version is not
/// back wards compatible, it is not the same GUID.
///
- UINT64 Revision;
+ UINT64 Revision;
///
/// Pointer to the EFI_BLOCK_IO_MEDIA data for this device.
///
- EFI_BLOCK_IO_MEDIA *Media;
-
- EFI_BLOCK_RESET Reset;
- EFI_BLOCK_READ ReadBlocks;
- EFI_BLOCK_WRITE WriteBlocks;
- EFI_BLOCK_FLUSH FlushBlocks;
+ EFI_BLOCK_IO_MEDIA *Media;
+ EFI_BLOCK_RESET Reset;
+ EFI_BLOCK_READ ReadBlocks;
+ EFI_BLOCK_WRITE WriteBlocks;
+ EFI_BLOCK_FLUSH FlushBlocks;
};
-extern EFI_GUID gEfiBlockIoProtocolGuid;
+extern EFI_GUID gEfiBlockIoProtocolGuid;
#endif
diff --git a/MdePkg/Include/Protocol/BlockIo2.h b/MdePkg/Include/Protocol/BlockIo2.h
index 75ea914f..f629d8eb 100644
--- a/MdePkg/Include/Protocol/BlockIo2.h
+++ b/MdePkg/Include/Protocol/BlockIo2.h
@@ -20,27 +20,25 @@
0xa77b2472, 0xe282, 0x4e9f, {0xa2, 0x45, 0xc2, 0xc0, 0xe2, 0x7b, 0xbc, 0xc1} \
}
-typedef struct _EFI_BLOCK_IO2_PROTOCOL EFI_BLOCK_IO2_PROTOCOL;
+typedef struct _EFI_BLOCK_IO2_PROTOCOL EFI_BLOCK_IO2_PROTOCOL;
/**
The struct of Block IO2 Token.
**/
typedef struct {
-
///
/// If Event is NULL, then blocking I/O is performed.If Event is not NULL and
/// non-blocking I/O is supported, then non-blocking I/O is performed, and
/// Event will be signaled when the read request is completed.
///
- EFI_EVENT Event;
+ EFI_EVENT Event;
///
/// Defines whether or not the signaled event encountered an error.
///
- EFI_STATUS TransactionStatus;
+ EFI_STATUS TransactionStatus;
} EFI_BLOCK_IO2_TOKEN;
-
/**
Reset the block device hardware.
@@ -56,7 +54,7 @@ typedef struct {
**/
typedef
EFI_STATUS
-(EFIAPI *EFI_BLOCK_RESET_EX) (
+(EFIAPI *EFI_BLOCK_RESET_EX)(
IN EFI_BLOCK_IO2_PROTOCOL *This,
IN BOOLEAN ExtendedVerification
);
@@ -96,13 +94,13 @@ EFI_STATUS
**/
typedef
EFI_STATUS
-(EFIAPI *EFI_BLOCK_READ_EX) (
+(EFIAPI *EFI_BLOCK_READ_EX)(
IN EFI_BLOCK_IO2_PROTOCOL *This,
IN UINT32 MediaId,
IN EFI_LBA LBA,
IN OUT EFI_BLOCK_IO2_TOKEN *Token,
IN UINTN BufferSize,
- OUT VOID *Buffer
+ OUT VOID *Buffer
);
/**
@@ -138,7 +136,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
-(EFIAPI *EFI_BLOCK_WRITE_EX) (
+(EFIAPI *EFI_BLOCK_WRITE_EX)(
IN EFI_BLOCK_IO2_PROTOCOL *This,
IN UINT32 MediaId,
IN EFI_LBA LBA,
@@ -171,7 +169,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
-(EFIAPI *EFI_BLOCK_FLUSH_EX) (
+(EFIAPI *EFI_BLOCK_FLUSH_EX)(
IN EFI_BLOCK_IO2_PROTOCOL *This,
IN OUT EFI_BLOCK_IO2_TOKEN *Token
);
@@ -186,15 +184,14 @@ struct _EFI_BLOCK_IO2_PROTOCOL {
/// A pointer to the EFI_BLOCK_IO_MEDIA data for this device.
/// Type EFI_BLOCK_IO_MEDIA is defined in BlockIo.h.
///
- EFI_BLOCK_IO_MEDIA *Media;
+ EFI_BLOCK_IO_MEDIA *Media;
- EFI_BLOCK_RESET_EX Reset;
- EFI_BLOCK_READ_EX ReadBlocksEx;
- EFI_BLOCK_WRITE_EX WriteBlocksEx;
- EFI_BLOCK_FLUSH_EX FlushBlocksEx;
+ EFI_BLOCK_RESET_EX Reset;
+ EFI_BLOCK_READ_EX ReadBlocksEx;
+ EFI_BLOCK_WRITE_EX WriteBlocksEx;
+ EFI_BLOCK_FLUSH_EX FlushBlocksEx;
};
-extern EFI_GUID gEfiBlockIo2ProtocolGuid;
+extern EFI_GUID gEfiBlockIo2ProtocolGuid;
#endif
-
diff --git a/MdePkg/Include/Protocol/DebugSupport.h b/MdePkg/Include/Protocol/DebugSupport.h
index 3ab78ee1..f65737d5 100644
--- a/MdePkg/Include/Protocol/DebugSupport.h
+++ b/MdePkg/Include/Protocol/DebugSupport.h
@@ -32,221 +32,221 @@ typedef struct _EFI_DEBUG_SUPPORT_PROTOCOL EFI_DEBUG_SUPPORT_PROTOCOL;
/// Processor exception to be hooked.
/// All exception types for IA32, X64, Itanium and EBC processors are defined.
///
-typedef INTN EFI_EXCEPTION_TYPE;
+typedef INTN EFI_EXCEPTION_TYPE;
///
/// IA-32 processor exception types.
///
-#define EXCEPT_IA32_DIVIDE_ERROR 0
-#define EXCEPT_IA32_DEBUG 1
-#define EXCEPT_IA32_NMI 2
-#define EXCEPT_IA32_BREAKPOINT 3
-#define EXCEPT_IA32_OVERFLOW 4
-#define EXCEPT_IA32_BOUND 5
-#define EXCEPT_IA32_INVALID_OPCODE 6
-#define EXCEPT_IA32_DOUBLE_FAULT 8
-#define EXCEPT_IA32_INVALID_TSS 10
-#define EXCEPT_IA32_SEG_NOT_PRESENT 11
-#define EXCEPT_IA32_STACK_FAULT 12
-#define EXCEPT_IA32_GP_FAULT 13
-#define EXCEPT_IA32_PAGE_FAULT 14
-#define EXCEPT_IA32_FP_ERROR 16
-#define EXCEPT_IA32_ALIGNMENT_CHECK 17
-#define EXCEPT_IA32_MACHINE_CHECK 18
-#define EXCEPT_IA32_SIMD 19
+#define EXCEPT_IA32_DIVIDE_ERROR 0
+#define EXCEPT_IA32_DEBUG 1
+#define EXCEPT_IA32_NMI 2
+#define EXCEPT_IA32_BREAKPOINT 3
+#define EXCEPT_IA32_OVERFLOW 4
+#define EXCEPT_IA32_BOUND 5
+#define EXCEPT_IA32_INVALID_OPCODE 6
+#define EXCEPT_IA32_DOUBLE_FAULT 8
+#define EXCEPT_IA32_INVALID_TSS 10
+#define EXCEPT_IA32_SEG_NOT_PRESENT 11
+#define EXCEPT_IA32_STACK_FAULT 12
+#define EXCEPT_IA32_GP_FAULT 13
+#define EXCEPT_IA32_PAGE_FAULT 14
+#define EXCEPT_IA32_FP_ERROR 16
+#define EXCEPT_IA32_ALIGNMENT_CHECK 17
+#define EXCEPT_IA32_MACHINE_CHECK 18
+#define EXCEPT_IA32_SIMD 19
///
/// FXSAVE_STATE.
/// FP / MMX / XMM registers (see fxrstor instruction definition).
///
typedef struct {
- UINT16 Fcw;
- UINT16 Fsw;
- UINT16 Ftw;
- UINT16 Opcode;
- UINT32 Eip;
- UINT16 Cs;
- UINT16 Reserved1;
- UINT32 DataOffset;
- UINT16 Ds;
- UINT8 Reserved2[10];
- UINT8 St0Mm0[10], Reserved3[6];
- UINT8 St1Mm1[10], Reserved4[6];
- UINT8 St2Mm2[10], Reserved5[6];
- UINT8 St3Mm3[10], Reserved6[6];
- UINT8 St4Mm4[10], Reserved7[6];
- UINT8 St5Mm5[10], Reserved8[6];
- UINT8 St6Mm6[10], Reserved9[6];
- UINT8 St7Mm7[10], Reserved10[6];
- UINT8 Xmm0[16];
- UINT8 Xmm1[16];
- UINT8 Xmm2[16];
- UINT8 Xmm3[16];
- UINT8 Xmm4[16];
- UINT8 Xmm5[16];
- UINT8 Xmm6[16];
- UINT8 Xmm7[16];
- UINT8 Reserved11[14 * 16];
+ UINT16 Fcw;
+ UINT16 Fsw;
+ UINT16 Ftw;
+ UINT16 Opcode;
+ UINT32 Eip;
+ UINT16 Cs;
+ UINT16 Reserved1;
+ UINT32 DataOffset;
+ UINT16 Ds;
+ UINT8 Reserved2[10];
+ UINT8 St0Mm0[10], Reserved3[6];
+ UINT8 St1Mm1[10], Reserved4[6];
+ UINT8 St2Mm2[10], Reserved5[6];
+ UINT8 St3Mm3[10], Reserved6[6];
+ UINT8 St4Mm4[10], Reserved7[6];
+ UINT8 St5Mm5[10], Reserved8[6];
+ UINT8 St6Mm6[10], Reserved9[6];
+ UINT8 St7Mm7[10], Reserved10[6];
+ UINT8 Xmm0[16];
+ UINT8 Xmm1[16];
+ UINT8 Xmm2[16];
+ UINT8 Xmm3[16];
+ UINT8 Xmm4[16];
+ UINT8 Xmm5[16];
+ UINT8 Xmm6[16];
+ UINT8 Xmm7[16];
+ UINT8 Reserved11[14 * 16];
} EFI_FX_SAVE_STATE_IA32;
///
/// IA-32 processor context definition.
///
typedef struct {
- UINT32 ExceptionData;
- EFI_FX_SAVE_STATE_IA32 FxSaveState;
- UINT32 Dr0;
- UINT32 Dr1;
- UINT32 Dr2;
- UINT32 Dr3;
- UINT32 Dr6;
- UINT32 Dr7;
- UINT32 Cr0;
- UINT32 Cr1; /* Reserved */
- UINT32 Cr2;
- UINT32 Cr3;
- UINT32 Cr4;
- UINT32 Eflags;
- UINT32 Ldtr;
- UINT32 Tr;
- UINT32 Gdtr[2];
- UINT32 Idtr[2];
- UINT32 Eip;
- UINT32 Gs;
- UINT32 Fs;
- UINT32 Es;
- UINT32 Ds;
- UINT32 Cs;
- UINT32 Ss;
- UINT32 Edi;
- UINT32 Esi;
- UINT32 Ebp;
- UINT32 Esp;
- UINT32 Ebx;
- UINT32 Edx;
- UINT32 Ecx;
- UINT32 Eax;
+ UINT32 ExceptionData;
+ EFI_FX_SAVE_STATE_IA32 FxSaveState;
+ UINT32 Dr0;
+ UINT32 Dr1;
+ UINT32 Dr2;
+ UINT32 Dr3;
+ UINT32 Dr6;
+ UINT32 Dr7;
+ UINT32 Cr0;
+ UINT32 Cr1; /* Reserved */
+ UINT32 Cr2;
+ UINT32 Cr3;
+ UINT32 Cr4;
+ UINT32 Eflags;
+ UINT32 Ldtr;
+ UINT32 Tr;
+ UINT32 Gdtr[2];
+ UINT32 Idtr[2];
+ UINT32 Eip;
+ UINT32 Gs;
+ UINT32 Fs;
+ UINT32 Es;
+ UINT32 Ds;
+ UINT32 Cs;
+ UINT32 Ss;
+ UINT32 Edi;
+ UINT32 Esi;
+ UINT32 Ebp;
+ UINT32 Esp;
+ UINT32 Ebx;
+ UINT32 Edx;
+ UINT32 Ecx;
+ UINT32 Eax;
} EFI_SYSTEM_CONTEXT_IA32;
///
/// x64 processor exception types.
///
-#define EXCEPT_X64_DIVIDE_ERROR 0
-#define EXCEPT_X64_DEBUG 1
-#define EXCEPT_X64_NMI 2
-#define EXCEPT_X64_BREAKPOINT 3
-#define EXCEPT_X64_OVERFLOW 4
-#define EXCEPT_X64_BOUND 5
-#define EXCEPT_X64_INVALID_OPCODE 6
-#define EXCEPT_X64_DOUBLE_FAULT 8
-#define EXCEPT_X64_INVALID_TSS 10
-#define EXCEPT_X64_SEG_NOT_PRESENT 11
-#define EXCEPT_X64_STACK_FAULT 12
-#define EXCEPT_X64_GP_FAULT 13
-#define EXCEPT_X64_PAGE_FAULT 14
-#define EXCEPT_X64_FP_ERROR 16
-#define EXCEPT_X64_ALIGNMENT_CHECK 17
-#define EXCEPT_X64_MACHINE_CHECK 18
-#define EXCEPT_X64_SIMD 19
+#define EXCEPT_X64_DIVIDE_ERROR 0
+#define EXCEPT_X64_DEBUG 1
+#define EXCEPT_X64_NMI 2
+#define EXCEPT_X64_BREAKPOINT 3
+#define EXCEPT_X64_OVERFLOW 4
+#define EXCEPT_X64_BOUND 5
+#define EXCEPT_X64_INVALID_OPCODE 6
+#define EXCEPT_X64_DOUBLE_FAULT 8
+#define EXCEPT_X64_INVALID_TSS 10
+#define EXCEPT_X64_SEG_NOT_PRESENT 11
+#define EXCEPT_X64_STACK_FAULT 12
+#define EXCEPT_X64_GP_FAULT 13
+#define EXCEPT_X64_PAGE_FAULT 14
+#define EXCEPT_X64_FP_ERROR 16
+#define EXCEPT_X64_ALIGNMENT_CHECK 17
+#define EXCEPT_X64_MACHINE_CHECK 18
+#define EXCEPT_X64_SIMD 19
///
/// FXSAVE_STATE.
/// FP / MMX / XMM registers (see fxrstor instruction definition).
///
typedef struct {
- UINT16 Fcw;
- UINT16 Fsw;
- UINT16 Ftw;
- UINT16 Opcode;
- UINT64 Rip;
- UINT64 DataOffset;
- UINT8 Reserved1[8];
- UINT8 St0Mm0[10], Reserved2[6];
- UINT8 St1Mm1[10], Reserved3[6];
- UINT8 St2Mm2[10], Reserved4[6];
- UINT8 St3Mm3[10], Reserved5[6];
- UINT8 St4Mm4[10], Reserved6[6];
- UINT8 St5Mm5[10], Reserved7[6];
- UINT8 St6Mm6[10], Reserved8[6];
- UINT8 St7Mm7[10], Reserved9[6];
- UINT8 Xmm0[16];
- UINT8 Xmm1[16];
- UINT8 Xmm2[16];
- UINT8 Xmm3[16];
- UINT8 Xmm4[16];
- UINT8 Xmm5[16];
- UINT8 Xmm6[16];
- UINT8 Xmm7[16];
+ UINT16 Fcw;
+ UINT16 Fsw;
+ UINT16 Ftw;
+ UINT16 Opcode;
+ UINT64 Rip;
+ UINT64 DataOffset;
+ UINT8 Reserved1[8];
+ UINT8 St0Mm0[10], Reserved2[6];
+ UINT8 St1Mm1[10], Reserved3[6];
+ UINT8 St2Mm2[10], Reserved4[6];
+ UINT8 St3Mm3[10], Reserved5[6];
+ UINT8 St4Mm4[10], Reserved6[6];
+ UINT8 St5Mm5[10], Reserved7[6];
+ UINT8 St6Mm6[10], Reserved8[6];
+ UINT8 St7Mm7[10], Reserved9[6];
+ UINT8 Xmm0[16];
+ UINT8 Xmm1[16];
+ UINT8 Xmm2[16];
+ UINT8 Xmm3[16];
+ UINT8 Xmm4[16];
+ UINT8 Xmm5[16];
+ UINT8 Xmm6[16];
+ UINT8 Xmm7[16];
//
// NOTE: UEFI 2.0 spec definition as follows.
//
- UINT8 Reserved11[14 * 16];
+ UINT8 Reserved11[14 * 16];
} EFI_FX_SAVE_STATE_X64;
///
/// x64 processor context definition.
///
typedef struct {
- UINT64 ExceptionData;
- EFI_FX_SAVE_STATE_X64 FxSaveState;
- UINT64 Dr0;
- UINT64 Dr1;
- UINT64 Dr2;
- UINT64 Dr3;
- UINT64 Dr6;
- UINT64 Dr7;
- UINT64 Cr0;
- UINT64 Cr1; /* Reserved */
- UINT64 Cr2;
- UINT64 Cr3;
- UINT64 Cr4;
- UINT64 Cr8;
- UINT64 Rflags;
- UINT64 Ldtr;
- UINT64 Tr;
- UINT64 Gdtr[2];
- UINT64 Idtr[2];
- UINT64 Rip;
- UINT64 Gs;
- UINT64 Fs;
- UINT64 Es;
- UINT64 Ds;
- UINT64 Cs;
- UINT64 Ss;
- UINT64 Rdi;
- UINT64 Rsi;
- UINT64 Rbp;
- UINT64 Rsp;
- UINT64 Rbx;
- UINT64 Rdx;
- UINT64 Rcx;
- UINT64 Rax;
- UINT64 R8;
- UINT64 R9;
- UINT64 R10;
- UINT64 R11;
- UINT64 R12;
- UINT64 R13;
- UINT64 R14;
- UINT64 R15;
+ UINT64 ExceptionData;
+ EFI_FX_SAVE_STATE_X64 FxSaveState;
+ UINT64 Dr0;
+ UINT64 Dr1;
+ UINT64 Dr2;
+ UINT64 Dr3;
+ UINT64 Dr6;
+ UINT64 Dr7;
+ UINT64 Cr0;
+ UINT64 Cr1; /* Reserved */
+ UINT64 Cr2;
+ UINT64 Cr3;
+ UINT64 Cr4;
+ UINT64 Cr8;
+ UINT64 Rflags;
+ UINT64 Ldtr;
+ UINT64 Tr;
+ UINT64 Gdtr[2];
+ UINT64 Idtr[2];
+ UINT64 Rip;
+ UINT64 Gs;
+ UINT64 Fs;
+ UINT64 Es;
+ UINT64 Ds;
+ UINT64 Cs;
+ UINT64 Ss;
+ UINT64 Rdi;
+ UINT64 Rsi;
+ UINT64 Rbp;
+ UINT64 Rsp;
+ UINT64 Rbx;
+ UINT64 Rdx;
+ UINT64 Rcx;
+ UINT64 Rax;
+ UINT64 R8;
+ UINT64 R9;
+ UINT64 R10;
+ UINT64 R11;
+ UINT64 R12;
+ UINT64 R13;
+ UINT64 R14;
+ UINT64 R15;
} EFI_SYSTEM_CONTEXT_X64;
///
/// Itanium Processor Family Exception types.
///
-#define EXCEPT_IPF_VHTP_TRANSLATION 0
-#define EXCEPT_IPF_INSTRUCTION_TLB 1
-#define EXCEPT_IPF_DATA_TLB 2
-#define EXCEPT_IPF_ALT_INSTRUCTION_TLB 3
-#define EXCEPT_IPF_ALT_DATA_TLB 4
-#define EXCEPT_IPF_DATA_NESTED_TLB 5
-#define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6
-#define EXCEPT_IPF_DATA_KEY_MISSED 7
-#define EXCEPT_IPF_DIRTY_BIT 8
-#define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9
-#define EXCEPT_IPF_DATA_ACCESS_BIT 10
-#define EXCEPT_IPF_BREAKPOINT 11
-#define EXCEPT_IPF_EXTERNAL_INTERRUPT 12
+#define EXCEPT_IPF_VHTP_TRANSLATION 0
+#define EXCEPT_IPF_INSTRUCTION_TLB 1
+#define EXCEPT_IPF_DATA_TLB 2
+#define EXCEPT_IPF_ALT_INSTRUCTION_TLB 3
+#define EXCEPT_IPF_ALT_DATA_TLB 4
+#define EXCEPT_IPF_DATA_NESTED_TLB 5
+#define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6
+#define EXCEPT_IPF_DATA_KEY_MISSED 7
+#define EXCEPT_IPF_DIRTY_BIT 8
+#define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9
+#define EXCEPT_IPF_DATA_ACCESS_BIT 10
+#define EXCEPT_IPF_BREAKPOINT 11
+#define EXCEPT_IPF_EXTERNAL_INTERRUPT 12
//
// 13 - 19 reserved
//
@@ -272,9 +272,9 @@ typedef struct {
//
// 37 - 44 reserved
//
-#define EXCEPT_IPF_IA32_EXCEPTION 45
-#define EXCEPT_IPF_IA32_INTERCEPT 46
-#define EXCEPT_IPF_IA32_INTERRUPT 47
+#define EXCEPT_IPF_IA32_EXCEPTION 45
+#define EXCEPT_IPF_IA32_INTERCEPT 46
+#define EXCEPT_IPF_IA32_INTERRUPT 47
///
/// IPF processor context definition.
@@ -284,391 +284,506 @@ typedef struct {
// The first reserved field is necessary to preserve alignment for the correct
// bits in UNAT and to insure F2 is 16 byte aligned.
//
- UINT64 Reserved;
- UINT64 R1;
- UINT64 R2;
- UINT64 R3;
- UINT64 R4;
- UINT64 R5;
- UINT64 R6;
- UINT64 R7;
- UINT64 R8;
- UINT64 R9;
- UINT64 R10;
- UINT64 R11;
- UINT64 R12;
- UINT64 R13;
- UINT64 R14;
- UINT64 R15;
- UINT64 R16;
- UINT64 R17;
- UINT64 R18;
- UINT64 R19;
- UINT64 R20;
- UINT64 R21;
- UINT64 R22;
- UINT64 R23;
- UINT64 R24;
- UINT64 R25;
- UINT64 R26;
- UINT64 R27;
- UINT64 R28;
- UINT64 R29;
- UINT64 R30;
- UINT64 R31;
+ UINT64 Reserved;
+ UINT64 R1;
+ UINT64 R2;
+ UINT64 R3;
+ UINT64 R4;
+ UINT64 R5;
+ UINT64 R6;
+ UINT64 R7;
+ UINT64 R8;
+ UINT64 R9;
+ UINT64 R10;
+ UINT64 R11;
+ UINT64 R12;
+ UINT64 R13;
+ UINT64 R14;
+ UINT64 R15;
+ UINT64 R16;
+ UINT64 R17;
+ UINT64 R18;
+ UINT64 R19;
+ UINT64 R20;
+ UINT64 R21;
+ UINT64 R22;
+ UINT64 R23;
+ UINT64 R24;
+ UINT64 R25;
+ UINT64 R26;
+ UINT64 R27;
+ UINT64 R28;
+ UINT64 R29;
+ UINT64 R30;
+ UINT64 R31;
- UINT64 F2[2];
- UINT64 F3[2];
- UINT64 F4[2];
- UINT64 F5[2];
- UINT64 F6[2];
- UINT64 F7[2];
- UINT64 F8[2];
- UINT64 F9[2];
- UINT64 F10[2];
- UINT64 F11[2];
- UINT64 F12[2];
- UINT64 F13[2];
- UINT64 F14[2];
- UINT64 F15[2];
- UINT64 F16[2];
- UINT64 F17[2];
- UINT64 F18[2];
- UINT64 F19[2];
- UINT64 F20[2];
- UINT64 F21[2];
- UINT64 F22[2];
- UINT64 F23[2];
- UINT64 F24[2];
- UINT64 F25[2];
- UINT64 F26[2];
- UINT64 F27[2];
- UINT64 F28[2];
- UINT64 F29[2];
- UINT64 F30[2];
- UINT64 F31[2];
+ UINT64 F2[2];
+ UINT64 F3[2];
+ UINT64 F4[2];
+ UINT64 F5[2];
+ UINT64 F6[2];
+ UINT64 F7[2];
+ UINT64 F8[2];
+ UINT64 F9[2];
+ UINT64 F10[2];
+ UINT64 F11[2];
+ UINT64 F12[2];
+ UINT64 F13[2];
+ UINT64 F14[2];
+ UINT64 F15[2];
+ UINT64 F16[2];
+ UINT64 F17[2];
+ UINT64 F18[2];
+ UINT64 F19[2];
+ UINT64 F20[2];
+ UINT64 F21[2];
+ UINT64 F22[2];
+ UINT64 F23[2];
+ UINT64 F24[2];
+ UINT64 F25[2];
+ UINT64 F26[2];
+ UINT64 F27[2];
+ UINT64 F28[2];
+ UINT64 F29[2];
+ UINT64 F30[2];
+ UINT64 F31[2];
- UINT64 Pr;
+ UINT64 Pr;
- UINT64 B0;
- UINT64 B1;
- UINT64 B2;
- UINT64 B3;
- UINT64 B4;
- UINT64 B5;
- UINT64 B6;
- UINT64 B7;
+ UINT64 B0;
+ UINT64 B1;
+ UINT64 B2;
+ UINT64 B3;
+ UINT64 B4;
+ UINT64 B5;
+ UINT64 B6;
+ UINT64 B7;
//
// application registers
//
- UINT64 ArRsc;
- UINT64 ArBsp;
- UINT64 ArBspstore;
- UINT64 ArRnat;
+ UINT64 ArRsc;
+ UINT64 ArBsp;
+ UINT64 ArBspstore;
+ UINT64 ArRnat;
- UINT64 ArFcr;
+ UINT64 ArFcr;
- UINT64 ArEflag;
- UINT64 ArCsd;
- UINT64 ArSsd;
- UINT64 ArCflg;
- UINT64 ArFsr;
- UINT64 ArFir;
- UINT64 ArFdr;
+ UINT64 ArEflag;
+ UINT64 ArCsd;
+ UINT64 ArSsd;
+ UINT64 ArCflg;
+ UINT64 ArFsr;
+ UINT64 ArFir;
+ UINT64 ArFdr;
- UINT64 ArCcv;
+ UINT64 ArCcv;
- UINT64 ArUnat;
+ UINT64 ArUnat;
- UINT64 ArFpsr;
+ UINT64 ArFpsr;
- UINT64 ArPfs;
- UINT64 ArLc;
- UINT64 ArEc;
+ UINT64 ArPfs;
+ UINT64 ArLc;
+ UINT64 ArEc;
//
// control registers
//
- UINT64 CrDcr;
- UINT64 CrItm;
- UINT64 CrIva;
- UINT64 CrPta;
- UINT64 CrIpsr;
- UINT64 CrIsr;
- UINT64 CrIip;
- UINT64 CrIfa;
- UINT64 CrItir;
- UINT64 CrIipa;
- UINT64 CrIfs;
- UINT64 CrIim;
- UINT64 CrIha;
+ UINT64 CrDcr;
+ UINT64 CrItm;
+ UINT64 CrIva;
+ UINT64 CrPta;
+ UINT64 CrIpsr;
+ UINT64 CrIsr;
+ UINT64 CrIip;
+ UINT64 CrIfa;
+ UINT64 CrItir;
+ UINT64 CrIipa;
+ UINT64 CrIfs;
+ UINT64 CrIim;
+ UINT64 CrIha;
//
// debug registers
//
- UINT64 Dbr0;
- UINT64 Dbr1;
- UINT64 Dbr2;
- UINT64 Dbr3;
- UINT64 Dbr4;
- UINT64 Dbr5;
- UINT64 Dbr6;
- UINT64 Dbr7;
+ UINT64 Dbr0;
+ UINT64 Dbr1;
+ UINT64 Dbr2;
+ UINT64 Dbr3;
+ UINT64 Dbr4;
+ UINT64 Dbr5;
+ UINT64 Dbr6;
+ UINT64 Dbr7;
- UINT64 Ibr0;
- UINT64 Ibr1;
- UINT64 Ibr2;
- UINT64 Ibr3;
- UINT64 Ibr4;
- UINT64 Ibr5;
- UINT64 Ibr6;
- UINT64 Ibr7;
+ UINT64 Ibr0;
+ UINT64 Ibr1;
+ UINT64 Ibr2;
+ UINT64 Ibr3;
+ UINT64 Ibr4;
+ UINT64 Ibr5;
+ UINT64 Ibr6;
+ UINT64 Ibr7;
//
// virtual registers - nat bits for R1-R31
//
- UINT64 IntNat;
-
+ UINT64 IntNat;
} EFI_SYSTEM_CONTEXT_IPF;
///
/// EBC processor exception types.
///
-#define EXCEPT_EBC_UNDEFINED 0
-#define EXCEPT_EBC_DIVIDE_ERROR 1
-#define EXCEPT_EBC_DEBUG 2
-#define EXCEPT_EBC_BREAKPOINT 3
-#define EXCEPT_EBC_OVERFLOW 4
-#define EXCEPT_EBC_INVALID_OPCODE 5 ///< Opcode out of range.
-#define EXCEPT_EBC_STACK_FAULT 6
-#define EXCEPT_EBC_ALIGNMENT_CHECK 7
-#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 ///< Malformed instruction.
-#define EXCEPT_EBC_BAD_BREAK 9 ///< BREAK 0 or undefined BREAK.
-#define EXCEPT_EBC_STEP 10 ///< To support debug stepping.
+#define EXCEPT_EBC_UNDEFINED 0
+#define EXCEPT_EBC_DIVIDE_ERROR 1
+#define EXCEPT_EBC_DEBUG 2
+#define EXCEPT_EBC_BREAKPOINT 3
+#define EXCEPT_EBC_OVERFLOW 4
+#define EXCEPT_EBC_INVALID_OPCODE 5 ///< Opcode out of range.
+#define EXCEPT_EBC_STACK_FAULT 6
+#define EXCEPT_EBC_ALIGNMENT_CHECK 7
+#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 ///< Malformed instruction.
+#define EXCEPT_EBC_BAD_BREAK 9 ///< BREAK 0 or undefined BREAK.
+#define EXCEPT_EBC_STEP 10 ///< To support debug stepping.
///
/// For coding convenience, define the maximum valid EBC exception.
///
-#define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP
+#define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP
///
/// EBC processor context definition.
///
typedef struct {
- UINT64 R0;
- UINT64 R1;
- UINT64 R2;
- UINT64 R3;
- UINT64 R4;
- UINT64 R5;
- UINT64 R6;
- UINT64 R7;
- UINT64 Flags;
- UINT64 ControlFlags;
- UINT64 Ip;
+ UINT64 R0;
+ UINT64 R1;
+ UINT64 R2;
+ UINT64 R3;
+ UINT64 R4;
+ UINT64 R5;
+ UINT64 R6;
+ UINT64 R7;
+ UINT64 Flags;
+ UINT64 ControlFlags;
+ UINT64 Ip;
} EFI_SYSTEM_CONTEXT_EBC;
-
-
///
/// ARM processor exception types.
///
-#define EXCEPT_ARM_RESET 0
-#define EXCEPT_ARM_UNDEFINED_INSTRUCTION 1
-#define EXCEPT_ARM_SOFTWARE_INTERRUPT 2
-#define EXCEPT_ARM_PREFETCH_ABORT 3
-#define EXCEPT_ARM_DATA_ABORT 4
-#define EXCEPT_ARM_RESERVED 5
-#define EXCEPT_ARM_IRQ 6
-#define EXCEPT_ARM_FIQ 7
+#define EXCEPT_ARM_RESET 0
+#define EXCEPT_ARM_UNDEFINED_INSTRUCTION 1
+#define EXCEPT_ARM_SOFTWARE_INTERRUPT 2
+#define EXCEPT_ARM_PREFETCH_ABORT 3
+#define EXCEPT_ARM_DATA_ABORT 4
+#define EXCEPT_ARM_RESERVED 5
+#define EXCEPT_ARM_IRQ 6
+#define EXCEPT_ARM_FIQ 7
///
/// For coding convenience, define the maximum valid ARM exception.
///
-#define MAX_ARM_EXCEPTION EXCEPT_ARM_FIQ
+#define MAX_ARM_EXCEPTION EXCEPT_ARM_FIQ
///
/// ARM processor context definition.
///
typedef struct {
- UINT32 R0;
- UINT32 R1;
- UINT32 R2;
- UINT32 R3;
- UINT32 R4;
- UINT32 R5;
- UINT32 R6;
- UINT32 R7;
- UINT32 R8;
- UINT32 R9;
- UINT32 R10;
- UINT32 R11;
- UINT32 R12;
- UINT32 SP;
- UINT32 LR;
- UINT32 PC;
- UINT32 CPSR;
- UINT32 DFSR;
- UINT32 DFAR;
- UINT32 IFSR;
- UINT32 IFAR;
+ UINT32 R0;
+ UINT32 R1;
+ UINT32 R2;
+ UINT32 R3;
+ UINT32 R4;
+ UINT32 R5;
+ UINT32 R6;
+ UINT32 R7;
+ UINT32 R8;
+ UINT32 R9;
+ UINT32 R10;
+ UINT32 R11;
+ UINT32 R12;
+ UINT32 SP;
+ UINT32 LR;
+ UINT32 PC;
+ UINT32 CPSR;
+ UINT32 DFSR;
+ UINT32 DFAR;
+ UINT32 IFSR;
+ UINT32 IFAR;
} EFI_SYSTEM_CONTEXT_ARM;
-
///
/// AARCH64 processor exception types.
///
-#define EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS 0
-#define EXCEPT_AARCH64_IRQ 1
-#define EXCEPT_AARCH64_FIQ 2
-#define EXCEPT_AARCH64_SERROR 3
+#define EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS 0
+#define EXCEPT_AARCH64_IRQ 1
+#define EXCEPT_AARCH64_FIQ 2
+#define EXCEPT_AARCH64_SERROR 3
///
/// For coding convenience, define the maximum valid ARM exception.
///
-#define MAX_AARCH64_EXCEPTION EXCEPT_AARCH64_SERROR
+#define MAX_AARCH64_EXCEPTION EXCEPT_AARCH64_SERROR
typedef struct {
// General Purpose Registers
- UINT64 X0;
- UINT64 X1;
- UINT64 X2;
- UINT64 X3;
- UINT64 X4;
- UINT64 X5;
- UINT64 X6;
- UINT64 X7;
- UINT64 X8;
- UINT64 X9;
- UINT64 X10;
- UINT64 X11;
- UINT64 X12;
- UINT64 X13;
- UINT64 X14;
- UINT64 X15;
- UINT64 X16;
- UINT64 X17;
- UINT64 X18;
- UINT64 X19;
- UINT64 X20;
- UINT64 X21;
- UINT64 X22;
- UINT64 X23;
- UINT64 X24;
- UINT64 X25;
- UINT64 X26;
- UINT64 X27;
- UINT64 X28;
- UINT64 FP; // x29 - Frame pointer
- UINT64 LR; // x30 - Link Register
- UINT64 SP; // x31 - Stack pointer
+ UINT64 X0;
+ UINT64 X1;
+ UINT64 X2;
+ UINT64 X3;
+ UINT64 X4;
+ UINT64 X5;
+ UINT64 X6;
+ UINT64 X7;
+ UINT64 X8;
+ UINT64 X9;
+ UINT64 X10;
+ UINT64 X11;
+ UINT64 X12;
+ UINT64 X13;
+ UINT64 X14;
+ UINT64 X15;
+ UINT64 X16;
+ UINT64 X17;
+ UINT64 X18;
+ UINT64 X19;
+ UINT64 X20;
+ UINT64 X21;
+ UINT64 X22;
+ UINT64 X23;
+ UINT64 X24;
+ UINT64 X25;
+ UINT64 X26;
+ UINT64 X27;
+ UINT64 X28;
+ UINT64 FP; // x29 - Frame pointer
+ UINT64 LR; // x30 - Link Register
+ UINT64 SP; // x31 - Stack pointer
// FP/SIMD Registers
- UINT64 V0[2];
- UINT64 V1[2];
- UINT64 V2[2];
- UINT64 V3[2];
- UINT64 V4[2];
- UINT64 V5[2];
- UINT64 V6[2];
- UINT64 V7[2];
- UINT64 V8[2];
- UINT64 V9[2];
- UINT64 V10[2];
- UINT64 V11[2];
- UINT64 V12[2];
- UINT64 V13[2];
- UINT64 V14[2];
- UINT64 V15[2];
- UINT64 V16[2];
- UINT64 V17[2];
- UINT64 V18[2];
- UINT64 V19[2];
- UINT64 V20[2];
- UINT64 V21[2];
- UINT64 V22[2];
- UINT64 V23[2];
- UINT64 V24[2];
- UINT64 V25[2];
- UINT64 V26[2];
- UINT64 V27[2];
- UINT64 V28[2];
- UINT64 V29[2];
- UINT64 V30[2];
- UINT64 V31[2];
+ UINT64 V0[2];
+ UINT64 V1[2];
+ UINT64 V2[2];
+ UINT64 V3[2];
+ UINT64 V4[2];
+ UINT64 V5[2];
+ UINT64 V6[2];
+ UINT64 V7[2];
+ UINT64 V8[2];
+ UINT64 V9[2];
+ UINT64 V10[2];
+ UINT64 V11[2];
+ UINT64 V12[2];
+ UINT64 V13[2];
+ UINT64 V14[2];
+ UINT64 V15[2];
+ UINT64 V16[2];
+ UINT64 V17[2];
+ UINT64 V18[2];
+ UINT64 V19[2];
+ UINT64 V20[2];
+ UINT64 V21[2];
+ UINT64 V22[2];
+ UINT64 V23[2];
+ UINT64 V24[2];
+ UINT64 V25[2];
+ UINT64 V26[2];
+ UINT64 V27[2];
+ UINT64 V28[2];
+ UINT64 V29[2];
+ UINT64 V30[2];
+ UINT64 V31[2];
- UINT64 ELR; // Exception Link Register
- UINT64 SPSR; // Saved Processor Status Register
- UINT64 FPSR; // Floating Point Status Register
- UINT64 ESR; // Exception syndrome register
- UINT64 FAR; // Fault Address Register
+ UINT64 ELR; // Exception Link Register
+ UINT64 SPSR; // Saved Processor Status Register
+ UINT64 FPSR; // Floating Point Status Register
+ UINT64 ESR; // Exception syndrome register
+ UINT64 FAR; // Fault Address Register
} EFI_SYSTEM_CONTEXT_AARCH64;
///
/// RISC-V processor exception types.
///
-#define EXCEPT_RISCV_INST_MISALIGNED 0
-#define EXCEPT_RISCV_INST_ACCESS_FAULT 1
-#define EXCEPT_RISCV_ILLEGAL_INST 2
-#define EXCEPT_RISCV_BREAKPOINT 3
-#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED 4
-#define EXCEPT_RISCV_LOAD_ACCESS_FAULT 5
-#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6
-#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7
-#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8
-#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9
-#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE 10
-#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11
+#define EXCEPT_RISCV_INST_MISALIGNED 0
+#define EXCEPT_RISCV_INST_ACCESS_FAULT 1
+#define EXCEPT_RISCV_ILLEGAL_INST 2
+#define EXCEPT_RISCV_BREAKPOINT 3
+#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED 4
+#define EXCEPT_RISCV_LOAD_ACCESS_FAULT 5
+#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6
+#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7
+#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8
+#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9
+#define EXCEPT_RISCV_ENV_CALL_FROM_VS_MODE 10
+#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11
+#define EXCEPT_RISCV_INST_ACCESS_PAGE_FAULT 12
+#define EXCEPT_RISCV_LOAD_ACCESS_PAGE_FAULT 13
+#define EXCEPT_RISCV_14 14
+#define EXCEPT_RISCV_STORE_ACCESS_PAGE_FAULT 15
+#define EXCEPT_RISCV_16 16
+#define EXCEPT_RISCV_17 17
+#define EXCEPT_RISCV_18 18
+#define EXCEPT_RISCV_19 19
+#define EXCEPT_RISCV_INST_GUEST_PAGE_FAULT 20
+#define EXCEPT_RISCV_LOAD_GUEST_PAGE_FAULT 21
+#define EXCEPT_RISCV_VIRTUAL_INSTRUCTION 22
+#define EXCEPT_RISCV_STORE_GUEST_PAGE_FAULT 23
+#define EXCEPT_RISCV_MAX_EXCEPTIONS (EXCEPT_RISCV_STORE_GUEST_PAGE_FAULT)
-#define EXCEPT_RISCV_SOFTWARE_INT 0x0
-#define EXCEPT_RISCV_TIMER_INT 0x1
+///
+/// RISC-V processor exception types for interrupts.
+///
+#define EXCEPT_RISCV_IS_IRQ(x) ((x & 0x8000000000000000UL) != 0)
+#define EXCEPT_RISCV_IRQ_INDEX(x) (x & 0x7FFFFFFFFFFFFFFFUL)
+#define EXCEPT_RISCV_IRQ_0 0x8000000000000000UL
+#define EXCEPT_RISCV_IRQ_SOFT_FROM_SMODE 0x8000000000000001UL
+#define EXCEPT_RISCV_IRQ_SOFT_FROM_VSMODE 0x8000000000000002UL
+#define EXCEPT_RISCV_IRQ_SOFT_FROM_MMODE 0x8000000000000003UL
+#define EXCEPT_RISCV_IRQ_4 0x8000000000000004UL
+#define EXCEPT_RISCV_IRQ_TIMER_FROM_SMODE 0x8000000000000005UL
+#define EXCEPT_RISCV_MAX_IRQS (EXCEPT_RISCV_IRQ_INDEX(EXCEPT_RISCV_IRQ_TIMER_FROM_SMODE))
typedef struct {
- UINT64 X0;
- UINT64 X1;
- UINT64 X2;
- UINT64 X3;
- UINT64 X4;
- UINT64 X5;
- UINT64 X6;
- UINT64 X7;
- UINT64 X8;
- UINT64 X9;
- UINT64 X10;
- UINT64 X11;
- UINT64 X12;
- UINT64 X13;
- UINT64 X14;
- UINT64 X15;
- UINT64 X16;
- UINT64 X17;
- UINT64 X18;
- UINT64 X19;
- UINT64 X20;
- UINT64 X21;
- UINT64 X22;
- UINT64 X23;
- UINT64 X24;
- UINT64 X25;
- UINT64 X26;
- UINT64 X27;
- UINT64 X28;
- UINT64 X29;
- UINT64 X30;
- UINT64 X31;
+ UINT64 X0;
+ UINT64 X1;
+ UINT64 X2;
+ UINT64 X3;
+ UINT64 X4;
+ UINT64 X5;
+ UINT64 X6;
+ UINT64 X7;
+ UINT64 X8;
+ UINT64 X9;
+ UINT64 X10;
+ UINT64 X11;
+ UINT64 X12;
+ UINT64 X13;
+ UINT64 X14;
+ UINT64 X15;
+ UINT64 X16;
+ UINT64 X17;
+ UINT64 X18;
+ UINT64 X19;
+ UINT64 X20;
+ UINT64 X21;
+ UINT64 X22;
+ UINT64 X23;
+ UINT64 X24;
+ UINT64 X25;
+ UINT64 X26;
+ UINT64 X27;
+ UINT64 X28;
+ UINT64 X29;
+ UINT64 X30;
+ UINT64 X31;
+ UINT64 SEPC;
+ UINT32 SSTATUS;
+ UINT32 STVAL;
} EFI_SYSTEM_CONTEXT_RISCV64;
+//
+// LoongArch processor exception types.
+//
+#define EXCEPT_LOONGARCH_INT 0
+#define EXCEPT_LOONGARCH_PIL 1
+#define EXCEPT_LOONGARCH_PIS 2
+#define EXCEPT_LOONGARCH_PIF 3
+#define EXCEPT_LOONGARCH_PME 4
+#define EXCEPT_LOONGARCH_PNR 5
+#define EXCEPT_LOONGARCH_PNX 6
+#define EXCEPT_LOONGARCH_PPI 7
+#define EXCEPT_LOONGARCH_ADE 8
+#define EXCEPT_LOONGARCH_ALE 9
+#define EXCEPT_LOONGARCH_BCE 10
+#define EXCEPT_LOONGARCH_SYS 11
+#define EXCEPT_LOONGARCH_BRK 12
+#define EXCEPT_LOONGARCH_INE 13
+#define EXCEPT_LOONGARCH_IPE 14
+#define EXCEPT_LOONGARCH_FPD 15
+#define EXCEPT_LOONGARCH_SXD 16
+#define EXCEPT_LOONGARCH_ASXD 17
+#define EXCEPT_LOONGARCH_FPE 18
+#define EXCEPT_LOONGARCH_TBR 64 // For code only, there is no such type in the ISA spec, the TLB refill is defined for an independent exception.
+
+//
+// LoongArch processor Interrupt types.
+//
+#define EXCEPT_LOONGARCH_INT_SIP0 0
+#define EXCEPT_LOONGARCH_INT_SIP1 1
+#define EXCEPT_LOONGARCH_INT_IP0 2
+#define EXCEPT_LOONGARCH_INT_IP1 3
+#define EXCEPT_LOONGARCH_INT_IP2 4
+#define EXCEPT_LOONGARCH_INT_IP3 5
+#define EXCEPT_LOONGARCH_INT_IP4 6
+#define EXCEPT_LOONGARCH_INT_IP5 7
+#define EXCEPT_LOONGARCH_INT_IP6 8
+#define EXCEPT_LOONGARCH_INT_IP7 9
+#define EXCEPT_LOONGARCH_INT_PMC 10
+#define EXCEPT_LOONGARCH_INT_TIMER 11
+#define EXCEPT_LOONGARCH_INT_IPI 12
+
+//
+// For coding convenience, define the maximum valid
+// LoongArch interrupt.
+//
+#define MAX_LOONGARCH_INTERRUPT 14
+
+typedef struct {
+ UINT64 R0;
+ UINT64 R1;
+ UINT64 R2;
+ UINT64 R3;
+ UINT64 R4;
+ UINT64 R5;
+ UINT64 R6;
+ UINT64 R7;
+ UINT64 R8;
+ UINT64 R9;
+ UINT64 R10;
+ UINT64 R11;
+ UINT64 R12;
+ UINT64 R13;
+ UINT64 R14;
+ UINT64 R15;
+ UINT64 R16;
+ UINT64 R17;
+ UINT64 R18;
+ UINT64 R19;
+ UINT64 R20;
+ UINT64 R21;
+ UINT64 R22;
+ UINT64 R23;
+ UINT64 R24;
+ UINT64 R25;
+ UINT64 R26;
+ UINT64 R27;
+ UINT64 R28;
+ UINT64 R29;
+ UINT64 R30;
+ UINT64 R31;
+
+ UINT64 CRMD; // CuRrent MoDe information
+ UINT64 PRMD; // PRe-exception MoDe information
+ UINT64 EUEN; // Extended component Unit ENable
+ UINT64 MISC; // MISCellaneous controller
+ UINT64 ECFG; // Exception ConFiGuration
+ UINT64 ESTAT; // Exception STATus
+ UINT64 ERA; // Exception Return Address
+ UINT64 BADV; // BAD Virtual address
+ UINT64 BADI; // BAD Instruction
+} EFI_SYSTEM_CONTEXT_LOONGARCH64;
+
///
/// Universal EFI_SYSTEM_CONTEXT definition.
///
typedef union {
- EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;
- EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;
- EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;
- EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;
- EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;
- EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;
- EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;
+ EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;
+ EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;
+ EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;
+ EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;
+ EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;
+ EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;
+ EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;
+ EFI_SYSTEM_CONTEXT_LOONGARCH64 *SystemContextLoongArch64;
} EFI_SYSTEM_CONTEXT;
//
@@ -705,15 +820,14 @@ VOID
/// Machine type definition
///
typedef enum {
- IsaIa32 = IMAGE_FILE_MACHINE_I386, ///< 0x014C
- IsaX64 = IMAGE_FILE_MACHINE_X64, ///< 0x8664
- IsaIpf = IMAGE_FILE_MACHINE_IA64, ///< 0x0200
- IsaEbc = IMAGE_FILE_MACHINE_EBC, ///< 0x0EBC
- IsaArm = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED, ///< 0x01c2
- IsaAArch64 = IMAGE_FILE_MACHINE_ARM64 ///< 0xAA64
+ IsaIa32 = IMAGE_FILE_MACHINE_I386, ///< 0x014C
+ IsaX64 = IMAGE_FILE_MACHINE_X64, ///< 0x8664
+ IsaIpf = IMAGE_FILE_MACHINE_IA64, ///< 0x0200
+ IsaEbc = IMAGE_FILE_MACHINE_EBC, ///< 0x0EBC
+ IsaArm = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED, ///< 0x01c2
+ IsaAArch64 = IMAGE_FILE_MACHINE_ARM64 ///< 0xAA64
} EFI_INSTRUCTION_SET_ARCHITECTURE;
-
//
// DebugSupport member function definitions
//
@@ -815,13 +929,13 @@ struct _EFI_DEBUG_SUPPORT_PROTOCOL {
///
/// Declares the processor architecture for this instance of the EFI Debug Support protocol.
///
- EFI_INSTRUCTION_SET_ARCHITECTURE Isa;
- EFI_GET_MAXIMUM_PROCESSOR_INDEX GetMaximumProcessorIndex;
- EFI_REGISTER_PERIODIC_CALLBACK RegisterPeriodicCallback;
- EFI_REGISTER_EXCEPTION_CALLBACK RegisterExceptionCallback;
- EFI_INVALIDATE_INSTRUCTION_CACHE InvalidateInstructionCache;
+ EFI_INSTRUCTION_SET_ARCHITECTURE Isa;
+ EFI_GET_MAXIMUM_PROCESSOR_INDEX GetMaximumProcessorIndex;
+ EFI_REGISTER_PERIODIC_CALLBACK RegisterPeriodicCallback;
+ EFI_REGISTER_EXCEPTION_CALLBACK RegisterExceptionCallback;
+ EFI_INVALIDATE_INSTRUCTION_CACHE InvalidateInstructionCache;
};
-extern EFI_GUID gEfiDebugSupportProtocolGuid;
+extern EFI_GUID gEfiDebugSupportProtocolGuid;
#endif
diff --git a/MdePkg/Include/Protocol/DevicePath.h b/MdePkg/Include/Protocol/DevicePath.h
index 5eeca70c..b80cb6ff 100644
--- a/MdePkg/Include/Protocol/DevicePath.h
+++ b/MdePkg/Include/Protocol/DevicePath.h
@@ -41,97 +41,96 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
that make up the Device Path.
**/
typedef struct {
- UINT8 Type; ///< 0x01 Hardware Device Path.
+ UINT8 Type; ///< 0x01 Hardware Device Path.
///< 0x02 ACPI Device Path.
///< 0x03 Messaging Device Path.
///< 0x04 Media Device Path.
///< 0x05 BIOS Boot Specification Device Path.
///< 0x7F End of Hardware Device Path.
- UINT8 SubType; ///< Varies by Type
+ UINT8 SubType; ///< Varies by Type
///< 0xFF End Entire Device Path, or
///< 0x01 End This Instance of a Device Path and start a new
///< Device Path.
- UINT8 Length[2]; ///< Specific Device Path data. Type and Sub-Type define
- ///< type of data. Size of data is included in Length.
-
+ UINT8 Length[2]; ///< Specific Device Path data. Type and Sub-Type define
+ ///< type of data. Size of data is included in Length.
} EFI_DEVICE_PATH_PROTOCOL;
///
/// Device Path protocol definition for backward-compatible with EFI1.1.
///
-typedef EFI_DEVICE_PATH_PROTOCOL EFI_DEVICE_PATH;
+typedef EFI_DEVICE_PATH_PROTOCOL EFI_DEVICE_PATH;
///
/// Hardware Device Paths.
///
-#define HARDWARE_DEVICE_PATH 0x01
+#define HARDWARE_DEVICE_PATH 0x01
///
/// PCI Device Path SubType.
///
-#define HW_PCI_DP 0x01
+#define HW_PCI_DP 0x01
///
/// PCI Device Path.
///
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// PCI Function Number.
///
- UINT8 Function;
+ UINT8 Function;
///
/// PCI Device Number.
///
- UINT8 Device;
+ UINT8 Device;
} PCI_DEVICE_PATH;
///
/// PCCARD Device Path SubType.
///
-#define HW_PCCARD_DP 0x02
+#define HW_PCCARD_DP 0x02
///
/// PCCARD Device Path.
///
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Function Number (0 = First Function).
///
- UINT8 FunctionNumber;
+ UINT8 FunctionNumber;
} PCCARD_DEVICE_PATH;
///
/// Memory Mapped Device Path SubType.
///
-#define HW_MEMMAP_DP 0x03
+#define HW_MEMMAP_DP 0x03
///
/// Memory Mapped Device Path.
///
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// EFI_MEMORY_TYPE
///
- UINT32 MemoryType;
+ UINT32 MemoryType;
///
/// Starting Memory Address.
///
- EFI_PHYSICAL_ADDRESS StartingAddress;
+ EFI_PHYSICAL_ADDRESS StartingAddress;
///
/// Ending Memory Address.
///
- EFI_PHYSICAL_ADDRESS EndingAddress;
+ EFI_PHYSICAL_ADDRESS EndingAddress;
} MEMMAP_DEVICE_PATH;
///
/// Hardware Vendor Device Path SubType.
///
-#define HW_VENDOR_DP 0x04
+#define HW_VENDOR_DP 0x04
///
/// The Vendor Device Path allows the creation of vendor-defined Device Paths. A vendor must
@@ -139,11 +138,11 @@ typedef struct {
/// contents on the n bytes that follow in the Vendor Device Path node.
///
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Vendor-assigned GUID that defines the data that follows.
///
- EFI_GUID Guid;
+ EFI_GUID Guid;
///
/// Vendor-defined variable size data.
///
@@ -152,56 +151,56 @@ typedef struct {
///
/// Controller Device Path SubType.
///
-#define HW_CONTROLLER_DP 0x05
+#define HW_CONTROLLER_DP 0x05
///
/// Controller Device Path.
///
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Controller number.
///
- UINT32 ControllerNumber;
+ UINT32 ControllerNumber;
} CONTROLLER_DEVICE_PATH;
///
/// BMC Device Path SubType.
///
-#define HW_BMC_DP 0x06
+#define HW_BMC_DP 0x06
///
/// BMC Device Path.
///
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Interface Type.
///
- UINT8 InterfaceType;
+ UINT8 InterfaceType;
///
/// Base Address.
///
- UINT8 BaseAddress[8];
+ UINT8 BaseAddress[8];
} BMC_DEVICE_PATH;
///
/// ACPI Device Paths.
///
-#define ACPI_DEVICE_PATH 0x02
+#define ACPI_DEVICE_PATH 0x02
///
/// ACPI Device Path SubType.
///
-#define ACPI_DP 0x01
+#define ACPI_DP 0x01
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Device's PnP hardware ID stored in a numeric 32-bit
/// compressed EISA-type ID. This value must match the
/// corresponding _HID in the ACPI name space.
///
- UINT32 HID;
+ UINT32 HID;
///
/// Unique ID that is required by ACPI if two devices have the
/// same _HID. This value must also match the corresponding
@@ -209,34 +208,34 @@ typedef struct {
/// numeric value type of _UID is supported. Thus, strings must
/// not be used for the _UID in the ACPI name space.
///
- UINT32 UID;
+ UINT32 UID;
} ACPI_HID_DEVICE_PATH;
///
/// Expanded ACPI Device Path SubType.
///
-#define ACPI_EXTENDED_DP 0x02
+#define ACPI_EXTENDED_DP 0x02
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Device's PnP hardware ID stored in a numeric 32-bit
/// compressed EISA-type ID. This value must match the
/// corresponding _HID in the ACPI name space.
///
- UINT32 HID;
+ UINT32 HID;
///
/// Unique ID that is required by ACPI if two devices have the
/// same _HID. This value must also match the corresponding
/// _UID/_HID pair in the ACPI name space.
///
- UINT32 UID;
+ UINT32 UID;
///
/// Device's compatible PnP hardware ID stored in a numeric
/// 32-bit compressed EISA-type ID. This value must match at
/// least one of the compatible device IDs returned by the
/// corresponding _CID in the ACPI name space.
///
- UINT32 CID;
+ UINT32 CID;
///
/// Optional variable length _HIDSTR.
/// Optional variable length _UIDSTR.
@@ -251,18 +250,18 @@ typedef struct {
// bits[31:16] - binary number
// Compressed ASCII is 5 bits per character 0b00001 = 'A' 0b11010 = 'Z'
//
-#define PNP_EISA_ID_CONST 0x41d0
-#define EISA_ID(_Name, _Num) ((UINT32)((_Name) | (_Num) << 16))
-#define EISA_PNP_ID(_PNPId) (EISA_ID(PNP_EISA_ID_CONST, (_PNPId)))
-#define EFI_PNP_ID(_PNPId) (EISA_ID(PNP_EISA_ID_CONST, (_PNPId)))
+#define PNP_EISA_ID_CONST 0x41d0
+#define EISA_ID(_Name, _Num) ((UINT32)((_Name) | (_Num) << 16))
+#define EISA_PNP_ID(_PNPId) (EISA_ID(PNP_EISA_ID_CONST, (_PNPId)))
+#define EFI_PNP_ID(_PNPId) (EISA_ID(PNP_EISA_ID_CONST, (_PNPId)))
-#define PNP_EISA_ID_MASK 0xffff
-#define EISA_ID_TO_NUM(_Id) ((_Id) >> 16)
+#define PNP_EISA_ID_MASK 0xffff
+#define EISA_ID_TO_NUM(_Id) ((_Id) >> 16)
///
/// ACPI _ADR Device Path SubType.
///
-#define ACPI_ADR_DP 0x03
+#define ACPI_ADR_DP 0x03
///
/// The _ADR device path is used to contain video output device attributes to support the Graphics
@@ -270,13 +269,13 @@ typedef struct {
/// devices are displaying the same output.
///
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// _ADR value. For video output devices the value of this
/// field comes from Table B-2 of the ACPI 3.0 specification. At
/// least one _ADR value is required.
///
- UINT32 ADR;
+ UINT32 ADR;
//
// This device path may optionally contain more than one _ADR entry.
//
@@ -285,16 +284,16 @@ typedef struct {
///
/// ACPI NVDIMM Device Path SubType.
///
-#define ACPI_NVDIMM_DP 0x04
+#define ACPI_NVDIMM_DP 0x04
///
///
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// NFIT Device Handle, the _ADR of the NVDIMM device.
/// The value of this field comes from Section 9.20.3 of the ACPI 6.2A specification.
///
- UINT32 NFITDeviceHandle;
+ UINT32 NFITDeviceHandle;
} ACPI_NVDIMM_DEVICE_PATH;
#define ACPI_ADR_DISPLAY_TYPE_OTHER 0
@@ -319,171 +318,171 @@ typedef struct {
/// system. This Device Path can describe physical messaging information like SCSI ID, or abstract
/// information like networking protocol IP addresses.
///
-#define MESSAGING_DEVICE_PATH 0x03
+#define MESSAGING_DEVICE_PATH 0x03
///
/// ATAPI Device Path SubType
///
-#define MSG_ATAPI_DP 0x01
+#define MSG_ATAPI_DP 0x01
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Set to zero for primary, or one for secondary.
///
- UINT8 PrimarySecondary;
+ UINT8 PrimarySecondary;
///
/// Set to zero for master, or one for slave mode.
///
- UINT8 SlaveMaster;
+ UINT8 SlaveMaster;
///
/// Logical Unit Number.
///
- UINT16 Lun;
+ UINT16 Lun;
} ATAPI_DEVICE_PATH;
///
/// SCSI Device Path SubType.
///
-#define MSG_SCSI_DP 0x02
+#define MSG_SCSI_DP 0x02
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Target ID on the SCSI bus (PUN).
///
- UINT16 Pun;
+ UINT16 Pun;
///
/// Logical Unit Number (LUN).
///
- UINT16 Lun;
+ UINT16 Lun;
} SCSI_DEVICE_PATH;
///
/// Fibre Channel SubType.
///
-#define MSG_FIBRECHANNEL_DP 0x03
+#define MSG_FIBRECHANNEL_DP 0x03
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Reserved for the future.
///
- UINT32 Reserved;
+ UINT32 Reserved;
///
/// Fibre Channel World Wide Number.
///
- UINT64 WWN;
+ UINT64 WWN;
///
/// Fibre Channel Logical Unit Number.
///
- UINT64 Lun;
+ UINT64 Lun;
} FIBRECHANNEL_DEVICE_PATH;
///
/// Fibre Channel Ex SubType.
///
-#define MSG_FIBRECHANNELEX_DP 0x15
+#define MSG_FIBRECHANNELEX_DP 0x15
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Reserved for the future.
///
- UINT32 Reserved;
+ UINT32 Reserved;
///
/// 8 byte array containing Fibre Channel End Device Port Name.
///
- UINT8 WWN[8];
+ UINT8 WWN[8];
///
/// 8 byte array containing Fibre Channel Logical Unit Number.
///
- UINT8 Lun[8];
+ UINT8 Lun[8];
} FIBRECHANNELEX_DEVICE_PATH;
///
/// 1394 Device Path SubType
///
-#define MSG_1394_DP 0x04
+#define MSG_1394_DP 0x04
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Reserved for the future.
///
- UINT32 Reserved;
+ UINT32 Reserved;
///
/// 1394 Global Unique ID (GUID).
///
- UINT64 Guid;
+ UINT64 Guid;
} F1394_DEVICE_PATH;
///
/// USB Device Path SubType.
///
-#define MSG_USB_DP 0x05
+#define MSG_USB_DP 0x05
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// USB Parent Port Number.
///
- UINT8 ParentPortNumber;
+ UINT8 ParentPortNumber;
///
/// USB Interface Number.
///
- UINT8 InterfaceNumber;
+ UINT8 InterfaceNumber;
} USB_DEVICE_PATH;
///
/// USB Class Device Path SubType.
///
-#define MSG_USB_CLASS_DP 0x0f
+#define MSG_USB_CLASS_DP 0x0f
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Vendor ID assigned by USB-IF. A value of 0xFFFF will
/// match any Vendor ID.
///
- UINT16 VendorId;
+ UINT16 VendorId;
///
/// Product ID assigned by USB-IF. A value of 0xFFFF will
/// match any Product ID.
///
- UINT16 ProductId;
+ UINT16 ProductId;
///
/// The class code assigned by the USB-IF. A value of 0xFF
/// will match any class code.
///
- UINT8 DeviceClass;
+ UINT8 DeviceClass;
///
/// The subclass code assigned by the USB-IF. A value of
/// 0xFF will match any subclass code.
///
- UINT8 DeviceSubClass;
+ UINT8 DeviceSubClass;
///
/// The protocol code assigned by the USB-IF. A value of
/// 0xFF will match any protocol code.
///
- UINT8 DeviceProtocol;
+ UINT8 DeviceProtocol;
} USB_CLASS_DEVICE_PATH;
///
/// USB WWID Device Path SubType.
///
-#define MSG_USB_WWID_DP 0x10
+#define MSG_USB_WWID_DP 0x10
///
/// This device path describes a USB device using its serial number.
///
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// USB interface number.
///
- UINT16 InterfaceNumber;
+ UINT16 InterfaceNumber;
///
/// USB vendor id of the device.
///
- UINT16 VendorId;
+ UINT16 VendorId;
///
/// USB product id of the device.
///
- UINT16 ProductId;
+ UINT16 ProductId;
///
/// Last 64-or-fewer UTF-16 characters of the USB
/// serial number. The length of the string is
@@ -498,136 +497,136 @@ typedef struct {
///
#define MSG_DEVICE_LOGICAL_UNIT_DP 0x11
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Logical Unit Number for the interface.
///
- UINT8 Lun;
+ UINT8 Lun;
} DEVICE_LOGICAL_UNIT_DEVICE_PATH;
///
/// SATA Device Path SubType.
///
-#define MSG_SATA_DP 0x12
+#define MSG_SATA_DP 0x12
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// The HBA port number that facilitates the connection to the
/// device or a port multiplier. The value 0xFFFF is reserved.
///
- UINT16 HBAPortNumber;
+ UINT16 HBAPortNumber;
///
/// The Port multiplier port number that facilitates the connection
/// to the device. Must be set to 0xFFFF if the device is directly
/// connected to the HBA.
///
- UINT16 PortMultiplierPortNumber;
+ UINT16 PortMultiplierPortNumber;
///
/// Logical Unit Number.
///
- UINT16 Lun;
+ UINT16 Lun;
} SATA_DEVICE_PATH;
///
/// Flag for if the device is directly connected to the HBA.
///
-#define SATA_HBA_DIRECT_CONNECT_FLAG 0x8000
+#define SATA_HBA_DIRECT_CONNECT_FLAG 0x8000
///
/// I2O Device Path SubType.
///
-#define MSG_I2O_DP 0x06
+#define MSG_I2O_DP 0x06
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Target ID (TID) for a device.
///
- UINT32 Tid;
+ UINT32 Tid;
} I2O_DEVICE_PATH;
///
/// MAC Address Device Path SubType.
///
-#define MSG_MAC_ADDR_DP 0x0b
+#define MSG_MAC_ADDR_DP 0x0b
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// The MAC address for a network interface padded with 0s.
///
- EFI_MAC_ADDRESS MacAddress;
+ EFI_MAC_ADDRESS MacAddress;
///
/// Network interface type(i.e. 802.3, FDDI).
///
- UINT8 IfType;
+ UINT8 IfType;
} MAC_ADDR_DEVICE_PATH;
///
/// IPv4 Device Path SubType
///
-#define MSG_IPv4_DP 0x0c
+#define MSG_IPv4_DP 0x0c
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// The local IPv4 address.
///
- EFI_IPv4_ADDRESS LocalIpAddress;
+ EFI_IPv4_ADDRESS LocalIpAddress;
///
/// The remote IPv4 address.
///
- EFI_IPv4_ADDRESS RemoteIpAddress;
+ EFI_IPv4_ADDRESS RemoteIpAddress;
///
/// The local port number.
///
- UINT16 LocalPort;
+ UINT16 LocalPort;
///
/// The remote port number.
///
- UINT16 RemotePort;
+ UINT16 RemotePort;
///
/// The network protocol(i.e. UDP, TCP).
///
- UINT16 Protocol;
+ UINT16 Protocol;
///
/// 0x00 - The Source IP Address was assigned though DHCP.
/// 0x01 - The Source IP Address is statically bound.
///
- BOOLEAN StaticIpAddress;
+ BOOLEAN StaticIpAddress;
///
/// The gateway IP address
///
- EFI_IPv4_ADDRESS GatewayIpAddress;
+ EFI_IPv4_ADDRESS GatewayIpAddress;
///
/// The subnet mask
///
- EFI_IPv4_ADDRESS SubnetMask;
+ EFI_IPv4_ADDRESS SubnetMask;
} IPv4_DEVICE_PATH;
///
/// IPv6 Device Path SubType.
///
-#define MSG_IPv6_DP 0x0d
+#define MSG_IPv6_DP 0x0d
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// The local IPv6 address.
///
- EFI_IPv6_ADDRESS LocalIpAddress;
+ EFI_IPv6_ADDRESS LocalIpAddress;
///
/// The remote IPv6 address.
///
- EFI_IPv6_ADDRESS RemoteIpAddress;
+ EFI_IPv6_ADDRESS RemoteIpAddress;
///
/// The local port number.
///
- UINT16 LocalPort;
+ UINT16 LocalPort;
///
/// The remote port number.
///
- UINT16 RemotePort;
+ UINT16 RemotePort;
///
/// The network protocol(i.e. UDP, TCP).
///
- UINT16 Protocol;
+ UINT16 Protocol;
///
/// 0x00 - The Local IP Address was manually configured.
/// 0x01 - The Local IP Address is assigned through IPv6
@@ -635,23 +634,23 @@ typedef struct {
/// 0x02 - The Local IP Address is assigned through IPv6
/// stateful configuration.
///
- UINT8 IpAddressOrigin;
+ UINT8 IpAddressOrigin;
///
/// The prefix length
///
- UINT8 PrefixLength;
+ UINT8 PrefixLength;
///
/// The gateway IP address
///
- EFI_IPv6_ADDRESS GatewayIpAddress;
+ EFI_IPv6_ADDRESS GatewayIpAddress;
} IPv6_DEVICE_PATH;
///
/// InfiniBand Device Path SubType.
///
-#define MSG_INFINIBAND_DP 0x09
+#define MSG_INFINIBAND_DP 0x09
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Flags to help identify/manage InfiniBand device path elements:
/// Bit 0 - IOC/Service (0b = IOC, 1b = Service).
@@ -661,24 +660,24 @@ typedef struct {
/// Bit 4 - Network Protocol.
/// All other bits are reserved.
///
- UINT32 ResourceFlags;
+ UINT32 ResourceFlags;
///
/// 128-bit Global Identifier for remote fabric port.
///
- UINT8 PortGid[16];
+ UINT8 PortGid[16];
///
/// 64-bit unique identifier to remote IOC or server process.
/// Interpretation of field specified by Resource Flags (bit 0).
///
- UINT64 ServiceId;
+ UINT64 ServiceId;
///
/// 64-bit persistent ID of remote IOC port.
///
- UINT64 TargetPortId;
+ UINT64 TargetPortId;
///
/// 64-bit persistent ID of remote device.
///
- UINT64 DeviceId;
+ UINT64 DeviceId;
} INFINIBAND_DEVICE_PATH;
#define INFINIBAND_RESOURCE_FLAG_IOC_SERVICE 0x01
@@ -690,23 +689,23 @@ typedef struct {
///
/// UART Device Path SubType.
///
-#define MSG_UART_DP 0x0e
+#define MSG_UART_DP 0x0e
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Reserved.
///
- UINT32 Reserved;
+ UINT32 Reserved;
///
/// The baud rate setting for the UART style device. A value of 0
/// means that the device's default baud rate will be used.
///
- UINT64 BaudRate;
+ UINT64 BaudRate;
///
/// The number of data bits for the UART style device. A value
/// of 0 means that the device's default number of data bits will be used.
///
- UINT8 DataBits;
+ UINT8 DataBits;
///
/// The parity setting for the UART style device.
/// Parity 0x00 - Default Parity.
@@ -716,7 +715,7 @@ typedef struct {
/// Parity 0x04 - Mark Parity.
/// Parity 0x05 - Space Parity.
///
- UINT8 Parity;
+ UINT8 Parity;
///
/// The number of stop bits for the UART style device.
/// Stop Bits 0x00 - Default Stop Bits.
@@ -724,205 +723,205 @@ typedef struct {
/// Stop Bits 0x02 - 1.5 Stop Bits.
/// Stop Bits 0x03 - 2 Stop Bits.
///
- UINT8 StopBits;
+ UINT8 StopBits;
} UART_DEVICE_PATH;
///
/// NVDIMM Namespace Device Path SubType.
///
-#define NVDIMM_NAMESPACE_DP 0x20
+#define NVDIMM_NAMESPACE_DP 0x20
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Namespace unique label identifier UUID.
///
- EFI_GUID Uuid;
+ EFI_GUID Uuid;
} NVDIMM_NAMESPACE_DEVICE_PATH;
//
// Use VENDOR_DEVICE_PATH struct
//
-#define MSG_VENDOR_DP 0x0a
-typedef VENDOR_DEVICE_PATH VENDOR_DEFINED_DEVICE_PATH;
+#define MSG_VENDOR_DP 0x0a
+typedef VENDOR_DEVICE_PATH VENDOR_DEFINED_DEVICE_PATH;
-#define DEVICE_PATH_MESSAGING_PC_ANSI EFI_PC_ANSI_GUID
-#define DEVICE_PATH_MESSAGING_VT_100 EFI_VT_100_GUID
-#define DEVICE_PATH_MESSAGING_VT_100_PLUS EFI_VT_100_PLUS_GUID
-#define DEVICE_PATH_MESSAGING_VT_UTF8 EFI_VT_UTF8_GUID
+#define DEVICE_PATH_MESSAGING_PC_ANSI EFI_PC_ANSI_GUID
+#define DEVICE_PATH_MESSAGING_VT_100 EFI_VT_100_GUID
+#define DEVICE_PATH_MESSAGING_VT_100_PLUS EFI_VT_100_PLUS_GUID
+#define DEVICE_PATH_MESSAGING_VT_UTF8 EFI_VT_UTF8_GUID
///
/// A new device path node is defined to declare flow control characteristics.
/// UART Flow Control Messaging Device Path
///
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// DEVICE_PATH_MESSAGING_UART_FLOW_CONTROL GUID.
///
- EFI_GUID Guid;
+ EFI_GUID Guid;
///
/// Bitmap of supported flow control types.
/// Bit 0 set indicates hardware flow control.
/// Bit 1 set indicates Xon/Xoff flow control.
/// All other bits are reserved and are clear.
///
- UINT32 FlowControlMap;
+ UINT32 FlowControlMap;
} UART_FLOW_CONTROL_DEVICE_PATH;
-#define UART_FLOW_CONTROL_HARDWARE 0x00000001
-#define UART_FLOW_CONTROL_XON_XOFF 0x00000010
+#define UART_FLOW_CONTROL_HARDWARE 0x00000001
+#define UART_FLOW_CONTROL_XON_XOFF 0x00000010
-#define DEVICE_PATH_MESSAGING_SAS EFI_SAS_DEVICE_PATH_GUID
+#define DEVICE_PATH_MESSAGING_SAS EFI_SAS_DEVICE_PATH_GUID
///
/// Serial Attached SCSI (SAS) Device Path.
///
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// DEVICE_PATH_MESSAGING_SAS GUID.
///
- EFI_GUID Guid;
+ EFI_GUID Guid;
///
/// Reserved for future use.
///
- UINT32 Reserved;
+ UINT32 Reserved;
///
/// SAS Address for Serial Attached SCSI Target.
///
- UINT64 SasAddress;
+ UINT64 SasAddress;
///
/// SAS Logical Unit Number.
///
- UINT64 Lun;
+ UINT64 Lun;
///
/// More Information about the device and its interconnect.
///
- UINT16 DeviceTopology;
+ UINT16 DeviceTopology;
///
/// Relative Target Port (RTP).
///
- UINT16 RelativeTargetPort;
+ UINT16 RelativeTargetPort;
} SAS_DEVICE_PATH;
///
/// Serial Attached SCSI (SAS) Ex Device Path SubType
///
-#define MSG_SASEX_DP 0x16
+#define MSG_SASEX_DP 0x16
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// 8-byte array of the SAS Address for Serial Attached SCSI Target Port.
///
- UINT8 SasAddress[8];
+ UINT8 SasAddress[8];
///
/// 8-byte array of the SAS Logical Unit Number.
///
- UINT8 Lun[8];
+ UINT8 Lun[8];
///
/// More Information about the device and its interconnect.
///
- UINT16 DeviceTopology;
+ UINT16 DeviceTopology;
///
/// Relative Target Port (RTP).
///
- UINT16 RelativeTargetPort;
+ UINT16 RelativeTargetPort;
} SASEX_DEVICE_PATH;
///
/// NvmExpress Namespace Device Path SubType.
///
-#define MSG_NVME_NAMESPACE_DP 0x17
+#define MSG_NVME_NAMESPACE_DP 0x17
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
- UINT32 NamespaceId;
- UINT64 NamespaceUuid;
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ UINT32 NamespaceId;
+ UINT64 NamespaceUuid;
} NVME_NAMESPACE_DEVICE_PATH;
///
/// DNS Device Path SubType
///
-#define MSG_DNS_DP 0x1F
+#define MSG_DNS_DP 0x1F
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Indicates the DNS server address is IPv4 or IPv6 address.
///
- UINT8 IsIPv6;
+ UINT8 IsIPv6;
///
/// Instance of the DNS server address.
///
- EFI_IP_ADDRESS DnsServerIp[];
+ EFI_IP_ADDRESS DnsServerIp[];
} DNS_DEVICE_PATH;
///
/// Uniform Resource Identifiers (URI) Device Path SubType
///
-#define MSG_URI_DP 0x18
+#define MSG_URI_DP 0x18
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Instance of the URI pursuant to RFC 3986.
///
- CHAR8 Uri[];
+ CHAR8 Uri[];
} URI_DEVICE_PATH;
///
/// Universal Flash Storage (UFS) Device Path SubType.
///
-#define MSG_UFS_DP 0x19
+#define MSG_UFS_DP 0x19
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Target ID on the UFS bus (PUN).
///
- UINT8 Pun;
+ UINT8 Pun;
///
/// Logical Unit Number (LUN).
///
- UINT8 Lun;
+ UINT8 Lun;
} UFS_DEVICE_PATH;
///
/// SD (Secure Digital) Device Path SubType.
///
-#define MSG_SD_DP 0x1A
+#define MSG_SD_DP 0x1A
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
- UINT8 SlotNumber;
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ UINT8 SlotNumber;
} SD_DEVICE_PATH;
///
/// EMMC (Embedded MMC) Device Path SubType.
///
-#define MSG_EMMC_DP 0x1D
+#define MSG_EMMC_DP 0x1D
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
- UINT8 SlotNumber;
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ UINT8 SlotNumber;
} EMMC_DEVICE_PATH;
///
/// iSCSI Device Path SubType
///
-#define MSG_ISCSI_DP 0x13
+#define MSG_ISCSI_DP 0x13
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Network Protocol (0 = TCP, 1+ = reserved).
///
- UINT16 NetworkProtocol;
+ UINT16 NetworkProtocol;
///
/// iSCSI Login Options.
///
- UINT16 LoginOption;
+ UINT16 LoginOption;
///
/// iSCSI Logical Unit Number.
///
- UINT64 Lun;
+ UINT64 Lun;
///
/// iSCSI Target Portal group tag the initiator intends
/// to establish a session with.
///
- UINT16 TargetPortalGroupTag;
+ UINT16 TargetPortalGroupTag;
///
/// iSCSI NodeTarget Name. The length of the name
/// is determined by subtracting the offset of this field from Length.
@@ -930,90 +929,90 @@ typedef struct {
/// CHAR8 iSCSI Target Name.
} ISCSI_DEVICE_PATH;
-#define ISCSI_LOGIN_OPTION_NO_HEADER_DIGEST 0x0000
-#define ISCSI_LOGIN_OPTION_HEADER_DIGEST_USING_CRC32C 0x0002
-#define ISCSI_LOGIN_OPTION_NO_DATA_DIGEST 0x0000
-#define ISCSI_LOGIN_OPTION_DATA_DIGEST_USING_CRC32C 0x0008
-#define ISCSI_LOGIN_OPTION_AUTHMETHOD_CHAP 0x0000
-#define ISCSI_LOGIN_OPTION_AUTHMETHOD_NON 0x1000
-#define ISCSI_LOGIN_OPTION_CHAP_BI 0x0000
-#define ISCSI_LOGIN_OPTION_CHAP_UNI 0x2000
+#define ISCSI_LOGIN_OPTION_NO_HEADER_DIGEST 0x0000
+#define ISCSI_LOGIN_OPTION_HEADER_DIGEST_USING_CRC32C 0x0002
+#define ISCSI_LOGIN_OPTION_NO_DATA_DIGEST 0x0000
+#define ISCSI_LOGIN_OPTION_DATA_DIGEST_USING_CRC32C 0x0008
+#define ISCSI_LOGIN_OPTION_AUTHMETHOD_CHAP 0x0000
+#define ISCSI_LOGIN_OPTION_AUTHMETHOD_NON 0x1000
+#define ISCSI_LOGIN_OPTION_CHAP_BI 0x0000
+#define ISCSI_LOGIN_OPTION_CHAP_UNI 0x2000
///
/// VLAN Device Path SubType.
///
-#define MSG_VLAN_DP 0x14
+#define MSG_VLAN_DP 0x14
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// VLAN identifier (0-4094).
///
- UINT16 VlanId;
+ UINT16 VlanId;
} VLAN_DEVICE_PATH;
///
/// Bluetooth Device Path SubType.
///
-#define MSG_BLUETOOTH_DP 0x1b
+#define MSG_BLUETOOTH_DP 0x1b
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// 48bit Bluetooth device address.
///
- BLUETOOTH_ADDRESS BD_ADDR;
+ BLUETOOTH_ADDRESS BD_ADDR;
} BLUETOOTH_DEVICE_PATH;
///
/// Wi-Fi Device Path SubType.
///
-#define MSG_WIFI_DP 0x1C
+#define MSG_WIFI_DP 0x1C
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Service set identifier. A 32-byte octets string.
///
- UINT8 SSId[32];
+ UINT8 SSId[32];
} WIFI_DEVICE_PATH;
///
/// Bluetooth LE Device Path SubType.
///
-#define MSG_BLUETOOTH_LE_DP 0x1E
+#define MSG_BLUETOOTH_LE_DP 0x1E
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
- BLUETOOTH_LE_ADDRESS Address;
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ BLUETOOTH_LE_ADDRESS Address;
} BLUETOOTH_LE_DEVICE_PATH;
//
// Media Device Path
//
-#define MEDIA_DEVICE_PATH 0x04
+#define MEDIA_DEVICE_PATH 0x04
///
/// Hard Drive Media Device Path SubType.
///
-#define MEDIA_HARDDRIVE_DP 0x01
+#define MEDIA_HARDDRIVE_DP 0x01
///
/// The Hard Drive Media Device Path is used to represent a partition on a hard drive.
///
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Describes the entry in a partition table, starting with entry 1.
/// Partition number zero represents the entire device. Valid
/// partition numbers for a MBR partition are [1, 4]. Valid
/// partition numbers for a GPT partition are [1, NumberOfPartitionEntries].
///
- UINT32 PartitionNumber;
+ UINT32 PartitionNumber;
///
/// Starting LBA of the partition on the hard drive.
///
- UINT64 PartitionStart;
+ UINT64 PartitionStart;
///
/// Size of the partition in units of Logical Blocks.
///
- UINT64 PartitionSize;
+ UINT64 PartitionSize;
///
/// Signature unique to this partition:
/// If SignatureType is 0, this field has to be initialized with 16 zeros.
@@ -1021,68 +1020,68 @@ typedef struct {
/// The other 12 bytes are initialized with zeros.
/// If SignatureType is 2, this field contains a 16 byte signature.
///
- UINT8 Signature[16];
+ UINT8 Signature[16];
///
/// Partition Format: (Unused values reserved).
/// 0x01 - PC-AT compatible legacy MBR.
/// 0x02 - GUID Partition Table.
///
- UINT8 MBRType;
+ UINT8 MBRType;
///
/// Type of Disk Signature: (Unused values reserved).
/// 0x00 - No Disk Signature.
/// 0x01 - 32-bit signature from address 0x1b8 of the type 0x01 MBR.
/// 0x02 - GUID signature.
///
- UINT8 SignatureType;
+ UINT8 SignatureType;
} HARDDRIVE_DEVICE_PATH;
-#define MBR_TYPE_PCAT 0x01
-#define MBR_TYPE_EFI_PARTITION_TABLE_HEADER 0x02
+#define MBR_TYPE_PCAT 0x01
+#define MBR_TYPE_EFI_PARTITION_TABLE_HEADER 0x02
-#define NO_DISK_SIGNATURE 0x00
-#define SIGNATURE_TYPE_MBR 0x01
-#define SIGNATURE_TYPE_GUID 0x02
+#define NO_DISK_SIGNATURE 0x00
+#define SIGNATURE_TYPE_MBR 0x01
+#define SIGNATURE_TYPE_GUID 0x02
///
/// CD-ROM Media Device Path SubType.
///
-#define MEDIA_CDROM_DP 0x02
+#define MEDIA_CDROM_DP 0x02
///
/// The CD-ROM Media Device Path is used to define a system partition that exists on a CD-ROM.
///
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Boot Entry number from the Boot Catalog. The Initial/Default entry is defined as zero.
///
- UINT32 BootEntry;
+ UINT32 BootEntry;
///
/// Starting RBA of the partition on the medium. CD-ROMs use Relative logical Block Addressing.
///
- UINT64 PartitionStart;
+ UINT64 PartitionStart;
///
/// Size of the partition in units of Blocks, also called Sectors.
///
- UINT64 PartitionSize;
+ UINT64 PartitionSize;
} CDROM_DEVICE_PATH;
//
// Use VENDOR_DEVICE_PATH struct
//
-#define MEDIA_VENDOR_DP 0x03 ///< Media vendor device path subtype.
+#define MEDIA_VENDOR_DP 0x03 ///< Media vendor device path subtype.
///
/// File Path Media Device Path SubType
///
-#define MEDIA_FILEPATH_DP 0x04
+#define MEDIA_FILEPATH_DP 0x04
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// A NULL-terminated Path string including directory and file names.
///
- CHAR16 PathName[1];
+ CHAR16 PathName[1];
} FILEPATH_DEVICE_PATH;
#define SIZE_OF_FILEPATH_DEVICE_PATH OFFSET_OF(FILEPATH_DEVICE_PATH,PathName)
@@ -1090,7 +1089,7 @@ typedef struct {
///
/// Media Protocol Device Path SubType.
///
-#define MEDIA_PROTOCOL_DP 0x05
+#define MEDIA_PROTOCOL_DP 0x05
///
/// The Media Protocol Device Path is used to denote the protocol that is being
@@ -1098,157 +1097,156 @@ typedef struct {
/// Many protocols are inherent to the style of device path.
///
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// The ID of the protocol.
///
- EFI_GUID Protocol;
+ EFI_GUID Protocol;
} MEDIA_PROTOCOL_DEVICE_PATH;
///
/// PIWG Firmware File SubType.
///
-#define MEDIA_PIWG_FW_FILE_DP 0x06
+#define MEDIA_PIWG_FW_FILE_DP 0x06
///
/// This device path is used by systems implementing the UEFI PI Specification 1.0 to describe a firmware file.
///
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Firmware file name
///
- EFI_GUID FvFileName;
+ EFI_GUID FvFileName;
} MEDIA_FW_VOL_FILEPATH_DEVICE_PATH;
///
/// PIWG Firmware Volume Device Path SubType.
///
-#define MEDIA_PIWG_FW_VOL_DP 0x07
+#define MEDIA_PIWG_FW_VOL_DP 0x07
///
/// This device path is used by systems implementing the UEFI PI Specification 1.0 to describe a firmware volume.
///
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Firmware volume name.
///
- EFI_GUID FvName;
+ EFI_GUID FvName;
} MEDIA_FW_VOL_DEVICE_PATH;
///
/// Media relative offset range device path.
///
-#define MEDIA_RELATIVE_OFFSET_RANGE_DP 0x08
+#define MEDIA_RELATIVE_OFFSET_RANGE_DP 0x08
///
/// Used to describe the offset range of media relative.
///
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
- UINT32 Reserved;
- UINT64 StartingOffset;
- UINT64 EndingOffset;
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ UINT32 Reserved;
+ UINT64 StartingOffset;
+ UINT64 EndingOffset;
} MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH;
///
/// This GUID defines a RAM Disk supporting a raw disk format in volatile memory.
///
-#define EFI_VIRTUAL_DISK_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE
+#define EFI_VIRTUAL_DISK_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE
-extern EFI_GUID gEfiVirtualDiskGuid;
+extern EFI_GUID gEfiVirtualDiskGuid;
///
/// This GUID defines a RAM Disk supporting an ISO image in volatile memory.
///
-#define EFI_VIRTUAL_CD_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE
+#define EFI_VIRTUAL_CD_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE
-extern EFI_GUID gEfiVirtualCdGuid;
+extern EFI_GUID gEfiVirtualCdGuid;
///
/// This GUID defines a RAM Disk supporting a raw disk format in persistent memory.
///
-#define EFI_PERSISTENT_VIRTUAL_DISK_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT
+#define EFI_PERSISTENT_VIRTUAL_DISK_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT
-extern EFI_GUID gEfiPersistentVirtualDiskGuid;
+extern EFI_GUID gEfiPersistentVirtualDiskGuid;
///
/// This GUID defines a RAM Disk supporting an ISO image in persistent memory.
///
-#define EFI_PERSISTENT_VIRTUAL_CD_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT
+#define EFI_PERSISTENT_VIRTUAL_CD_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT
-extern EFI_GUID gEfiPersistentVirtualCdGuid;
+extern EFI_GUID gEfiPersistentVirtualCdGuid;
///
/// Media ram disk device path.
///
-#define MEDIA_RAM_DISK_DP 0x09
+#define MEDIA_RAM_DISK_DP 0x09
///
/// Used to describe the ram disk device path.
///
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Starting Memory Address.
///
- UINT32 StartingAddr[2];
+ UINT32 StartingAddr[2];
///
/// Ending Memory Address.
///
- UINT32 EndingAddr[2];
+ UINT32 EndingAddr[2];
///
/// GUID that defines the type of the RAM Disk.
///
- EFI_GUID TypeGuid;
+ EFI_GUID TypeGuid;
///
/// RAM Diskinstance number, if supported. The default value is zero.
///
- UINT16 Instance;
+ UINT16 Instance;
} MEDIA_RAM_DISK_DEVICE_PATH;
///
/// BIOS Boot Specification Device Path.
///
-#define BBS_DEVICE_PATH 0x05
+#define BBS_DEVICE_PATH 0x05
///
/// BIOS Boot Specification Device Path SubType.
///
-#define BBS_BBS_DP 0x01
+#define BBS_BBS_DP 0x01
///
/// This Device Path is used to describe the booting of non-EFI-aware operating systems.
///
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_DEVICE_PATH_PROTOCOL Header;
///
/// Device Type as defined by the BIOS Boot Specification.
///
- UINT16 DeviceType;
+ UINT16 DeviceType;
///
/// Status Flags as defined by the BIOS Boot Specification.
///
- UINT16 StatusFlag;
+ UINT16 StatusFlag;
///
/// Null-terminated ASCII string that describes the boot device to a user.
///
- CHAR8 String[1];
+ CHAR8 String[1];
} BBS_BBS_DEVICE_PATH;
//
// DeviceType definitions - from BBS specification
//
-#define BBS_TYPE_FLOPPY 0x01
-#define BBS_TYPE_HARDDRIVE 0x02
-#define BBS_TYPE_CDROM 0x03
-#define BBS_TYPE_PCMCIA 0x04
-#define BBS_TYPE_USB 0x05
-#define BBS_TYPE_EMBEDDED_NETWORK 0x06
-#define BBS_TYPE_BEV 0x80
-#define BBS_TYPE_UNKNOWN 0xFF
-
+#define BBS_TYPE_FLOPPY 0x01
+#define BBS_TYPE_HARDDRIVE 0x02
+#define BBS_TYPE_CDROM 0x03
+#define BBS_TYPE_PCMCIA 0x04
+#define BBS_TYPE_USB 0x05
+#define BBS_TYPE_EMBEDDED_NETWORK 0x06
+#define BBS_TYPE_BEV 0x80
+#define BBS_TYPE_UNKNOWN 0xFF
///
/// Union of all possible Device Paths and pointers to Device Paths.
@@ -1309,8 +1307,6 @@ typedef union {
BBS_BBS_DEVICE_PATH Bbs;
} EFI_DEV_PATH;
-
-
typedef union {
EFI_DEVICE_PATH_PROTOCOL *DevPath;
PCI_DEVICE_PATH *Pci;
@@ -1370,10 +1366,10 @@ typedef union {
#pragma pack()
-#define END_DEVICE_PATH_TYPE 0x7f
-#define END_ENTIRE_DEVICE_PATH_SUBTYPE 0xFF
-#define END_INSTANCE_DEVICE_PATH_SUBTYPE 0x01
+#define END_DEVICE_PATH_TYPE 0x7f
+#define END_ENTIRE_DEVICE_PATH_SUBTYPE 0xFF
+#define END_INSTANCE_DEVICE_PATH_SUBTYPE 0x01
-extern EFI_GUID gEfiDevicePathProtocolGuid;
+extern EFI_GUID gEfiDevicePathProtocolGuid;
#endif
diff --git a/MdePkg/Include/Protocol/DiskInfo.h b/MdePkg/Include/Protocol/DiskInfo.h
index e0215d61..69f559da 100644
--- a/MdePkg/Include/Protocol/DiskInfo.h
+++ b/MdePkg/Include/Protocol/DiskInfo.h
@@ -25,7 +25,7 @@
///
/// Forward declaration for EFI_DISK_INFO_PROTOCOL
///
-typedef struct _EFI_DISK_INFO_PROTOCOL EFI_DISK_INFO_PROTOCOL;
+typedef struct _EFI_DISK_INFO_PROTOCOL EFI_DISK_INFO_PROTOCOL;
///
/// Global ID for an IDE interface. Used to fill in EFI_DISK_INFO_PROTOCOL.Interface
@@ -186,36 +186,36 @@ struct _EFI_DISK_INFO_PROTOCOL {
/// A GUID that defines the format of buffers for the other member functions
/// of this protocol.
///
- EFI_GUID Interface;
+ EFI_GUID Interface;
///
/// Return the results of the Inquiry command to a drive in InquiryData. Data
/// format of Inquiry data is defined by the Interface GUID.
///
- EFI_DISK_INFO_INQUIRY Inquiry;
+ EFI_DISK_INFO_INQUIRY Inquiry;
///
/// Return the results of the Identify command to a drive in IdentifyData. Data
/// format of Identify data is defined by the Interface GUID.
///
- EFI_DISK_INFO_IDENTIFY Identify;
+ EFI_DISK_INFO_IDENTIFY Identify;
///
/// Return the results of the Request Sense command to a drive in SenseData. Data
/// format of Sense data is defined by the Interface GUID.
///
- EFI_DISK_INFO_SENSE_DATA SenseData;
+ EFI_DISK_INFO_SENSE_DATA SenseData;
///
/// Specific controller.
///
- EFI_DISK_INFO_WHICH_IDE WhichIde;
+ EFI_DISK_INFO_WHICH_IDE WhichIde;
};
-extern EFI_GUID gEfiDiskInfoProtocolGuid;
+extern EFI_GUID gEfiDiskInfoProtocolGuid;
-extern EFI_GUID gEfiDiskInfoIdeInterfaceGuid;
-extern EFI_GUID gEfiDiskInfoScsiInterfaceGuid;
-extern EFI_GUID gEfiDiskInfoUsbInterfaceGuid;
-extern EFI_GUID gEfiDiskInfoAhciInterfaceGuid;
-extern EFI_GUID gEfiDiskInfoNvmeInterfaceGuid;
-extern EFI_GUID gEfiDiskInfoUfsInterfaceGuid;
-extern EFI_GUID gEfiDiskInfoSdMmcInterfaceGuid;
+extern EFI_GUID gEfiDiskInfoIdeInterfaceGuid;
+extern EFI_GUID gEfiDiskInfoScsiInterfaceGuid;
+extern EFI_GUID gEfiDiskInfoUsbInterfaceGuid;
+extern EFI_GUID gEfiDiskInfoAhciInterfaceGuid;
+extern EFI_GUID gEfiDiskInfoNvmeInterfaceGuid;
+extern EFI_GUID gEfiDiskInfoUfsInterfaceGuid;
+extern EFI_GUID gEfiDiskInfoSdMmcInterfaceGuid;
#endif
diff --git a/MdePkg/Include/Protocol/GraphicsOutput.h b/MdePkg/Include/Protocol/GraphicsOutput.h
index 9ba38c57..edd5495e 100644
--- a/MdePkg/Include/Protocol/GraphicsOutput.h
+++ b/MdePkg/Include/Protocol/GraphicsOutput.h
@@ -19,10 +19,10 @@
typedef struct _EFI_GRAPHICS_OUTPUT_PROTOCOL EFI_GRAPHICS_OUTPUT_PROTOCOL;
typedef struct {
- UINT32 RedMask;
- UINT32 GreenMask;
- UINT32 BlueMask;
- UINT32 ReservedMask;
+ UINT32 RedMask;
+ UINT32 GreenMask;
+ UINT32 BlueMask;
+ UINT32 ReservedMask;
} EFI_PIXEL_BITMASK;
typedef enum {
@@ -61,29 +61,29 @@ typedef struct {
/// The version of this data structure. A value of zero represents the
/// EFI_GRAPHICS_OUTPUT_MODE_INFORMATION structure as defined in this specification.
///
- UINT32 Version;
+ UINT32 Version;
///
/// The size of video screen in pixels in the X dimension.
///
- UINT32 HorizontalResolution;
+ UINT32 HorizontalResolution;
///
/// The size of video screen in pixels in the Y dimension.
///
- UINT32 VerticalResolution;
+ UINT32 VerticalResolution;
///
/// Enumeration that defines the physical format of the pixel. A value of PixelBltOnly
/// implies that a linear frame buffer is not available for this mode.
///
- EFI_GRAPHICS_PIXEL_FORMAT PixelFormat;
+ EFI_GRAPHICS_PIXEL_FORMAT PixelFormat;
///
/// This bit-mask is only valid if PixelFormat is set to PixelPixelBitMask.
/// A bit being set defines what bits are used for what purpose such as Red, Green, Blue, or Reserved.
///
- EFI_PIXEL_BITMASK PixelInformation;
+ EFI_PIXEL_BITMASK PixelInformation;
///
/// Defines the number of pixel elements per video memory line.
///
- UINT32 PixelsPerScanLine;
+ UINT32 PixelsPerScanLine;
} EFI_GRAPHICS_OUTPUT_MODE_INFORMATION;
/**
@@ -129,15 +129,15 @@ EFI_STATUS
);
typedef struct {
- UINT8 Blue;
- UINT8 Green;
- UINT8 Red;
- UINT8 Reserved;
+ UINT8 Blue;
+ UINT8 Green;
+ UINT8 Red;
+ UINT8 Reserved;
} EFI_GRAPHICS_OUTPUT_BLT_PIXEL;
typedef union {
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL Pixel;
- UINT32 Raw;
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL Pixel;
+ UINT32 Raw;
} EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION;
///
@@ -210,7 +210,7 @@ typedef
EFI_STATUS
(EFIAPI *EFI_GRAPHICS_OUTPUT_PROTOCOL_BLT)(
IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer OPTIONAL,
IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION BltOperation,
IN UINTN SourceX,
IN UINTN SourceY,
@@ -225,29 +225,29 @@ typedef struct {
///
/// The number of modes supported by QueryMode() and SetMode().
///
- UINT32 MaxMode;
+ UINT32 MaxMode;
///
/// Current Mode of the graphics device. Valid mode numbers are 0 to MaxMode -1.
///
- UINT32 Mode;
+ UINT32 Mode;
///
/// Pointer to read-only EFI_GRAPHICS_OUTPUT_MODE_INFORMATION data.
///
- EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info;
+ EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info;
///
/// Size of Info structure in bytes.
///
- UINTN SizeOfInfo;
+ UINTN SizeOfInfo;
///
/// Base address of graphics linear frame buffer.
/// Offset zero in FrameBufferBase represents the upper left pixel of the display.
///
- EFI_PHYSICAL_ADDRESS FrameBufferBase;
+ EFI_PHYSICAL_ADDRESS FrameBufferBase;
///
/// Amount of frame buffer needed to support the active mode as defined by
/// PixelsPerScanLine xVerticalResolution x PixelElementSize.
///
- UINTN FrameBufferSize;
+ UINTN FrameBufferSize;
} EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE;
///
@@ -256,15 +256,15 @@ typedef struct {
/// frame buffer is also exposed so software can write directly to the video hardware.
///
struct _EFI_GRAPHICS_OUTPUT_PROTOCOL {
- EFI_GRAPHICS_OUTPUT_PROTOCOL_QUERY_MODE QueryMode;
- EFI_GRAPHICS_OUTPUT_PROTOCOL_SET_MODE SetMode;
- EFI_GRAPHICS_OUTPUT_PROTOCOL_BLT Blt;
+ EFI_GRAPHICS_OUTPUT_PROTOCOL_QUERY_MODE QueryMode;
+ EFI_GRAPHICS_OUTPUT_PROTOCOL_SET_MODE SetMode;
+ EFI_GRAPHICS_OUTPUT_PROTOCOL_BLT Blt;
///
/// Pointer to EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE data.
///
- EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE *Mode;
+ EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE *Mode;
};
-extern EFI_GUID gEfiGraphicsOutputProtocolGuid;
+extern EFI_GUID gEfiGraphicsOutputProtocolGuid;
#endif
diff --git a/MdePkg/Include/Protocol/NvmExpressPassthru.h b/MdePkg/Include/Protocol/NvmExpressPassthru.h
index bd3b4bc5..6b9b3cbf 100644
--- a/MdePkg/Include/Protocol/NvmExpressPassthru.h
+++ b/MdePkg/Include/Protocol/NvmExpressPassthru.h
@@ -13,9 +13,7 @@
#ifndef _UEFI_NVM_EXPRESS_PASS_THRU_H_
#define _UEFI_NVM_EXPRESS_PASS_THRU_H_
-
#include
-
#define EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL_GUID \
{ \
0x52c78312, 0x8edc, 0x4233, { 0x98, 0xf2, 0x1a, 0x1a, 0xa5, 0xe3, 0x88, 0xa5 } \
@@ -24,98 +22,99 @@
typedef struct _EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL;
typedef struct {
- UINT32 Attributes;
- UINT32 IoAlign;
- UINT32 NvmeVersion;
+ UINT32 Attributes;
+ UINT32 IoAlign;
+ UINT32 NvmeVersion;
} EFI_NVM_EXPRESS_PASS_THRU_MODE;
//
// If this bit is set, then the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL interface is
// for directly addressable namespaces.
//
-#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL 0x0001
+#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL 0x0001
//
// If this bit is set, then the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL interface is
// for a single volume logical namespace comprised of multiple namespaces.
//
-#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL 0x0002
+#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL 0x0002
//
// If this bit is set, then the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL interface
// supports non-blocking I/O.
//
-#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_NONBLOCKIO 0x0004
+#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_NONBLOCKIO 0x0004
//
// If this bit is set, then the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL interface
// supports NVM command set.
//
-#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_CMD_SET_NVM 0x0008
+#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_CMD_SET_NVM 0x0008
//
// FusedOperation
//
-#define NORMAL_CMD 0x00
-#define FUSED_FIRST_CMD 0x01
-#define FUSED_SECOND_CMD 0x02
+#define NORMAL_CMD 0x00
+#define FUSED_FIRST_CMD 0x01
+#define FUSED_SECOND_CMD 0x02
typedef struct {
- UINT32 Opcode:8;
- UINT32 FusedOperation:2;
- UINT32 Reserved:22;
+ UINT32 Opcode : 8;
+ UINT32 FusedOperation : 2;
+ UINT32 Reserved : 22;
} NVME_CDW0;
//
// Flags
//
-#define CDW2_VALID 0x01
-#define CDW3_VALID 0x02
-#define CDW10_VALID 0x04
-#define CDW11_VALID 0x08
-#define CDW12_VALID 0x10
-#define CDW13_VALID 0x20
-#define CDW14_VALID 0x40
-#define CDW15_VALID 0x80
+#define CDW2_VALID 0x01
+#define CDW3_VALID 0x02
+#define CDW10_VALID 0x04
+#define CDW11_VALID 0x08
+#define CDW12_VALID 0x10
+#define CDW13_VALID 0x20
+#define CDW14_VALID 0x40
+#define CDW15_VALID 0x80
//
// Queue Type
//
-#define NVME_ADMIN_QUEUE 0x00
-#define NVME_IO_QUEUE 0x01
+#define NVME_ADMIN_QUEUE 0x00
+#define NVME_IO_QUEUE 0x01
typedef struct {
- NVME_CDW0 Cdw0;
- UINT8 Flags;
- UINT32 Nsid;
- UINT32 Cdw2;
- UINT32 Cdw3;
- UINT32 Cdw10;
- UINT32 Cdw11;
- UINT32 Cdw12;
- UINT32 Cdw13;
- UINT32 Cdw14;
- UINT32 Cdw15;
+ NVME_CDW0 Cdw0;
+ UINT8 Flags;
+ UINT32 Nsid;
+ UINT32 Cdw2;
+ UINT32 Cdw3;
+ UINT32 Cdw10;
+ UINT32 Cdw11;
+ UINT32 Cdw12;
+ UINT32 Cdw13;
+ UINT32 Cdw14;
+ UINT32 Cdw15;
} EFI_NVM_EXPRESS_COMMAND;
typedef struct {
- UINT32 DW0;
- UINT32 DW1;
- UINT32 DW2;
- UINT32 DW3;
+ UINT32 DW0;
+ UINT32 DW1;
+ UINT32 DW2;
+ UINT32 DW3;
} EFI_NVM_EXPRESS_COMPLETION;
typedef struct {
- UINT64 CommandTimeout;
- VOID *TransferBuffer;
- UINT32 TransferLength;
- VOID *MetadataBuffer;
- UINT32 MetadataLength;
- UINT8 QueueType;
- EFI_NVM_EXPRESS_COMMAND *NvmeCmd;
- EFI_NVM_EXPRESS_COMPLETION *NvmeCompletion;
+ UINT64 CommandTimeout;
+ VOID *TransferBuffer;
+ UINT32 TransferLength;
+ VOID *MetadataBuffer;
+ UINT32 MetadataLength;
+ UINT8 QueueType;
+ EFI_NVM_EXPRESS_COMMAND *NvmeCmd;
+ EFI_NVM_EXPRESS_COMPLETION *NvmeCompletion;
} EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET;
//
// Protocol function prototypes
//
+
/**
Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports
both blocking I/O and non-blocking I/O. The blocking I/O functionality is required, and the non-blocking
@@ -265,21 +264,20 @@ EFI_STATUS
(EFIAPI *EFI_NVM_EXPRESS_PASS_THRU_GET_NAMESPACE)(
IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
- OUT UINT32 *NamespaceId
+ OUT UINT32 *NamespaceId
);
//
// Protocol Interface Structure
//
struct _EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL {
- EFI_NVM_EXPRESS_PASS_THRU_MODE *Mode;
- EFI_NVM_EXPRESS_PASS_THRU_PASSTHRU PassThru;
- EFI_NVM_EXPRESS_PASS_THRU_GET_NEXT_NAMESPACE GetNextNamespace;
- EFI_NVM_EXPRESS_PASS_THRU_BUILD_DEVICE_PATH BuildDevicePath;
- EFI_NVM_EXPRESS_PASS_THRU_GET_NAMESPACE GetNamespace;
+ EFI_NVM_EXPRESS_PASS_THRU_MODE *Mode;
+ EFI_NVM_EXPRESS_PASS_THRU_PASSTHRU PassThru;
+ EFI_NVM_EXPRESS_PASS_THRU_GET_NEXT_NAMESPACE GetNextNamespace;
+ EFI_NVM_EXPRESS_PASS_THRU_BUILD_DEVICE_PATH BuildDevicePath;
+ EFI_NVM_EXPRESS_PASS_THRU_GET_NAMESPACE GetNamespace;
};
-extern EFI_GUID gEfiNvmExpressPassThruProtocolGuid;
+extern EFI_GUID gEfiNvmExpressPassThruProtocolGuid;
#endif
-
diff --git a/MdePkg/Include/Protocol/SerialIo.h b/MdePkg/Include/Protocol/SerialIo.h
index 3a726537..ccaf602d 100644
--- a/MdePkg/Include/Protocol/SerialIo.h
+++ b/MdePkg/Include/Protocol/SerialIo.h
@@ -29,11 +29,10 @@
typedef struct _EFI_SERIAL_IO_PROTOCOL EFI_SERIAL_IO_PROTOCOL;
-
///
/// Backward-compatible with EFI1.1.
///
-typedef EFI_SERIAL_IO_PROTOCOL SERIAL_IO_INTERFACE;
+typedef EFI_SERIAL_IO_PROTOCOL SERIAL_IO_INTERFACE;
///
/// Parity type that is computed or checked as each character is transmitted or received. If the
@@ -80,13 +79,14 @@ typedef enum {
//
// Read Write
//
-#define EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE 0x00001000
-#define EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE 0x00002000
-#define EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE 0x00004000
+#define EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE 0x00001000
+#define EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE 0x00002000
+#define EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE 0x00004000
//
// Serial IO Member Functions
//
+
/**
Reset the serial device.
@@ -254,22 +254,22 @@ EFI_STATUS
**/
typedef struct {
- UINT32 ControlMask;
+ UINT32 ControlMask;
//
// current Attributes
//
- UINT32 Timeout;
- UINT64 BaudRate;
- UINT32 ReceiveFifoDepth;
- UINT32 DataBits;
- UINT32 Parity;
- UINT32 StopBits;
+ UINT32 Timeout;
+ UINT64 BaudRate;
+ UINT32 ReceiveFifoDepth;
+ UINT32 DataBits;
+ UINT32 Parity;
+ UINT32 StopBits;
} EFI_SERIAL_IO_MODE;
-#define EFI_SERIAL_IO_PROTOCOL_REVISION 0x00010000
-#define EFI_SERIAL_IO_PROTOCOL_REVISION1p1 0x00010001
-#define SERIAL_IO_INTERFACE_REVISION EFI_SERIAL_IO_PROTOCOL_REVISION
+#define EFI_SERIAL_IO_PROTOCOL_REVISION 0x00010000
+#define EFI_SERIAL_IO_PROTOCOL_REVISION1p1 0x00010001
+#define SERIAL_IO_INTERFACE_REVISION EFI_SERIAL_IO_PROTOCOL_REVISION
///
/// The Serial I/O protocol is used to communicate with UART-style serial devices.
@@ -282,17 +282,17 @@ struct _EFI_SERIAL_IO_PROTOCOL {
/// must be backwards compatible. If a future version is not backwards compatible,
/// it is not the same GUID.
///
- UINT32 Revision;
- EFI_SERIAL_RESET Reset;
- EFI_SERIAL_SET_ATTRIBUTES SetAttributes;
- EFI_SERIAL_SET_CONTROL_BITS SetControl;
- EFI_SERIAL_GET_CONTROL_BITS GetControl;
- EFI_SERIAL_WRITE Write;
- EFI_SERIAL_READ Read;
+ UINT32 Revision;
+ EFI_SERIAL_RESET Reset;
+ EFI_SERIAL_SET_ATTRIBUTES SetAttributes;
+ EFI_SERIAL_SET_CONTROL_BITS SetControl;
+ EFI_SERIAL_GET_CONTROL_BITS GetControl;
+ EFI_SERIAL_WRITE Write;
+ EFI_SERIAL_READ Read;
///
/// Pointer to SERIAL_IO_MODE data.
///
- EFI_SERIAL_IO_MODE *Mode;
+ EFI_SERIAL_IO_MODE *Mode;
///
/// Pointer to a GUID identifying the device connected to the serial port.
/// This field is NULL when the protocol is installed by the serial port
@@ -300,10 +300,10 @@ struct _EFI_SERIAL_IO_PROTOCOL {
/// with a known device attached. The field will remain NULL if there is
/// no platform serial device identification information available.
///
- CONST EFI_GUID *DeviceTypeGuid; // Revision 1.1
+ CONST EFI_GUID *DeviceTypeGuid; // Revision 1.1
};
-extern EFI_GUID gEfiSerialIoProtocolGuid;
-extern EFI_GUID gEfiSerialTerminalDeviceTypeGuid;
+extern EFI_GUID gEfiSerialIoProtocolGuid;
+extern EFI_GUID gEfiSerialTerminalDeviceTypeGuid;
#endif
diff --git a/MdePkg/Include/Protocol/StorageSecurityCommand.h b/MdePkg/Include/Protocol/StorageSecurityCommand.h
index db38fb49..894d5f0b 100644
--- a/MdePkg/Include/Protocol/StorageSecurityCommand.h
+++ b/MdePkg/Include/Protocol/StorageSecurityCommand.h
@@ -18,7 +18,7 @@
0xC88B0B6D, 0x0DFC, 0x49A7, {0x9C, 0xB4, 0x49, 0x07, 0x4B, 0x4C, 0x3A, 0x78 } \
}
-typedef struct _EFI_STORAGE_SECURITY_COMMAND_PROTOCOL EFI_STORAGE_SECURITY_COMMAND_PROTOCOL;
+typedef struct _EFI_STORAGE_SECURITY_COMMAND_PROTOCOL EFI_STORAGE_SECURITY_COMMAND_PROTOCOL;
/**
Send a security protocol command to a device that receives data and/or the result
@@ -166,7 +166,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
-(EFIAPI *EFI_STORAGE_SECURITY_SEND_DATA) (
+(EFIAPI *EFI_STORAGE_SECURITY_SEND_DATA)(
IN EFI_STORAGE_SECURITY_COMMAND_PROTOCOL *This,
IN UINT32 MediaId,
IN UINT64 Timeout,
@@ -174,7 +174,7 @@ EFI_STATUS
IN UINT16 SecurityProtocolSpecificData,
IN UINTN PayloadBufferSize,
IN VOID *PayloadBuffer
-);
+ );
///
/// The EFI_STORAGE_SECURITY_COMMAND_PROTOCOL is used to send security protocol
@@ -197,10 +197,10 @@ EFI_STATUS
/// or their successors.
///
struct _EFI_STORAGE_SECURITY_COMMAND_PROTOCOL {
- EFI_STORAGE_SECURITY_RECEIVE_DATA ReceiveData;
- EFI_STORAGE_SECURITY_SEND_DATA SendData;
+ EFI_STORAGE_SECURITY_RECEIVE_DATA ReceiveData;
+ EFI_STORAGE_SECURITY_SEND_DATA SendData;
};
-extern EFI_GUID gEfiStorageSecurityCommandProtocolGuid;
+extern EFI_GUID gEfiStorageSecurityCommandProtocolGuid;
#endif
diff --git a/MdePkg/Include/Protocol/Usb2HostController.h b/MdePkg/Include/Protocol/Usb2HostController.h
index 01538095..b5dc003e 100644
--- a/MdePkg/Include/Protocol/Usb2HostController.h
+++ b/MdePkg/Include/Protocol/Usb2HostController.h
@@ -24,35 +24,33 @@
///
typedef struct _EFI_USB2_HC_PROTOCOL EFI_USB2_HC_PROTOCOL;
-
typedef struct {
- UINT16 PortStatus; ///< Contains current port status bitmap.
- UINT16 PortChangeStatus; ///< Contains current port status change bitmap.
+ UINT16 PortStatus; ///< Contains current port status bitmap.
+ UINT16 PortChangeStatus; ///< Contains current port status change bitmap.
} EFI_USB_PORT_STATUS;
///
/// EFI_USB_PORT_STATUS.PortStatus bit definition
///
-#define USB_PORT_STAT_CONNECTION 0x0001
-#define USB_PORT_STAT_ENABLE 0x0002
-#define USB_PORT_STAT_SUSPEND 0x0004
-#define USB_PORT_STAT_OVERCURRENT 0x0008
-#define USB_PORT_STAT_RESET 0x0010
-#define USB_PORT_STAT_POWER 0x0100
-#define USB_PORT_STAT_LOW_SPEED 0x0200
-#define USB_PORT_STAT_HIGH_SPEED 0x0400
-#define USB_PORT_STAT_SUPER_SPEED 0x0800
-#define USB_PORT_STAT_OWNER 0x2000
+#define USB_PORT_STAT_CONNECTION 0x0001
+#define USB_PORT_STAT_ENABLE 0x0002
+#define USB_PORT_STAT_SUSPEND 0x0004
+#define USB_PORT_STAT_OVERCURRENT 0x0008
+#define USB_PORT_STAT_RESET 0x0010
+#define USB_PORT_STAT_POWER 0x0100
+#define USB_PORT_STAT_LOW_SPEED 0x0200
+#define USB_PORT_STAT_HIGH_SPEED 0x0400
+#define USB_PORT_STAT_SUPER_SPEED 0x0800
+#define USB_PORT_STAT_OWNER 0x2000
///
/// EFI_USB_PORT_STATUS.PortChangeStatus bit definition
///
-#define USB_PORT_STAT_C_CONNECTION 0x0001
-#define USB_PORT_STAT_C_ENABLE 0x0002
-#define USB_PORT_STAT_C_SUSPEND 0x0004
-#define USB_PORT_STAT_C_OVERCURRENT 0x0008
-#define USB_PORT_STAT_C_RESET 0x0010
-
+#define USB_PORT_STAT_C_CONNECTION 0x0001
+#define USB_PORT_STAT_C_ENABLE 0x0002
+#define USB_PORT_STAT_C_SUSPEND 0x0004
+#define USB_PORT_STAT_C_OVERCURRENT 0x0008
+#define USB_PORT_STAT_C_RESET 0x0010
///
/// Usb port features value
@@ -72,14 +70,14 @@ typedef enum {
EfiUsbPortResetChange = 20
} EFI_USB_PORT_FEATURE;
-#define EFI_USB_SPEED_FULL 0x0000 ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.
-#define EFI_USB_SPEED_LOW 0x0001 ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.
-#define EFI_USB_SPEED_HIGH 0x0002 ///< 480 Mb/s, USB 2.0 EHCI HC.
-#define EFI_USB_SPEED_SUPER 0x0003 ///< 4.8 Gb/s, USB 3.0 XHCI HC.
+#define EFI_USB_SPEED_FULL 0x0000 ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.
+#define EFI_USB_SPEED_LOW 0x0001 ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.
+#define EFI_USB_SPEED_HIGH 0x0002 ///< 480 Mb/s, USB 2.0 EHCI HC.
+#define EFI_USB_SPEED_SUPER 0x0003 ///< 4.8 Gb/s, USB 3.0 XHCI HC.
typedef struct {
- UINT8 TranslatorHubAddress; ///< device address
- UINT8 TranslatorPortNumber; ///< the port number of the hub that device is connected to.
+ UINT8 TranslatorHubAddress; ///< device address
+ UINT8 TranslatorPortNumber; ///< the port number of the hub that device is connected to.
} EFI_USB2_HC_TRANSACTION_TRANSLATOR;
//
@@ -114,6 +112,7 @@ EFI_STATUS
#define EFI_USB_HC_RESET_HOST_CONTROLLER 0x0002
#define EFI_USB_HC_RESET_GLOBAL_WITH_DEBUG 0x0004
#define EFI_USB_HC_RESET_HOST_WITH_DEBUG 0x0008
+
/**
Provides software reset for the USB host controller.
@@ -192,7 +191,7 @@ EFI_STATUS
(EFIAPI *EFI_USB2_HC_PROTOCOL_GET_STATE)(
IN EFI_USB2_HC_PROTOCOL *This,
OUT EFI_USB_HC_STATE *State
-);
+ );
/**
Sets the USB host controller to a specific state.
@@ -258,7 +257,7 @@ EFI_STATUS
OUT UINT32 *TransferResult
);
-#define EFI_USB_MAX_BULK_BUFFER_NUM 10
+#define EFI_USB_MAX_BULK_BUFFER_NUM 10
/**
Submits bulk transfer to a bulk endpoint of a USB device.
@@ -401,8 +400,8 @@ EFI_STATUS
OUT UINT32 *TransferResult
);
-#define EFI_USB_MAX_ISO_BUFFER_NUM 7
-#define EFI_USB_MAX_ISO_BUFFER_NUM1 2
+#define EFI_USB_MAX_ISO_BUFFER_NUM 7
+#define EFI_USB_MAX_ISO_BUFFER_NUM1 2
/**
Submits isochronous transfer to an isochronous endpoint of a USB device.
@@ -624,35 +623,35 @@ EFI_STATUS
/// instance, and an EFI_USB2_HC_PROTOCOL instance.
///
struct _EFI_USB2_HC_PROTOCOL {
- EFI_USB2_HC_PROTOCOL_GET_CAPABILITY GetCapability;
- EFI_USB2_HC_PROTOCOL_RESET Reset;
- EFI_USB2_HC_PROTOCOL_GET_STATE GetState;
- EFI_USB2_HC_PROTOCOL_SET_STATE SetState;
- EFI_USB2_HC_PROTOCOL_CONTROL_TRANSFER ControlTransfer;
- EFI_USB2_HC_PROTOCOL_BULK_TRANSFER BulkTransfer;
- EFI_USB2_HC_PROTOCOL_ASYNC_INTERRUPT_TRANSFER AsyncInterruptTransfer;
- EFI_USB2_HC_PROTOCOL_SYNC_INTERRUPT_TRANSFER SyncInterruptTransfer;
- EFI_USB2_HC_PROTOCOL_ISOCHRONOUS_TRANSFER IsochronousTransfer;
- EFI_USB2_HC_PROTOCOL_ASYNC_ISOCHRONOUS_TRANSFER AsyncIsochronousTransfer;
- EFI_USB2_HC_PROTOCOL_GET_ROOTHUB_PORT_STATUS GetRootHubPortStatus;
- EFI_USB2_HC_PROTOCOL_SET_ROOTHUB_PORT_FEATURE SetRootHubPortFeature;
- EFI_USB2_HC_PROTOCOL_CLEAR_ROOTHUB_PORT_FEATURE ClearRootHubPortFeature;
+ EFI_USB2_HC_PROTOCOL_GET_CAPABILITY GetCapability;
+ EFI_USB2_HC_PROTOCOL_RESET Reset;
+ EFI_USB2_HC_PROTOCOL_GET_STATE GetState;
+ EFI_USB2_HC_PROTOCOL_SET_STATE SetState;
+ EFI_USB2_HC_PROTOCOL_CONTROL_TRANSFER ControlTransfer;
+ EFI_USB2_HC_PROTOCOL_BULK_TRANSFER BulkTransfer;
+ EFI_USB2_HC_PROTOCOL_ASYNC_INTERRUPT_TRANSFER AsyncInterruptTransfer;
+ EFI_USB2_HC_PROTOCOL_SYNC_INTERRUPT_TRANSFER SyncInterruptTransfer;
+ EFI_USB2_HC_PROTOCOL_ISOCHRONOUS_TRANSFER IsochronousTransfer;
+ EFI_USB2_HC_PROTOCOL_ASYNC_ISOCHRONOUS_TRANSFER AsyncIsochronousTransfer;
+ EFI_USB2_HC_PROTOCOL_GET_ROOTHUB_PORT_STATUS GetRootHubPortStatus;
+ EFI_USB2_HC_PROTOCOL_SET_ROOTHUB_PORT_FEATURE SetRootHubPortFeature;
+ EFI_USB2_HC_PROTOCOL_CLEAR_ROOTHUB_PORT_FEATURE ClearRootHubPortFeature;
///
/// The major revision number of the USB host controller. The revision information
/// indicates the release of the Universal Serial Bus Specification with which the
/// host controller is compliant.
///
- UINT16 MajorRevision;
+ UINT16 MajorRevision;
///
/// The minor revision number of the USB host controller. The revision information
/// indicates the release of the Universal Serial Bus Specification with which the
/// host controller is compliant.
///
- UINT16 MinorRevision;
+ UINT16 MinorRevision;
};
-extern EFI_GUID gEfiUsb2HcProtocolGuid;
+extern EFI_GUID gEfiUsb2HcProtocolGuid;
#endif
diff --git a/MdePkg/Include/Protocol/UsbIo.h b/MdePkg/Include/Protocol/UsbIo.h
index dec24652..489db023 100644
--- a/MdePkg/Include/Protocol/UsbIo.h
+++ b/MdePkg/Include/Protocol/UsbIo.h
@@ -23,7 +23,7 @@
0x2B2F68D6, 0x0CD2, 0x44cf, {0x8E, 0x8B, 0xBB, 0xA2, 0x0B, 0x1B, 0x5B, 0x75 } \
}
-typedef struct _EFI_USB_IO_PROTOCOL EFI_USB_IO_PROTOCOL;
+typedef struct _EFI_USB_IO_PROTOCOL EFI_USB_IO_PROTOCOL;
//
// Related Definition for EFI USB I/O protocol
@@ -32,11 +32,11 @@ typedef struct _EFI_USB_IO_PROTOCOL EFI_USB_IO_PROTOCOL;
//
// USB standard descriptors and reqeust
//
-typedef USB_DEVICE_REQUEST EFI_USB_DEVICE_REQUEST;
-typedef USB_DEVICE_DESCRIPTOR EFI_USB_DEVICE_DESCRIPTOR;
-typedef USB_CONFIG_DESCRIPTOR EFI_USB_CONFIG_DESCRIPTOR;
-typedef USB_INTERFACE_DESCRIPTOR EFI_USB_INTERFACE_DESCRIPTOR;
-typedef USB_ENDPOINT_DESCRIPTOR EFI_USB_ENDPOINT_DESCRIPTOR;
+typedef USB_DEVICE_REQUEST EFI_USB_DEVICE_REQUEST;
+typedef USB_DEVICE_DESCRIPTOR EFI_USB_DEVICE_DESCRIPTOR;
+typedef USB_CONFIG_DESCRIPTOR EFI_USB_CONFIG_DESCRIPTOR;
+typedef USB_INTERFACE_DESCRIPTOR EFI_USB_INTERFACE_DESCRIPTOR;
+typedef USB_ENDPOINT_DESCRIPTOR EFI_USB_ENDPOINT_DESCRIPTOR;
///
/// USB data transfer direction
@@ -50,16 +50,16 @@ typedef enum {
//
// USB Transfer Results
//
-#define EFI_USB_NOERROR 0x00
-#define EFI_USB_ERR_NOTEXECUTE 0x01
-#define EFI_USB_ERR_STALL 0x02
-#define EFI_USB_ERR_BUFFER 0x04
-#define EFI_USB_ERR_BABBLE 0x08
-#define EFI_USB_ERR_NAK 0x10
-#define EFI_USB_ERR_CRC 0x20
-#define EFI_USB_ERR_TIMEOUT 0x40
-#define EFI_USB_ERR_BITSTUFF 0x80
-#define EFI_USB_ERR_SYSTEM 0x100
+#define EFI_USB_NOERROR 0x00
+#define EFI_USB_ERR_NOTEXECUTE 0x01
+#define EFI_USB_ERR_STALL 0x02
+#define EFI_USB_ERR_BUFFER 0x04
+#define EFI_USB_ERR_BABBLE 0x08
+#define EFI_USB_ERR_NAK 0x10
+#define EFI_USB_ERR_CRC 0x20
+#define EFI_USB_ERR_TIMEOUT 0x40
+#define EFI_USB_ERR_BITSTUFF 0x80
+#define EFI_USB_ERR_SYSTEM 0x100
/**
Async USB transfer callback routine.
@@ -88,7 +88,6 @@ EFI_STATUS
// Prototype for EFI USB I/O protocol
//
-
/**
This function is used to manage a USB device with a control transfer pipe. A control transfer is
typically used to perform device initialization and configuration.
@@ -106,7 +105,7 @@ EFI_STATUS
@retval EFI_SUCCESS The control transfer has been successfully executed.
@retval EFI_DEVICE_ERROR The transfer failed. The transfer status is returned in Status.
- @retval EFI_INVALID_PARAMETE One or more parameters are invalid.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_TIMEOUT The control transfer fails due to timeout.
@@ -149,7 +148,7 @@ EFI_STATUS
@retval EFI_SUCCESS The bulk transfer has been successfully executed.
@retval EFI_DEVICE_ERROR The transfer failed. The transfer status is returned in Status.
- @retval EFI_INVALID_PARAMETE One or more parameters are invalid.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
@retval EFI_OUT_OF_RESOURCES The request could not be submitted due to a lack of resources.
@retval EFI_TIMEOUT The control transfer fails due to timeout.
@@ -478,29 +477,29 @@ struct _EFI_USB_IO_PROTOCOL {
//
// IO transfer
//
- EFI_USB_IO_CONTROL_TRANSFER UsbControlTransfer;
- EFI_USB_IO_BULK_TRANSFER UsbBulkTransfer;
- EFI_USB_IO_ASYNC_INTERRUPT_TRANSFER UsbAsyncInterruptTransfer;
- EFI_USB_IO_SYNC_INTERRUPT_TRANSFER UsbSyncInterruptTransfer;
- EFI_USB_IO_ISOCHRONOUS_TRANSFER UsbIsochronousTransfer;
- EFI_USB_IO_ASYNC_ISOCHRONOUS_TRANSFER UsbAsyncIsochronousTransfer;
+ EFI_USB_IO_CONTROL_TRANSFER UsbControlTransfer;
+ EFI_USB_IO_BULK_TRANSFER UsbBulkTransfer;
+ EFI_USB_IO_ASYNC_INTERRUPT_TRANSFER UsbAsyncInterruptTransfer;
+ EFI_USB_IO_SYNC_INTERRUPT_TRANSFER UsbSyncInterruptTransfer;
+ EFI_USB_IO_ISOCHRONOUS_TRANSFER UsbIsochronousTransfer;
+ EFI_USB_IO_ASYNC_ISOCHRONOUS_TRANSFER UsbAsyncIsochronousTransfer;
//
// Common device request
//
- EFI_USB_IO_GET_DEVICE_DESCRIPTOR UsbGetDeviceDescriptor;
- EFI_USB_IO_GET_CONFIG_DESCRIPTOR UsbGetConfigDescriptor;
- EFI_USB_IO_GET_INTERFACE_DESCRIPTOR UsbGetInterfaceDescriptor;
- EFI_USB_IO_GET_ENDPOINT_DESCRIPTOR UsbGetEndpointDescriptor;
- EFI_USB_IO_GET_STRING_DESCRIPTOR UsbGetStringDescriptor;
- EFI_USB_IO_GET_SUPPORTED_LANGUAGE UsbGetSupportedLanguages;
+ EFI_USB_IO_GET_DEVICE_DESCRIPTOR UsbGetDeviceDescriptor;
+ EFI_USB_IO_GET_CONFIG_DESCRIPTOR UsbGetConfigDescriptor;
+ EFI_USB_IO_GET_INTERFACE_DESCRIPTOR UsbGetInterfaceDescriptor;
+ EFI_USB_IO_GET_ENDPOINT_DESCRIPTOR UsbGetEndpointDescriptor;
+ EFI_USB_IO_GET_STRING_DESCRIPTOR UsbGetStringDescriptor;
+ EFI_USB_IO_GET_SUPPORTED_LANGUAGE UsbGetSupportedLanguages;
//
// Reset controller's parent port
//
- EFI_USB_IO_PORT_RESET UsbPortReset;
+ EFI_USB_IO_PORT_RESET UsbPortReset;
};
-extern EFI_GUID gEfiUsbIoProtocolGuid;
+extern EFI_GUID gEfiUsbIoProtocolGuid;
#endif
diff --git a/BootloaderCommonPkg/Include/Register/Intel/ArchitecturalMsr.h b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
similarity index 80%
rename from BootloaderCommonPkg/Include/Register/Intel/ArchitecturalMsr.h
rename to MdePkg/Include/Register/Intel/ArchitecturalMsr.h
index 22b9ec36..26bc6ba3 100644
--- a/BootloaderCommonPkg/Include/Register/Intel/ArchitecturalMsr.h
+++ b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@@ -34,8 +34,7 @@
@endcode
@note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.
**/
-#define MSR_IA32_P5_MC_ADDR 0x00000000
-
+#define MSR_IA32_P5_MC_ADDR 0x00000000
/**
See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.
@@ -53,8 +52,7 @@
@endcode
@note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.
**/
-#define MSR_IA32_P5_MC_TYPE 0x00000001
-
+#define MSR_IA32_P5_MC_TYPE 0x00000001
/**
See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced
@@ -73,8 +71,7 @@
@endcode
@note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.
**/
-#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006
-
+#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006
/**
See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family /
@@ -93,8 +90,7 @@
@endcode
@note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.
**/
-#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010
-
+#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010
/**
Platform ID (RO) The operating system can use this MSR to determine "slot"
@@ -115,7 +111,7 @@
@endcode
@note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.
**/
-#define MSR_IA32_PLATFORM_ID 0x00000017
+#define MSR_IA32_PLATFORM_ID 0x00000017
/**
MSR information returned for MSR index #MSR_IA32_PLATFORM_ID
@@ -125,8 +121,8 @@ typedef union {
/// Individual bit fields
///
struct {
- UINT32 Reserved1:32;
- UINT32 Reserved2:18;
+ UINT32 Reserved1 : 32;
+ UINT32 Reserved2 : 18;
///
/// [Bits 52:50] Platform Id (RO) Contains information concerning the
/// intended platform for the processor.
@@ -141,16 +137,15 @@ typedef union {
/// 1 1 0 Processor Flag 6
/// 1 1 1 Processor Flag 7
///
- UINT32 PlatformId:3;
- UINT32 Reserved3:11;
+ UINT32 PlatformId : 3;
+ UINT32 Reserved3 : 11;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PLATFORM_ID_REGISTER;
-
/**
06_01H.
@@ -169,7 +164,7 @@ typedef union {
@endcode
@note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.
**/
-#define MSR_IA32_APIC_BASE 0x0000001B
+#define MSR_IA32_APIC_BASE 0x0000001B
/**
MSR information returned for MSR index #MSR_IA32_APIC_BASE
@@ -179,37 +174,36 @@ typedef union {
/// Individual bit fields
///
struct {
- UINT32 Reserved1:8;
+ UINT32 Reserved1 : 8;
///
/// [Bit 8] BSP flag (R/W).
///
- UINT32 BSP:1;
- UINT32 Reserved2:1;
+ UINT32 BSP : 1;
+ UINT32 Reserved2 : 1;
///
/// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display
/// Model 06_1AH.
///
- UINT32 EXTD:1;
+ UINT32 EXTD : 1;
///
/// [Bit 11] APIC Global Enable (R/W).
///
- UINT32 EN:1;
+ UINT32 EN : 1;
///
/// [Bits 31:12] APIC Base (R/W).
///
- UINT32 ApicBase:20;
+ UINT32 ApicBase : 20;
///
/// [Bits 63:32] APIC Base (R/W).
///
- UINT32 ApicBaseHi:32;
+ UINT32 ApicBaseHi : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_APIC_BASE_REGISTER;
-
/**
Control Features in Intel 64 Processor (R/W). If any one enumeration
condition for defined bit field holds.
@@ -229,7 +223,7 @@ typedef union {
@endcode
@note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
**/
-#define MSR_IA32_FEATURE_CONTROL 0x0000003A
+#define MSR_IA32_FEATURE_CONTROL 0x0000003A
/**
MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL
@@ -250,7 +244,7 @@ typedef union {
/// is not deasserted. If any one enumeration condition for defined bit
/// field position greater than bit 0 holds.
///
- UINT32 Lock:1;
+ UINT32 Lock : 1;
///
/// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a
/// system executive to use VMX in conjunction with SMX to support
@@ -259,61 +253,60 @@ typedef union {
/// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&
/// CPUID.01H:ECX[6] = 1.
///
- UINT32 EnableVmxInsideSmx:1;
+ UINT32 EnableVmxInsideSmx : 1;
///
/// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX
/// for system executive that do not require SMX. BIOS must set this bit
/// only when the CPUID function 1 returns VMX feature flag set (ECX bit
/// 5). If CPUID.01H:ECX[5] = 1.
///
- UINT32 EnableVmxOutsideSmx:1;
- UINT32 Reserved1:5;
+ UINT32 EnableVmxOutsideSmx : 1;
+ UINT32 Reserved1 : 5;
///
/// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit
/// in the field represents an enable control for a corresponding SENTER
/// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If
/// CPUID.01H:ECX[6] = 1.
///
- UINT32 SenterLocalFunctionEnables:7;
+ UINT32 SenterLocalFunctionEnables : 7;
///
/// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable
/// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit
/// 6] is set. If CPUID.01H:ECX[6] = 1.
///
- UINT32 SenterGlobalEnable:1;
- UINT32 Reserved2:1;
+ UINT32 SenterGlobalEnable : 1;
+ UINT32 Reserved2 : 1;
///
/// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to
/// enable runtime reconfiguration of SGX Launch Control via
/// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.
///
- UINT32 SgxLaunchControlEnable:1;
+ UINT32 SgxLaunchControlEnable : 1;
///
/// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX
/// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.
///
- UINT32 SgxEnable:1;
- UINT32 Reserved3:1;
+ UINT32 SgxEnable : 1;
+ UINT32 Reserved3 : 1;
///
/// [Bit 20] LMCE On (R/WL): When set, system software can program the
/// MSRs associated with LMCE to configure delivery of some machine check
/// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.
///
- UINT32 LmceOn:1;
- UINT32 Reserved4:11;
- UINT32 Reserved5:32;
+ UINT32 LmceOn : 1;
+ UINT32 Reserved4 : 11;
+ UINT32 Reserved5 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_FEATURE_CONTROL_REGISTER;
-
/**
Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,
ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for
@@ -334,8 +327,7 @@ typedef union {
@endcode
@note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.
**/
-#define MSR_IA32_TSC_ADJUST 0x0000003B
-
+#define MSR_IA32_TSC_ADJUST 0x0000003B
/**
BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a
@@ -357,8 +349,7 @@ typedef union {
@endcode
@note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.
**/
-#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
-
+#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
/**
BIOS Update Signature (RO) Returns the microcode update signature following
@@ -380,7 +371,7 @@ typedef union {
@endcode
@note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.
**/
-#define MSR_IA32_BIOS_SIGN_ID 0x0000008B
+#define MSR_IA32_BIOS_SIGN_ID 0x0000008B
/**
MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID
@@ -390,7 +381,7 @@ typedef union {
/// Individual bit fields
///
struct {
- UINT32 Reserved:32;
+ UINT32 Reserved : 32;
///
/// [Bits 63:32] Microcode update signature. This field contains the
/// signature of the currently loaded microcode update when read following
@@ -400,15 +391,14 @@ typedef union {
/// is no microcode update loaded. Another nonzero value will be the
/// signature.
///
- UINT32 MicrocodeUpdateSignature:32;
+ UINT32 MicrocodeUpdateSignature : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_BIOS_SIGN_ID_REGISTER;
-
/**
IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the
SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the
@@ -433,13 +423,12 @@ typedef union {
MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.
@{
**/
-#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
-#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
-#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
-#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
+#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
+#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
+#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
+#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
/// @}
-
/**
SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =
1.
@@ -459,7 +448,7 @@ typedef union {
@endcode
@note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.
**/
-#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B
+#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B
/**
MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL
@@ -476,28 +465,28 @@ typedef union {
/// if the bit is 0. This bit is cleared when the logical processor is
/// reset.
///
- UINT32 Valid:1;
- UINT32 Reserved1:1;
+ UINT32 Valid : 1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If
/// IA32_VMX_MISC[28].
///
- UINT32 BlockSmi:1;
- UINT32 Reserved2:9;
+ UINT32 BlockSmi : 1;
+ UINT32 Reserved2 : 9;
///
/// [Bits 31:12] MSEG Base (R/W).
///
- UINT32 MsegBase:20;
- UINT32 Reserved3:32;
+ UINT32 MsegBase : 20;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_SMM_MONITOR_CTL_REGISTER;
/**
@@ -512,29 +501,29 @@ typedef struct {
/// discover the MSEG revision identifier that a processor uses by reading
/// the VMX capability MSR IA32_VMX_MISC.
//
- UINT32 MsegHeaderRevision;
+ UINT32 MsegHeaderRevision;
///
/// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field
/// is the IA-32e mode SMM feature bit. It indicates whether the logical
/// processor will be in IA-32e mode after the STM is activated.
///
- UINT32 MonitorFeatures;
- UINT32 GdtrLimit;
- UINT32 GdtrBaseOffset;
- UINT32 CsSelector;
- UINT32 EipOffset;
- UINT32 EspOffset;
- UINT32 Cr3Offset;
+ UINT32 MonitorFeatures;
+ UINT32 GdtrLimit;
+ UINT32 GdtrBaseOffset;
+ UINT32 CsSelector;
+ UINT32 EipOffset;
+ UINT32 EspOffset;
+ UINT32 Cr3Offset;
///
/// Pad header so total size is 2KB
///
- UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];
+ UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];
} MSEG_HEADER;
///
/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER
///
-#define STM_FEATURES_IA32E 0x1
+#define STM_FEATURES_IA32E 0x1
///
/// @}
///
@@ -555,8 +544,7 @@ typedef struct {
@endcode
@note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.
**/
-#define MSR_IA32_SMBASE 0x0000009E
-
+#define MSR_IA32_SMBASE 0x0000009E
/**
General Performance Counters (R/W).
@@ -583,17 +571,16 @@ typedef struct {
MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.
@{
**/
-#define MSR_IA32_PMC0 0x000000C1
-#define MSR_IA32_PMC1 0x000000C2
-#define MSR_IA32_PMC2 0x000000C3
-#define MSR_IA32_PMC3 0x000000C4
-#define MSR_IA32_PMC4 0x000000C5
-#define MSR_IA32_PMC5 0x000000C6
-#define MSR_IA32_PMC6 0x000000C7
-#define MSR_IA32_PMC7 0x000000C8
+#define MSR_IA32_PMC0 0x000000C1
+#define MSR_IA32_PMC1 0x000000C2
+#define MSR_IA32_PMC2 0x000000C3
+#define MSR_IA32_PMC3 0x000000C4
+#define MSR_IA32_PMC4 0x000000C5
+#define MSR_IA32_PMC5 0x000000C6
+#define MSR_IA32_PMC6 0x000000C7
+#define MSR_IA32_PMC7 0x000000C8
/// @}
-
/**
TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.
C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative
@@ -613,8 +600,7 @@ typedef struct {
@endcode
@note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.
**/
-#define MSR_IA32_MPERF 0x000000E7
-
+#define MSR_IA32_MPERF 0x000000E7
/**
Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =
@@ -635,8 +621,7 @@ typedef struct {
@endcode
@note MSR_IA32_APERF is defined as IA32_APERF in SDM.
**/
-#define MSR_IA32_APERF 0x000000E8
-
+#define MSR_IA32_APERF 0x000000E8
/**
MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".
@@ -656,7 +641,7 @@ typedef struct {
@endcode
@note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.
**/
-#define MSR_IA32_MTRRCAP 0x000000FE
+#define MSR_IA32_MTRRCAP 0x000000FE
/**
MSR information returned for MSR index #MSR_IA32_MTRRCAP
@@ -670,34 +655,33 @@ typedef union {
/// [Bits 7:0] VCNT: The number of variable memory type ranges in the
/// processor.
///
- UINT32 VCNT:8;
+ UINT32 VCNT : 8;
///
/// [Bit 8] Fixed range MTRRs are supported when set.
///
- UINT32 FIX:1;
- UINT32 Reserved1:1;
+ UINT32 FIX : 1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 10] WC Supported when set.
///
- UINT32 WC:1;
+ UINT32 WC : 1;
///
/// [Bit 11] SMRR Supported when set.
///
- UINT32 SMRR:1;
- UINT32 Reserved2:20;
- UINT32 Reserved3:32;
+ UINT32 SMRR : 1;
+ UINT32 Reserved2 : 20;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_MTRRCAP_REGISTER;
-
/**
SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
@@ -716,7 +700,7 @@ typedef union {
@endcode
@note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.
**/
-#define MSR_IA32_SYSENTER_CS 0x00000174
+#define MSR_IA32_SYSENTER_CS 0x00000174
/**
MSR information returned for MSR index #MSR_IA32_SYSENTER_CS
@@ -729,21 +713,20 @@ typedef union {
///
/// [Bits 15:0] CS Selector.
///
- UINT32 CS:16;
- UINT32 Reserved1:16;
- UINT32 Reserved2:32;
+ UINT32 CS : 16;
+ UINT32 Reserved1 : 16;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_SYSENTER_CS_REGISTER;
-
/**
SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
@@ -760,8 +743,7 @@ typedef union {
@endcode
@note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.
**/
-#define MSR_IA32_SYSENTER_ESP 0x00000175
-
+#define MSR_IA32_SYSENTER_ESP 0x00000175
/**
SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
@@ -779,8 +761,7 @@ typedef union {
@endcode
@note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.
**/
-#define MSR_IA32_SYSENTER_EIP 0x00000176
-
+#define MSR_IA32_SYSENTER_EIP 0x00000176
/**
Global Machine Check Capability (RO). Introduced at Display Family / Display
@@ -800,7 +781,7 @@ typedef union {
@endcode
@note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
**/
-#define MSR_IA32_MCG_CAP 0x00000179
+#define MSR_IA32_MCG_CAP 0x00000179
/**
MSR information returned for MSR index #MSR_IA32_MCG_CAP
@@ -813,38 +794,38 @@ typedef union {
///
/// [Bits 7:0] Count: Number of reporting banks.
///
- UINT32 Count:8;
+ UINT32 Count : 8;
///
/// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.
///
- UINT32 MCG_CTL_P:1;
+ UINT32 MCG_CTL_P : 1;
///
/// [Bit 9] MCG_EXT_P: Extended machine check state registers are present
/// if this bit is set.
///
- UINT32 MCG_EXT_P:1;
+ UINT32 MCG_EXT_P : 1;
///
/// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.
/// Introduced at Display Family / Display Model 06_01H.
///
- UINT32 MCP_CMCI_P:1;
+ UINT32 MCP_CMCI_P : 1;
///
/// [Bit 11] MCG_TES_P: Threshold-based error status register are present
/// if this bit is set.
///
- UINT32 MCG_TES_P:1;
- UINT32 Reserved1:4;
+ UINT32 MCG_TES_P : 1;
+ UINT32 Reserved1 : 4;
///
/// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state
/// registers present.
///
- UINT32 MCG_EXT_CNT:8;
+ UINT32 MCG_EXT_CNT : 8;
///
/// [Bit 24] MCG_SER_P: The processor supports software error recovery if
/// this bit is set.
///
- UINT32 MCG_SER_P:1;
- UINT32 Reserved2:1;
+ UINT32 MCG_SER_P : 1;
+ UINT32 Reserved2 : 1;
///
/// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform
/// firmware to be invoked when an error is detected so that it may
@@ -853,28 +834,27 @@ typedef union {
/// check bank registers. Introduced at Display Family / Display Model
/// 06_3EH.
///
- UINT32 MCG_ELOG_P:1;
+ UINT32 MCG_ELOG_P : 1;
///
/// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended
/// state in IA32_MCG_STATUS and associated MSR necessary to configure
/// Local Machine Check Exception (LMCE). Introduced at Display Family /
/// Display Model 06_3EH.
///
- UINT32 MCG_LMCE_P:1;
- UINT32 Reserved3:4;
- UINT32 Reserved4:32;
+ UINT32 MCG_LMCE_P : 1;
+ UINT32 Reserved3 : 4;
+ UINT32 Reserved4 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_MCG_CAP_REGISTER;
-
/**
Global Machine Check Status (R/W0). Introduced at Display Family / Display
Model 06_01H.
@@ -894,7 +874,7 @@ typedef union {
@endcode
@note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.
**/
-#define MSR_IA32_MCG_STATUS 0x0000017A
+#define MSR_IA32_MCG_STATUS 0x0000017A
/**
MSR information returned for MSR index #MSR_IA32_MCG_STATUS
@@ -908,35 +888,34 @@ typedef union {
/// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display
/// Model 06_01H.
///
- UINT32 RIPV:1;
+ UINT32 RIPV : 1;
///
/// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display
/// Model 06_01H.
///
- UINT32 EIPV:1;
+ UINT32 EIPV : 1;
///
/// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family
/// / Display Model 06_01H.
///
- UINT32 MCIP:1;
+ UINT32 MCIP : 1;
///
/// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.
///
- UINT32 LMCE_S:1;
- UINT32 Reserved1:28;
- UINT32 Reserved2:32;
+ UINT32 LMCE_S : 1;
+ UINT32 Reserved1 : 28;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_MCG_STATUS_REGISTER;
-
/**
Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.
@@ -953,8 +932,7 @@ typedef union {
@endcode
@note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.
**/
-#define MSR_IA32_MCG_CTL 0x0000017B
-
+#define MSR_IA32_MCG_CTL 0x0000017B
/**
Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.
@@ -978,10 +956,10 @@ typedef union {
MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.
@{
**/
-#define MSR_IA32_PERFEVTSEL0 0x00000186
-#define MSR_IA32_PERFEVTSEL1 0x00000187
-#define MSR_IA32_PERFEVTSEL2 0x00000188
-#define MSR_IA32_PERFEVTSEL3 0x00000189
+#define MSR_IA32_PERFEVTSEL0 0x00000186
+#define MSR_IA32_PERFEVTSEL1 0x00000187
+#define MSR_IA32_PERFEVTSEL2 0x00000188
+#define MSR_IA32_PERFEVTSEL3 0x00000189
/// @}
/**
@@ -996,32 +974,32 @@ typedef union {
///
/// [Bits 7:0] Event Select: Selects a performance event logic unit.
///
- UINT32 EventSelect:8;
+ UINT32 EventSelect : 8;
///
/// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
/// detect on the selected event logic.
///
- UINT32 UMASK:8;
+ UINT32 UMASK : 8;
///
/// [Bit 16] USR: Counts while in privilege level is not ring 0.
///
- UINT32 USR:1;
+ UINT32 USR : 1;
///
/// [Bit 17] OS: Counts while in privilege level is ring 0.
///
- UINT32 OS:1;
+ UINT32 OS : 1;
///
/// [Bit 18] Edge: Enables edge detection if set.
///
- UINT32 E:1;
+ UINT32 E : 1;
///
/// [Bit 19] PC: enables pin control.
///
- UINT32 PC:1;
+ UINT32 PC : 1;
///
/// [Bit 20] INT: enables interrupt on counter overflow.
///
- UINT32 INT:1;
+ UINT32 INT : 1;
///
/// [Bit 21] AnyThread: When set to 1, it enables counting the associated
/// event conditions occurring across all logical processors sharing a
@@ -1029,35 +1007,34 @@ typedef union {
/// associated event conditions occurring in the logical processor which
/// programmed the MSR.
///
- UINT32 ANY:1;
+ UINT32 ANY : 1;
///
/// [Bit 22] EN: enables the corresponding performance counter to commence
/// counting when this bit is set.
///
- UINT32 EN:1;
+ UINT32 EN : 1;
///
/// [Bit 23] INV: invert the CMASK.
///
- UINT32 INV:1;
+ UINT32 INV : 1;
///
/// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
/// performance counter increments each cycle if the event count is
/// greater than or equal to the CMASK.
///
- UINT32 CMASK:8;
- UINT32 Reserved:32;
+ UINT32 CMASK : 8;
+ UINT32 Reserved : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PERFEVTSEL_REGISTER;
-
/**
Current performance state(P-State) operating point (RO). Introduced at
Display Family / Display Model 0F_03H.
@@ -1076,7 +1053,7 @@ typedef union {
@endcode
@note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM.
**/
-#define MSR_IA32_PERF_STATUS 0x00000198
+#define MSR_IA32_PERF_STATUS 0x00000198
/**
MSR information returned for MSR index #MSR_IA32_PERF_STATUS
@@ -1089,21 +1066,20 @@ typedef union {
///
/// [Bits 15:0] Current performance State Value.
///
- UINT32 State:16;
- UINT32 Reserved1:16;
- UINT32 Reserved2:32;
+ UINT32 State : 16;
+ UINT32 Reserved1 : 16;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PERF_STATUS_REGISTER;
-
/**
(R/W). Introduced at Display Family / Display Model 0F_03H.
@@ -1122,7 +1098,7 @@ typedef union {
@endcode
@note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM.
**/
-#define MSR_IA32_PERF_CTL 0x00000199
+#define MSR_IA32_PERF_CTL 0x00000199
/**
MSR information returned for MSR index #MSR_IA32_PERF_CTL
@@ -1135,22 +1111,21 @@ typedef union {
///
/// [Bits 15:0] Target performance State Value.
///
- UINT32 TargetState:16;
- UINT32 Reserved1:16;
+ UINT32 TargetState : 16;
+ UINT32 Reserved1 : 16;
///
/// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH
/// (Mobile only).
///
- UINT32 IDA:1;
- UINT32 Reserved2:31;
+ UINT32 IDA : 1;
+ UINT32 Reserved2 : 31;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PERF_CTL_REGISTER;
-
/**
Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled
Clock Modulation.". If CPUID.01H:EDX[22] = 1.
@@ -1170,7 +1145,7 @@ typedef union {
@endcode
@note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.
**/
-#define MSR_IA32_CLOCK_MODULATION 0x0000019A
+#define MSR_IA32_CLOCK_MODULATION 0x0000019A
/**
MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION
@@ -1184,31 +1159,30 @@ typedef union {
/// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If
/// CPUID.06H:EAX[5] = 1.
///
- UINT32 ExtendedOnDemandClockModulationDutyCycle:1;
+ UINT32 ExtendedOnDemandClockModulationDutyCycle : 1;
///
/// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded
/// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1.
///
- UINT32 OnDemandClockModulationDutyCycle:3;
+ UINT32 OnDemandClockModulationDutyCycle : 3;
///
/// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.
/// If CPUID.01H:EDX[22] = 1.
///
- UINT32 OnDemandClockModulationEnable:1;
- UINT32 Reserved1:27;
- UINT32 Reserved2:32;
+ UINT32 OnDemandClockModulationEnable : 1;
+ UINT32 Reserved1 : 27;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_CLOCK_MODULATION_REGISTER;
-
/**
Thermal Interrupt Control (R/W) Enables and disables the generation of an
interrupt on temperature transitions detected with the processor's thermal
@@ -1230,7 +1204,7 @@ typedef union {
@endcode
@note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM.
**/
-#define MSR_IA32_THERM_INTERRUPT 0x0000019B
+#define MSR_IA32_THERM_INTERRUPT 0x0000019B
/**
MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT
@@ -1243,59 +1217,58 @@ typedef union {
///
/// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.
///
- UINT32 HighTempEnable:1;
+ UINT32 HighTempEnable : 1;
///
/// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.
///
- UINT32 LowTempEnable:1;
+ UINT32 LowTempEnable : 1;
///
/// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1.
///
- UINT32 PROCHOT_Enable:1;
+ UINT32 PROCHOT_Enable : 1;
///
/// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1.
///
- UINT32 FORCEPR_Enable:1;
+ UINT32 FORCEPR_Enable : 1;
///
/// [Bit 4] Critical Temperature Interrupt Enable.
/// If CPUID.01H:EDX[22] = 1.
///
- UINT32 CriticalTempEnable:1;
- UINT32 Reserved1:3;
+ UINT32 CriticalTempEnable : 1;
+ UINT32 Reserved1 : 3;
///
/// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1.
///
- UINT32 Threshold1:7;
+ UINT32 Threshold1 : 7;
///
/// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1.
///
- UINT32 Threshold1Enable:1;
+ UINT32 Threshold1Enable : 1;
///
/// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1.
///
- UINT32 Threshold2:7;
+ UINT32 Threshold2 : 7;
///
/// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1.
///
- UINT32 Threshold2Enable:1;
+ UINT32 Threshold2Enable : 1;
///
/// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.
///
- UINT32 PowerLimitNotificationEnable:1;
- UINT32 Reserved2:7;
- UINT32 Reserved3:32;
+ UINT32 PowerLimitNotificationEnable : 1;
+ UINT32 Reserved2 : 7;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_THERM_INTERRUPT_REGISTER;
-
/**
Thermal Status Information (RO) Contains status information about the
processor's thermal sensor and automatic thermal monitoring facilities. See
@@ -1315,7 +1288,7 @@ typedef union {
@endcode
@note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM.
**/
-#define MSR_IA32_THERM_STATUS 0x0000019C
+#define MSR_IA32_THERM_STATUS 0x0000019C
/**
MSR information returned for MSR index #MSR_IA32_THERM_STATUS
@@ -1328,95 +1301,94 @@ typedef union {
///
/// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1.
///
- UINT32 ThermalStatus:1;
+ UINT32 ThermalStatus : 1;
///
/// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1.
///
- UINT32 ThermalStatusLog:1;
+ UINT32 ThermalStatusLog : 1;
///
/// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1.
///
- UINT32 PROCHOT_FORCEPR_Event:1;
+ UINT32 PROCHOT_FORCEPR_Event : 1;
///
/// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1.
///
- UINT32 PROCHOT_FORCEPR_Log:1;
+ UINT32 PROCHOT_FORCEPR_Log : 1;
///
/// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1.
///
- UINT32 CriticalTempStatus:1;
+ UINT32 CriticalTempStatus : 1;
///
/// [Bit 5] Critical Temperature Status log (R/WC0).
/// If CPUID.01H:EDX[22] = 1.
///
- UINT32 CriticalTempStatusLog:1;
+ UINT32 CriticalTempStatusLog : 1;
///
/// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.
///
- UINT32 ThermalThreshold1Status:1;
+ UINT32 ThermalThreshold1Status : 1;
///
/// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.
///
- UINT32 ThermalThreshold1Log:1;
+ UINT32 ThermalThreshold1Log : 1;
///
/// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.
///
- UINT32 ThermalThreshold2Status:1;
+ UINT32 ThermalThreshold2Status : 1;
///
/// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.
///
- UINT32 ThermalThreshold2Log:1;
+ UINT32 ThermalThreshold2Log : 1;
///
/// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.
///
- UINT32 PowerLimitStatus:1;
+ UINT32 PowerLimitStatus : 1;
///
/// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.
///
- UINT32 PowerLimitLog:1;
+ UINT32 PowerLimitLog : 1;
///
/// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.
///
- UINT32 CurrentLimitStatus:1;
+ UINT32 CurrentLimitStatus : 1;
///
/// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
///
- UINT32 CurrentLimitLog:1;
+ UINT32 CurrentLimitLog : 1;
///
/// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.
///
- UINT32 CrossDomainLimitStatus:1;
+ UINT32 CrossDomainLimitStatus : 1;
///
/// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
///
- UINT32 CrossDomainLimitLog:1;
+ UINT32 CrossDomainLimitLog : 1;
///
/// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.
///
- UINT32 DigitalReadout:7;
- UINT32 Reserved1:4;
+ UINT32 DigitalReadout : 7;
+ UINT32 Reserved1 : 4;
///
/// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] =
/// 1.
///
- UINT32 ResolutionInDegreesCelsius:4;
+ UINT32 ResolutionInDegreesCelsius : 4;
///
/// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.
///
- UINT32 ReadingValid:1;
- UINT32 Reserved2:32;
+ UINT32 ReadingValid : 1;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_THERM_STATUS_REGISTER;
-
/**
Enable Misc. Processor Features (R/W) Allows a variety of processor
functions to be enabled and disabled.
@@ -1436,7 +1408,7 @@ typedef union {
@endcode
@note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
**/
-#define MSR_IA32_MISC_ENABLE 0x000001A0
+#define MSR_IA32_MISC_ENABLE 0x000001A0
/**
MSR information returned for MSR index #MSR_IA32_MISC_ENABLE
@@ -1451,8 +1423,8 @@ typedef union {
/// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings
/// are disabled. Introduced at Display Family / Display Model 0F_0H.
///
- UINT32 FastStrings:1;
- UINT32 Reserved1:2;
+ UINT32 FastStrings : 1;
+ UINT32 Reserved1 : 2;
///
/// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting
/// this bit enables the thermal control circuit (TCC) portion of the
@@ -1464,35 +1436,35 @@ typedef union {
/// field varies with product. See respective tables where default value is
/// listed. Introduced at Display Family / Display Model 0F_0H.
///
- UINT32 AutomaticThermalControlCircuit:1;
- UINT32 Reserved2:3;
+ UINT32 AutomaticThermalControlCircuit : 1;
+ UINT32 Reserved2 : 3;
///
/// [Bit 7] Performance Monitoring Available (R) 1 = Performance
/// monitoring enabled 0 = Performance monitoring disabled. Introduced at
/// Display Family / Display Model 0F_0H.
///
- UINT32 PerformanceMonitoring:1;
- UINT32 Reserved3:3;
+ UINT32 PerformanceMonitoring : 1;
+ UINT32 Reserved3 : 3;
///
/// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't
/// support branch trace storage (BTS) 0 = BTS is supported. Introduced at
/// Display Family / Display Model 0F_0H.
///
- UINT32 BTS:1;
+ UINT32 BTS : 1;
///
/// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 =
/// PEBS is not supported; 0 = PEBS is supported. Introduced at Display
/// Family / Display Model 06_0FH.
///
- UINT32 PEBS:1;
- UINT32 Reserved4:3;
+ UINT32 PEBS : 1;
+ UINT32 Reserved4 : 3;
///
/// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced
/// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep
/// Technology enabled. If CPUID.01H: ECX[7] =1.
///
- UINT32 EIST:1;
- UINT32 Reserved5:1;
+ UINT32 EIST : 1;
+ UINT32 Reserved5 : 1;
///
/// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the
/// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This
@@ -1505,8 +1477,8 @@ typedef union {
/// set to 0 may generate a #GP exception. Introduced at Display Family /
/// Display Model 0F_03H.
///
- UINT32 MONITOR:1;
- UINT32 Reserved6:3;
+ UINT32 MONITOR : 1;
+ UINT32 Reserved6 : 3;
///
/// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H
/// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup
@@ -1520,15 +1492,15 @@ typedef union {
/// depends on the availability of CPUID leaves greater than 2. Introduced
/// at Display Family / Display Model 0F_03H.
///
- UINT32 LimitCpuidMaxval:1;
+ UINT32 LimitCpuidMaxval : 1;
///
/// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
/// disabled. xTPR messages are optional messages that allow the processor
/// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.
///
- UINT32 xTPR_Message_Disable:1;
- UINT32 Reserved7:8;
- UINT32 Reserved8:2;
+ UINT32 xTPR_Message_Disable : 1;
+ UINT32 Reserved7 : 8;
+ UINT32 Reserved8 : 2;
///
/// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit
/// feature (XD Bit) is disabled and the XD Bit extended feature flag will
@@ -1539,16 +1511,15 @@ typedef union {
/// this bit to 1 when the XD Bit extended feature flag is set to 0 may
/// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.
///
- UINT32 XD:1;
- UINT32 Reserved9:29;
+ UINT32 XD : 1;
+ UINT32 Reserved9 : 29;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_MISC_ENABLE_REGISTER;
-
/**
Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.
@@ -1567,7 +1538,7 @@ typedef union {
@endcode
@note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
**/
-#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0
+#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0
/**
MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS
@@ -1581,21 +1552,20 @@ typedef union {
/// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest
/// performance. 15 indicates preference to maximize energy saving.
///
- UINT32 PowerPolicyPreference:4;
- UINT32 Reserved1:28;
- UINT32 Reserved2:32;
+ UINT32 PowerPolicyPreference : 4;
+ UINT32 Reserved1 : 28;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_ENERGY_PERF_BIAS_REGISTER;
-
/**
Package Thermal Status Information (RO) Contains status information about
the package's thermal sensor. See Section 14.8, "Package Level Thermal
@@ -1615,7 +1585,7 @@ typedef union {
@endcode
@note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM.
**/
-#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1
+#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1
/**
MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS
@@ -1628,70 +1598,69 @@ typedef union {
///
/// [Bit 0] Pkg Thermal Status (RO):.
///
- UINT32 ThermalStatus:1;
+ UINT32 ThermalStatus : 1;
///
/// [Bit 1] Pkg Thermal Status Log (R/W):.
///
- UINT32 ThermalStatusLog:1;
+ UINT32 ThermalStatusLog : 1;
///
/// [Bit 2] Pkg PROCHOT # event (RO).
///
- UINT32 PROCHOT_Event:1;
+ UINT32 PROCHOT_Event : 1;
///
/// [Bit 3] Pkg PROCHOT # log (R/WC0).
///
- UINT32 PROCHOT_Log:1;
+ UINT32 PROCHOT_Log : 1;
///
/// [Bit 4] Pkg Critical Temperature Status (RO).
///
- UINT32 CriticalTempStatus:1;
+ UINT32 CriticalTempStatus : 1;
///
/// [Bit 5] Pkg Critical Temperature Status log (R/WC0).
///
- UINT32 CriticalTempStatusLog:1;
+ UINT32 CriticalTempStatusLog : 1;
///
/// [Bit 6] Pkg Thermal Threshold #1 Status (RO).
///
- UINT32 ThermalThreshold1Status:1;
+ UINT32 ThermalThreshold1Status : 1;
///
/// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0).
///
- UINT32 ThermalThreshold1Log:1;
+ UINT32 ThermalThreshold1Log : 1;
///
/// [Bit 8] Pkg Thermal Threshold #2 Status (RO).
///
- UINT32 ThermalThreshold2Status:1;
+ UINT32 ThermalThreshold2Status : 1;
///
/// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0).
///
- UINT32 ThermalThreshold2Log:1;
+ UINT32 ThermalThreshold2Log : 1;
///
/// [Bit 10] Pkg Power Limitation Status (RO).
///
- UINT32 PowerLimitStatus:1;
+ UINT32 PowerLimitStatus : 1;
///
/// [Bit 11] Pkg Power Limitation log (R/WC0).
///
- UINT32 PowerLimitLog:1;
- UINT32 Reserved1:4;
+ UINT32 PowerLimitLog : 1;
+ UINT32 Reserved1 : 4;
///
/// [Bits 22:16] Pkg Digital Readout (RO).
///
- UINT32 DigitalReadout:7;
- UINT32 Reserved2:9;
- UINT32 Reserved3:32;
+ UINT32 DigitalReadout : 7;
+ UINT32 Reserved2 : 9;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PACKAGE_THERM_STATUS_REGISTER;
-
/**
Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of
an interrupt on temperature transitions detected with the package's thermal
@@ -1713,7 +1682,7 @@ typedef union {
@endcode
@note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM.
**/
-#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2
+#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2
/**
MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT
@@ -1726,55 +1695,54 @@ typedef union {
///
/// [Bit 0] Pkg High-Temperature Interrupt Enable.
///
- UINT32 HighTempEnable:1;
+ UINT32 HighTempEnable : 1;
///
/// [Bit 1] Pkg Low-Temperature Interrupt Enable.
///
- UINT32 LowTempEnable:1;
+ UINT32 LowTempEnable : 1;
///
/// [Bit 2] Pkg PROCHOT# Interrupt Enable.
///
- UINT32 PROCHOT_Enable:1;
- UINT32 Reserved1:1;
+ UINT32 PROCHOT_Enable : 1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 4] Pkg Overheat Interrupt Enable.
///
- UINT32 OverheatEnable:1;
- UINT32 Reserved2:3;
+ UINT32 OverheatEnable : 1;
+ UINT32 Reserved2 : 3;
///
/// [Bits 14:8] Pkg Threshold #1 Value.
///
- UINT32 Threshold1:7;
+ UINT32 Threshold1 : 7;
///
/// [Bit 15] Pkg Threshold #1 Interrupt Enable.
///
- UINT32 Threshold1Enable:1;
+ UINT32 Threshold1Enable : 1;
///
/// [Bits 22:16] Pkg Threshold #2 Value.
///
- UINT32 Threshold2:7;
+ UINT32 Threshold2 : 7;
///
/// [Bit 23] Pkg Threshold #2 Interrupt Enable.
///
- UINT32 Threshold2Enable:1;
+ UINT32 Threshold2Enable : 1;
///
/// [Bit 24] Pkg Power Limit Notification Enable.
///
- UINT32 PowerLimitNotificationEnable:1;
- UINT32 Reserved3:7;
- UINT32 Reserved4:32;
+ UINT32 PowerLimitNotificationEnable : 1;
+ UINT32 Reserved3 : 7;
+ UINT32 Reserved4 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER;
-
/**
Trace/Profile Resource Control (R/W). Introduced at Display Family / Display
Model 06_0EH.
@@ -1794,7 +1762,7 @@ typedef union {
@endcode
@note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM.
**/
-#define MSR_IA32_DEBUGCTL 0x000001D9
+#define MSR_IA32_DEBUGCTL 0x000001D9
/**
MSR information returned for MSR index #MSR_IA32_DEBUGCTL
@@ -1809,83 +1777,82 @@ typedef union {
/// running trace of the most recent branches taken by the processor in
/// the LBR stack. Introduced at Display Family / Display Model 06_01H.
///
- UINT32 LBR:1;
+ UINT32 LBR : 1;
///
/// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat
/// EFLAGS.TF as single-step on branches instead of single-step on
/// instructions. Introduced at Display Family / Display Model 06_01H.
///
- UINT32 BTF:1;
- UINT32 Reserved1:4;
+ UINT32 BTF : 1;
+ UINT32 Reserved1 : 4;
///
/// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be
/// sent. Introduced at Display Family / Display Model 06_0EH.
///
- UINT32 TR:1;
+ UINT32 TR : 1;
///
/// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to
/// be logged in a BTS buffer. Introduced at Display Family / Display
/// Model 06_0EH.
///
- UINT32 BTS:1;
+ UINT32 BTS : 1;
///
/// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular
/// fashion. When this bit is set, an interrupt is generated by the BTS
/// facility when the BTS buffer is full. Introduced at Display Family /
/// Display Model 06_0EH.
///
- UINT32 BTINT:1;
+ UINT32 BTINT : 1;
///
/// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.
/// Introduced at Display Family / Display Model 06_0FH.
///
- UINT32 BTS_OFF_OS:1;
+ UINT32 BTS_OFF_OS : 1;
///
/// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.
/// Introduced at Display Family / Display Model 06_0FH.
///
- UINT32 BTS_OFF_USR:1;
+ UINT32 BTS_OFF_USR : 1;
///
/// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a
/// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
///
- UINT32 FREEZE_LBRS_ON_PMI:1;
+ UINT32 FREEZE_LBRS_ON_PMI : 1;
///
/// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the
/// global counter control MSR are frozen (address 38FH) on a PMI request.
/// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
///
- UINT32 FREEZE_PERFMON_ON_PMI:1;
+ UINT32 FREEZE_PERFMON_ON_PMI : 1;
///
/// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to
/// receive and generate PMI on behalf of the uncore. Introduced at
/// Display Family / Display Model 06_1AH.
///
- UINT32 ENABLE_UNCORE_PMI:1;
+ UINT32 ENABLE_UNCORE_PMI : 1;
///
/// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace
/// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.
///
- UINT32 FREEZE_WHILE_SMM:1;
+ UINT32 FREEZE_WHILE_SMM : 1;
///
/// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If
/// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).
///
- UINT32 RTM_DEBUG:1;
- UINT32 Reserved2:16;
- UINT32 Reserved3:32;
+ UINT32 RTM_DEBUG : 1;
+ UINT32 Reserved2 : 16;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_DEBUGCTL_REGISTER;
-
/**
SMRR Base Address (Writeable only in SMM) Base address of SMM memory range.
If IA32_MTRRCAP.SMRR[11] = 1.
@@ -1905,7 +1872,7 @@ typedef union {
@endcode
@note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM.
**/
-#define MSR_IA32_SMRR_PHYSBASE 0x000001F2
+#define MSR_IA32_SMRR_PHYSBASE 0x000001F2
/**
MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE
@@ -1918,25 +1885,24 @@ typedef union {
///
/// [Bits 7:0] Type. Specifies memory type of the range.
///
- UINT32 Type:8;
- UINT32 Reserved1:4;
+ UINT32 Type : 8;
+ UINT32 Reserved1 : 4;
///
/// [Bits 31:12] PhysBase. SMRR physical Base Address.
///
- UINT32 PhysBase:20;
- UINT32 Reserved2:32;
+ UINT32 PhysBase : 20;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_SMRR_PHYSBASE_REGISTER;
-
/**
SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If
IA32_MTRRCAP[SMRR] = 1.
@@ -1956,7 +1922,7 @@ typedef union {
@endcode
@note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM.
**/
-#define MSR_IA32_SMRR_PHYSMASK 0x000001F3
+#define MSR_IA32_SMRR_PHYSMASK 0x000001F3
/**
MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK
@@ -1966,28 +1932,27 @@ typedef union {
/// Individual bit fields
///
struct {
- UINT32 Reserved1:11;
+ UINT32 Reserved1 : 11;
///
/// [Bit 11] Valid Enable range mask.
///
- UINT32 Valid:1;
+ UINT32 Valid : 1;
///
/// [Bits 31:12] PhysMask SMRR address range mask.
///
- UINT32 PhysMask:20;
- UINT32 Reserved2:32;
+ UINT32 PhysMask : 20;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_SMRR_PHYSMASK_REGISTER;
-
/**
DCA Capability (R). If CPUID.01H: ECX[18] = 1.
@@ -2003,8 +1968,7 @@ typedef union {
@endcode
@note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM.
**/
-#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8
-
+#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8
/**
If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.
@@ -2022,8 +1986,7 @@ typedef union {
@endcode
@note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM.
**/
-#define MSR_IA32_CPU_DCA_CAP 0x000001F9
-
+#define MSR_IA32_CPU_DCA_CAP 0x000001F9
/**
DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.
@@ -2043,7 +2006,7 @@ typedef union {
@endcode
@note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM.
**/
-#define MSR_IA32_DCA_0_CAP 0x000001FA
+#define MSR_IA32_DCA_0_CAP 0x000001FA
/**
MSR information returned for MSR index #MSR_IA32_DCA_0_CAP
@@ -2057,49 +2020,48 @@ typedef union {
/// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no
/// defeatures are set.
///
- UINT32 DCA_ACTIVE:1;
+ UINT32 DCA_ACTIVE : 1;
///
/// [Bits 2:1] TRANSACTION.
///
- UINT32 TRANSACTION:2;
+ UINT32 TRANSACTION : 2;
///
/// [Bits 6:3] DCA_TYPE.
///
- UINT32 DCA_TYPE:4;
+ UINT32 DCA_TYPE : 4;
///
/// [Bits 10:7] DCA_QUEUE_SIZE.
///
- UINT32 DCA_QUEUE_SIZE:4;
- UINT32 Reserved1:2;
+ UINT32 DCA_QUEUE_SIZE : 4;
+ UINT32 Reserved1 : 2;
///
/// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW
/// side-effect.
///
- UINT32 DCA_DELAY:4;
- UINT32 Reserved2:7;
+ UINT32 DCA_DELAY : 4;
+ UINT32 Reserved2 : 7;
///
/// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.
///
- UINT32 SW_BLOCK:1;
- UINT32 Reserved3:1;
+ UINT32 SW_BLOCK : 1;
+ UINT32 Reserved3 : 1;
///
/// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).
///
- UINT32 HW_BLOCK:1;
- UINT32 Reserved4:5;
- UINT32 Reserved5:32;
+ UINT32 HW_BLOCK : 1;
+ UINT32 Reserved4 : 5;
+ UINT32 Reserved5 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_DCA_0_CAP_REGISTER;
-
/**
MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs".
If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
@@ -2129,16 +2091,16 @@ typedef union {
MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.
@{
**/
-#define MSR_IA32_MTRR_PHYSBASE0 0x00000200
-#define MSR_IA32_MTRR_PHYSBASE1 0x00000202
-#define MSR_IA32_MTRR_PHYSBASE2 0x00000204
-#define MSR_IA32_MTRR_PHYSBASE3 0x00000206
-#define MSR_IA32_MTRR_PHYSBASE4 0x00000208
-#define MSR_IA32_MTRR_PHYSBASE5 0x0000020A
-#define MSR_IA32_MTRR_PHYSBASE6 0x0000020C
-#define MSR_IA32_MTRR_PHYSBASE7 0x0000020E
-#define MSR_IA32_MTRR_PHYSBASE8 0x00000210
-#define MSR_IA32_MTRR_PHYSBASE9 0x00000212
+#define MSR_IA32_MTRR_PHYSBASE0 0x00000200
+#define MSR_IA32_MTRR_PHYSBASE1 0x00000202
+#define MSR_IA32_MTRR_PHYSBASE2 0x00000204
+#define MSR_IA32_MTRR_PHYSBASE3 0x00000206
+#define MSR_IA32_MTRR_PHYSBASE4 0x00000208
+#define MSR_IA32_MTRR_PHYSBASE5 0x0000020A
+#define MSR_IA32_MTRR_PHYSBASE6 0x0000020C
+#define MSR_IA32_MTRR_PHYSBASE7 0x0000020E
+#define MSR_IA32_MTRR_PHYSBASE8 0x00000210
+#define MSR_IA32_MTRR_PHYSBASE9 0x00000212
/// @}
/**
@@ -2153,12 +2115,12 @@ typedef union {
///
/// [Bits 7:0] Type. Specifies memory type of the range.
///
- UINT32 Type:8;
- UINT32 Reserved1:4;
+ UINT32 Type : 8;
+ UINT32 Reserved1 : 4;
///
/// [Bits 31:12] PhysBase. MTRR physical Base Address.
///
- UINT32 PhysBase:20;
+ UINT32 PhysBase : 20;
///
/// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address.
/// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
@@ -2167,15 +2129,14 @@ typedef union {
/// leaf 80000008H, the processor supports 36-bit physical address size,
/// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
///
- UINT32 PhysBaseHi:32;
+ UINT32 PhysBaseHi : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_MTRR_PHYSBASE_REGISTER;
-
/**
MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs".
If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
@@ -2205,16 +2166,16 @@ typedef union {
MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.
@{
**/
-#define MSR_IA32_MTRR_PHYSMASK0 0x00000201
-#define MSR_IA32_MTRR_PHYSMASK1 0x00000203
-#define MSR_IA32_MTRR_PHYSMASK2 0x00000205
-#define MSR_IA32_MTRR_PHYSMASK3 0x00000207
-#define MSR_IA32_MTRR_PHYSMASK4 0x00000209
-#define MSR_IA32_MTRR_PHYSMASK5 0x0000020B
-#define MSR_IA32_MTRR_PHYSMASK6 0x0000020D
-#define MSR_IA32_MTRR_PHYSMASK7 0x0000020F
-#define MSR_IA32_MTRR_PHYSMASK8 0x00000211
-#define MSR_IA32_MTRR_PHYSMASK9 0x00000213
+#define MSR_IA32_MTRR_PHYSMASK0 0x00000201
+#define MSR_IA32_MTRR_PHYSMASK1 0x00000203
+#define MSR_IA32_MTRR_PHYSMASK2 0x00000205
+#define MSR_IA32_MTRR_PHYSMASK3 0x00000207
+#define MSR_IA32_MTRR_PHYSMASK4 0x00000209
+#define MSR_IA32_MTRR_PHYSMASK5 0x0000020B
+#define MSR_IA32_MTRR_PHYSMASK6 0x0000020D
+#define MSR_IA32_MTRR_PHYSMASK7 0x0000020F
+#define MSR_IA32_MTRR_PHYSMASK8 0x00000211
+#define MSR_IA32_MTRR_PHYSMASK9 0x00000213
/// @}
/**
@@ -2226,15 +2187,15 @@ typedef union {
/// Individual bit fields
///
struct {
- UINT32 Reserved1:11;
+ UINT32 Reserved1 : 11;
///
/// [Bit 11] Valid Enable range mask.
///
- UINT32 V:1;
+ UINT32 V : 1;
///
/// [Bits 31:12] PhysMask. MTRR address range mask.
///
- UINT32 PhysMask:20;
+ UINT32 PhysMask : 20;
///
/// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask.
/// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
@@ -2243,15 +2204,14 @@ typedef union {
/// leaf 80000008H, the processor supports 36-bit physical address size,
/// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
///
- UINT32 PhysMaskHi:32;
+ UINT32 PhysMaskHi : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_MTRR_PHYSMASK_REGISTER;
-
/**
MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.
@@ -2268,8 +2228,7 @@ typedef union {
@endcode
@note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM.
**/
-#define MSR_IA32_MTRR_FIX64K_00000 0x00000250
-
+#define MSR_IA32_MTRR_FIX64K_00000 0x00000250
/**
MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.
@@ -2287,8 +2246,7 @@ typedef union {
@endcode
@note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM.
**/
-#define MSR_IA32_MTRR_FIX16K_80000 0x00000258
-
+#define MSR_IA32_MTRR_FIX16K_80000 0x00000258
/**
MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.
@@ -2306,8 +2264,7 @@ typedef union {
@endcode
@note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM.
**/
-#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259
-
+#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259
/**
See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.
@@ -2325,8 +2282,7 @@ typedef union {
@endcode
@note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM.
**/
-#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268
-
+#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268
/**
MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.
@@ -2344,8 +2300,7 @@ typedef union {
@endcode
@note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM.
**/
-#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269
-
+#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269
/**
MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.
@@ -2363,8 +2318,7 @@ typedef union {
@endcode
@note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM.
**/
-#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A
-
+#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A
/**
MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.
@@ -2382,8 +2336,7 @@ typedef union {
@endcode
@note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM.
**/
-#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B
-
+#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B
/**
MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.
@@ -2401,8 +2354,7 @@ typedef union {
@endcode
@note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM.
**/
-#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C
-
+#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C
/**
MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.
@@ -2420,8 +2372,7 @@ typedef union {
@endcode
@note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM.
**/
-#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D
-
+#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D
/**
MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.
@@ -2439,8 +2390,7 @@ typedef union {
@endcode
@note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM.
**/
-#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E
-
+#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E
/**
MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.
@@ -2458,8 +2408,7 @@ typedef union {
@endcode
@note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM.
**/
-#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F
-
+#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F
/**
IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.
@@ -2479,7 +2428,7 @@ typedef union {
@endcode
@note MSR_IA32_PAT is defined as IA32_PAT in SDM.
**/
-#define MSR_IA32_PAT 0x00000277
+#define MSR_IA32_PAT 0x00000277
/**
MSR information returned for MSR index #MSR_IA32_PAT
@@ -2492,51 +2441,50 @@ typedef union {
///
/// [Bits 2:0] PA0.
///
- UINT32 PA0:3;
- UINT32 Reserved1:5;
+ UINT32 PA0 : 3;
+ UINT32 Reserved1 : 5;
///
/// [Bits 10:8] PA1.
///
- UINT32 PA1:3;
- UINT32 Reserved2:5;
+ UINT32 PA1 : 3;
+ UINT32 Reserved2 : 5;
///
/// [Bits 18:16] PA2.
///
- UINT32 PA2:3;
- UINT32 Reserved3:5;
+ UINT32 PA2 : 3;
+ UINT32 Reserved3 : 5;
///
/// [Bits 26:24] PA3.
///
- UINT32 PA3:3;
- UINT32 Reserved4:5;
+ UINT32 PA3 : 3;
+ UINT32 Reserved4 : 5;
///
/// [Bits 34:32] PA4.
///
- UINT32 PA4:3;
- UINT32 Reserved5:5;
+ UINT32 PA4 : 3;
+ UINT32 Reserved5 : 5;
///
/// [Bits 42:40] PA5.
///
- UINT32 PA5:3;
- UINT32 Reserved6:5;
+ UINT32 PA5 : 3;
+ UINT32 Reserved6 : 5;
///
/// [Bits 50:48] PA6.
///
- UINT32 PA6:3;
- UINT32 Reserved7:5;
+ UINT32 PA6 : 3;
+ UINT32 Reserved7 : 5;
///
/// [Bits 58:56] PA7.
///
- UINT32 PA7:3;
- UINT32 Reserved8:5;
+ UINT32 PA7 : 3;
+ UINT32 Reserved8 : 5;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PAT_REGISTER;
-
/**
Provides the programming interface to use corrected MC error signaling
capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.
@@ -2588,38 +2536,38 @@ typedef union {
MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.
@{
**/
-#define MSR_IA32_MC0_CTL2 0x00000280
-#define MSR_IA32_MC1_CTL2 0x00000281
-#define MSR_IA32_MC2_CTL2 0x00000282
-#define MSR_IA32_MC3_CTL2 0x00000283
-#define MSR_IA32_MC4_CTL2 0x00000284
-#define MSR_IA32_MC5_CTL2 0x00000285
-#define MSR_IA32_MC6_CTL2 0x00000286
-#define MSR_IA32_MC7_CTL2 0x00000287
-#define MSR_IA32_MC8_CTL2 0x00000288
-#define MSR_IA32_MC9_CTL2 0x00000289
-#define MSR_IA32_MC10_CTL2 0x0000028A
-#define MSR_IA32_MC11_CTL2 0x0000028B
-#define MSR_IA32_MC12_CTL2 0x0000028C
-#define MSR_IA32_MC13_CTL2 0x0000028D
-#define MSR_IA32_MC14_CTL2 0x0000028E
-#define MSR_IA32_MC15_CTL2 0x0000028F
-#define MSR_IA32_MC16_CTL2 0x00000290
-#define MSR_IA32_MC17_CTL2 0x00000291
-#define MSR_IA32_MC18_CTL2 0x00000292
-#define MSR_IA32_MC19_CTL2 0x00000293
-#define MSR_IA32_MC20_CTL2 0x00000294
-#define MSR_IA32_MC21_CTL2 0x00000295
-#define MSR_IA32_MC22_CTL2 0x00000296
-#define MSR_IA32_MC23_CTL2 0x00000297
-#define MSR_IA32_MC24_CTL2 0x00000298
-#define MSR_IA32_MC25_CTL2 0x00000299
-#define MSR_IA32_MC26_CTL2 0x0000029A
-#define MSR_IA32_MC27_CTL2 0x0000029B
-#define MSR_IA32_MC28_CTL2 0x0000029C
-#define MSR_IA32_MC29_CTL2 0x0000029D
-#define MSR_IA32_MC30_CTL2 0x0000029E
-#define MSR_IA32_MC31_CTL2 0x0000029F
+#define MSR_IA32_MC0_CTL2 0x00000280
+#define MSR_IA32_MC1_CTL2 0x00000281
+#define MSR_IA32_MC2_CTL2 0x00000282
+#define MSR_IA32_MC3_CTL2 0x00000283
+#define MSR_IA32_MC4_CTL2 0x00000284
+#define MSR_IA32_MC5_CTL2 0x00000285
+#define MSR_IA32_MC6_CTL2 0x00000286
+#define MSR_IA32_MC7_CTL2 0x00000287
+#define MSR_IA32_MC8_CTL2 0x00000288
+#define MSR_IA32_MC9_CTL2 0x00000289
+#define MSR_IA32_MC10_CTL2 0x0000028A
+#define MSR_IA32_MC11_CTL2 0x0000028B
+#define MSR_IA32_MC12_CTL2 0x0000028C
+#define MSR_IA32_MC13_CTL2 0x0000028D
+#define MSR_IA32_MC14_CTL2 0x0000028E
+#define MSR_IA32_MC15_CTL2 0x0000028F
+#define MSR_IA32_MC16_CTL2 0x00000290
+#define MSR_IA32_MC17_CTL2 0x00000291
+#define MSR_IA32_MC18_CTL2 0x00000292
+#define MSR_IA32_MC19_CTL2 0x00000293
+#define MSR_IA32_MC20_CTL2 0x00000294
+#define MSR_IA32_MC21_CTL2 0x00000295
+#define MSR_IA32_MC22_CTL2 0x00000296
+#define MSR_IA32_MC23_CTL2 0x00000297
+#define MSR_IA32_MC24_CTL2 0x00000298
+#define MSR_IA32_MC25_CTL2 0x00000299
+#define MSR_IA32_MC26_CTL2 0x0000029A
+#define MSR_IA32_MC27_CTL2 0x0000029B
+#define MSR_IA32_MC28_CTL2 0x0000029C
+#define MSR_IA32_MC29_CTL2 0x0000029D
+#define MSR_IA32_MC30_CTL2 0x0000029E
+#define MSR_IA32_MC31_CTL2 0x0000029F
/// @}
/**
@@ -2634,26 +2582,25 @@ typedef union {
///
/// [Bits 14:0] Corrected error count threshold.
///
- UINT32 CorrectedErrorCountThreshold:15;
- UINT32 Reserved1:15;
+ UINT32 CorrectedErrorCountThreshold : 15;
+ UINT32 Reserved1 : 15;
///
/// [Bit 30] CMCI_EN.
///
- UINT32 CMCI_EN:1;
- UINT32 Reserved2:1;
- UINT32 Reserved3:32;
+ UINT32 CMCI_EN : 1;
+ UINT32 Reserved2 : 1;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_MC_CTL2_REGISTER;
-
/**
MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.
@@ -2672,7 +2619,7 @@ typedef union {
@endcode
@note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM.
**/
-#define MSR_IA32_MTRR_DEF_TYPE 0x000002FF
+#define MSR_IA32_MTRR_DEF_TYPE 0x000002FF
/**
MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE
@@ -2685,30 +2632,29 @@ typedef union {
///
/// [Bits 2:0] Default Memory Type.
///
- UINT32 Type:3;
- UINT32 Reserved1:7;
+ UINT32 Type : 3;
+ UINT32 Reserved1 : 7;
///
/// [Bit 10] Fixed Range MTRR Enable.
///
- UINT32 FE:1;
+ UINT32 FE : 1;
///
/// [Bit 11] MTRR Enable.
///
- UINT32 E:1;
- UINT32 Reserved2:20;
- UINT32 Reserved3:32;
+ UINT32 E : 1;
+ UINT32 Reserved2 : 20;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_MTRR_DEF_TYPE_REGISTER;
-
/**
Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If
CPUID.0AH: EDX[4:0] > 0.
@@ -2726,8 +2672,7 @@ typedef union {
@endcode
@note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM.
**/
-#define MSR_IA32_FIXED_CTR0 0x00000309
-
+#define MSR_IA32_FIXED_CTR0 0x00000309
/**
Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If
@@ -2746,8 +2691,7 @@ typedef union {
@endcode
@note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM.
**/
-#define MSR_IA32_FIXED_CTR1 0x0000030A
-
+#define MSR_IA32_FIXED_CTR1 0x0000030A
/**
Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If
@@ -2766,8 +2710,7 @@ typedef union {
@endcode
@note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM.
**/
-#define MSR_IA32_FIXED_CTR2 0x0000030B
-
+#define MSR_IA32_FIXED_CTR2 0x0000030B
/**
RO. If CPUID.01H: ECX[15] = 1.
@@ -2787,7 +2730,7 @@ typedef union {
@endcode
@note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM.
**/
-#define MSR_IA32_PERF_CAPABILITIES 0x00000345
+#define MSR_IA32_PERF_CAPABILITIES 0x00000345
/**
MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES
@@ -2800,41 +2743,40 @@ typedef union {
///
/// [Bits 5:0] LBR format.
///
- UINT32 LBR_FMT:6;
+ UINT32 LBR_FMT : 6;
///
/// [Bit 6] PEBS Trap.
///
- UINT32 PEBS_TRAP:1;
+ UINT32 PEBS_TRAP : 1;
///
/// [Bit 7] PEBSSaveArchRegs.
///
- UINT32 PEBS_ARCH_REG:1;
+ UINT32 PEBS_ARCH_REG : 1;
///
/// [Bits 11:8] PEBS Record Format.
///
- UINT32 PEBS_REC_FMT:4;
+ UINT32 PEBS_REC_FMT : 4;
///
/// [Bit 12] 1: Freeze while SMM is supported.
///
- UINT32 SMM_FREEZE:1;
+ UINT32 SMM_FREEZE : 1;
///
/// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx.
///
- UINT32 FW_WRITE:1;
- UINT32 Reserved1:18;
- UINT32 Reserved2:32;
+ UINT32 FW_WRITE : 1;
+ UINT32 Reserved1 : 18;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PERF_CAPABILITIES_REGISTER;
-
/**
Fixed-Function Performance Counter Control (R/W) Counter increments while
the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with
@@ -2856,7 +2798,7 @@ typedef union {
@endcode
@note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM.
**/
-#define MSR_IA32_FIXED_CTR_CTRL 0x0000038D
+#define MSR_IA32_FIXED_CTR_CTRL 0x0000038D
/**
MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL
@@ -2869,11 +2811,11 @@ typedef union {
///
/// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.
///
- UINT32 EN0_OS:1;
+ UINT32 EN0_OS : 1;
///
/// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.
///
- UINT32 EN0_Usr:1;
+ UINT32 EN0_Usr : 1;
///
/// [Bit 2] AnyThread: When set to 1, it enables counting the associated
/// event conditions occurring across all logical processors sharing a
@@ -2881,19 +2823,19 @@ typedef union {
/// associated event conditions occurring in the logical processor which
/// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
///
- UINT32 AnyThread0:1;
+ UINT32 AnyThread0 : 1;
///
/// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.
///
- UINT32 EN0_PMI:1;
+ UINT32 EN0_PMI : 1;
///
/// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.
///
- UINT32 EN1_OS:1;
+ UINT32 EN1_OS : 1;
///
/// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.
///
- UINT32 EN1_Usr:1;
+ UINT32 EN1_Usr : 1;
///
/// [Bit 6] AnyThread: When set to 1, it enables counting the associated
/// event conditions occurring across all logical processors sharing a
@@ -2901,19 +2843,19 @@ typedef union {
/// associated event conditions occurring in the logical processor which
/// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
///
- UINT32 AnyThread1:1;
+ UINT32 AnyThread1 : 1;
///
/// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.
///
- UINT32 EN1_PMI:1;
+ UINT32 EN1_PMI : 1;
///
/// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.
///
- UINT32 EN2_OS:1;
+ UINT32 EN2_OS : 1;
///
/// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.
///
- UINT32 EN2_Usr:1;
+ UINT32 EN2_Usr : 1;
///
/// [Bit 10] AnyThread: When set to 1, it enables counting the associated
/// event conditions occurring across all logical processors sharing a
@@ -2921,25 +2863,24 @@ typedef union {
/// associated event conditions occurring in the logical processor which
/// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
///
- UINT32 AnyThread2:1;
+ UINT32 AnyThread2 : 1;
///
/// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.
///
- UINT32 EN2_PMI:1;
- UINT32 Reserved1:20;
- UINT32 Reserved2:32;
+ UINT32 EN2_PMI : 1;
+ UINT32 Reserved1 : 20;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_FIXED_CTR_CTRL_REGISTER;
-
/**
Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.
@@ -2957,7 +2898,7 @@ typedef union {
@endcode
@note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
**/
-#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E
+#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E
/**
MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS
@@ -2971,87 +2912,86 @@ typedef union {
/// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH:
/// EAX[15:8] > 0.
///
- UINT32 Ovf_PMC0:1;
+ UINT32 Ovf_PMC0 : 1;
///
/// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH:
/// EAX[15:8] > 1.
///
- UINT32 Ovf_PMC1:1;
+ UINT32 Ovf_PMC1 : 1;
///
/// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH:
/// EAX[15:8] > 2.
///
- UINT32 Ovf_PMC2:1;
+ UINT32 Ovf_PMC2 : 1;
///
/// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH:
/// EAX[15:8] > 3.
///
- UINT32 Ovf_PMC3:1;
- UINT32 Reserved1:28;
+ UINT32 Ovf_PMC3 : 1;
+ UINT32 Reserved1 : 28;
///
/// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If
/// CPUID.0AH: EAX[7:0] > 1.
///
- UINT32 Ovf_FixedCtr0:1;
+ UINT32 Ovf_FixedCtr0 : 1;
///
/// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If
/// CPUID.0AH: EAX[7:0] > 1.
///
- UINT32 Ovf_FixedCtr1:1;
+ UINT32 Ovf_FixedCtr1 : 1;
///
/// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If
/// CPUID.0AH: EAX[7:0] > 1.
///
- UINT32 Ovf_FixedCtr2:1;
- UINT32 Reserved2:20;
+ UINT32 Ovf_FixedCtr2 : 1;
+ UINT32 Reserved2 : 20;
///
/// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory
/// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
/// && IA32_RTIT_CTL.ToPA = 1.
///
- UINT32 Trace_ToPA_PMI:1;
- UINT32 Reserved3:2;
+ UINT32 Trace_ToPA_PMI : 1;
+ UINT32 Reserved3 : 2;
///
/// [Bit 58] LBR_Frz: LBRs are frozen due to -
/// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If
/// CPUID.0AH: EAX[7:0] > 3.
///
- UINT32 LBR_Frz:1;
+ UINT32 LBR_Frz : 1;
///
/// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due
/// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU
/// counters overflowed. If CPUID.0AH: EAX[7:0] > 3.
///
- UINT32 CTR_Frz:1;
+ UINT32 CTR_Frz : 1;
///
/// [Bit 60] ASCI: Data in the performance counters in the core PMU may
/// include contributions from the direct or indirect operation intel SGX
/// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.
///
- UINT32 ASCI:1;
+ UINT32 ASCI : 1;
///
/// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH:
/// EAX[7:0] > 2.
///
- UINT32 Ovf_Uncore:1;
+ UINT32 Ovf_Uncore : 1;
///
/// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH:
/// EAX[7:0] > 0.
///
- UINT32 OvfBuf:1;
+ UINT32 OvfBuf : 1;
///
/// [Bit 63] CondChgd: status bits of this register has changed. If
/// CPUID.0AH: EAX[7:0] > 0.
///
- UINT32 CondChgd:1;
+ UINT32 CondChgd : 1;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PERF_GLOBAL_STATUS_REGISTER;
-
/**
Global Performance Counter Control (R/W) Counter increments while the result
of ANDing respective enable bit in this MSR with the corresponding OS or USR
@@ -3073,7 +3013,7 @@ typedef union {
@endcode
@note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.
**/
-#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F
+#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F
/**
MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL
@@ -3081,28 +3021,27 @@ typedef union {
typedef union {
///
/// Individual bit fields
-///
+ ///
struct {
///
/// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n.
/// Enable bitmask. Only the first n-1 bits are valid.
/// Bits n..31 are reserved.
///
- UINT32 EN_PMCn:32;
+ UINT32 EN_PMCn : 32;
///
/// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n.
/// Enable bitmask. Only the first n-1 bits are valid.
/// Bits 31:n are reserved.
///
- UINT32 EN_FIXED_CTRn:32;
+ UINT32 EN_FIXED_CTRn : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PERF_GLOBAL_CTRL_REGISTER;
-
/**
Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] >
0 && CPUID.0AH: EAX[7:0] <= 3.
@@ -3122,7 +3061,7 @@ typedef union {
@endcode
@note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.
**/
-#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
+#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
/**
MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL
@@ -3137,41 +3076,40 @@ typedef union {
/// Clear bitmask. Only the first n-1 bits are valid.
/// Bits 31:n are reserved.
///
- UINT32 Ovf_PMCn:32;
+ UINT32 Ovf_PMCn : 32;
///
/// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
/// If CPUID.0AH: EDX[4:0] > n.
/// Clear bitmask. Only the first n-1 bits are valid.
/// Bits 22:n are reserved.
///
- UINT32 Ovf_FIXED_CTRn:23;
+ UINT32 Ovf_FIXED_CTRn : 23;
///
/// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
/// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.
///
- UINT32 Trace_ToPA_PMI:1;
- UINT32 Reserved2:5;
+ UINT32 Trace_ToPA_PMI : 1;
+ UINT32 Reserved2 : 5;
///
/// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
/// Display Model 06_2EH.
///
- UINT32 Ovf_Uncore:1;
+ UINT32 Ovf_Uncore : 1;
///
/// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
///
- UINT32 OvfBuf:1;
+ UINT32 OvfBuf : 1;
///
/// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
///
- UINT32 CondChgd:1;
+ UINT32 CondChgd : 1;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;
-
/**
Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH:
EAX[7:0] > 3.
@@ -3191,7 +3129,7 @@ typedef union {
@endcode
@note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
**/
-#define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
+#define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
/**
MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET
@@ -3206,53 +3144,52 @@ typedef union {
/// Clear bitmask. Only the first n-1 bits are valid.
/// Bits 31:n are reserved.
///
- UINT32 Ovf_PMCn:32;
+ UINT32 Ovf_PMCn : 32;
///
/// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
/// If CPUID.0AH: EDX[4:0] > n.
/// Clear bitmask. Only the first n-1 bits are valid.
/// Bits 22:n are reserved.
///
- UINT32 Ovf_FIXED_CTRn:23;
+ UINT32 Ovf_FIXED_CTRn : 23;
///
/// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
/// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.
///
- UINT32 Trace_ToPA_PMI:1;
- UINT32 Reserved2:2;
+ UINT32 Trace_ToPA_PMI : 1;
+ UINT32 Reserved2 : 2;
///
/// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
///
- UINT32 LBR_Frz:1;
+ UINT32 LBR_Frz : 1;
///
/// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
///
- UINT32 CTR_Frz:1;
+ UINT32 CTR_Frz : 1;
///
/// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.
///
- UINT32 ASCI:1;
+ UINT32 ASCI : 1;
///
/// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
/// Display Model 06_2EH.
///
- UINT32 Ovf_Uncore:1;
+ UINT32 Ovf_Uncore : 1;
///
/// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
///
- UINT32 OvfBuf:1;
+ UINT32 OvfBuf : 1;
///
/// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
///
- UINT32 CondChgd:1;
+ UINT32 CondChgd : 1;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;
-
/**
Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH:
EAX[7:0] > 3.
@@ -3272,7 +3209,7 @@ typedef union {
@endcode
@note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
**/
-#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
+#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
/**
MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET
@@ -3287,48 +3224,47 @@ typedef union {
/// Set bitmask. Only the first n-1 bits are valid.
/// Bits 31:n are reserved.
///
- UINT32 Ovf_PMCn:32;
+ UINT32 Ovf_PMCn : 32;
///
/// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1.
/// If CPUID.0AH: EAX[7:0] > n.
/// Set bitmask. Only the first n-1 bits are valid.
/// Bits 22:n are reserved.
///
- UINT32 Ovf_FIXED_CTRn:23;
+ UINT32 Ovf_FIXED_CTRn : 23;
///
/// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.
///
- UINT32 Trace_ToPA_PMI:1;
- UINT32 Reserved2:2;
+ UINT32 Trace_ToPA_PMI : 1;
+ UINT32 Reserved2 : 2;
///
/// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
///
- UINT32 LBR_Frz:1;
+ UINT32 LBR_Frz : 1;
///
/// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
///
- UINT32 CTR_Frz:1;
+ UINT32 CTR_Frz : 1;
///
/// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.
///
- UINT32 ASCI:1;
+ UINT32 ASCI : 1;
///
/// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.
///
- UINT32 Ovf_Uncore:1;
+ UINT32 Ovf_Uncore : 1;
///
/// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.
///
- UINT32 OvfBuf:1;
- UINT32 Reserved3:1;
+ UINT32 OvfBuf : 1;
+ UINT32 Reserved3 : 1;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;
-
/**
Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] >
3.
@@ -3347,7 +3283,7 @@ typedef union {
@endcode
@note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM.
**/
-#define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392
+#define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392
/**
MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE
@@ -3362,26 +3298,25 @@ typedef union {
/// Status bitmask. Only the first n-1 bits are valid.
/// Bits 31:n are reserved.
///
- UINT32 IA32_PERFEVTSELn:32;
+ UINT32 IA32_PERFEVTSELn : 32;
///
/// [Bits 62:32] IA32_FIXED_CTRn in use.
/// If CPUID.0AH: EAX[7:0] > n.
/// Status bitmask. Only the first n-1 bits are valid.
/// Bits 30:n are reserved.
///
- UINT32 IA32_FIXED_CTRn:31;
+ UINT32 IA32_FIXED_CTRn : 31;
///
/// [Bit 63] PMI in use.
///
- UINT32 PMI:1;
+ UINT32 PMI : 1;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PERF_GLOBAL_INUSE_REGISTER;
-
/**
PEBS Control (R/W).
@@ -3400,7 +3335,7 @@ typedef union {
@endcode
@note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM.
**/
-#define MSR_IA32_PEBS_ENABLE 0x000003F1
+#define MSR_IA32_PEBS_ENABLE 0x000003F1
/**
MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE
@@ -3414,25 +3349,24 @@ typedef union {
/// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family /
/// Display Model 06_0FH.
///
- UINT32 Enable:1;
+ UINT32 Enable : 1;
///
/// [Bits 3:1] Reserved or Model specific.
///
- UINT32 Reserved1:3;
- UINT32 Reserved2:28;
+ UINT32 Reserved1 : 3;
+ UINT32 Reserved2 : 28;
///
/// [Bits 35:32] Reserved or Model specific.
///
- UINT32 Reserved3:4;
- UINT32 Reserved4:28;
+ UINT32 Reserved3 : 4;
+ UINT32 Reserved4 : 28;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PEBS_ENABLE_REGISTER;
-
/**
MCn_CTL. If IA32_MCG_CAP.CNT > n.
@@ -3478,38 +3412,37 @@ typedef union {
MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.
@{
**/
-#define MSR_IA32_MC0_CTL 0x00000400
-#define MSR_IA32_MC1_CTL 0x00000404
-#define MSR_IA32_MC2_CTL 0x00000408
-#define MSR_IA32_MC3_CTL 0x0000040C
-#define MSR_IA32_MC4_CTL 0x00000410
-#define MSR_IA32_MC5_CTL 0x00000414
-#define MSR_IA32_MC6_CTL 0x00000418
-#define MSR_IA32_MC7_CTL 0x0000041C
-#define MSR_IA32_MC8_CTL 0x00000420
-#define MSR_IA32_MC9_CTL 0x00000424
-#define MSR_IA32_MC10_CTL 0x00000428
-#define MSR_IA32_MC11_CTL 0x0000042C
-#define MSR_IA32_MC12_CTL 0x00000430
-#define MSR_IA32_MC13_CTL 0x00000434
-#define MSR_IA32_MC14_CTL 0x00000438
-#define MSR_IA32_MC15_CTL 0x0000043C
-#define MSR_IA32_MC16_CTL 0x00000440
-#define MSR_IA32_MC17_CTL 0x00000444
-#define MSR_IA32_MC18_CTL 0x00000448
-#define MSR_IA32_MC19_CTL 0x0000044C
-#define MSR_IA32_MC20_CTL 0x00000450
-#define MSR_IA32_MC21_CTL 0x00000454
-#define MSR_IA32_MC22_CTL 0x00000458
-#define MSR_IA32_MC23_CTL 0x0000045C
-#define MSR_IA32_MC24_CTL 0x00000460
-#define MSR_IA32_MC25_CTL 0x00000464
-#define MSR_IA32_MC26_CTL 0x00000468
-#define MSR_IA32_MC27_CTL 0x0000046C
-#define MSR_IA32_MC28_CTL 0x00000470
+#define MSR_IA32_MC0_CTL 0x00000400
+#define MSR_IA32_MC1_CTL 0x00000404
+#define MSR_IA32_MC2_CTL 0x00000408
+#define MSR_IA32_MC3_CTL 0x0000040C
+#define MSR_IA32_MC4_CTL 0x00000410
+#define MSR_IA32_MC5_CTL 0x00000414
+#define MSR_IA32_MC6_CTL 0x00000418
+#define MSR_IA32_MC7_CTL 0x0000041C
+#define MSR_IA32_MC8_CTL 0x00000420
+#define MSR_IA32_MC9_CTL 0x00000424
+#define MSR_IA32_MC10_CTL 0x00000428
+#define MSR_IA32_MC11_CTL 0x0000042C
+#define MSR_IA32_MC12_CTL 0x00000430
+#define MSR_IA32_MC13_CTL 0x00000434
+#define MSR_IA32_MC14_CTL 0x00000438
+#define MSR_IA32_MC15_CTL 0x0000043C
+#define MSR_IA32_MC16_CTL 0x00000440
+#define MSR_IA32_MC17_CTL 0x00000444
+#define MSR_IA32_MC18_CTL 0x00000448
+#define MSR_IA32_MC19_CTL 0x0000044C
+#define MSR_IA32_MC20_CTL 0x00000450
+#define MSR_IA32_MC21_CTL 0x00000454
+#define MSR_IA32_MC22_CTL 0x00000458
+#define MSR_IA32_MC23_CTL 0x0000045C
+#define MSR_IA32_MC24_CTL 0x00000460
+#define MSR_IA32_MC25_CTL 0x00000464
+#define MSR_IA32_MC26_CTL 0x00000468
+#define MSR_IA32_MC27_CTL 0x0000046C
+#define MSR_IA32_MC28_CTL 0x00000470
/// @}
-
/**
MCn_STATUS. If IA32_MCG_CAP.CNT > n.
@@ -3555,38 +3488,37 @@ typedef union {
MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.
@{
**/
-#define MSR_IA32_MC0_STATUS 0x00000401
-#define MSR_IA32_MC1_STATUS 0x00000405
-#define MSR_IA32_MC2_STATUS 0x00000409
-#define MSR_IA32_MC3_STATUS 0x0000040D
-#define MSR_IA32_MC4_STATUS 0x00000411
-#define MSR_IA32_MC5_STATUS 0x00000415
-#define MSR_IA32_MC6_STATUS 0x00000419
-#define MSR_IA32_MC7_STATUS 0x0000041D
-#define MSR_IA32_MC8_STATUS 0x00000421
-#define MSR_IA32_MC9_STATUS 0x00000425
-#define MSR_IA32_MC10_STATUS 0x00000429
-#define MSR_IA32_MC11_STATUS 0x0000042D
-#define MSR_IA32_MC12_STATUS 0x00000431
-#define MSR_IA32_MC13_STATUS 0x00000435
-#define MSR_IA32_MC14_STATUS 0x00000439
-#define MSR_IA32_MC15_STATUS 0x0000043D
-#define MSR_IA32_MC16_STATUS 0x00000441
-#define MSR_IA32_MC17_STATUS 0x00000445
-#define MSR_IA32_MC18_STATUS 0x00000449
-#define MSR_IA32_MC19_STATUS 0x0000044D
-#define MSR_IA32_MC20_STATUS 0x00000451
-#define MSR_IA32_MC21_STATUS 0x00000455
-#define MSR_IA32_MC22_STATUS 0x00000459
-#define MSR_IA32_MC23_STATUS 0x0000045D
-#define MSR_IA32_MC24_STATUS 0x00000461
-#define MSR_IA32_MC25_STATUS 0x00000465
-#define MSR_IA32_MC26_STATUS 0x00000469
-#define MSR_IA32_MC27_STATUS 0x0000046D
-#define MSR_IA32_MC28_STATUS 0x00000471
+#define MSR_IA32_MC0_STATUS 0x00000401
+#define MSR_IA32_MC1_STATUS 0x00000405
+#define MSR_IA32_MC2_STATUS 0x00000409
+#define MSR_IA32_MC3_STATUS 0x0000040D
+#define MSR_IA32_MC4_STATUS 0x00000411
+#define MSR_IA32_MC5_STATUS 0x00000415
+#define MSR_IA32_MC6_STATUS 0x00000419
+#define MSR_IA32_MC7_STATUS 0x0000041D
+#define MSR_IA32_MC8_STATUS 0x00000421
+#define MSR_IA32_MC9_STATUS 0x00000425
+#define MSR_IA32_MC10_STATUS 0x00000429
+#define MSR_IA32_MC11_STATUS 0x0000042D
+#define MSR_IA32_MC12_STATUS 0x00000431
+#define MSR_IA32_MC13_STATUS 0x00000435
+#define MSR_IA32_MC14_STATUS 0x00000439
+#define MSR_IA32_MC15_STATUS 0x0000043D
+#define MSR_IA32_MC16_STATUS 0x00000441
+#define MSR_IA32_MC17_STATUS 0x00000445
+#define MSR_IA32_MC18_STATUS 0x00000449
+#define MSR_IA32_MC19_STATUS 0x0000044D
+#define MSR_IA32_MC20_STATUS 0x00000451
+#define MSR_IA32_MC21_STATUS 0x00000455
+#define MSR_IA32_MC22_STATUS 0x00000459
+#define MSR_IA32_MC23_STATUS 0x0000045D
+#define MSR_IA32_MC24_STATUS 0x00000461
+#define MSR_IA32_MC25_STATUS 0x00000465
+#define MSR_IA32_MC26_STATUS 0x00000469
+#define MSR_IA32_MC27_STATUS 0x0000046D
+#define MSR_IA32_MC28_STATUS 0x00000471
/// @}
-
/**
MCn_ADDR. If IA32_MCG_CAP.CNT > n.
@@ -3632,38 +3564,37 @@ typedef union {
MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.
@{
**/
-#define MSR_IA32_MC0_ADDR 0x00000402
-#define MSR_IA32_MC1_ADDR 0x00000406
-#define MSR_IA32_MC2_ADDR 0x0000040A
-#define MSR_IA32_MC3_ADDR 0x0000040E
-#define MSR_IA32_MC4_ADDR 0x00000412
-#define MSR_IA32_MC5_ADDR 0x00000416
-#define MSR_IA32_MC6_ADDR 0x0000041A
-#define MSR_IA32_MC7_ADDR 0x0000041E
-#define MSR_IA32_MC8_ADDR 0x00000422
-#define MSR_IA32_MC9_ADDR 0x00000426
-#define MSR_IA32_MC10_ADDR 0x0000042A
-#define MSR_IA32_MC11_ADDR 0x0000042E
-#define MSR_IA32_MC12_ADDR 0x00000432
-#define MSR_IA32_MC13_ADDR 0x00000436
-#define MSR_IA32_MC14_ADDR 0x0000043A
-#define MSR_IA32_MC15_ADDR 0x0000043E
-#define MSR_IA32_MC16_ADDR 0x00000442
-#define MSR_IA32_MC17_ADDR 0x00000446
-#define MSR_IA32_MC18_ADDR 0x0000044A
-#define MSR_IA32_MC19_ADDR 0x0000044E
-#define MSR_IA32_MC20_ADDR 0x00000452
-#define MSR_IA32_MC21_ADDR 0x00000456
-#define MSR_IA32_MC22_ADDR 0x0000045A
-#define MSR_IA32_MC23_ADDR 0x0000045E
-#define MSR_IA32_MC24_ADDR 0x00000462
-#define MSR_IA32_MC25_ADDR 0x00000466
-#define MSR_IA32_MC26_ADDR 0x0000046A
-#define MSR_IA32_MC27_ADDR 0x0000046E
-#define MSR_IA32_MC28_ADDR 0x00000472
+#define MSR_IA32_MC0_ADDR 0x00000402
+#define MSR_IA32_MC1_ADDR 0x00000406
+#define MSR_IA32_MC2_ADDR 0x0000040A
+#define MSR_IA32_MC3_ADDR 0x0000040E
+#define MSR_IA32_MC4_ADDR 0x00000412
+#define MSR_IA32_MC5_ADDR 0x00000416
+#define MSR_IA32_MC6_ADDR 0x0000041A
+#define MSR_IA32_MC7_ADDR 0x0000041E
+#define MSR_IA32_MC8_ADDR 0x00000422
+#define MSR_IA32_MC9_ADDR 0x00000426
+#define MSR_IA32_MC10_ADDR 0x0000042A
+#define MSR_IA32_MC11_ADDR 0x0000042E
+#define MSR_IA32_MC12_ADDR 0x00000432
+#define MSR_IA32_MC13_ADDR 0x00000436
+#define MSR_IA32_MC14_ADDR 0x0000043A
+#define MSR_IA32_MC15_ADDR 0x0000043E
+#define MSR_IA32_MC16_ADDR 0x00000442
+#define MSR_IA32_MC17_ADDR 0x00000446
+#define MSR_IA32_MC18_ADDR 0x0000044A
+#define MSR_IA32_MC19_ADDR 0x0000044E
+#define MSR_IA32_MC20_ADDR 0x00000452
+#define MSR_IA32_MC21_ADDR 0x00000456
+#define MSR_IA32_MC22_ADDR 0x0000045A
+#define MSR_IA32_MC23_ADDR 0x0000045E
+#define MSR_IA32_MC24_ADDR 0x00000462
+#define MSR_IA32_MC25_ADDR 0x00000466
+#define MSR_IA32_MC26_ADDR 0x0000046A
+#define MSR_IA32_MC27_ADDR 0x0000046E
+#define MSR_IA32_MC28_ADDR 0x00000472
/// @}
-
/**
MCn_MISC. If IA32_MCG_CAP.CNT > n.
@@ -3709,38 +3640,37 @@ typedef union {
MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.
@{
**/
-#define MSR_IA32_MC0_MISC 0x00000403
-#define MSR_IA32_MC1_MISC 0x00000407
-#define MSR_IA32_MC2_MISC 0x0000040B
-#define MSR_IA32_MC3_MISC 0x0000040F
-#define MSR_IA32_MC4_MISC 0x00000413
-#define MSR_IA32_MC5_MISC 0x00000417
-#define MSR_IA32_MC6_MISC 0x0000041B
-#define MSR_IA32_MC7_MISC 0x0000041F
-#define MSR_IA32_MC8_MISC 0x00000423
-#define MSR_IA32_MC9_MISC 0x00000427
-#define MSR_IA32_MC10_MISC 0x0000042B
-#define MSR_IA32_MC11_MISC 0x0000042F
-#define MSR_IA32_MC12_MISC 0x00000433
-#define MSR_IA32_MC13_MISC 0x00000437
-#define MSR_IA32_MC14_MISC 0x0000043B
-#define MSR_IA32_MC15_MISC 0x0000043F
-#define MSR_IA32_MC16_MISC 0x00000443
-#define MSR_IA32_MC17_MISC 0x00000447
-#define MSR_IA32_MC18_MISC 0x0000044B
-#define MSR_IA32_MC19_MISC 0x0000044F
-#define MSR_IA32_MC20_MISC 0x00000453
-#define MSR_IA32_MC21_MISC 0x00000457
-#define MSR_IA32_MC22_MISC 0x0000045B
-#define MSR_IA32_MC23_MISC 0x0000045F
-#define MSR_IA32_MC24_MISC 0x00000463
-#define MSR_IA32_MC25_MISC 0x00000467
-#define MSR_IA32_MC26_MISC 0x0000046B
-#define MSR_IA32_MC27_MISC 0x0000046F
-#define MSR_IA32_MC28_MISC 0x00000473
+#define MSR_IA32_MC0_MISC 0x00000403
+#define MSR_IA32_MC1_MISC 0x00000407
+#define MSR_IA32_MC2_MISC 0x0000040B
+#define MSR_IA32_MC3_MISC 0x0000040F
+#define MSR_IA32_MC4_MISC 0x00000413
+#define MSR_IA32_MC5_MISC 0x00000417
+#define MSR_IA32_MC6_MISC 0x0000041B
+#define MSR_IA32_MC7_MISC 0x0000041F
+#define MSR_IA32_MC8_MISC 0x00000423
+#define MSR_IA32_MC9_MISC 0x00000427
+#define MSR_IA32_MC10_MISC 0x0000042B
+#define MSR_IA32_MC11_MISC 0x0000042F
+#define MSR_IA32_MC12_MISC 0x00000433
+#define MSR_IA32_MC13_MISC 0x00000437
+#define MSR_IA32_MC14_MISC 0x0000043B
+#define MSR_IA32_MC15_MISC 0x0000043F
+#define MSR_IA32_MC16_MISC 0x00000443
+#define MSR_IA32_MC17_MISC 0x00000447
+#define MSR_IA32_MC18_MISC 0x0000044B
+#define MSR_IA32_MC19_MISC 0x0000044F
+#define MSR_IA32_MC20_MISC 0x00000453
+#define MSR_IA32_MC21_MISC 0x00000457
+#define MSR_IA32_MC22_MISC 0x0000045B
+#define MSR_IA32_MC23_MISC 0x0000045F
+#define MSR_IA32_MC24_MISC 0x00000463
+#define MSR_IA32_MC25_MISC 0x00000467
+#define MSR_IA32_MC26_MISC 0x0000046B
+#define MSR_IA32_MC27_MISC 0x0000046F
+#define MSR_IA32_MC28_MISC 0x00000473
/// @}
-
/**
Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic
VMX Information.". If CPUID.01H:ECX.[5] = 1.
@@ -3757,7 +3687,7 @@ typedef union {
@endcode
@note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.
**/
-#define MSR_IA32_VMX_BASIC 0x00000480
+#define MSR_IA32_VMX_BASIC 0x00000480
/**
MSR information returned for MSR index #MSR_IA32_VMX_BASIC
@@ -3777,15 +3707,15 @@ typedef union {
/// processors produced prior to this change, bit 31 of this MSR was read
/// as 0.
///
- UINT32 VmcsRevisonId:31;
- UINT32 MustBeZero:1;
+ UINT32 VmcsRevisonId : 31;
+ UINT32 MustBeZero : 1;
///
/// [Bit 44:32] Reports the number of bytes that software should allocate
/// for the VMXON region and any VMCS region. It is a value greater than
/// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).
///
- UINT32 VmcsSize:13;
- UINT32 Reserved1:3;
+ UINT32 VmcsSize : 13;
+ UINT32 Reserved1 : 3;
///
/// [Bit 48] Indicates the width of the physical addresses that may be used
/// for the VMXON region, each VMCS, and data structures referenced by
@@ -3798,13 +3728,13 @@ typedef union {
/// @note On processors that support Intel 64 architecture, the pointer
/// must not set bits beyond the processor's physical address width.
///
- UINT32 VmcsAddressWidth:1;
+ UINT32 VmcsAddressWidth : 1;
///
/// [Bit 49] If bit 49 is read as 1, the logical processor supports the
/// dual-monitor treatment of system-management interrupts and
/// system-management mode. See Section 34.15 for details of this treatment.
///
- UINT32 DualMonitor:1;
+ UINT32 DualMonitor : 1;
///
/// [Bit 53:50] report the memory type that should be used for the VMCS,
/// for data structures referenced by pointers in the VMCS (I/O bitmaps,
@@ -3830,14 +3760,14 @@ typedef union {
/// performance of software accesses to those structures to suffer.
///
///
- UINT32 MemoryType:4;
+ UINT32 MemoryType : 4;
///
/// [Bit 54] If bit 54 is read as 1, the processor reports information in
/// the VM-exit instruction-information field on VM exitsdue to execution
/// of the INS and OUTS instructions (see Section 27.2.4). This reporting
/// is done only if this bit is read as 1.
///
- UINT32 InsOutsReporting:1;
+ UINT32 InsOutsReporting : 1;
///
/// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may
/// be cleared to 0. See Appendix A.2 for details. It also reports support
@@ -3846,13 +3776,13 @@ typedef union {
/// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2,
/// Appendix A.4, and Appendix A.5 for details.
///
- UINT32 VmxControls:1;
- UINT32 Reserved2:8;
+ UINT32 VmxControls : 1;
+ UINT32 Reserved2 : 8;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_VMX_BASIC_REGISTER;
///
@@ -3864,7 +3794,6 @@ typedef union {
/// @}
///
-
/**
Capability Reporting Register of Pinbased VM-execution Controls (R/O) See
Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.
@@ -3881,8 +3810,7 @@ typedef union {
@endcode
@note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM.
**/
-#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
-
+#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
/**
Capability Reporting Register of Primary Processor-based VM-execution
@@ -3901,8 +3829,7 @@ typedef union {
@endcode
@note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM.
**/
-#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
-
+#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
/**
Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4,
@@ -3920,8 +3847,7 @@ typedef union {
@endcode
@note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM.
**/
-#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
-
+#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
/**
Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5,
@@ -3939,8 +3865,7 @@ typedef union {
@endcode
@note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM.
**/
-#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
-
+#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
/**
Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6,
@@ -3958,7 +3883,7 @@ typedef union {
@endcode
@note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.
**/
-#define MSR_IA32_VMX_MISC 0x00000485
+#define MSR_IA32_VMX_MISC 0x00000485
/**
MSR information returned for MSR index #IA32_VMX_MISC
@@ -3974,27 +3899,27 @@ typedef union {
/// Specifically, the VMX-preemption timer (if it is active) counts down by
/// 1 every time bit X in the TSC changes due to a TSC increment.
///
- UINT32 VmxTimerRatio:5;
+ UINT32 VmxTimerRatio : 5;
///
/// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA
/// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more
/// details. This bit is read as 1 on any logical processor that supports
/// the 1-setting of the "unrestricted guest" VM-execution control.
///
- UINT32 VmExitEferLma:1;
+ UINT32 VmExitEferLma : 1;
///
/// [Bit 6] reports (if set) the support for activity state 1 (HLT).
///
- UINT32 HltActivityStateSupported:1;
+ UINT32 HltActivityStateSupported : 1;
///
/// [Bit 7] reports (if set) the support for activity state 2 (shutdown).
///
- UINT32 ShutdownActivityStateSupported:1;
+ UINT32 ShutdownActivityStateSupported : 1;
///
/// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).
///
- UINT32 WaitForSipiActivityStateSupported:1;
- UINT32 Reserved1:5;
+ UINT32 WaitForSipiActivityStateSupported : 1;
+ UINT32 Reserved1 : 5;
///
/// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used
/// in VMX operation. If the processor supports Intel PT but does not allow
@@ -4004,19 +3929,19 @@ typedef union {
/// operation) using the WRMSR instruction causes a general-protection
/// exception.
///
- UINT32 ProcessorTraceSupported:1;
+ UINT32 ProcessorTraceSupported : 1;
///
/// [Bit 15] If read as 1, the RDMSR instruction can be used in system-
/// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).
/// See Section 34.15.6.3.
///
- UINT32 SmBaseMsrSupported:1;
+ UINT32 SmBaseMsrSupported : 1;
///
/// [Bits 24:16] Indicate the number of CR3-target values supported by the
/// processor. This number is a value between 0 and 256, inclusive (bit 24
/// is set if and only if bits 23:16 are clear).
///
- UINT32 NumberOfCr3TargetValues:9;
+ UINT32 NumberOfCr3TargetValues : 9;
///
/// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum
/// number of MSRs that should appear in the VM-exit MSR-store list, the
@@ -4026,39 +3951,38 @@ typedef union {
/// limit is exceeded, undefined processor behavior may result (including a
/// machine check during the VMX transition).
///
- UINT32 MsrStoreListMaximum:3;
+ UINT32 MsrStoreListMaximum : 3;
///
/// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set
/// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1
/// (see Section 34.14.4).
///
- UINT32 BlockSmiSupported:1;
+ UINT32 BlockSmiSupported : 1;
///
/// [Bit 29] read as 1, software can use VMWRITE to write to any supported
/// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit
/// information fields.
///
- UINT32 VmWriteSupported:1;
+ UINT32 VmWriteSupported : 1;
///
/// [Bit 30] If read as 1, VM entry allows injection of a software
/// interrupt, software exception, or privileged software exception with an
/// instruction length of 0.
///
- UINT32 VmInjectSupported:1;
- UINT32 Reserved2:1;
+ UINT32 VmInjectSupported : 1;
+ UINT32 Reserved2 : 1;
///
/// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the
/// processor.
///
- UINT32 MsegRevisionIdentifier:32;
+ UINT32 MsegRevisionIdentifier : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} IA32_VMX_MISC_REGISTER;
-
/**
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,
"VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.
@@ -4075,8 +3999,7 @@ typedef union {
@endcode
@note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM.
**/
-#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
-
+#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
/**
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7,
@@ -4094,8 +4017,7 @@ typedef union {
@endcode
@note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM.
**/
-#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
-
+#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
/**
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8,
@@ -4113,8 +4035,7 @@ typedef union {
@endcode
@note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM.
**/
-#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
-
+#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
/**
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8,
@@ -4132,8 +4053,7 @@ typedef union {
@endcode
@note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM.
**/
-#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
-
+#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
/**
Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix
@@ -4151,8 +4071,7 @@ typedef union {
@endcode
@note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM.
**/
-#define MSR_IA32_VMX_VMCS_ENUM 0x0000048A
-
+#define MSR_IA32_VMX_VMCS_ENUM 0x0000048A
/**
Capability Reporting Register of Secondary Processor-based VM-execution
@@ -4171,8 +4090,7 @@ typedef union {
@endcode
@note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM.
**/
-#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B
-
+#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B
/**
Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10,
@@ -4191,8 +4109,7 @@ typedef union {
@endcode
@note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM.
**/
-#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C
-
+#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C
/**
Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O)
@@ -4211,8 +4128,7 @@ typedef union {
@endcode
@note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM.
**/
-#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D
-
+#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D
/**
Capability Reporting Register of Primary Processor-based VM-execution Flex
@@ -4231,8 +4147,7 @@ typedef union {
@endcode
@note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM.
**/
-#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E
-
+#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E
/**
Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix
@@ -4250,8 +4165,7 @@ typedef union {
@endcode
@note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM.
**/
-#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F
-
+#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F
/**
Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix
@@ -4269,8 +4183,7 @@ typedef union {
@endcode
@note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM.
**/
-#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
-
+#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
/**
Capability Reporting Register of VMfunction Controls (R/O). If(
@@ -4288,8 +4201,7 @@ typedef union {
@endcode
@note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM.
**/
-#define MSR_IA32_VMX_VMFUNC 0x00000491
-
+#define MSR_IA32_VMX_VMFUNC 0x00000491
/**
Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) &&
@@ -4316,17 +4228,16 @@ typedef union {
MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.
@{
**/
-#define MSR_IA32_A_PMC0 0x000004C1
-#define MSR_IA32_A_PMC1 0x000004C2
-#define MSR_IA32_A_PMC2 0x000004C3
-#define MSR_IA32_A_PMC3 0x000004C4
-#define MSR_IA32_A_PMC4 0x000004C5
-#define MSR_IA32_A_PMC5 0x000004C6
-#define MSR_IA32_A_PMC6 0x000004C7
-#define MSR_IA32_A_PMC7 0x000004C8
+#define MSR_IA32_A_PMC0 0x000004C1
+#define MSR_IA32_A_PMC1 0x000004C2
+#define MSR_IA32_A_PMC2 0x000004C3
+#define MSR_IA32_A_PMC3 0x000004C4
+#define MSR_IA32_A_PMC4 0x000004C5
+#define MSR_IA32_A_PMC5 0x000004C6
+#define MSR_IA32_A_PMC6 0x000004C7
+#define MSR_IA32_A_PMC7 0x000004C8
/// @}
-
/**
(R/W). If IA32_MCG_CAP.LMCE_P =1.
@@ -4345,7 +4256,7 @@ typedef union {
@endcode
@note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM.
**/
-#define MSR_IA32_MCG_EXT_CTL 0x000004D0
+#define MSR_IA32_MCG_EXT_CTL 0x000004D0
/**
MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL
@@ -4358,21 +4269,20 @@ typedef union {
///
/// [Bit 0] LMCE_EN.
///
- UINT32 LMCE_EN:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
+ UINT32 LMCE_EN : 1;
+ UINT32 Reserved1 : 31;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_MCG_EXT_CTL_REGISTER;
-
/**
Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H,
ECX=0H): EBX[2] = 1.
@@ -4391,7 +4301,7 @@ typedef union {
@endcode
@note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM.
**/
-#define MSR_IA32_SGX_SVN_STATUS 0x00000500
+#define MSR_IA32_SGX_SVN_STATUS 0x00000500
/**
MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS
@@ -4405,27 +4315,26 @@ typedef union {
/// [Bit 0] Lock. See Section 41.11.3, "Interactions with Authenticated
/// Code Modules (ACMs)".
///
- UINT32 Lock:1;
- UINT32 Reserved1:15;
+ UINT32 Lock : 1;
+ UINT32 Reserved1 : 15;
///
/// [Bits 23:16] SGX_SVN_SINIT. See Section 41.11.3, "Interactions with
/// Authenticated Code Modules (ACMs)".
///
- UINT32 SGX_SVN_SINIT:8;
- UINT32 Reserved2:8;
- UINT32 Reserved3:32;
+ UINT32 SGX_SVN_SINIT : 8;
+ UINT32 Reserved2 : 8;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_SGX_SVN_STATUS_REGISTER;
-
/**
Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
&& ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1)
@@ -4446,7 +4355,7 @@ typedef union {
@endcode
@note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM.
**/
-#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
+#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
/**
MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE
@@ -4456,23 +4365,22 @@ typedef union {
/// Individual bit fields
///
struct {
- UINT32 Reserved:7;
+ UINT32 Reserved : 7;
///
/// [Bits 31:7] Base physical address.
///
- UINT32 Base:25;
+ UINT32 Base : 25;
///
/// [Bits 63:32] Base physical address.
///
- UINT32 BaseHi:32;
+ UINT32 BaseHi : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_RTIT_OUTPUT_BASE_REGISTER;
-
/**
Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H,
ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1)
@@ -4493,7 +4401,7 @@ typedef union {
@endcode
@note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM.
**/
-#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561
+#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561
/**
MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS
@@ -4503,20 +4411,20 @@ typedef union {
/// Individual bit fields
///
struct {
- UINT32 Reserved:7;
+ UINT32 Reserved : 7;
///
/// [Bits 31:7] MaskOrTableOffset.
///
- UINT32 MaskOrTableOffset:25;
+ UINT32 MaskOrTableOffset : 25;
///
/// [Bits 63:32] Output Offset.
///
- UINT32 OutputOffset:32;
+ UINT32 OutputOffset : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER;
/**
@@ -4530,24 +4438,24 @@ typedef union {
///
/// [Bit 0] END. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
///
- UINT32 END:1;
- UINT32 Reserved1:1;
+ UINT32 END : 1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 2] INT. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
///
- UINT32 INT:1;
- UINT32 Reserved2:1;
+ UINT32 INT : 1;
+ UINT32 Reserved2 : 1;
///
/// [Bit 4] STOP. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
///
- UINT32 STOP:1;
- UINT32 Reserved3:1;
+ UINT32 STOP : 1;
+ UINT32 Reserved3 : 1;
///
/// [Bit 6:9] Indicates the size of the associated output region. See Section
/// 35.2.6.2, "Table of Physical Addresses (ToPA)".
///
- UINT32 Size:4;
- UINT32 Reserved4:2;
+ UINT32 Size : 4;
+ UINT32 Reserved4 : 2;
///
/// [Bit 12:31] Output Region Base Physical Address low part.
/// [Bit 12:31] Output Region Base Physical Address [12:63] value to match.
@@ -4557,7 +4465,7 @@ typedef union {
/// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.
/// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
///
- UINT32 Base:20;
+ UINT32 Base : 20;
///
/// [Bit 32:63] Output Region Base Physical Address high part.
/// [Bit 32:63] Output Region Base Physical Address [12:63] value to match.
@@ -4567,12 +4475,12 @@ typedef union {
/// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.
/// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
///
- UINT32 BaseHi:32;
+ UINT32 BaseHi : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} RTIT_TOPA_TABLE_ENTRY;
///
@@ -4615,7 +4523,7 @@ typedef enum {
@endcode
@note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.
**/
-#define MSR_IA32_RTIT_CTL 0x00000570
+#define MSR_IA32_RTIT_CTL 0x00000570
/**
MSR information returned for MSR index #MSR_IA32_RTIT_CTL
@@ -4628,99 +4536,98 @@ typedef union {
///
/// [Bit 0] TraceEn.
///
- UINT32 TraceEn:1;
+ UINT32 TraceEn : 1;
///
/// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
///
- UINT32 CYCEn:1;
+ UINT32 CYCEn : 1;
///
/// [Bit 2] OS.
///
- UINT32 OS:1;
+ UINT32 OS : 1;
///
/// [Bit 3] User.
///
- UINT32 User:1;
+ UINT32 User : 1;
///
/// [Bit 4] PwrEvtEn.
///
- UINT32 PwrEvtEn:1;
+ UINT32 PwrEvtEn : 1;
///
/// [Bit 5] FUPonPTW.
///
- UINT32 FUPonPTW:1;
+ UINT32 FUPonPTW : 1;
///
/// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).
///
- UINT32 FabricEn:1;
+ UINT32 FabricEn : 1;
///
/// [Bit 7] CR3 filter.
///
- UINT32 CR3:1;
+ UINT32 CR3 : 1;
///
/// [Bit 8] ToPA.
///
- UINT32 ToPA:1;
+ UINT32 ToPA : 1;
///
/// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
///
- UINT32 MTCEn:1;
+ UINT32 MTCEn : 1;
///
/// [Bit 10] TSCEn.
///
- UINT32 TSCEn:1;
+ UINT32 TSCEn : 1;
///
/// [Bit 11] DisRETC.
///
- UINT32 DisRETC:1;
+ UINT32 DisRETC : 1;
///
/// [Bit 12] PTWEn.
///
- UINT32 PTWEn:1;
+ UINT32 PTWEn : 1;
///
/// [Bit 13] BranchEn.
///
- UINT32 BranchEn:1;
+ UINT32 BranchEn : 1;
///
/// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
///
- UINT32 MTCFreq:4;
- UINT32 Reserved3:1;
+ UINT32 MTCFreq : 4;
+ UINT32 Reserved3 : 1;
///
/// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
///
- UINT32 CYCThresh:4;
- UINT32 Reserved4:1;
+ UINT32 CYCThresh : 4;
+ UINT32 Reserved4 : 1;
///
/// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
///
- UINT32 PSBFreq:4;
- UINT32 Reserved5:4;
+ UINT32 PSBFreq : 4;
+ UINT32 Reserved5 : 4;
///
/// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).
///
- UINT32 ADDR0_CFG:4;
+ UINT32 ADDR0_CFG : 4;
///
/// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1).
///
- UINT32 ADDR1_CFG:4;
+ UINT32 ADDR1_CFG : 4;
///
/// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2).
///
- UINT32 ADDR2_CFG:4;
+ UINT32 ADDR2_CFG : 4;
///
/// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).
///
- UINT32 ADDR3_CFG:4;
- UINT32 Reserved6:16;
+ UINT32 ADDR3_CFG : 4;
+ UINT32 Reserved6 : 16;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_RTIT_CTL_REGISTER;
-
/**
Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
@@ -4739,7 +4646,7 @@ typedef union {
@endcode
@note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM.
**/
-#define MSR_IA32_RTIT_STATUS 0x00000571
+#define MSR_IA32_RTIT_STATUS 0x00000571
/**
MSR information returned for MSR index #MSR_IA32_RTIT_STATUS
@@ -4753,38 +4660,37 @@ typedef union {
/// [Bit 0] FilterEn, (writes ignored).
/// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1).
///
- UINT32 FilterEn:1;
+ UINT32 FilterEn : 1;
///
/// [Bit 1] ContexEn, (writes ignored).
///
- UINT32 ContexEn:1;
+ UINT32 ContexEn : 1;
///
/// [Bit 2] TriggerEn, (writes ignored).
///
- UINT32 TriggerEn:1;
- UINT32 Reserved1:1;
+ UINT32 TriggerEn : 1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 4] Error.
///
- UINT32 Error:1;
+ UINT32 Error : 1;
///
/// [Bit 5] Stopped.
///
- UINT32 Stopped:1;
- UINT32 Reserved2:26;
+ UINT32 Stopped : 1;
+ UINT32 Reserved2 : 26;
///
/// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3).
///
- UINT32 PacketByteCnt:17;
- UINT32 Reserved3:15;
+ UINT32 PacketByteCnt : 17;
+ UINT32 Reserved3 : 15;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_RTIT_STATUS_REGISTER;
-
/**
Trace Filter CR3 Match Register (R/W).
If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
@@ -4804,7 +4710,7 @@ typedef union {
@endcode
@note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM.
**/
-#define MSR_IA32_RTIT_CR3_MATCH 0x00000572
+#define MSR_IA32_RTIT_CR3_MATCH 0x00000572
/**
MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH
@@ -4814,23 +4720,22 @@ typedef union {
/// Individual bit fields
///
struct {
- UINT32 Reserved:5;
+ UINT32 Reserved : 5;
///
/// [Bits 31:5] CR3[63:5] value to match.
///
- UINT32 Cr3:27;
+ UINT32 Cr3 : 27;
///
/// [Bits 63:32] CR3[63:5] value to match.
///
- UINT32 Cr3Hi:32;
+ UINT32 Cr3Hi : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_RTIT_CR3_MATCH_REGISTER;
-
/**
Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
@@ -4853,13 +4758,12 @@ typedef union {
MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.
@{
**/
-#define MSR_IA32_RTIT_ADDR0_A 0x00000580
-#define MSR_IA32_RTIT_ADDR1_A 0x00000582
-#define MSR_IA32_RTIT_ADDR2_A 0x00000584
-#define MSR_IA32_RTIT_ADDR3_A 0x00000586
+#define MSR_IA32_RTIT_ADDR0_A 0x00000580
+#define MSR_IA32_RTIT_ADDR1_A 0x00000582
+#define MSR_IA32_RTIT_ADDR2_A 0x00000584
+#define MSR_IA32_RTIT_ADDR3_A 0x00000586
/// @}
-
/**
Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
@@ -4882,13 +4786,12 @@ typedef union {
MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.
@{
**/
-#define MSR_IA32_RTIT_ADDR0_B 0x00000581
-#define MSR_IA32_RTIT_ADDR1_B 0x00000583
-#define MSR_IA32_RTIT_ADDR2_B 0x00000585
-#define MSR_IA32_RTIT_ADDR3_B 0x00000587
+#define MSR_IA32_RTIT_ADDR0_B 0x00000581
+#define MSR_IA32_RTIT_ADDR1_B 0x00000583
+#define MSR_IA32_RTIT_ADDR2_B 0x00000585
+#define MSR_IA32_RTIT_ADDR3_B 0x00000587
/// @}
-
/**
MSR information returned for MSR indexes
#MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and
@@ -4902,23 +4805,22 @@ typedef union {
///
/// [Bits 31:0] Virtual Address.
///
- UINT32 VirtualAddress:32;
+ UINT32 VirtualAddress : 32;
///
/// [Bits 47:32] Virtual Address.
///
- UINT32 VirtualAddressHi:16;
+ UINT32 VirtualAddressHi : 16;
///
/// [Bits 63:48] SignExt_VA.
///
- UINT32 SignExt_VA:16;
+ UINT32 SignExt_VA : 16;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_RTIT_ADDR_REGISTER;
-
/**
DS Save Area (R/W) Points to the linear address of the first byte of the DS
buffer management area, which is used to manage the BTS and PEBS buffers.
@@ -4941,8 +4843,7 @@ typedef union {
@endcode
@note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM.
**/
-#define MSR_IA32_DS_AREA 0x00000600
-
+#define MSR_IA32_DS_AREA 0x00000600
/**
TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] =
@@ -4961,8 +4862,7 @@ typedef union {
@endcode
@note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM.
**/
-#define MSR_IA32_TSC_DEADLINE 0x000006E0
-
+#define MSR_IA32_TSC_DEADLINE 0x000006E0
/**
Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1.
@@ -4982,7 +4882,7 @@ typedef union {
@endcode
@note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM.
**/
-#define MSR_IA32_PM_ENABLE 0x00000770
+#define MSR_IA32_PM_ENABLE 0x00000770
/**
MSR information returned for MSR index #MSR_IA32_PM_ENABLE
@@ -4996,21 +4896,20 @@ typedef union {
/// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If
/// CPUID.06H:EAX.[7] = 1.
///
- UINT32 HWP_ENABLE:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
+ UINT32 HWP_ENABLE : 1;
+ UINT32 Reserved1 : 31;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PM_ENABLE_REGISTER;
-
/**
HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1.
@@ -5028,7 +4927,7 @@ typedef union {
@endcode
@note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM.
**/
-#define MSR_IA32_HWP_CAPABILITIES 0x00000771
+#define MSR_IA32_HWP_CAPABILITIES 0x00000771
/**
MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES
@@ -5042,35 +4941,34 @@ typedef union {
/// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance
/// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
///
- UINT32 Highest_Performance:8;
+ UINT32 Highest_Performance : 8;
///
/// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP
/// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
///
- UINT32 Guaranteed_Performance:8;
+ UINT32 Guaranteed_Performance : 8;
///
/// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP
/// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
///
- UINT32 Most_Efficient_Performance:8;
+ UINT32 Most_Efficient_Performance : 8;
///
/// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance
/// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
///
- UINT32 Lowest_Performance:8;
- UINT32 Reserved:32;
+ UINT32 Lowest_Performance : 8;
+ UINT32 Reserved : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_HWP_CAPABILITIES_REGISTER;
-
/**
Power Management Control Hints for All Logical Processors in a Package
(R/W). If CPUID.06H:EAX.[11] = 1.
@@ -5090,7 +4988,7 @@ typedef union {
@endcode
@note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM.
**/
-#define MSR_IA32_HWP_REQUEST_PKG 0x00000772
+#define MSR_IA32_HWP_REQUEST_PKG 0x00000772
/**
MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG
@@ -5104,36 +5002,35 @@ typedef union {
/// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
/// CPUID.06H:EAX.[11] = 1.
///
- UINT32 Minimum_Performance:8;
+ UINT32 Minimum_Performance : 8;
///
/// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
/// CPUID.06H:EAX.[11] = 1.
///
- UINT32 Maximum_Performance:8;
+ UINT32 Maximum_Performance : 8;
///
/// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
/// If CPUID.06H:EAX.[11] = 1.
///
- UINT32 Desired_Performance:8;
+ UINT32 Desired_Performance : 8;
///
/// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
/// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.
///
- UINT32 Energy_Performance_Preference:8;
+ UINT32 Energy_Performance_Preference : 8;
///
/// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
/// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.
///
- UINT32 Activity_Window:10;
- UINT32 Reserved:22;
+ UINT32 Activity_Window : 10;
+ UINT32 Reserved : 22;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_HWP_REQUEST_PKG_REGISTER;
-
/**
Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1.
@@ -5152,7 +5049,7 @@ typedef union {
@endcode
@note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM.
**/
-#define MSR_IA32_HWP_INTERRUPT 0x00000773
+#define MSR_IA32_HWP_INTERRUPT 0x00000773
/**
MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT
@@ -5166,26 +5063,25 @@ typedef union {
/// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP
/// Notifications". If CPUID.06H:EAX.[8] = 1.
///
- UINT32 EN_Guaranteed_Performance_Change:1;
+ UINT32 EN_Guaranteed_Performance_Change : 1;
///
/// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications".
/// If CPUID.06H:EAX.[8] = 1.
///
- UINT32 EN_Excursion_Minimum:1;
- UINT32 Reserved1:30;
- UINT32 Reserved2:32;
+ UINT32 EN_Excursion_Minimum : 1;
+ UINT32 Reserved1 : 30;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_HWP_INTERRUPT_REGISTER;
-
/**
Power Management Control Hints to a Logical Processor (R/W). If
CPUID.06H:EAX.[7] = 1.
@@ -5205,7 +5101,7 @@ typedef union {
@endcode
@note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM.
**/
-#define MSR_IA32_HWP_REQUEST 0x00000774
+#define MSR_IA32_HWP_REQUEST 0x00000774
/**
MSR information returned for MSR index #MSR_IA32_HWP_REQUEST
@@ -5219,41 +5115,40 @@ typedef union {
/// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
/// CPUID.06H:EAX.[7] = 1.
///
- UINT32 Minimum_Performance:8;
+ UINT32 Minimum_Performance : 8;
///
/// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
/// CPUID.06H:EAX.[7] = 1.
///
- UINT32 Maximum_Performance:8;
+ UINT32 Maximum_Performance : 8;
///
/// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
/// If CPUID.06H:EAX.[7] = 1.
///
- UINT32 Desired_Performance:8;
+ UINT32 Desired_Performance : 8;
///
/// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
/// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1.
///
- UINT32 Energy_Performance_Preference:8;
+ UINT32 Energy_Performance_Preference : 8;
///
/// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
/// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1.
///
- UINT32 Activity_Window:10;
+ UINT32 Activity_Window : 10;
///
/// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If
/// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1.
///
- UINT32 Package_Control:1;
- UINT32 Reserved:21;
+ UINT32 Package_Control : 1;
+ UINT32 Reserved : 21;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_HWP_REQUEST_REGISTER;
-
/**
Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If
CPUID.06H:EAX.[7] = 1.
@@ -5273,7 +5168,7 @@ typedef union {
@endcode
@note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM.
**/
-#define MSR_IA32_HWP_STATUS 0x00000777
+#define MSR_IA32_HWP_STATUS 0x00000777
/**
MSR information returned for MSR index #MSR_IA32_HWP_STATUS
@@ -5287,27 +5182,26 @@ typedef union {
/// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5,
/// "HWP Feedback". If CPUID.06H:EAX.[7] = 1.
///
- UINT32 Guaranteed_Performance_Change:1;
- UINT32 Reserved1:1;
+ UINT32 Guaranteed_Performance_Change : 1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP
/// Feedback". If CPUID.06H:EAX.[7] = 1.
///
- UINT32 Excursion_To_Minimum:1;
- UINT32 Reserved2:29;
- UINT32 Reserved3:32;
+ UINT32 Excursion_To_Minimum : 1;
+ UINT32 Reserved2 : 29;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_HWP_STATUS_REGISTER;
-
/**
x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1
&& IA32_APIC_BASE.[10] = 1.
@@ -5324,8 +5218,7 @@ typedef union {
@endcode
@note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM.
**/
-#define MSR_IA32_X2APIC_APICID 0x00000802
-
+#define MSR_IA32_X2APIC_APICID 0x00000802
/**
x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
@@ -5343,8 +5236,7 @@ typedef union {
@endcode
@note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM.
**/
-#define MSR_IA32_X2APIC_VERSION 0x00000803
-
+#define MSR_IA32_X2APIC_VERSION 0x00000803
/**
x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
@@ -5363,8 +5255,7 @@ typedef union {
@endcode
@note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM.
**/
-#define MSR_IA32_X2APIC_TPR 0x00000808
-
+#define MSR_IA32_X2APIC_TPR 0x00000808
/**
x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
@@ -5382,8 +5273,7 @@ typedef union {
@endcode
@note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM.
**/
-#define MSR_IA32_X2APIC_PPR 0x0000080A
-
+#define MSR_IA32_X2APIC_PPR 0x0000080A
/**
x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10]
@@ -5402,8 +5292,7 @@ typedef union {
@endcode
@note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM.
**/
-#define MSR_IA32_X2APIC_EOI 0x0000080B
-
+#define MSR_IA32_X2APIC_EOI 0x0000080B
/**
x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
@@ -5421,8 +5310,7 @@ typedef union {
@endcode
@note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM.
**/
-#define MSR_IA32_X2APIC_LDR 0x0000080D
-
+#define MSR_IA32_X2APIC_LDR 0x0000080D
/**
x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1
@@ -5441,8 +5329,7 @@ typedef union {
@endcode
@note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM.
**/
-#define MSR_IA32_X2APIC_SIVR 0x0000080F
-
+#define MSR_IA32_X2APIC_SIVR 0x0000080F
/**
x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O).
@@ -5468,17 +5355,16 @@ typedef union {
MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.
@{
**/
-#define MSR_IA32_X2APIC_ISR0 0x00000810
-#define MSR_IA32_X2APIC_ISR1 0x00000811
-#define MSR_IA32_X2APIC_ISR2 0x00000812
-#define MSR_IA32_X2APIC_ISR3 0x00000813
-#define MSR_IA32_X2APIC_ISR4 0x00000814
-#define MSR_IA32_X2APIC_ISR5 0x00000815
-#define MSR_IA32_X2APIC_ISR6 0x00000816
-#define MSR_IA32_X2APIC_ISR7 0x00000817
+#define MSR_IA32_X2APIC_ISR0 0x00000810
+#define MSR_IA32_X2APIC_ISR1 0x00000811
+#define MSR_IA32_X2APIC_ISR2 0x00000812
+#define MSR_IA32_X2APIC_ISR3 0x00000813
+#define MSR_IA32_X2APIC_ISR4 0x00000814
+#define MSR_IA32_X2APIC_ISR5 0x00000815
+#define MSR_IA32_X2APIC_ISR6 0x00000816
+#define MSR_IA32_X2APIC_ISR7 0x00000817
/// @}
-
/**
x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O).
If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
@@ -5503,17 +5389,16 @@ typedef union {
MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.
@{
**/
-#define MSR_IA32_X2APIC_TMR0 0x00000818
-#define MSR_IA32_X2APIC_TMR1 0x00000819
-#define MSR_IA32_X2APIC_TMR2 0x0000081A
-#define MSR_IA32_X2APIC_TMR3 0x0000081B
-#define MSR_IA32_X2APIC_TMR4 0x0000081C
-#define MSR_IA32_X2APIC_TMR5 0x0000081D
-#define MSR_IA32_X2APIC_TMR6 0x0000081E
-#define MSR_IA32_X2APIC_TMR7 0x0000081F
+#define MSR_IA32_X2APIC_TMR0 0x00000818
+#define MSR_IA32_X2APIC_TMR1 0x00000819
+#define MSR_IA32_X2APIC_TMR2 0x0000081A
+#define MSR_IA32_X2APIC_TMR3 0x0000081B
+#define MSR_IA32_X2APIC_TMR4 0x0000081C
+#define MSR_IA32_X2APIC_TMR5 0x0000081D
+#define MSR_IA32_X2APIC_TMR6 0x0000081E
+#define MSR_IA32_X2APIC_TMR7 0x0000081F
/// @}
-
/**
x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O).
If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
@@ -5538,17 +5423,16 @@ typedef union {
MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.
@{
**/
-#define MSR_IA32_X2APIC_IRR0 0x00000820
-#define MSR_IA32_X2APIC_IRR1 0x00000821
-#define MSR_IA32_X2APIC_IRR2 0x00000822
-#define MSR_IA32_X2APIC_IRR3 0x00000823
-#define MSR_IA32_X2APIC_IRR4 0x00000824
-#define MSR_IA32_X2APIC_IRR5 0x00000825
-#define MSR_IA32_X2APIC_IRR6 0x00000826
-#define MSR_IA32_X2APIC_IRR7 0x00000827
+#define MSR_IA32_X2APIC_IRR0 0x00000820
+#define MSR_IA32_X2APIC_IRR1 0x00000821
+#define MSR_IA32_X2APIC_IRR2 0x00000822
+#define MSR_IA32_X2APIC_IRR3 0x00000823
+#define MSR_IA32_X2APIC_IRR4 0x00000824
+#define MSR_IA32_X2APIC_IRR5 0x00000825
+#define MSR_IA32_X2APIC_IRR6 0x00000826
+#define MSR_IA32_X2APIC_IRR7 0x00000827
/// @}
-
/**
x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1.
@@ -5566,8 +5450,7 @@ typedef union {
@endcode
@note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM.
**/
-#define MSR_IA32_X2APIC_ESR 0x00000828
-
+#define MSR_IA32_X2APIC_ESR 0x00000828
/**
x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If
@@ -5586,8 +5469,7 @@ typedef union {
@endcode
@note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM.
**/
-#define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F
-
+#define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F
/**
x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
@@ -5606,8 +5488,7 @@ typedef union {
@endcode
@note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM.
**/
-#define MSR_IA32_X2APIC_ICR 0x00000830
-
+#define MSR_IA32_X2APIC_ICR 0x00000830
/**
x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
@@ -5626,8 +5507,7 @@ typedef union {
@endcode
@note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM.
**/
-#define MSR_IA32_X2APIC_LVT_TIMER 0x00000832
-
+#define MSR_IA32_X2APIC_LVT_TIMER 0x00000832
/**
x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] =
@@ -5646,8 +5526,7 @@ typedef union {
@endcode
@note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM.
**/
-#define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833
-
+#define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833
/**
x2APIC LVT Performance Monitor Interrupt Register (R/W). If
@@ -5666,8 +5545,7 @@ typedef union {
@endcode
@note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM.
**/
-#define MSR_IA32_X2APIC_LVT_PMI 0x00000834
-
+#define MSR_IA32_X2APIC_LVT_PMI 0x00000834
/**
x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
@@ -5686,8 +5564,7 @@ typedef union {
@endcode
@note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM.
**/
-#define MSR_IA32_X2APIC_LVT_LINT0 0x00000835
-
+#define MSR_IA32_X2APIC_LVT_LINT0 0x00000835
/**
x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
@@ -5706,8 +5583,7 @@ typedef union {
@endcode
@note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM.
**/
-#define MSR_IA32_X2APIC_LVT_LINT1 0x00000836
-
+#define MSR_IA32_X2APIC_LVT_LINT1 0x00000836
/**
x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
@@ -5726,8 +5602,7 @@ typedef union {
@endcode
@note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM.
**/
-#define MSR_IA32_X2APIC_LVT_ERROR 0x00000837
-
+#define MSR_IA32_X2APIC_LVT_ERROR 0x00000837
/**
x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
@@ -5746,8 +5621,7 @@ typedef union {
@endcode
@note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM.
**/
-#define MSR_IA32_X2APIC_INIT_COUNT 0x00000838
-
+#define MSR_IA32_X2APIC_INIT_COUNT 0x00000838
/**
x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
@@ -5765,8 +5639,7 @@ typedef union {
@endcode
@note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM.
**/
-#define MSR_IA32_X2APIC_CUR_COUNT 0x00000839
-
+#define MSR_IA32_X2APIC_CUR_COUNT 0x00000839
/**
x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
@@ -5785,8 +5658,7 @@ typedef union {
@endcode
@note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM.
**/
-#define MSR_IA32_X2APIC_DIV_CONF 0x0000083E
-
+#define MSR_IA32_X2APIC_DIV_CONF 0x0000083E
/**
x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 &&
@@ -5805,8 +5677,111 @@ typedef union {
@endcode
@note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM.
**/
-#define MSR_IA32_X2APIC_SELF_IPI 0x0000083F
+#define MSR_IA32_X2APIC_SELF_IPI 0x0000083F
+/**
+ Memory Encryption Activation MSR. If CPUID.07H:ECX.[13] = 1.
+
+ @param ECX MSR_IA32_TME_ACTIVATE (0x00000982)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_IA32_TME_ACTIVATE_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_IA32_TME_ACTIVATE_REGISTER.
+
+ Example usage
+ @code
+ MSR_IA32_TME_ACTIVATE_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TME_ACTIVATE);
+ AsmWriteMsr64 (MSR_IA32_TME_ACTIVATE, Msr.Uint64);
+ @endcode
+ @note MSR_IA32_TME_ACTIVATE is defined as IA32_TME_ACTIVATE in SDM.
+**/
+#define MSR_IA32_TME_ACTIVATE 0x00000982
+
+/**
+ MSR information returned for MSR index #MSR_IA32_TME_ACTIVATE
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] Lock R/O: Will be set upon successful WRMSR (or first SMI);
+ /// written value ignored..
+ ///
+ UINT32 Lock : 1;
+ ///
+ /// [Bit 1] Hardware Encryption Enable: This bit also enables MKTME; MKTME
+ /// cannot be enabled without enabling encryption hardware.
+ ///
+ UINT32 TmeEnable : 1;
+ ///
+ /// [Bit 2] Key Select:
+ /// 0: Create a new TME key (expected cold/warm boot).
+ /// 1: Restore the TME key from storage (Expected when resume from standby).
+ ///
+ UINT32 KeySelect : 1;
+ ///
+ /// [Bit 3] Save TME Key for Standby: Save key into storage to be used when
+ /// resume from standby.
+ /// Note: This may not be supported in all processors.
+ ///
+ UINT32 SaveKeyForStandby : 1;
+ ///
+ /// [Bit 7:4] TME Policy/Encryption Algorithm: Only algorithms enumerated in
+ /// IA32_TME_CAPABILITY are allowed.
+ /// For example:
+ /// 0000 – AES-XTS-128.
+ /// 0001 – AES-XTS-128 with integrity.
+ /// 0010 – AES-XTS-256.
+ /// Other values are invalid.
+ ///
+ UINT32 TmePolicy : 4;
+ UINT32 Reserved : 23;
+ ///
+ /// [Bit 31] TME Encryption Bypass Enable: When encryption hardware is enabled:
+ /// * Total Memory Encryption is enabled using a CPU generated ephemeral key
+ /// based on a hardware random number generator when this bit is set to 0.
+ /// * Total Memory Encryption is bypassed (no encryption/decryption for KeyID0)
+ /// when this bit is set to 1.
+ /// Software must inspect Hardware Encryption Enable (bit 1) and TME encryption
+ /// bypass Enable (bit 31) to determine if TME encryption is enabled.
+ ///
+ UINT32 TmeBypassMode : 1;
+ ///
+ /// [Bit 35:32] MK_TME_KEYID_BITS: Reserved if MKTME is not enumerated, otherwise:
+ /// The number of key identifier bits to allocate to MKTME usage.
+ /// Similar to enumeration, this is an encoded value.
+ /// Writing a value greater than MK_TME_MAX_KEYID_BITS will result in #GP.
+ /// Writing a non-zero value to this field will #GP if bit 1 of EAX (Hardware
+ /// Encryption Enable) is not also set to ‘1, as encryption hardware must be
+ /// enabled to use MKTME.
+ /// Example: To support 255 keys, this field would be set to a value of 8.
+ ///
+ UINT32 MkTmeKeyidBits : 4;
+ UINT32 Reserved2 : 12;
+ ///
+ /// [Bit 63:48] MK_TME_CRYPTO_ALGS: Reserved if MKTME is not enumerated, otherwise:
+ /// Bit 48: AES-XTS 128.
+ /// Bit 49: AES-XTS 128 with integrity.
+ /// Bit 50: AES-XTS 256.
+ /// Bit 63:51: Reserved (#GP)
+ /// Bitmask for BIOS to set which encryption algorithms are allowed for MKTME, would
+ /// be later enforced by the key loading ISA ('1= allowed)
+ ///
+ UINT32 MkTmeCryptoAlgs : 16;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32[2];
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_IA32_TME_ACTIVATE_REGISTER;
/**
Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1.
@@ -5826,7 +5801,7 @@ typedef union {
@endcode
@note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM.
**/
-#define MSR_IA32_DEBUG_INTERFACE 0x00000C80
+#define MSR_IA32_DEBUG_INTERFACE 0x00000C80
/**
MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE
@@ -5840,32 +5815,31 @@ typedef union {
/// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features.
/// Default is 0. If CPUID.01H:ECX.[11] = 1.
///
- UINT32 Enable:1;
- UINT32 Reserved1:29;
+ UINT32 Enable : 1;
+ UINT32 Reserved1 : 29;
///
/// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The
/// lock bit is set automatically on the first SMI assertion even if not
/// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1.
///
- UINT32 Lock:1;
+ UINT32 Lock : 1;
///
/// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to
/// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1.
///
- UINT32 DebugOccurred:1;
- UINT32 Reserved2:32;
+ UINT32 DebugOccurred : 1;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_DEBUG_INTERFACE_REGISTER;
-
/**
L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ).
@@ -5884,7 +5858,7 @@ typedef union {
@endcode
@note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.
**/
-#define MSR_IA32_L3_QOS_CFG 0x00000C81
+#define MSR_IA32_L3_QOS_CFG 0x00000C81
/**
MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG
@@ -5898,18 +5872,18 @@ typedef union {
/// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate
/// in Code and Data Prioritization (CDP) mode.
///
- UINT32 Enable:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
+ UINT32 Enable : 1;
+ UINT32 Reserved1 : 31;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_L3_QOS_CFG_REGISTER;
/**
@@ -5930,7 +5904,7 @@ typedef union {
@endcode
@note MSR_IA32_L2_QOS_CFG is defined as IA32_L2_QOS_CFG in SDM.
**/
-#define MSR_IA32_L2_QOS_CFG 0x00000C82
+#define MSR_IA32_L2_QOS_CFG 0x00000C82
/**
MSR information returned for MSR index #MSR_IA32_L2_QOS_CFG
@@ -5944,18 +5918,18 @@ typedef union {
/// [Bit 0] Enable (R/W) Set 1 to enable L2 CAT masks and COS to operate
/// in Code and Data Prioritization (CDP) mode.
///
- UINT32 Enable:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
+ UINT32 Enable : 1;
+ UINT32 Reserved1 : 31;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_L2_QOS_CFG_REGISTER;
/**
@@ -5977,7 +5951,7 @@ typedef union {
@endcode
@note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
**/
-#define MSR_IA32_QM_EVTSEL 0x00000C8D
+#define MSR_IA32_QM_EVTSEL 0x00000C8D
/**
MSR information returned for MSR index #MSR_IA32_QM_EVTSEL
@@ -5991,22 +5965,21 @@ typedef union {
/// [Bits 7:0] Event ID: ID of a supported monitoring event to report via
/// IA32_QM_CTR.
///
- UINT32 EventID:8;
- UINT32 Reserved:24;
+ UINT32 EventID : 8;
+ UINT32 Reserved : 24;
///
/// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to
/// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` (
/// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
///
- UINT32 ResourceMonitoringID:32;
+ UINT32 ResourceMonitoringID : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_QM_EVTSEL_REGISTER;
-
/**
Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1
).
@@ -6025,7 +5998,7 @@ typedef union {
@endcode
@note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM.
**/
-#define MSR_IA32_QM_CTR 0x00000C8E
+#define MSR_IA32_QM_CTR 0x00000C8E
/**
MSR information returned for MSR index #MSR_IA32_QM_CTR
@@ -6038,29 +6011,28 @@ typedef union {
///
/// [Bits 31:0] Resource Monitored Data.
///
- UINT32 ResourceMonitoredData:32;
+ UINT32 ResourceMonitoredData : 32;
///
/// [Bits 61:32] Resource Monitored Data.
///
- UINT32 ResourceMonitoredDataHi:30;
+ UINT32 ResourceMonitoredDataHi : 30;
///
/// [Bit 62] Unavailable: If 1, indicates data for this RMID is not
/// available or not monitored for this resource or RMID.
///
- UINT32 Unavailable:1;
+ UINT32 Unavailable : 1;
///
/// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was
/// written to IA32_PQR_QM_EVTSEL.
///
- UINT32 Error:1;
+ UINT32 Error : 1;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_QM_CTR_REGISTER;
-
/**
Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12]
=1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ).
@@ -6080,7 +6052,7 @@ typedef union {
@endcode
@note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
**/
-#define MSR_IA32_PQR_ASSOC 0x00000C8F
+#define MSR_IA32_PQR_ASSOC 0x00000C8F
/**
MSR information returned for MSR index #MSR_IA32_PQR_ASSOC
@@ -6095,21 +6067,20 @@ typedef union {
/// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2`
/// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
///
- UINT32 ResourceMonitoringID:32;
+ UINT32 ResourceMonitoringID : 32;
///
/// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on
/// writes); returns the current COS when read. If ( CPUID.(EAX=07H,
/// ECX=0):EBX.[15] = 1 ).
///
- UINT32 COS:32;
+ UINT32 COS : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PQR_ASSOC_REGISTER;
-
/**
Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H,
ECX=0H):EBX[14] = 1).
@@ -6129,7 +6100,7 @@ typedef union {
@endcode
@note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM.
**/
-#define MSR_IA32_BNDCFGS 0x00000D90
+#define MSR_IA32_BNDCFGS 0x00000D90
/**
MSR information returned for MSR index #MSR_IA32_BNDCFGS
@@ -6142,29 +6113,28 @@ typedef union {
///
/// [Bit 0] EN: Enable Intel MPX in supervisor mode.
///
- UINT32 EN:1;
+ UINT32 EN : 1;
///
/// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch
/// instructions in the absence of the BND prefix.
///
- UINT32 BNDPRESERVE:1;
- UINT32 Reserved:10;
+ UINT32 BNDPRESERVE : 1;
+ UINT32 Reserved : 10;
///
/// [Bits 31:12] Base Address of Bound Directory.
///
- UINT32 Base:20;
+ UINT32 Base : 20;
///
/// [Bits 63:32] Base Address of Bound Directory.
///
- UINT32 BaseHi:32;
+ UINT32 BaseHi : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_BNDCFGS_REGISTER;
-
/**
Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1.
@@ -6183,7 +6153,7 @@ typedef union {
@endcode
@note MSR_IA32_XSS is defined as IA32_XSS in SDM.
**/
-#define MSR_IA32_XSS 0x00000DA0
+#define MSR_IA32_XSS 0x00000DA0
/**
MSR information returned for MSR index #MSR_IA32_XSS
@@ -6193,25 +6163,24 @@ typedef union {
/// Individual bit fields
///
struct {
- UINT32 Reserved1:8;
+ UINT32 Reserved1 : 8;
///
/// [Bit 8] Trace Packet Configuration State (R/W).
///
- UINT32 TracePacketConfigurationState:1;
- UINT32 Reserved2:23;
- UINT32 Reserved3:32;
+ UINT32 TracePacketConfigurationState : 1;
+ UINT32 Reserved2 : 23;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_XSS_REGISTER;
-
/**
Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1.
@@ -6230,7 +6199,7 @@ typedef union {
@endcode
@note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM.
**/
-#define MSR_IA32_PKG_HDC_CTL 0x00000DB0
+#define MSR_IA32_PKG_HDC_CTL 0x00000DB0
/**
MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL
@@ -6245,21 +6214,20 @@ typedef union {
/// logical processors in the package. See Section 14.5.2, "Package level
/// Enabling HDC". If CPUID.06H:EAX.[13] = 1.
///
- UINT32 HDC_Pkg_Enable:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
+ UINT32 HDC_Pkg_Enable : 1;
+ UINT32 Reserved1 : 31;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PKG_HDC_CTL_REGISTER;
-
/**
Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1.
@@ -6278,7 +6246,7 @@ typedef union {
@endcode
@note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM.
**/
-#define MSR_IA32_PM_CTL1 0x00000DB1
+#define MSR_IA32_PM_CTL1 0x00000DB1
/**
MSR information returned for MSR index #MSR_IA32_PM_CTL1
@@ -6293,21 +6261,20 @@ typedef union {
/// package level HDC control. See Section 14.5.3.
/// If CPUID.06H:EAX.[13] = 1.
///
- UINT32 HDC_Allow_Block:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
+ UINT32 HDC_Allow_Block : 1;
+ UINT32 Reserved1 : 31;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PM_CTL1_REGISTER;
-
/**
Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1.
Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical
@@ -6325,8 +6292,7 @@ typedef union {
@endcode
@note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM.
**/
-#define MSR_IA32_THREAD_STALL 0x00000DB2
-
+#define MSR_IA32_THREAD_STALL 0x00000DB2
/**
Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0]
@@ -6347,7 +6313,7 @@ typedef union {
@endcode
@note MSR_IA32_EFER is defined as IA32_EFER in SDM.
**/
-#define MSR_IA32_EFER 0xC0000080
+#define MSR_IA32_EFER 0xC0000080
/**
MSR information returned for MSR index #MSR_IA32_EFER
@@ -6361,37 +6327,36 @@ typedef union {
/// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET
/// instructions in 64-bit mode.
///
- UINT32 SCE:1;
- UINT32 Reserved1:7;
+ UINT32 SCE : 1;
+ UINT32 Reserved1 : 7;
///
/// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode
/// operation.
///
- UINT32 LME:1;
- UINT32 Reserved2:1;
+ UINT32 LME : 1;
+ UINT32 Reserved2 : 1;
///
/// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode
/// is active when set.
///
- UINT32 LMA:1;
+ UINT32 LMA : 1;
///
/// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W).
///
- UINT32 NXE:1;
- UINT32 Reserved3:20;
- UINT32 Reserved4:32;
+ UINT32 NXE : 1;
+ UINT32 Reserved3 : 20;
+ UINT32 Reserved4 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_EFER_REGISTER;
-
/**
System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
@@ -6408,8 +6373,7 @@ typedef union {
@endcode
@note MSR_IA32_STAR is defined as IA32_STAR in SDM.
**/
-#define MSR_IA32_STAR 0xC0000081
-
+#define MSR_IA32_STAR 0xC0000081
/**
IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
@@ -6427,7 +6391,7 @@ typedef union {
@endcode
@note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM.
**/
-#define MSR_IA32_LSTAR 0xC0000082
+#define MSR_IA32_LSTAR 0xC0000082
/**
IA-32e Mode System Call Target Address (R/W) Not used, as the SYSCALL
@@ -6447,7 +6411,7 @@ typedef union {
@endcode
@note MSR_IA32_CSTAR is defined as IA32_CSTAR in SDM.
**/
-#define MSR_IA32_CSTAR 0xC0000083
+#define MSR_IA32_CSTAR 0xC0000083
/**
System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.
@@ -6465,8 +6429,7 @@ typedef union {
@endcode
@note MSR_IA32_FMASK is defined as IA32_FMASK in SDM.
**/
-#define MSR_IA32_FMASK 0xC0000084
-
+#define MSR_IA32_FMASK 0xC0000084
/**
Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1.
@@ -6484,8 +6447,7 @@ typedef union {
@endcode
@note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM.
**/
-#define MSR_IA32_FS_BASE 0xC0000100
-
+#define MSR_IA32_FS_BASE 0xC0000100
/**
Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
@@ -6503,8 +6465,7 @@ typedef union {
@endcode
@note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM.
**/
-#define MSR_IA32_GS_BASE 0xC0000101
-
+#define MSR_IA32_GS_BASE 0xC0000101
/**
Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
@@ -6522,8 +6483,7 @@ typedef union {
@endcode
@note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM.
**/
-#define MSR_IA32_KERNEL_GS_BASE 0xC0000102
-
+#define MSR_IA32_KERNEL_GS_BASE 0xC0000102
/**
Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1.
@@ -6543,7 +6503,7 @@ typedef union {
@endcode
@note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM.
**/
-#define MSR_IA32_TSC_AUX 0xC0000103
+#define MSR_IA32_TSC_AUX 0xC0000103
/**
MSR information returned for MSR index #MSR_IA32_TSC_AUX
@@ -6556,17 +6516,17 @@ typedef union {
///
/// [Bits 31:0] AUX: Auxiliary signature of TSC.
///
- UINT32 AUX:32;
- UINT32 Reserved:32;
+ UINT32 AUX : 32;
+ UINT32 Reserved : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_TSC_AUX_REGISTER;
#endif
diff --git a/BootloaderCommonPkg/Include/Register/Intel/Cpuid.h b/MdePkg/Include/Register/Intel/Cpuid.h
similarity index 84%
rename from BootloaderCommonPkg/Include/Register/Intel/Cpuid.h
rename to MdePkg/Include/Register/Intel/Cpuid.h
index 47a694fd..03101ab2 100644
--- a/BootloaderCommonPkg/Include/Register/Intel/Cpuid.h
+++ b/MdePkg/Include/Register/Intel/Cpuid.h
@@ -6,12 +6,14 @@
If a register returned is a single 32-bit value, then a data structure is
not provided for that register.
- Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,
November 2018, CPUID instruction.
+ Architecture Specification: Intel(R) Trust Domain Extensions Module, Chap 10.2
+ 344425-003US, August 2021
**/
@@ -40,7 +42,7 @@
AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);
@endcode
**/
-#define CPUID_SIGNATURE 0x00
+#define CPUID_SIGNATURE 0x00
///
/// @{ CPUID signature values returned by Intel processors
@@ -52,7 +54,6 @@
/// @}
///
-
/**
CPUID Version Information
@@ -77,7 +78,7 @@
AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
@endcode
**/
-#define CPUID_VERSION_INFO 0x01
+#define CPUID_VERSION_INFO 0x01
/**
CPUID Version Information returned in EAX for CPUID leaf
@@ -88,14 +89,14 @@ typedef union {
/// Individual bit fields
///
struct {
- UINT32 SteppingId:4; ///< [Bits 3:0] Stepping ID
- UINT32 Model:4; ///< [Bits 7:4] Model
- UINT32 FamilyId:4; ///< [Bits 11:8] Family
- UINT32 ProcessorType:2; ///< [Bits 13:12] Processor Type
- UINT32 Reserved1:2; ///< [Bits 15:14] Reserved
- UINT32 ExtendedModelId:4; ///< [Bits 19:16] Extended Model ID
- UINT32 ExtendedFamilyId:8; ///< [Bits 27:20] Extended Family ID
- UINT32 Reserved2:4; ///< Reserved
+ UINT32 SteppingId : 4; ///< [Bits 3:0] Stepping ID
+ UINT32 Model : 4; ///< [Bits 7:4] Model
+ UINT32 FamilyId : 4; ///< [Bits 11:8] Family
+ UINT32 ProcessorType : 2; ///< [Bits 13:12] Processor Type
+ UINT32 Reserved1 : 2; ///< [Bits 15:14] Reserved
+ UINT32 ExtendedModelId : 4; ///< [Bits 19:16] Extended Model ID
+ UINT32 ExtendedFamilyId : 8; ///< [Bits 27:20] Extended Family ID
+ UINT32 Reserved2 : 4; ///< Reserved
} Bits;
///
/// All bit fields as a 32-bit value
@@ -126,13 +127,13 @@ typedef union {
/// [Bits 7:0] Provides an entry into a brand string table that contains
/// brand strings for IA-32 processors.
///
- UINT32 BrandIndex:8;
+ UINT32 BrandIndex : 8;
///
/// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH
/// and CLFLUSHOPT instructions in 8-byte increments. This field was
/// introduced in the Pentium 4 processor.
///
- UINT32 CacheLineSize:8;
+ UINT32 CacheLineSize : 8;
///
/// [Bits 23:16] Maximum number of addressable IDs for logical processors
/// in this physical package.
@@ -143,13 +144,13 @@ typedef union {
/// logical processors in a physical package. This field is only valid if
/// CPUID.1.EDX.HTT[bit 28]= 1.
///
- UINT32 MaximumAddressableIdsForLogicalProcessors:8;
+ UINT32 MaximumAddressableIdsForLogicalProcessors : 8;
///
/// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the
/// processor during power up. This field was introduced in the Pentium 4
/// processor.
///
- UINT32 InitialLocalApicId:8;
+ UINT32 InitialLocalApicId : 8;
} Bits;
///
/// All bit fields as a 32-bit value
@@ -170,161 +171,161 @@ typedef union {
/// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the
/// processor supports this technology
///
- UINT32 SSE3:1;
+ UINT32 SSE3 : 1;
///
/// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ
/// instruction. Carryless Multiplication
///
- UINT32 PCLMULQDQ:1;
+ UINT32 PCLMULQDQ : 1;
///
/// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports
/// DS area using 64-bit layout.
///
- UINT32 DTES64:1;
+ UINT32 DTES64 : 1;
///
/// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports
/// this feature.
///
- UINT32 MONITOR:1;
+ UINT32 MONITOR : 1;
///
/// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor
/// supports the extensions to the Debug Store feature to allow for branch
/// message storage qualified by CPL
///
- UINT32 DS_CPL:1;
+ UINT32 DS_CPL : 1;
///
/// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the
/// processor supports this technology.
///
- UINT32 VMX:1;
+ UINT32 VMX : 1;
///
/// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor
/// supports this technology
///
- UINT32 SMX:1;
+ UINT32 SMX : 1;
///
/// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates
/// that the processor supports this technology
///
- UINT32 EIST:1;
+ UINT32 EIST : 1;
///
/// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor
/// supports this technology
///
- UINT32 TM2:1;
+ UINT32 TM2 : 1;
///
/// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming
/// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction
/// extensions are not present in the processor.
///
- UINT32 SSSE3:1;
+ UINT32 SSSE3 : 1;
///
/// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode
/// can be set to either adaptive mode or shared mode. A value of 0 indicates
/// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR
/// Bit 24 (L1 Data Cache Context Mode) for details
///
- UINT32 CNXT_ID:1;
+ UINT32 CNXT_ID : 1;
///
/// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE
/// MSR for silicon debug
///
- UINT32 SDBG:1;
+ UINT32 SDBG : 1;
///
/// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple
/// Add) extensions using YMM state.
///
- UINT32 FMA:1;
+ UINT32 FMA : 1;
///
/// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature
/// is available.
///
- UINT32 CMPXCHG16B:1;
+ UINT32 CMPXCHG16B : 1;
///
/// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor
/// supports changing IA32_MISC_ENABLE[Bit 23].
///
- UINT32 xTPR_Update_Control:1;
+ UINT32 xTPR_Update_Control : 1;
///
/// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the
/// processor supports the performance and debug feature indication MSR
/// IA32_PERF_CAPABILITIES.
///
- UINT32 PDCM:1;
- UINT32 Reserved:1;
+ UINT32 PDCM : 1;
+ UINT32 Reserved : 1;
///
/// [Bit 17] Process-context identifiers. A value of 1 indicates that the
/// processor supports PCIDs and that software may set CR4.PCIDE to 1.
///
- UINT32 PCID:1;
+ UINT32 PCID : 1;
///
/// [Bit 18] A value of 1 indicates the processor supports the ability to
/// prefetch data from a memory mapped device. Direct Cache Access.
///
- UINT32 DCA:1;
+ UINT32 DCA : 1;
///
/// [Bit 19] A value of 1 indicates that the processor supports SSE4.1.
///
- UINT32 SSE4_1:1;
+ UINT32 SSE4_1 : 1;
///
/// [Bit 20] A value of 1 indicates that the processor supports SSE4.2.
///
- UINT32 SSE4_2:1;
+ UINT32 SSE4_2 : 1;
///
/// [Bit 21] A value of 1 indicates that the processor supports x2APIC
/// feature.
///
- UINT32 x2APIC:1;
+ UINT32 x2APIC : 1;
///
/// [Bit 22] A value of 1 indicates that the processor supports MOVBE
/// instruction.
///
- UINT32 MOVBE:1;
+ UINT32 MOVBE : 1;
///
/// [Bit 23] A value of 1 indicates that the processor supports the POPCNT
/// instruction.
///
- UINT32 POPCNT:1;
+ UINT32 POPCNT : 1;
///
/// [Bit 24] A value of 1 indicates that the processor's local APIC timer
/// supports one-shot operation using a TSC deadline value.
///
- UINT32 TSC_Deadline:1;
+ UINT32 TSC_Deadline : 1;
///
/// [Bit 25] A value of 1 indicates that the processor supports the AESNI
/// instruction extensions.
///
- UINT32 AESNI:1;
+ UINT32 AESNI : 1;
///
/// [Bit 26] A value of 1 indicates that the processor supports the
/// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV
/// instructions, and XCR0.
///
- UINT32 XSAVE:1;
+ UINT32 XSAVE : 1;
///
/// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18]
/// to enable XSETBV/XGETBV instructions to access XCR0 and to support
/// processor extended state management using XSAVE/XRSTOR.
///
- UINT32 OSXSAVE:1;
+ UINT32 OSXSAVE : 1;
///
/// [Bit 28] A value of 1 indicates the processor supports the AVX instruction
/// extensions.
///
- UINT32 AVX:1;
+ UINT32 AVX : 1;
///
/// [Bit 29] A value of 1 indicates that processor supports 16-bit
/// floating-point conversion instructions.
///
- UINT32 F16C:1;
+ UINT32 F16C : 1;
///
/// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction.
///
- UINT32 RDRAND:1;
+ UINT32 RDRAND : 1;
///
- /// [Bit 31] Always returns 0.
+ /// [Bit 31] A value of 1 indicates that processor is in Para-Virtualized.
///
- UINT32 NotUsed:1;
+ UINT32 ParaVirtualized : 1;
} Bits;
///
/// All bit fields as a 32-bit value
@@ -344,7 +345,7 @@ typedef union {
///
/// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU.
///
- UINT32 FPU:1;
+ UINT32 FPU : 1;
///
/// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,
/// including CR4.VME for controlling the feature, CR4.PVI for protected
@@ -352,38 +353,38 @@ typedef union {
/// the TSS with the software indirection bitmap, and EFLAGS.VIF and
/// EFLAGS.VIP flags.
///
- UINT32 VME:1;
+ UINT32 VME : 1;
///
/// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including
/// CR4.DE for controlling the feature, and optional trapping of accesses to
/// DR4 and DR5.
///
- UINT32 DE:1;
+ UINT32 DE : 1;
///
/// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported,
/// including CR4.PSE for controlling the feature, the defined dirty bit in
/// PDE (Page Directory Entries), optional reserved bit trapping in CR3,
/// PDEs, and PTEs.
///
- UINT32 PSE:1;
+ UINT32 PSE : 1;
///
/// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported,
/// including CR4.TSD for controlling privilege.
///
- UINT32 TSC:1;
+ UINT32 TSC : 1;
///
/// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The
/// RDMSR and WRMSR instructions are supported. Some of the MSRs are
/// implementation dependent.
///
- UINT32 MSR:1;
+ UINT32 MSR : 1;
///
/// [Bit 6] Physical Address Extension. Physical addresses greater than 32
/// bits are supported: extended page table entry formats, an extra level in
/// the page translation tables is defined, 2-MByte pages are supported
/// instead of 4 Mbyte pages if PAE bit is 1.
///
- UINT32 PAE:1;
+ UINT32 PAE : 1;
///
/// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine
/// Checks, including CR4.MCE for controlling the feature. This feature does
@@ -393,59 +394,59 @@ typedef union {
/// processing of the exception, or test for the presence of the Machine
/// Check feature.
///
- UINT32 MCE:1;
+ UINT32 MCE : 1;
///
/// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits)
/// instruction is supported (implicitly locked and atomic).
///
- UINT32 CX8:1;
+ UINT32 CX8 : 1;
///
/// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable
/// Interrupt Controller (APIC), responding to memory mapped commands in the
/// physical address range FFFE0000H to FFFE0FFFH (by default - some
/// processors permit the APIC to be relocated).
///
- UINT32 APIC:1;
- UINT32 Reserved1:1;
+ UINT32 APIC : 1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT
/// and associated MSRs are supported.
///
- UINT32 SEP:1;
+ UINT32 SEP : 1;
///
/// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap
/// MSR contains feature bits that describe what memory types are supported,
/// how many variable MTRRs are supported, and whether fixed MTRRs are
/// supported.
///
- UINT32 MTRR:1;
+ UINT32 MTRR : 1;
///
/// [Bit 13] Page Global Bit. The global bit is supported in paging-structure
/// entries that map a page, indicating TLB entries that are common to
/// different processes and need not be flushed. The CR4.PGE bit controls
/// this feature.
///
- UINT32 PGE:1;
+ UINT32 PGE : 1;
///
/// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine
/// Check Architecture of reporting machine errors is supported. The MCG_CAP
/// MSR contains feature bits describing how many banks of error reporting
/// MSRs are supported.
///
- UINT32 MCA:1;
+ UINT32 MCA : 1;
///
/// [Bit 15] Conditional Move Instructions. The conditional move instruction
/// CMOV is supported. In addition, if x87 FPU is present as indicated by the
/// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported.
///
- UINT32 CMOV:1;
+ UINT32 CMOV : 1;
///
/// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This
/// feature augments the Memory Type Range Registers (MTRRs), allowing an
/// operating system to specify attributes of memory accessed through a
/// linear address on a 4KB granularity.
///
- UINT32 PAT:1;
+ UINT32 PAT : 1;
///
/// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical
/// memory beyond 4 GBytes are supported with 32-bit paging. This feature
@@ -453,36 +454,36 @@ typedef union {
/// encoded in bits 20:13 of the page-directory entry. Such physical
/// addresses are limited by MAXPHYADDR and may be up to 40 bits in size.
///
- UINT32 PSE_36:1;
+ UINT32 PSE_36 : 1;
///
/// [Bit 18] Processor Serial Number. The processor supports the 96-bit
/// processor identification number feature and the feature is enabled.
///
- UINT32 PSN:1;
+ UINT32 PSN : 1;
///
/// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported.
///
- UINT32 CLFSH:1;
- UINT32 Reserved2:1;
+ UINT32 CLFSH : 1;
+ UINT32 Reserved2 : 1;
///
/// [Bit 21] Debug Store. The processor supports the ability to write debug
/// information into a memory resident buffer. This feature is used by the
/// branch trace store (BTS) and precise event-based sampling (PEBS)
/// facilities.
///
- UINT32 DS:1;
+ UINT32 DS : 1;
///
/// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The
/// processor implements internal MSRs that allow processor temperature to
/// be monitored and processor performance to be modulated in predefined
/// duty cycles under software control.
///
- UINT32 ACPI:1;
+ UINT32 ACPI : 1;
///
/// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX
/// technology.
///
- UINT32 MMX:1;
+ UINT32 MMX : 1;
///
/// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR
/// instructions are supported for fast save and restore of the floating
@@ -490,21 +491,21 @@ typedef union {
/// available for an operating system to indicate that it supports the
/// FXSAVE and FXRSTOR instructions.
///
- UINT32 FXSR:1;
+ UINT32 FXSR : 1;
///
/// [Bit 25] SSE. The processor supports the SSE extensions.
///
- UINT32 SSE:1;
+ UINT32 SSE : 1;
///
/// [Bit 26] SSE2. The processor supports the SSE2 extensions.
///
- UINT32 SSE2:1;
+ UINT32 SSE2 : 1;
///
/// [Bit 27] Self Snoop. The processor supports the management of
/// conflicting memory types by performing a snoop of its own cache
/// structure for transactions issued to the bus.
///
- UINT32 SS:1;
+ UINT32 SS : 1;
///
/// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT
/// indicates there is only a single logical processor in the package and
@@ -513,13 +514,13 @@ typedef union {
/// addressable IDs for logical processors in this package) is valid for the
/// package.
///
- UINT32 HTT:1;
+ UINT32 HTT : 1;
///
/// [Bit 29] Thermal Monitor. The processor implements the thermal monitor
/// automatic thermal control circuitry (TCC).
///
- UINT32 TM:1;
- UINT32 Reserved3:1;
+ UINT32 TM : 1;
+ UINT32 Reserved3 : 1;
///
/// [Bit 31] Pending Break Enable. The processor supports the use of the
/// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is
@@ -527,7 +528,7 @@ typedef union {
/// the processor should return to normal operation to handle the interrupt.
/// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.
///
- UINT32 PBE:1;
+ UINT32 PBE : 1;
} Bits;
///
/// All bit fields as a 32-bit value
@@ -535,7 +536,6 @@ typedef union {
UINT32 Uint32;
} CPUID_VERSION_INFO_EDX;
-
/**
CPUID Cache and TLB Information
@@ -707,7 +707,7 @@ typedef union {
use CPUID leaf 4 to query cache parameters
**/
-#define CPUID_CACHE_INFO 0x02
+#define CPUID_CACHE_INFO 0x02
/**
CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID
@@ -718,24 +718,23 @@ typedef union {
/// Individual bit fields
///
struct {
- UINT32 Reserved:31;
+ UINT32 Reserved : 31;
///
/// [Bit 31] If 0, then the cache descriptor bytes in the register are valid.
/// if 1, then none of the cache descriptor bytes in the register are valid.
///
- UINT32 NotValid:1;
+ UINT32 NotValid : 1;
} Bits;
///
/// Array of Cache and TLB descriptor bytes
///
- UINT8 CacheDescriptor[4];
+ UINT8 CacheDescriptor[4];
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_CACHE_INFO_CACHE_TLB;
-
/**
CPUID Processor Serial Number
@@ -762,8 +761,7 @@ typedef union {
AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);
@endcode
**/
-#define CPUID_SERIAL_NUMBER 0x03
-
+#define CPUID_SERIAL_NUMBER 0x03
/**
CPUID Cache Parameters
@@ -801,7 +799,7 @@ typedef union {
} while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);
@endcode
**/
-#define CPUID_CACHE_PARAMS 0x04
+#define CPUID_CACHE_PARAMS 0x04
/**
CPUID Cache Parameters Information returned in EAX for CPUID leaf
@@ -816,23 +814,23 @@ typedef union {
/// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL,
/// then there is no information for the requested cache level.
///
- UINT32 CacheType:5;
+ UINT32 CacheType : 5;
///
/// [Bits 7:5] Cache level (Starts at 1).
///
- UINT32 CacheLevel:3;
+ UINT32 CacheLevel : 3;
///
/// [Bit 8] Self Initializing cache level (does not need SW initialization).
///
- UINT32 SelfInitializingCache:1;
+ UINT32 SelfInitializingCache : 1;
///
/// [Bit 9] Fully Associative cache.
///
- UINT32 FullyAssociativeCache:1;
+ UINT32 FullyAssociativeCache : 1;
///
/// [Bits 13:10] Reserved.
///
- UINT32 Reserved:4;
+ UINT32 Reserved : 4;
///
/// [Bits 25:14] Maximum number of addressable IDs for logical processors
/// sharing this cache.
@@ -842,7 +840,7 @@ typedef union {
/// is the number of unique initial APIC IDs reserved for addressing
/// different logical processors sharing this cache.
///
- UINT32 MaximumAddressableIdsForLogicalProcessors:12;
+ UINT32 MaximumAddressableIdsForLogicalProcessors : 12;
///
/// [Bits 31:26] Maximum number of addressable IDs for processor cores in
/// the physical package.
@@ -854,12 +852,12 @@ typedef union {
/// The returned value is constant for valid initial values in ECX. Valid
/// ECX values start from 0.
///
- UINT32 MaximumAddressableIdsForProcessorCores:6;
+ UINT32 MaximumAddressableIdsForProcessorCores : 6;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_CACHE_PARAMS_EAX;
///
@@ -886,22 +884,22 @@ typedef union {
/// [Bits 11:0] System Coherency Line Size. Add one to the return value to
/// get the result.
///
- UINT32 LineSize:12;
+ UINT32 LineSize : 12;
///
/// [Bits 21:12] Physical Line Partitions. Add one to the return value to
/// get the result.
///
- UINT32 LinePartitions:10;
+ UINT32 LinePartitions : 10;
///
/// [Bits 31:22] Ways of associativity. Add one to the return value to get
/// the result.
///
- UINT32 Ways:10;
+ UINT32 Ways : 10;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_CACHE_PARAMS_EBX;
/**
@@ -920,29 +918,28 @@ typedef union {
/// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of
/// non-originating threads sharing this cache.
///
- UINT32 Invalidate:1;
+ UINT32 Invalidate : 1;
///
/// [Bit 1] Cache Inclusiveness.
/// 0 = Cache is not inclusive of lower cache levels.
/// 1 = Cache is inclusive of lower cache levels.
///
- UINT32 CacheInclusiveness:1;
+ UINT32 CacheInclusiveness : 1;
///
/// [Bit 2] Complex Cache Indexing.
/// 0 = Direct mapped cache.
/// 1 = A complex function is used to index the cache, potentially using all
/// address bits.
///
- UINT32 ComplexCacheIndexing:1;
- UINT32 Reserved:29;
+ UINT32 ComplexCacheIndexing : 1;
+ UINT32 Reserved : 29;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_CACHE_PARAMS_EDX;
-
/**
CPUID MONITOR/MWAIT Information
@@ -967,7 +964,7 @@ typedef union {
AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
@endcode
**/
-#define CPUID_MONITOR_MWAIT 0x05
+#define CPUID_MONITOR_MWAIT 0x05
/**
CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf
@@ -982,13 +979,13 @@ typedef union {
/// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's
/// monitor granularity).
///
- UINT32 SmallestMonitorLineSize:16;
- UINT32 Reserved:16;
+ UINT32 SmallestMonitorLineSize : 16;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_MONITOR_MWAIT_EAX;
/**
@@ -1004,13 +1001,13 @@ typedef union {
/// [Bits 15:0] Largest monitor-line size in bytes (default is processor's
/// monitor granularity).
///
- UINT32 LargestMonitorLineSize:16;
- UINT32 Reserved:16;
+ UINT32 LargestMonitorLineSize : 16;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_MONITOR_MWAIT_EBX;
/**
@@ -1026,18 +1023,18 @@ typedef union {
/// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX,
/// and EDX are valid.
///
- UINT32 ExtensionsSupported:1;
+ UINT32 ExtensionsSupported : 1;
///
/// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when
/// interrupts disabled.
///
- UINT32 InterruptAsBreak:1;
- UINT32 Reserved:30;
+ UINT32 InterruptAsBreak : 1;
+ UINT32 Reserved : 30;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_MONITOR_MWAIT_ECX;
/**
@@ -1056,43 +1053,42 @@ typedef union {
///
/// [Bits 3:0] Number of C0 sub C-states supported using MWAIT.
///
- UINT32 C0States:4;
+ UINT32 C0States : 4;
///
/// [Bits 7:4] Number of C1 sub C-states supported using MWAIT.
///
- UINT32 C1States:4;
+ UINT32 C1States : 4;
///
/// [Bits 11:8] Number of C2 sub C-states supported using MWAIT.
///
- UINT32 C2States:4;
+ UINT32 C2States : 4;
///
/// [Bits 15:12] Number of C3 sub C-states supported using MWAIT.
///
- UINT32 C3States:4;
+ UINT32 C3States : 4;
///
/// [Bits 19:16] Number of C4 sub C-states supported using MWAIT.
///
- UINT32 C4States:4;
+ UINT32 C4States : 4;
///
/// [Bits 23:20] Number of C5 sub C-states supported using MWAIT.
///
- UINT32 C5States:4;
+ UINT32 C5States : 4;
///
/// [Bits 27:24] Number of C6 sub C-states supported using MWAIT.
///
- UINT32 C6States:4;
+ UINT32 C6States : 4;
///
/// [Bits 31:28] Number of C7 sub C-states supported using MWAIT.
///
- UINT32 C7States:4;
+ UINT32 C7States : 4;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_MONITOR_MWAIT_EDX;
-
/**
CPUID Thermal and Power Management
@@ -1115,7 +1111,7 @@ typedef union {
AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
@endcode
**/
-#define CPUID_THERMAL_POWER_MANAGEMENT 0x06
+#define CPUID_THERMAL_POWER_MANAGEMENT 0x06
/**
CPUID Thermal and Power Management Information returned in EAX for CPUID leaf
@@ -1129,87 +1125,87 @@ typedef union {
///
/// [Bit 0] Digital temperature sensor is supported if set.
///
- UINT32 DigitalTemperatureSensor:1;
+ UINT32 DigitalTemperatureSensor : 1;
///
/// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]).
///
- UINT32 TurboBoostTechnology:1;
+ UINT32 TurboBoostTechnology : 1;
///
/// [Bit 2] APIC-Timer-always-running feature is supported if set.
///
- UINT32 ARAT:1;
- UINT32 Reserved1:1;
+ UINT32 ARAT : 1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 4] Power limit notification controls are supported if set.
///
- UINT32 PLN:1;
+ UINT32 PLN : 1;
///
/// [Bit 5] Clock modulation duty cycle extension is supported if set.
///
- UINT32 ECMD:1;
+ UINT32 ECMD : 1;
///
/// [Bit 6] Package thermal management is supported if set.
///
- UINT32 PTM:1;
+ UINT32 PTM : 1;
///
/// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES,
/// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.
///
- UINT32 HWP:1;
+ UINT32 HWP : 1;
///
/// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set.
///
- UINT32 HWP_Notification:1;
+ UINT32 HWP_Notification : 1;
///
/// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set.
///
- UINT32 HWP_Activity_Window:1;
+ UINT32 HWP_Activity_Window : 1;
///
/// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set.
///
- UINT32 HWP_Energy_Performance_Preference:1;
+ UINT32 HWP_Energy_Performance_Preference : 1;
///
/// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set.
///
- UINT32 HWP_Package_Level_Request:1;
- UINT32 Reserved2:1;
+ UINT32 HWP_Package_Level_Request : 1;
+ UINT32 Reserved2 : 1;
///
/// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1,
/// IA32_THREAD_STALL MSRs are supported if set.
///
- UINT32 HDC:1;
+ UINT32 HDC : 1;
///
/// [Bit 14] Intel Turbo Boost Max Technology 3.0 available.
///
- UINT32 TurboBoostMaxTechnology30:1;
+ UINT32 TurboBoostMaxTechnology30 : 1;
///
/// [Bit 15] HWP Capabilities.
/// Highest Performance change is supported if set.
///
- UINT32 HWPCapabilities:1;
+ UINT32 HWPCapabilities : 1;
///
/// [Bit 16] HWP PECI override is supported if set.
///
- UINT32 HWPPECIOverride:1;
+ UINT32 HWPPECIOverride : 1;
///
/// [Bit 17] Flexible HWP is supported if set.
///
- UINT32 FlexibleHWP:1;
+ UINT32 FlexibleHWP : 1;
///
/// [Bit 18] Fast access mode for the IA32_HWP_REQUEST MSR is supported if set.
///
- UINT32 FastAccessMode:1;
- UINT32 Reserved4:1;
+ UINT32 FastAccessMode : 1;
+ UINT32 Reserved4 : 1;
///
/// [Bit 20] Ignoring Idle Logical Processor HWP request is supported if set.
///
- UINT32 IgnoringIdleLogicalProcessorHWPRequest:1;
- UINT32 Reserved5:11;
+ UINT32 IgnoringIdleLogicalProcessorHWPRequest : 1;
+ UINT32 Reserved5 : 11;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_THERMAL_POWER_MANAGEMENT_EAX;
/**
@@ -1224,13 +1220,13 @@ typedef union {
///
/// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor.
///
- UINT32 InterruptThresholds:4;
- UINT32 Reserved:28;
+ UINT32 InterruptThresholds : 4;
+ UINT32 Reserved : 28;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_THERMAL_POWER_MANAGEMENT_EBX;
/**
@@ -1248,23 +1244,22 @@ typedef union {
/// processor performance (since last reset of the counters), as a percentage
/// of the expected processor performance when running at the TSC frequency.
///
- UINT32 HardwareCoordinationFeedback:1;
- UINT32 Reserved1:2;
+ UINT32 HardwareCoordinationFeedback : 1;
+ UINT32 Reserved1 : 2;
///
/// [Bit 3] If this bit is set, then the processor supports performance-energy
/// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS
/// (1B0H).
///
- UINT32 PerformanceEnergyBias:1;
- UINT32 Reserved2:28;
+ UINT32 PerformanceEnergyBias : 1;
+ UINT32 Reserved2 : 28;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_THERMAL_POWER_MANAGEMENT_ECX;
-
/**
CPUID Structured Extended Feature Flags Enumeration
@@ -1278,7 +1273,7 @@ typedef union {
@retval EAX The maximum input value for ECX to retrieve sub-leaf information.
@retval EBX Structured Extended Feature Flags described by the type
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX.
- @retval EBX Structured Extended Feature Flags described by the type
+ @retval ECX Structured Extended Feature Flags described by the type
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX.
@retval EDX Reserved.
@@ -1303,7 +1298,7 @@ typedef union {
}
@endcode
**/
-#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07
+#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07
///
/// CPUID Structured Extended Feature Flags Enumeration sub-leaf
@@ -1323,144 +1318,144 @@ typedef union {
///
/// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.
///
- UINT32 FSGSBASE:1;
+ UINT32 FSGSBASE : 1;
///
/// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1.
///
- UINT32 IA32_TSC_ADJUST:1;
+ UINT32 IA32_TSC_ADJUST : 1;
///
/// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT
/// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS".
///
- UINT32 SGX:1;
+ UINT32 SGX : 1;
///
/// [Bit 3] If 1 indicates the processor supports the first group of advanced
/// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)
///
- UINT32 BMI1:1;
+ UINT32 BMI1 : 1;
///
/// [Bit 4] Hardware Lock Elision
///
- UINT32 HLE:1;
+ UINT32 HLE : 1;
///
/// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions.
///
- UINT32 AVX2:1;
+ UINT32 AVX2 : 1;
///
/// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1.
///
- UINT32 FDP_EXCPTN_ONLY:1;
+ UINT32 FDP_EXCPTN_ONLY : 1;
///
/// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1.
///
- UINT32 SMEP:1;
+ UINT32 SMEP : 1;
///
/// [Bit 8] If 1 indicates the processor supports the second group of
/// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX,
/// SARX, SHLX, SHRX)
///
- UINT32 BMI2:1;
+ UINT32 BMI2 : 1;
///
/// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1.
///
- UINT32 EnhancedRepMovsbStosb:1;
+ UINT32 EnhancedRepMovsbStosb : 1;
///
/// [Bit 10] If 1, supports INVPCID instruction for system software that
/// manages process-context identifiers.
///
- UINT32 INVPCID:1;
+ UINT32 INVPCID : 1;
///
/// [Bit 11] Restricted Transactional Memory
///
- UINT32 RTM:1;
+ UINT32 RTM : 1;
///
/// [Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT)
/// Monitoring capability if 1.
///
- UINT32 RDT_M:1;
+ UINT32 RDT_M : 1;
///
/// [Bit 13] Deprecates FPU CS and FPU DS values if 1.
///
- UINT32 DeprecateFpuCsDs:1;
+ UINT32 DeprecateFpuCsDs : 1;
///
/// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1.
///
- UINT32 MPX:1;
+ UINT32 MPX : 1;
///
/// [Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT)
/// Allocation capability if 1.
///
- UINT32 RDT_A:1;
+ UINT32 RDT_A : 1;
///
/// [Bit 16] AVX512F.
///
- UINT32 AVX512F:1;
+ UINT32 AVX512F : 1;
///
/// [Bit 17] AVX512DQ.
///
- UINT32 AVX512DQ:1;
+ UINT32 AVX512DQ : 1;
///
/// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.
///
- UINT32 RDSEED:1;
+ UINT32 RDSEED : 1;
///
/// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX
/// instructions.
///
- UINT32 ADX:1;
+ UINT32 ADX : 1;
///
/// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC
/// instructions) if 1.
///
- UINT32 SMAP:1;
+ UINT32 SMAP : 1;
///
/// [Bit 21] AVX512_IFMA.
///
- UINT32 AVX512_IFMA:1;
- UINT32 Reserved6:1;
+ UINT32 AVX512_IFMA : 1;
+ UINT32 Reserved6 : 1;
///
/// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.
///
- UINT32 CLFLUSHOPT:1;
+ UINT32 CLFLUSHOPT : 1;
///
/// [Bit 24] If 1 indicates the processor supports the CLWB instruction.
///
- UINT32 CLWB:1;
+ UINT32 CLWB : 1;
///
/// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace
/// extensions.
///
- UINT32 IntelProcessorTrace:1;
+ UINT32 IntelProcessorTrace : 1;
///
/// [Bit 26] AVX512PF. (Intel Xeon Phi only.).
///
- UINT32 AVX512PF:1;
+ UINT32 AVX512PF : 1;
///
/// [Bit 27] AVX512ER. (Intel Xeon Phi only.).
///
- UINT32 AVX512ER:1;
+ UINT32 AVX512ER : 1;
///
/// [Bit 28] AVX512CD.
///
- UINT32 AVX512CD:1;
+ UINT32 AVX512CD : 1;
///
/// [Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R)
/// SHA Extensions) if 1.
///
- UINT32 SHA:1;
+ UINT32 SHA : 1;
///
/// [Bit 30] AVX512BW.
///
- UINT32 AVX512BW:1;
+ UINT32 AVX512BW : 1;
///
/// [Bit 31] AVX512VL.
///
- UINT32 AVX512VL:1;
+ UINT32 AVX512VL : 1;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX;
/**
@@ -1477,54 +1472,59 @@ typedef union {
/// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.
/// (Intel Xeon Phi only.)
///
- UINT32 PREFETCHWT1:1;
+ UINT32 PREFETCHWT1 : 1;
///
/// [Bit 1] AVX512_VBMI.
///
- UINT32 AVX512_VBMI:1;
+ UINT32 AVX512_VBMI : 1;
///
/// [Bit 2] Supports user-mode instruction prevention if 1.
///
- UINT32 UMIP:1;
+ UINT32 UMIP : 1;
///
/// [Bit 3] Supports protection keys for user-mode pages if 1.
///
- UINT32 PKU:1;
+ UINT32 PKU : 1;
///
/// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the
/// RDPKRU/WRPKRU instructions).
///
- UINT32 OSPKE:1;
- UINT32 Reserved5:9;
+ UINT32 OSPKE : 1;
+ UINT32 Reserved8 : 8;
+ ///
+ /// [Bit 13] If 1, the following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE,
+ /// IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE.
+ ///
+ UINT32 TME_EN : 1;
///
/// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.).
///
- UINT32 AVX512_VPOPCNTDQ:1;
- UINT32 Reserved7:1;
+ UINT32 AVX512_VPOPCNTDQ : 1;
+ UINT32 Reserved7 : 1;
///
/// [Bits 16] Supports 5-level paging if 1.
///
- UINT32 FiveLevelPage:1;
+ UINT32 FiveLevelPage : 1;
///
/// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions
/// in 64-bit mode.
///
- UINT32 MAWAU:5;
+ UINT32 MAWAU : 5;
///
/// [Bit 22] RDPID and IA32_TSC_AUX are available if 1.
///
- UINT32 RDPID:1;
- UINT32 Reserved3:7;
+ UINT32 RDPID : 1;
+ UINT32 Reserved3 : 7;
///
/// [Bit 30] Supports SGX Launch Configuration if 1.
///
- UINT32 SGX_LC:1;
- UINT32 Reserved4:1;
+ UINT32 SGX_LC : 1;
+ UINT32 Reserved4 : 1;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX;
/**
@@ -1540,19 +1540,27 @@ typedef union {
///
/// [Bit 1:0] Reserved.
///
- UINT32 Reserved1:2;
+ UINT32 Reserved1 : 2;
///
/// [Bit 2] AVX512_4VNNIW. (Intel Xeon Phi only.)
///
- UINT32 AVX512_4VNNIW:1;
+ UINT32 AVX512_4VNNIW : 1;
///
/// [Bit 3] AVX512_4FMAPS. (Intel Xeon Phi only.)
///
- UINT32 AVX512_4FMAPS:1;
+ UINT32 AVX512_4FMAPS : 1;
///
- /// [Bit 25:4] Reserved.
+ /// [Bit 14:4] Reserved.
///
- UINT32 Reserved2:22;
+ UINT32 Reserved4 : 11;
+ ///
+ /// [Bit 15] Hybrid. If 1, the processor is identified as a hybrid part.
+ ///
+ UINT32 Hybrid : 1;
+ ///
+ /// [Bit 25:16] Reserved.
+ ///
+ UINT32 Reserved5 : 10;
///
/// [Bit 26] Enumerates support for indirect branch restricted speculation
/// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processors
@@ -1560,39 +1568,39 @@ typedef union {
/// MSR. They allow software to set IA32_SPEC_CTRL[0] (IBRS) and
/// IA32_PRED_CMD[0] (IBPB).
///
- UINT32 EnumeratesSupportForIBRSAndIBPB:1;
+ UINT32 EnumeratesSupportForIBRSAndIBPB : 1;
///
/// [Bit 27] Enumerates support for single thread indirect branch
/// predictors (STIBP). Processors that set this bit support the
/// IA32_SPEC_CTRL MSR. They allow software to set IA32_SPEC_CTRL[1]
/// (STIBP).
///
- UINT32 EnumeratesSupportForSTIBP:1;
+ UINT32 EnumeratesSupportForSTIBP : 1;
///
/// [Bit 28] Enumerates support for L1D_FLUSH. Processors that set this bit
/// support the IA32_FLUSH_CMD MSR. They allow software to set
/// IA32_FLUSH_CMD[0] (L1D_FLUSH).
///
- UINT32 EnumeratesSupportForL1D_FLUSH:1;
+ UINT32 EnumeratesSupportForL1D_FLUSH : 1;
///
/// [Bit 29] Enumerates support for the IA32_ARCH_CAPABILITIES MSR.
///
- UINT32 EnumeratesSupportForCapability:1;
+ UINT32 EnumeratesSupportForCapability : 1;
///
- /// [Bit 30] Reserved.
+ /// [Bit 30] Enumerates support for the IA32_CORE_CAPABILITIES MSR.
///
- UINT32 Reserved3:1;
+ UINT32 EnumeratesSupportForCoreCapabilitiesMsr : 1;
///
/// [Bit 31] Enumerates support for Speculative Store Bypass Disable (SSBD).
/// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They allow
/// software to set IA32_SPEC_CTRL[2] (SSBD).
///
- UINT32 EnumeratesSupportForSSBD:1;
+ UINT32 EnumeratesSupportForSSBD : 1;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX;
/**
@@ -1612,8 +1620,7 @@ typedef union {
AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);
@endcode
**/
-#define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09
-
+#define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09
/**
CPUID Architectural Performance Monitoring
@@ -1651,7 +1658,7 @@ typedef union {
///
/// [Bit 7:0] Version ID of architectural performance monitoring.
///
- UINT32 ArchPerfMonVerID:8;
+ UINT32 ArchPerfMonVerID : 8;
///
/// [Bits 15:8] Number of general-purpose performance monitoring counter
/// per logical processor.
@@ -1661,7 +1668,7 @@ typedef union {
/// paired with a corresponding performance counter in the 0C1H address
/// block.
///
- UINT32 PerformanceMonitorCounters:8;
+ UINT32 PerformanceMonitorCounters : 8;
///
/// [Bits 23:16] Bit width of general-purpose, performance monitoring counter.
///
@@ -1670,17 +1677,17 @@ typedef union {
/// may be written with any value, and the high-order bits are sign-extended
/// from the value of bit 31.
///
- UINT32 PerformanceMonitorCounterWidth:8;
+ UINT32 PerformanceMonitorCounterWidth : 8;
///
/// [Bits 31:24] Length of EBX bit vector to enumerate architectural
/// performance monitoring events.
///
- UINT32 EbxBitVectorLength:8;
+ UINT32 EbxBitVectorLength : 8;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX;
/**
@@ -1695,37 +1702,37 @@ typedef union {
///
/// [Bit 0] Core cycle event not available if 1.
///
- UINT32 UnhaltedCoreCycles:1;
+ UINT32 UnhaltedCoreCycles : 1;
///
/// [Bit 1] Instruction retired event not available if 1.
///
- UINT32 InstructionsRetired:1;
+ UINT32 InstructionsRetired : 1;
///
/// [Bit 2] Reference cycles event not available if 1.
///
- UINT32 UnhaltedReferenceCycles:1;
+ UINT32 UnhaltedReferenceCycles : 1;
///
/// [Bit 3] Last-level cache reference event not available if 1.
///
- UINT32 LastLevelCacheReferences:1;
+ UINT32 LastLevelCacheReferences : 1;
///
/// [Bit 4] Last-level cache misses event not available if 1.
///
- UINT32 LastLevelCacheMisses:1;
+ UINT32 LastLevelCacheMisses : 1;
///
/// [Bit 5] Branch instruction retired event not available if 1.
///
- UINT32 BranchInstructionsRetired:1;
+ UINT32 BranchInstructionsRetired : 1;
///
/// [Bit 6] Branch mispredict retired event not available if 1.
///
- UINT32 AllBranchMispredictRetired:1;
- UINT32 Reserved:25;
+ UINT32 AllBranchMispredictRetired : 1;
+ UINT32 Reserved : 25;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX;
/**
@@ -1741,26 +1748,25 @@ typedef union {
/// [Bits 4:0] Number of fixed-function performance counters
/// (if Version ID > 1).
///
- UINT32 FixedFunctionPerformanceCounters:5;
+ UINT32 FixedFunctionPerformanceCounters : 5;
///
/// [Bits 12:5] Bit width of fixed-function performance counters
/// (if Version ID > 1).
///
- UINT32 FixedFunctionPerformanceCounterWidth:8;
- UINT32 Reserved1:2;
+ UINT32 FixedFunctionPerformanceCounterWidth : 8;
+ UINT32 Reserved1 : 2;
///
/// [Bits 15] AnyThread deprecation.
///
- UINT32 AnyThreadDeprecation:1;
- UINT32 Reserved2:16;
+ UINT32 AnyThreadDeprecation : 1;
+ UINT32 Reserved2 : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX;
-
/**
CPUID Extended Topology Information
@@ -1806,7 +1812,7 @@ typedef union {
} while (Eax.Bits.ApicIdShift != 0);
@endcode
**/
-#define CPUID_EXTENDED_TOPOLOGY 0x0B
+#define CPUID_EXTENDED_TOPOLOGY 0x0B
/**
CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
@@ -1825,13 +1831,13 @@ typedef union {
/// Software should use this field (EAX[4:0]) to enumerate processor
/// topology of the system.
///
- UINT32 ApicIdShift:5;
- UINT32 Reserved:27;
+ UINT32 ApicIdShift : 5;
+ UINT32 Reserved : 27;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_EXTENDED_TOPOLOGY_EAX;
/**
@@ -1853,13 +1859,13 @@ typedef union {
/// available to BIOS/OS/Applications may be different from the value of
/// EBX[15:0], depending on software and platform hardware configurations.
///
- UINT32 LogicalProcessors:16;
- UINT32 Reserved:16;
+ UINT32 LogicalProcessors : 16;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_EXTENDED_TOPOLOGY_EBX;
/**
@@ -1873,7 +1879,7 @@ typedef union {
///
/// [Bits 7:0] Level number. Same value in ECX input.
///
- UINT32 LevelNumber:8;
+ UINT32 LevelNumber : 8;
///
/// [Bits 15:8] Level type.
///
@@ -1881,26 +1887,25 @@ typedef union {
/// The value of the "level type" field is not related to level numbers in
/// any way, higher "level type" values do not mean higher levels.
///
- UINT32 LevelType:8;
- UINT32 Reserved:16;
+ UINT32 LevelType : 8;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_EXTENDED_TOPOLOGY_ECX;
///
/// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType
///
-#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00
-#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01
-#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02
+#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00
+#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01
+#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02
///
/// @}
///
-
/**
CPUID Extended State Information
@@ -1910,7 +1915,7 @@ typedef union {
CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02).
Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.
**/
-#define CPUID_EXTENDED_STATE 0x0D
+#define CPUID_EXTENDED_STATE 0x0D
/**
CPUID Extended State Information Main Leaf
@@ -1945,7 +1950,7 @@ typedef union {
);
@endcode
**/
-#define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00
+#define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00
/**
CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
@@ -1959,42 +1964,42 @@ typedef union {
///
/// [Bit 0] x87 state.
///
- UINT32 x87:1;
+ UINT32 x87 : 1;
///
/// [Bit 1] SSE state.
///
- UINT32 SSE:1;
+ UINT32 SSE : 1;
///
/// [Bit 2] AVX state.
///
- UINT32 AVX:1;
+ UINT32 AVX : 1;
///
/// [Bits 4:3] MPX state.
///
- UINT32 MPX:2;
+ UINT32 MPX : 2;
///
/// [Bits 7:5] AVX-512 state.
///
- UINT32 AVX_512:3;
+ UINT32 AVX_512 : 3;
///
/// [Bit 8] Used for IA32_XSS.
///
- UINT32 IA32_XSS:1;
+ UINT32 IA32_XSS : 1;
///
/// [Bit 9] PKRU state.
///
- UINT32 PKRU:1;
- UINT32 Reserved1:3;
+ UINT32 PKRU : 1;
+ UINT32 Reserved1 : 3;
///
/// [Bit 13] Used for IA32_XSS, part 2.
///
- UINT32 IA32_XSS_2:1;
- UINT32 Reserved2:18;
+ UINT32 IA32_XSS_2 : 1;
+ UINT32 Reserved2 : 18;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_EXTENDED_STATE_MAIN_LEAF_EAX;
/**
@@ -2025,7 +2030,7 @@ typedef union {
);
@endcode
**/
-#define CPUID_EXTENDED_STATE_SUB_LEAF 0x01
+#define CPUID_EXTENDED_STATE_SUB_LEAF 0x01
/**
CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
@@ -2039,25 +2044,25 @@ typedef union {
///
/// [Bit 0] XSAVEOPT is available.
///
- UINT32 XSAVEOPT:1;
+ UINT32 XSAVEOPT : 1;
///
/// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set.
///
- UINT32 XSAVEC:1;
+ UINT32 XSAVEC : 1;
///
/// [Bit 2] Supports XGETBV with ECX = 1 if set.
///
- UINT32 XGETBV:1;
+ UINT32 XGETBV : 1;
///
/// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set.
///
- UINT32 XSAVES:1;
- UINT32 Reserved:28;
+ UINT32 XSAVES : 1;
+ UINT32 Reserved : 28;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_EXTENDED_STATE_SUB_LEAF_EAX;
/**
@@ -2072,26 +2077,26 @@ typedef union {
///
/// [Bits 7:0] Used for XCR0.
///
- UINT32 XCR0:1;
+ UINT32 XCR0 : 1;
///
/// [Bit 8] PT STate.
///
- UINT32 PT:1;
+ UINT32 PT : 1;
///
/// [Bit 9] Used for XCR0.
///
- UINT32 XCR0_1:1;
- UINT32 Reserved1:3;
+ UINT32 XCR0_1 : 1;
+ UINT32 Reserved1 : 3;
///
/// [Bit 13] HWP state.
///
- UINT32 HWPState:1;
- UINT32 Reserved8:18;
+ UINT32 HWPState : 1;
+ UINT32 Reserved8 : 18;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_EXTENDED_STATE_SUB_LEAF_ECX;
/**
@@ -2139,7 +2144,7 @@ typedef union {
}
@endcode
**/
-#define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02
+#define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02
/**
CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
@@ -2155,23 +2160,22 @@ typedef union {
/// supported in the IA32_XSS MSR; it is clear if bit n is instead supported
/// in XCR0.
///
- UINT32 XSS:1;
+ UINT32 XSS : 1;
///
/// [Bit 1] is set if, when the compacted format of an XSAVE area is used,
/// this extended state component located on the next 64-byte boundary
/// following the preceding state component (otherwise, it is located
/// immediately following the preceding state component).
///
- UINT32 Compacted:1;
- UINT32 Reserved:30;
+ UINT32 Compacted : 1;
+ UINT32 Reserved : 30;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX;
-
/**
CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information
@@ -2180,7 +2184,7 @@ typedef union {
CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01).
**/
-#define CPUID_INTEL_RDT_MONITORING 0x0F
+#define CPUID_INTEL_RDT_MONITORING 0x0F
/**
CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information
@@ -2207,7 +2211,7 @@ typedef union {
);
@endcode
**/
-#define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00
+#define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00
/**
CPUID Intel RDT Monitoring Information EDX for CPUID leaf
@@ -2219,17 +2223,17 @@ typedef union {
/// Individual bit fields
///
struct {
- UINT32 Reserved1:1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1.
///
- UINT32 L3CacheRDT_M:1;
- UINT32 Reserved2:30;
+ UINT32 L3CacheRDT_M : 1;
+ UINT32 Reserved2 : 30;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX;
/**
@@ -2256,7 +2260,7 @@ typedef union {
);
@endcode
**/
-#define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01
+#define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01
/**
CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf
@@ -2271,24 +2275,23 @@ typedef union {
///
/// [Bit 0] Supports L3 occupancy monitoring if 1.
///
- UINT32 L3CacheOccupancyMonitoring:1;
+ UINT32 L3CacheOccupancyMonitoring : 1;
///
/// [Bit 1] Supports L3 Total Bandwidth monitoring if 1.
///
- UINT32 L3CacheTotalBandwidthMonitoring:1;
+ UINT32 L3CacheTotalBandwidthMonitoring : 1;
///
/// [Bit 2] Supports L3 Local Bandwidth monitoring if 1.
///
- UINT32 L3CacheLocalBandwidthMonitoring:1;
- UINT32 Reserved:29;
+ UINT32 L3CacheLocalBandwidthMonitoring : 1;
+ UINT32 Reserved : 29;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX;
-
/**
CPUID Intel Resource Director Technology (Intel RDT) Allocation Information
@@ -2297,7 +2300,7 @@ typedef union {
CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01).
CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02).
**/
-#define CPUID_INTEL_RDT_ALLOCATION 0x10
+#define CPUID_INTEL_RDT_ALLOCATION 0x10
/**
Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf
@@ -2321,7 +2324,7 @@ typedef union {
);
@endcode
**/
-#define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00
+#define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00
/**
CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf
@@ -2333,28 +2336,27 @@ typedef union {
/// Individual bit fields
///
struct {
- UINT32 Reserved1:1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 1] Supports L3 Cache Allocation Technology if 1.
///
- UINT32 L3CacheAllocation:1;
+ UINT32 L3CacheAllocation : 1;
///
/// [Bit 2] Supports L2 Cache Allocation Technology if 1.
///
- UINT32 L2CacheAllocation:1;
+ UINT32 L2CacheAllocation : 1;
///
/// [Bit 3] Supports Memory Bandwidth Allocation if 1.
///
- UINT32 MemoryBandwidth:1;
- UINT32 Reserved3:28;
+ UINT32 MemoryBandwidth : 1;
+ UINT32 Reserved3 : 28;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX;
-
/**
L3 Cache Allocation Technology Enumeration Sub-leaf
@@ -2382,7 +2384,7 @@ typedef union {
);
@endcode
**/
-#define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01
+#define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01
/**
CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf
@@ -2398,13 +2400,13 @@ typedef union {
/// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID
/// using minus-one notation.
///
- UINT32 CapacityLength:5;
- UINT32 Reserved:27;
+ UINT32 CapacityLength : 5;
+ UINT32 Reserved : 27;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX;
/**
@@ -2417,17 +2419,17 @@ typedef union {
/// Individual bit fields
///
struct {
- UINT32 Reserved3:2;
+ UINT32 Reserved3 : 2;
///
/// [Bit 2] Code and Data Prioritization Technology supported if 1.
///
- UINT32 CodeDataPrioritization:1;
- UINT32 Reserved2:29;
+ UINT32 CodeDataPrioritization : 1;
+ UINT32 Reserved2 : 29;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX;
/**
@@ -2443,13 +2445,13 @@ typedef union {
///
/// [Bits 15:0] Highest COS number supported for this ResID.
///
- UINT32 HighestCosNumber:16;
- UINT32 Reserved:16;
+ UINT32 HighestCosNumber : 16;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX;
/**
@@ -2477,7 +2479,7 @@ typedef union {
);
@endcode
**/
-#define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02
+#define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02
/**
CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf
@@ -2493,13 +2495,13 @@ typedef union {
/// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID
/// using minus-one notation.
///
- UINT32 CapacityLength:5;
- UINT32 Reserved:27;
+ UINT32 CapacityLength : 5;
+ UINT32 Reserved : 27;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX;
/**
@@ -2515,13 +2517,13 @@ typedef union {
///
/// [Bits 15:0] Highest COS number supported for this ResID.
///
- UINT32 HighestCosNumber:16;
- UINT32 Reserved:16;
+ UINT32 HighestCosNumber : 16;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX;
/**
@@ -2555,7 +2557,7 @@ typedef union {
);
@endcode
**/
-#define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03
+#define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03
/**
CPUID memory bandwidth Allocation Technology Information EAX for CPUID leaf
@@ -2571,13 +2573,13 @@ typedef union {
/// [Bits 11:0] Reports the maximum MBA throttling value supported for
/// the corresponding ResID using minus-one notation.
///
- UINT32 MaximumMBAThrottling:12;
- UINT32 Reserved:20;
+ UINT32 MaximumMBAThrottling : 12;
+ UINT32 Reserved : 20;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX;
/**
@@ -2593,17 +2595,17 @@ typedef union {
///
/// [Bits 1:0] Reserved.
///
- UINT32 Reserved1:2;
+ UINT32 Reserved1 : 2;
///
/// [Bits 3] Reports whether the response of the delay values is linear.
///
- UINT32 Liner:1;
- UINT32 Reserved2:29;
+ UINT32 Liner : 1;
+ UINT32 Reserved2 : 29;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX;
/**
@@ -2619,13 +2621,13 @@ typedef union {
///
/// [Bits 15:0] Highest COS number supported for this ResID.
///
- UINT32 HighestCosNumber:16;
- UINT32 Reserved:16;
+ UINT32 HighestCosNumber : 16;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX;
/**
@@ -2643,7 +2645,7 @@ typedef union {
until the sub-leaf type is invalid.
**/
-#define CPUID_INTEL_SGX 0x12
+#define CPUID_INTEL_SGX 0x12
/**
Sub-Leaf 0 Enumeration of Intel SGX Capabilities.
@@ -2672,7 +2674,7 @@ typedef union {
);
@endcode
**/
-#define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00
+#define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00
/**
Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX,
@@ -2686,28 +2688,28 @@ typedef union {
///
/// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported.
///
- UINT32 SGX1:1;
+ UINT32 SGX1 : 1;
///
/// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.
///
- UINT32 SGX2:1;
- UINT32 Reserved1:3;
+ UINT32 SGX2 : 1;
+ UINT32 Reserved1 : 3;
///
/// [Bit 5] If 1, indicates Intel SGX supports ENCLV instruction leaves
/// EINCVIRTCHILD, EDECVIRTCHILD, and ESETCONTEXT.
///
- UINT32 ENCLV:1;
+ UINT32 ENCLV : 1;
///
/// [Bit 6] If 1, indicates Intel SGX supports ENCLS instruction leaves ETRACKC,
/// ERDINFO, ELDBC, and ELDUC.
///
- UINT32 ENCLS:1;
- UINT32 Reserved2:25;
+ UINT32 ENCLS : 1;
+ UINT32 Reserved2 : 25;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX;
/**
@@ -2723,21 +2725,20 @@ typedef union {
/// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes
/// when not in 64-bit mode.
///
- UINT32 MaxEnclaveSize_Not64:8;
+ UINT32 MaxEnclaveSize_Not64 : 8;
///
/// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes
/// when operating in 64-bit mode.
///
- UINT32 MaxEnclaveSize_64:8;
- UINT32 Reserved:16;
+ UINT32 MaxEnclaveSize_64 : 8;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX;
-
/**
Sub-Leaf 1 Enumeration of Intel SGX Capabilities.
Enumerates Intel SGX capability of processor state configuration and enclave
@@ -2772,8 +2773,7 @@ typedef union {
);
@endcode
**/
-#define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01
-
+#define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01
/**
Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.
@@ -2826,18 +2826,18 @@ typedef union {
/// in EBX:EAX and EDX:ECX.
/// All other encoding are reserved.
///
- UINT32 SubLeafType:4;
- UINT32 Reserved:8;
+ UINT32 SubLeafType : 4;
+ UINT32 Reserved : 8;
///
/// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of
/// the base of the EPC section.
///
- UINT32 LowAddressOfEpcSection:20;
+ UINT32 LowAddressOfEpcSection : 20;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX;
/**
@@ -2853,13 +2853,13 @@ typedef union {
/// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of
/// the base of the EPC section.
///
- UINT32 HighAddressOfEpcSection:20;
- UINT32 Reserved:12;
+ UINT32 HighAddressOfEpcSection : 20;
+ UINT32 Reserved : 12;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX;
/**
@@ -2877,18 +2877,18 @@ typedef union {
/// 0001b: The EPC section is confidentiality, integrity and replay protected.
/// All other encoding are reserved.
///
- UINT32 EpcSection:4;
- UINT32 Reserved:8;
+ UINT32 EpcSection : 4;
+ UINT32 Reserved : 8;
///
/// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the
/// corresponding EPC section within the Processor Reserved Memory.
///
- UINT32 LowSizeOfEpcSection:20;
+ UINT32 LowSizeOfEpcSection : 20;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX;
/**
@@ -2904,16 +2904,15 @@ typedef union {
/// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the
/// corresponding EPC section within the Processor Reserved Memory.
///
- UINT32 HighSizeOfEpcSection:20;
- UINT32 Reserved:12;
+ UINT32 HighSizeOfEpcSection : 20;
+ UINT32 Reserved : 12;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX;
-
/**
CPUID Intel Processor Trace Information
@@ -2922,7 +2921,7 @@ typedef union {
CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01).
**/
-#define CPUID_INTEL_PROCESSOR_TRACE 0x14
+#define CPUID_INTEL_PROCESSOR_TRACE 0x14
/**
CPUID Intel Processor Trace Information Main Leaf
@@ -2949,7 +2948,7 @@ typedef union {
);
@endcode
**/
-#define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00
+#define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00
/**
CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
@@ -2964,40 +2963,40 @@ typedef union {
/// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,
/// and that IA32_RTIT_CR3_MATCH MSR can be accessed.
///
- UINT32 Cr3Filter:1;
+ UINT32 Cr3Filter : 1;
///
/// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate
/// Mode.
///
- UINT32 ConfigurablePsb:1;
+ UINT32 ConfigurablePsb : 1;
///
/// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering,
/// and preservation of Intel PT MSRs across warm reset.
///
- UINT32 IpTraceStopFiltering:1;
+ UINT32 IpTraceStopFiltering : 1;
///
/// [Bit 3] If 1, indicates support of MTC timing packet and suppression of
/// COFI-based packets.
///
- UINT32 Mtc:1;
+ UINT32 Mtc : 1;
///
/// [Bit 4] If 1, indicates support of PTWRITE. Writes can set
/// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE
/// can generate packets.
///
- UINT32 PTWrite:1;
+ UINT32 PTWrite : 1;
///
/// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set
/// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet
/// generation.
///
- UINT32 PowerEventTrace:1;
- UINT32 Reserved:26;
+ UINT32 PowerEventTrace : 1;
+ UINT32 Reserved : 26;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX;
/**
@@ -3014,35 +3013,34 @@ typedef union {
/// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and
/// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.
///
- UINT32 RTIT:1;
+ UINT32 RTIT : 1;
///
/// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to
/// the maximum allowed by the MaskOrTableOffset field of
/// IA32_RTIT_OUTPUT_MASK_PTRS.
///
- UINT32 ToPA:1;
+ UINT32 ToPA : 1;
///
/// [Bit 2] If 1, indicates support of Single-Range Output scheme.
///
- UINT32 SingleRangeOutput:1;
+ UINT32 SingleRangeOutput : 1;
///
/// [Bit 3] If 1, indicates support of output to Trace Transport subsystem.
///
- UINT32 TraceTransportSubsystem:1;
- UINT32 Reserved:27;
+ UINT32 TraceTransportSubsystem : 1;
+ UINT32 Reserved : 27;
///
/// [Bit 31] If 1, generated packets which contain IP payloads have LIP
/// values, which include the CS base component.
///
- UINT32 LIP:1;
+ UINT32 LIP : 1;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX;
-
/**
CPUID Intel Processor Trace Information Sub-leaf
@@ -3076,7 +3074,7 @@ typedef union {
}
@endcode
**/
-#define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01
+#define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01
/**
CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
@@ -3090,18 +3088,17 @@ typedef union {
///
/// [Bits 2:0] Number of configurable Address Ranges for filtering.
///
- UINT32 ConfigurableAddressRanges:3;
- UINT32 Reserved:13;
+ UINT32 ConfigurableAddressRanges : 3;
+ UINT32 Reserved : 13;
///
/// [Bits 31:16] Bitmap of supported MTC period encodings
///
- UINT32 MtcPeriodEncodings:16;
-
+ UINT32 MtcPeriodEncodings : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX;
/**
@@ -3116,20 +3113,18 @@ typedef union {
///
/// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings.
///
- UINT32 CycleThresholdEncodings:16;
+ UINT32 CycleThresholdEncodings : 16;
///
/// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings.
///
- UINT32 PsbFrequencyEncodings:16;
-
+ UINT32 PsbFrequencyEncodings : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX;
-
/**
CPUID Time Stamp Counter and Nominal Core Crystal Clock Information
@@ -3161,8 +3156,7 @@ typedef union {
AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);
@endcode
**/
-#define CPUID_TIME_STAMP_COUNTER 0x15
-
+#define CPUID_TIME_STAMP_COUNTER 0x15
/**
CPUID Processor Frequency Information
@@ -3197,7 +3191,7 @@ typedef union {
AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
@endcode
**/
-#define CPUID_PROCESSOR_FREQUENCY 0x16
+#define CPUID_PROCESSOR_FREQUENCY 0x16
/**
CPUID Processor Frequency Information EAX for CPUID leaf
@@ -3211,13 +3205,13 @@ typedef union {
///
/// [Bits 15:0] Processor Base Frequency (in MHz).
///
- UINT32 ProcessorBaseFrequency:16;
- UINT32 Reserved:16;
+ UINT32 ProcessorBaseFrequency : 16;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_PROCESSOR_FREQUENCY_EAX;
/**
@@ -3232,13 +3226,13 @@ typedef union {
///
/// [Bits 15:0] Maximum Frequency (in MHz).
///
- UINT32 MaximumFrequency:16;
- UINT32 Reserved:16;
+ UINT32 MaximumFrequency : 16;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_PROCESSOR_FREQUENCY_EBX;
/**
@@ -3253,16 +3247,15 @@ typedef union {
///
/// [Bits 15:0] Bus (Reference) Frequency (in MHz).
///
- UINT32 BusFrequency:16;
- UINT32 Reserved:16;
+ UINT32 BusFrequency : 16;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_PROCESSOR_FREQUENCY_ECX;
-
/**
CPUID SoC Vendor Information
@@ -3279,7 +3272,7 @@ typedef union {
EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.
**/
-#define CPUID_SOC_VENDOR 0x17
+#define CPUID_SOC_VENDOR 0x17
/**
CPUID SoC Vendor Information
@@ -3309,7 +3302,7 @@ typedef union {
);
@endcode
**/
-#define CPUID_SOC_VENDOR_MAIN_LEAF 0x00
+#define CPUID_SOC_VENDOR_MAIN_LEAF 0x00
/**
CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf
@@ -3323,19 +3316,19 @@ typedef union {
///
/// [Bits 15:0] SOC Vendor ID.
///
- UINT32 SocVendorId:16;
+ UINT32 SocVendorId : 16;
///
/// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry
/// standard enumeration scheme. Otherwise, the SOC Vendor ID field is
/// assigned by Intel.
///
- UINT32 IsVendorScheme:1;
- UINT32 Reserved:15;
+ UINT32 IsVendorScheme : 1;
+ UINT32 Reserved : 15;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_SOC_VENDOR_MAIN_LEAF_EBX;
/**
@@ -3366,7 +3359,7 @@ typedef union {
);
@endcode
**/
-#define CPUID_SOC_VENDOR_BRAND_STRING1 0x01
+#define CPUID_SOC_VENDOR_BRAND_STRING1 0x01
/**
CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1,
@@ -3376,11 +3369,11 @@ typedef union {
///
/// 4 UTF-8 characters of Soc Vendor Brand String
///
- CHAR8 BrandString[4];
+ CHAR8 BrandString[4];
///
/// All fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_SOC_VENDOR_BRAND_STRING_DATA;
/**
@@ -3411,7 +3404,7 @@ typedef union {
);
@endcode
**/
-#define CPUID_SOC_VENDOR_BRAND_STRING2 0x02
+#define CPUID_SOC_VENDOR_BRAND_STRING2 0x02
/**
CPUID SoC Vendor Information
@@ -3441,7 +3434,7 @@ typedef union {
);
@endcode
**/
-#define CPUID_SOC_VENDOR_BRAND_STRING3 0x03
+#define CPUID_SOC_VENDOR_BRAND_STRING3 0x03
/**
CPUID Deterministic Address Translation Parameters
@@ -3466,7 +3459,7 @@ typedef union {
CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_SUB_LEAF (0x*)
**/
-#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18
+#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18
/**
CPUID Deterministic Address Translation Parameters
@@ -3495,7 +3488,7 @@ typedef union {
);
@endcode
**/
-#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF 0x00
+#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF 0x00
/**
CPUID Deterministic Address Translation Parameters EBX for CPUID leafs.
@@ -3508,41 +3501,41 @@ typedef union {
///
/// [Bits 0] 4K page size entries supported by this structure.
///
- UINT32 Page4K:1;
+ UINT32 Page4K : 1;
///
/// [Bits 1] 2MB page size entries supported by this structure.
///
- UINT32 Page2M:1;
+ UINT32 Page2M : 1;
///
/// [Bits 2] 4MB page size entries supported by this structure.
///
- UINT32 Page4M:1;
+ UINT32 Page4M : 1;
///
/// [Bits 3] 1 GB page size entries supported by this structure.
///
- UINT32 Page1G:1;
+ UINT32 Page1G : 1;
///
/// [Bits 7:4] Reserved.
///
- UINT32 Reserved1:4;
+ UINT32 Reserved1 : 4;
///
/// [Bits 10:8] Partitioning (0: Soft partitioning between the logical
/// processors sharing this structure)
///
- UINT32 Partitioning:3;
+ UINT32 Partitioning : 3;
///
/// [Bits 15:11] Reserved.
///
- UINT32 Reserved2:5;
+ UINT32 Reserved2 : 5;
///
/// [Bits 31:16] W = Ways of associativity.
///
- UINT32 Way:16;
+ UINT32 Way : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX;
/**
@@ -3556,33 +3549,33 @@ typedef union {
///
/// [Bits 4:0] Translation cache type field.
///
- UINT32 TranslationCacheType:5;
+ UINT32 TranslationCacheType : 5;
///
/// [Bits 7:5] Translation cache level (starts at 1).
///
- UINT32 TranslationCacheLevel:3;
+ UINT32 TranslationCacheLevel : 3;
///
/// [Bits 8] Fully associative structure.
///
- UINT32 FullyAssociative:1;
+ UINT32 FullyAssociative : 1;
///
/// [Bits 13:9] Reserved.
///
- UINT32 Reserved1:5;
+ UINT32 Reserved1 : 5;
///
/// [Bits 25:14] Maximum number of addressable IDs for logical
/// processors sharing this translation cache.
///
- UINT32 MaximumNum:12;
+ UINT32 MaximumNum : 12;
///
/// [Bits 31:26] Reserved.
///
- UINT32 Reserved2:6;
+ UINT32 Reserved2 : 6;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX;
///
@@ -3596,6 +3589,74 @@ typedef union {
/// @}
///
+/**
+ CPUID Hybrid Information Enumeration Leaf
+
+ @param EAX CPUID_HYBRID_INFORMATION (0x1A)
+ @param ECX CPUID_HYBRID_INFORMATION_MAIN_LEAF (0x00).
+
+ @retval EAX Enumerates the native model ID and core type described
+ by the type CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX
+ @retval EBX Reserved.
+ @retval ECX Reserved.
+ @retval EDX Reserved.
+
+ Example usage
+ @code
+ CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX Eax;
+
+ AsmCpuidEx (
+ CPUID_HYBRID_INFORMATION,
+ CPUID_HYBRID_INFORMATION_MAIN_LEAF,
+ &Eax, NULL, NULL, NULL
+ );
+ @endcode
+
+**/
+#define CPUID_HYBRID_INFORMATION 0x1A
+
+///
+/// CPUID Hybrid Information Enumeration main leaf
+///
+#define CPUID_HYBRID_INFORMATION_MAIN_LEAF 0x00
+
+/**
+ CPUID Hybrid Information EAX for CPUID leaf #CPUID_HYBRID_INFORMATION,
+ main leaf #CPUID_HYBRID_INFORMATION_MAIN_LEAF.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 23:0] Native model ID of the core.
+ ///
+ /// The core-type and native mode ID can be used to uniquely identify
+ /// the microarchitecture of the core.This native model ID is not unique
+ /// across core types, and not related to the model ID reported in CPUID
+ /// leaf 01H, and does not identify the SOC.
+ ///
+ UINT32 NativeModelId : 24;
+ ///
+ /// [Bit 31:24] Core type
+ ///
+ UINT32 CoreType : 8;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX;
+
+///
+/// @{ Define value for CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX.CoreType
+///
+#define CPUID_CORE_TYPE_INTEL_ATOM 0x20
+#define CPUID_CORE_TYPE_INTEL_CORE 0x40
+///
+/// @}
+///
/**
CPUID V2 Extended Topology Enumeration Leaf
@@ -3621,16 +3682,45 @@ typedef union {
@param ECX Level number
**/
-#define CPUID_V2_EXTENDED_TOPOLOGY 0x1F
+#define CPUID_V2_EXTENDED_TOPOLOGY 0x1F
///
/// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType
/// The value of the "level type" field is not related to level numbers in
/// any way, higher "level type" values do not mean higher levels.
///
-#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE 0x03
-#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE 0x04
-#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE 0x05
+#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE 0x03
+#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE 0x04
+#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE 0x05
+///
+/// @}
+///
+
+/**
+ CPUID Guest TD Run Time Environment Enumeration Leaf
+
+ @note
+ Guest software can be designed to run either as a TD, as a legacy virtual machine,
+ or directly on the CPU, based on enumeration of its run-time environment.
+ CPUID leaf 21H emulation is done by the Intel TDX module. Sub-leaf 0 returns the values
+ shown below. Other sub-leaves return 0 in EAX/EBX/ECX/EDX.
+ EAX: 0x00000000
+ EBX: 0x65746E49 "Inte"
+ ECX: 0x20202020 " "
+ EDX: 0x5844546C "lTDX"
+
+ @param EAX CPUID_GUESTTD_RUNTIME_ENVIRONMENT (0x21)
+ @param ECX Level number
+
+**/
+#define CPUID_GUESTTD_RUNTIME_ENVIRONMENT 0x21
+
+///
+/// @{ CPUID Guest TD signature values returned by Intel processors
+///
+#define CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('I', 'n', 't', 'e')
+#define CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 (' ', ' ', ' ', ' ')
+#define CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('l', 'T', 'D', 'X')
///
/// @}
///
@@ -3652,8 +3742,7 @@ typedef union {
AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);
@endcode
**/
-#define CPUID_EXTENDED_FUNCTION 0x80000000
-
+#define CPUID_EXTENDED_FUNCTION 0x80000000
/**
CPUID Extended Processor Signature and Feature Bits
@@ -3676,7 +3765,7 @@ typedef union {
AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);
@endcode
**/
-#define CPUID_EXTENDED_CPU_SIG 0x80000001
+#define CPUID_EXTENDED_CPU_SIG 0x80000001
/**
CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf
@@ -3690,23 +3779,23 @@ typedef union {
///
/// [Bit 0] LAHF/SAHF available in 64-bit mode.
///
- UINT32 LAHF_SAHF:1;
- UINT32 Reserved1:4;
+ UINT32 LAHF_SAHF : 1;
+ UINT32 Reserved1 : 4;
///
/// [Bit 5] LZCNT.
///
- UINT32 LZCNT:1;
- UINT32 Reserved2:2;
+ UINT32 LZCNT : 1;
+ UINT32 Reserved2 : 2;
///
/// [Bit 8] PREFETCHW.
///
- UINT32 PREFETCHW:1;
- UINT32 Reserved3:23;
+ UINT32 PREFETCHW : 1;
+ UINT32 Reserved3 : 23;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_EXTENDED_CPU_SIG_ECX;
/**
@@ -3718,39 +3807,38 @@ typedef union {
/// Individual bit fields
///
struct {
- UINT32 Reserved1:11;
+ UINT32 Reserved1 : 11;
///
/// [Bit 11] SYSCALL/SYSRET available in 64-bit mode.
///
- UINT32 SYSCALL_SYSRET:1;
- UINT32 Reserved2:8;
+ UINT32 SYSCALL_SYSRET : 1;
+ UINT32 Reserved2 : 8;
///
/// [Bit 20] Execute Disable Bit available.
///
- UINT32 NX:1;
- UINT32 Reserved3:5;
+ UINT32 NX : 1;
+ UINT32 Reserved3 : 5;
///
/// [Bit 26] 1-GByte pages are available if 1.
///
- UINT32 Page1GB:1;
+ UINT32 Page1GB : 1;
///
/// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1.
///
- UINT32 RDTSCP:1;
- UINT32 Reserved4:1;
+ UINT32 RDTSCP : 1;
+ UINT32 Reserved4 : 1;
///
/// [Bit 29] Intel(R) 64 Architecture available if 1.
///
- UINT32 LM:1;
- UINT32 Reserved5:2;
+ UINT32 LM : 1;
+ UINT32 Reserved5 : 2;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_EXTENDED_CPU_SIG_EDX;
-
/**
CPUID Processor Brand String
@@ -3771,7 +3859,7 @@ typedef union {
AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
@endcode
**/
-#define CPUID_BRAND_STRING1 0x80000002
+#define CPUID_BRAND_STRING1 0x80000002
/**
CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1,
@@ -3781,11 +3869,11 @@ typedef union {
///
/// 4 ASCII characters of Processor Brand String
///
- CHAR8 BrandString[4];
+ CHAR8 BrandString[4];
///
/// All fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_BRAND_STRING_DATA;
/**
@@ -3808,7 +3896,7 @@ typedef union {
AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
@endcode
**/
-#define CPUID_BRAND_STRING2 0x80000003
+#define CPUID_BRAND_STRING2 0x80000003
/**
CPUID Processor Brand String
@@ -3830,8 +3918,7 @@ typedef union {
AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
@endcode
**/
-#define CPUID_BRAND_STRING3 0x80000004
-
+#define CPUID_BRAND_STRING3 0x80000004
/**
CPUID Extended Cache information
@@ -3851,7 +3938,7 @@ typedef union {
AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);
@endcode
**/
-#define CPUID_EXTENDED_CACHE_INFO 0x80000006
+#define CPUID_EXTENDED_CACHE_INFO 0x80000006
/**
CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO.
@@ -3864,23 +3951,23 @@ typedef union {
///
/// [Bits 7:0] Cache line size in bytes.
///
- UINT32 CacheLineSize:8;
- UINT32 Reserved:4;
+ UINT32 CacheLineSize : 8;
+ UINT32 Reserved : 4;
///
/// [Bits 15:12] L2 Associativity field. Supported values are in the range
/// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to
/// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL
///
- UINT32 L2Associativity:4;
+ UINT32 L2Associativity : 4;
///
/// [Bits 31:16] Cache size in 1K units.
///
- UINT32 CacheSize:16;
+ UINT32 CacheSize : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_EXTENDED_CACHE_INFO_ECX;
///
@@ -3920,7 +4007,7 @@ typedef union {
AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);
@endcode
**/
-#define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007
+#define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007
/**
CPUID Extended Time Stamp Counter information EDX for CPUID leaf
@@ -3931,20 +4018,19 @@ typedef union {
/// Individual bit fields
///
struct {
- UINT32 Reserved1:8;
+ UINT32 Reserved1 : 8;
///
/// [Bit 8] Invariant TSC available if 1.
///
- UINT32 InvariantTsc:1;
- UINT32 Reserved2:23;
+ UINT32 InvariantTsc : 1;
+ UINT32 Reserved2 : 23;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX;
-
/**
CPUID Linear Physical Address Size
@@ -3963,7 +4049,7 @@ typedef union {
AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);
@endcode
**/
-#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
+#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
/**
CPUID Linear Physical Address Size EAX for CPUID leaf
@@ -3981,17 +4067,17 @@ typedef union {
/// If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address
/// number supported should come from this field.
///
- UINT32 PhysicalAddressBits:8;
+ UINT32 PhysicalAddressBits : 8;
///
/// [Bits 15:8] Number of linear address bits.
///
- UINT32 LinearAddressBits:8;
- UINT32 Reserved:16;
+ UINT32 LinearAddressBits : 8;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_VIR_PHY_ADDRESS_SIZE_EAX;
#endif
diff --git a/MdePkg/Include/Register/Intel/LocalApic.h b/MdePkg/Include/Register/Intel/LocalApic.h
new file mode 100644
index 00000000..6afca8f3
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/LocalApic.h
@@ -0,0 +1,182 @@
+/** @file
+ IA32 Local APIC Definitions.
+
+ Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __INTEL_LOCAL_APIC_H__
+#define __INTEL_LOCAL_APIC_H__
+
+//
+// Definition for Local APIC registers and related values
+//
+#define XAPIC_ID_OFFSET 0x20
+#define XAPIC_VERSION_OFFSET 0x30
+#define XAPIC_EOI_OFFSET 0x0b0
+#define XAPIC_ICR_DFR_OFFSET 0x0e0
+#define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0
+#define XAPIC_ICR_LOW_OFFSET 0x300
+#define XAPIC_ICR_HIGH_OFFSET 0x310
+#define XAPIC_LVT_TIMER_OFFSET 0x320
+#define XAPIC_LVT_LINT0_OFFSET 0x350
+#define XAPIC_LVT_LINT1_OFFSET 0x360
+#define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380
+#define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390
+#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0
+
+#define X2APIC_MSR_BASE_ADDRESS 0x800
+#define X2APIC_MSR_ICR_ADDRESS 0x830
+
+#define LOCAL_APIC_DELIVERY_MODE_FIXED 0
+#define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1
+#define LOCAL_APIC_DELIVERY_MODE_SMI 2
+#define LOCAL_APIC_DELIVERY_MODE_NMI 4
+#define LOCAL_APIC_DELIVERY_MODE_INIT 5
+#define LOCAL_APIC_DELIVERY_MODE_STARTUP 6
+#define LOCAL_APIC_DELIVERY_MODE_EXTINT 7
+
+#define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0
+#define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1
+#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2
+#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3
+
+//
+// Local APIC Version Register.
+//
+typedef union {
+ struct {
+ UINT32 Version : 8; ///< The version numbers of the local APIC.
+ UINT32 Reserved0 : 8; ///< Reserved.
+ UINT32 MaxLvtEntry : 8; ///< Number of LVT entries minus 1.
+ UINT32 EoiBroadcastSuppression : 1; ///< 1 if EOI-broadcast suppression supported.
+ UINT32 Reserved1 : 7; ///< Reserved.
+ } Bits;
+ UINT32 Uint32;
+} LOCAL_APIC_VERSION;
+
+//
+// Low half of Interrupt Command Register (ICR).
+//
+typedef union {
+ struct {
+ UINT32 Vector : 8; ///< The vector number of the interrupt being sent.
+ UINT32 DeliveryMode : 3; ///< Specifies the type of IPI to be sent.
+ UINT32 DestinationMode : 1; ///< 0: physical destination mode, 1: logical destination mode.
+ UINT32 DeliveryStatus : 1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.
+ UINT32 Reserved0 : 1; ///< Reserved.
+ UINT32 Level : 1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.
+ UINT32 TriggerMode : 1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.
+ UINT32 Reserved1 : 2; ///< Reserved.
+ UINT32 DestinationShorthand : 2; ///< A shorthand notation to specify the destination of the interrupt.
+ UINT32 Reserved2 : 12; ///< Reserved.
+ } Bits;
+ UINT32 Uint32;
+} LOCAL_APIC_ICR_LOW;
+
+//
+// High half of Interrupt Command Register (ICR)
+//
+typedef union {
+ struct {
+ UINT32 Reserved0 : 24; ///< Reserved.
+ UINT32 Destination : 8; ///< Specifies the target processor or processors in xAPIC mode.
+ } Bits;
+ UINT32 Uint32; ///< Destination field expanded to 32-bit in x2APIC mode.
+} LOCAL_APIC_ICR_HIGH;
+
+//
+// Spurious-Interrupt Vector Register (SVR)
+//
+typedef union {
+ struct {
+ UINT32 SpuriousVector : 8; ///< Spurious Vector.
+ UINT32 SoftwareEnable : 1; ///< APIC Software Enable/Disable.
+ UINT32 FocusProcessorChecking : 1; ///< Focus Processor Checking.
+ UINT32 Reserved0 : 2; ///< Reserved.
+ UINT32 EoiBroadcastSuppression : 1; ///< EOI-Broadcast Suppression.
+ UINT32 Reserved1 : 19; ///< Reserved.
+ } Bits;
+ UINT32 Uint32;
+} LOCAL_APIC_SVR;
+
+//
+// Divide Configuration Register (DCR)
+//
+typedef union {
+ struct {
+ UINT32 DivideValue1 : 2; ///< Low 2 bits of the divide value.
+ UINT32 Reserved0 : 1; ///< Always 0.
+ UINT32 DivideValue2 : 1; ///< Highest 1 bit of the divide value.
+ UINT32 Reserved1 : 28; ///< Reserved.
+ } Bits;
+ UINT32 Uint32;
+} LOCAL_APIC_DCR;
+
+//
+// LVT Timer Register
+//
+typedef union {
+ struct {
+ UINT32 Vector : 8; ///< The vector number of the interrupt being sent.
+ UINT32 Reserved0 : 4; ///< Reserved.
+ UINT32 DeliveryStatus : 1; ///< 0: Idle, 1: send pending.
+ UINT32 Reserved1 : 3; ///< Reserved.
+ UINT32 Mask : 1; ///< 0: Not masked, 1: Masked.
+ UINT32 TimerMode : 1; ///< 0: One-shot, 1: Periodic.
+ UINT32 Reserved2 : 14; ///< Reserved.
+ } Bits;
+ UINT32 Uint32;
+} LOCAL_APIC_LVT_TIMER;
+
+//
+// LVT LINT0/LINT1 Register
+//
+typedef union {
+ struct {
+ UINT32 Vector : 8; ///< The vector number of the interrupt being sent.
+ UINT32 DeliveryMode : 3; ///< Specifies the type of interrupt to be sent.
+ UINT32 Reserved0 : 1; ///< Reserved.
+ UINT32 DeliveryStatus : 1; ///< 0: Idle, 1: send pending.
+ UINT32 InputPinPolarity : 1; ///< Interrupt Input Pin Polarity.
+ UINT32 RemoteIrr : 1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.
+ UINT32 TriggerMode : 1; ///< 0:edge, 1:level.
+ UINT32 Mask : 1; ///< 0: Not masked, 1: Masked.
+ UINT32 Reserved1 : 15; ///< Reserved.
+ } Bits;
+ UINT32 Uint32;
+} LOCAL_APIC_LVT_LINT;
+
+//
+// MSI Address Register
+//
+typedef union {
+ struct {
+ UINT32 Reserved0 : 2; ///< Reserved
+ UINT32 DestinationMode : 1; ///< Specifies the Destination Mode.
+ UINT32 RedirectionHint : 1; ///< Specifies the Redirection Hint.
+ UINT32 Reserved1 : 8; ///< Reserved.
+ UINT32 DestinationId : 8; ///< Specifies the Destination ID.
+ UINT32 BaseAddress : 12; ///< Must be 0FEEH
+ } Bits;
+ UINT32 Uint32;
+} LOCAL_APIC_MSI_ADDRESS;
+
+//
+// MSI Address Register
+//
+typedef union {
+ struct {
+ UINT32 Vector : 8; ///< Interrupt vector in range 010h..0FEH
+ UINT32 DeliveryMode : 3; ///< Specifies the type of interrupt to be sent.
+ UINT32 Reserved0 : 3; ///< Reserved.
+ UINT32 Level : 1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts.
+ UINT32 TriggerMode : 1; ///< 0:Edge, 1:Level.
+ UINT32 Reserved1 : 16; ///< Reserved.
+ UINT32 Reserved2 : 32; ///< Reserved.
+ } Bits;
+ UINT64 Uint64;
+} LOCAL_APIC_MSI_DATA;
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Microcode.h b/MdePkg/Include/Register/Intel/Microcode.h
new file mode 100644
index 00000000..71833023
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Microcode.h
@@ -0,0 +1,194 @@
+/** @file
+ Microcode Definitions.
+
+ Microcode Definitions based on contents of the
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual
+ Volume 3A, Section 9.11 Microcode Definitions
+
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3A,
+ June 2016, Chapter 9 Processor Management and Initialization, Section 9-11.
+
+**/
+
+#ifndef __INTEL_MICROCODE_H__
+#define __INTEL_MICROCODE_H__
+
+///
+/// CPU Microcode Date in BCD format
+///
+typedef union {
+ struct {
+ UINT32 Year : 16;
+ UINT32 Day : 8;
+ UINT32 Month : 8;
+ } Bits;
+ UINT32 Uint32;
+} CPU_MICROCODE_DATE;
+
+///
+/// CPU Microcode Processor Signature format
+///
+typedef union {
+ struct {
+ UINT32 Stepping : 4;
+ UINT32 Model : 4;
+ UINT32 Family : 4;
+ UINT32 Type : 2;
+ UINT32 Reserved1 : 2;
+ UINT32 ExtendedModel : 4;
+ UINT32 ExtendedFamily : 8;
+ UINT32 Reserved2 : 4;
+ } Bits;
+ UINT32 Uint32;
+} CPU_MICROCODE_PROCESSOR_SIGNATURE;
+
+#pragma pack (1)
+
+///
+/// Microcode Update Format definition
+///
+typedef struct {
+ ///
+ /// Version number of the update header
+ ///
+ UINT32 HeaderVersion;
+ ///
+ /// Unique version number for the update, the basis for the update
+ /// signature provided by the processor to indicate the current update
+ /// functioning within the processor. Used by the BIOS to authenticate
+ /// the update and verify that the processor loads successfully. The
+ /// value in this field cannot be used for processor stepping identification
+ /// alone. This is a signed 32-bit number.
+ ///
+ UINT32 UpdateRevision;
+ ///
+ /// Date of the update creation in binary format: mmddyyyy (e.g.
+ /// 07/18/98 is 07181998H).
+ ///
+ CPU_MICROCODE_DATE Date;
+ ///
+ /// Extended family, extended model, type, family, model, and stepping
+ /// of processor that requires this particular update revision (e.g.,
+ /// 00000650H). Each microcode update is designed specifically for a
+ /// given extended family, extended model, type, family, model, and
+ /// stepping of the processor.
+ /// The BIOS uses the processor signature field in conjunction with the
+ /// CPUID instruction to determine whether or not an update is
+ /// appropriate to load on a processor. The information encoded within
+ /// this field exactly corresponds to the bit representations returned by
+ /// the CPUID instruction.
+ ///
+ CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature;
+ ///
+ /// Checksum of Update Data and Header. Used to verify the integrity of
+ /// the update header and data. Checksum is correct when the
+ /// summation of all the DWORDs (including the extended Processor
+ /// Signature Table) that comprise the microcode update result in
+ /// 00000000H.
+ ///
+ UINT32 Checksum;
+ ///
+ /// Version number of the loader program needed to correctly load this
+ /// update. The initial version is 00000001H
+ ///
+ UINT32 LoaderRevision;
+ ///
+ /// Platform type information is encoded in the lower 8 bits of this 4-
+ /// byte field. Each bit represents a particular platform type for a given
+ /// CPUID. The BIOS uses the processor flags field in conjunction with
+ /// the platform Id bits in MSR (17H) to determine whether or not an
+ /// update is appropriate to load on a processor. Multiple bits may be set
+ /// representing support for multiple platform IDs.
+ ///
+ UINT32 ProcessorFlags;
+ ///
+ /// Specifies the size of the encrypted data in bytes, and must be a
+ /// multiple of DWORDs. If this value is 00000000H, then the microcode
+ /// update encrypted data is 2000 bytes (or 500 DWORDs).
+ ///
+ UINT32 DataSize;
+ ///
+ /// Specifies the total size of the microcode update in bytes. It is the
+ /// summation of the header size, the encrypted data size and the size of
+ /// the optional extended signature table. This value is always a multiple
+ /// of 1024.
+ ///
+ UINT32 TotalSize;
+ ///
+ /// Reserved fields for future expansion.
+ ///
+ UINT8 Reserved[12];
+} CPU_MICROCODE_HEADER;
+
+///
+/// Extended Signature Table Header Field Definitions
+///
+typedef struct {
+ ///
+ /// Specifies the number of extended signature structures (Processor
+ /// Signature[n], processor flags[n] and checksum[n]) that exist in this
+ /// microcode update
+ ///
+ UINT32 ExtendedSignatureCount;
+ ///
+ /// Checksum of update extended processor signature table. Used to
+ /// verify the integrity of the extended processor signature table.
+ /// Checksum is correct when the summation of the DWORDs that
+ /// comprise the extended processor signature table results in
+ /// 00000000H.
+ ///
+ UINT32 ExtendedChecksum;
+ ///
+ /// Reserved fields.
+ ///
+ UINT8 Reserved[12];
+} CPU_MICROCODE_EXTENDED_TABLE_HEADER;
+
+///
+/// Extended Signature Table Field Definitions
+///
+typedef struct {
+ ///
+ /// Extended family, extended model, type, family, model, and stepping
+ /// of processor that requires this particular update revision (e.g.,
+ /// 00000650H). Each microcode update is designed specifically for a
+ /// given extended family, extended model, type, family, model, and
+ /// stepping of the processor.
+ /// The BIOS uses the processor signature field in conjunction with the
+ /// CPUID instruction to determine whether or not an update is
+ /// appropriate to load on a processor. The information encoded within
+ /// this field exactly corresponds to the bit representations returned by
+ /// the CPUID instruction.
+ ///
+ CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature;
+ ///
+ /// Platform type information is encoded in the lower 8 bits of this 4-
+ /// byte field. Each bit represents a particular platform type for a given
+ /// CPUID. The BIOS uses the processor flags field in conjunction with
+ /// the platform Id bits in MSR (17H) to determine whether or not an
+ /// update is appropriate to load on a processor. Multiple bits may be set
+ /// representing support for multiple platform IDs.
+ ///
+ UINT32 ProcessorFlag;
+ ///
+ /// Used by utility software to decompose a microcode update into
+ /// multiple microcode updates where each of the new updates is
+ /// constructed without the optional Extended Processor Signature
+ /// Table.
+ /// To calculate the Checksum, substitute the Primary Processor
+ /// Signature entry and the Processor Flags entry with the
+ /// corresponding Extended Patch entry. Delete the Extended Processor
+ /// Signature Table entries. The Checksum is correct when the
+ /// summation of all DWORDs that comprise the created Extended
+ /// Processor Patch results in 00000000H.
+ ///
+ UINT32 Checksum;
+} CPU_MICROCODE_EXTENDED_TABLE;
+
+#pragma pack ()
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/ArchitecturalMsr.h b/MdePkg/Include/Register/Intel/Msr/ArchitecturalMsr.h
deleted file mode 100644
index 22b9ec36..00000000
--- a/MdePkg/Include/Register/Intel/Msr/ArchitecturalMsr.h
+++ /dev/null
@@ -1,6572 +0,0 @@
-/** @file
- Intel Architectural MSR Definitions.
-
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures
- are provided for MSRs that contain one or more bit fields. If the MSR value
- returned is a single 32-bit or 64-bit value, then a data structure is not
- provided for that MSR.
-
- Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
- May 2018, Volume 4: Model-Specific-Registers (MSR)
-
-**/
-
-#ifndef __INTEL_ARCHITECTURAL_MSR_H__
-#define __INTEL_ARCHITECTURAL_MSR_H__
-
-/**
- See Section 2.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
-
- @param ECX MSR_IA32_P5_MC_ADDR (0x00000000)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);
- AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);
- @endcode
- @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.
-**/
-#define MSR_IA32_P5_MC_ADDR 0x00000000
-
-
-/**
- See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.
-
- @param ECX MSR_IA32_P5_MC_TYPE (0x00000001)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);
- AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);
- @endcode
- @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.
-**/
-#define MSR_IA32_P5_MC_TYPE 0x00000001
-
-
-/**
- See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced
- at Display Family / Display Model 0F_03H.
-
- @param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);
- AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);
- @endcode
- @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.
-**/
-#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006
-
-
-/**
- See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family /
- Display Model 05_01H.
-
- @param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);
- AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);
- @endcode
- @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.
-**/
-#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010
-
-
-/**
- Platform ID (RO) The operating system can use this MSR to determine "slot"
- information for the processor and the proper microcode update to load.
- Introduced at Display Family / Display Model 06_01H.
-
- @param ECX MSR_IA32_PLATFORM_ID (0x00000017)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
-
- Example usage
- @code
- MSR_IA32_PLATFORM_ID_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);
- @endcode
- @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.
-**/
-#define MSR_IA32_PLATFORM_ID 0x00000017
-
-/**
- MSR information returned for MSR index #MSR_IA32_PLATFORM_ID
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:32;
- UINT32 Reserved2:18;
- ///
- /// [Bits 52:50] Platform Id (RO) Contains information concerning the
- /// intended platform for the processor.
- /// 52 51 50
- /// -- -- --
- /// 0 0 0 Processor Flag 0.
- /// 0 0 1 Processor Flag 1
- /// 0 1 0 Processor Flag 2
- /// 0 1 1 Processor Flag 3
- /// 1 0 0 Processor Flag 4
- /// 1 0 1 Processor Flag 5
- /// 1 1 0 Processor Flag 6
- /// 1 1 1 Processor Flag 7
- ///
- UINT32 PlatformId:3;
- UINT32 Reserved3:11;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PLATFORM_ID_REGISTER;
-
-
-/**
- 06_01H.
-
- @param ECX MSR_IA32_APIC_BASE (0x0000001B)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_APIC_BASE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_APIC_BASE_REGISTER.
-
- Example usage
- @code
- MSR_IA32_APIC_BASE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
- AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);
- @endcode
- @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.
-**/
-#define MSR_IA32_APIC_BASE 0x0000001B
-
-/**
- MSR information returned for MSR index #MSR_IA32_APIC_BASE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:8;
- ///
- /// [Bit 8] BSP flag (R/W).
- ///
- UINT32 BSP:1;
- UINT32 Reserved2:1;
- ///
- /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display
- /// Model 06_1AH.
- ///
- UINT32 EXTD:1;
- ///
- /// [Bit 11] APIC Global Enable (R/W).
- ///
- UINT32 EN:1;
- ///
- /// [Bits 31:12] APIC Base (R/W).
- ///
- UINT32 ApicBase:20;
- ///
- /// [Bits 63:32] APIC Base (R/W).
- ///
- UINT32 ApicBaseHi:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_APIC_BASE_REGISTER;
-
-
-/**
- Control Features in Intel 64 Processor (R/W). If any one enumeration
- condition for defined bit field holds.
-
- @param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
-
- Example usage
- @code
- MSR_IA32_FEATURE_CONTROL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);
- AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);
- @endcode
- @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
-**/
-#define MSR_IA32_FEATURE_CONTROL 0x0000003A
-
-/**
- MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from
- /// being written, writes to this bit will result in GP(0). Note: Once the
- /// Lock bit is set, the contents of this register cannot be modified.
- /// Therefore the lock bit must be set after configuring support for Intel
- /// Virtualization Technology and prior to transferring control to an
- /// option ROM or the OS. Hence, once the Lock bit is set, the entire
- /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD
- /// is not deasserted. If any one enumeration condition for defined bit
- /// field position greater than bit 0 holds.
- ///
- UINT32 Lock:1;
- ///
- /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a
- /// system executive to use VMX in conjunction with SMX to support
- /// Intel(R) Trusted Execution Technology. BIOS must set this bit only
- /// when the CPUID function 1 returns VMX feature flag and SMX feature
- /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&
- /// CPUID.01H:ECX[6] = 1.
- ///
- UINT32 EnableVmxInsideSmx:1;
- ///
- /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX
- /// for system executive that do not require SMX. BIOS must set this bit
- /// only when the CPUID function 1 returns VMX feature flag set (ECX bit
- /// 5). If CPUID.01H:ECX[5] = 1.
- ///
- UINT32 EnableVmxOutsideSmx:1;
- UINT32 Reserved1:5;
- ///
- /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit
- /// in the field represents an enable control for a corresponding SENTER
- /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If
- /// CPUID.01H:ECX[6] = 1.
- ///
- UINT32 SenterLocalFunctionEnables:7;
- ///
- /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable
- /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit
- /// 6] is set. If CPUID.01H:ECX[6] = 1.
- ///
- UINT32 SenterGlobalEnable:1;
- UINT32 Reserved2:1;
- ///
- /// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to
- /// enable runtime reconfiguration of SGX Launch Control via
- /// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.
- ///
- UINT32 SgxLaunchControlEnable:1;
- ///
- /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX
- /// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.
- ///
- UINT32 SgxEnable:1;
- UINT32 Reserved3:1;
- ///
- /// [Bit 20] LMCE On (R/WL): When set, system software can program the
- /// MSRs associated with LMCE to configure delivery of some machine check
- /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.
- ///
- UINT32 LmceOn:1;
- UINT32 Reserved4:11;
- UINT32 Reserved5:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_FEATURE_CONTROL_REGISTER;
-
-
-/**
- Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,
- ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for
- a logical processor. Reset value is Zero. A write to IA32_TSC will modify
- the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does
- not affect the internal invariant TSC hardware.
-
- @param ECX MSR_IA32_TSC_ADJUST (0x0000003B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);
- AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);
- @endcode
- @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.
-**/
-#define MSR_IA32_TSC_ADJUST 0x0000003B
-
-
-/**
- BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a
- microcode update to be loaded into the processor. See Section 9.11.6,
- "Microcode Update Loader." A processor may prevent writing to this MSR when
- loading guest states on VM entries or saving guest states on VM exits.
- Introduced at Display Family / Display Model 06_01H.
-
- @param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = 0;
- AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);
- @endcode
- @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.
-**/
-#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
-
-
-/**
- BIOS Update Signature (RO) Returns the microcode update signature following
- the execution of CPUID.01H. A processor may prevent writing to this MSR when
- loading guest states on VM entries or saving guest states on VM exits.
- Introduced at Display Family / Display Model 06_01H.
-
- @param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
-
- Example usage
- @code
- MSR_IA32_BIOS_SIGN_ID_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);
- @endcode
- @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.
-**/
-#define MSR_IA32_BIOS_SIGN_ID 0x0000008B
-
-/**
- MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved:32;
- ///
- /// [Bits 63:32] Microcode update signature. This field contains the
- /// signature of the currently loaded microcode update when read following
- /// the execution of the CPUID instruction, function 1. It is required
- /// that this register field be pre-loaded with zero prior to executing
- /// the CPUID, function 1. If the field remains equal to zero, then there
- /// is no microcode update loaded. Another nonzero value will be the
- /// signature.
- ///
- UINT32 MicrocodeUpdateSignature:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_BIOS_SIGN_ID_REGISTER;
-
-
-/**
- IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the
- SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the
- default value is the digest of Intel's signing key. Read permitted If
- CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H):
- EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1.
-
- @param ECX MSR_IA32_SGXLEPUBKEYHASHn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn);
- AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr);
- @endcode
- @note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM.
- MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM.
- MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM.
- MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.
- @{
-**/
-#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
-#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
-#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
-#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
-/// @}
-
-
-/**
- SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =
- 1.
-
- @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
-
- Example usage
- @code
- MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);
- AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);
- @endcode
- @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.
-**/
-#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B
-
-/**
- MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this
- /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment
- /// (see Section 34.15.6), the dual-monitor treatment cannot be activated
- /// if the bit is 0. This bit is cleared when the logical processor is
- /// reset.
- ///
- UINT32 Valid:1;
- UINT32 Reserved1:1;
- ///
- /// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If
- /// IA32_VMX_MISC[28].
- ///
- UINT32 BlockSmi:1;
- UINT32 Reserved2:9;
- ///
- /// [Bits 31:12] MSEG Base (R/W).
- ///
- UINT32 MsegBase:20;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_SMM_MONITOR_CTL_REGISTER;
-
-/**
- MSEG header that is located at the physical address specified by the MsegBase
- field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.
-**/
-typedef struct {
- ///
- /// Different processors may use different MSEG revision identifiers. These
- /// identifiers enable software to avoid using an MSEG header formatted for
- /// one processor on a processor that uses a different format. Software can
- /// discover the MSEG revision identifier that a processor uses by reading
- /// the VMX capability MSR IA32_VMX_MISC.
- //
- UINT32 MsegHeaderRevision;
- ///
- /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field
- /// is the IA-32e mode SMM feature bit. It indicates whether the logical
- /// processor will be in IA-32e mode after the STM is activated.
- ///
- UINT32 MonitorFeatures;
- UINT32 GdtrLimit;
- UINT32 GdtrBaseOffset;
- UINT32 CsSelector;
- UINT32 EipOffset;
- UINT32 EspOffset;
- UINT32 Cr3Offset;
- ///
- /// Pad header so total size is 2KB
- ///
- UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];
-} MSEG_HEADER;
-
-///
-/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER
-///
-#define STM_FEATURES_IA32E 0x1
-///
-/// @}
-///
-
-/**
- Base address of the logical processor's SMRAM image (RO, SMM only). If
- IA32_VMX_MISC[15].
-
- @param ECX MSR_IA32_SMBASE (0x0000009E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_SMBASE);
- @endcode
- @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.
-**/
-#define MSR_IA32_SMBASE 0x0000009E
-
-
-/**
- General Performance Counters (R/W).
- MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.
-
- @param ECX MSR_IA32_PMCn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_PMC0);
- AsmWriteMsr64 (MSR_IA32_PMC0, Msr);
- @endcode
- @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM.
- MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM.
- MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM.
- MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM.
- MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM.
- MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM.
- MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM.
- MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.
- @{
-**/
-#define MSR_IA32_PMC0 0x000000C1
-#define MSR_IA32_PMC1 0x000000C2
-#define MSR_IA32_PMC2 0x000000C3
-#define MSR_IA32_PMC3 0x000000C4
-#define MSR_IA32_PMC4 0x000000C5
-#define MSR_IA32_PMC5 0x000000C6
-#define MSR_IA32_PMC6 0x000000C7
-#define MSR_IA32_PMC7 0x000000C8
-/// @}
-
-
-/**
- TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.
- C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative
- to TSC freq.) when the logical processor is in C0. Cleared upon overflow /
- wrap-around of IA32_APERF.
-
- @param ECX MSR_IA32_MPERF (0x000000E7)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MPERF);
- AsmWriteMsr64 (MSR_IA32_MPERF, Msr);
- @endcode
- @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.
-**/
-#define MSR_IA32_MPERF 0x000000E7
-
-
-/**
- Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =
- 1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at
- the coordinated clock frequency, when the logical processor is in C0.
- Cleared upon overflow / wrap-around of IA32_MPERF.
-
- @param ECX MSR_IA32_APERF (0x000000E8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_APERF);
- AsmWriteMsr64 (MSR_IA32_APERF, Msr);
- @endcode
- @note MSR_IA32_APERF is defined as IA32_APERF in SDM.
-**/
-#define MSR_IA32_APERF 0x000000E8
-
-
-/**
- MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".
- Introduced at Display Family / Display Model 06_01H.
-
- @param ECX MSR_IA32_MTRRCAP (0x000000FE)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_MTRRCAP_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_MTRRCAP_REGISTER.
-
- Example usage
- @code
- MSR_IA32_MTRRCAP_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);
- @endcode
- @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.
-**/
-#define MSR_IA32_MTRRCAP 0x000000FE
-
-/**
- MSR information returned for MSR index #MSR_IA32_MTRRCAP
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] VCNT: The number of variable memory type ranges in the
- /// processor.
- ///
- UINT32 VCNT:8;
- ///
- /// [Bit 8] Fixed range MTRRs are supported when set.
- ///
- UINT32 FIX:1;
- UINT32 Reserved1:1;
- ///
- /// [Bit 10] WC Supported when set.
- ///
- UINT32 WC:1;
- ///
- /// [Bit 11] SMRR Supported when set.
- ///
- UINT32 SMRR:1;
- UINT32 Reserved2:20;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_MTRRCAP_REGISTER;
-
-
-/**
- SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
-
- @param ECX MSR_IA32_SYSENTER_CS (0x00000174)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
-
- Example usage
- @code
- MSR_IA32_SYSENTER_CS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);
- AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);
- @endcode
- @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.
-**/
-#define MSR_IA32_SYSENTER_CS 0x00000174
-
-/**
- MSR information returned for MSR index #MSR_IA32_SYSENTER_CS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] CS Selector.
- ///
- UINT32 CS:16;
- UINT32 Reserved1:16;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_SYSENTER_CS_REGISTER;
-
-
-/**
- SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
-
- @param ECX MSR_IA32_SYSENTER_ESP (0x00000175)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);
- AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);
- @endcode
- @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.
-**/
-#define MSR_IA32_SYSENTER_ESP 0x00000175
-
-
-/**
- SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
-
- @param ECX MSR_IA32_SYSENTER_EIP (0x00000176)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);
- AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);
- @endcode
- @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.
-**/
-#define MSR_IA32_SYSENTER_EIP 0x00000176
-
-
-/**
- Global Machine Check Capability (RO). Introduced at Display Family / Display
- Model 06_01H.
-
- @param ECX MSR_IA32_MCG_CAP (0x00000179)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_MCG_CAP_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_MCG_CAP_REGISTER.
-
- Example usage
- @code
- MSR_IA32_MCG_CAP_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
- @endcode
- @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
-**/
-#define MSR_IA32_MCG_CAP 0x00000179
-
-/**
- MSR information returned for MSR index #MSR_IA32_MCG_CAP
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Count: Number of reporting banks.
- ///
- UINT32 Count:8;
- ///
- /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.
- ///
- UINT32 MCG_CTL_P:1;
- ///
- /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present
- /// if this bit is set.
- ///
- UINT32 MCG_EXT_P:1;
- ///
- /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.
- /// Introduced at Display Family / Display Model 06_01H.
- ///
- UINT32 MCP_CMCI_P:1;
- ///
- /// [Bit 11] MCG_TES_P: Threshold-based error status register are present
- /// if this bit is set.
- ///
- UINT32 MCG_TES_P:1;
- UINT32 Reserved1:4;
- ///
- /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state
- /// registers present.
- ///
- UINT32 MCG_EXT_CNT:8;
- ///
- /// [Bit 24] MCG_SER_P: The processor supports software error recovery if
- /// this bit is set.
- ///
- UINT32 MCG_SER_P:1;
- UINT32 Reserved2:1;
- ///
- /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform
- /// firmware to be invoked when an error is detected so that it may
- /// provide additional platform specific information in an ACPI format
- /// "Generic Error Data Entry" that augments the data included in machine
- /// check bank registers. Introduced at Display Family / Display Model
- /// 06_3EH.
- ///
- UINT32 MCG_ELOG_P:1;
- ///
- /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended
- /// state in IA32_MCG_STATUS and associated MSR necessary to configure
- /// Local Machine Check Exception (LMCE). Introduced at Display Family /
- /// Display Model 06_3EH.
- ///
- UINT32 MCG_LMCE_P:1;
- UINT32 Reserved3:4;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_MCG_CAP_REGISTER;
-
-
-/**
- Global Machine Check Status (R/W0). Introduced at Display Family / Display
- Model 06_01H.
-
- @param ECX MSR_IA32_MCG_STATUS (0x0000017A)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_MCG_STATUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_MCG_STATUS_REGISTER.
-
- Example usage
- @code
- MSR_IA32_MCG_STATUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);
- AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);
- @endcode
- @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.
-**/
-#define MSR_IA32_MCG_STATUS 0x0000017A
-
-/**
- MSR information returned for MSR index #MSR_IA32_MCG_STATUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display
- /// Model 06_01H.
- ///
- UINT32 RIPV:1;
- ///
- /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display
- /// Model 06_01H.
- ///
- UINT32 EIPV:1;
- ///
- /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family
- /// / Display Model 06_01H.
- ///
- UINT32 MCIP:1;
- ///
- /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.
- ///
- UINT32 LMCE_S:1;
- UINT32 Reserved1:28;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_MCG_STATUS_REGISTER;
-
-
-/**
- Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.
-
- @param ECX MSR_IA32_MCG_CTL (0x0000017B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);
- AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);
- @endcode
- @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.
-**/
-#define MSR_IA32_MCG_CTL 0x0000017B
-
-
-/**
- Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.
-
- @param ECX MSR_IA32_PERFEVTSELn
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
-
- Example usage
- @code
- MSR_IA32_PERFEVTSEL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);
- AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);
- @endcode
- @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.
- MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.
- MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.
- MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.
- @{
-**/
-#define MSR_IA32_PERFEVTSEL0 0x00000186
-#define MSR_IA32_PERFEVTSEL1 0x00000187
-#define MSR_IA32_PERFEVTSEL2 0x00000188
-#define MSR_IA32_PERFEVTSEL3 0x00000189
-/// @}
-
-/**
- MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to
- #MSR_IA32_PERFEVTSEL3
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Event Select: Selects a performance event logic unit.
- ///
- UINT32 EventSelect:8;
- ///
- /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
- /// detect on the selected event logic.
- ///
- UINT32 UMASK:8;
- ///
- /// [Bit 16] USR: Counts while in privilege level is not ring 0.
- ///
- UINT32 USR:1;
- ///
- /// [Bit 17] OS: Counts while in privilege level is ring 0.
- ///
- UINT32 OS:1;
- ///
- /// [Bit 18] Edge: Enables edge detection if set.
- ///
- UINT32 E:1;
- ///
- /// [Bit 19] PC: enables pin control.
- ///
- UINT32 PC:1;
- ///
- /// [Bit 20] INT: enables interrupt on counter overflow.
- ///
- UINT32 INT:1;
- ///
- /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
- /// event conditions occurring across all logical processors sharing a
- /// processor core. When set to 0, the counter only increments the
- /// associated event conditions occurring in the logical processor which
- /// programmed the MSR.
- ///
- UINT32 ANY:1;
- ///
- /// [Bit 22] EN: enables the corresponding performance counter to commence
- /// counting when this bit is set.
- ///
- UINT32 EN:1;
- ///
- /// [Bit 23] INV: invert the CMASK.
- ///
- UINT32 INV:1;
- ///
- /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
- /// performance counter increments each cycle if the event count is
- /// greater than or equal to the CMASK.
- ///
- UINT32 CMASK:8;
- UINT32 Reserved:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PERFEVTSEL_REGISTER;
-
-
-/**
- Current performance state(P-State) operating point (RO). Introduced at
- Display Family / Display Model 0F_03H.
-
- @param ECX MSR_IA32_PERF_STATUS (0x00000198)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_STATUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_STATUS_REGISTER.
-
- Example usage
- @code
- MSR_IA32_PERF_STATUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS);
- @endcode
- @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM.
-**/
-#define MSR_IA32_PERF_STATUS 0x00000198
-
-/**
- MSR information returned for MSR index #MSR_IA32_PERF_STATUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] Current performance State Value.
- ///
- UINT32 State:16;
- UINT32 Reserved1:16;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PERF_STATUS_REGISTER;
-
-
-/**
- (R/W). Introduced at Display Family / Display Model 0F_03H.
-
- @param ECX MSR_IA32_PERF_CTL (0x00000199)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_CTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_CTL_REGISTER.
-
- Example usage
- @code
- MSR_IA32_PERF_CTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL);
- AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64);
- @endcode
- @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM.
-**/
-#define MSR_IA32_PERF_CTL 0x00000199
-
-/**
- MSR information returned for MSR index #MSR_IA32_PERF_CTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 15:0] Target performance State Value.
- ///
- UINT32 TargetState:16;
- UINT32 Reserved1:16;
- ///
- /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH
- /// (Mobile only).
- ///
- UINT32 IDA:1;
- UINT32 Reserved2:31;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PERF_CTL_REGISTER;
-
-
-/**
- Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled
- Clock Modulation.". If CPUID.01H:EDX[22] = 1.
-
- @param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.
-
- Example usage
- @code
- MSR_IA32_CLOCK_MODULATION_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);
- AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64);
- @endcode
- @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.
-**/
-#define MSR_IA32_CLOCK_MODULATION 0x0000019A
-
-/**
- MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If
- /// CPUID.06H:EAX[5] = 1.
- ///
- UINT32 ExtendedOnDemandClockModulationDutyCycle:1;
- ///
- /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded
- /// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1.
- ///
- UINT32 OnDemandClockModulationDutyCycle:3;
- ///
- /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.
- /// If CPUID.01H:EDX[22] = 1.
- ///
- UINT32 OnDemandClockModulationEnable:1;
- UINT32 Reserved1:27;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_CLOCK_MODULATION_REGISTER;
-
-
-/**
- Thermal Interrupt Control (R/W) Enables and disables the generation of an
- interrupt on temperature transitions detected with the processor's thermal
- sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".
- If CPUID.01H:EDX[22] = 1
-
- @param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.
-
- Example usage
- @code
- MSR_IA32_THERM_INTERRUPT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT);
- AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64);
- @endcode
- @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM.
-**/
-#define MSR_IA32_THERM_INTERRUPT 0x0000019B
-
-/**
- MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.
- ///
- UINT32 HighTempEnable:1;
- ///
- /// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.
- ///
- UINT32 LowTempEnable:1;
- ///
- /// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1.
- ///
- UINT32 PROCHOT_Enable:1;
- ///
- /// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1.
- ///
- UINT32 FORCEPR_Enable:1;
- ///
- /// [Bit 4] Critical Temperature Interrupt Enable.
- /// If CPUID.01H:EDX[22] = 1.
- ///
- UINT32 CriticalTempEnable:1;
- UINT32 Reserved1:3;
- ///
- /// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1.
- ///
- UINT32 Threshold1:7;
- ///
- /// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1.
- ///
- UINT32 Threshold1Enable:1;
- ///
- /// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1.
- ///
- UINT32 Threshold2:7;
- ///
- /// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1.
- ///
- UINT32 Threshold2Enable:1;
- ///
- /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.
- ///
- UINT32 PowerLimitNotificationEnable:1;
- UINT32 Reserved2:7;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_THERM_INTERRUPT_REGISTER;
-
-
-/**
- Thermal Status Information (RO) Contains status information about the
- processor's thermal sensor and automatic thermal monitoring facilities. See
- Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1.
-
- @param ECX MSR_IA32_THERM_STATUS (0x0000019C)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_THERM_STATUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_THERM_STATUS_REGISTER.
-
- Example usage
- @code
- MSR_IA32_THERM_STATUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS);
- @endcode
- @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM.
-**/
-#define MSR_IA32_THERM_STATUS 0x0000019C
-
-/**
- MSR information returned for MSR index #MSR_IA32_THERM_STATUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1.
- ///
- UINT32 ThermalStatus:1;
- ///
- /// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1.
- ///
- UINT32 ThermalStatusLog:1;
- ///
- /// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1.
- ///
- UINT32 PROCHOT_FORCEPR_Event:1;
- ///
- /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1.
- ///
- UINT32 PROCHOT_FORCEPR_Log:1;
- ///
- /// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1.
- ///
- UINT32 CriticalTempStatus:1;
- ///
- /// [Bit 5] Critical Temperature Status log (R/WC0).
- /// If CPUID.01H:EDX[22] = 1.
- ///
- UINT32 CriticalTempStatusLog:1;
- ///
- /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.
- ///
- UINT32 ThermalThreshold1Status:1;
- ///
- /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.
- ///
- UINT32 ThermalThreshold1Log:1;
- ///
- /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.
- ///
- UINT32 ThermalThreshold2Status:1;
- ///
- /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.
- ///
- UINT32 ThermalThreshold2Log:1;
- ///
- /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.
- ///
- UINT32 PowerLimitStatus:1;
- ///
- /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.
- ///
- UINT32 PowerLimitLog:1;
- ///
- /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.
- ///
- UINT32 CurrentLimitStatus:1;
- ///
- /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
- ///
- UINT32 CurrentLimitLog:1;
- ///
- /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.
- ///
- UINT32 CrossDomainLimitStatus:1;
- ///
- /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
- ///
- UINT32 CrossDomainLimitLog:1;
- ///
- /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.
- ///
- UINT32 DigitalReadout:7;
- UINT32 Reserved1:4;
- ///
- /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] =
- /// 1.
- ///
- UINT32 ResolutionInDegreesCelsius:4;
- ///
- /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.
- ///
- UINT32 ReadingValid:1;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_THERM_STATUS_REGISTER;
-
-
-/**
- Enable Misc. Processor Features (R/W) Allows a variety of processor
- functions to be enabled and disabled.
-
- @param ECX MSR_IA32_MISC_ENABLE (0x000001A0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_MISC_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_MISC_ENABLE_REGISTER.
-
- Example usage
- @code
- MSR_IA32_MISC_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
- AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64);
- @endcode
- @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
-**/
-#define MSR_IA32_MISC_ENABLE 0x000001A0
-
-/**
- MSR information returned for MSR index #MSR_IA32_MISC_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for
- /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings
- /// are disabled. Introduced at Display Family / Display Model 0F_0H.
- ///
- UINT32 FastStrings:1;
- UINT32 Reserved1:2;
- ///
- /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting
- /// this bit enables the thermal control circuit (TCC) portion of the
- /// Intel Thermal Monitor feature. This allows the processor to
- /// automatically reduce power consumption in response to TCC activation.
- /// 0 = Disabled. Note: In some products clearing this bit might be
- /// ignored in critical thermal conditions, and TM1, TM2 and adaptive
- /// thermal throttling will still be activated. The default value of this
- /// field varies with product. See respective tables where default value is
- /// listed. Introduced at Display Family / Display Model 0F_0H.
- ///
- UINT32 AutomaticThermalControlCircuit:1;
- UINT32 Reserved2:3;
- ///
- /// [Bit 7] Performance Monitoring Available (R) 1 = Performance
- /// monitoring enabled 0 = Performance monitoring disabled. Introduced at
- /// Display Family / Display Model 0F_0H.
- ///
- UINT32 PerformanceMonitoring:1;
- UINT32 Reserved3:3;
- ///
- /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't
- /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at
- /// Display Family / Display Model 0F_0H.
- ///
- UINT32 BTS:1;
- ///
- /// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 =
- /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display
- /// Family / Display Model 06_0FH.
- ///
- UINT32 PEBS:1;
- UINT32 Reserved4:3;
- ///
- /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced
- /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep
- /// Technology enabled. If CPUID.01H: ECX[7] =1.
- ///
- UINT32 EIST:1;
- UINT32 Reserved5:1;
- ///
- /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the
- /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This
- /// indicates that MONITOR/MWAIT are not supported. Software attempts to
- /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit
- /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit
- /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit
- /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it
- /// in the default state. Writing this bit when the SSE3 feature flag is
- /// set to 0 may generate a #GP exception. Introduced at Display Family /
- /// Display Model 0F_03H.
- ///
- UINT32 MONITOR:1;
- UINT32 Reserved6:3;
- ///
- /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H
- /// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup
- /// question that allows users to specify when the installed OS does not
- /// support CPUID functions greater than 2. Before setting this bit, BIOS
- /// must execute the CPUID.0H and examine the maximum value returned in
- /// EAX[7:0]. If the maximum value is greater than 2, this bit is
- /// supported. Otherwise, this bit is not supported. Setting this bit when
- /// the maximum value is not greater than 2 may generate a #GP exception.
- /// Setting this bit may cause unexpected behavior in software that
- /// depends on the availability of CPUID leaves greater than 2. Introduced
- /// at Display Family / Display Model 0F_03H.
- ///
- UINT32 LimitCpuidMaxval:1;
- ///
- /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
- /// disabled. xTPR messages are optional messages that allow the processor
- /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.
- ///
- UINT32 xTPR_Message_Disable:1;
- UINT32 Reserved7:8;
- UINT32 Reserved8:2;
- ///
- /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit
- /// feature (XD Bit) is disabled and the XD Bit extended feature flag will
- /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the
- /// Execute Disable Bit feature (if available) allows the OS to enable PAE
- /// paging and take advantage of data only pages. BIOS must not alter the
- /// contents of this bit location, if XD bit is not supported. Writing
- /// this bit to 1 when the XD Bit extended feature flag is set to 0 may
- /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.
- ///
- UINT32 XD:1;
- UINT32 Reserved9:29;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_MISC_ENABLE_REGISTER;
-
-
-/**
- Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.
-
- @param ECX MSR_IA32_ENERGY_PERF_BIAS (0x000001B0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.
-
- Example usage
- @code
- MSR_IA32_ENERGY_PERF_BIAS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS);
- AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64);
- @endcode
- @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
-**/
-#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0
-
-/**
- MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest
- /// performance. 15 indicates preference to maximize energy saving.
- ///
- UINT32 PowerPolicyPreference:4;
- UINT32 Reserved1:28;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_ENERGY_PERF_BIAS_REGISTER;
-
-
-/**
- Package Thermal Status Information (RO) Contains status information about
- the package's thermal sensor. See Section 14.8, "Package Level Thermal
- Management.". If CPUID.06H: EAX[6] = 1.
-
- @param ECX MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.
-
- Example usage
- @code
- MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS);
- @endcode
- @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM.
-**/
-#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1
-
-/**
- MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Pkg Thermal Status (RO):.
- ///
- UINT32 ThermalStatus:1;
- ///
- /// [Bit 1] Pkg Thermal Status Log (R/W):.
- ///
- UINT32 ThermalStatusLog:1;
- ///
- /// [Bit 2] Pkg PROCHOT # event (RO).
- ///
- UINT32 PROCHOT_Event:1;
- ///
- /// [Bit 3] Pkg PROCHOT # log (R/WC0).
- ///
- UINT32 PROCHOT_Log:1;
- ///
- /// [Bit 4] Pkg Critical Temperature Status (RO).
- ///
- UINT32 CriticalTempStatus:1;
- ///
- /// [Bit 5] Pkg Critical Temperature Status log (R/WC0).
- ///
- UINT32 CriticalTempStatusLog:1;
- ///
- /// [Bit 6] Pkg Thermal Threshold #1 Status (RO).
- ///
- UINT32 ThermalThreshold1Status:1;
- ///
- /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0).
- ///
- UINT32 ThermalThreshold1Log:1;
- ///
- /// [Bit 8] Pkg Thermal Threshold #2 Status (RO).
- ///
- UINT32 ThermalThreshold2Status:1;
- ///
- /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0).
- ///
- UINT32 ThermalThreshold2Log:1;
- ///
- /// [Bit 10] Pkg Power Limitation Status (RO).
- ///
- UINT32 PowerLimitStatus:1;
- ///
- /// [Bit 11] Pkg Power Limitation log (R/WC0).
- ///
- UINT32 PowerLimitLog:1;
- UINT32 Reserved1:4;
- ///
- /// [Bits 22:16] Pkg Digital Readout (RO).
- ///
- UINT32 DigitalReadout:7;
- UINT32 Reserved2:9;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PACKAGE_THERM_STATUS_REGISTER;
-
-
-/**
- Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of
- an interrupt on temperature transitions detected with the package's thermal
- sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H:
- EAX[6] = 1.
-
- @param ECX MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.
-
- Example usage
- @code
- MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT);
- AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64);
- @endcode
- @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM.
-**/
-#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2
-
-/**
- MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Pkg High-Temperature Interrupt Enable.
- ///
- UINT32 HighTempEnable:1;
- ///
- /// [Bit 1] Pkg Low-Temperature Interrupt Enable.
- ///
- UINT32 LowTempEnable:1;
- ///
- /// [Bit 2] Pkg PROCHOT# Interrupt Enable.
- ///
- UINT32 PROCHOT_Enable:1;
- UINT32 Reserved1:1;
- ///
- /// [Bit 4] Pkg Overheat Interrupt Enable.
- ///
- UINT32 OverheatEnable:1;
- UINT32 Reserved2:3;
- ///
- /// [Bits 14:8] Pkg Threshold #1 Value.
- ///
- UINT32 Threshold1:7;
- ///
- /// [Bit 15] Pkg Threshold #1 Interrupt Enable.
- ///
- UINT32 Threshold1Enable:1;
- ///
- /// [Bits 22:16] Pkg Threshold #2 Value.
- ///
- UINT32 Threshold2:7;
- ///
- /// [Bit 23] Pkg Threshold #2 Interrupt Enable.
- ///
- UINT32 Threshold2Enable:1;
- ///
- /// [Bit 24] Pkg Power Limit Notification Enable.
- ///
- UINT32 PowerLimitNotificationEnable:1;
- UINT32 Reserved3:7;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER;
-
-
-/**
- Trace/Profile Resource Control (R/W). Introduced at Display Family / Display
- Model 06_0EH.
-
- @param ECX MSR_IA32_DEBUGCTL (0x000001D9)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_DEBUGCTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_DEBUGCTL_REGISTER.
-
- Example usage
- @code
- MSR_IA32_DEBUGCTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);
- AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64);
- @endcode
- @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM.
-**/
-#define MSR_IA32_DEBUGCTL 0x000001D9
-
-/**
- MSR information returned for MSR index #MSR_IA32_DEBUGCTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a
- /// running trace of the most recent branches taken by the processor in
- /// the LBR stack. Introduced at Display Family / Display Model 06_01H.
- ///
- UINT32 LBR:1;
- ///
- /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat
- /// EFLAGS.TF as single-step on branches instead of single-step on
- /// instructions. Introduced at Display Family / Display Model 06_01H.
- ///
- UINT32 BTF:1;
- UINT32 Reserved1:4;
- ///
- /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be
- /// sent. Introduced at Display Family / Display Model 06_0EH.
- ///
- UINT32 TR:1;
- ///
- /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to
- /// be logged in a BTS buffer. Introduced at Display Family / Display
- /// Model 06_0EH.
- ///
- UINT32 BTS:1;
- ///
- /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular
- /// fashion. When this bit is set, an interrupt is generated by the BTS
- /// facility when the BTS buffer is full. Introduced at Display Family /
- /// Display Model 06_0EH.
- ///
- UINT32 BTINT:1;
- ///
- /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.
- /// Introduced at Display Family / Display Model 06_0FH.
- ///
- UINT32 BTS_OFF_OS:1;
- ///
- /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.
- /// Introduced at Display Family / Display Model 06_0FH.
- ///
- UINT32 BTS_OFF_USR:1;
- ///
- /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a
- /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
- ///
- UINT32 FREEZE_LBRS_ON_PMI:1;
- ///
- /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the
- /// global counter control MSR are frozen (address 38FH) on a PMI request.
- /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
- ///
- UINT32 FREEZE_PERFMON_ON_PMI:1;
- ///
- /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to
- /// receive and generate PMI on behalf of the uncore. Introduced at
- /// Display Family / Display Model 06_1AH.
- ///
- UINT32 ENABLE_UNCORE_PMI:1;
- ///
- /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace
- /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.
- ///
- UINT32 FREEZE_WHILE_SMM:1;
- ///
- /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If
- /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).
- ///
- UINT32 RTM_DEBUG:1;
- UINT32 Reserved2:16;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_DEBUGCTL_REGISTER;
-
-
-/**
- SMRR Base Address (Writeable only in SMM) Base address of SMM memory range.
- If IA32_MTRRCAP.SMRR[11] = 1.
-
- @param ECX MSR_IA32_SMRR_PHYSBASE (0x000001F2)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.
-
- Example usage
- @code
- MSR_IA32_SMRR_PHYSBASE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE);
- AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64);
- @endcode
- @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM.
-**/
-#define MSR_IA32_SMRR_PHYSBASE 0x000001F2
-
-/**
- MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Type. Specifies memory type of the range.
- ///
- UINT32 Type:8;
- UINT32 Reserved1:4;
- ///
- /// [Bits 31:12] PhysBase. SMRR physical Base Address.
- ///
- UINT32 PhysBase:20;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_SMRR_PHYSBASE_REGISTER;
-
-
-/**
- SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If
- IA32_MTRRCAP[SMRR] = 1.
-
- @param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.
-
- Example usage
- @code
- MSR_IA32_SMRR_PHYSMASK_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK);
- AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64);
- @endcode
- @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM.
-**/
-#define MSR_IA32_SMRR_PHYSMASK 0x000001F3
-
-/**
- MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:11;
- ///
- /// [Bit 11] Valid Enable range mask.
- ///
- UINT32 Valid:1;
- ///
- /// [Bits 31:12] PhysMask SMRR address range mask.
- ///
- UINT32 PhysMask:20;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_SMRR_PHYSMASK_REGISTER;
-
-
-/**
- DCA Capability (R). If CPUID.01H: ECX[18] = 1.
-
- @param ECX MSR_IA32_PLATFORM_DCA_CAP (0x000001F8)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP);
- @endcode
- @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM.
-**/
-#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8
-
-
-/**
- If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.
-
- @param ECX MSR_IA32_CPU_DCA_CAP (0x000001F9)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP);
- AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr);
- @endcode
- @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM.
-**/
-#define MSR_IA32_CPU_DCA_CAP 0x000001F9
-
-
-/**
- DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.
-
- @param ECX MSR_IA32_DCA_0_CAP (0x000001FA)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_DCA_0_CAP_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_DCA_0_CAP_REGISTER.
-
- Example usage
- @code
- MSR_IA32_DCA_0_CAP_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP);
- AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64);
- @endcode
- @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM.
-**/
-#define MSR_IA32_DCA_0_CAP 0x000001FA
-
-/**
- MSR information returned for MSR index #MSR_IA32_DCA_0_CAP
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no
- /// defeatures are set.
- ///
- UINT32 DCA_ACTIVE:1;
- ///
- /// [Bits 2:1] TRANSACTION.
- ///
- UINT32 TRANSACTION:2;
- ///
- /// [Bits 6:3] DCA_TYPE.
- ///
- UINT32 DCA_TYPE:4;
- ///
- /// [Bits 10:7] DCA_QUEUE_SIZE.
- ///
- UINT32 DCA_QUEUE_SIZE:4;
- UINT32 Reserved1:2;
- ///
- /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW
- /// side-effect.
- ///
- UINT32 DCA_DELAY:4;
- UINT32 Reserved2:7;
- ///
- /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.
- ///
- UINT32 SW_BLOCK:1;
- UINT32 Reserved3:1;
- ///
- /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).
- ///
- UINT32 HW_BLOCK:1;
- UINT32 Reserved4:5;
- UINT32 Reserved5:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_DCA_0_CAP_REGISTER;
-
-
-/**
- MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs".
- If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
-
- @param ECX MSR_IA32_MTRR_PHYSBASEn
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
-
- Example usage
- @code
- MSR_IA32_MTRR_PHYSBASE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);
- AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);
- @endcode
- @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM.
- MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM.
- MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM.
- MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM.
- MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM.
- MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM.
- MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM.
- MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM.
- MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM.
- MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.
- @{
-**/
-#define MSR_IA32_MTRR_PHYSBASE0 0x00000200
-#define MSR_IA32_MTRR_PHYSBASE1 0x00000202
-#define MSR_IA32_MTRR_PHYSBASE2 0x00000204
-#define MSR_IA32_MTRR_PHYSBASE3 0x00000206
-#define MSR_IA32_MTRR_PHYSBASE4 0x00000208
-#define MSR_IA32_MTRR_PHYSBASE5 0x0000020A
-#define MSR_IA32_MTRR_PHYSBASE6 0x0000020C
-#define MSR_IA32_MTRR_PHYSBASE7 0x0000020E
-#define MSR_IA32_MTRR_PHYSBASE8 0x00000210
-#define MSR_IA32_MTRR_PHYSBASE9 0x00000212
-/// @}
-
-/**
- MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to
- #MSR_IA32_MTRR_PHYSBASE9
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Type. Specifies memory type of the range.
- ///
- UINT32 Type:8;
- UINT32 Reserved1:4;
- ///
- /// [Bits 31:12] PhysBase. MTRR physical Base Address.
- ///
- UINT32 PhysBase:20;
- ///
- /// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address.
- /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
- /// maximum physical address range supported by the processor. It is
- /// reported by CPUID leaf function 80000008H. If CPUID does not support
- /// leaf 80000008H, the processor supports 36-bit physical address size,
- /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
- ///
- UINT32 PhysBaseHi:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_MTRR_PHYSBASE_REGISTER;
-
-
-/**
- MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs".
- If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
-
- @param ECX MSR_IA32_MTRR_PHYSMASKn
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
-
- Example usage
- @code
- MSR_IA32_MTRR_PHYSMASK_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);
- AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);
- @endcode
- @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM.
- MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM.
- MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM.
- MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM.
- MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM.
- MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM.
- MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM.
- MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM.
- MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM.
- MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.
- @{
-**/
-#define MSR_IA32_MTRR_PHYSMASK0 0x00000201
-#define MSR_IA32_MTRR_PHYSMASK1 0x00000203
-#define MSR_IA32_MTRR_PHYSMASK2 0x00000205
-#define MSR_IA32_MTRR_PHYSMASK3 0x00000207
-#define MSR_IA32_MTRR_PHYSMASK4 0x00000209
-#define MSR_IA32_MTRR_PHYSMASK5 0x0000020B
-#define MSR_IA32_MTRR_PHYSMASK6 0x0000020D
-#define MSR_IA32_MTRR_PHYSMASK7 0x0000020F
-#define MSR_IA32_MTRR_PHYSMASK8 0x00000211
-#define MSR_IA32_MTRR_PHYSMASK9 0x00000213
-/// @}
-
-/**
- MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to
- #MSR_IA32_MTRR_PHYSMASK9
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:11;
- ///
- /// [Bit 11] Valid Enable range mask.
- ///
- UINT32 V:1;
- ///
- /// [Bits 31:12] PhysMask. MTRR address range mask.
- ///
- UINT32 PhysMask:20;
- ///
- /// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask.
- /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
- /// maximum physical address range supported by the processor. It is
- /// reported by CPUID leaf function 80000008H. If CPUID does not support
- /// leaf 80000008H, the processor supports 36-bit physical address size,
- /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
- ///
- UINT32 PhysMaskHi:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_MTRR_PHYSMASK_REGISTER;
-
-
-/**
- MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_FIX64K_00000 (0x00000250)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000);
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr);
- @endcode
- @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM.
-**/
-#define MSR_IA32_MTRR_FIX64K_00000 0x00000250
-
-
-/**
- MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_FIX16K_80000 (0x00000258)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000);
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr);
- @endcode
- @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM.
-**/
-#define MSR_IA32_MTRR_FIX16K_80000 0x00000258
-
-
-/**
- MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_FIX16K_A0000 (0x00000259)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000);
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr);
- @endcode
- @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM.
-**/
-#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259
-
-
-/**
- See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_FIX4K_C0000 (0x00000268)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000);
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr);
- @endcode
- @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM.
-**/
-#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268
-
-
-/**
- MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_FIX4K_C8000 (0x00000269)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000);
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr);
- @endcode
- @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM.
-**/
-#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269
-
-
-/**
- MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000);
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr);
- @endcode
- @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM.
-**/
-#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A
-
-
-/**
- MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000);
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr);
- @endcode
- @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM.
-**/
-#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B
-
-
-/**
- MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000);
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr);
- @endcode
- @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM.
-**/
-#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C
-
-
-/**
- MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000);
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr);
- @endcode
- @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM.
-**/
-#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D
-
-
-/**
- MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000);
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr);
- @endcode
- @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM.
-**/
-#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E
-
-
-/**
- MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000);
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr);
- @endcode
- @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM.
-**/
-#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F
-
-
-/**
- IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.
-
- @param ECX MSR_IA32_PAT (0x00000277)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PAT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PAT_REGISTER.
-
- Example usage
- @code
- MSR_IA32_PAT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT);
- AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64);
- @endcode
- @note MSR_IA32_PAT is defined as IA32_PAT in SDM.
-**/
-#define MSR_IA32_PAT 0x00000277
-
-/**
- MSR information returned for MSR index #MSR_IA32_PAT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 2:0] PA0.
- ///
- UINT32 PA0:3;
- UINT32 Reserved1:5;
- ///
- /// [Bits 10:8] PA1.
- ///
- UINT32 PA1:3;
- UINT32 Reserved2:5;
- ///
- /// [Bits 18:16] PA2.
- ///
- UINT32 PA2:3;
- UINT32 Reserved3:5;
- ///
- /// [Bits 26:24] PA3.
- ///
- UINT32 PA3:3;
- UINT32 Reserved4:5;
- ///
- /// [Bits 34:32] PA4.
- ///
- UINT32 PA4:3;
- UINT32 Reserved5:5;
- ///
- /// [Bits 42:40] PA5.
- ///
- UINT32 PA5:3;
- UINT32 Reserved6:5;
- ///
- /// [Bits 50:48] PA6.
- ///
- UINT32 PA6:3;
- UINT32 Reserved7:5;
- ///
- /// [Bits 58:56] PA7.
- ///
- UINT32 PA7:3;
- UINT32 Reserved8:5;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PAT_REGISTER;
-
-
-/**
- Provides the programming interface to use corrected MC error signaling
- capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.
-
- @param ECX MSR_IA32_MCn_CTL2
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_MC_CTL2_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_MC_CTL2_REGISTER.
-
- Example usage
- @code
- MSR_IA32_MC_CTL2_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
- AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);
- @endcode
- @note MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM.
- MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM.
- MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM.
- MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM.
- MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.
- MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM.
- MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM.
- MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM.
- MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM.
- MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM.
- MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM.
- MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM.
- MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM.
- MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM.
- MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM.
- MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM.
- MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM.
- MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM.
- MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM.
- MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM.
- MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM.
- MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM.
- MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM.
- MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM.
- MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM.
- MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM.
- MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM.
- MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM.
- MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM.
- MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM.
- MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM.
- MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.
- @{
-**/
-#define MSR_IA32_MC0_CTL2 0x00000280
-#define MSR_IA32_MC1_CTL2 0x00000281
-#define MSR_IA32_MC2_CTL2 0x00000282
-#define MSR_IA32_MC3_CTL2 0x00000283
-#define MSR_IA32_MC4_CTL2 0x00000284
-#define MSR_IA32_MC5_CTL2 0x00000285
-#define MSR_IA32_MC6_CTL2 0x00000286
-#define MSR_IA32_MC7_CTL2 0x00000287
-#define MSR_IA32_MC8_CTL2 0x00000288
-#define MSR_IA32_MC9_CTL2 0x00000289
-#define MSR_IA32_MC10_CTL2 0x0000028A
-#define MSR_IA32_MC11_CTL2 0x0000028B
-#define MSR_IA32_MC12_CTL2 0x0000028C
-#define MSR_IA32_MC13_CTL2 0x0000028D
-#define MSR_IA32_MC14_CTL2 0x0000028E
-#define MSR_IA32_MC15_CTL2 0x0000028F
-#define MSR_IA32_MC16_CTL2 0x00000290
-#define MSR_IA32_MC17_CTL2 0x00000291
-#define MSR_IA32_MC18_CTL2 0x00000292
-#define MSR_IA32_MC19_CTL2 0x00000293
-#define MSR_IA32_MC20_CTL2 0x00000294
-#define MSR_IA32_MC21_CTL2 0x00000295
-#define MSR_IA32_MC22_CTL2 0x00000296
-#define MSR_IA32_MC23_CTL2 0x00000297
-#define MSR_IA32_MC24_CTL2 0x00000298
-#define MSR_IA32_MC25_CTL2 0x00000299
-#define MSR_IA32_MC26_CTL2 0x0000029A
-#define MSR_IA32_MC27_CTL2 0x0000029B
-#define MSR_IA32_MC28_CTL2 0x0000029C
-#define MSR_IA32_MC29_CTL2 0x0000029D
-#define MSR_IA32_MC30_CTL2 0x0000029E
-#define MSR_IA32_MC31_CTL2 0x0000029F
-/// @}
-
-/**
- MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2
- to #MSR_IA32_MC31_CTL2
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 14:0] Corrected error count threshold.
- ///
- UINT32 CorrectedErrorCountThreshold:15;
- UINT32 Reserved1:15;
- ///
- /// [Bit 30] CMCI_EN.
- ///
- UINT32 CMCI_EN:1;
- UINT32 Reserved2:1;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_MC_CTL2_REGISTER;
-
-
-/**
- MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.
-
- @param ECX MSR_IA32_MTRR_DEF_TYPE (0x000002FF)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.
-
- Example usage
- @code
- MSR_IA32_MTRR_DEF_TYPE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
- AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64);
- @endcode
- @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM.
-**/
-#define MSR_IA32_MTRR_DEF_TYPE 0x000002FF
-
-/**
- MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 2:0] Default Memory Type.
- ///
- UINT32 Type:3;
- UINT32 Reserved1:7;
- ///
- /// [Bit 10] Fixed Range MTRR Enable.
- ///
- UINT32 FE:1;
- ///
- /// [Bit 11] MTRR Enable.
- ///
- UINT32 E:1;
- UINT32 Reserved2:20;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_MTRR_DEF_TYPE_REGISTER;
-
-
-/**
- Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If
- CPUID.0AH: EDX[4:0] > 0.
-
- @param ECX MSR_IA32_FIXED_CTR0 (0x00000309)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0);
- AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr);
- @endcode
- @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM.
-**/
-#define MSR_IA32_FIXED_CTR0 0x00000309
-
-
-/**
- Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If
- CPUID.0AH: EDX[4:0] > 1.
-
- @param ECX MSR_IA32_FIXED_CTR1 (0x0000030A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1);
- AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr);
- @endcode
- @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM.
-**/
-#define MSR_IA32_FIXED_CTR1 0x0000030A
-
-
-/**
- Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If
- CPUID.0AH: EDX[4:0] > 2.
-
- @param ECX MSR_IA32_FIXED_CTR2 (0x0000030B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2);
- AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr);
- @endcode
- @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM.
-**/
-#define MSR_IA32_FIXED_CTR2 0x0000030B
-
-
-/**
- RO. If CPUID.01H: ECX[15] = 1.
-
- @param ECX MSR_IA32_PERF_CAPABILITIES (0x00000345)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.
-
- Example usage
- @code
- MSR_IA32_PERF_CAPABILITIES_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES);
- AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64);
- @endcode
- @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM.
-**/
-#define MSR_IA32_PERF_CAPABILITIES 0x00000345
-
-/**
- MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 5:0] LBR format.
- ///
- UINT32 LBR_FMT:6;
- ///
- /// [Bit 6] PEBS Trap.
- ///
- UINT32 PEBS_TRAP:1;
- ///
- /// [Bit 7] PEBSSaveArchRegs.
- ///
- UINT32 PEBS_ARCH_REG:1;
- ///
- /// [Bits 11:8] PEBS Record Format.
- ///
- UINT32 PEBS_REC_FMT:4;
- ///
- /// [Bit 12] 1: Freeze while SMM is supported.
- ///
- UINT32 SMM_FREEZE:1;
- ///
- /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx.
- ///
- UINT32 FW_WRITE:1;
- UINT32 Reserved1:18;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PERF_CAPABILITIES_REGISTER;
-
-
-/**
- Fixed-Function Performance Counter Control (R/W) Counter increments while
- the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with
- the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0]
- > 1.
-
- @param ECX MSR_IA32_FIXED_CTR_CTRL (0x0000038D)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.
-
- Example usage
- @code
- MSR_IA32_FIXED_CTR_CTRL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL);
- AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64);
- @endcode
- @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM.
-**/
-#define MSR_IA32_FIXED_CTR_CTRL 0x0000038D
-
-/**
- MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.
- ///
- UINT32 EN0_OS:1;
- ///
- /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.
- ///
- UINT32 EN0_Usr:1;
- ///
- /// [Bit 2] AnyThread: When set to 1, it enables counting the associated
- /// event conditions occurring across all logical processors sharing a
- /// processor core. When set to 0, the counter only increments the
- /// associated event conditions occurring in the logical processor which
- /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
- ///
- UINT32 AnyThread0:1;
- ///
- /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.
- ///
- UINT32 EN0_PMI:1;
- ///
- /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.
- ///
- UINT32 EN1_OS:1;
- ///
- /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.
- ///
- UINT32 EN1_Usr:1;
- ///
- /// [Bit 6] AnyThread: When set to 1, it enables counting the associated
- /// event conditions occurring across all logical processors sharing a
- /// processor core. When set to 0, the counter only increments the
- /// associated event conditions occurring in the logical processor which
- /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
- ///
- UINT32 AnyThread1:1;
- ///
- /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.
- ///
- UINT32 EN1_PMI:1;
- ///
- /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.
- ///
- UINT32 EN2_OS:1;
- ///
- /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.
- ///
- UINT32 EN2_Usr:1;
- ///
- /// [Bit 10] AnyThread: When set to 1, it enables counting the associated
- /// event conditions occurring across all logical processors sharing a
- /// processor core. When set to 0, the counter only increments the
- /// associated event conditions occurring in the logical processor which
- /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
- ///
- UINT32 AnyThread2:1;
- ///
- /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.
- ///
- UINT32 EN2_PMI:1;
- UINT32 Reserved1:20;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_FIXED_CTR_CTRL_REGISTER;
-
-
-/**
- Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.
-
- @param ECX MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.
-
- Example usage
- @code
- MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS);
- @endcode
- @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
-**/
-#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E
-
-/**
- MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH:
- /// EAX[15:8] > 0.
- ///
- UINT32 Ovf_PMC0:1;
- ///
- /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH:
- /// EAX[15:8] > 1.
- ///
- UINT32 Ovf_PMC1:1;
- ///
- /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH:
- /// EAX[15:8] > 2.
- ///
- UINT32 Ovf_PMC2:1;
- ///
- /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH:
- /// EAX[15:8] > 3.
- ///
- UINT32 Ovf_PMC3:1;
- UINT32 Reserved1:28;
- ///
- /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If
- /// CPUID.0AH: EAX[7:0] > 1.
- ///
- UINT32 Ovf_FixedCtr0:1;
- ///
- /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If
- /// CPUID.0AH: EAX[7:0] > 1.
- ///
- UINT32 Ovf_FixedCtr1:1;
- ///
- /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If
- /// CPUID.0AH: EAX[7:0] > 1.
- ///
- UINT32 Ovf_FixedCtr2:1;
- UINT32 Reserved2:20;
- ///
- /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory
- /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
- /// && IA32_RTIT_CTL.ToPA = 1.
- ///
- UINT32 Trace_ToPA_PMI:1;
- UINT32 Reserved3:2;
- ///
- /// [Bit 58] LBR_Frz: LBRs are frozen due to -
- /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If
- /// CPUID.0AH: EAX[7:0] > 3.
- ///
- UINT32 LBR_Frz:1;
- ///
- /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due
- /// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU
- /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3.
- ///
- UINT32 CTR_Frz:1;
- ///
- /// [Bit 60] ASCI: Data in the performance counters in the core PMU may
- /// include contributions from the direct or indirect operation intel SGX
- /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.
- ///
- UINT32 ASCI:1;
- ///
- /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH:
- /// EAX[7:0] > 2.
- ///
- UINT32 Ovf_Uncore:1;
- ///
- /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH:
- /// EAX[7:0] > 0.
- ///
- UINT32 OvfBuf:1;
- ///
- /// [Bit 63] CondChgd: status bits of this register has changed. If
- /// CPUID.0AH: EAX[7:0] > 0.
- ///
- UINT32 CondChgd:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PERF_GLOBAL_STATUS_REGISTER;
-
-
-/**
- Global Performance Counter Control (R/W) Counter increments while the result
- of ANDing respective enable bit in this MSR with the corresponding OS or USR
- bits in the general-purpose or fixed counter control MSR is true. If
- CPUID.0AH: EAX[7:0] > 0.
-
- @param ECX MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.
-
- Example usage
- @code
- MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL);
- AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);
- @endcode
- @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.
-**/
-#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F
-
-/**
- MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL
-**/
-typedef union {
- ///
- /// Individual bit fields
-///
- struct {
- ///
- /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n.
- /// Enable bitmask. Only the first n-1 bits are valid.
- /// Bits n..31 are reserved.
- ///
- UINT32 EN_PMCn:32;
- ///
- /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n.
- /// Enable bitmask. Only the first n-1 bits are valid.
- /// Bits 31:n are reserved.
- ///
- UINT32 EN_FIXED_CTRn:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PERF_GLOBAL_CTRL_REGISTER;
-
-
-/**
- Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] >
- 0 && CPUID.0AH: EAX[7:0] <= 3.
-
- @param ECX MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
-
- Example usage
- @code
- MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL);
- AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
- @endcode
- @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.
-**/
-#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
-
-/**
- MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.
- /// Clear bitmask. Only the first n-1 bits are valid.
- /// Bits 31:n are reserved.
- ///
- UINT32 Ovf_PMCn:32;
- ///
- /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
- /// If CPUID.0AH: EDX[4:0] > n.
- /// Clear bitmask. Only the first n-1 bits are valid.
- /// Bits 22:n are reserved.
- ///
- UINT32 Ovf_FIXED_CTRn:23;
- ///
- /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
- /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.
- ///
- UINT32 Trace_ToPA_PMI:1;
- UINT32 Reserved2:5;
- ///
- /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
- /// Display Model 06_2EH.
- ///
- UINT32 Ovf_Uncore:1;
- ///
- /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
- ///
- UINT32 OvfBuf:1;
- ///
- /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
- ///
- UINT32 CondChgd:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;
-
-
-/**
- Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH:
- EAX[7:0] > 3.
-
- @param ECX MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
-
- Example usage
- @code
- MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET);
- AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
- @endcode
- @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
-**/
-#define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
-
-/**
- MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.
- /// Clear bitmask. Only the first n-1 bits are valid.
- /// Bits 31:n are reserved.
- ///
- UINT32 Ovf_PMCn:32;
- ///
- /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
- /// If CPUID.0AH: EDX[4:0] > n.
- /// Clear bitmask. Only the first n-1 bits are valid.
- /// Bits 22:n are reserved.
- ///
- UINT32 Ovf_FIXED_CTRn:23;
- ///
- /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
- /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.
- ///
- UINT32 Trace_ToPA_PMI:1;
- UINT32 Reserved2:2;
- ///
- /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
- ///
- UINT32 LBR_Frz:1;
- ///
- /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
- ///
- UINT32 CTR_Frz:1;
- ///
- /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.
- ///
- UINT32 ASCI:1;
- ///
- /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
- /// Display Model 06_2EH.
- ///
- UINT32 Ovf_Uncore:1;
- ///
- /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
- ///
- UINT32 OvfBuf:1;
- ///
- /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
- ///
- UINT32 CondChgd:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;
-
-
-/**
- Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH:
- EAX[7:0] > 3.
-
- @param ECX MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
-
- Example usage
- @code
- MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET);
- AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
- @endcode
- @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
-**/
-#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
-
-/**
- MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n.
- /// Set bitmask. Only the first n-1 bits are valid.
- /// Bits 31:n are reserved.
- ///
- UINT32 Ovf_PMCn:32;
- ///
- /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1.
- /// If CPUID.0AH: EAX[7:0] > n.
- /// Set bitmask. Only the first n-1 bits are valid.
- /// Bits 22:n are reserved.
- ///
- UINT32 Ovf_FIXED_CTRn:23;
- ///
- /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.
- ///
- UINT32 Trace_ToPA_PMI:1;
- UINT32 Reserved2:2;
- ///
- /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
- ///
- UINT32 LBR_Frz:1;
- ///
- /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
- ///
- UINT32 CTR_Frz:1;
- ///
- /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.
- ///
- UINT32 ASCI:1;
- ///
- /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.
- ///
- UINT32 Ovf_Uncore:1;
- ///
- /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.
- ///
- UINT32 OvfBuf:1;
- UINT32 Reserved3:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;
-
-
-/**
- Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] >
- 3.
-
- @param ECX MSR_IA32_PERF_GLOBAL_INUSE (0x00000392)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.
-
- Example usage
- @code
- MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE);
- @endcode
- @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM.
-**/
-#define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392
-
-/**
- MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n.
- /// Status bitmask. Only the first n-1 bits are valid.
- /// Bits 31:n are reserved.
- ///
- UINT32 IA32_PERFEVTSELn:32;
- ///
- /// [Bits 62:32] IA32_FIXED_CTRn in use.
- /// If CPUID.0AH: EAX[7:0] > n.
- /// Status bitmask. Only the first n-1 bits are valid.
- /// Bits 30:n are reserved.
- ///
- UINT32 IA32_FIXED_CTRn:31;
- ///
- /// [Bit 63] PMI in use.
- ///
- UINT32 PMI:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PERF_GLOBAL_INUSE_REGISTER;
-
-
-/**
- PEBS Control (R/W).
-
- @param ECX MSR_IA32_PEBS_ENABLE (0x000003F1)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.
-
- Example usage
- @code
- MSR_IA32_PEBS_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE);
- AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64);
- @endcode
- @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM.
-**/
-#define MSR_IA32_PEBS_ENABLE 0x000003F1
-
-/**
- MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family /
- /// Display Model 06_0FH.
- ///
- UINT32 Enable:1;
- ///
- /// [Bits 3:1] Reserved or Model specific.
- ///
- UINT32 Reserved1:3;
- UINT32 Reserved2:28;
- ///
- /// [Bits 35:32] Reserved or Model specific.
- ///
- UINT32 Reserved3:4;
- UINT32 Reserved4:28;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PEBS_ENABLE_REGISTER;
-
-
-/**
- MCn_CTL. If IA32_MCG_CAP.CNT > n.
-
- @param ECX MSR_IA32_MCn_CTL
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
- AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);
- @endcode
- @note MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM.
- MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM.
- MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM.
- MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM.
- MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.
- MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM.
- MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM.
- MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM.
- MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM.
- MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM.
- MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM.
- MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM.
- MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM.
- MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM.
- MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM.
- MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM.
- MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM.
- MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM.
- MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM.
- MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM.
- MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM.
- MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM.
- MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM.
- MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM.
- MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM.
- MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM.
- MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM.
- MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM.
- MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.
- @{
-**/
-#define MSR_IA32_MC0_CTL 0x00000400
-#define MSR_IA32_MC1_CTL 0x00000404
-#define MSR_IA32_MC2_CTL 0x00000408
-#define MSR_IA32_MC3_CTL 0x0000040C
-#define MSR_IA32_MC4_CTL 0x00000410
-#define MSR_IA32_MC5_CTL 0x00000414
-#define MSR_IA32_MC6_CTL 0x00000418
-#define MSR_IA32_MC7_CTL 0x0000041C
-#define MSR_IA32_MC8_CTL 0x00000420
-#define MSR_IA32_MC9_CTL 0x00000424
-#define MSR_IA32_MC10_CTL 0x00000428
-#define MSR_IA32_MC11_CTL 0x0000042C
-#define MSR_IA32_MC12_CTL 0x00000430
-#define MSR_IA32_MC13_CTL 0x00000434
-#define MSR_IA32_MC14_CTL 0x00000438
-#define MSR_IA32_MC15_CTL 0x0000043C
-#define MSR_IA32_MC16_CTL 0x00000440
-#define MSR_IA32_MC17_CTL 0x00000444
-#define MSR_IA32_MC18_CTL 0x00000448
-#define MSR_IA32_MC19_CTL 0x0000044C
-#define MSR_IA32_MC20_CTL 0x00000450
-#define MSR_IA32_MC21_CTL 0x00000454
-#define MSR_IA32_MC22_CTL 0x00000458
-#define MSR_IA32_MC23_CTL 0x0000045C
-#define MSR_IA32_MC24_CTL 0x00000460
-#define MSR_IA32_MC25_CTL 0x00000464
-#define MSR_IA32_MC26_CTL 0x00000468
-#define MSR_IA32_MC27_CTL 0x0000046C
-#define MSR_IA32_MC28_CTL 0x00000470
-/// @}
-
-
-/**
- MCn_STATUS. If IA32_MCG_CAP.CNT > n.
-
- @param ECX MSR_IA32_MCn_STATUS
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
- AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);
- @endcode
- @note MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM.
- MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM.
- MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM.
- MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM.
- MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM.
- MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM.
- MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM.
- MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM.
- MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM.
- MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM.
- MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM.
- MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM.
- MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM.
- MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM.
- MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM.
- MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM.
- MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM.
- MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM.
- MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM.
- MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM.
- MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM.
- MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM.
- MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM.
- MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM.
- MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM.
- MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM.
- MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM.
- MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM.
- MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.
- @{
-**/
-#define MSR_IA32_MC0_STATUS 0x00000401
-#define MSR_IA32_MC1_STATUS 0x00000405
-#define MSR_IA32_MC2_STATUS 0x00000409
-#define MSR_IA32_MC3_STATUS 0x0000040D
-#define MSR_IA32_MC4_STATUS 0x00000411
-#define MSR_IA32_MC5_STATUS 0x00000415
-#define MSR_IA32_MC6_STATUS 0x00000419
-#define MSR_IA32_MC7_STATUS 0x0000041D
-#define MSR_IA32_MC8_STATUS 0x00000421
-#define MSR_IA32_MC9_STATUS 0x00000425
-#define MSR_IA32_MC10_STATUS 0x00000429
-#define MSR_IA32_MC11_STATUS 0x0000042D
-#define MSR_IA32_MC12_STATUS 0x00000431
-#define MSR_IA32_MC13_STATUS 0x00000435
-#define MSR_IA32_MC14_STATUS 0x00000439
-#define MSR_IA32_MC15_STATUS 0x0000043D
-#define MSR_IA32_MC16_STATUS 0x00000441
-#define MSR_IA32_MC17_STATUS 0x00000445
-#define MSR_IA32_MC18_STATUS 0x00000449
-#define MSR_IA32_MC19_STATUS 0x0000044D
-#define MSR_IA32_MC20_STATUS 0x00000451
-#define MSR_IA32_MC21_STATUS 0x00000455
-#define MSR_IA32_MC22_STATUS 0x00000459
-#define MSR_IA32_MC23_STATUS 0x0000045D
-#define MSR_IA32_MC24_STATUS 0x00000461
-#define MSR_IA32_MC25_STATUS 0x00000465
-#define MSR_IA32_MC26_STATUS 0x00000469
-#define MSR_IA32_MC27_STATUS 0x0000046D
-#define MSR_IA32_MC28_STATUS 0x00000471
-/// @}
-
-
-/**
- MCn_ADDR. If IA32_MCG_CAP.CNT > n.
-
- @param ECX MSR_IA32_MCn_ADDR
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
- AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);
- @endcode
- @note MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM.
- MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM.
- MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM.
- MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM.
- MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM.
- MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM.
- MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM.
- MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM.
- MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM.
- MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM.
- MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM.
- MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM.
- MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM.
- MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM.
- MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM.
- MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM.
- MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM.
- MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM.
- MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM.
- MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM.
- MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM.
- MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM.
- MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM.
- MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM.
- MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM.
- MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM.
- MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM.
- MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM.
- MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.
- @{
-**/
-#define MSR_IA32_MC0_ADDR 0x00000402
-#define MSR_IA32_MC1_ADDR 0x00000406
-#define MSR_IA32_MC2_ADDR 0x0000040A
-#define MSR_IA32_MC3_ADDR 0x0000040E
-#define MSR_IA32_MC4_ADDR 0x00000412
-#define MSR_IA32_MC5_ADDR 0x00000416
-#define MSR_IA32_MC6_ADDR 0x0000041A
-#define MSR_IA32_MC7_ADDR 0x0000041E
-#define MSR_IA32_MC8_ADDR 0x00000422
-#define MSR_IA32_MC9_ADDR 0x00000426
-#define MSR_IA32_MC10_ADDR 0x0000042A
-#define MSR_IA32_MC11_ADDR 0x0000042E
-#define MSR_IA32_MC12_ADDR 0x00000432
-#define MSR_IA32_MC13_ADDR 0x00000436
-#define MSR_IA32_MC14_ADDR 0x0000043A
-#define MSR_IA32_MC15_ADDR 0x0000043E
-#define MSR_IA32_MC16_ADDR 0x00000442
-#define MSR_IA32_MC17_ADDR 0x00000446
-#define MSR_IA32_MC18_ADDR 0x0000044A
-#define MSR_IA32_MC19_ADDR 0x0000044E
-#define MSR_IA32_MC20_ADDR 0x00000452
-#define MSR_IA32_MC21_ADDR 0x00000456
-#define MSR_IA32_MC22_ADDR 0x0000045A
-#define MSR_IA32_MC23_ADDR 0x0000045E
-#define MSR_IA32_MC24_ADDR 0x00000462
-#define MSR_IA32_MC25_ADDR 0x00000466
-#define MSR_IA32_MC26_ADDR 0x0000046A
-#define MSR_IA32_MC27_ADDR 0x0000046E
-#define MSR_IA32_MC28_ADDR 0x00000472
-/// @}
-
-
-/**
- MCn_MISC. If IA32_MCG_CAP.CNT > n.
-
- @param ECX MSR_IA32_MCn_MISC
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
- AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);
- @endcode
- @note MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM.
- MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM.
- MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM.
- MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM.
- MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM.
- MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM.
- MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.
- MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM.
- MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM.
- MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM.
- MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM.
- MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM.
- MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM.
- MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM.
- MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM.
- MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM.
- MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM.
- MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM.
- MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM.
- MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM.
- MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM.
- MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM.
- MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM.
- MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM.
- MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM.
- MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM.
- MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM.
- MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM.
- MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.
- @{
-**/
-#define MSR_IA32_MC0_MISC 0x00000403
-#define MSR_IA32_MC1_MISC 0x00000407
-#define MSR_IA32_MC2_MISC 0x0000040B
-#define MSR_IA32_MC3_MISC 0x0000040F
-#define MSR_IA32_MC4_MISC 0x00000413
-#define MSR_IA32_MC5_MISC 0x00000417
-#define MSR_IA32_MC6_MISC 0x0000041B
-#define MSR_IA32_MC7_MISC 0x0000041F
-#define MSR_IA32_MC8_MISC 0x00000423
-#define MSR_IA32_MC9_MISC 0x00000427
-#define MSR_IA32_MC10_MISC 0x0000042B
-#define MSR_IA32_MC11_MISC 0x0000042F
-#define MSR_IA32_MC12_MISC 0x00000433
-#define MSR_IA32_MC13_MISC 0x00000437
-#define MSR_IA32_MC14_MISC 0x0000043B
-#define MSR_IA32_MC15_MISC 0x0000043F
-#define MSR_IA32_MC16_MISC 0x00000443
-#define MSR_IA32_MC17_MISC 0x00000447
-#define MSR_IA32_MC18_MISC 0x0000044B
-#define MSR_IA32_MC19_MISC 0x0000044F
-#define MSR_IA32_MC20_MISC 0x00000453
-#define MSR_IA32_MC21_MISC 0x00000457
-#define MSR_IA32_MC22_MISC 0x0000045B
-#define MSR_IA32_MC23_MISC 0x0000045F
-#define MSR_IA32_MC24_MISC 0x00000463
-#define MSR_IA32_MC25_MISC 0x00000467
-#define MSR_IA32_MC26_MISC 0x0000046B
-#define MSR_IA32_MC27_MISC 0x0000046F
-#define MSR_IA32_MC28_MISC 0x00000473
-/// @}
-
-
-/**
- Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic
- VMX Information.". If CPUID.01H:ECX.[5] = 1.
-
- @param ECX MSR_IA32_VMX_BASIC (0x00000480)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- MSR_IA32_VMX_BASIC_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC);
- @endcode
- @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.
-**/
-#define MSR_IA32_VMX_BASIC 0x00000480
-
-/**
- MSR information returned for MSR index #MSR_IA32_VMX_BASIC
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 30:0] VMCS revision identifier used by the processor. Processors
- /// that use the same VMCS revision identifier use the same size for VMCS
- /// regions (see subsequent item on bits 44:32).
- ///
- /// @note Earlier versions of this manual specified that the VMCS revision
- /// identifier was a 32-bit field in bits 31:0 of this MSR. For all
- /// processors produced prior to this change, bit 31 of this MSR was read
- /// as 0.
- ///
- UINT32 VmcsRevisonId:31;
- UINT32 MustBeZero:1;
- ///
- /// [Bit 44:32] Reports the number of bytes that software should allocate
- /// for the VMXON region and any VMCS region. It is a value greater than
- /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).
- ///
- UINT32 VmcsSize:13;
- UINT32 Reserved1:3;
- ///
- /// [Bit 48] Indicates the width of the physical addresses that may be used
- /// for the VMXON region, each VMCS, and data structures referenced by
- /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX
- /// transitions). If the bit is 0, these addresses are limited to the
- /// processor's physical-address width. If the bit is 1, these addresses
- /// are limited to 32 bits. This bit is always 0 for processors that
- /// support Intel 64 architecture.
- ///
- /// @note On processors that support Intel 64 architecture, the pointer
- /// must not set bits beyond the processor's physical address width.
- ///
- UINT32 VmcsAddressWidth:1;
- ///
- /// [Bit 49] If bit 49 is read as 1, the logical processor supports the
- /// dual-monitor treatment of system-management interrupts and
- /// system-management mode. See Section 34.15 for details of this treatment.
- ///
- UINT32 DualMonitor:1;
- ///
- /// [Bit 53:50] report the memory type that should be used for the VMCS,
- /// for data structures referenced by pointers in the VMCS (I/O bitmaps,
- /// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG
- /// header. If software needs to access these data structures (e.g., to
- /// modify the contents of the MSR bitmaps), it can configure the paging
- /// structures to map them into the linear-address space. If it does so,
- /// it should establish mappings that use the memory type reported bits
- /// 53:50 in this MSR.
- ///
- /// As of this writing, all processors that support VMX operation indicate
- /// the write-back type.
- ///
- /// If software needs to access these data structures (e.g., to modify
- /// the contents of the MSR bitmaps), it can configure the paging
- /// structures to map them into the linear-address space. If it does so,
- /// it should establish mappings that use the memory type reported in this
- /// MSR.
- ///
- /// @note Alternatively, software may map any of these regions or
- /// structures with the UC memory type. (This may be necessary for the MSEG
- /// header.) Doing so is discouraged unless necessary as it will cause the
- /// performance of software accesses to those structures to suffer.
- ///
- ///
- UINT32 MemoryType:4;
- ///
- /// [Bit 54] If bit 54 is read as 1, the processor reports information in
- /// the VM-exit instruction-information field on VM exitsdue to execution
- /// of the INS and OUTS instructions (see Section 27.2.4). This reporting
- /// is done only if this bit is read as 1.
- ///
- UINT32 InsOutsReporting:1;
- ///
- /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may
- /// be cleared to 0. See Appendix A.2 for details. It also reports support
- /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS,
- /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and
- /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2,
- /// Appendix A.4, and Appendix A.5 for details.
- ///
- UINT32 VmxControls:1;
- UINT32 Reserved2:8;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_VMX_BASIC_REGISTER;
-
-///
-/// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType
-///
-#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00
-#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06
-///
-/// @}
-///
-
-
-/**
- Capability Reporting Register of Pinbased VM-execution Controls (R/O) See
- Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.
-
- @param ECX MSR_IA32_VMX_PINBASED_CTLS (0x00000481)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS);
- @endcode
- @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM.
-**/
-#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
-
-
-/**
- Capability Reporting Register of Primary Processor-based VM-execution
- Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution
- Controls.". If CPUID.01H:ECX.[5] = 1.
-
- @param ECX MSR_IA32_VMX_PROCBASED_CTLS (0x00000482)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS);
- @endcode
- @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM.
-**/
-#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
-
-
-/**
- Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4,
- "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1.
-
- @param ECX MSR_IA32_VMX_EXIT_CTLS (0x00000483)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS);
- @endcode
- @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM.
-**/
-#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
-
-
-/**
- Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5,
- "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1.
-
- @param ECX MSR_IA32_VMX_ENTRY_CTLS (0x00000484)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS);
- @endcode
- @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM.
-**/
-#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
-
-
-/**
- Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6,
- "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1.
-
- @param ECX MSR_IA32_VMX_MISC (0x00000485)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- IA32_VMX_MISC_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC);
- @endcode
- @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.
-**/
-#define MSR_IA32_VMX_MISC 0x00000485
-
-/**
- MSR information returned for MSR index #IA32_VMX_MISC
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 4:0] Reports a value X that specifies the relationship between the
- /// rate of the VMX-preemption timer and that of the timestamp counter (TSC).
- /// Specifically, the VMX-preemption timer (if it is active) counts down by
- /// 1 every time bit X in the TSC changes due to a TSC increment.
- ///
- UINT32 VmxTimerRatio:5;
- ///
- /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA
- /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more
- /// details. This bit is read as 1 on any logical processor that supports
- /// the 1-setting of the "unrestricted guest" VM-execution control.
- ///
- UINT32 VmExitEferLma:1;
- ///
- /// [Bit 6] reports (if set) the support for activity state 1 (HLT).
- ///
- UINT32 HltActivityStateSupported:1;
- ///
- /// [Bit 7] reports (if set) the support for activity state 2 (shutdown).
- ///
- UINT32 ShutdownActivityStateSupported:1;
- ///
- /// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).
- ///
- UINT32 WaitForSipiActivityStateSupported:1;
- UINT32 Reserved1:5;
- ///
- /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used
- /// in VMX operation. If the processor supports Intel PT but does not allow
- /// it to be used in VMX operation, execution of VMXON clears
- /// IA32_RTIT_CTL.TraceEn (see "VMXON-Enter VMX Operation" in Chapter 30);
- /// any attempt to set that bit while in VMX operation (including VMX root
- /// operation) using the WRMSR instruction causes a general-protection
- /// exception.
- ///
- UINT32 ProcessorTraceSupported:1;
- ///
- /// [Bit 15] If read as 1, the RDMSR instruction can be used in system-
- /// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).
- /// See Section 34.15.6.3.
- ///
- UINT32 SmBaseMsrSupported:1;
- ///
- /// [Bits 24:16] Indicate the number of CR3-target values supported by the
- /// processor. This number is a value between 0 and 256, inclusive (bit 24
- /// is set if and only if bits 23:16 are clear).
- ///
- UINT32 NumberOfCr3TargetValues:9;
- ///
- /// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum
- /// number of MSRs that should appear in the VM-exit MSR-store list, the
- /// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if
- /// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the
- /// recommended maximum number of MSRs to be included in each list. If the
- /// limit is exceeded, undefined processor behavior may result (including a
- /// machine check during the VMX transition).
- ///
- UINT32 MsrStoreListMaximum:3;
- ///
- /// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set
- /// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1
- /// (see Section 34.14.4).
- ///
- UINT32 BlockSmiSupported:1;
- ///
- /// [Bit 29] read as 1, software can use VMWRITE to write to any supported
- /// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit
- /// information fields.
- ///
- UINT32 VmWriteSupported:1;
- ///
- /// [Bit 30] If read as 1, VM entry allows injection of a software
- /// interrupt, software exception, or privileged software exception with an
- /// instruction length of 0.
- ///
- UINT32 VmInjectSupported:1;
- UINT32 Reserved2:1;
- ///
- /// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the
- /// processor.
- ///
- UINT32 MsegRevisionIdentifier:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} IA32_VMX_MISC_REGISTER;
-
-
-/**
- Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,
- "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.
-
- @param ECX MSR_IA32_VMX_CR0_FIXED0 (0x00000486)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0);
- @endcode
- @note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM.
-**/
-#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
-
-
-/**
- Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7,
- "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.
-
- @param ECX MSR_IA32_VMX_CR0_FIXED1 (0x00000487)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1);
- @endcode
- @note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM.
-**/
-#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
-
-
-/**
- Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8,
- "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.
-
- @param ECX MSR_IA32_VMX_CR4_FIXED0 (0x00000488)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0);
- @endcode
- @note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM.
-**/
-#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
-
-
-/**
- Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8,
- "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.
-
- @param ECX MSR_IA32_VMX_CR4_FIXED1 (0x00000489)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1);
- @endcode
- @note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM.
-**/
-#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
-
-
-/**
- Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix
- A.9, "VMCS Enumeration.". If CPUID.01H:ECX.[5] = 1.
-
- @param ECX MSR_IA32_VMX_VMCS_ENUM (0x0000048A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM);
- @endcode
- @note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM.
-**/
-#define MSR_IA32_VMX_VMCS_ENUM 0x0000048A
-
-
-/**
- Capability Reporting Register of Secondary Processor-based VM-execution
- Controls (R/O) See Appendix A.3.3, "Secondary Processor- Based VM-Execution
- Controls.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]).
-
- @param ECX MSR_IA32_VMX_PROCBASED_CTLS2 (0x0000048B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2);
- @endcode
- @note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM.
-**/
-#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B
-
-
-/**
- Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10,
- "VPID and EPT Capabilities.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C
- TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] IA32_VMX_PROCBASED_C TLS2[37]) ).
-
- @param ECX MSR_IA32_VMX_EPT_VPID_CAP (0x0000048C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP);
- @endcode
- @note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM.
-**/
-#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C
-
-
-/**
- Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O)
- See Appendix A.3.1, "Pin-Based VMExecution Controls.". If (
- CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
-
- @param ECX MSR_IA32_VMX_TRUE_PINBASED_CTLS (0x0000048D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS);
- @endcode
- @note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM.
-**/
-#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D
-
-
-/**
- Capability Reporting Register of Primary Processor-based VM-execution Flex
- Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution
- Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
-
- @param ECX MSR_IA32_VMX_TRUE_PROCBASED_CTLS (0x0000048E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS);
- @endcode
- @note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM.
-**/
-#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E
-
-
-/**
- Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix
- A.4, "VM-Exit Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
-
- @param ECX MSR_IA32_VMX_TRUE_EXIT_CTLS (0x0000048F)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS);
- @endcode
- @note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM.
-**/
-#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F
-
-
-/**
- Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix
- A.5, "VM-Entry Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
-
- @param ECX MSR_IA32_VMX_TRUE_ENTRY_CTLS (0x00000490)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS);
- @endcode
- @note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM.
-**/
-#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
-
-
-/**
- Capability Reporting Register of VMfunction Controls (R/O). If(
- CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
-
- @param ECX MSR_IA32_VMX_VMFUNC (0x00000491)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC);
- @endcode
- @note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM.
-**/
-#define MSR_IA32_VMX_VMFUNC 0x00000491
-
-
-/**
- Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) &&
- IA32_PERF_CAPABILITIES[ 13] = 1.
-
- @param ECX MSR_IA32_A_PMCn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);
- AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);
- @endcode
- @note MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM.
- MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM.
- MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM.
- MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM.
- MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM.
- MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM.
- MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM.
- MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.
- @{
-**/
-#define MSR_IA32_A_PMC0 0x000004C1
-#define MSR_IA32_A_PMC1 0x000004C2
-#define MSR_IA32_A_PMC2 0x000004C3
-#define MSR_IA32_A_PMC3 0x000004C4
-#define MSR_IA32_A_PMC4 0x000004C5
-#define MSR_IA32_A_PMC5 0x000004C6
-#define MSR_IA32_A_PMC6 0x000004C7
-#define MSR_IA32_A_PMC7 0x000004C8
-/// @}
-
-
-/**
- (R/W). If IA32_MCG_CAP.LMCE_P =1.
-
- @param ECX MSR_IA32_MCG_EXT_CTL (0x000004D0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.
-
- Example usage
- @code
- MSR_IA32_MCG_EXT_CTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);
- AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64);
- @endcode
- @note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM.
-**/
-#define MSR_IA32_MCG_EXT_CTL 0x000004D0
-
-/**
- MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] LMCE_EN.
- ///
- UINT32 LMCE_EN:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_MCG_EXT_CTL_REGISTER;
-
-
-/**
- Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H,
- ECX=0H): EBX[2] = 1.
-
- @param ECX MSR_IA32_SGX_SVN_STATUS (0x00000500)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.
-
- Example usage
- @code
- MSR_IA32_SGX_SVN_STATUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS);
- @endcode
- @note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM.
-**/
-#define MSR_IA32_SGX_SVN_STATUS 0x00000500
-
-/**
- MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Lock. See Section 41.11.3, "Interactions with Authenticated
- /// Code Modules (ACMs)".
- ///
- UINT32 Lock:1;
- UINT32 Reserved1:15;
- ///
- /// [Bits 23:16] SGX_SVN_SINIT. See Section 41.11.3, "Interactions with
- /// Authenticated Code Modules (ACMs)".
- ///
- UINT32 SGX_SVN_SINIT:8;
- UINT32 Reserved2:8;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_SGX_SVN_STATUS_REGISTER;
-
-
-/**
- Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
- && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1)
- ) ).
-
- @param ECX MSR_IA32_RTIT_OUTPUT_BASE (0x00000560)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.
-
- Example usage
- @code
- MSR_IA32_RTIT_OUTPUT_BASE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);
- AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64);
- @endcode
- @note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM.
-**/
-#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
-
-/**
- MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved:7;
- ///
- /// [Bits 31:7] Base physical address.
- ///
- UINT32 Base:25;
- ///
- /// [Bits 63:32] Base physical address.
- ///
- UINT32 BaseHi:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_RTIT_OUTPUT_BASE_REGISTER;
-
-
-/**
- Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H,
- ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1)
- (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ).
-
- @param ECX MSR_IA32_RTIT_OUTPUT_MASK_PTRS (0x00000561)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.
-
- Example usage
- @code
- MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);
- AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64);
- @endcode
- @note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM.
-**/
-#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561
-
-/**
- MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved:7;
- ///
- /// [Bits 31:7] MaskOrTableOffset.
- ///
- UINT32 MaskOrTableOffset:25;
- ///
- /// [Bits 63:32] Output Offset.
- ///
- UINT32 OutputOffset:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER;
-
-/**
- Format of ToPA table entries.
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] END. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
- ///
- UINT32 END:1;
- UINT32 Reserved1:1;
- ///
- /// [Bit 2] INT. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
- ///
- UINT32 INT:1;
- UINT32 Reserved2:1;
- ///
- /// [Bit 4] STOP. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
- ///
- UINT32 STOP:1;
- UINT32 Reserved3:1;
- ///
- /// [Bit 6:9] Indicates the size of the associated output region. See Section
- /// 35.2.6.2, "Table of Physical Addresses (ToPA)".
- ///
- UINT32 Size:4;
- UINT32 Reserved4:2;
- ///
- /// [Bit 12:31] Output Region Base Physical Address low part.
- /// [Bit 12:31] Output Region Base Physical Address [12:63] value to match.
- /// ATTENTION: The size of the address field is determined by the processor's
- /// physical-address width (MAXPHYADDR) in bits, as reported in
- /// CPUID.80000008H:EAX[7:0]. the above part of address reserved.
- /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.
- /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
- ///
- UINT32 Base:20;
- ///
- /// [Bit 32:63] Output Region Base Physical Address high part.
- /// [Bit 32:63] Output Region Base Physical Address [12:63] value to match.
- /// ATTENTION: The size of the address field is determined by the processor's
- /// physical-address width (MAXPHYADDR) in bits, as reported in
- /// CPUID.80000008H:EAX[7:0]. the above part of address reserved.
- /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.
- /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
- ///
- UINT32 BaseHi:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} RTIT_TOPA_TABLE_ENTRY;
-
-///
-/// The size of the associated output region usd by Topa.
-///
-typedef enum {
- RtitTopaMemorySize4K = 0,
- RtitTopaMemorySize8K,
- RtitTopaMemorySize16K,
- RtitTopaMemorySize32K,
- RtitTopaMemorySize64K,
- RtitTopaMemorySize128K,
- RtitTopaMemorySize256K,
- RtitTopaMemorySize512K,
- RtitTopaMemorySize1M,
- RtitTopaMemorySize2M,
- RtitTopaMemorySize4M,
- RtitTopaMemorySize8M,
- RtitTopaMemorySize16M,
- RtitTopaMemorySize32M,
- RtitTopaMemorySize64M,
- RtitTopaMemorySize128M
-} RTIT_TOPA_MEMORY_SIZE;
-
-/**
- Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
-
- @param ECX MSR_IA32_RTIT_CTL (0x00000570)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_CTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_CTL_REGISTER.
-
- Example usage
- @code
- MSR_IA32_RTIT_CTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
- AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64);
- @endcode
- @note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.
-**/
-#define MSR_IA32_RTIT_CTL 0x00000570
-
-/**
- MSR information returned for MSR index #MSR_IA32_RTIT_CTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] TraceEn.
- ///
- UINT32 TraceEn:1;
- ///
- /// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
- ///
- UINT32 CYCEn:1;
- ///
- /// [Bit 2] OS.
- ///
- UINT32 OS:1;
- ///
- /// [Bit 3] User.
- ///
- UINT32 User:1;
- ///
- /// [Bit 4] PwrEvtEn.
- ///
- UINT32 PwrEvtEn:1;
- ///
- /// [Bit 5] FUPonPTW.
- ///
- UINT32 FUPonPTW:1;
- ///
- /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).
- ///
- UINT32 FabricEn:1;
- ///
- /// [Bit 7] CR3 filter.
- ///
- UINT32 CR3:1;
- ///
- /// [Bit 8] ToPA.
- ///
- UINT32 ToPA:1;
- ///
- /// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
- ///
- UINT32 MTCEn:1;
- ///
- /// [Bit 10] TSCEn.
- ///
- UINT32 TSCEn:1;
- ///
- /// [Bit 11] DisRETC.
- ///
- UINT32 DisRETC:1;
- ///
- /// [Bit 12] PTWEn.
- ///
- UINT32 PTWEn:1;
- ///
- /// [Bit 13] BranchEn.
- ///
- UINT32 BranchEn:1;
- ///
- /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
- ///
- UINT32 MTCFreq:4;
- UINT32 Reserved3:1;
- ///
- /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
- ///
- UINT32 CYCThresh:4;
- UINT32 Reserved4:1;
- ///
- /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
- ///
- UINT32 PSBFreq:4;
- UINT32 Reserved5:4;
- ///
- /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).
- ///
- UINT32 ADDR0_CFG:4;
- ///
- /// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1).
- ///
- UINT32 ADDR1_CFG:4;
- ///
- /// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2).
- ///
- UINT32 ADDR2_CFG:4;
- ///
- /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).
- ///
- UINT32 ADDR3_CFG:4;
- UINT32 Reserved6:16;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_RTIT_CTL_REGISTER;
-
-
-/**
- Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
-
- @param ECX MSR_IA32_RTIT_STATUS (0x00000571)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_STATUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_STATUS_REGISTER.
-
- Example usage
- @code
- MSR_IA32_RTIT_STATUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);
- AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64);
- @endcode
- @note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM.
-**/
-#define MSR_IA32_RTIT_STATUS 0x00000571
-
-/**
- MSR information returned for MSR index #MSR_IA32_RTIT_STATUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] FilterEn, (writes ignored).
- /// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1).
- ///
- UINT32 FilterEn:1;
- ///
- /// [Bit 1] ContexEn, (writes ignored).
- ///
- UINT32 ContexEn:1;
- ///
- /// [Bit 2] TriggerEn, (writes ignored).
- ///
- UINT32 TriggerEn:1;
- UINT32 Reserved1:1;
- ///
- /// [Bit 4] Error.
- ///
- UINT32 Error:1;
- ///
- /// [Bit 5] Stopped.
- ///
- UINT32 Stopped:1;
- UINT32 Reserved2:26;
- ///
- /// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3).
- ///
- UINT32 PacketByteCnt:17;
- UINT32 Reserved3:15;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_RTIT_STATUS_REGISTER;
-
-
-/**
- Trace Filter CR3 Match Register (R/W).
- If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
-
- @param ECX MSR_IA32_RTIT_CR3_MATCH (0x00000572)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.
-
- Example usage
- @code
- MSR_IA32_RTIT_CR3_MATCH_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH);
- AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64);
- @endcode
- @note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM.
-**/
-#define MSR_IA32_RTIT_CR3_MATCH 0x00000572
-
-/**
- MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved:5;
- ///
- /// [Bits 31:5] CR3[63:5] value to match.
- ///
- UINT32 Cr3:27;
- ///
- /// [Bits 63:32] CR3[63:5] value to match.
- ///
- UINT32 Cr3Hi:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_RTIT_CR3_MATCH_REGISTER;
-
-
-/**
- Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
-
- @param ECX MSR_IA32_RTIT_ADDRn_A
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
-
- Example usage
- @code
- MSR_IA32_RTIT_ADDR_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);
- AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);
- @endcode
- @note MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM.
- MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM.
- MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM.
- MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.
- @{
-**/
-#define MSR_IA32_RTIT_ADDR0_A 0x00000580
-#define MSR_IA32_RTIT_ADDR1_A 0x00000582
-#define MSR_IA32_RTIT_ADDR2_A 0x00000584
-#define MSR_IA32_RTIT_ADDR3_A 0x00000586
-/// @}
-
-
-/**
- Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
-
- @param ECX MSR_IA32_RTIT_ADDRn_B
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
-
- Example usage
- @code
- MSR_IA32_RTIT_ADDR_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);
- AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);
- @endcode
- @note MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM.
- MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM.
- MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM.
- MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.
- @{
-**/
-#define MSR_IA32_RTIT_ADDR0_B 0x00000581
-#define MSR_IA32_RTIT_ADDR1_B 0x00000583
-#define MSR_IA32_RTIT_ADDR2_B 0x00000585
-#define MSR_IA32_RTIT_ADDR3_B 0x00000587
-/// @}
-
-
-/**
- MSR information returned for MSR indexes
- #MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and
- #MSR_IA32_RTIT_ADDR0_B to #MSR_IA32_RTIT_ADDR3_B
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Virtual Address.
- ///
- UINT32 VirtualAddress:32;
- ///
- /// [Bits 47:32] Virtual Address.
- ///
- UINT32 VirtualAddressHi:16;
- ///
- /// [Bits 63:48] SignExt_VA.
- ///
- UINT32 SignExt_VA:16;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_RTIT_ADDR_REGISTER;
-
-
-/**
- DS Save Area (R/W) Points to the linear address of the first byte of the DS
- buffer management area, which is used to manage the BTS and PEBS buffers.
- See Section 18.6.3.4, "Debug Store (DS) Mechanism.". If(
- CPUID.01H:EDX.DS[21] = 1. The linear address of the first byte of the DS
- buffer management area, if IA-32e mode is active.
-
- @param ECX MSR_IA32_DS_AREA (0x00000600)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_DS_AREA_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_DS_AREA_REGISTER.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_DS_AREA);
- AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr);
- @endcode
- @note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM.
-**/
-#define MSR_IA32_DS_AREA 0x00000600
-
-
-/**
- TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] =
- 1.
-
- @param ECX MSR_IA32_TSC_DEADLINE (0x000006E0)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE);
- AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr);
- @endcode
- @note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM.
-**/
-#define MSR_IA32_TSC_DEADLINE 0x000006E0
-
-
-/**
- Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1.
-
- @param ECX MSR_IA32_PM_ENABLE (0x00000770)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PM_ENABLE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PM_ENABLE_REGISTER.
-
- Example usage
- @code
- MSR_IA32_PM_ENABLE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE);
- AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64);
- @endcode
- @note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM.
-**/
-#define MSR_IA32_PM_ENABLE 0x00000770
-
-/**
- MSR information returned for MSR index #MSR_IA32_PM_ENABLE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If
- /// CPUID.06H:EAX.[7] = 1.
- ///
- UINT32 HWP_ENABLE:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PM_ENABLE_REGISTER;
-
-
-/**
- HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1.
-
- @param ECX MSR_IA32_HWP_CAPABILITIES (0x00000771)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.
-
- Example usage
- @code
- MSR_IA32_HWP_CAPABILITIES_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES);
- @endcode
- @note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM.
-**/
-#define MSR_IA32_HWP_CAPABILITIES 0x00000771
-
-/**
- MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance
- /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
- ///
- UINT32 Highest_Performance:8;
- ///
- /// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP
- /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
- ///
- UINT32 Guaranteed_Performance:8;
- ///
- /// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP
- /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
- ///
- UINT32 Most_Efficient_Performance:8;
- ///
- /// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance
- /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
- ///
- UINT32 Lowest_Performance:8;
- UINT32 Reserved:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_HWP_CAPABILITIES_REGISTER;
-
-
-/**
- Power Management Control Hints for All Logical Processors in a Package
- (R/W). If CPUID.06H:EAX.[11] = 1.
-
- @param ECX MSR_IA32_HWP_REQUEST_PKG (0x00000772)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.
-
- Example usage
- @code
- MSR_IA32_HWP_REQUEST_PKG_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG);
- AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64);
- @endcode
- @note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM.
-**/
-#define MSR_IA32_HWP_REQUEST_PKG 0x00000772
-
-/**
- MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
- /// CPUID.06H:EAX.[11] = 1.
- ///
- UINT32 Minimum_Performance:8;
- ///
- /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
- /// CPUID.06H:EAX.[11] = 1.
- ///
- UINT32 Maximum_Performance:8;
- ///
- /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
- /// If CPUID.06H:EAX.[11] = 1.
- ///
- UINT32 Desired_Performance:8;
- ///
- /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
- /// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.
- ///
- UINT32 Energy_Performance_Preference:8;
- ///
- /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
- /// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.
- ///
- UINT32 Activity_Window:10;
- UINT32 Reserved:22;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_HWP_REQUEST_PKG_REGISTER;
-
-
-/**
- Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1.
-
- @param ECX MSR_IA32_HWP_INTERRUPT (0x00000773)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.
-
- Example usage
- @code
- MSR_IA32_HWP_INTERRUPT_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT);
- AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64);
- @endcode
- @note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM.
-**/
-#define MSR_IA32_HWP_INTERRUPT 0x00000773
-
-/**
- MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP
- /// Notifications". If CPUID.06H:EAX.[8] = 1.
- ///
- UINT32 EN_Guaranteed_Performance_Change:1;
- ///
- /// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications".
- /// If CPUID.06H:EAX.[8] = 1.
- ///
- UINT32 EN_Excursion_Minimum:1;
- UINT32 Reserved1:30;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_HWP_INTERRUPT_REGISTER;
-
-
-/**
- Power Management Control Hints to a Logical Processor (R/W). If
- CPUID.06H:EAX.[7] = 1.
-
- @param ECX MSR_IA32_HWP_REQUEST (0x00000774)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_HWP_REQUEST_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_HWP_REQUEST_REGISTER.
-
- Example usage
- @code
- MSR_IA32_HWP_REQUEST_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST);
- AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64);
- @endcode
- @note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM.
-**/
-#define MSR_IA32_HWP_REQUEST 0x00000774
-
-/**
- MSR information returned for MSR index #MSR_IA32_HWP_REQUEST
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
- /// CPUID.06H:EAX.[7] = 1.
- ///
- UINT32 Minimum_Performance:8;
- ///
- /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
- /// CPUID.06H:EAX.[7] = 1.
- ///
- UINT32 Maximum_Performance:8;
- ///
- /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
- /// If CPUID.06H:EAX.[7] = 1.
- ///
- UINT32 Desired_Performance:8;
- ///
- /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
- /// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1.
- ///
- UINT32 Energy_Performance_Preference:8;
- ///
- /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
- /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1.
- ///
- UINT32 Activity_Window:10;
- ///
- /// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If
- /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1.
- ///
- UINT32 Package_Control:1;
- UINT32 Reserved:21;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_HWP_REQUEST_REGISTER;
-
-
-/**
- Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If
- CPUID.06H:EAX.[7] = 1.
-
- @param ECX MSR_IA32_HWP_STATUS (0x00000777)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_HWP_STATUS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_HWP_STATUS_REGISTER.
-
- Example usage
- @code
- MSR_IA32_HWP_STATUS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS);
- AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64);
- @endcode
- @note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM.
-**/
-#define MSR_IA32_HWP_STATUS 0x00000777
-
-/**
- MSR information returned for MSR index #MSR_IA32_HWP_STATUS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5,
- /// "HWP Feedback". If CPUID.06H:EAX.[7] = 1.
- ///
- UINT32 Guaranteed_Performance_Change:1;
- UINT32 Reserved1:1;
- ///
- /// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP
- /// Feedback". If CPUID.06H:EAX.[7] = 1.
- ///
- UINT32 Excursion_To_Minimum:1;
- UINT32 Reserved2:29;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_HWP_STATUS_REGISTER;
-
-
-/**
- x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1
- && IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_APICID (0x00000802)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID);
- @endcode
- @note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM.
-**/
-#define MSR_IA32_X2APIC_APICID 0x00000802
-
-
-/**
- x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_VERSION (0x00000803)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION);
- @endcode
- @note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM.
-**/
-#define MSR_IA32_X2APIC_VERSION 0x00000803
-
-
-/**
- x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_TPR (0x00000808)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR);
- AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr);
- @endcode
- @note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM.
-**/
-#define MSR_IA32_X2APIC_TPR 0x00000808
-
-
-/**
- x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_PPR (0x0000080A)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR);
- @endcode
- @note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM.
-**/
-#define MSR_IA32_X2APIC_PPR 0x0000080A
-
-
-/**
- x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10]
- = 1.
-
- @param ECX MSR_IA32_X2APIC_EOI (0x0000080B)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = 0;
- AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr);
- @endcode
- @note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM.
-**/
-#define MSR_IA32_X2APIC_EOI 0x0000080B
-
-
-/**
- x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_LDR (0x0000080D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR);
- @endcode
- @note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM.
-**/
-#define MSR_IA32_X2APIC_LDR 0x0000080D
-
-
-/**
- x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1
- && IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_SIVR (0x0000080F)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR);
- AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr);
- @endcode
- @note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM.
-**/
-#define MSR_IA32_X2APIC_SIVR 0x0000080F
-
-
-/**
- x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O).
- If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_ISRn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);
- @endcode
- @note MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM.
- MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM.
- MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM.
- MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM.
- MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM.
- MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM.
- MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM.
- MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.
- @{
-**/
-#define MSR_IA32_X2APIC_ISR0 0x00000810
-#define MSR_IA32_X2APIC_ISR1 0x00000811
-#define MSR_IA32_X2APIC_ISR2 0x00000812
-#define MSR_IA32_X2APIC_ISR3 0x00000813
-#define MSR_IA32_X2APIC_ISR4 0x00000814
-#define MSR_IA32_X2APIC_ISR5 0x00000815
-#define MSR_IA32_X2APIC_ISR6 0x00000816
-#define MSR_IA32_X2APIC_ISR7 0x00000817
-/// @}
-
-
-/**
- x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O).
- If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_TMRn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);
- @endcode
- @note MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM.
- MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM.
- MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM.
- MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM.
- MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM.
- MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM.
- MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM.
- MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.
- @{
-**/
-#define MSR_IA32_X2APIC_TMR0 0x00000818
-#define MSR_IA32_X2APIC_TMR1 0x00000819
-#define MSR_IA32_X2APIC_TMR2 0x0000081A
-#define MSR_IA32_X2APIC_TMR3 0x0000081B
-#define MSR_IA32_X2APIC_TMR4 0x0000081C
-#define MSR_IA32_X2APIC_TMR5 0x0000081D
-#define MSR_IA32_X2APIC_TMR6 0x0000081E
-#define MSR_IA32_X2APIC_TMR7 0x0000081F
-/// @}
-
-
-/**
- x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O).
- If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_IRRn
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);
- @endcode
- @note MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM.
- MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM.
- MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM.
- MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM.
- MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM.
- MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM.
- MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM.
- MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.
- @{
-**/
-#define MSR_IA32_X2APIC_IRR0 0x00000820
-#define MSR_IA32_X2APIC_IRR1 0x00000821
-#define MSR_IA32_X2APIC_IRR2 0x00000822
-#define MSR_IA32_X2APIC_IRR3 0x00000823
-#define MSR_IA32_X2APIC_IRR4 0x00000824
-#define MSR_IA32_X2APIC_IRR5 0x00000825
-#define MSR_IA32_X2APIC_IRR6 0x00000826
-#define MSR_IA32_X2APIC_IRR7 0x00000827
-/// @}
-
-
-/**
- x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_ESR (0x00000828)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR);
- AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr);
- @endcode
- @note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM.
-**/
-#define MSR_IA32_X2APIC_ESR 0x00000828
-
-
-/**
- x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If
- CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_LVT_CMCI (0x0000082F)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI);
- AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr);
- @endcode
- @note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM.
-**/
-#define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F
-
-
-/**
- x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_ICR (0x00000830)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR);
- AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr);
- @endcode
- @note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM.
-**/
-#define MSR_IA32_X2APIC_ICR 0x00000830
-
-
-/**
- x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_LVT_TIMER (0x00000832)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER);
- AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr);
- @endcode
- @note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM.
-**/
-#define MSR_IA32_X2APIC_LVT_TIMER 0x00000832
-
-
-/**
- x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] =
- 1 && IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_LVT_THERMAL (0x00000833)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL);
- AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr);
- @endcode
- @note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM.
-**/
-#define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833
-
-
-/**
- x2APIC LVT Performance Monitor Interrupt Register (R/W). If
- CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_LVT_PMI (0x00000834)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI);
- AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr);
- @endcode
- @note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM.
-**/
-#define MSR_IA32_X2APIC_LVT_PMI 0x00000834
-
-
-/**
- x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_LVT_LINT0 (0x00000835)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0);
- AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr);
- @endcode
- @note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM.
-**/
-#define MSR_IA32_X2APIC_LVT_LINT0 0x00000835
-
-
-/**
- x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_LVT_LINT1 (0x00000836)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1);
- AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr);
- @endcode
- @note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM.
-**/
-#define MSR_IA32_X2APIC_LVT_LINT1 0x00000836
-
-
-/**
- x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_LVT_ERROR (0x00000837)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR);
- AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr);
- @endcode
- @note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM.
-**/
-#define MSR_IA32_X2APIC_LVT_ERROR 0x00000837
-
-
-/**
- x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_INIT_COUNT (0x00000838)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT);
- AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr);
- @endcode
- @note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM.
-**/
-#define MSR_IA32_X2APIC_INIT_COUNT 0x00000838
-
-
-/**
- x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_CUR_COUNT (0x00000839)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT);
- @endcode
- @note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM.
-**/
-#define MSR_IA32_X2APIC_CUR_COUNT 0x00000839
-
-
-/**
- x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_DIV_CONF (0x0000083E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF);
- AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr);
- @endcode
- @note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM.
-**/
-#define MSR_IA32_X2APIC_DIV_CONF 0x0000083E
-
-
-/**
- x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 &&
- IA32_APIC_BASE.[10] = 1.
-
- @param ECX MSR_IA32_X2APIC_SELF_IPI (0x0000083F)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = 0;
- AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr);
- @endcode
- @note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM.
-**/
-#define MSR_IA32_X2APIC_SELF_IPI 0x0000083F
-
-
-/**
- Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1.
-
- @param ECX MSR_IA32_DEBUG_INTERFACE (0x00000C80)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.
-
- Example usage
- @code
- MSR_IA32_DEBUG_INTERFACE_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);
- AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64);
- @endcode
- @note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM.
-**/
-#define MSR_IA32_DEBUG_INTERFACE 0x00000C80
-
-/**
- MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features.
- /// Default is 0. If CPUID.01H:ECX.[11] = 1.
- ///
- UINT32 Enable:1;
- UINT32 Reserved1:29;
- ///
- /// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The
- /// lock bit is set automatically on the first SMI assertion even if not
- /// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1.
- ///
- UINT32 Lock:1;
- ///
- /// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to
- /// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1.
- ///
- UINT32 DebugOccurred:1;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_DEBUG_INTERFACE_REGISTER;
-
-
-/**
- L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ).
-
- @param ECX MSR_IA32_L3_QOS_CFG (0x00000C81)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.
-
- Example usage
- @code
- MSR_IA32_L3_QOS_CFG_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG);
- AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64);
- @endcode
- @note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.
-**/
-#define MSR_IA32_L3_QOS_CFG 0x00000C81
-
-/**
- MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate
- /// in Code and Data Prioritization (CDP) mode.
- ///
- UINT32 Enable:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_L3_QOS_CFG_REGISTER;
-
-/**
- L2 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=2):ECX.[2] = 1 ).
-
- @param ECX MSR_IA32_L2_QOS_CFG (0x00000C82)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.
-
- Example usage
- @code
- MSR_IA32_L2_QOS_CFG_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L2_QOS_CFG);
- AsmWriteMsr64 (MSR_IA32_L2_QOS_CFG, Msr.Uint64);
- @endcode
- @note MSR_IA32_L2_QOS_CFG is defined as IA32_L2_QOS_CFG in SDM.
-**/
-#define MSR_IA32_L2_QOS_CFG 0x00000C82
-
-/**
- MSR information returned for MSR index #MSR_IA32_L2_QOS_CFG
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] Enable (R/W) Set 1 to enable L2 CAT masks and COS to operate
- /// in Code and Data Prioritization (CDP) mode.
- ///
- UINT32 Enable:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_L2_QOS_CFG_REGISTER;
-
-/**
- Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]
- = 1 ).
-
- @param ECX MSR_IA32_QM_EVTSEL (0x00000C8D)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_QM_EVTSEL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_QM_EVTSEL_REGISTER.
-
- Example usage
- @code
- MSR_IA32_QM_EVTSEL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL);
- AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64);
- @endcode
- @note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
-**/
-#define MSR_IA32_QM_EVTSEL 0x00000C8D
-
-/**
- MSR information returned for MSR index #MSR_IA32_QM_EVTSEL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 7:0] Event ID: ID of a supported monitoring event to report via
- /// IA32_QM_CTR.
- ///
- UINT32 EventID:8;
- UINT32 Reserved:24;
- ///
- /// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to
- /// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` (
- /// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
- ///
- UINT32 ResourceMonitoringID:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_QM_EVTSEL_REGISTER;
-
-
-/**
- Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1
- ).
-
- @param ECX MSR_IA32_QM_CTR (0x00000C8E)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_QM_CTR_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_QM_CTR_REGISTER.
-
- Example usage
- @code
- MSR_IA32_QM_CTR_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR);
- @endcode
- @note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM.
-**/
-#define MSR_IA32_QM_CTR 0x00000C8E
-
-/**
- MSR information returned for MSR index #MSR_IA32_QM_CTR
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Resource Monitored Data.
- ///
- UINT32 ResourceMonitoredData:32;
- ///
- /// [Bits 61:32] Resource Monitored Data.
- ///
- UINT32 ResourceMonitoredDataHi:30;
- ///
- /// [Bit 62] Unavailable: If 1, indicates data for this RMID is not
- /// available or not monitored for this resource or RMID.
- ///
- UINT32 Unavailable:1;
- ///
- /// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was
- /// written to IA32_PQR_QM_EVTSEL.
- ///
- UINT32 Error:1;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_QM_CTR_REGISTER;
-
-
-/**
- Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12]
- =1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ).
-
- @param ECX MSR_IA32_PQR_ASSOC (0x00000C8F)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PQR_ASSOC_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PQR_ASSOC_REGISTER.
-
- Example usage
- @code
- MSR_IA32_PQR_ASSOC_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC);
- AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64);
- @endcode
- @note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
-**/
-#define MSR_IA32_PQR_ASSOC 0x00000C8F
-
-/**
- MSR information returned for MSR index #MSR_IA32_PQR_ASSOC
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Resource Monitoring ID (R/W): ID for monitoring hardware
- /// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2`
- /// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
- ///
- UINT32 ResourceMonitoringID:32;
- ///
- /// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on
- /// writes); returns the current COS when read. If ( CPUID.(EAX=07H,
- /// ECX=0):EBX.[15] = 1 ).
- ///
- UINT32 COS:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PQR_ASSOC_REGISTER;
-
-
-/**
- Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H,
- ECX=0H):EBX[14] = 1).
-
- @param ECX MSR_IA32_BNDCFGS (0x00000D90)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_BNDCFGS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_BNDCFGS_REGISTER.
-
- Example usage
- @code
- MSR_IA32_BNDCFGS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS);
- AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64);
- @endcode
- @note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM.
-**/
-#define MSR_IA32_BNDCFGS 0x00000D90
-
-/**
- MSR information returned for MSR index #MSR_IA32_BNDCFGS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] EN: Enable Intel MPX in supervisor mode.
- ///
- UINT32 EN:1;
- ///
- /// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch
- /// instructions in the absence of the BND prefix.
- ///
- UINT32 BNDPRESERVE:1;
- UINT32 Reserved:10;
- ///
- /// [Bits 31:12] Base Address of Bound Directory.
- ///
- UINT32 Base:20;
- ///
- /// [Bits 63:32] Base Address of Bound Directory.
- ///
- UINT32 BaseHi:32;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_BNDCFGS_REGISTER;
-
-
-/**
- Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1.
-
- @param ECX MSR_IA32_XSS (0x00000DA0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_XSS_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_XSS_REGISTER.
-
- Example usage
- @code
- MSR_IA32_XSS_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS);
- AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64);
- @endcode
- @note MSR_IA32_XSS is defined as IA32_XSS in SDM.
-**/
-#define MSR_IA32_XSS 0x00000DA0
-
-/**
- MSR information returned for MSR index #MSR_IA32_XSS
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:8;
- ///
- /// [Bit 8] Trace Packet Configuration State (R/W).
- ///
- UINT32 TracePacketConfigurationState:1;
- UINT32 Reserved2:23;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_XSS_REGISTER;
-
-
-/**
- Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1.
-
- @param ECX MSR_IA32_PKG_HDC_CTL (0x00000DB0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.
-
- Example usage
- @code
- MSR_IA32_PKG_HDC_CTL_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL);
- AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64);
- @endcode
- @note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM.
-**/
-#define MSR_IA32_PKG_HDC_CTL 0x00000DB0
-
-/**
- MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] HDC_Pkg_Enable (R/W) Force HDC idling or wake up HDC-idled
- /// logical processors in the package. See Section 14.5.2, "Package level
- /// Enabling HDC". If CPUID.06H:EAX.[13] = 1.
- ///
- UINT32 HDC_Pkg_Enable:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PKG_HDC_CTL_REGISTER;
-
-
-/**
- Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1.
-
- @param ECX MSR_IA32_PM_CTL1 (0x00000DB1)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_PM_CTL1_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_PM_CTL1_REGISTER.
-
- Example usage
- @code
- MSR_IA32_PM_CTL1_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1);
- AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64);
- @endcode
- @note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM.
-**/
-#define MSR_IA32_PM_CTL1 0x00000DB1
-
-/**
- MSR information returned for MSR index #MSR_IA32_PM_CTL1
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] HDC_Allow_Block (R/W) Allow/Block this logical processor for
- /// package level HDC control. See Section 14.5.3.
- /// If CPUID.06H:EAX.[13] = 1.
- ///
- UINT32 HDC_Allow_Block:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_PM_CTL1_REGISTER;
-
-
-/**
- Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1.
- Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical
- processor. See Section 14.5.4.1. If CPUID.06H:EAX.[13] = 1.
-
- @param ECX MSR_IA32_THREAD_STALL (0x00000DB2)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL);
- @endcode
- @note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM.
-**/
-#define MSR_IA32_THREAD_STALL 0x00000DB2
-
-
-/**
- Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0]
- CPUID.80000001H:EDX.[2 9]).
-
- @param ECX MSR_IA32_EFER (0xC0000080)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_EFER_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_EFER_REGISTER.
-
- Example usage
- @code
- MSR_IA32_EFER_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);
- AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64);
- @endcode
- @note MSR_IA32_EFER is defined as IA32_EFER in SDM.
-**/
-#define MSR_IA32_EFER 0xC0000080
-
-/**
- MSR information returned for MSR index #MSR_IA32_EFER
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET
- /// instructions in 64-bit mode.
- ///
- UINT32 SCE:1;
- UINT32 Reserved1:7;
- ///
- /// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode
- /// operation.
- ///
- UINT32 LME:1;
- UINT32 Reserved2:1;
- ///
- /// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode
- /// is active when set.
- ///
- UINT32 LMA:1;
- ///
- /// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W).
- ///
- UINT32 NXE:1;
- UINT32 Reserved3:20;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_EFER_REGISTER;
-
-
-/**
- System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
-
- @param ECX MSR_IA32_STAR (0xC0000081)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_STAR);
- AsmWriteMsr64 (MSR_IA32_STAR, Msr);
- @endcode
- @note MSR_IA32_STAR is defined as IA32_STAR in SDM.
-**/
-#define MSR_IA32_STAR 0xC0000081
-
-
-/**
- IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
-
- @param ECX MSR_IA32_LSTAR (0xC0000082)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_LSTAR);
- AsmWriteMsr64 (MSR_IA32_LSTAR, Msr);
- @endcode
- @note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM.
-**/
-#define MSR_IA32_LSTAR 0xC0000082
-
-/**
- IA-32e Mode System Call Target Address (R/W) Not used, as the SYSCALL
- instruction is not recognized in compatibility mode. If
- CPUID.80000001:EDX.[29] = 1.
-
- @param ECX MSR_IA32_CSTAR (0xC0000083)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_CSTAR);
- AsmWriteMsr64 (MSR_IA32_CSTAR, Msr);
- @endcode
- @note MSR_IA32_CSTAR is defined as IA32_CSTAR in SDM.
-**/
-#define MSR_IA32_CSTAR 0xC0000083
-
-/**
- System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.
-
- @param ECX MSR_IA32_FMASK (0xC0000084)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_FMASK);
- AsmWriteMsr64 (MSR_IA32_FMASK, Msr);
- @endcode
- @note MSR_IA32_FMASK is defined as IA32_FMASK in SDM.
-**/
-#define MSR_IA32_FMASK 0xC0000084
-
-
-/**
- Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1.
-
- @param ECX MSR_IA32_FS_BASE (0xC0000100)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_FS_BASE);
- AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr);
- @endcode
- @note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM.
-**/
-#define MSR_IA32_FS_BASE 0xC0000100
-
-
-/**
- Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
-
- @param ECX MSR_IA32_GS_BASE (0xC0000101)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_GS_BASE);
- AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr);
- @endcode
- @note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM.
-**/
-#define MSR_IA32_GS_BASE 0xC0000101
-
-
-/**
- Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
-
- @param ECX MSR_IA32_KERNEL_GS_BASE (0xC0000102)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- Example usage
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE);
- AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr);
- @endcode
- @note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM.
-**/
-#define MSR_IA32_KERNEL_GS_BASE 0xC0000102
-
-
-/**
- Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1.
-
- @param ECX MSR_IA32_TSC_AUX (0xC0000103)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IA32_TSC_AUX_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IA32_TSC_AUX_REGISTER.
-
- Example usage
- @code
- MSR_IA32_TSC_AUX_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX);
- AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64);
- @endcode
- @note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM.
-**/
-#define MSR_IA32_TSC_AUX 0xC0000103
-
-/**
- MSR information returned for MSR index #MSR_IA32_TSC_AUX
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] AUX: Auxiliary signature of TSC.
- ///
- UINT32 AUX:32;
- UINT32 Reserved:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IA32_TSC_AUX_REGISTER;
-
-#endif
diff --git a/MdePkg/Include/Uefi/UefiBaseType.h b/MdePkg/Include/Uefi/UefiBaseType.h
index b9183fda..d1900b8d 100755
--- a/MdePkg/Include/Uefi/UefiBaseType.h
+++ b/MdePkg/Include/Uefi/UefiBaseType.h
@@ -4,6 +4,7 @@
Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
Portions copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.
Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -21,37 +22,37 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
///
/// 128-bit buffer containing a unique identifier value.
///
-typedef GUID EFI_GUID;
+typedef GUID EFI_GUID;
///
/// Function return status for EFI API.
///
-typedef RETURN_STATUS EFI_STATUS;
+typedef RETURN_STATUS EFI_STATUS;
///
/// A collection of related interfaces.
///
-typedef VOID *EFI_HANDLE;
+typedef VOID *EFI_HANDLE;
///
/// Handle to an event structure.
///
-typedef VOID *EFI_EVENT;
+typedef VOID *EFI_EVENT;
///
/// Task priority level.
///
-typedef UINTN EFI_TPL;
+typedef UINTN EFI_TPL;
///
/// Logical block address.
///
-typedef UINT64 EFI_LBA;
+typedef UINT64 EFI_LBA;
///
/// 64-bit physical memory address.
///
-typedef UINT64 EFI_PHYSICAL_ADDRESS;
+typedef UINT64 EFI_PHYSICAL_ADDRESS;
///
/// 64-bit virtual memory address.
///
-typedef UINT64 EFI_VIRTUAL_ADDRESS;
+typedef UINT64 EFI_VIRTUAL_ADDRESS;
///
/// EFI Time Abstraction:
@@ -65,20 +66,19 @@ typedef UINT64 EFI_VIRTUAL_ADDRESS;
/// TimeZone: -1440 to 1440 or 2047
///
typedef struct {
- UINT16 Year;
- UINT8 Month;
- UINT8 Day;
- UINT8 Hour;
- UINT8 Minute;
- UINT8 Second;
- UINT8 Pad1;
- UINT32 Nanosecond;
- INT16 TimeZone;
- UINT8 Daylight;
- UINT8 Pad2;
+ UINT16 Year;
+ UINT8 Month;
+ UINT8 Day;
+ UINT8 Hour;
+ UINT8 Minute;
+ UINT8 Second;
+ UINT8 Pad1;
+ UINT32 Nanosecond;
+ INT16 TimeZone;
+ UINT8 Daylight;
+ UINT8 Pad2;
} EFI_TIME;
-
///
/// 4-byte buffer. An IPv4 internet protocol address.
///
@@ -93,7 +93,7 @@ typedef IPv6_ADDRESS EFI_IPv6_ADDRESS;
/// 32-byte buffer containing a network Media Access Control address.
///
typedef struct {
- UINT8 Addr[32];
+ UINT8 Addr[32];
} EFI_MAC_ADDRESS;
///
@@ -101,12 +101,11 @@ typedef struct {
/// An IPv4 or IPv6 internet protocol address.
///
typedef union {
- UINT32 Addr[4];
- EFI_IPv4_ADDRESS v4;
- EFI_IPv6_ADDRESS v6;
+ UINT32 Addr[4];
+ EFI_IPv4_ADDRESS v4;
+ EFI_IPv6_ADDRESS v6;
} EFI_IP_ADDRESS;
-
///
/// Enumeration of EFI_STATUS.
///@{
@@ -142,22 +141,24 @@ typedef union {
#define EFI_END_OF_FILE RETURN_END_OF_FILE
#define EFI_INVALID_LANGUAGE RETURN_INVALID_LANGUAGE
#define EFI_COMPROMISED_DATA RETURN_COMPROMISED_DATA
+#define EFI_IP_ADDRESS_CONFLICT RETURN_IP_ADDRESS_CONFLICT
#define EFI_HTTP_ERROR RETURN_HTTP_ERROR
-#define EFI_WARN_UNKNOWN_GLYPH RETURN_WARN_UNKNOWN_GLYPH
-#define EFI_WARN_DELETE_FAILURE RETURN_WARN_DELETE_FAILURE
-#define EFI_WARN_WRITE_FAILURE RETURN_WARN_WRITE_FAILURE
-#define EFI_WARN_BUFFER_TOO_SMALL RETURN_WARN_BUFFER_TOO_SMALL
-#define EFI_WARN_STALE_DATA RETURN_WARN_STALE_DATA
-#define EFI_WARN_FILE_SYSTEM RETURN_WARN_FILE_SYSTEM
+#define EFI_WARN_UNKNOWN_GLYPH RETURN_WARN_UNKNOWN_GLYPH
+#define EFI_WARN_DELETE_FAILURE RETURN_WARN_DELETE_FAILURE
+#define EFI_WARN_WRITE_FAILURE RETURN_WARN_WRITE_FAILURE
+#define EFI_WARN_BUFFER_TOO_SMALL RETURN_WARN_BUFFER_TOO_SMALL
+#define EFI_WARN_STALE_DATA RETURN_WARN_STALE_DATA
+#define EFI_WARN_FILE_SYSTEM RETURN_WARN_FILE_SYSTEM
+#define EFI_WARN_RESET_REQUIRED RETURN_WARN_RESET_REQUIRED
///@}
///
/// Define macro to encode the status code.
///
-#define EFIERR(_a) ENCODE_ERROR(_a)
+#define EFIERR(_a) ENCODE_ERROR(_a)
-#define EFI_ERROR(A) RETURN_ERROR(A)
+#define EFI_ERROR(A) RETURN_ERROR(A)
///
/// ICMP error definitions
@@ -171,9 +172,9 @@ typedef union {
///
/// Tcp connection status definitions
///@{
-#define EFI_CONNECTION_FIN EFIERR(104)
-#define EFI_CONNECTION_RESET EFIERR(105)
-#define EFI_CONNECTION_REFUSED EFIERR(106)
+#define EFI_CONNECTION_FIN EFIERR(104)
+#define EFI_CONNECTION_RESET EFIERR(105)
+#define EFI_CONNECTION_REFUSED EFIERR(106)
///@}
//
@@ -181,9 +182,9 @@ typedef union {
// 4KB. This should in no way be confused with the page size of the processor.
// An EFI_PAGE is just the quanta of memory in EFI.
//
-#define EFI_PAGE_SIZE SIZE_4KB
-#define EFI_PAGE_MASK 0xFFF
-#define EFI_PAGE_SHIFT 12
+#define EFI_PAGE_SIZE SIZE_4KB
+#define EFI_PAGE_MASK 0xFFF
+#define EFI_PAGE_SHIFT 12
/**
Macro that converts a size, in bytes, to a number of EFI_PAGESs.
@@ -214,22 +215,22 @@ typedef union {
///
/// PE32+ Machine type for IA32 UEFI images.
///
-#define EFI_IMAGE_MACHINE_IA32 0x014C
+#define EFI_IMAGE_MACHINE_IA32 0x014C
///
/// PE32+ Machine type for IA64 UEFI images.
///
-#define EFI_IMAGE_MACHINE_IA64 0x0200
+#define EFI_IMAGE_MACHINE_IA64 0x0200
///
/// PE32+ Machine type for EBC UEFI images.
///
-#define EFI_IMAGE_MACHINE_EBC 0x0EBC
+#define EFI_IMAGE_MACHINE_EBC 0x0EBC
///
/// PE32+ Machine type for X64 UEFI images.
///
-#define EFI_IMAGE_MACHINE_X64 0x8664
+#define EFI_IMAGE_MACHINE_X64 0x8664
///
/// PE32+ Machine type for ARM mixed ARM and Thumb/Thumb2 images.
@@ -248,64 +249,77 @@ typedef union {
#define EFI_IMAGE_MACHINE_RISCV64 0x5064
#define EFI_IMAGE_MACHINE_RISCV128 0x5128
-#if !defined(EFI_IMAGE_MACHINE_TYPE_VALUE) && !defined(EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE)
-#if defined (MDE_CPU_IA32)
+///
+/// PE32+ Machine type for LoongArch 32/64 images.
+///
+#define EFI_IMAGE_MACHINE_LOONGARCH32 0x6232
+#define EFI_IMAGE_MACHINE_LOONGARCH64 0x6264
+
+#if !defined (EFI_IMAGE_MACHINE_TYPE_VALUE) && !defined (EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE)
+ #if defined (MDE_CPU_IA32)
#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
((Machine) == EFI_IMAGE_MACHINE_IA32)
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_X64)
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_X64)
-#elif defined (MDE_CPU_X64)
+ #elif defined (MDE_CPU_X64)
#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
((Machine) == EFI_IMAGE_MACHINE_X64)
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_IA32)
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_IA32)
-#elif defined (MDE_CPU_ARM)
+ #elif defined (MDE_CPU_ARM)
-#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_ARMTHUMB_MIXED)
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_ARMTHUMB_MIXED)
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
-#elif defined (MDE_CPU_AARCH64)
+ #elif defined (MDE_CPU_AARCH64)
#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
((Machine) == EFI_IMAGE_MACHINE_AARCH64)
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
-#elif defined (MDE_CPU_RISCV64)
+ #elif defined (MDE_CPU_RISCV64)
#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
((Machine) == EFI_IMAGE_MACHINE_RISCV64)
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
-#elif defined (MDE_CPU_EBC)
+ #elif defined (MDE_CPU_LOONGARCH64)
+
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
+ ((Machine) == EFI_IMAGE_MACHINE_LOONGARCH64)
+
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
+
+ #elif defined (MDE_CPU_EBC)
///
/// This is just to make sure you can cross compile with the EBC compiler.
/// It does not make sense to have a PE loader coded in EBC.
///
-#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_EBC)
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_EBC)
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
+ #else
+ #error Unknown Processor Type
+ #endif
#else
-#error Unknown Processor Type
-#endif
-#else
-#if defined (EFI_IMAGE_MACHINE_TYPE_VALUE)
-#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_TYPE_VALUE)
-#else
-#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) (FALSE)
-#endif
-#if defined (EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE)
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE)
-#else
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
-#endif
+ #if defined (EFI_IMAGE_MACHINE_TYPE_VALUE)
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_TYPE_VALUE)
+ #else
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) (FALSE)
+ #endif
+ #if defined (EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE)
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE)
+ #else
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
+ #endif
#endif
#endif
diff --git a/MdePkg/Include/Uefi/UefiGpt.h b/MdePkg/Include/Uefi/UefiGpt.h
index af055613..70e03e76 100644
--- a/MdePkg/Include/Uefi/UefiGpt.h
+++ b/MdePkg/Include/Uefi/UefiGpt.h
@@ -13,15 +13,15 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
/// The primary GUID Partition Table Header must be
/// located in LBA 1 (i.e., the second logical block).
///
-#define PRIMARY_PART_HEADER_LBA 1
+#define PRIMARY_PART_HEADER_LBA 1
///
/// EFI Partition Table Signature: "EFI PART".
///
-#define EFI_PTAB_HEADER_ID SIGNATURE_64 ('E','F','I',' ','P','A','R','T')
+#define EFI_PTAB_HEADER_ID SIGNATURE_64 ('E','F','I',' ','P','A','R','T')
///
/// Minimum bytes reserve for EFI entry array buffer.
///
-#define EFI_GPT_PART_ENTRY_MIN_SIZE 16384
+#define EFI_GPT_PART_ENTRY_MIN_SIZE 16384
#pragma pack(1)
@@ -33,51 +33,51 @@ typedef struct {
/// The table header for the GPT partition Table.
/// This header contains EFI_PTAB_HEADER_ID.
///
- EFI_TABLE_HEADER Header;
+ EFI_TABLE_HEADER Header;
///
/// The LBA that contains this data structure.
///
- EFI_LBA MyLBA;
+ EFI_LBA MyLBA;
///
/// LBA address of the alternate GUID Partition Table Header.
///
- EFI_LBA AlternateLBA;
+ EFI_LBA AlternateLBA;
///
/// The first usable logical block that may be used
/// by a partition described by a GUID Partition Entry.
///
- EFI_LBA FirstUsableLBA;
+ EFI_LBA FirstUsableLBA;
///
/// The last usable logical block that may be used
/// by a partition described by a GUID Partition Entry.
///
- EFI_LBA LastUsableLBA;
+ EFI_LBA LastUsableLBA;
///
/// GUID that can be used to uniquely identify the disk.
///
- EFI_GUID DiskGUID;
+ EFI_GUID DiskGUID;
///
/// The starting LBA of the GUID Partition Entry array.
///
- EFI_LBA PartitionEntryLBA;
+ EFI_LBA PartitionEntryLBA;
///
/// The number of Partition Entries in the GUID Partition Entry array.
///
- UINT32 NumberOfPartitionEntries;
+ UINT32 NumberOfPartitionEntries;
///
/// The size, in bytes, of each the GUID Partition
/// Entry structures in the GUID Partition Entry
/// array. This field shall be set to a value of 128 x 2^n where n is
/// an integer greater than or equal to zero (e.g., 128, 256, 512, etc.).
///
- UINT32 SizeOfPartitionEntry;
+ UINT32 SizeOfPartitionEntry;
///
/// The CRC32 of the GUID Partition Entry array.
/// Starts at PartitionEntryLBA and is
/// computed over a byte length of
/// NumberOfPartitionEntries * SizeOfPartitionEntry.
///
- UINT32 PartitionEntryArrayCRC32;
+ UINT32 PartitionEntryArrayCRC32;
} EFI_PARTITION_TABLE_HEADER;
///
@@ -88,21 +88,21 @@ typedef struct {
/// Unique ID that defines the purpose and type of this Partition. A value of
/// zero defines that this partition entry is not being used.
///
- EFI_GUID PartitionTypeGUID;
+ EFI_GUID PartitionTypeGUID;
///
/// GUID that is unique for every partition entry. Every partition ever
/// created will have a unique GUID.
/// This GUID must be assigned when the GUID Partition Entry is created.
///
- EFI_GUID UniquePartitionGUID;
+ EFI_GUID UniquePartitionGUID;
///
/// Starting LBA of the partition defined by this entry
///
- EFI_LBA StartingLBA;
+ EFI_LBA StartingLBA;
///
/// Ending LBA of the partition defined by this entry.
///
- EFI_LBA EndingLBA;
+ EFI_LBA EndingLBA;
///
/// Attribute bits, all bits reserved by UEFI
/// Bit 0: If this bit is set, the partition is required for the platform to function. The owner/creator of the
@@ -135,5 +135,3 @@ typedef struct {
#pragma pack()
#endif
-
-
diff --git a/MdePkg/Include/Uefi/UefiMultiPhase.h b/MdePkg/Include/Uefi/UefiMultiPhase.h
index dd97e4e3..21a541fc 100644
--- a/MdePkg/Include/Uefi/UefiMultiPhase.h
+++ b/MdePkg/Include/Uefi/UefiMultiPhase.h
@@ -12,26 +12,26 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
///
/// Attributes of variable.
///
-#define EFI_VARIABLE_NON_VOLATILE 0x00000001
-#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x00000002
-#define EFI_VARIABLE_RUNTIME_ACCESS 0x00000004
+#define EFI_VARIABLE_NON_VOLATILE 0x00000001
+#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x00000002
+#define EFI_VARIABLE_RUNTIME_ACCESS 0x00000004
///
/// This attribute is identified by the mnemonic 'HR'
/// elsewhere in this specification.
///
-#define EFI_VARIABLE_HARDWARE_ERROR_RECORD 0x00000008
+#define EFI_VARIABLE_HARDWARE_ERROR_RECORD 0x00000008
///
/// Attributes of Authenticated Variable
///
-#define EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS 0x00000020
-#define EFI_VARIABLE_APPEND_WRITE 0x00000040
+#define EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS 0x00000020
+#define EFI_VARIABLE_APPEND_WRITE 0x00000040
///
/// NOTE: EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS is deprecated and should be considered reserved.
///
-#define EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS 0x00000010
+#define EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS 0x00000010
#ifndef VFRCOMPILE
-#include
+ #include
///
/// Enumeration of memory types introduced in UEFI.
///
@@ -103,6 +103,11 @@ typedef enum {
/// however it happens to also support byte-addressable non-volatility.
///
EfiPersistentMemory,
+ ///
+ /// A memory region that describes system memory that has not been accepted
+ /// by a corresponding call to the underlying isolation architecture.
+ ///
+ EfiUnacceptedMemoryType,
EfiMaxMemoryType
} EFI_MEMORY_TYPE;
@@ -148,27 +153,27 @@ typedef struct {
/// Unique signatures have been generated for the EFI System Table,
/// the EFI Boot Services Table, and the EFI Runtime Services Table.
///
- UINT64 Signature;
+ UINT64 Signature;
///
/// The revision of the EFI Specification to which this table
/// conforms. The upper 16 bits of this field contain the major
/// revision value, and the lower 16 bits contain the minor revision
/// value. The minor revision values are limited to the range of 00..99.
///
- UINT32 Revision;
+ UINT32 Revision;
///
/// The size, in bytes, of the entire table including the EFI_TABLE_HEADER.
///
- UINT32 HeaderSize;
+ UINT32 HeaderSize;
///
/// The 32-bit CRC for the entire table. This value is computed by
/// setting this field to 0, and computing the 32-bit CRC for HeaderSize bytes.
///
- UINT32 CRC32;
+ UINT32 CRC32;
///
/// Reserved field that must be set to 0.
///
- UINT32 Reserved;
+ UINT32 Reserved;
} EFI_TABLE_HEADER;
///
@@ -193,7 +198,7 @@ typedef struct {
/// replay. Incremented during each
/// "Write" access.
///
- UINT64 MonotonicCount;
+ UINT64 MonotonicCount;
///
/// Provides the authorization for the variable
/// access. It is a signature across the
@@ -202,7 +207,7 @@ typedef struct {
/// associated with a public key that has been
/// provisioned via the key exchange.
///
- WIN_CERTIFICATE_UEFI_GUID AuthInfo;
+ WIN_CERTIFICATE_UEFI_GUID AuthInfo;
} EFI_VARIABLE_AUTHENTICATION;
///
@@ -218,12 +223,12 @@ typedef struct {
/// For the TimeStamp value, components Pad1, Nanosecond, TimeZone, Daylight and
/// Pad2 shall be set to 0. This means that the time shall always be expressed in GMT.
///
- EFI_TIME TimeStamp;
+ EFI_TIME TimeStamp;
///
/// Only a CertType of EFI_CERT_TYPE_PKCS7_GUID is accepted.
///
- WIN_CERTIFICATE_UEFI_GUID AuthInfo;
- } EFI_VARIABLE_AUTHENTICATION_2;
+ WIN_CERTIFICATE_UEFI_GUID AuthInfo;
+} EFI_VARIABLE_AUTHENTICATION_2;
#endif // VFRCOMPILE
#endif
diff --git a/MdePkg/Include/Uefi/UefiSpec.h b/MdePkg/Include/Uefi/UefiSpec.h
index d34cc15c..2365b299 100644
--- a/MdePkg/Include/Uefi/UefiSpec.h
+++ b/MdePkg/Include/Uefi/UefiSpec.h
@@ -27,11 +27,11 @@ typedef struct {
///
/// The 128-bit GUID value that uniquely identifies the system configuration table.
///
- EFI_GUID VendorGuid;
+ EFI_GUID VendorGuid;
///
/// A pointer to the table associated with VendorGuid.
///
- VOID *VendorTable;
+ VOID *VendorTable;
} EFI_CONFIGURATION_TABLE;
#include
diff --git a/MdePkg/Include/X64/Nasm.inc b/MdePkg/Include/X64/Nasm.inc
index 51dc5341..4fa18453 100644
--- a/MdePkg/Include/X64/Nasm.inc
+++ b/MdePkg/Include/X64/Nasm.inc
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
+; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
@@ -9,30 +9,6 @@
;
;------------------------------------------------------------------------------
-%macro SAVEPREVSSP 0
- DB 0xF3, 0x0F, 0x01, 0xEA
-%endmacro
-
-%macro CLRSSBSY_RAX 0
- DB 0xF3, 0x0F, 0xAE, 0x30
-%endmacro
-
-%macro RSTORSSP_RAX 0
- DB 0xF3, 0x0F, 0x01, 0x28
-%endmacro
-
-%macro SETSSBSY 0
- DB 0xF3, 0x0F, 0x01, 0xE8
-%endmacro
-
-%macro READSSP_RAX 0
- DB 0xF3, 0x48, 0x0F, 0x1E, 0xC8
-%endmacro
-
-%macro INCSSP_RAX 0
- DB 0xF3, 0x48, 0x0F, 0xAE, 0xE8
-%endmacro
-
;
; Macro for the PVALIDATE instruction, defined in AMD APM volume 3.
; NASM feature request URL: https://bugzilla.nasm.us/show_bug.cgi?id=3392753
diff --git a/MdePkg/Include/X64/ProcessorBind.h b/MdePkg/Include/X64/ProcessorBind.h
index a1b947c5..25198438 100644
--- a/MdePkg/Include/X64/ProcessorBind.h
+++ b/MdePkg/Include/X64/ProcessorBind.h
@@ -17,53 +17,38 @@
//
// Make sure we are using the correct packing rules per EFI specification
//
-#if !defined(__GNUC__)
-#pragma pack()
+#if !defined (__GNUC__)
+ #pragma pack()
#endif
-#if defined(__GNUC__) && defined(__pic__) && !defined(USING_LTO) && !defined(__APPLE__)
-//
-// Mark all symbol declarations and references as hidden, meaning they will
-// not be subject to symbol preemption. This allows the compiler to refer to
-// symbols directly using relative references rather than via the GOT, which
-// contains absolute symbol addresses that are subject to runtime relocation.
-//
-// The LTO linker will not emit GOT based relocations when all symbol
-// references can be resolved locally, and so there is no need to set the
-// pragma in that case (and doing so will cause other issues).
-//
-#pragma GCC visibility push (hidden)
-#endif
-
-#if defined(__INTEL_COMPILER)
+#if defined (__INTEL_COMPILER)
//
// Disable ICC's remark #869: "Parameter" was never referenced warning.
// This is legal ANSI C code so we disable the remark that is turned on with -Wall
//
-#pragma warning ( disable : 869 )
+ #pragma warning ( disable : 869 )
//
// Disable ICC's remark #1418: external function definition with no prior declaration.
// This is legal ANSI C code so we disable the remark that is turned on with /W4
//
-#pragma warning ( disable : 1418 )
+ #pragma warning ( disable : 1418 )
//
// Disable ICC's remark #1419: external declaration in primary source file
// This is legal ANSI C code so we disable the remark that is turned on with /W4
//
-#pragma warning ( disable : 1419 )
+ #pragma warning ( disable : 1419 )
//
// Disable ICC's remark #593: "Variable" was set but never used.
// This is legal ANSI C code so we disable the remark that is turned on with /W4
//
-#pragma warning ( disable : 593 )
+ #pragma warning ( disable : 593 )
#endif
-
-#if defined(_MSC_EXTENSIONS)
+#if defined (_MSC_EXTENSIONS)
//
// Disable warning that make it impossible to compile at /W4
@@ -73,168 +58,162 @@
//
// Disabling bitfield type checking warnings.
//
-#pragma warning ( disable : 4214 )
+ #pragma warning ( disable : 4214 )
//
// Disabling the unreferenced formal parameter warnings.
//
-#pragma warning ( disable : 4100 )
+ #pragma warning ( disable : 4100 )
//
// Disable slightly different base types warning as CHAR8 * can not be set
// to a constant string.
//
-#pragma warning ( disable : 4057 )
+ #pragma warning ( disable : 4057 )
//
// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning
//
-#pragma warning ( disable : 4127 )
+ #pragma warning ( disable : 4127 )
//
// This warning is caused by functions defined but not used. For precompiled header only.
//
-#pragma warning ( disable : 4505 )
+ #pragma warning ( disable : 4505 )
//
// This warning is caused by empty (after preprocessing) source file. For precompiled header only.
//
-#pragma warning ( disable : 4206 )
+ #pragma warning ( disable : 4206 )
-#if defined(_MSC_VER) && _MSC_VER >= 1800
-
-//
-// Disable these warnings for VS2013.
-//
+ #if defined (_MSC_VER) && _MSC_VER >= 1800
//
// This warning is for potentially uninitialized local variable, and it may cause false
-// positive issues in VS2013 and VS2015 build
+// positive issues in VS2015 build
//
-#pragma warning ( disable : 4701 )
+ #pragma warning ( disable : 4701 )
//
// This warning is for potentially uninitialized local pointer variable, and it may cause
-// false positive issues in VS2013 and VS2015 build
+// false positive issues in VS2015 build
//
-#pragma warning ( disable : 4703 )
+ #pragma warning ( disable : 4703 )
+
+ #endif
#endif
-#endif
+#if defined (_MSC_EXTENSIONS)
+//
+// use Microsoft C compiler dependent integer width types
+//
-
-#if defined(_MSC_EXTENSIONS)
- //
- // use Microsoft C compiler dependent integer width types
- //
-
- ///
- /// 8-byte unsigned value
- ///
- typedef unsigned __int64 UINT64;
- ///
- /// 8-byte signed value
- ///
- typedef __int64 INT64;
- ///
- /// 4-byte unsigned value
- ///
- typedef unsigned __int32 UINT32;
- ///
- /// 4-byte signed value
- ///
- typedef __int32 INT32;
- ///
- /// 2-byte unsigned value
- ///
- typedef unsigned short UINT16;
- ///
- /// 2-byte Character. Unless otherwise specified all strings are stored in the
- /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
- ///
- typedef unsigned short CHAR16;
- ///
- /// 2-byte signed value
- ///
- typedef short INT16;
- ///
- /// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
- /// values are undefined.
- ///
- typedef unsigned char BOOLEAN;
- ///
- /// 1-byte unsigned value
- ///
- typedef unsigned char UINT8;
- ///
- /// 1-byte Character
- ///
- typedef char CHAR8;
- ///
- /// 1-byte signed value
- ///
- typedef signed char INT8;
+///
+/// 8-byte unsigned value
+///
+typedef unsigned __int64 UINT64;
+///
+/// 8-byte signed value
+///
+typedef __int64 INT64;
+///
+/// 4-byte unsigned value
+///
+typedef unsigned __int32 UINT32;
+///
+/// 4-byte signed value
+///
+typedef __int32 INT32;
+///
+/// 2-byte unsigned value
+///
+typedef unsigned short UINT16;
+///
+/// 2-byte Character. Unless otherwise specified all strings are stored in the
+/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
+///
+typedef unsigned short CHAR16;
+///
+/// 2-byte signed value
+///
+typedef short INT16;
+///
+/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
+/// values are undefined.
+///
+typedef unsigned char BOOLEAN;
+///
+/// 1-byte unsigned value
+///
+typedef unsigned char UINT8;
+///
+/// 1-byte Character
+///
+typedef char CHAR8;
+///
+/// 1-byte signed value
+///
+typedef signed char INT8;
#else
- ///
- /// 8-byte unsigned value
- ///
- typedef unsigned long long UINT64;
- ///
- /// 8-byte signed value
- ///
- typedef long long INT64;
- ///
- /// 4-byte unsigned value
- ///
- typedef unsigned int UINT32;
- ///
- /// 4-byte signed value
- ///
- typedef int INT32;
- ///
- /// 2-byte unsigned value
- ///
- typedef unsigned short UINT16;
- ///
- /// 2-byte Character. Unless otherwise specified all strings are stored in the
- /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
- ///
- typedef unsigned short CHAR16;
- ///
- /// 2-byte signed value
- ///
- typedef short INT16;
- ///
- /// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
- /// values are undefined.
- ///
- typedef unsigned char BOOLEAN;
- ///
- /// 1-byte unsigned value
- ///
- typedef unsigned char UINT8;
- ///
- /// 1-byte Character
- ///
- typedef char CHAR8;
- ///
- /// 1-byte signed value
- ///
- typedef signed char INT8;
+///
+/// 8-byte unsigned value
+///
+typedef unsigned long long UINT64;
+///
+/// 8-byte signed value
+///
+typedef long long INT64;
+///
+/// 4-byte unsigned value
+///
+typedef unsigned int UINT32;
+///
+/// 4-byte signed value
+///
+typedef int INT32;
+///
+/// 2-byte unsigned value
+///
+typedef unsigned short UINT16;
+///
+/// 2-byte Character. Unless otherwise specified all strings are stored in the
+/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
+///
+typedef unsigned short CHAR16;
+///
+/// 2-byte signed value
+///
+typedef short INT16;
+///
+/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
+/// values are undefined.
+///
+typedef unsigned char BOOLEAN;
+///
+/// 1-byte unsigned value
+///
+typedef unsigned char UINT8;
+///
+/// 1-byte Character
+///
+typedef char CHAR8;
+///
+/// 1-byte signed value
+///
+typedef signed char INT8;
#endif
///
/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
/// 8 bytes on supported 64-bit processor instructions)
///
-typedef UINT64 UINTN;
+typedef UINT64 UINTN;
///
/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
/// 8 bytes on supported 64-bit processor instructions)
///
-typedef INT64 INTN;
-
+typedef INT64 INTN;
//
// Processor specific defines
@@ -243,7 +222,7 @@ typedef INT64 INTN;
///
/// A value of native width with the highest bit set.
///
-#define MAX_BIT 0x8000000000000000ULL
+#define MAX_BIT 0x8000000000000000ULL
///
/// A value of native width with the two highest bits set.
///
@@ -252,12 +231,12 @@ typedef INT64 INTN;
///
/// Maximum legal x64 address
///
-#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL
+#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL
///
/// Maximum usable address at boot time
///
-#define MAX_ALLOC_ADDRESS MAX_ADDRESS
+#define MAX_ALLOC_ADDRESS MAX_ADDRESS
///
/// Maximum legal x64 INTN and UINTN values.
@@ -268,18 +247,18 @@ typedef INT64 INTN;
///
/// Minimum legal x64 INTN value.
///
-#define MIN_INTN (((INTN)-9223372036854775807LL) - 1)
+#define MIN_INTN (((INTN)-9223372036854775807LL) - 1)
///
/// The stack alignment required for x64
///
-#define CPU_STACK_ALIGNMENT 16
+#define CPU_STACK_ALIGNMENT 16
///
/// Page allocation granularity for x64
///
-#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
-#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)
+#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
+#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)
//
// Modifier to ensure that all protocol member functions and EFI intrinsics
@@ -287,38 +266,38 @@ typedef INT64 INTN;
// EFI intrinsics are required to modify their member functions with EFIAPI.
//
#ifdef EFIAPI
- ///
- /// If EFIAPI is already defined, then we use that definition.
- ///
-#elif defined(_MSC_EXTENSIONS)
- ///
- /// Microsoft* compiler specific method for EFIAPI calling convention.
- ///
- #define EFIAPI __cdecl
-#elif defined(__GNUC__)
- ///
- /// Define the standard calling convention regardless of optimization level.
- /// The GCC support assumes a GCC compiler that supports the EFI ABI. The EFI
- /// ABI is much closer to the x64 Microsoft* ABI than standard x64 (x86-64)
- /// GCC ABI. Thus a standard x64 (x86-64) GCC compiler can not be used for
- /// x64. Warning the assembly code in the MDE x64 does not follow the correct
- /// ABI for the standard x64 (x86-64) GCC.
- ///
- #define EFIAPI
+///
+/// If EFIAPI is already defined, then we use that definition.
+///
+#elif defined (_MSC_EXTENSIONS)
+///
+/// Microsoft* compiler specific method for EFIAPI calling convention.
+///
+#define EFIAPI __cdecl
+#elif defined (__GNUC__)
+///
+/// Define the standard calling convention regardless of optimization level.
+/// The GCC support assumes a GCC compiler that supports the EFI ABI. The EFI
+/// ABI is much closer to the x64 Microsoft* ABI than standard x64 (x86-64)
+/// GCC ABI. Thus a standard x64 (x86-64) GCC compiler can not be used for
+/// x64. Warning the assembly code in the MDE x64 does not follow the correct
+/// ABI for the standard x64 (x86-64) GCC.
+///
+#define EFIAPI
#else
- ///
- /// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI
- /// is the standard.
- ///
- #define EFIAPI
+///
+/// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI
+/// is the standard.
+///
+#define EFIAPI
#endif
-#if defined(__GNUC__) || defined(__clang__)
- ///
- /// For GNU assembly code, .global or .globl can declare global symbols.
- /// Define this macro to unify the usage.
- ///
- #define ASM_GLOBAL .globl
+#if defined (__GNUC__) || defined (__clang__)
+///
+/// For GNU assembly code, .global or .globl can declare global symbols.
+/// Define this macro to unify the usage.
+///
+#define ASM_GLOBAL .globl
#endif
/**
@@ -331,11 +310,10 @@ typedef INT64 INTN;
@return The pointer to the first instruction of a function given a function pointer.
**/
-#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
+#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
#ifndef __USER_LABEL_PREFIX__
#define __USER_LABEL_PREFIX__
#endif
#endif
-
diff --git a/MdePkg/Library/BaseDebugLibNull/DebugLib.c b/MdePkg/Library/BaseDebugLibNull/DebugLib.c
index f6b8faf5..c1b3438a 100644
--- a/MdePkg/Library/BaseDebugLibNull/DebugLib.c
+++ b/MdePkg/Library/BaseDebugLibNull/DebugLib.c
@@ -34,7 +34,6 @@ DebugPrint (
{
}
-
/**
Prints a debug message to the debug output device if the specified
error level is enabled.
@@ -53,14 +52,13 @@ DebugPrint (
VOID
EFIAPI
DebugVPrint (
- IN UINTN ErrorLevel,
- IN CONST CHAR8 *Format,
- IN VA_LIST VaListMarker
+ IN UINTN ErrorLevel,
+ IN CONST CHAR8 *Format,
+ IN VA_LIST VaListMarker
)
{
}
-
/**
Prints a debug message to the debug output device if the specified
error level is enabled.
@@ -81,14 +79,13 @@ DebugVPrint (
VOID
EFIAPI
DebugBPrint (
- IN UINTN ErrorLevel,
- IN CONST CHAR8 *Format,
- IN BASE_LIST BaseListMarker
+ IN UINTN ErrorLevel,
+ IN CONST CHAR8 *Format,
+ IN BASE_LIST BaseListMarker
)
{
}
-
/**
Prints an assert message containing a filename, line number, and description.
This may be followed by a breakpoint or a dead loop.
@@ -120,7 +117,6 @@ DebugAssert (
{
}
-
/**
Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.
@@ -146,7 +142,6 @@ DebugClearMemory (
return Buffer;
}
-
/**
Returns TRUE if ASSERT() macros are enabled.
@@ -166,7 +161,6 @@ DebugAssertEnabled (
return FALSE;
}
-
/**
Returns TRUE if DEBUG() macros are enabled.
@@ -186,7 +180,6 @@ DebugPrintEnabled (
return FALSE;
}
-
/**
Returns TRUE if DEBUG_CODE() macros are enabled.
@@ -206,7 +199,6 @@ DebugCodeEnabled (
return FALSE;
}
-
/**
Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.
@@ -238,9 +230,8 @@ DebugClearMemoryEnabled (
BOOLEAN
EFIAPI
DebugPrintLevelEnabled (
- IN CONST UINTN ErrorLevel
+ IN CONST UINTN ErrorLevel
)
{
return FALSE;
}
-
diff --git a/MdePkg/Library/BaseDebugLibSerialPort/DebugLib.c b/MdePkg/Library/BaseDebugLibSerialPort/DebugLib.c
index a4fe34d4..e659a7d2 100644
--- a/MdePkg/Library/BaseDebugLibSerialPort/DebugLib.c
+++ b/MdePkg/Library/BaseDebugLibSerialPort/DebugLib.c
@@ -30,7 +30,7 @@
// VA_LIST can not initialize to NULL for all compiler, so we use this to
// indicate a null VA_LIST
//
-VA_LIST mVaListNull;
+VA_LIST mVaListNull;
/**
The constructor function initialize the Serial Port Library
@@ -77,7 +77,6 @@ DebugPrint (
VA_END (Marker);
}
-
/**
Prints a debug message to the debug output device if the specified
error level is enabled base on Null-terminated format string and a
@@ -97,13 +96,13 @@ DebugPrint (
**/
VOID
DebugPrintMarker (
- IN UINTN ErrorLevel,
- IN CONST CHAR8 *Format,
- IN VA_LIST VaListMarker,
- IN BASE_LIST BaseListMarker
+ IN UINTN ErrorLevel,
+ IN CONST CHAR8 *Format,
+ IN VA_LIST VaListMarker,
+ IN BASE_LIST BaseListMarker
)
{
- CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];
+ CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];
//
// If Format is NULL, then ASSERT().
@@ -132,7 +131,6 @@ DebugPrintMarker (
SerialPortWrite ((UINT8 *)Buffer, AsciiStrLen (Buffer));
}
-
/**
Prints a debug message to the debug output device if the specified
error level is enabled.
@@ -151,15 +149,14 @@ DebugPrintMarker (
VOID
EFIAPI
DebugVPrint (
- IN UINTN ErrorLevel,
- IN CONST CHAR8 *Format,
- IN VA_LIST VaListMarker
+ IN UINTN ErrorLevel,
+ IN CONST CHAR8 *Format,
+ IN VA_LIST VaListMarker
)
{
DebugPrintMarker (ErrorLevel, Format, VaListMarker, NULL);
}
-
/**
Prints a debug message to the debug output device if the specified
error level is enabled.
@@ -180,15 +177,14 @@ DebugVPrint (
VOID
EFIAPI
DebugBPrint (
- IN UINTN ErrorLevel,
- IN CONST CHAR8 *Format,
- IN BASE_LIST BaseListMarker
+ IN UINTN ErrorLevel,
+ IN CONST CHAR8 *Format,
+ IN BASE_LIST BaseListMarker
)
{
DebugPrintMarker (ErrorLevel, Format, mVaListNull, BaseListMarker);
}
-
/**
Prints an assert message containing a filename, line number, and description.
This may be followed by a breakpoint or a dead loop.
@@ -233,14 +229,13 @@ DebugAssert (
//
// Generate a Breakpoint, DeadLoop, or NOP based on PCD settings
//
- if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED) != 0) {
+ if ((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED) != 0) {
CpuBreakpoint ();
- } else if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED) != 0) {
+ } else if ((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED) != 0) {
CpuDeadLoop ();
}
}
-
/**
Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.
@@ -271,10 +266,9 @@ DebugClearMemory (
//
// SetMem() checks for the the ASSERT() condition on Length and returns Buffer
//
- return SetMem (Buffer, Length, PcdGet8(PcdDebugClearMemoryValue));
+ return SetMem (Buffer, Length, PcdGet8 (PcdDebugClearMemoryValue));
}
-
/**
Returns TRUE if ASSERT() macros are enabled.
@@ -291,10 +285,9 @@ DebugAssertEnabled (
VOID
)
{
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);
}
-
/**
Returns TRUE if DEBUG() macros are enabled.
@@ -311,10 +304,9 @@ DebugPrintEnabled (
VOID
)
{
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);
}
-
/**
Returns TRUE if DEBUG_CODE() macros are enabled.
@@ -331,10 +323,9 @@ DebugCodeEnabled (
VOID
)
{
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);
}
-
/**
Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.
@@ -351,7 +342,7 @@ DebugClearMemoryEnabled (
VOID
)
{
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);
}
/**
@@ -366,9 +357,8 @@ DebugClearMemoryEnabled (
BOOLEAN
EFIAPI
DebugPrintLevelEnabled (
- IN CONST UINTN ErrorLevel
+ IN CONST UINTN ErrorLevel
)
{
- return (BOOLEAN) ((ErrorLevel & PcdGet32(PcdFixedDebugPrintErrorLevel)) != 0);
+ return (BOOLEAN)((ErrorLevel & PcdGet32 (PcdFixedDebugPrintErrorLevel)) != 0);
}
-
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
index 33d2672e..42795f2e 100755
--- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
@@ -4,13 +4,14 @@
# I/O Library that uses compiler intrinsics to perform IN and OUT instructions
# for IA-32 and x64. On IPF, I/O port requests are translated into MMIO requests.
# MMIO requests are forwarded directly to memory. For EBC, I/O port requests
-# ASSERT(). For ARM, AARCH64 and RISCV64, this I/O library only provides non I/O
-# read and write.
+# ASSERT(). For ARM, AARCH64, RISCV64 and LoongArch, this I/O library only provides
+# non I/O read and write.
#
# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Copyright (c) 2017, AMD Incorporated. All rights reserved.
# Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+# Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -27,13 +28,15 @@
#
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARCH64
#
[Sources]
IoLibMmioBuffer.c
BaseIoLibIntrinsicInternal.h
IoHighLevel.c
+ IoLibInternalTdxNull.c
+ IoLibTdx.h
[Sources.IA32]
IoLibGcc.c | GCC
@@ -60,6 +63,9 @@
[Sources.RISCV64]
IoLibNoIo.c
+[Sources.LOONGARCH64]
+ IoLibNoIo.c
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicInternal.h b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicInternal.h
index 8b10be6f..df34ee49 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicInternal.h
+++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicInternal.h
@@ -10,8 +10,6 @@
#ifndef __BASEIOLIB_INTRINSIC_INTERNAL_H_
#define __BASEIOLIB_INTRINSIC_INTERNAL_H_
-
-
#include
#include
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf
new file mode 100644
index 00000000..a2f0a4c3
--- /dev/null
+++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf
@@ -0,0 +1,61 @@
+## @file
+# Instance of I/O Library using compiler intrinsics.
+#
+# I/O Library that uses compiler intrinsics to perform IN and OUT instructions
+# for IA-32 and x64.
+#
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseIoLibIntrinsicSev
+ MODULE_UNI_FILE = BaseIoLibIntrinsic.uni
+ FILE_GUID = 93742f95-6e71-4581-b600-8e1da443f95a
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = IoLib
+
+
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources]
+ IoLibMmioBuffer.c
+ BaseIoLibIntrinsicInternal.h
+ IoHighLevel.c
+ IoLibTdx.h
+ IoLibSev.h
+
+[Sources.IA32]
+ IoLibGcc.c | GCC
+ IoLibMsc.c | MSFT
+ IoLib.c
+ IoLibInternalTdxNull.c
+ Ia32/IoFifoSev.nasm
+
+[Sources.X64]
+ IoLibGcc.c | GCC
+ IoLibMsc.c | MSFT
+ IoLib.c
+ IoLibInternalTdx.c
+ IoLibFifo.c
+ X64/IoFifoSev.nasm
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ DebugLib
+ BaseLib
+ RegisterFilterLib
+ CcProbeLib
+
+[LibraryClasses.X64]
+ TdxLib
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Ia32/IoFifoSev.nasm b/MdePkg/Library/BaseIoLibIntrinsic/Ia32/IoFifoSev.nasm
new file mode 100644
index 00000000..3a7a25bb
--- /dev/null
+++ b/MdePkg/Library/BaseIoLibIntrinsic/Ia32/IoFifoSev.nasm
@@ -0,0 +1,293 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; Check whether we need to unroll the String I/O under SEV guest
+;
+; Return // eax (1 - unroll, 0 - no unroll)
+;------------------------------------------------------------------------------
+global ASM_PFX(SevNoRepIo)
+ASM_PFX(SevNoRepIo):
+
+ ; CPUID clobbers ebx, ecx and edx
+ push ebx
+ push ecx
+ push edx
+
+ ; Check if we are running under hypervisor
+ ; CPUID(1).ECX Bit 31
+ mov eax, 1
+ cpuid
+ bt ecx, 31
+ jnc @UseRepIo
+
+ ; Check if we have Memory encryption CPUID leaf
+ mov eax, 0x80000000
+ cpuid
+ cmp eax, 0x8000001f
+ jl @UseRepIo
+
+ ; Check for memory encryption feature:
+ ; CPUID Fn8000_001F[EAX] - Bit 1
+ ;
+ mov eax, 0x8000001f
+ cpuid
+ bt eax, 1
+ jnc @UseRepIo
+
+ ; Check if memory encryption is enabled
+ ; MSR_0xC0010131 - Bit 0 (SEV enabled)
+ ; MSR_0xC0010131 - Bit 1 (SEV-ES enabled)
+ mov ecx, 0xc0010131
+ rdmsr
+
+ ; Check for (SevEsEnabled == 0 && SevEnabled == 1)
+ and eax, 3
+ cmp eax, 1
+ je @SevNoRepIo_Done
+
+@UseRepIo:
+ xor eax, eax
+
+@SevNoRepIo_Done:
+ pop edx
+ pop ecx
+ pop ebx
+ ret
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; IoReadFifo8 (
+; IN UINTN Port,
+; IN UINTN Size,
+; OUT VOID *Buffer
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(IoReadFifo8)
+ASM_PFX(IoReadFifo8):
+ push edi
+ mov dx, [esp + 8]
+ mov ecx, [esp + 12]
+ mov edi, [esp + 16]
+
+ ; Check if we need to unroll String I/O
+ call ASM_PFX(SevNoRepIo)
+ test eax, eax
+ jnz @IoReadFifo8_NoRep
+
+ cld
+ rep insb
+ jmp @IoReadFifo8_Done
+
+@IoReadFifo8_NoRep:
+ jecxz @IoReadFifo8_Done
+
+@IoReadFifo8_Loop:
+ in al, dx
+ mov byte [edi], al
+ inc edi
+ loop @IoReadFifo8_Loop
+
+@IoReadFifo8_Done:
+ pop edi
+ ret
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; IoReadFifo16 (
+; IN UINTN Port,
+; IN UINTN Size,
+; OUT VOID *Buffer
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(IoReadFifo16)
+ASM_PFX(IoReadFifo16):
+ push edi
+ mov dx, [esp + 8]
+ mov ecx, [esp + 12]
+ mov edi, [esp + 16]
+
+ ; Check if we need to unroll String I/O
+ call ASM_PFX(SevNoRepIo)
+ test eax, eax
+ jnz @IoReadFifo16_NoRep
+
+ cld
+ rep insw
+ jmp @IoReadFifo16_Done
+
+@IoReadFifo16_NoRep:
+ jecxz @IoReadFifo16_Done
+
+@IoReadFifo16_Loop:
+ in ax, dx
+ mov word [edi], ax
+ add edi, 2
+ loop @IoReadFifo16_Loop
+
+@IoReadFifo16_Done:
+ pop edi
+ ret
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; IoReadFifo32 (
+; IN UINTN Port,
+; IN UINTN Size,
+; OUT VOID *Buffer
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(IoReadFifo32)
+ASM_PFX(IoReadFifo32):
+ push edi
+ mov dx, [esp + 8]
+ mov ecx, [esp + 12]
+ mov edi, [esp + 16]
+
+ ; Check if we need to unroll String I/O
+ call ASM_PFX(SevNoRepIo)
+ test eax, eax
+ jnz @IoReadFifo32_NoRep
+
+ cld
+ rep insd
+ jmp @IoReadFifo32_Done
+
+@IoReadFifo32_NoRep:
+ jecxz @IoReadFifo32_Done
+
+@IoReadFifo32_Loop:
+ in eax, dx
+ mov dword [edi], eax
+ add edi, 4
+ loop @IoReadFifo32_Loop
+
+@IoReadFifo32_Done:
+ pop edi
+ ret
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; IoWriteFifo8 (
+; IN UINTN Port,
+; IN UINTN Size,
+; IN VOID *Buffer
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(IoWriteFifo8)
+ASM_PFX(IoWriteFifo8):
+ push esi
+ mov dx, [esp + 8]
+ mov ecx, [esp + 12]
+ mov esi, [esp + 16]
+
+ ; Check if we need to unroll String I/O
+ call ASM_PFX(SevNoRepIo)
+ test eax, eax
+ jnz @IoWriteFifo8_NoRep
+
+ cld
+ rep outsb
+ jmp @IoWriteFifo8_Done
+
+@IoWriteFifo8_NoRep:
+ jecxz @IoWriteFifo8_Done
+
+@IoWriteFifo8_Loop:
+ mov al, byte [esi]
+ out dx, al
+ inc esi
+ loop @IoWriteFifo8_Loop
+
+@IoWriteFifo8_Done:
+ pop esi
+ ret
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; IoWriteFifo16 (
+; IN UINTN Port,
+; IN UINTN Size,
+; IN VOID *Buffer
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(IoWriteFifo16)
+ASM_PFX(IoWriteFifo16):
+ push esi
+ mov dx, [esp + 8]
+ mov ecx, [esp + 12]
+ mov esi, [esp + 16]
+
+ ; Check if we need to unroll String I/O
+ call ASM_PFX(SevNoRepIo)
+ test eax, eax
+ jnz @IoWriteFifo16_NoRep
+
+ cld
+ rep outsw
+ jmp @IoWriteFifo16_Done
+
+@IoWriteFifo16_NoRep:
+ jecxz @IoWriteFifo16_Done
+
+@IoWriteFifo16_Loop:
+ mov ax, word [esi]
+ out dx, ax
+ add esi, 2
+ loop @IoWriteFifo16_Loop
+
+@IoWriteFifo16_Done:
+ pop esi
+ ret
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; IoWriteFifo32 (
+; IN UINTN Port,
+; IN UINTN Size,
+; IN VOID *Buffer
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(IoWriteFifo32)
+ASM_PFX(IoWriteFifo32):
+ push esi
+ mov dx, [esp + 8]
+ mov ecx, [esp + 12]
+ mov esi, [esp + 16]
+
+ ; Check if we need to unroll String I/O
+ call ASM_PFX(SevNoRepIo)
+ test eax, eax
+ jnz @IoWriteFifo32_NoRep
+
+ cld
+ rep outsd
+ jmp @IoWriteFifo32_Done
+
+@IoWriteFifo32_NoRep:
+ jecxz @IoWriteFifo32_Done
+
+@IoWriteFifo32_Loop:
+ mov eax, dword [esi]
+ out dx, eax
+ add esi, 4
+ loop @IoWriteFifo32_Loop
+
+@IoWriteFifo32_Done:
+ pop esi
+ ret
+
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoHighLevel.c b/MdePkg/Library/BaseIoLibIntrinsic/IoHighLevel.c
index ff54bf7e..0d8b6914 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/IoHighLevel.c
+++ b/MdePkg/Library/BaseIoLibIntrinsic/IoHighLevel.c
@@ -38,11 +38,11 @@
UINT8
EFIAPI
IoOr8 (
- IN UINTN Port,
- IN UINT8 OrData
+ IN UINTN Port,
+ IN UINT8 OrData
)
{
- return IoWrite8 (Port, (UINT8) (IoRead8 (Port) | OrData));
+ return IoWrite8 (Port, (UINT8)(IoRead8 (Port) | OrData));
}
/**
@@ -66,11 +66,11 @@ IoOr8 (
UINT8
EFIAPI
IoAnd8 (
- IN UINTN Port,
- IN UINT8 AndData
+ IN UINTN Port,
+ IN UINT8 AndData
)
{
- return IoWrite8 (Port, (UINT8) (IoRead8 (Port) & AndData));
+ return IoWrite8 (Port, (UINT8)(IoRead8 (Port) & AndData));
}
/**
@@ -96,12 +96,12 @@ IoAnd8 (
UINT8
EFIAPI
IoAndThenOr8 (
- IN UINTN Port,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINTN Port,
+ IN UINT8 AndData,
+ IN UINT8 OrData
)
{
- return IoWrite8 (Port, (UINT8) ((IoRead8 (Port) & AndData) | OrData));
+ return IoWrite8 (Port, (UINT8)((IoRead8 (Port) & AndData) | OrData));
}
/**
@@ -127,9 +127,9 @@ IoAndThenOr8 (
UINT8
EFIAPI
IoBitFieldRead8 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
return BitFieldRead8 (IoRead8 (Port), StartBit, EndBit);
@@ -161,10 +161,10 @@ IoBitFieldRead8 (
UINT8
EFIAPI
IoBitFieldWrite8 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 Value
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
)
{
return IoWrite8 (
@@ -202,10 +202,10 @@ IoBitFieldWrite8 (
UINT8
EFIAPI
IoBitFieldOr8 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 OrData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
)
{
return IoWrite8 (
@@ -243,10 +243,10 @@ IoBitFieldOr8 (
UINT8
EFIAPI
IoBitFieldAnd8 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
)
{
return IoWrite8 (
@@ -288,11 +288,11 @@ IoBitFieldAnd8 (
UINT8
EFIAPI
IoBitFieldAndThenOr8 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
)
{
return IoWrite8 (
@@ -323,11 +323,11 @@ IoBitFieldAndThenOr8 (
UINT16
EFIAPI
IoOr16 (
- IN UINTN Port,
- IN UINT16 OrData
+ IN UINTN Port,
+ IN UINT16 OrData
)
{
- return IoWrite16 (Port, (UINT16) (IoRead16 (Port) | OrData));
+ return IoWrite16 (Port, (UINT16)(IoRead16 (Port) | OrData));
}
/**
@@ -352,11 +352,11 @@ IoOr16 (
UINT16
EFIAPI
IoAnd16 (
- IN UINTN Port,
- IN UINT16 AndData
+ IN UINTN Port,
+ IN UINT16 AndData
)
{
- return IoWrite16 (Port, (UINT16) (IoRead16 (Port) & AndData));
+ return IoWrite16 (Port, (UINT16)(IoRead16 (Port) & AndData));
}
/**
@@ -383,12 +383,12 @@ IoAnd16 (
UINT16
EFIAPI
IoAndThenOr16 (
- IN UINTN Port,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINTN Port,
+ IN UINT16 AndData,
+ IN UINT16 OrData
)
{
- return IoWrite16 (Port, (UINT16) ((IoRead16 (Port) & AndData) | OrData));
+ return IoWrite16 (Port, (UINT16)((IoRead16 (Port) & AndData) | OrData));
}
/**
@@ -415,9 +415,9 @@ IoAndThenOr16 (
UINT16
EFIAPI
IoBitFieldRead16 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
return BitFieldRead16 (IoRead16 (Port), StartBit, EndBit);
@@ -451,10 +451,10 @@ IoBitFieldRead16 (
UINT16
EFIAPI
IoBitFieldWrite16 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 Value
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
)
{
return IoWrite16 (
@@ -493,10 +493,10 @@ IoBitFieldWrite16 (
UINT16
EFIAPI
IoBitFieldOr16 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 OrData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
)
{
return IoWrite16 (
@@ -535,10 +535,10 @@ IoBitFieldOr16 (
UINT16
EFIAPI
IoBitFieldAnd16 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
)
{
return IoWrite16 (
@@ -581,11 +581,11 @@ IoBitFieldAnd16 (
UINT16
EFIAPI
IoBitFieldAndThenOr16 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
)
{
return IoWrite16 (
@@ -616,8 +616,8 @@ IoBitFieldAndThenOr16 (
UINT32
EFIAPI
IoOr32 (
- IN UINTN Port,
- IN UINT32 OrData
+ IN UINTN Port,
+ IN UINT32 OrData
)
{
return IoWrite32 (Port, IoRead32 (Port) | OrData);
@@ -645,8 +645,8 @@ IoOr32 (
UINT32
EFIAPI
IoAnd32 (
- IN UINTN Port,
- IN UINT32 AndData
+ IN UINTN Port,
+ IN UINT32 AndData
)
{
return IoWrite32 (Port, IoRead32 (Port) & AndData);
@@ -676,9 +676,9 @@ IoAnd32 (
UINT32
EFIAPI
IoAndThenOr32 (
- IN UINTN Port,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINTN Port,
+ IN UINT32 AndData,
+ IN UINT32 OrData
)
{
return IoWrite32 (Port, (IoRead32 (Port) & AndData) | OrData);
@@ -708,9 +708,9 @@ IoAndThenOr32 (
UINT32
EFIAPI
IoBitFieldRead32 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
return BitFieldRead32 (IoRead32 (Port), StartBit, EndBit);
@@ -744,10 +744,10 @@ IoBitFieldRead32 (
UINT32
EFIAPI
IoBitFieldWrite32 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
)
{
return IoWrite32 (
@@ -786,10 +786,10 @@ IoBitFieldWrite32 (
UINT32
EFIAPI
IoBitFieldOr32 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
)
{
return IoWrite32 (
@@ -828,10 +828,10 @@ IoBitFieldOr32 (
UINT32
EFIAPI
IoBitFieldAnd32 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
)
{
return IoWrite32 (
@@ -874,11 +874,11 @@ IoBitFieldAnd32 (
UINT32
EFIAPI
IoBitFieldAndThenOr32 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
)
{
return IoWrite32 (
@@ -909,8 +909,8 @@ IoBitFieldAndThenOr32 (
UINT64
EFIAPI
IoOr64 (
- IN UINTN Port,
- IN UINT64 OrData
+ IN UINTN Port,
+ IN UINT64 OrData
)
{
return IoWrite64 (Port, IoRead64 (Port) | OrData);
@@ -938,8 +938,8 @@ IoOr64 (
UINT64
EFIAPI
IoAnd64 (
- IN UINTN Port,
- IN UINT64 AndData
+ IN UINTN Port,
+ IN UINT64 AndData
)
{
return IoWrite64 (Port, IoRead64 (Port) & AndData);
@@ -969,9 +969,9 @@ IoAnd64 (
UINT64
EFIAPI
IoAndThenOr64 (
- IN UINTN Port,
- IN UINT64 AndData,
- IN UINT64 OrData
+ IN UINTN Port,
+ IN UINT64 AndData,
+ IN UINT64 OrData
)
{
return IoWrite64 (Port, (IoRead64 (Port) & AndData) | OrData);
@@ -1001,9 +1001,9 @@ IoAndThenOr64 (
UINT64
EFIAPI
IoBitFieldRead64 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
return BitFieldRead64 (IoRead64 (Port), StartBit, EndBit);
@@ -1037,10 +1037,10 @@ IoBitFieldRead64 (
UINT64
EFIAPI
IoBitFieldWrite64 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 Value
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 Value
)
{
return IoWrite64 (
@@ -1079,10 +1079,10 @@ IoBitFieldWrite64 (
UINT64
EFIAPI
IoBitFieldOr64 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 OrData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 OrData
)
{
return IoWrite64 (
@@ -1121,10 +1121,10 @@ IoBitFieldOr64 (
UINT64
EFIAPI
IoBitFieldAnd64 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 AndData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData
)
{
return IoWrite64 (
@@ -1167,11 +1167,11 @@ IoBitFieldAnd64 (
UINT64
EFIAPI
IoBitFieldAndThenOr64 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 AndData,
- IN UINT64 OrData
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData,
+ IN UINT64 OrData
)
{
return IoWrite64 (
@@ -1201,11 +1201,11 @@ IoBitFieldAndThenOr64 (
UINT8
EFIAPI
MmioOr8 (
- IN UINTN Address,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINT8 OrData
)
{
- return MmioWrite8 (Address, (UINT8) (MmioRead8 (Address) | OrData));
+ return MmioWrite8 (Address, (UINT8)(MmioRead8 (Address) | OrData));
}
/**
@@ -1229,11 +1229,11 @@ MmioOr8 (
UINT8
EFIAPI
MmioAnd8 (
- IN UINTN Address,
- IN UINT8 AndData
+ IN UINTN Address,
+ IN UINT8 AndData
)
{
- return MmioWrite8 (Address, (UINT8) (MmioRead8 (Address) & AndData));
+ return MmioWrite8 (Address, (UINT8)(MmioRead8 (Address) & AndData));
}
/**
@@ -1260,12 +1260,12 @@ MmioAnd8 (
UINT8
EFIAPI
MmioAndThenOr8 (
- IN UINTN Address,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
)
{
- return MmioWrite8 (Address, (UINT8) ((MmioRead8 (Address) & AndData) | OrData));
+ return MmioWrite8 (Address, (UINT8)((MmioRead8 (Address) & AndData) | OrData));
}
/**
@@ -1291,9 +1291,9 @@ MmioAndThenOr8 (
UINT8
EFIAPI
MmioBitFieldRead8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
return BitFieldRead8 (MmioRead8 (Address), StartBit, EndBit);
@@ -1325,10 +1325,10 @@ MmioBitFieldRead8 (
UINT8
EFIAPI
MmioBitFieldWrite8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
)
{
return MmioWrite8 (
@@ -1367,10 +1367,10 @@ MmioBitFieldWrite8 (
UINT8
EFIAPI
MmioBitFieldOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
)
{
return MmioWrite8 (
@@ -1409,10 +1409,10 @@ MmioBitFieldOr8 (
UINT8
EFIAPI
MmioBitFieldAnd8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
)
{
return MmioWrite8 (
@@ -1454,11 +1454,11 @@ MmioBitFieldAnd8 (
UINT8
EFIAPI
MmioBitFieldAndThenOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
)
{
return MmioWrite8 (
@@ -1489,11 +1489,11 @@ MmioBitFieldAndThenOr8 (
UINT16
EFIAPI
MmioOr16 (
- IN UINTN Address,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINT16 OrData
)
{
- return MmioWrite16 (Address, (UINT16) (MmioRead16 (Address) | OrData));
+ return MmioWrite16 (Address, (UINT16)(MmioRead16 (Address) | OrData));
}
/**
@@ -1518,11 +1518,11 @@ MmioOr16 (
UINT16
EFIAPI
MmioAnd16 (
- IN UINTN Address,
- IN UINT16 AndData
+ IN UINTN Address,
+ IN UINT16 AndData
)
{
- return MmioWrite16 (Address, (UINT16) (MmioRead16 (Address) & AndData));
+ return MmioWrite16 (Address, (UINT16)(MmioRead16 (Address) & AndData));
}
/**
@@ -1549,12 +1549,12 @@ MmioAnd16 (
UINT16
EFIAPI
MmioAndThenOr16 (
- IN UINTN Address,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
)
{
- return MmioWrite16 (Address, (UINT16) ((MmioRead16 (Address) & AndData) | OrData));
+ return MmioWrite16 (Address, (UINT16)((MmioRead16 (Address) & AndData) | OrData));
}
/**
@@ -1581,9 +1581,9 @@ MmioAndThenOr16 (
UINT16
EFIAPI
MmioBitFieldRead16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
return BitFieldRead16 (MmioRead16 (Address), StartBit, EndBit);
@@ -1616,10 +1616,10 @@ MmioBitFieldRead16 (
UINT16
EFIAPI
MmioBitFieldWrite16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
)
{
return MmioWrite16 (
@@ -1659,10 +1659,10 @@ MmioBitFieldWrite16 (
UINT16
EFIAPI
MmioBitFieldOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
)
{
return MmioWrite16 (
@@ -1702,10 +1702,10 @@ MmioBitFieldOr16 (
UINT16
EFIAPI
MmioBitFieldAnd16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
)
{
return MmioWrite16 (
@@ -1748,11 +1748,11 @@ MmioBitFieldAnd16 (
UINT16
EFIAPI
MmioBitFieldAndThenOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
)
{
return MmioWrite16 (
@@ -1783,8 +1783,8 @@ MmioBitFieldAndThenOr16 (
UINT32
EFIAPI
MmioOr32 (
- IN UINTN Address,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINT32 OrData
)
{
return MmioWrite32 (Address, MmioRead32 (Address) | OrData);
@@ -1812,8 +1812,8 @@ MmioOr32 (
UINT32
EFIAPI
MmioAnd32 (
- IN UINTN Address,
- IN UINT32 AndData
+ IN UINTN Address,
+ IN UINT32 AndData
)
{
return MmioWrite32 (Address, MmioRead32 (Address) & AndData);
@@ -1843,9 +1843,9 @@ MmioAnd32 (
UINT32
EFIAPI
MmioAndThenOr32 (
- IN UINTN Address,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
)
{
return MmioWrite32 (Address, (MmioRead32 (Address) & AndData) | OrData);
@@ -1875,9 +1875,9 @@ MmioAndThenOr32 (
UINT32
EFIAPI
MmioBitFieldRead32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
return BitFieldRead32 (MmioRead32 (Address), StartBit, EndBit);
@@ -1910,10 +1910,10 @@ MmioBitFieldRead32 (
UINT32
EFIAPI
MmioBitFieldWrite32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
)
{
return MmioWrite32 (
@@ -1953,10 +1953,10 @@ MmioBitFieldWrite32 (
UINT32
EFIAPI
MmioBitFieldOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
)
{
return MmioWrite32 (
@@ -1996,10 +1996,10 @@ MmioBitFieldOr32 (
UINT32
EFIAPI
MmioBitFieldAnd32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
)
{
return MmioWrite32 (
@@ -2042,11 +2042,11 @@ MmioBitFieldAnd32 (
UINT32
EFIAPI
MmioBitFieldAndThenOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
)
{
return MmioWrite32 (
@@ -2077,8 +2077,8 @@ MmioBitFieldAndThenOr32 (
UINT64
EFIAPI
MmioOr64 (
- IN UINTN Address,
- IN UINT64 OrData
+ IN UINTN Address,
+ IN UINT64 OrData
)
{
return MmioWrite64 (Address, MmioRead64 (Address) | OrData);
@@ -2106,8 +2106,8 @@ MmioOr64 (
UINT64
EFIAPI
MmioAnd64 (
- IN UINTN Address,
- IN UINT64 AndData
+ IN UINTN Address,
+ IN UINT64 AndData
)
{
return MmioWrite64 (Address, MmioRead64 (Address) & AndData);
@@ -2137,9 +2137,9 @@ MmioAnd64 (
UINT64
EFIAPI
MmioAndThenOr64 (
- IN UINTN Address,
- IN UINT64 AndData,
- IN UINT64 OrData
+ IN UINTN Address,
+ IN UINT64 AndData,
+ IN UINT64 OrData
)
{
return MmioWrite64 (Address, (MmioRead64 (Address) & AndData) | OrData);
@@ -2169,9 +2169,9 @@ MmioAndThenOr64 (
UINT64
EFIAPI
MmioBitFieldRead64 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
return BitFieldRead64 (MmioRead64 (Address), StartBit, EndBit);
@@ -2204,10 +2204,10 @@ MmioBitFieldRead64 (
UINT64
EFIAPI
MmioBitFieldWrite64 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 Value
)
{
return MmioWrite64 (
@@ -2247,10 +2247,10 @@ MmioBitFieldWrite64 (
UINT64
EFIAPI
MmioBitFieldOr64 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 OrData
)
{
return MmioWrite64 (
@@ -2290,10 +2290,10 @@ MmioBitFieldOr64 (
UINT64
EFIAPI
MmioBitFieldAnd64 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData
)
{
return MmioWrite64 (
@@ -2336,11 +2336,11 @@ MmioBitFieldAnd64 (
UINT64
EFIAPI
MmioBitFieldAndThenOr64 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 AndData,
- IN UINT64 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData,
+ IN UINT64 OrData
)
{
return MmioWrite64 (
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLib.c b/MdePkg/Library/BaseIoLibIntrinsic/IoLib.c
index 73160f39..57fd1814 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/IoLib.c
+++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLib.c
@@ -7,6 +7,7 @@
**/
#include "BaseIoLibIntrinsicInternal.h"
+#include "IoLibTdx.h"
/**
Reads a 64-bit I/O port.
@@ -26,7 +27,7 @@
UINT64
EFIAPI
IoRead64 (
- IN UINTN Port
+ IN UINTN Port
)
{
ASSERT (FALSE);
@@ -52,15 +53,14 @@ IoRead64 (
UINT64
EFIAPI
IoWrite64 (
- IN UINTN Port,
- IN UINT64 Value
+ IN UINTN Port,
+ IN UINT64 Value
)
{
ASSERT (FALSE);
return 0;
}
-
/**
Reads an 8-bit MMIO register.
@@ -70,6 +70,8 @@ IoWrite64 (
If 8-bit MMIO register operations are not supported, then ASSERT().
+ For Td guest TDVMCALL_MMIO is invoked to read MMIO registers.
+
@param Address The MMIO register to read.
@return The value read.
@@ -78,18 +80,25 @@ IoWrite64 (
UINT8
EFIAPI
MmioRead8 (
- IN UINTN Address
+ IN UINTN Address
)
{
- UINT8 Value;
- BOOLEAN Flag;
+ UINT8 Value;
+ BOOLEAN Flag;
Flag = FilterBeforeMmIoRead (FilterWidth8, Address, &Value);
if (Flag) {
MemoryFence ();
- Value = *(volatile UINT8*)Address;
+
+ if (IsTdxGuest ()) {
+ Value = TdMmioRead8 (Address);
+ } else {
+ Value = *(volatile UINT8 *)Address;
+ }
+
MemoryFence ();
}
+
FilterAfterMmIoRead (FilterWidth8, Address, &Value);
return Value;
@@ -104,6 +113,8 @@ MmioRead8 (
If 8-bit MMIO register operations are not supported, then ASSERT().
+ For Td guest TDVMCALL_MMIO is invoked to write MMIO registers.
+
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
@@ -113,18 +124,25 @@ MmioRead8 (
UINT8
EFIAPI
MmioWrite8 (
- IN UINTN Address,
- IN UINT8 Value
+ IN UINTN Address,
+ IN UINT8 Value
)
{
- BOOLEAN Flag;
+ BOOLEAN Flag;
Flag = FilterBeforeMmIoWrite (FilterWidth8, Address, &Value);
if (Flag) {
MemoryFence ();
- *(volatile UINT8*)Address = Value;
+
+ if (IsTdxGuest ()) {
+ TdMmioWrite8 (Address, Value);
+ } else {
+ *(volatile UINT8 *)Address = Value;
+ }
+
MemoryFence ();
}
+
FilterAfterMmIoWrite (FilterWidth8, Address, &Value);
return Value;
@@ -140,6 +158,8 @@ MmioWrite8 (
If 16-bit MMIO register operations are not supported, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
+ For Td guest TDVMCALL_MMIO is invoked to read MMIO registers.
+
@param Address The MMIO register to read.
@return The value read.
@@ -148,19 +168,26 @@ MmioWrite8 (
UINT16
EFIAPI
MmioRead16 (
- IN UINTN Address
+ IN UINTN Address
)
{
- UINT16 Value;
- BOOLEAN Flag;
+ UINT16 Value;
+ BOOLEAN Flag;
ASSERT ((Address & 1) == 0);
Flag = FilterBeforeMmIoRead (FilterWidth16, Address, &Value);
if (Flag) {
MemoryFence ();
- Value = *(volatile UINT16*)Address;
+
+ if (IsTdxGuest ()) {
+ Value = TdMmioRead16 (Address);
+ } else {
+ Value = *(volatile UINT16 *)Address;
+ }
+
MemoryFence ();
}
+
FilterAfterMmIoRead (FilterWidth16, Address, &Value);
return Value;
@@ -176,6 +203,8 @@ MmioRead16 (
If 16-bit MMIO register operations are not supported, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
+ For Td guest TDVMCALL_MMIO is invoked to write MMIO registers.
+
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
@@ -185,20 +214,27 @@ MmioRead16 (
UINT16
EFIAPI
MmioWrite16 (
- IN UINTN Address,
- IN UINT16 Value
+ IN UINTN Address,
+ IN UINT16 Value
)
{
- BOOLEAN Flag;
+ BOOLEAN Flag;
ASSERT ((Address & 1) == 0);
Flag = FilterBeforeMmIoWrite (FilterWidth16, Address, &Value);
if (Flag) {
MemoryFence ();
- *(volatile UINT16*)Address = Value;
+
+ if (IsTdxGuest ()) {
+ TdMmioWrite16 (Address, Value);
+ } else {
+ *(volatile UINT16 *)Address = Value;
+ }
+
MemoryFence ();
}
+
FilterAfterMmIoWrite (FilterWidth16, Address, &Value);
return Value;
@@ -214,6 +250,8 @@ MmioWrite16 (
If 32-bit MMIO register operations are not supported, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
+ For Td guest TDVMCALL_MMIO is invoked to read MMIO registers.
+
@param Address The MMIO register to read.
@return The value read.
@@ -222,20 +260,27 @@ MmioWrite16 (
UINT32
EFIAPI
MmioRead32 (
- IN UINTN Address
+ IN UINTN Address
)
{
- UINT32 Value;
- BOOLEAN Flag;
+ UINT32 Value;
+ BOOLEAN Flag;
ASSERT ((Address & 3) == 0);
Flag = FilterBeforeMmIoRead (FilterWidth32, Address, &Value);
if (Flag) {
MemoryFence ();
- Value = *(volatile UINT32*)Address;
+
+ if (IsTdxGuest ()) {
+ Value = TdMmioRead32 (Address);
+ } else {
+ Value = *(volatile UINT32 *)Address;
+ }
+
MemoryFence ();
}
+
FilterAfterMmIoRead (FilterWidth32, Address, &Value);
return Value;
@@ -251,6 +296,8 @@ MmioRead32 (
If 32-bit MMIO register operations are not supported, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
+ For Td guest TDVMCALL_MMIO is invoked to write MMIO registers.
+
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
@@ -260,20 +307,27 @@ MmioRead32 (
UINT32
EFIAPI
MmioWrite32 (
- IN UINTN Address,
- IN UINT32 Value
+ IN UINTN Address,
+ IN UINT32 Value
)
{
- BOOLEAN Flag;
+ BOOLEAN Flag;
ASSERT ((Address & 3) == 0);
Flag = FilterBeforeMmIoWrite (FilterWidth32, Address, &Value);
if (Flag) {
MemoryFence ();
- *(volatile UINT32*)Address = Value;
+
+ if (IsTdxGuest ()) {
+ TdMmioWrite32 (Address, Value);
+ } else {
+ *(volatile UINT32 *)Address = Value;
+ }
+
MemoryFence ();
}
+
FilterAfterMmIoWrite (FilterWidth32, Address, &Value);
return Value;
@@ -289,6 +343,8 @@ MmioWrite32 (
If 64-bit MMIO register operations are not supported, then ASSERT().
If Address is not aligned on a 64-bit boundary, then ASSERT().
+ For Td guest TDVMCALL_MMIO is invoked to read MMIO registers.
+
@param Address The MMIO register to read.
@return The value read.
@@ -297,20 +353,27 @@ MmioWrite32 (
UINT64
EFIAPI
MmioRead64 (
- IN UINTN Address
+ IN UINTN Address
)
{
- UINT64 Value;
- BOOLEAN Flag;
+ UINT64 Value;
+ BOOLEAN Flag;
ASSERT ((Address & 7) == 0);
Flag = FilterBeforeMmIoRead (FilterWidth64, Address, &Value);
if (Flag) {
MemoryFence ();
- Value = *(volatile UINT64*)Address;
+
+ if (IsTdxGuest ()) {
+ Value = TdMmioRead64 (Address);
+ } else {
+ Value = *(volatile UINT64 *)Address;
+ }
+
MemoryFence ();
}
+
FilterAfterMmIoRead (FilterWidth64, Address, &Value);
return Value;
@@ -326,6 +389,8 @@ MmioRead64 (
If 64-bit MMIO register operations are not supported, then ASSERT().
If Address is not aligned on a 64-bit boundary, then ASSERT().
+ For Td guest TDVMCALL_MMIO is invoked to write MMIO registers.
+
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
@@ -333,22 +398,28 @@ MmioRead64 (
UINT64
EFIAPI
MmioWrite64 (
- IN UINTN Address,
- IN UINT64 Value
+ IN UINTN Address,
+ IN UINT64 Value
)
{
- BOOLEAN Flag;
+ BOOLEAN Flag;
ASSERT ((Address & 7) == 0);
Flag = FilterBeforeMmIoWrite (FilterWidth64, Address, &Value);
if (Flag) {
MemoryFence ();
- *(volatile UINT64*)Address = Value;
+
+ if (IsTdxGuest ()) {
+ TdMmioWrite64 (Address, Value);
+ } else {
+ *(volatile UINT64 *)Address = Value;
+ }
+
MemoryFence ();
}
+
FilterAfterMmIoWrite (FilterWidth64, Address, &Value);
return Value;
}
-
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibEbc.c b/MdePkg/Library/BaseIoLibIntrinsic/IoLibEbc.c
new file mode 100644
index 00000000..49a19171
--- /dev/null
+++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibEbc.c
@@ -0,0 +1,335 @@
+/** @file
+ I/O Library for EBC.
+
+ EBC does not support port I/O. All APIs in this file ASSERT().
+
+ Copyright (c) 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseIoLibIntrinsicInternal.h"
+
+/**
+ Reads an 8-bit I/O port.
+
+ Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+IoRead8 (
+ IN UINTN Port
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Writes an 8-bit I/O port.
+
+ Writes the 8-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written to the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoWrite8 (
+ IN UINTN Port,
+ IN UINT8 Value
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Reads a 16-bit I/O port.
+
+ Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+IoRead16 (
+ IN UINTN Port
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Writes a 16-bit I/O port.
+
+ Writes the 16-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written to the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoWrite16 (
+ IN UINTN Port,
+ IN UINT16 Value
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Reads a 32-bit I/O port.
+
+ Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+IoRead32 (
+ IN UINTN Port
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Writes a 32-bit I/O port.
+
+ Writes the 32-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written to the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoWrite32 (
+ IN UINTN Port,
+ IN UINT32 Value
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Reads an 8-bit I/O port fifo into a block of memory.
+
+ Reads the 8-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+IoReadFifo8 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Writes a block of memory into an 8-bit I/O port fifo.
+
+ Writes the 8-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+IoWriteFifo8 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Reads a 16-bit I/O port fifo into a block of memory.
+
+ Reads the 16-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+IoReadFifo16 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Writes a block of memory into a 16-bit I/O port fifo.
+
+ Writes the 16-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+IoWriteFifo16 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Reads a 32-bit I/O port fifo into a block of memory.
+
+ Reads the 32-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+IoReadFifo32 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Writes a block of memory into a 32-bit I/O port fifo.
+
+ Writes the 32-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+IoWriteFifo32 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibFifo.c b/MdePkg/Library/BaseIoLibIntrinsic/IoLibFifo.c
new file mode 100644
index 00000000..d2bddb1f
--- /dev/null
+++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibFifo.c
@@ -0,0 +1,217 @@
+/** @file
+ IoFifo read/write routines.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseIoLibIntrinsicInternal.h"
+#include "IoLibSev.h"
+#include "IoLibTdx.h"
+#include
+#include
+
+/**
+ Reads an 8-bit I/O port fifo into a block of memory.
+
+ Reads the 8-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ In TDX a serial of TdIoRead8 is invoked to read the I/O port fifo.
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+IoReadFifo8 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ if (IsTdxGuest ()) {
+ TdIoReadFifo8 (Port, Count, Buffer);
+ } else {
+ SevIoReadFifo8 (Port, Count, Buffer);
+ }
+}
+
+/**
+ Writes a block of memory into an 8-bit I/O port fifo.
+
+ Writes the 8-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ In TDX a serial of TdIoWrite8 is invoked to write data to the I/O port.
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+IoWriteFifo8 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ if (IsTdxGuest ()) {
+ TdIoWriteFifo8 (Port, Count, Buffer);
+ } else {
+ SevIoWriteFifo8 (Port, Count, Buffer);
+ }
+}
+
+/**
+ Reads a 16-bit I/O port fifo into a block of memory.
+
+ Reads the 16-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ In TDX a serial of TdIoRead16 is invoked to read data from the I/O port.
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+IoReadFifo16 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ if (IsTdxGuest ()) {
+ TdIoReadFifo16 (Port, Count, Buffer);
+ } else {
+ SevIoReadFifo16 (Port, Count, Buffer);
+ }
+}
+
+/**
+ Writes a block of memory into a 16-bit I/O port fifo.
+
+ Writes the 16-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ In TDX a serial of TdIoWrite16 is invoked to write data to the I/O port.
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+IoWriteFifo16 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ if (IsTdxGuest ()) {
+ TdIoWriteFifo16 (Port, Count, Buffer);
+ } else {
+ SevIoWriteFifo16 (Port, Count, Buffer);
+ }
+}
+
+/**
+ Reads a 32-bit I/O port fifo into a block of memory.
+
+ Reads the 32-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ In TDX a serial of TdIoRead32 is invoked to read data from the I/O port.
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+IoReadFifo32 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ if (IsTdxGuest ()) {
+ TdIoReadFifo32 (Port, Count, Buffer);
+ } else {
+ SevIoReadFifo32 (Port, Count, Buffer);
+ }
+}
+
+/**
+ Writes a block of memory into a 32-bit I/O port fifo.
+
+ Writes the 32-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ In TDX a serial of TdIoWrite32 is invoked to write data to the I/O port.
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+IoWriteFifo32 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ if (IsTdxGuest ()) {
+ TdIoWriteFifo32 (Port, Count, Buffer);
+ } else {
+ SevIoWriteFifo32 (Port, Count, Buffer);
+ }
+}
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibGcc.c b/MdePkg/Library/BaseIoLibIntrinsic/IoLibGcc.c
index e7502822..d0cc02d5 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/IoLibGcc.c
+++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibGcc.c
@@ -15,8 +15,8 @@
**/
-
#include "BaseIoLibIntrinsicInternal.h"
+#include "IoLibTdx.h"
/**
Reads an 8-bit I/O port.
@@ -25,7 +25,9 @@
This function must guarantee that all I/O read and write operations are
serialized.
- If 8-bit I/O port operations are not supported, then ASSERT().
+ If 8-bit I/O port operations are not supported, then ASSERT()
+
+ For Td guest TDVMCALL_IO is invoked to read I/O port.
@param Port The I/O port to read.
@@ -35,16 +37,21 @@
UINT8
EFIAPI
IoRead8 (
- IN UINTN Port
+ IN UINTN Port
)
{
- UINT8 Data;
- BOOLEAN Flag;
+ UINT8 Data;
+ BOOLEAN Flag;
Flag = FilterBeforeIoRead (FilterWidth8, Port, &Data);
if (Flag) {
- __asm__ __volatile__ ("inb %w1,%b0" : "=a" (Data) : "d" ((UINT16)Port));
+ if (IsTdxGuest ()) {
+ Data = TdIoRead8 (Port);
+ } else {
+ __asm__ __volatile__ ("inb %w1,%b0" : "=a" (Data) : "d" ((UINT16)Port));
+ }
}
+
FilterAfterIoRead (FilterWidth8, Port, &Data);
return Data;
@@ -59,6 +66,8 @@ IoRead8 (
If 8-bit I/O port operations are not supported, then ASSERT().
+ For Td guest TDVMCALL_IO is invoked to write I/O port.
+
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@@ -68,19 +77,24 @@ IoRead8 (
UINT8
EFIAPI
IoWrite8 (
- IN UINTN Port,
- IN UINT8 Value
+ IN UINTN Port,
+ IN UINT8 Value
)
{
- BOOLEAN Flag;
+ BOOLEAN Flag;
Flag = FilterBeforeIoWrite (FilterWidth8, Port, &Value);
if (Flag) {
- __asm__ __volatile__ ("outb %b0,%w1" : : "a" (Value), "d" ((UINT16)Port));
+ if (IsTdxGuest ()) {
+ TdIoWrite8 (Port, Value);
+ } else {
+ __asm__ __volatile__ ("outb %b0,%w1" : : "a" (Value), "d" ((UINT16)Port));
+ }
}
+
FilterAfterIoWrite (FilterWidth8, Port, &Value);
- return Value;;
+ return Value;
}
/**
@@ -93,6 +107,8 @@ IoWrite8 (
If 16-bit I/O port operations are not supported, then ASSERT().
If Port is not aligned on a 16-bit boundary, then ASSERT().
+ For Td guest TDVMCALL_IO is invoked to read I/O port.
+
@param Port The I/O port to read.
@return The value read.
@@ -101,7 +117,7 @@ IoWrite8 (
UINT16
EFIAPI
IoRead16 (
- IN UINTN Port
+ IN UINTN Port
)
{
UINT16 Data;
@@ -111,8 +127,13 @@ IoRead16 (
Flag = FilterBeforeIoRead (FilterWidth16, Port, &Data);
if (Flag) {
- __asm__ __volatile__ ("inw %w1,%w0" : "=a" (Data) : "d" ((UINT16)Port));
+ if (IsTdxGuest ()) {
+ Data = TdIoRead16 (Port);
+ } else {
+ __asm__ __volatile__ ("inw %w1,%w0" : "=a" (Data) : "d" ((UINT16)Port));
+ }
}
+
FilterAfterIoRead (FilterWidth16, Port, &Data);
return Data;
@@ -128,6 +149,8 @@ IoRead16 (
If 16-bit I/O port operations are not supported, then ASSERT().
If Port is not aligned on a 16-bit boundary, then ASSERT().
+ For Td guest TDVMCALL_IO is invoked to write I/O port.
+
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@@ -137,22 +160,26 @@ IoRead16 (
UINT16
EFIAPI
IoWrite16 (
- IN UINTN Port,
- IN UINT16 Value
+ IN UINTN Port,
+ IN UINT16 Value
)
{
-
- BOOLEAN Flag;
+ BOOLEAN Flag;
ASSERT ((Port & 1) == 0);
Flag = FilterBeforeIoWrite (FilterWidth16, Port, &Value);
if (Flag) {
- __asm__ __volatile__ ("outw %w0,%w1" : : "a" (Value), "d" ((UINT16)Port));
+ if (IsTdxGuest ()) {
+ TdIoWrite16 (Port, Value);
+ } else {
+ __asm__ __volatile__ ("outw %w0,%w1" : : "a" (Value), "d" ((UINT16)Port));
+ }
}
+
FilterAfterIoWrite (FilterWidth16, Port, &Value);
- return Value;;
+ return Value;
}
/**
@@ -165,6 +192,8 @@ IoWrite16 (
If 32-bit I/O port operations are not supported, then ASSERT().
If Port is not aligned on a 32-bit boundary, then ASSERT().
+ For Td guest TDVMCALL_IO is invoked to read I/O port.
+
@param Port The I/O port to read.
@return The value read.
@@ -173,7 +202,7 @@ IoWrite16 (
UINT32
EFIAPI
IoRead32 (
- IN UINTN Port
+ IN UINTN Port
)
{
UINT32 Data;
@@ -183,8 +212,13 @@ IoRead32 (
Flag = FilterBeforeIoRead (FilterWidth32, Port, &Data);
if (Flag) {
- __asm__ __volatile__ ("inl %w1,%0" : "=a" (Data) : "d" ((UINT16)Port));
+ if (IsTdxGuest ()) {
+ Data = TdIoRead32 (Port);
+ } else {
+ __asm__ __volatile__ ("inl %w1,%0" : "=a" (Data) : "d" ((UINT16)Port));
+ }
}
+
FilterAfterIoRead (FilterWidth32, Port, &Data);
return Data;
@@ -200,6 +234,8 @@ IoRead32 (
If 32-bit I/O port operations are not supported, then ASSERT().
If Port is not aligned on a 32-bit boundary, then ASSERT().
+ For Td guest TDVMCALL_IO is invoked to write I/O port.
+
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@@ -209,8 +245,8 @@ IoRead32 (
UINT32
EFIAPI
IoWrite32 (
- IN UINTN Port,
- IN UINT32 Value
+ IN UINTN Port,
+ IN UINT32 Value
)
{
BOOLEAN Flag;
@@ -219,10 +255,14 @@ IoWrite32 (
Flag = FilterBeforeIoWrite (FilterWidth32, Port, &Value);
if (Flag) {
- __asm__ __volatile__ ("outl %0,%w1" : : "a" (Value), "d" ((UINT16)Port));
+ if (IsTdxGuest ()) {
+ TdIoWrite32 (Port, Value);
+ } else {
+ __asm__ __volatile__ ("outl %0,%w1" : : "a" (Value), "d" ((UINT16)Port));
+ }
}
+
FilterAfterIoWrite (FilterWidth32, Port, &Value);
return Value;
}
-
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdx.c b/MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdx.c
new file mode 100644
index 00000000..af22143f
--- /dev/null
+++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdx.c
@@ -0,0 +1,665 @@
+/** @file
+ TDX I/O Library routines.
+
+ Copyright (c) 2020-2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "BaseIoLibIntrinsicInternal.h"
+#include
+#include
+#include
+#include
+#include
+#include "IoLibTdx.h"
+
+// Size of TDVMCALL Access, including IO and MMIO
+#define TDVMCALL_ACCESS_SIZE_1 1
+#define TDVMCALL_ACCESS_SIZE_2 2
+#define TDVMCALL_ACCESS_SIZE_4 4
+#define TDVMCALL_ACCESS_SIZE_8 8
+
+// Direction of TDVMCALL Access, including IO and MMIO
+#define TDVMCALL_ACCESS_READ 0
+#define TDVMCALL_ACCESS_WRITE 1
+
+/**
+ Check if it is Tdx guest.
+
+ @return TRUE It is Tdx guest
+ @return FALSE It is not Tdx guest
+
+**/
+BOOLEAN
+EFIAPI
+IsTdxGuest (
+ VOID
+ )
+{
+ return CcProbe () == CcGuestTypeIntelTdx;
+}
+
+/**
+ Reads an 8-bit I/O port.
+
+ TDVMCALL_IO is invoked to read I/O port.
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+TdIoRead8 (
+ IN UINTN Port
+ )
+{
+ UINT64 Status;
+ UINT64 Val;
+
+ Status = TdVmCall (TDVMCALL_IO, TDVMCALL_ACCESS_SIZE_1, TDVMCALL_ACCESS_READ, Port, 0, &Val);
+ if (Status != 0) {
+ TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0);
+ }
+
+ return (UINT8)Val;
+}
+
+/**
+ Reads a 16-bit I/O port.
+
+ TDVMCALL_IO is invoked to write I/O port.
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+TdIoRead16 (
+ IN UINTN Port
+ )
+{
+ UINT64 Status;
+ UINT64 Val;
+
+ ASSERT ((Port & 1) == 0);
+
+ Status = TdVmCall (TDVMCALL_IO, TDVMCALL_ACCESS_SIZE_2, TDVMCALL_ACCESS_READ, Port, 0, &Val);
+ if (Status != 0) {
+ TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0);
+ }
+
+ return (UINT16)Val;
+}
+
+/**
+ Reads a 32-bit I/O port.
+
+ TDVMCALL_IO is invoked to read I/O port.
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+TdIoRead32 (
+ IN UINTN Port
+ )
+{
+ UINT64 Status;
+ UINT64 Val;
+
+ ASSERT ((Port & 3) == 0);
+
+ Status = TdVmCall (TDVMCALL_IO, TDVMCALL_ACCESS_SIZE_4, TDVMCALL_ACCESS_READ, Port, 0, &Val);
+ if (Status != 0) {
+ TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0);
+ }
+
+ return (UINT32)Val;
+}
+
+/**
+ Writes an 8-bit I/O port.
+
+ TDVMCALL_IO is invoked to write I/O port.
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT8
+EFIAPI
+TdIoWrite8 (
+ IN UINTN Port,
+ IN UINT8 Value
+ )
+{
+ UINT64 Status;
+ UINT64 Val;
+
+ Val = Value;
+ Status = TdVmCall (TDVMCALL_IO, TDVMCALL_ACCESS_SIZE_1, TDVMCALL_ACCESS_WRITE, Port, Val, 0);
+ if (Status != 0) {
+ TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0);
+ }
+
+ return Value;
+}
+
+/**
+ Writes a 16-bit I/O port.
+
+ TDVMCALL_IO is invoked to write I/O port.
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT16
+EFIAPI
+TdIoWrite16 (
+ IN UINTN Port,
+ IN UINT16 Value
+ )
+{
+ UINT64 Status;
+ UINT64 Val;
+
+ ASSERT ((Port & 1) == 0);
+ Val = Value;
+ Status = TdVmCall (TDVMCALL_IO, TDVMCALL_ACCESS_SIZE_2, TDVMCALL_ACCESS_WRITE, Port, Val, 0);
+ if (Status != 0) {
+ TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0);
+ }
+
+ return Value;
+}
+
+/**
+ Writes a 32-bit I/O port.
+
+ TDVMCALL_IO is invoked to write I/O port.
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT32
+EFIAPI
+TdIoWrite32 (
+ IN UINTN Port,
+ IN UINT32 Value
+ )
+{
+ UINT64 Status;
+ UINT64 Val;
+
+ ASSERT ((Port & 3) == 0);
+ Val = Value;
+ Status = TdVmCall (TDVMCALL_IO, TDVMCALL_ACCESS_SIZE_4, TDVMCALL_ACCESS_WRITE, Port, Val, 0);
+ if (Status != 0) {
+ TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0);
+ }
+
+ return Value;
+}
+
+/**
+ Reads an 8-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to read MMIO registers.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+TdMmioRead8 (
+ IN UINTN Address
+ )
+{
+ UINT64 Value;
+ UINT64 Status;
+
+ Status = TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_1, TDVMCALL_ACCESS_READ, Address | TdSharedPageMask (), 0, &Value);
+ if (Status != 0) {
+ Value = *(volatile UINT64 *)Address;
+ }
+
+ return (UINT8)Value;
+}
+
+/**
+ Writes an 8-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to read write registers.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+
+**/
+UINT8
+EFIAPI
+TdMmioWrite8 (
+ IN UINTN Address,
+ IN UINT8 Value
+ )
+{
+ UINT64 Val;
+ UINT64 Status;
+
+ Val = Value;
+ Status = TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_1, TDVMCALL_ACCESS_WRITE, Address | TdSharedPageMask (), Val, 0);
+ if (Status != 0) {
+ *(volatile UINT8 *)Address = Value;
+ }
+
+ return Value;
+}
+
+/**
+ Reads a 16-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to read MMIO registers.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+TdMmioRead16 (
+ IN UINTN Address
+ )
+{
+ UINT64 Value;
+ UINT64 Status;
+
+ Status = TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_2, TDVMCALL_ACCESS_READ, Address | TdSharedPageMask (), 0, &Value);
+ if (Status != 0) {
+ Value = *(volatile UINT64 *)Address;
+ }
+
+ return (UINT16)Value;
+}
+
+/**
+ Writes a 16-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to write MMIO registers.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+
+**/
+UINT16
+EFIAPI
+TdMmioWrite16 (
+ IN UINTN Address,
+ IN UINT16 Value
+ )
+{
+ UINT64 Val;
+ UINT64 Status;
+
+ ASSERT ((Address & 1) == 0);
+
+ Val = Value;
+ Status = TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_2, TDVMCALL_ACCESS_WRITE, Address | TdSharedPageMask (), Val, 0);
+ if (Status != 0) {
+ *(volatile UINT16 *)Address = Value;
+ }
+
+ return Value;
+}
+
+/**
+ Reads a 32-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to read MMIO registers.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+TdMmioRead32 (
+ IN UINTN Address
+ )
+{
+ UINT64 Value;
+ UINT64 Status;
+
+ Status = TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_4, TDVMCALL_ACCESS_READ, Address | TdSharedPageMask (), 0, &Value);
+ if (Status != 0) {
+ Value = *(volatile UINT64 *)Address;
+ }
+
+ return (UINT32)Value;
+}
+
+/**
+ Writes a 32-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to write MMIO registers.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+
+**/
+UINT32
+EFIAPI
+TdMmioWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ UINT64 Val;
+ UINT64 Status;
+
+ ASSERT ((Address & 3) == 0);
+
+ Val = Value;
+ Status = TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_4, TDVMCALL_ACCESS_WRITE, Address | TdSharedPageMask (), Val, 0);
+ if (Status != 0) {
+ *(volatile UINT32 *)Address = Value;
+ }
+
+ return Value;
+}
+
+/**
+ Reads a 64-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to read MMIO registers.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+TdMmioRead64 (
+ IN UINTN Address
+ )
+{
+ UINT64 Value;
+ UINT64 Status;
+
+ Status = TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_8, TDVMCALL_ACCESS_READ, Address | TdSharedPageMask (), 0, &Value);
+ if (Status != 0) {
+ Value = *(volatile UINT64 *)Address;
+ }
+
+ return Value;
+}
+
+/**
+ Writes a 64-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to write MMIO registers.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+TdMmioWrite64 (
+ IN UINTN Address,
+ IN UINT64 Value
+ )
+{
+ UINT64 Status;
+ UINT64 Val;
+
+ ASSERT ((Address & 7) == 0);
+
+ Val = Value;
+ Status = TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_8, TDVMCALL_ACCESS_WRITE, Address | TdSharedPageMask (), Val, 0);
+ if (Status != 0) {
+ *(volatile UINT64 *)Address = Value;
+ }
+
+ return Value;
+}
+
+/**
+ Reads an 8-bit I/O port fifo into a block of memory.
+
+ Reads the 8-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ In TDX a serial of TdIoRead8 is invoked to read the I/O port fifo.
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+TdIoReadFifo8 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ UINT8 *Buf8;
+ UINTN Index;
+
+ Buf8 = (UINT8 *)Buffer;
+ for (Index = 0; Index < Count; Index++) {
+ Buf8[Index] = TdIoRead8 (Port);
+ }
+}
+
+/**
+ Writes a block of memory into an 8-bit I/O port fifo.
+
+ Writes the 8-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ In TDX a serial of TdIoWrite8 is invoked to write data to the I/O port.
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+TdIoWriteFifo8 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ UINT8 *Buf8;
+ UINTN Index;
+
+ Buf8 = (UINT8 *)Buffer;
+ for (Index = 0; Index < Count; Index++) {
+ TdIoWrite8 (Port, Buf8[Index]);
+ }
+}
+
+/**
+ Reads a 16-bit I/O port fifo into a block of memory.
+
+ Reads the 16-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ In TDX a serial of TdIoRead16 is invoked to read data from the I/O port.
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+TdIoReadFifo16 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ UINT16 *Buf16;
+ UINTN Index;
+
+ Buf16 = (UINT16 *)Buffer;
+ for (Index = 0; Index < Count; Index++) {
+ Buf16[Index] = TdIoRead16 (Port);
+ }
+}
+
+/**
+ Writes a block of memory into a 16-bit I/O port fifo.
+
+ Writes the 16-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ In TDX a serial of TdIoWrite16 is invoked to write data to the I/O port.
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+TdIoWriteFifo16 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ UINT16 *Buf16;
+ UINTN Index;
+
+ Buf16 = (UINT16 *)Buffer;
+ for (Index = 0; Index < Count; Index++) {
+ TdIoWrite16 (Port, Buf16[Index]);
+ }
+}
+
+/**
+ Reads a 32-bit I/O port fifo into a block of memory.
+
+ Reads the 32-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ In TDX a serial of TdIoRead32 is invoked to read data from the I/O port.
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+TdIoReadFifo32 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ UINT32 *Buf32;
+ UINTN Index;
+
+ Buf32 = (UINT32 *)Buffer;
+ for (Index = 0; Index < Count; Index++) {
+ Buf32[Index] = TdIoRead32 (Port);
+ }
+}
+
+/**
+ Writes a block of memory into a 32-bit I/O port fifo.
+
+ Writes the 32-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ In TDX a serial of TdIoWrite32 is invoked to write data to the I/O port.
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+TdIoWriteFifo32 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ UINT32 *Buf32;
+ UINTN Index;
+
+ Buf32 = (UINT32 *)Buffer;
+ for (Index = 0; Index < Count; Index++) {
+ TdIoWrite32 (Port, Buf32[Index]);
+ }
+}
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdxNull.c b/MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdxNull.c
new file mode 100644
index 00000000..60a569e9
--- /dev/null
+++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdxNull.c
@@ -0,0 +1,497 @@
+/** @file
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include "BaseIoLibIntrinsicInternal.h"
+#include "IoLibTdx.h"
+
+/**
+ Check if it is Tdx guest.
+
+ @return TRUE It is Tdx guest
+ @return FALSE It is not Tdx guest
+
+**/
+BOOLEAN
+EFIAPI
+IsTdxGuest (
+ VOID
+ )
+{
+ return FALSE;
+}
+
+/**
+ Reads an 8-bit I/O port.
+
+ TDVMCALL_IO is invoked to read I/O port.
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+TdIoRead8 (
+ IN UINTN Port
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Reads a 16-bit I/O port.
+
+ TDVMCALL_IO is invoked to write I/O port.
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+TdIoRead16 (
+ IN UINTN Port
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Reads a 32-bit I/O port.
+
+ TDVMCALL_IO is invoked to read I/O port.
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+TdIoRead32 (
+ IN UINTN Port
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Writes an 8-bit I/O port.
+
+ TDVMCALL_IO is invoked to write I/O port.
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT8
+EFIAPI
+TdIoWrite8 (
+ IN UINTN Port,
+ IN UINT8 Value
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Writes a 16-bit I/O port.
+
+ TDVMCALL_IO is invoked to write I/O port.
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT16
+EFIAPI
+TdIoWrite16 (
+ IN UINTN Port,
+ IN UINT16 Value
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Writes a 32-bit I/O port.
+
+ TDVMCALL_IO is invoked to write I/O port.
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT32
+EFIAPI
+TdIoWrite32 (
+ IN UINTN Port,
+ IN UINT32 Value
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Reads an 8-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to read MMIO registers.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+TdMmioRead8 (
+ IN UINTN Address
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Writes an 8-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to read write registers.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+
+**/
+UINT8
+EFIAPI
+TdMmioWrite8 (
+ IN UINTN Address,
+ IN UINT8 Val
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Reads a 16-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to read MMIO registers.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+TdMmioRead16 (
+ IN UINTN Address
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Writes a 16-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to write MMIO registers.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+
+**/
+UINT16
+EFIAPI
+TdMmioWrite16 (
+ IN UINTN Address,
+ IN UINT16 Val
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Reads a 32-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to read MMIO registers.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+TdMmioRead32 (
+ IN UINTN Address
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Writes a 32-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to write MMIO registers.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+
+**/
+UINT32
+EFIAPI
+TdMmioWrite32 (
+ IN UINTN Address,
+ IN UINT32 Val
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Reads a 64-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to read MMIO registers.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+TdMmioRead64 (
+ IN UINTN Address
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Writes a 64-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to write MMIO registers.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+TdMmioWrite64 (
+ IN UINTN Address,
+ IN UINT64 Value
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Reads an 8-bit I/O port fifo into a block of memory.
+
+ Reads the 8-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ In TDX a serial of TdIoRead8 is invoked to read the I/O port fifo.
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+TdIoReadFifo8 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Writes a block of memory into an 8-bit I/O port fifo.
+
+ Writes the 8-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ In TDX a serial of TdIoWrite8 is invoked to write data to the I/O port.
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+TdIoWriteFifo8 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Reads a 16-bit I/O port fifo into a block of memory.
+
+ Reads the 16-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ In TDX a serial of TdIoRead16 is invoked to read data from the I/O port.
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+TdIoReadFifo16 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Writes a block of memory into a 16-bit I/O port fifo.
+
+ Writes the 16-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ In TDX a serial of TdIoWrite16 is invoked to write data to the I/O port.
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+TdIoWriteFifo16 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Reads a 32-bit I/O port fifo into a block of memory.
+
+ Reads the 32-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ In TDX a serial of TdIoRead32 is invoked to read data from the I/O port.
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+TdIoReadFifo32 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Writes a block of memory into a 32-bit I/O port fifo.
+
+ Writes the 32-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ In TDX a serial of TdIoWrite32 is invoked to write data to the I/O port.
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+TdIoWriteFifo32 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibMmioBuffer.c b/MdePkg/Library/BaseIoLibIntrinsic/IoLibMmioBuffer.c
index a0789733..d7c96976 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/IoLibMmioBuffer.c
+++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibMmioBuffer.c
@@ -29,15 +29,15 @@
UINT8 *
EFIAPI
MmioReadBuffer8 (
- IN UINTN StartAddress,
- IN UINTN Length,
- OUT UINT8 *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ OUT UINT8 *Buffer
)
{
- UINT8 *ReturnBuffer;
+ UINT8 *ReturnBuffer;
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));
ReturnBuffer = Buffer;
@@ -73,27 +73,27 @@ MmioReadBuffer8 (
UINT16 *
EFIAPI
MmioReadBuffer16 (
- IN UINTN StartAddress,
- IN UINTN Length,
- OUT UINT16 *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ OUT UINT16 *Buffer
)
{
- UINT16 *ReturnBuffer;
+ UINT16 *ReturnBuffer;
ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));
ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);
- ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);
+ ASSERT (((UINTN)Buffer & (sizeof (UINT16) - 1)) == 0);
ReturnBuffer = Buffer;
while (Length != 0) {
- *(Buffer++) = MmioRead16 (StartAddress);
+ *(Buffer++) = MmioRead16 (StartAddress);
StartAddress += sizeof (UINT16);
- Length -= sizeof (UINT16);
+ Length -= sizeof (UINT16);
}
return ReturnBuffer;
@@ -124,27 +124,27 @@ MmioReadBuffer16 (
UINT32 *
EFIAPI
MmioReadBuffer32 (
- IN UINTN StartAddress,
- IN UINTN Length,
- OUT UINT32 *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ OUT UINT32 *Buffer
)
{
- UINT32 *ReturnBuffer;
+ UINT32 *ReturnBuffer;
ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));
ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);
- ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);
+ ASSERT (((UINTN)Buffer & (sizeof (UINT32) - 1)) == 0);
ReturnBuffer = Buffer;
while (Length != 0) {
- *(Buffer++) = MmioRead32 (StartAddress);
+ *(Buffer++) = MmioRead32 (StartAddress);
StartAddress += sizeof (UINT32);
- Length -= sizeof (UINT32);
+ Length -= sizeof (UINT32);
}
return ReturnBuffer;
@@ -175,33 +175,32 @@ MmioReadBuffer32 (
UINT64 *
EFIAPI
MmioReadBuffer64 (
- IN UINTN StartAddress,
- IN UINTN Length,
- OUT UINT64 *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ OUT UINT64 *Buffer
)
{
- UINT64 *ReturnBuffer;
+ UINT64 *ReturnBuffer;
ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));
ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);
- ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);
+ ASSERT (((UINTN)Buffer & (sizeof (UINT64) - 1)) == 0);
ReturnBuffer = Buffer;
while (Length != 0) {
- *(Buffer++) = MmioRead64 (StartAddress);
+ *(Buffer++) = MmioRead64 (StartAddress);
StartAddress += sizeof (UINT64);
- Length -= sizeof (UINT64);
+ Length -= sizeof (UINT64);
}
return ReturnBuffer;
}
-
/**
Copy data from system memory to the MMIO region by using 8-bit access.
@@ -223,24 +222,23 @@ MmioReadBuffer64 (
UINT8 *
EFIAPI
MmioWriteBuffer8 (
- IN UINTN StartAddress,
- IN UINTN Length,
- IN CONST UINT8 *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ IN CONST UINT8 *Buffer
)
{
- VOID* ReturnBuffer;
+ VOID *ReturnBuffer;
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));
- ReturnBuffer = (UINT8 *) Buffer;
+ ReturnBuffer = (UINT8 *)Buffer;
while (Length-- != 0) {
- MmioWrite8 (StartAddress++, *(Buffer++));
+ MmioWrite8 (StartAddress++, *(Buffer++));
}
return ReturnBuffer;
-
}
/**
@@ -269,34 +267,33 @@ MmioWriteBuffer8 (
UINT16 *
EFIAPI
MmioWriteBuffer16 (
- IN UINTN StartAddress,
- IN UINTN Length,
- IN CONST UINT16 *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ IN CONST UINT16 *Buffer
)
{
- UINT16 *ReturnBuffer;
+ UINT16 *ReturnBuffer;
ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));
ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);
- ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);
+ ASSERT (((UINTN)Buffer & (sizeof (UINT16) - 1)) == 0);
- ReturnBuffer = (UINT16 *) Buffer;
+ ReturnBuffer = (UINT16 *)Buffer;
while (Length != 0) {
MmioWrite16 (StartAddress, *(Buffer++));
StartAddress += sizeof (UINT16);
- Length -= sizeof (UINT16);
+ Length -= sizeof (UINT16);
}
return ReturnBuffer;
}
-
/**
Copy data from system memory to the MMIO region by using 32-bit access.
@@ -323,28 +320,28 @@ MmioWriteBuffer16 (
UINT32 *
EFIAPI
MmioWriteBuffer32 (
- IN UINTN StartAddress,
- IN UINTN Length,
- IN CONST UINT32 *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ IN CONST UINT32 *Buffer
)
{
- UINT32 *ReturnBuffer;
+ UINT32 *ReturnBuffer;
ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));
ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);
- ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);
+ ASSERT (((UINTN)Buffer & (sizeof (UINT32) - 1)) == 0);
- ReturnBuffer = (UINT32 *) Buffer;
+ ReturnBuffer = (UINT32 *)Buffer;
while (Length != 0) {
MmioWrite32 (StartAddress, *(Buffer++));
StartAddress += sizeof (UINT32);
- Length -= sizeof (UINT32);
+ Length -= sizeof (UINT32);
}
return ReturnBuffer;
@@ -376,30 +373,29 @@ MmioWriteBuffer32 (
UINT64 *
EFIAPI
MmioWriteBuffer64 (
- IN UINTN StartAddress,
- IN UINTN Length,
- IN CONST UINT64 *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ IN CONST UINT64 *Buffer
)
{
- UINT64 *ReturnBuffer;
+ UINT64 *ReturnBuffer;
ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));
ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);
- ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);
+ ASSERT (((UINTN)Buffer & (sizeof (UINT64) - 1)) == 0);
- ReturnBuffer = (UINT64 *) Buffer;
+ ReturnBuffer = (UINT64 *)Buffer;
while (Length != 0) {
MmioWrite64 (StartAddress, *(Buffer++));
StartAddress += sizeof (UINT64);
- Length -= sizeof (UINT64);
+ Length -= sizeof (UINT64);
}
return ReturnBuffer;
}
-
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibMsc.c b/MdePkg/Library/BaseIoLibIntrinsic/IoLibMsc.c
index 339711a7..aafd0555 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/IoLibMsc.c
+++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibMsc.c
@@ -13,21 +13,50 @@
**/
-
-
#include "BaseIoLibIntrinsicInternal.h"
+#include "IoLibTdx.h"
//
// Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
//
-int _inp (unsigned short port);
-unsigned short _inpw (unsigned short port);
-unsigned long _inpd (unsigned short port);
-int _outp (unsigned short port, int databyte );
-unsigned short _outpw (unsigned short port, unsigned short dataword );
-unsigned long _outpd (unsigned short port, unsigned long dataword );
-void _ReadWriteBarrier (void);
+int
+_inp (
+ unsigned short port
+ );
+
+unsigned short
+_inpw (
+ unsigned short port
+ );
+
+unsigned long
+_inpd (
+ unsigned short port
+ );
+
+int
+_outp (
+ unsigned short port,
+ int databyte
+ );
+
+unsigned short
+_outpw (
+ unsigned short port,
+ unsigned short dataword
+ );
+
+unsigned long
+_outpd (
+ unsigned short port,
+ unsigned long dataword
+ );
+
+void
+_ReadWriteBarrier (
+ void
+ );
#pragma intrinsic(_inp)
#pragma intrinsic(_inpw)
@@ -54,6 +83,8 @@ void _ReadWriteBarrier (void);
If 8-bit I/O port operations are not supported, then ASSERT().
+ For Td guest TDVMCALL_IO is invoked to read I/O port.
+
@param Port The I/O port to read.
@return The value read.
@@ -62,18 +93,23 @@ void _ReadWriteBarrier (void);
UINT8
EFIAPI
IoRead8 (
- IN UINTN Port
+ IN UINTN Port
)
{
- UINT8 Value;
- BOOLEAN Flag;
+ UINT8 Value;
+ BOOLEAN Flag;
Flag = FilterBeforeIoRead (FilterWidth8, Port, &Value);
if (Flag) {
- _ReadWriteBarrier ();
- Value = (UINT8)_inp ((UINT16)Port);
- _ReadWriteBarrier ();
+ if (IsTdxGuest ()) {
+ Value = TdIoRead8 (Port);
+ } else {
+ _ReadWriteBarrier ();
+ Value = (UINT8)_inp ((UINT16)Port);
+ _ReadWriteBarrier ();
+ }
}
+
FilterAfterIoRead (FilterWidth8, Port, &Value);
return Value;
@@ -88,6 +124,8 @@ IoRead8 (
If 8-bit I/O port operations are not supported, then ASSERT().
+ For Td guest TDVMCALL_IO is invoked to write I/O port.
+
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@@ -97,18 +135,23 @@ IoRead8 (
UINT8
EFIAPI
IoWrite8 (
- IN UINTN Port,
- IN UINT8 Value
+ IN UINTN Port,
+ IN UINT8 Value
)
{
- BOOLEAN Flag;
+ BOOLEAN Flag;
- Flag = FilterBeforeIoWrite(FilterWidth8, Port, &Value);
+ Flag = FilterBeforeIoWrite (FilterWidth8, Port, &Value);
if (Flag) {
- _ReadWriteBarrier ();
- (UINT8)_outp ((UINT16)Port, Value);
- _ReadWriteBarrier ();
+ if (IsTdxGuest ()) {
+ TdIoWrite8 (Port, Value);
+ } else {
+ _ReadWriteBarrier ();
+ (UINT8)_outp ((UINT16)Port, Value);
+ _ReadWriteBarrier ();
+ }
}
+
FilterAfterIoWrite (FilterWidth8, Port, &Value);
return Value;
@@ -124,6 +167,8 @@ IoWrite8 (
If 16-bit I/O port operations are not supported, then ASSERT().
If Port is not aligned on a 16-bit boundary, then ASSERT().
+ For Td guest TDVMCALL_IO is invoked to read I/O port.
+
@param Port The I/O port to read.
@return The value read.
@@ -132,20 +177,25 @@ IoWrite8 (
UINT16
EFIAPI
IoRead16 (
- IN UINTN Port
+ IN UINTN Port
)
{
- UINT16 Value;
- BOOLEAN Flag;
+ UINT16 Value;
+ BOOLEAN Flag;
ASSERT ((Port & 1) == 0);
Flag = FilterBeforeIoRead (FilterWidth16, Port, &Value);
if (Flag) {
- _ReadWriteBarrier ();
- Value = _inpw ((UINT16)Port);
- _ReadWriteBarrier ();
+ if (IsTdxGuest ()) {
+ Value = TdIoRead16 (Port);
+ } else {
+ _ReadWriteBarrier ();
+ Value = _inpw ((UINT16)Port);
+ _ReadWriteBarrier ();
+ }
}
+
FilterBeforeIoRead (FilterWidth16, Port, &Value);
return Value;
@@ -161,6 +211,8 @@ IoRead16 (
If 16-bit I/O port operations are not supported, then ASSERT().
If Port is not aligned on a 16-bit boundary, then ASSERT().
+ For Td guest TDVMCALL_IO is invoked to write I/O port.
+
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@@ -170,20 +222,25 @@ IoRead16 (
UINT16
EFIAPI
IoWrite16 (
- IN UINTN Port,
- IN UINT16 Value
+ IN UINTN Port,
+ IN UINT16 Value
)
{
- BOOLEAN Flag;
+ BOOLEAN Flag;
ASSERT ((Port & 1) == 0);
- Flag = FilterBeforeIoWrite(FilterWidth16, Port, &Value);
+ Flag = FilterBeforeIoWrite (FilterWidth16, Port, &Value);
if (Flag) {
- _ReadWriteBarrier ();
- _outpw ((UINT16)Port, Value);
- _ReadWriteBarrier ();
+ if (IsTdxGuest ()) {
+ TdIoWrite16 (Port, Value);
+ } else {
+ _ReadWriteBarrier ();
+ _outpw ((UINT16)Port, Value);
+ _ReadWriteBarrier ();
+ }
}
+
FilterAfterIoWrite (FilterWidth16, Port, &Value);
return Value;
@@ -199,6 +256,8 @@ IoWrite16 (
If 32-bit I/O port operations are not supported, then ASSERT().
If Port is not aligned on a 32-bit boundary, then ASSERT().
+ For Td guest TDVMCALL_IO is invoked to read I/O port.
+
@param Port The I/O port to read.
@return The value read.
@@ -207,20 +266,25 @@ IoWrite16 (
UINT32
EFIAPI
IoRead32 (
- IN UINTN Port
+ IN UINTN Port
)
{
- UINT32 Value;
- BOOLEAN Flag;
+ UINT32 Value;
+ BOOLEAN Flag;
ASSERT ((Port & 3) == 0);
- Flag = FilterBeforeIoRead(FilterWidth32, Port, &Value);
+ Flag = FilterBeforeIoRead (FilterWidth32, Port, &Value);
if (Flag) {
- _ReadWriteBarrier ();
- Value = _inpd ((UINT16)Port);
- _ReadWriteBarrier ();
+ if (IsTdxGuest ()) {
+ Value = TdIoRead32 (Port);
+ } else {
+ _ReadWriteBarrier ();
+ Value = _inpd ((UINT16)Port);
+ _ReadWriteBarrier ();
+ }
}
+
FilterAfterIoRead (FilterWidth32, Port, &Value);
return Value;
@@ -236,6 +300,8 @@ IoRead32 (
If 32-bit I/O port operations are not supported, then ASSERT().
If Port is not aligned on a 32-bit boundary, then ASSERT().
+ For Td guest TDVMCALL_IO is invoked to write I/O port.
+
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@@ -245,20 +311,25 @@ IoRead32 (
UINT32
EFIAPI
IoWrite32 (
- IN UINTN Port,
- IN UINT32 Value
+ IN UINTN Port,
+ IN UINT32 Value
)
{
- BOOLEAN Flag;
+ BOOLEAN Flag;
ASSERT ((Port & 3) == 0);
- Flag = FilterBeforeIoWrite(FilterWidth32, Port, &Value);
+ Flag = FilterBeforeIoWrite (FilterWidth32, Port, &Value);
if (Flag) {
- _ReadWriteBarrier ();
- _outpd ((UINT16)Port, Value);
- _ReadWriteBarrier ();
+ if (IsTdxGuest ()) {
+ TdIoWrite32 (Port, Value);
+ } else {
+ _ReadWriteBarrier ();
+ _outpd ((UINT16)Port, Value);
+ _ReadWriteBarrier ();
+ }
}
+
FilterAfterIoWrite (FilterWidth32, Port, &Value);
return Value;
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c b/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c
new file mode 100644
index 00000000..58506878
--- /dev/null
+++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c
@@ -0,0 +1,660 @@
+/** @file
+ I/O library for non I/O read and write access (memory map I/O read and
+ write only) architecture, such as ARM, RISC-V and LoongArch processor.
+
+ Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// Include common header file for this module.
+//
+#include "BaseIoLibIntrinsicInternal.h"
+
+/**
+ Reads an 8-bit I/O port.
+
+ Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+IoRead8 (
+ IN UINTN Port
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Writes an 8-bit I/O port.
+
+ Writes the 8-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoWrite8 (
+ IN UINTN Port,
+ IN UINT8 Value
+ )
+{
+ ASSERT (FALSE);
+ return Value;
+}
+
+/**
+ Reads a 16-bit I/O port.
+
+ Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+IoRead16 (
+ IN UINTN Port
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Writes a 16-bit I/O port.
+
+ Writes the 16-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoWrite16 (
+ IN UINTN Port,
+ IN UINT16 Value
+ )
+{
+ ASSERT (FALSE);
+ return Value;
+}
+
+/**
+ Reads a 32-bit I/O port.
+
+ Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+IoRead32 (
+ IN UINTN Port
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Writes a 32-bit I/O port.
+
+ Writes the 32-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoWrite32 (
+ IN UINTN Port,
+ IN UINT32 Value
+ )
+{
+ ASSERT (FALSE);
+ return Value;
+}
+
+/**
+ Reads a 64-bit I/O port.
+
+ Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+IoRead64 (
+ IN UINTN Port
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Writes a 64-bit I/O port.
+
+ Writes the 64-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoWrite64 (
+ IN UINTN Port,
+ IN UINT64 Value
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Reads an 8-bit I/O port fifo into a block of memory.
+
+ Reads the 8-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+IoReadFifo8 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Writes a block of memory into an 8-bit I/O port fifo.
+
+ Writes the 8-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+IoWriteFifo8 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Reads a 16-bit I/O port fifo into a block of memory.
+
+ Reads the 16-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+IoReadFifo16 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Writes a block of memory into a 16-bit I/O port fifo.
+
+ Writes the 16-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+IoWriteFifo16 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Reads a 32-bit I/O port fifo into a block of memory.
+
+ Reads the 32-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+IoReadFifo32 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Writes a block of memory into a 32-bit I/O port fifo.
+
+ Writes the 32-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+IoWriteFifo32 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Reads an 8-bit MMIO register.
+
+ Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+MmioRead8 (
+ IN UINTN Address
+ )
+{
+ UINT8 Value;
+ BOOLEAN Flag;
+
+ Flag = FilterBeforeMmIoRead (FilterWidth8, Address, &Value);
+ if (Flag) {
+ Value = *(volatile UINT8 *)Address;
+ }
+
+ FilterAfterMmIoRead (FilterWidth8, Address, &Value);
+
+ return Value;
+}
+
+/**
+ Writes an 8-bit MMIO register.
+
+ Writes the 8-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+MmioWrite8 (
+ IN UINTN Address,
+ IN UINT8 Value
+ )
+{
+ BOOLEAN Flag;
+
+ Flag = FilterBeforeMmIoWrite (FilterWidth8, Address, &Value);
+ if (Flag) {
+ *(volatile UINT8 *)Address = Value;
+ }
+
+ FilterAfterMmIoWrite (FilterWidth8, Address, &Value);
+
+ return Value;
+}
+
+/**
+ Reads a 16-bit MMIO register.
+
+ Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+MmioRead16 (
+ IN UINTN Address
+ )
+{
+ UINT16 Value;
+ BOOLEAN Flag;
+
+ ASSERT ((Address & 1) == 0);
+
+ Flag = FilterBeforeMmIoRead (FilterWidth16, Address, &Value);
+ if (Flag) {
+ Value = *(volatile UINT16 *)Address;
+ }
+
+ FilterAfterMmIoRead (FilterWidth16, Address, &Value);
+
+ return Value;
+}
+
+/**
+ Writes a 16-bit MMIO register.
+
+ Writes the 16-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+MmioWrite16 (
+ IN UINTN Address,
+ IN UINT16 Value
+ )
+{
+ BOOLEAN Flag;
+
+ ASSERT ((Address & 1) == 0);
+
+ Flag = FilterBeforeMmIoWrite (FilterWidth16, Address, &Value);
+ if (Flag) {
+ *(volatile UINT16 *)Address = Value;
+ }
+
+ FilterAfterMmIoWrite (FilterWidth16, Address, &Value);
+
+ return Value;
+}
+
+/**
+ Reads a 32-bit MMIO register.
+
+ Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+MmioRead32 (
+ IN UINTN Address
+ )
+{
+ UINT32 Value;
+ BOOLEAN Flag;
+
+ ASSERT ((Address & 3) == 0);
+
+ Flag = FilterBeforeMmIoRead (FilterWidth32, Address, &Value);
+ if (Flag) {
+ Value = *(volatile UINT32 *)Address;
+ }
+
+ FilterAfterMmIoRead (FilterWidth32, Address, &Value);
+
+ return Value;
+}
+
+/**
+ Writes a 32-bit MMIO register.
+
+ Writes the 32-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+MmioWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ BOOLEAN Flag;
+
+ ASSERT ((Address & 3) == 0);
+
+ Flag = FilterBeforeMmIoWrite (FilterWidth32, Address, &Value);
+ if (Flag) {
+ *(volatile UINT32 *)Address = Value;
+ }
+
+ FilterAfterMmIoWrite (FilterWidth32, Address, &Value);
+
+ return Value;
+}
+
+/**
+ Reads a 64-bit MMIO register.
+
+ Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+MmioRead64 (
+ IN UINTN Address
+ )
+{
+ UINT64 Value;
+ BOOLEAN Flag;
+
+ ASSERT ((Address & 7) == 0);
+
+ Flag = FilterBeforeMmIoRead (FilterWidth64, Address, &Value);
+ if (Flag) {
+ Value = *(volatile UINT64 *)Address;
+ }
+
+ FilterAfterMmIoRead (FilterWidth64, Address, &Value);
+
+ return Value;
+}
+
+/**
+ Writes a 64-bit MMIO register.
+
+ Writes the 64-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+MmioWrite64 (
+ IN UINTN Address,
+ IN UINT64 Value
+ )
+{
+ BOOLEAN Flag;
+
+ ASSERT ((Address & 7) == 0);
+
+ Flag = FilterBeforeMmIoWrite (FilterWidth64, Address, &Value);
+ if (Flag) {
+ *(volatile UINT64 *)Address = Value;
+ }
+
+ FilterAfterMmIoWrite (FilterWidth64, Address, &Value);
+
+ return Value;
+}
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibSev.h b/MdePkg/Library/BaseIoLibIntrinsic/IoLibSev.h
new file mode 100644
index 00000000..628a9876
--- /dev/null
+++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibSev.h
@@ -0,0 +1,166 @@
+/** @file
+ Header file for SEV IO library.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef IOLIB_SEV_H_
+#define IOLIB_SEV_H_
+
+#include
+
+#include
+#include
+
+/**
+ Reads an 8-bit I/O port fifo into a block of memory.
+
+ Reads the 8-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+SevIoReadFifo8 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ );
+
+/**
+ Writes a block of memory into an 8-bit I/O port fifo.
+
+ Writes the 8-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+SevIoWriteFifo8 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ );
+
+/**
+ Reads an 8-bit I/O port fifo into a block of memory.
+
+ Reads the 8-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+SevIoReadFifo16 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ );
+
+/**
+ Writes a block of memory into an 8-bit I/O port fifo.
+
+ Writes the 8-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+SevIoWriteFifo16 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ );
+
+/**
+ Reads an 8-bit I/O port fifo into a block of memory.
+
+ Reads the 8-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+SevIoReadFifo32 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ );
+
+/**
+ Writes a block of memory into an 8-bit I/O port fifo.
+
+ Writes the 8-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+SevIoWriteFifo32 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ );
+
+#endif
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibTdx.h b/MdePkg/Library/BaseIoLibIntrinsic/IoLibTdx.h
new file mode 100644
index 00000000..0df84289
--- /dev/null
+++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibTdx.h
@@ -0,0 +1,410 @@
+/** @file
+ Header file for Tdx IO library.
+
+ Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef IOLIB_TDX_H_
+#define IOLIB_TDX_H_
+
+/**
+ Check if it is Tdx guest.
+
+ @return TRUE It is Tdx guest
+ @return FALSE It is not Tdx guest
+
+**/
+BOOLEAN
+EFIAPI
+IsTdxGuest (
+ VOID
+ );
+
+/**
+ Reads an 8-bit I/O port.
+
+ TDVMCALL_IO is invoked to read I/O port.
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+TdIoRead8 (
+ IN UINTN Port
+ );
+
+/**
+ Reads a 16-bit I/O port.
+
+ TDVMCALL_IO is invoked to write I/O port.
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+TdIoRead16 (
+ IN UINTN Port
+ );
+
+/**
+ Reads a 32-bit I/O port.
+
+ TDVMCALL_IO is invoked to read I/O port.
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+TdIoRead32 (
+ IN UINTN Port
+ );
+
+/**
+ Writes an 8-bit I/O port.
+
+ TDVMCALL_IO is invoked to write I/O port.
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT8
+EFIAPI
+TdIoWrite8 (
+ IN UINTN Port,
+ IN UINT8 Value
+ );
+
+/**
+ Writes a 16-bit I/O port.
+
+ TDVMCALL_IO is invoked to write I/O port.
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT16
+EFIAPI
+TdIoWrite16 (
+ IN UINTN Port,
+ IN UINT16 Value
+ );
+
+/**
+ Writes a 32-bit I/O port.
+
+ TDVMCALL_IO is invoked to write I/O port.
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT32
+EFIAPI
+TdIoWrite32 (
+ IN UINTN Port,
+ IN UINT32 Value
+ );
+
+/**
+ Reads an 8-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to read MMIO registers.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+TdMmioRead8 (
+ IN UINTN Address
+ );
+
+/**
+ Writes an 8-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to read write registers.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+
+**/
+UINT8
+EFIAPI
+TdMmioWrite8 (
+ IN UINTN Address,
+ IN UINT8 Val
+ );
+
+/**
+ Reads a 16-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to read MMIO registers.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+TdMmioRead16 (
+ IN UINTN Address
+ );
+
+/**
+ Writes a 16-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to write MMIO registers.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+
+**/
+UINT16
+EFIAPI
+TdMmioWrite16 (
+ IN UINTN Address,
+ IN UINT16 Val
+ );
+
+/**
+ Reads a 32-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to read MMIO registers.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+TdMmioRead32 (
+ IN UINTN Address
+ );
+
+/**
+ Writes a 32-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to write MMIO registers.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+
+**/
+UINT32
+EFIAPI
+TdMmioWrite32 (
+ IN UINTN Address,
+ IN UINT32 Val
+ );
+
+/**
+ Reads a 64-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to read MMIO registers.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+TdMmioRead64 (
+ IN UINTN Address
+ );
+
+/**
+ Writes a 64-bit MMIO register.
+
+ TDVMCALL_MMIO is invoked to write MMIO registers.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+TdMmioWrite64 (
+ IN UINTN Address,
+ IN UINT64 Value
+ );
+
+/**
+ Reads an 8-bit I/O port fifo into a block of memory in Tdx.
+
+ Reads the 8-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+TdIoReadFifo8 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ );
+
+/**
+ Writes a block of memory into an 8-bit I/O port fifo in Tdx.
+
+ Writes the 8-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+TdIoWriteFifo8 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ );
+
+/**
+ Reads a 16-bit I/O port fifo into a block of memory in Tdx.
+
+ Reads the 16-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+TdIoReadFifo16 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ );
+
+/**
+ Writes a block of memory into a 16-bit I/O port fifo in Tdx.
+
+ Writes the 16-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+TdIoWriteFifo16 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ );
+
+/**
+ Reads a 32-bit I/O port fifo into a block of memory in Tdx.
+
+ Reads the 32-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+TdIoReadFifo32 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ );
+
+/**
+ Writes a block of memory into a 32-bit I/O port fifo in Tdx.
+
+ Writes the 32-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+TdIoWriteFifo32 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ );
+
+#endif
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/X64/IoFifoSev.nasm b/MdePkg/Library/BaseIoLibIntrinsic/X64/IoFifoSev.nasm
new file mode 100644
index 00000000..18c9a277
--- /dev/null
+++ b/MdePkg/Library/BaseIoLibIntrinsic/X64/IoFifoSev.nasm
@@ -0,0 +1,282 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; Check whether we need to unroll the String I/O in SEV guest
+;
+; Return // eax (1 - unroll, 0 - no unroll)
+;------------------------------------------------------------------------------
+global ASM_PFX(SevNoRepIo)
+ASM_PFX(SevNoRepIo):
+
+ ; CPUID clobbers ebx, ecx and edx
+ push rbx
+ push rcx
+ push rdx
+
+ ; Check if we are runing under hypervisor
+ ; CPUID(1).ECX Bit 31
+ mov eax, 1
+ cpuid
+ bt ecx, 31
+ jnc @UseRepIo
+
+ ; Check if we have Memory encryption CPUID leaf
+ mov eax, 0x80000000
+ cpuid
+ cmp eax, 0x8000001f
+ jl @UseRepIo
+
+ ; Check for memory encryption feature:
+ ; CPUID Fn8000_001F[EAX] - Bit 1
+ ;
+ mov eax, 0x8000001f
+ cpuid
+ bt eax, 1
+ jnc @UseRepIo
+
+ ; Check if memory encryption is enabled
+ ; MSR_0xC0010131 - Bit 0 (SEV enabled)
+ ; MSR_0xC0010131 - Bit 1 (SEV-ES enabled)
+ mov ecx, 0xc0010131
+ rdmsr
+
+ ; Check for (SevEsEnabled == 0 && SevEnabled == 1)
+ and eax, 3
+ cmp eax, 1
+ je @SevNoRepIo_Done
+
+@UseRepIo:
+ xor eax, eax
+
+@SevNoRepIo_Done:
+ pop rdx
+ pop rcx
+ pop rbx
+ ret
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; SevIoReadFifo8 (
+; IN UINTN Port, // rcx
+; IN UINTN Size, // rdx
+; OUT VOID *Buffer // r8
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(SevIoReadFifo8)
+ASM_PFX(SevIoReadFifo8):
+ xchg rcx, rdx
+ xchg rdi, r8 ; rdi: buffer address; r8: save rdi
+
+ ; Check if we need to unroll String I/O
+ call ASM_PFX(SevNoRepIo)
+ test eax, eax
+ jnz @IoReadFifo8_NoRep
+
+ cld
+ rep insb
+ jmp @IoReadFifo8_Done
+
+@IoReadFifo8_NoRep:
+ jrcxz @IoReadFifo8_Done
+
+@IoReadFifo8_Loop:
+ in al, dx
+ mov byte [rdi], al
+ inc rdi
+ loop @IoReadFifo8_Loop
+
+@IoReadFifo8_Done:
+ mov rdi, r8 ; restore rdi
+ ret
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; SevIoReadFifo16 (
+; IN UINTN Port, // rcx
+; IN UINTN Size, // rdx
+; OUT VOID *Buffer // r8
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(SevIoReadFifo16)
+ASM_PFX(SevIoReadFifo16):
+ xchg rcx, rdx
+ xchg rdi, r8 ; rdi: buffer address; r8: save rdi
+
+ ; Check if we need to unroll String I/O
+ call ASM_PFX(SevNoRepIo)
+ test eax, eax
+ jnz @IoReadFifo16_NoRep
+
+ cld
+ rep insw
+ jmp @IoReadFifo16_Done
+
+@IoReadFifo16_NoRep:
+ jrcxz @IoReadFifo16_Done
+
+@IoReadFifo16_Loop:
+ in ax, dx
+ mov word [rdi], ax
+ add rdi, 2
+ loop @IoReadFifo16_Loop
+
+@IoReadFifo16_Done:
+ mov rdi, r8 ; restore rdi
+ ret
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; SevIoReadFifo32 (
+; IN UINTN Port, // rcx
+; IN UINTN Size, // rdx
+; OUT VOID *Buffer // r8
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(SevIoReadFifo32)
+ASM_PFX(SevIoReadFifo32):
+ xchg rcx, rdx
+ xchg rdi, r8 ; rdi: buffer address; r8: save rdi
+
+ ; Check if we need to unroll String I/O
+ call ASM_PFX(SevNoRepIo)
+ test eax, eax
+ jnz @IoReadFifo32_NoRep
+
+ cld
+ rep insd
+ jmp @IoReadFifo32_Done
+
+@IoReadFifo32_NoRep:
+ jrcxz @IoReadFifo32_Done
+
+@IoReadFifo32_Loop:
+ in eax, dx
+ mov dword [rdi], eax
+ add rdi, 4
+ loop @IoReadFifo32_Loop
+
+@IoReadFifo32_Done:
+ mov rdi, r8 ; restore rdi
+ ret
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; IoWriteFifo8 (
+; IN UINTN Port, // rcx
+; IN UINTN Size, // rdx
+; IN VOID *Buffer // r8
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(SevIoWriteFifo8)
+ASM_PFX(SevIoWriteFifo8):
+ xchg rcx, rdx
+ xchg rsi, r8 ; rsi: buffer address; r8: save rsi
+
+ ; Check if we need to unroll String I/O
+ call ASM_PFX(SevNoRepIo)
+ test eax, eax
+ jnz @IoWriteFifo8_NoRep
+
+ cld
+ rep outsb
+ jmp @IoWriteFifo8_Done
+
+@IoWriteFifo8_NoRep:
+ jrcxz @IoWriteFifo8_Done
+
+@IoWriteFifo8_Loop:
+ mov al, byte [rsi]
+ out dx, al
+ inc rsi
+ loop @IoWriteFifo8_Loop
+
+@IoWriteFifo8_Done:
+ mov rsi, r8 ; restore rsi
+ ret
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; SevIoWriteFifo16 (
+; IN UINTN Port, // rcx
+; IN UINTN Size, // rdx
+; IN VOID *Buffer // r8
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(SevIoWriteFifo16)
+ASM_PFX(SevIoWriteFifo16):
+ xchg rcx, rdx
+ xchg rsi, r8 ; rsi: buffer address; r8: save rsi
+
+ ; Check if we need to unroll String I/O
+ call ASM_PFX(SevNoRepIo)
+ test eax, eax
+ jnz @IoWriteFifo16_NoRep
+
+ cld
+ rep outsw
+ jmp @IoWriteFifo16_Done
+
+@IoWriteFifo16_NoRep:
+ jrcxz @IoWriteFifo16_Done
+
+@IoWriteFifo16_Loop:
+ mov ax, word [rsi]
+ out dx, ax
+ add rsi, 2
+ loop @IoWriteFifo16_Loop
+
+@IoWriteFifo16_Done:
+ mov rsi, r8 ; restore rsi
+ ret
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; SevIoWriteFifo32 (
+; IN UINTN Port, // rcx
+; IN UINTN Size, // rdx
+; IN VOID *Buffer // r8
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(SevIoWriteFifo32)
+ASM_PFX(SevIoWriteFifo32):
+ xchg rcx, rdx
+ xchg rsi, r8 ; rsi: buffer address; r8: save rsi
+
+ ; Check if we need to unroll String I/O
+ call ASM_PFX(SevNoRepIo)
+ test eax, eax
+ jnz @IoWriteFifo32_NoRep
+
+ cld
+ rep outsd
+ jmp @IoWriteFifo32_Done
+
+@IoWriteFifo32_NoRep:
+ jrcxz @IoWriteFifo32_Done
+
+@IoWriteFifo32_Loop:
+ mov eax, dword [rsi]
+ out dx, eax
+ add rsi, 4
+ loop @IoWriteFifo32_Loop
+
+@IoWriteFifo32_Done:
+ mov rsi, r8 ; restore rsi
+ ret
+
diff --git a/MdePkg/Library/BaseLib/ARShiftU64.c b/MdePkg/Library/BaseLib/ARShiftU64.c
index 3388b274..6ea1721f 100644
--- a/MdePkg/Library/BaseLib/ARShiftU64.c
+++ b/MdePkg/Library/BaseLib/ARShiftU64.c
@@ -26,8 +26,8 @@
UINT64
EFIAPI
ARShiftU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
)
{
ASSERT (Count < 64);
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index cd1ff63c..60bbedd9 100755
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -21,7 +21,7 @@
LIBRARY_CLASS = BaseLib
#
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARCH64
#
[Sources]
@@ -210,6 +210,7 @@
X86RdRand.c
X86PatchInstruction.c
X86SpeculationBarrier.c
+ IntelTdxNull.c
[Sources.X64]
X64/Thunk16.nasm
@@ -293,6 +294,9 @@
X64/ReadCr0.nasm| MSFT
X64/ReadEflags.nasm| MSFT
+ X64/TdCall.nasm
+ X64/TdVmcall.nasm
+ X64/TdProbe.c
X64/Non-existing.c
Math64.c
@@ -337,19 +341,8 @@
[Sources.ARM]
Arm/InternalSwitchStack.c
Arm/Unaligned.c
- Math64.c | RVCT
Math64.c | MSFT
- Arm/SwitchStack.asm | RVCT
- Arm/SetJumpLongJump.asm | RVCT
- Arm/DisableInterrupts.asm | RVCT
- Arm/EnableInterrupts.asm | RVCT
- Arm/GetInterruptsState.asm | RVCT
- Arm/CpuPause.asm | RVCT
- Arm/CpuBreakpoint.asm | RVCT
- Arm/MemoryFence.asm | RVCT
- Arm/SpeculationBarrier.S | RVCT
-
Arm/SwitchStack.asm | MSFT
Arm/SetJumpLongJump.asm | MSFT
Arm/DisableInterrupts.asm | MSFT
@@ -408,6 +401,24 @@
RiscV64/RiscVCpuPause.S | GCC
RiscV64/RiscVInterrupt.S | GCC
RiscV64/FlushCache.S | GCC
+ RiscV64/CpuScratch.S | GCC
+ RiscV64/ReadTimer.S | GCC
+ RiscV64/RiscVMmu.S | GCC
+ RiscV64/SpeculationBarrier.S | GCC
+
+[Sources.LOONGARCH64]
+ Math64.c
+ Unaligned.c
+ LoongArch64/InternalSwitchStack.c
+ LoongArch64/GetInterruptState.S | GCC
+ LoongArch64/EnableInterrupts.S | GCC
+ LoongArch64/DisableInterrupts.S | GCC
+ LoongArch64/Barrier.S | GCC
+ LoongArch64/MemoryFence.S | GCC
+ LoongArch64/CpuBreakpoint.S | GCC
+ LoongArch64/CpuPause.S | GCC
+ LoongArch64/SetJumpLongJump.S | GCC
+ LoongArch64/SwitchStack.S | GCC
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseLib/BaseLibInternals.h b/MdePkg/Library/BaseLib/BaseLibInternals.h
index 41869562..c9dfc3f2 100644
--- a/MdePkg/Library/BaseLib/BaseLibInternals.h
+++ b/MdePkg/Library/BaseLib/BaseLibInternals.h
@@ -35,8 +35,8 @@
UINT64
EFIAPI
InternalMathLShiftU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
);
/**
@@ -55,8 +55,8 @@ InternalMathLShiftU64 (
UINT64
EFIAPI
InternalMathRShiftU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
);
/**
@@ -75,8 +75,8 @@ InternalMathRShiftU64 (
UINT64
EFIAPI
InternalMathARShiftU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
);
/**
@@ -96,8 +96,8 @@ InternalMathARShiftU64 (
UINT64
EFIAPI
InternalMathLRotU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
);
/**
@@ -117,8 +117,8 @@ InternalMathLRotU64 (
UINT64
EFIAPI
InternalMathRRotU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
);
/**
@@ -136,7 +136,7 @@ InternalMathRRotU64 (
UINT64
EFIAPI
InternalMathSwapBytes64 (
- IN UINT64 Operand
+ IN UINT64 Operand
);
/**
@@ -156,8 +156,8 @@ InternalMathSwapBytes64 (
UINT64
EFIAPI
InternalMathMultU64x32 (
- IN UINT64 Multiplicand,
- IN UINT32 Multiplier
+ IN UINT64 Multiplicand,
+ IN UINT32 Multiplier
);
/**
@@ -177,8 +177,8 @@ InternalMathMultU64x32 (
UINT64
EFIAPI
InternalMathMultU64x64 (
- IN UINT64 Multiplicand,
- IN UINT64 Multiplier
+ IN UINT64 Multiplicand,
+ IN UINT64 Multiplier
);
/**
@@ -198,8 +198,8 @@ InternalMathMultU64x64 (
UINT64
EFIAPI
InternalMathDivU64x32 (
- IN UINT64 Dividend,
- IN UINT32 Divisor
+ IN UINT64 Dividend,
+ IN UINT32 Divisor
);
/**
@@ -219,8 +219,8 @@ InternalMathDivU64x32 (
UINT32
EFIAPI
InternalMathModU64x32 (
- IN UINT64 Dividend,
- IN UINT32 Divisor
+ IN UINT64 Dividend,
+ IN UINT32 Divisor
);
/**
@@ -243,9 +243,9 @@ InternalMathModU64x32 (
UINT64
EFIAPI
InternalMathDivRemU64x32 (
- IN UINT64 Dividend,
- IN UINT32 Divisor,
- OUT UINT32 *Remainder OPTIONAL
+ IN UINT64 Dividend,
+ IN UINT32 Divisor,
+ OUT UINT32 *Remainder OPTIONAL
);
/**
@@ -268,9 +268,9 @@ InternalMathDivRemU64x32 (
UINT64
EFIAPI
InternalMathDivRemU64x64 (
- IN UINT64 Dividend,
- IN UINT64 Divisor,
- OUT UINT64 *Remainder OPTIONAL
+ IN UINT64 Dividend,
+ IN UINT64 Divisor,
+ OUT UINT64 *Remainder OPTIONAL
);
/**
@@ -293,9 +293,9 @@ InternalMathDivRemU64x64 (
INT64
EFIAPI
InternalMathDivRemS64x64 (
- IN INT64 Dividend,
- IN INT64 Divisor,
- OUT INT64 *Remainder OPTIONAL
+ IN INT64 Dividend,
+ IN INT64 Divisor,
+ OUT INT64 *Remainder OPTIONAL
);
/**
@@ -326,13 +326,12 @@ VOID
EFIAPI
InternalSwitchStack (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
- IN VOID *Context1, OPTIONAL
- IN VOID *Context2, OPTIONAL
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL,
IN VOID *NewStack,
IN VA_LIST Marker
);
-
/**
Worker function that returns a bit field from Operand.
@@ -348,12 +347,11 @@ InternalSwitchStack (
UINTN
EFIAPI
BitFieldReadUint (
- IN UINTN Operand,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
);
-
/**
Worker function that reads a bit field from Operand, performs a bitwise OR,
and returns the result.
@@ -373,13 +371,12 @@ BitFieldReadUint (
UINTN
EFIAPI
BitFieldOrUint (
- IN UINTN Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINTN OrData
+ IN UINTN Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINTN OrData
);
-
/**
Worker function that reads a bit field from Operand, performs a bitwise AND,
and returns the result.
@@ -399,13 +396,12 @@ BitFieldOrUint (
UINTN
EFIAPI
BitFieldAndUint (
- IN UINTN Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINTN AndData
+ IN UINTN Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINTN AndData
);
-
/**
Worker function that checks ASSERT condition for JumpBuffer
@@ -423,7 +419,6 @@ InternalAssertJumpBuffer (
IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer
);
-
/**
Restores the CPU context that was saved with SetJump().
@@ -442,7 +437,6 @@ InternalLongJump (
IN UINTN Value
);
-
/**
Check if a Unicode character is a decimal character.
@@ -459,10 +453,9 @@ InternalLongJump (
BOOLEAN
EFIAPI
InternalIsDecimalDigitCharacter (
- IN CHAR16 Char
+ IN CHAR16 Char
);
-
/**
Convert a Unicode character to numerical value.
@@ -479,10 +472,9 @@ InternalIsDecimalDigitCharacter (
UINTN
EFIAPI
InternalHexCharToUintn (
- IN CHAR16 Char
+ IN CHAR16 Char
);
-
/**
Check if a Unicode character is a hexadecimal character.
@@ -500,10 +492,9 @@ InternalHexCharToUintn (
BOOLEAN
EFIAPI
InternalIsHexaDecimalDigitCharacter (
- IN CHAR16 Char
+ IN CHAR16 Char
);
-
/**
Check if a ASCII character is a decimal character.
@@ -520,10 +511,9 @@ InternalIsHexaDecimalDigitCharacter (
BOOLEAN
EFIAPI
InternalAsciiIsDecimalDigitCharacter (
- IN CHAR8 Char
+ IN CHAR8 Char
);
-
/**
Check if a ASCII character is a hexadecimal character.
@@ -541,10 +531,9 @@ InternalAsciiIsDecimalDigitCharacter (
BOOLEAN
EFIAPI
InternalAsciiIsHexaDecimalDigitCharacter (
- IN CHAR8 Char
+ IN CHAR8 Char
);
-
/**
Convert a ASCII character to numerical value.
@@ -561,10 +550,9 @@ InternalAsciiIsHexaDecimalDigitCharacter (
UINTN
EFIAPI
InternalAsciiHexCharToUintn (
- IN CHAR8 Char
+ IN CHAR8 Char
);
-
//
// Ia32 and x64 specific functions
//
@@ -582,7 +570,7 @@ InternalAsciiHexCharToUintn (
VOID
EFIAPI
InternalX86ReadGdtr (
- OUT IA32_DESCRIPTOR *Gdtr
+ OUT IA32_DESCRIPTOR *Gdtr
);
/**
@@ -597,7 +585,7 @@ InternalX86ReadGdtr (
VOID
EFIAPI
InternalX86WriteGdtr (
- IN CONST IA32_DESCRIPTOR *Gdtr
+ IN CONST IA32_DESCRIPTOR *Gdtr
);
/**
@@ -612,7 +600,7 @@ InternalX86WriteGdtr (
VOID
EFIAPI
InternalX86ReadIdtr (
- OUT IA32_DESCRIPTOR *Idtr
+ OUT IA32_DESCRIPTOR *Idtr
);
/**
@@ -627,7 +615,7 @@ InternalX86ReadIdtr (
VOID
EFIAPI
InternalX86WriteIdtr (
- IN CONST IA32_DESCRIPTOR *Idtr
+ IN CONST IA32_DESCRIPTOR *Idtr
);
/**
@@ -643,7 +631,7 @@ InternalX86WriteIdtr (
VOID
EFIAPI
InternalX86FxSave (
- OUT IA32_FX_BUFFER *Buffer
+ OUT IA32_FX_BUFFER *Buffer
);
/**
@@ -659,7 +647,7 @@ InternalX86FxSave (
VOID
EFIAPI
InternalX86FxRestore (
- IN CONST IA32_FX_BUFFER *Buffer
+ IN CONST IA32_FX_BUFFER *Buffer
);
/**
@@ -699,8 +687,8 @@ VOID
EFIAPI
InternalX86EnablePaging32 (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
- IN VOID *Context1, OPTIONAL
- IN VOID *Context2, OPTIONAL
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL,
IN VOID *NewStack
);
@@ -738,8 +726,8 @@ VOID
EFIAPI
InternalX86DisablePaging32 (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
- IN VOID *Context1, OPTIONAL
- IN VOID *Context2, OPTIONAL
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL,
IN VOID *NewStack
);
@@ -773,11 +761,11 @@ InternalX86DisablePaging32 (
VOID
EFIAPI
InternalX86EnablePaging64 (
- IN UINT16 Cs,
- IN UINT64 EntryPoint,
- IN UINT64 Context1, OPTIONAL
- IN UINT64 Context2, OPTIONAL
- IN UINT64 NewStack
+ IN UINT16 Cs,
+ IN UINT64 EntryPoint,
+ IN UINT64 Context1 OPTIONAL,
+ IN UINT64 Context2 OPTIONAL,
+ IN UINT64 NewStack
);
/**
@@ -809,11 +797,11 @@ InternalX86EnablePaging64 (
VOID
EFIAPI
InternalX86DisablePaging64 (
- IN UINT16 Cs,
- IN UINT32 EntryPoint,
- IN UINT32 Context1, OPTIONAL
- IN UINT32 Context2, OPTIONAL
- IN UINT32 NewStack
+ IN UINT16 Cs,
+ IN UINT32 EntryPoint,
+ IN UINT32 Context1 OPTIONAL,
+ IN UINT32 Context2 OPTIONAL,
+ IN UINT32 NewStack
);
/**
@@ -828,7 +816,7 @@ InternalX86DisablePaging64 (
BOOLEAN
EFIAPI
InternalX86RdRand16 (
- OUT UINT16 *Rand
+ OUT UINT16 *Rand
);
/**
@@ -843,7 +831,7 @@ InternalX86RdRand16 (
BOOLEAN
EFIAPI
InternalX86RdRand32 (
- OUT UINT32 *Rand
+ OUT UINT32 *Rand
);
/**
@@ -859,7 +847,7 @@ InternalX86RdRand32 (
BOOLEAN
EFIAPI
InternalX86RdRand64 (
- OUT UINT64 *Rand
+ OUT UINT64 *Rand
);
#else
diff --git a/MdePkg/Library/BaseLib/BitField.c b/MdePkg/Library/BaseLib/BitField.c
index e2098baa..e02d257d 100644
--- a/MdePkg/Library/BaseLib/BitField.c
+++ b/MdePkg/Library/BaseLib/BitField.c
@@ -23,9 +23,9 @@
UINTN
EFIAPI
InternalBaseLibBitFieldReadUint (
- IN UINTN Operand,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
//
@@ -56,10 +56,10 @@ InternalBaseLibBitFieldReadUint (
UINTN
EFIAPI
InternalBaseLibBitFieldOrUint (
- IN UINTN Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINTN OrData
+ IN UINTN Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINTN OrData
)
{
//
@@ -74,7 +74,7 @@ InternalBaseLibBitFieldOrUint (
// ~((UINTN)-2 << EndBit) is a mask in which bit[0] thru bit[EndBit]
// are 1's while bit[EndBit + 1] thru the most significant bit are 0's.
//
- return Operand | ((OrData << StartBit) & ~((UINTN) -2 << EndBit));
+ return Operand | ((OrData << StartBit) & ~((UINTN)-2 << EndBit));
}
/**
@@ -98,10 +98,10 @@ InternalBaseLibBitFieldOrUint (
UINTN
EFIAPI
InternalBaseLibBitFieldAndUint (
- IN UINTN Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINTN AndData
+ IN UINTN Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINTN AndData
)
{
//
@@ -141,9 +141,9 @@ InternalBaseLibBitFieldAndUint (
UINT8
EFIAPI
BitFieldRead8 (
- IN UINT8 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT8 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
ASSERT (EndBit < 8);
@@ -177,10 +177,10 @@ BitFieldRead8 (
UINT8
EFIAPI
BitFieldWrite8 (
- IN UINT8 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 Value
+ IN UINT8 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
)
{
ASSERT (EndBit < 8);
@@ -215,10 +215,10 @@ BitFieldWrite8 (
UINT8
EFIAPI
BitFieldOr8 (
- IN UINT8 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 OrData
+ IN UINT8 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
)
{
ASSERT (EndBit < 8);
@@ -253,10 +253,10 @@ BitFieldOr8 (
UINT8
EFIAPI
BitFieldAnd8 (
- IN UINT8 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData
+ IN UINT8 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
)
{
ASSERT (EndBit < 8);
@@ -294,11 +294,11 @@ BitFieldAnd8 (
UINT8
EFIAPI
BitFieldAndThenOr8 (
- IN UINT8 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINT8 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
)
{
ASSERT (EndBit < 8);
@@ -333,9 +333,9 @@ BitFieldAndThenOr8 (
UINT16
EFIAPI
BitFieldRead16 (
- IN UINT16 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT16 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
ASSERT (EndBit < 16);
@@ -369,10 +369,10 @@ BitFieldRead16 (
UINT16
EFIAPI
BitFieldWrite16 (
- IN UINT16 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 Value
+ IN UINT16 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
)
{
ASSERT (EndBit < 16);
@@ -407,10 +407,10 @@ BitFieldWrite16 (
UINT16
EFIAPI
BitFieldOr16 (
- IN UINT16 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 OrData
+ IN UINT16 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
)
{
ASSERT (EndBit < 16);
@@ -445,10 +445,10 @@ BitFieldOr16 (
UINT16
EFIAPI
BitFieldAnd16 (
- IN UINT16 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData
+ IN UINT16 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
)
{
ASSERT (EndBit < 16);
@@ -486,11 +486,11 @@ BitFieldAnd16 (
UINT16
EFIAPI
BitFieldAndThenOr16 (
- IN UINT16 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINT16 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
)
{
ASSERT (EndBit < 16);
@@ -525,9 +525,9 @@ BitFieldAndThenOr16 (
UINT32
EFIAPI
BitFieldRead32 (
- IN UINT32 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
ASSERT (EndBit < 32);
@@ -561,10 +561,10 @@ BitFieldRead32 (
UINT32
EFIAPI
BitFieldWrite32 (
- IN UINT32 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
)
{
ASSERT (EndBit < 32);
@@ -599,10 +599,10 @@ BitFieldWrite32 (
UINT32
EFIAPI
BitFieldOr32 (
- IN UINT32 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
)
{
ASSERT (EndBit < 32);
@@ -637,10 +637,10 @@ BitFieldOr32 (
UINT32
EFIAPI
BitFieldAnd32 (
- IN UINT32 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
)
{
ASSERT (EndBit < 32);
@@ -678,11 +678,11 @@ BitFieldAnd32 (
UINT32
EFIAPI
BitFieldAndThenOr32 (
- IN UINT32 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
)
{
ASSERT (EndBit < 32);
@@ -717,9 +717,9 @@ BitFieldAndThenOr32 (
UINT64
EFIAPI
BitFieldRead64 (
- IN UINT64 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
ASSERT (EndBit < 64);
@@ -753,10 +753,10 @@ BitFieldRead64 (
UINT64
EFIAPI
BitFieldWrite64 (
- IN UINT64 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 Value
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 Value
)
{
ASSERT (EndBit < 64);
@@ -791,10 +791,10 @@ BitFieldWrite64 (
UINT64
EFIAPI
BitFieldOr64 (
- IN UINT64 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 OrData
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 OrData
)
{
UINT64 Value1;
@@ -811,7 +811,7 @@ BitFieldOr64 (
ASSERT (RShiftU64 (OrData, EndBit - StartBit) == (RShiftU64 (OrData, EndBit - StartBit) & 1));
Value1 = LShiftU64 (OrData, StartBit);
- Value2 = LShiftU64 ((UINT64) - 2, EndBit);
+ Value2 = LShiftU64 ((UINT64)-2, EndBit);
return Operand | (Value1 & ~Value2);
}
@@ -843,10 +843,10 @@ BitFieldOr64 (
UINT64
EFIAPI
BitFieldAnd64 (
- IN UINT64 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 AndData
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData
)
{
UINT64 Value1;
@@ -898,11 +898,11 @@ BitFieldAnd64 (
UINT64
EFIAPI
BitFieldAndThenOr64 (
- IN UINT64 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 AndData,
- IN UINT64 OrData
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData,
+ IN UINT64 OrData
)
{
ASSERT (EndBit < 64);
@@ -938,25 +938,25 @@ BitFieldAndThenOr64 (
UINT8
EFIAPI
BitFieldCountOnes32 (
- IN UINT32 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
- UINT32 Count;
+ UINT32 Count;
ASSERT (EndBit < 32);
ASSERT (StartBit <= EndBit);
- Count = BitFieldRead32 (Operand, StartBit, EndBit);
+ Count = BitFieldRead32 (Operand, StartBit, EndBit);
Count -= ((Count >> 1) & 0x55555555);
- Count = (Count & 0x33333333) + ((Count >> 2) & 0x33333333);
+ Count = (Count & 0x33333333) + ((Count >> 2) & 0x33333333);
Count += Count >> 4;
Count &= 0x0F0F0F0F;
Count += Count >> 8;
Count += Count >> 16;
- return (UINT8) Count & 0x3F;
+ return (UINT8)Count & 0x3F;
}
/**
@@ -982,21 +982,20 @@ BitFieldCountOnes32 (
UINT8
EFIAPI
BitFieldCountOnes64 (
- IN UINT64 Operand,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
- UINT64 BitField;
- UINT8 Count;
+ UINT64 BitField;
+ UINT8 Count;
ASSERT (EndBit < 64);
ASSERT (StartBit <= EndBit);
BitField = BitFieldRead64 (Operand, StartBit, EndBit);
- Count = BitFieldCountOnes32 ((UINT32) BitField, 0, 31);
- Count += BitFieldCountOnes32 ((UINT32) RShiftU64(BitField, 32), 0, 31);
+ Count = BitFieldCountOnes32 ((UINT32)BitField, 0, 31);
+ Count += BitFieldCountOnes32 ((UINT32)RShiftU64 (BitField, 32), 0, 31);
return Count;
}
-
diff --git a/MdePkg/Library/BaseLib/CheckSum.c b/MdePkg/Library/BaseLib/CheckSum.c
index 433f165c..1bdbc5b4 100644
--- a/MdePkg/Library/BaseLib/CheckSum.c
+++ b/MdePkg/Library/BaseLib/CheckSum.c
@@ -3,6 +3,7 @@
algorithm.
Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2022, Pedro Falcato. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -30,24 +31,23 @@
UINT8
EFIAPI
CalculateSum8 (
- IN CONST UINT8 *Buffer,
- IN UINTN Length
+ IN CONST UINT8 *Buffer,
+ IN UINTN Length
)
{
- UINT8 Sum;
- UINTN Count;
+ UINT8 Sum;
+ UINTN Count;
ASSERT (Buffer != NULL);
- ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));
+ ASSERT (Length <= (MAX_ADDRESS - ((UINTN)Buffer) + 1));
for (Sum = 0, Count = 0; Count < Length; Count++) {
- Sum = (UINT8) (Sum + *(Buffer + Count));
+ Sum = (UINT8)(Sum + *(Buffer + Count));
}
return Sum;
}
-
/**
Returns the two's complement checksum of all elements in a buffer
of 8-bit values.
@@ -69,18 +69,18 @@ CalculateSum8 (
UINT8
EFIAPI
CalculateCheckSum8 (
- IN CONST UINT8 *Buffer,
- IN UINTN Length
+ IN CONST UINT8 *Buffer,
+ IN UINTN Length
)
{
- UINT8 CheckSum;
+ UINT8 CheckSum;
CheckSum = CalculateSum8 (Buffer, Length);
//
// Return the checksum based on 2's complement.
//
- return (UINT8) (0x100 - CheckSum);
+ return (UINT8)(0x100 - CheckSum);
}
/**
@@ -105,28 +105,27 @@ CalculateCheckSum8 (
UINT16
EFIAPI
CalculateSum16 (
- IN CONST UINT16 *Buffer,
- IN UINTN Length
+ IN CONST UINT16 *Buffer,
+ IN UINTN Length
)
{
- UINT16 Sum;
- UINTN Count;
- UINTN Total;
+ UINT16 Sum;
+ UINTN Count;
+ UINTN Total;
ASSERT (Buffer != NULL);
- ASSERT (((UINTN) Buffer & 0x1) == 0);
+ ASSERT (((UINTN)Buffer & 0x1) == 0);
ASSERT ((Length & 0x1) == 0);
- ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));
+ ASSERT (Length <= (MAX_ADDRESS - ((UINTN)Buffer) + 1));
Total = Length / sizeof (*Buffer);
for (Sum = 0, Count = 0; Count < Total; Count++) {
- Sum = (UINT16) (Sum + *(Buffer + Count));
+ Sum = (UINT16)(Sum + *(Buffer + Count));
}
return Sum;
}
-
/**
Returns the two's complement checksum of all elements in a buffer of
16-bit values.
@@ -150,21 +149,20 @@ CalculateSum16 (
UINT16
EFIAPI
CalculateCheckSum16 (
- IN CONST UINT16 *Buffer,
- IN UINTN Length
+ IN CONST UINT16 *Buffer,
+ IN UINTN Length
)
{
- UINT16 CheckSum;
+ UINT16 CheckSum;
CheckSum = CalculateSum16 (Buffer, Length);
//
// Return the checksum based on 2's complement.
//
- return (UINT16) (0x10000 - CheckSum);
+ return (UINT16)(0x10000 - CheckSum);
}
-
/**
Returns the sum of all elements in a buffer of 32-bit values. During
calculation, the carry bits are dropped.
@@ -187,18 +185,18 @@ CalculateCheckSum16 (
UINT32
EFIAPI
CalculateSum32 (
- IN CONST UINT32 *Buffer,
- IN UINTN Length
+ IN CONST UINT32 *Buffer,
+ IN UINTN Length
)
{
- UINT32 Sum;
- UINTN Count;
- UINTN Total;
+ UINT32 Sum;
+ UINTN Count;
+ UINTN Total;
ASSERT (Buffer != NULL);
- ASSERT (((UINTN) Buffer & 0x3) == 0);
+ ASSERT (((UINTN)Buffer & 0x3) == 0);
ASSERT ((Length & 0x3) == 0);
- ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));
+ ASSERT (Length <= (MAX_ADDRESS - ((UINTN)Buffer) + 1));
Total = Length / sizeof (*Buffer);
for (Sum = 0, Count = 0; Count < Total; Count++) {
@@ -208,7 +206,6 @@ CalculateSum32 (
return Sum;
}
-
/**
Returns the two's complement checksum of all elements in a buffer of
32-bit values.
@@ -232,21 +229,20 @@ CalculateSum32 (
UINT32
EFIAPI
CalculateCheckSum32 (
- IN CONST UINT32 *Buffer,
- IN UINTN Length
+ IN CONST UINT32 *Buffer,
+ IN UINTN Length
)
{
- UINT32 CheckSum;
+ UINT32 CheckSum;
CheckSum = CalculateSum32 (Buffer, Length);
//
// Return the checksum based on 2's complement.
//
- return (UINT32) ((UINT32)(-1) - CheckSum + 1);
+ return (UINT32)((UINT32)(-1) - CheckSum + 1);
}
-
/**
Returns the sum of all elements in a buffer of 64-bit values. During
calculation, the carry bits are dropped.
@@ -269,18 +265,18 @@ CalculateCheckSum32 (
UINT64
EFIAPI
CalculateSum64 (
- IN CONST UINT64 *Buffer,
- IN UINTN Length
+ IN CONST UINT64 *Buffer,
+ IN UINTN Length
)
{
- UINT64 Sum;
- UINTN Count;
- UINTN Total;
+ UINT64 Sum;
+ UINTN Count;
+ UINTN Total;
ASSERT (Buffer != NULL);
- ASSERT (((UINTN) Buffer & 0x7) == 0);
+ ASSERT (((UINTN)Buffer & 0x7) == 0);
ASSERT ((Length & 0x7) == 0);
- ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));
+ ASSERT (Length <= (MAX_ADDRESS - ((UINTN)Buffer) + 1));
Total = Length / sizeof (*Buffer);
for (Sum = 0, Count = 0; Count < Total; Count++) {
@@ -290,7 +286,6 @@ CalculateSum64 (
return Sum;
}
-
/**
Returns the two's complement checksum of all elements in a buffer of
64-bit values.
@@ -314,18 +309,18 @@ CalculateSum64 (
UINT64
EFIAPI
CalculateCheckSum64 (
- IN CONST UINT64 *Buffer,
- IN UINTN Length
+ IN CONST UINT64 *Buffer,
+ IN UINTN Length
)
{
- UINT64 CheckSum;
+ UINT64 CheckSum;
CheckSum = CalculateSum64 (Buffer, Length);
//
// Return the checksum based on 2's complement.
//
- return (UINT64) ((UINT64)(-1) - CheckSum + 1);
+ return (UINT64)((UINT64)(-1) - CheckSum + 1);
}
GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 mCrcTable[256] = {
@@ -602,9 +597,9 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 mCrcTable[256] = {
**/
UINT32
EFIAPI
-CalculateCrc32(
- IN VOID *Buffer,
- IN UINTN Length
+CalculateCrc32 (
+ IN VOID *Buffer,
+ IN UINTN Length
)
{
UINTN Index;
@@ -612,15 +607,158 @@ CalculateCrc32(
UINT8 *Ptr;
ASSERT (Buffer != NULL);
- ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));
+ ASSERT (Length <= (MAX_ADDRESS - ((UINTN)Buffer) + 1));
//
// Compute CRC
//
Crc = 0xffffffff;
for (Index = 0, Ptr = Buffer; Index < Length; Index++, Ptr++) {
- Crc = (Crc >> 8) ^ mCrcTable[(UINT8) Crc ^ *Ptr];
+ Crc = (Crc >> 8) ^ mCrcTable[(UINT8)Crc ^ *Ptr];
}
return Crc ^ 0xffffffff;
}
+
+GLOBAL_REMOVE_IF_UNREFERENCED STATIC CONST UINT16 mCrc16LookupTable[256] =
+{
+ 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
+ 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
+ 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
+ 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
+ 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
+ 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
+ 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
+ 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
+ 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
+ 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441,
+ 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41,
+ 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840,
+ 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41,
+ 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40,
+ 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640,
+ 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041,
+ 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240,
+ 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441,
+ 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41,
+ 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840,
+ 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41,
+ 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40,
+ 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640,
+ 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041,
+ 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241,
+ 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440,
+ 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40,
+ 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841,
+ 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40,
+ 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41,
+ 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641,
+ 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040
+};
+
+/**
+ Calculates the CRC16-ANSI checksum of the given buffer.
+
+ @param[in] Buffer Pointer to the buffer.
+ @param[in] Length Length of the buffer, in bytes.
+ @param[in] InitialValue Initial value of the CRC.
+
+ @return The CRC16-ANSI checksum.
+**/
+UINT16
+EFIAPI
+CalculateCrc16Ansi (
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN UINT16 InitialValue
+ )
+{
+ CONST UINT8 *Buf;
+ UINT16 Crc;
+
+ Buf = Buffer;
+
+ Crc = ~InitialValue;
+
+ while (Length-- != 0) {
+ Crc = mCrc16LookupTable[(Crc & 0xFF) ^ *(Buf++)] ^ (Crc >> 8);
+ }
+
+ return ~Crc;
+}
+
+GLOBAL_REMOVE_IF_UNREFERENCED STATIC CONST UINT32 mCrc32cLookupTable[256] = {
+ 0x00000000, 0xf26b8303, 0xe13b70f7, 0x1350f3f4, 0xc79a971f, 0x35f1141c,
+ 0x26a1e7e8, 0xd4ca64eb, 0x8ad958cf, 0x78b2dbcc, 0x6be22838, 0x9989ab3b,
+ 0x4d43cfd0, 0xbf284cd3, 0xac78bf27, 0x5e133c24, 0x105ec76f, 0xe235446c,
+ 0xf165b798, 0x030e349b, 0xd7c45070, 0x25afd373, 0x36ff2087, 0xc494a384,
+ 0x9a879fa0, 0x68ec1ca3, 0x7bbcef57, 0x89d76c54, 0x5d1d08bf, 0xaf768bbc,
+ 0xbc267848, 0x4e4dfb4b, 0x20bd8ede, 0xd2d60ddd, 0xc186fe29, 0x33ed7d2a,
+ 0xe72719c1, 0x154c9ac2, 0x061c6936, 0xf477ea35, 0xaa64d611, 0x580f5512,
+ 0x4b5fa6e6, 0xb93425e5, 0x6dfe410e, 0x9f95c20d, 0x8cc531f9, 0x7eaeb2fa,
+ 0x30e349b1, 0xc288cab2, 0xd1d83946, 0x23b3ba45, 0xf779deae, 0x05125dad,
+ 0x1642ae59, 0xe4292d5a, 0xba3a117e, 0x4851927d, 0x5b016189, 0xa96ae28a,
+ 0x7da08661, 0x8fcb0562, 0x9c9bf696, 0x6ef07595, 0x417b1dbc, 0xb3109ebf,
+ 0xa0406d4b, 0x522bee48, 0x86e18aa3, 0x748a09a0, 0x67dafa54, 0x95b17957,
+ 0xcba24573, 0x39c9c670, 0x2a993584, 0xd8f2b687, 0x0c38d26c, 0xfe53516f,
+ 0xed03a29b, 0x1f682198, 0x5125dad3, 0xa34e59d0, 0xb01eaa24, 0x42752927,
+ 0x96bf4dcc, 0x64d4cecf, 0x77843d3b, 0x85efbe38, 0xdbfc821c, 0x2997011f,
+ 0x3ac7f2eb, 0xc8ac71e8, 0x1c661503, 0xee0d9600, 0xfd5d65f4, 0x0f36e6f7,
+ 0x61c69362, 0x93ad1061, 0x80fde395, 0x72966096, 0xa65c047d, 0x5437877e,
+ 0x4767748a, 0xb50cf789, 0xeb1fcbad, 0x197448ae, 0x0a24bb5a, 0xf84f3859,
+ 0x2c855cb2, 0xdeeedfb1, 0xcdbe2c45, 0x3fd5af46, 0x7198540d, 0x83f3d70e,
+ 0x90a324fa, 0x62c8a7f9, 0xb602c312, 0x44694011, 0x5739b3e5, 0xa55230e6,
+ 0xfb410cc2, 0x092a8fc1, 0x1a7a7c35, 0xe811ff36, 0x3cdb9bdd, 0xceb018de,
+ 0xdde0eb2a, 0x2f8b6829, 0x82f63b78, 0x709db87b, 0x63cd4b8f, 0x91a6c88c,
+ 0x456cac67, 0xb7072f64, 0xa457dc90, 0x563c5f93, 0x082f63b7, 0xfa44e0b4,
+ 0xe9141340, 0x1b7f9043, 0xcfb5f4a8, 0x3dde77ab, 0x2e8e845f, 0xdce5075c,
+ 0x92a8fc17, 0x60c37f14, 0x73938ce0, 0x81f80fe3, 0x55326b08, 0xa759e80b,
+ 0xb4091bff, 0x466298fc, 0x1871a4d8, 0xea1a27db, 0xf94ad42f, 0x0b21572c,
+ 0xdfeb33c7, 0x2d80b0c4, 0x3ed04330, 0xccbbc033, 0xa24bb5a6, 0x502036a5,
+ 0x4370c551, 0xb11b4652, 0x65d122b9, 0x97baa1ba, 0x84ea524e, 0x7681d14d,
+ 0x2892ed69, 0xdaf96e6a, 0xc9a99d9e, 0x3bc21e9d, 0xef087a76, 0x1d63f975,
+ 0x0e330a81, 0xfc588982, 0xb21572c9, 0x407ef1ca, 0x532e023e, 0xa145813d,
+ 0x758fe5d6, 0x87e466d5, 0x94b49521, 0x66df1622, 0x38cc2a06, 0xcaa7a905,
+ 0xd9f75af1, 0x2b9cd9f2, 0xff56bd19, 0x0d3d3e1a, 0x1e6dcdee, 0xec064eed,
+ 0xc38d26c4, 0x31e6a5c7, 0x22b65633, 0xd0ddd530, 0x0417b1db, 0xf67c32d8,
+ 0xe52cc12c, 0x1747422f, 0x49547e0b, 0xbb3ffd08, 0xa86f0efc, 0x5a048dff,
+ 0x8ecee914, 0x7ca56a17, 0x6ff599e3, 0x9d9e1ae0, 0xd3d3e1ab, 0x21b862a8,
+ 0x32e8915c, 0xc083125f, 0x144976b4, 0xe622f5b7, 0xf5720643, 0x07198540,
+ 0x590ab964, 0xab613a67, 0xb831c993, 0x4a5a4a90, 0x9e902e7b, 0x6cfbad78,
+ 0x7fab5e8c, 0x8dc0dd8f, 0xe330a81a, 0x115b2b19, 0x020bd8ed, 0xf0605bee,
+ 0x24aa3f05, 0xd6c1bc06, 0xc5914ff2, 0x37faccf1, 0x69e9f0d5, 0x9b8273d6,
+ 0x88d28022, 0x7ab90321, 0xae7367ca, 0x5c18e4c9, 0x4f48173d, 0xbd23943e,
+ 0xf36e6f75, 0x0105ec76, 0x12551f82, 0xe03e9c81, 0x34f4f86a, 0xc69f7b69,
+ 0xd5cf889d, 0x27a40b9e, 0x79b737ba, 0x8bdcb4b9, 0x988c474d, 0x6ae7c44e,
+ 0xbe2da0a5, 0x4c4623a6, 0x5f16d052, 0xad7d5351
+};
+
+/**
+ Calculates the CRC32c checksum of the given buffer.
+
+ @param[in] Buffer Pointer to the buffer.
+ @param[in] Length Length of the buffer, in bytes.
+ @param[in] InitialValue Initial value of the CRC.
+
+ @return The CRC32c checksum.
+**/
+UINT32
+EFIAPI
+CalculateCrc32c (
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN UINT32 InitialValue
+ )
+{
+ CONST UINT8 *Buf;
+ UINT32 Crc;
+
+ Buf = Buffer;
+ Crc = ~InitialValue;
+
+ while (Length-- != 0) {
+ Crc = mCrc32cLookupTable[(Crc & 0xFF) ^ *(Buf++)] ^ (Crc >> 8);
+ }
+
+ return ~Crc;
+}
diff --git a/MdePkg/Library/BaseLib/ChkStkGcc.c b/MdePkg/Library/BaseLib/ChkStkGcc.c
index a1a9dc20..a20b6402 100644
--- a/MdePkg/Library/BaseLib/ChkStkGcc.c
+++ b/MdePkg/Library/BaseLib/ChkStkGcc.c
@@ -12,7 +12,7 @@
Hack function for passing GCC build.
**/
VOID
-__chkstk()
+__chkstk (
+ )
{
}
-
diff --git a/MdePkg/Library/BaseLib/Cpu.c b/MdePkg/Library/BaseLib/Cpu.c
index a3b9c66f..50e0545a 100644
--- a/MdePkg/Library/BaseLib/Cpu.c
+++ b/MdePkg/Library/BaseLib/Cpu.c
@@ -8,7 +8,6 @@
#include "BaseLibInternals.h"
-
/**
Disables CPU interrupts and returns the interrupt state prior to the disable
operation.
@@ -23,7 +22,7 @@ SaveAndDisableInterrupts (
VOID
)
{
- BOOLEAN InterruptState;
+ BOOLEAN InterruptState;
InterruptState = GetInterruptState ();
DisableInterrupts ();
@@ -47,7 +46,7 @@ SaveAndDisableInterrupts (
BOOLEAN
EFIAPI
SetInterruptState (
- IN BOOLEAN InterruptState
+ IN BOOLEAN InterruptState
)
{
if (InterruptState) {
@@ -55,5 +54,6 @@ SetInterruptState (
} else {
DisableInterrupts ();
}
+
return InterruptState;
}
diff --git a/MdePkg/Library/BaseLib/CpuDeadLoop.c b/MdePkg/Library/BaseLib/CpuDeadLoop.c
index 419fa173..8928acca 100644
--- a/MdePkg/Library/BaseLib/CpuDeadLoop.c
+++ b/MdePkg/Library/BaseLib/CpuDeadLoop.c
@@ -6,8 +6,6 @@
**/
-
-
#include
#include
@@ -29,6 +27,6 @@ CpuDeadLoop (
volatile UINTN Index;
for (Index = 0; Index == 0;) {
- CpuPause();
+ CpuPause ();
}
}
diff --git a/MdePkg/Library/BaseLib/DivS64x64Remainder.c b/MdePkg/Library/BaseLib/DivS64x64Remainder.c
index e7ab87c8..e34c8cf4 100644
--- a/MdePkg/Library/BaseLib/DivS64x64Remainder.c
+++ b/MdePkg/Library/BaseLib/DivS64x64Remainder.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -37,9 +34,9 @@
INT64
EFIAPI
DivS64x64Remainder (
- IN INT64 Dividend,
- IN INT64 Divisor,
- OUT INT64 *Remainder OPTIONAL
+ IN INT64 Dividend,
+ IN INT64 Divisor,
+ OUT INT64 *Remainder OPTIONAL
)
{
ASSERT (Divisor != 0);
diff --git a/MdePkg/Library/BaseLib/DivU64x32.c b/MdePkg/Library/BaseLib/DivU64x32.c
index 6cb75403..dc2d3f64 100644
--- a/MdePkg/Library/BaseLib/DivU64x32.c
+++ b/MdePkg/Library/BaseLib/DivU64x32.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -30,8 +27,8 @@
UINT64
EFIAPI
DivU64x32 (
- IN UINT64 Dividend,
- IN UINT32 Divisor
+ IN UINT64 Dividend,
+ IN UINT32 Divisor
)
{
ASSERT (Divisor != 0);
diff --git a/MdePkg/Library/BaseLib/DivU64x32Remainder.c b/MdePkg/Library/BaseLib/DivU64x32Remainder.c
index ca99d40c..48dfc1f9 100644
--- a/MdePkg/Library/BaseLib/DivU64x32Remainder.c
+++ b/MdePkg/Library/BaseLib/DivU64x32Remainder.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -33,9 +30,9 @@
UINT64
EFIAPI
DivU64x32Remainder (
- IN UINT64 Dividend,
- IN UINT32 Divisor,
- OUT UINT32 *Remainder OPTIONAL
+ IN UINT64 Dividend,
+ IN UINT32 Divisor,
+ OUT UINT32 *Remainder OPTIONAL
)
{
ASSERT (Divisor != 0);
diff --git a/MdePkg/Library/BaseLib/DivU64x64Remainder.c b/MdePkg/Library/BaseLib/DivU64x64Remainder.c
index 2264c362..233ba6c5 100644
--- a/MdePkg/Library/BaseLib/DivU64x64Remainder.c
+++ b/MdePkg/Library/BaseLib/DivU64x64Remainder.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -33,9 +30,9 @@
UINT64
EFIAPI
DivU64x64Remainder (
- IN UINT64 Dividend,
- IN UINT64 Divisor,
- OUT UINT64 *Remainder OPTIONAL
+ IN UINT64 Dividend,
+ IN UINT64 Divisor,
+ OUT UINT64 *Remainder OPTIONAL
)
{
ASSERT (Divisor != 0);
diff --git a/MdePkg/Library/BaseLib/FilePaths.c b/MdePkg/Library/BaseLib/FilePaths.c
index 77b3fc32..bb584d09 100644
--- a/MdePkg/Library/BaseLib/FilePaths.c
+++ b/MdePkg/Library/BaseLib/FilePaths.c
@@ -19,29 +19,33 @@
**/
BOOLEAN
EFIAPI
-PathRemoveLastItem(
- IN OUT CHAR16 *Path
+PathRemoveLastItem (
+ IN OUT CHAR16 *Path
)
{
- CHAR16 *Walker;
- CHAR16 *LastSlash;
+ CHAR16 *Walker;
+ CHAR16 *LastSlash;
+
//
// get directory name from path... ('chop' off extra)
//
for ( Walker = Path, LastSlash = NULL
- ; Walker != NULL && *Walker != CHAR_NULL
- ; Walker++
- ){
- if (*Walker == L'\\' && *(Walker + 1) != CHAR_NULL) {
+ ; Walker != NULL && *Walker != CHAR_NULL
+ ; Walker++
+ )
+ {
+ if ((*Walker == L'\\') && (*(Walker + 1) != CHAR_NULL)) {
LastSlash = Walker+1;
- } else if (*Walker == L':' && *(Walker + 1) != L'\\' && *(Walker + 1) != CHAR_NULL) {
+ } else if ((*Walker == L':') && (*(Walker + 1) != L'\\') && (*(Walker + 1) != CHAR_NULL)) {
LastSlash = Walker+1;
}
}
+
if (LastSlash != NULL) {
*LastSlash = CHAR_NULL;
return (TRUE);
}
+
return (FALSE);
}
@@ -59,11 +63,11 @@ PathRemoveLastItem(
@return Returns Path, otherwise returns NULL to indicate that an error has occurred.
**/
-CHAR16*
+CHAR16 *
EFIAPI
-PathCleanUpDirectories(
- IN CHAR16 *Path
-)
+PathCleanUpDirectories (
+ IN CHAR16 *Path
+ )
{
CHAR16 *TempString;
@@ -93,6 +97,7 @@ PathCleanUpDirectories(
while ((TempString = StrStr (Path, L"\\.\\")) != NULL) {
CopyMem (TempString, TempString + 2, StrSize (TempString + 2));
}
+
if ((StrLen (Path) >= 2) && (StrCmp (Path + StrLen (Path) - 2, L"\\.") == 0)) {
Path[StrLen (Path) - 1] = CHAR_NULL;
}
@@ -100,11 +105,12 @@ PathCleanUpDirectories(
//
// Remove all the "\..". E.g.: fs0:\abc\..\def\..
//
- while (((TempString = StrStr(Path, L"\\..")) != NULL) &&
+ while (((TempString = StrStr (Path, L"\\..")) != NULL) &&
((*(TempString + 3) == L'\\') || (*(TempString + 3) == CHAR_NULL))
- ) {
+ )
+ {
*(TempString + 1) = CHAR_NULL;
- PathRemoveLastItem(Path);
+ PathRemoveLastItem (Path);
if (*(TempString + 3) != CHAR_NULL) {
CopyMem (Path + StrLen (Path), TempString + 4, StrSize (TempString + 4));
}
@@ -112,4 +118,3 @@ PathCleanUpDirectories(
return Path;
}
-
diff --git a/MdePkg/Library/BaseLib/GetPowerOfTwo32.c b/MdePkg/Library/BaseLib/GetPowerOfTwo32.c
index 644bb4a8..33bb3572 100644
--- a/MdePkg/Library/BaseLib/GetPowerOfTwo32.c
+++ b/MdePkg/Library/BaseLib/GetPowerOfTwo32.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -27,7 +24,7 @@
UINT32
EFIAPI
GetPowerOfTwo32 (
- IN UINT32 Operand
+ IN UINT32 Operand
)
{
if (0 == Operand) {
diff --git a/MdePkg/Library/BaseLib/GetPowerOfTwo64.c b/MdePkg/Library/BaseLib/GetPowerOfTwo64.c
index fe0d8c7e..0e134289 100644
--- a/MdePkg/Library/BaseLib/GetPowerOfTwo64.c
+++ b/MdePkg/Library/BaseLib/GetPowerOfTwo64.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -27,12 +24,12 @@
UINT64
EFIAPI
GetPowerOfTwo64 (
- IN UINT64 Operand
+ IN UINT64 Operand
)
{
if (Operand == 0) {
return 0;
}
- return LShiftU64 (1, (UINTN) HighBitSet64 (Operand));
+ return LShiftU64 (1, (UINTN)HighBitSet64 (Operand));
}
diff --git a/MdePkg/Library/BaseLib/HighBitSet32.c b/MdePkg/Library/BaseLib/HighBitSet32.c
index adfaf6d9..01a082e2 100644
--- a/MdePkg/Library/BaseLib/HighBitSet32.c
+++ b/MdePkg/Library/BaseLib/HighBitSet32.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -28,14 +25,15 @@
INTN
EFIAPI
HighBitSet32 (
- IN UINT32 Operand
+ IN UINT32 Operand
)
{
- INTN BitIndex;
+ INTN BitIndex;
if (Operand == 0) {
- return - 1;
+ return -1;
}
+
for (BitIndex = 31; BitIndex > 0; BitIndex--, Operand <<= 1) {
if ((INT32)Operand < 0) {
break;
diff --git a/MdePkg/Library/BaseLib/HighBitSet64.c b/MdePkg/Library/BaseLib/HighBitSet64.c
index ac952087..6dcf202a 100644
--- a/MdePkg/Library/BaseLib/HighBitSet64.c
+++ b/MdePkg/Library/BaseLib/HighBitSet64.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -28,7 +25,7 @@
INTN
EFIAPI
HighBitSet64 (
- IN UINT64 Operand
+ IN UINT64 Operand
)
{
if (Operand == (UINT32)Operand) {
@@ -42,7 +39,7 @@ HighBitSet64 (
// Operand is really a 64-bit integer
//
if (sizeof (UINTN) == sizeof (UINT32)) {
- return HighBitSet32 (((UINT32*)&Operand)[1]) + 32;
+ return HighBitSet32 (((UINT32 *)&Operand)[1]) + 32;
} else {
return HighBitSet32 ((UINT32)RShiftU64 (Operand, 32)) + 32;
}
diff --git a/MdePkg/Library/BaseLib/Ia32/ARShiftU64.c b/MdePkg/Library/BaseLib/Ia32/ARShiftU64.c
index 33287bc1..c2d579fa 100644
--- a/MdePkg/Library/BaseLib/Ia32/ARShiftU64.c
+++ b/MdePkg/Library/BaseLib/Ia32/ARShiftU64.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Shifts a 64-bit integer right between 0 and 63 bits. The high bits
are filled with original integer's bit 63. The shifted value is returned.
@@ -25,8 +22,8 @@
UINT64
EFIAPI
InternalMathARShiftU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
)
{
_asm {
@@ -42,4 +39,3 @@ L0:
sar edx, cl
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.c b/MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.c
index 973c9acd..e6e5141b 100644
--- a/MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.c
+++ b/MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.c
@@ -6,14 +6,14 @@
**/
-
-
-
/**
Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
**/
-void __debugbreak (VOID);
+void
+__debugbreak (
+ VOID
+ );
#pragma intrinsic(__debugbreak)
@@ -32,4 +32,3 @@ CpuBreakpoint (
{
__debugbreak ();
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/CpuId.c b/MdePkg/Library/BaseLib/Ia32/CpuId.c
index b47c7380..43843a3a 100644
--- a/MdePkg/Library/BaseLib/Ia32/CpuId.c
+++ b/MdePkg/Library/BaseLib/Ia32/CpuId.c
@@ -34,11 +34,11 @@
UINT32
EFIAPI
AsmCpuid (
- IN UINT32 Index,
- OUT UINT32 *RegisterEax, OPTIONAL
- OUT UINT32 *RegisterEbx, OPTIONAL
- OUT UINT32 *RegisterEcx, OPTIONAL
- OUT UINT32 *RegisterEdx OPTIONAL
+ IN UINT32 Index,
+ OUT UINT32 *RegisterEax OPTIONAL,
+ OUT UINT32 *RegisterEbx OPTIONAL,
+ OUT UINT32 *RegisterEcx OPTIONAL,
+ OUT UINT32 *RegisterEdx OPTIONAL
)
{
_asm {
@@ -65,4 +65,3 @@ SkipEdx:
mov eax, Index
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/CpuIdEx.c b/MdePkg/Library/BaseLib/Ia32/CpuIdEx.c
index 2011645a..617db8d7 100644
--- a/MdePkg/Library/BaseLib/Ia32/CpuIdEx.c
+++ b/MdePkg/Library/BaseLib/Ia32/CpuIdEx.c
@@ -41,12 +41,12 @@
UINT32
EFIAPI
AsmCpuidEx (
- IN UINT32 Index,
- IN UINT32 SubIndex,
- OUT UINT32 *RegisterEax, OPTIONAL
- OUT UINT32 *RegisterEbx, OPTIONAL
- OUT UINT32 *RegisterEcx, OPTIONAL
- OUT UINT32 *RegisterEdx OPTIONAL
+ IN UINT32 Index,
+ IN UINT32 SubIndex,
+ OUT UINT32 *RegisterEax OPTIONAL,
+ OUT UINT32 *RegisterEbx OPTIONAL,
+ OUT UINT32 *RegisterEcx OPTIONAL,
+ OUT UINT32 *RegisterEdx OPTIONAL
)
{
_asm {
diff --git a/MdePkg/Library/BaseLib/Ia32/CpuPause.c b/MdePkg/Library/BaseLib/Ia32/CpuPause.c
index ba87f6df..f156158c 100644
--- a/MdePkg/Library/BaseLib/Ia32/CpuPause.c
+++ b/MdePkg/Library/BaseLib/Ia32/CpuPause.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Requests CPU to pause for a short period of time.
@@ -26,4 +23,3 @@ CpuPause (
pause
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/DisableCache.c b/MdePkg/Library/BaseLib/Ia32/DisableCache.c
index 9227a976..f65c9d2d 100644
--- a/MdePkg/Library/BaseLib/Ia32/DisableCache.c
+++ b/MdePkg/Library/BaseLib/Ia32/DisableCache.c
@@ -27,4 +27,3 @@ AsmDisableCache (
wbinvd
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/DisableInterrupts.c b/MdePkg/Library/BaseLib/Ia32/DisableInterrupts.c
index bb307768..47a8758c 100644
--- a/MdePkg/Library/BaseLib/Ia32/DisableInterrupts.c
+++ b/MdePkg/Library/BaseLib/Ia32/DisableInterrupts.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Disables CPU interrupts.
@@ -23,4 +20,3 @@ DisableInterrupts (
cli
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/DisablePaging32.c b/MdePkg/Library/BaseLib/Ia32/DisablePaging32.c
index 989c954c..72bf39e7 100644
--- a/MdePkg/Library/BaseLib/Ia32/DisablePaging32.c
+++ b/MdePkg/Library/BaseLib/Ia32/DisablePaging32.c
@@ -38,13 +38,13 @@
function after paging is disabled.
**/
-__declspec (naked)
+__declspec(naked)
VOID
EFIAPI
InternalX86DisablePaging32 (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
- IN VOID *Context1, OPTIONAL
- IN VOID *Context2, OPTIONAL
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL,
IN VOID *NewStack
)
{
diff --git a/MdePkg/Library/BaseLib/Ia32/DivS64x64Remainder.c b/MdePkg/Library/BaseLib/Ia32/DivS64x64Remainder.c
index 88a7ae91..57365850 100644
--- a/MdePkg/Library/BaseLib/Ia32/DivS64x64Remainder.c
+++ b/MdePkg/Library/BaseLib/Ia32/DivS64x64Remainder.c
@@ -28,20 +28,21 @@
INT64
EFIAPI
InternalMathDivRemS64x64 (
- IN INT64 Dividend,
- IN INT64 Divisor,
- OUT INT64 *Remainder OPTIONAL
+ IN INT64 Dividend,
+ IN INT64 Divisor,
+ OUT INT64 *Remainder OPTIONAL
)
{
- INT64 Quot;
+ INT64 Quot;
Quot = InternalMathDivRemU64x64 (
- (UINT64) (Dividend >= 0 ? Dividend : -Dividend),
- (UINT64) (Divisor >= 0 ? Divisor : -Divisor),
- (UINT64 *) Remainder
+ (UINT64)(Dividend >= 0 ? Dividend : -Dividend),
+ (UINT64)(Divisor >= 0 ? Divisor : -Divisor),
+ (UINT64 *)Remainder
);
- if (Remainder != NULL && Dividend < 0) {
+ if ((Remainder != NULL) && (Dividend < 0)) {
*Remainder = -*Remainder;
}
+
return (Dividend ^ Divisor) >= 0 ? Quot : -Quot;
}
diff --git a/MdePkg/Library/BaseLib/Ia32/DivU64x32.c b/MdePkg/Library/BaseLib/Ia32/DivU64x32.c
index 4bb45311..7f077948 100644
--- a/MdePkg/Library/BaseLib/Ia32/DivU64x32.c
+++ b/MdePkg/Library/BaseLib/Ia32/DivU64x32.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Divides a 64-bit unsigned integer by a 32-bit unsigned integer and
generates a 64-bit unsigned result.
@@ -26,8 +23,8 @@
UINT64
EFIAPI
InternalMathDivU64x32 (
- IN UINT64 Dividend,
- IN UINT32 Divisor
+ IN UINT64 Dividend,
+ IN UINT32 Divisor
)
{
_asm {
@@ -41,4 +38,3 @@ InternalMathDivU64x32 (
pop edx ; restore high-order dword of the quotient
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.c b/MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.c
index bd80a7b0..b68b76ac 100644
--- a/MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.c
+++ b/MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.c
@@ -26,9 +26,9 @@
UINT64
EFIAPI
InternalMathDivRemU64x32 (
- IN UINT64 Dividend,
- IN UINT32 Divisor,
- OUT UINT32 *Remainder
+ IN UINT64 Dividend,
+ IN UINT32 Divisor,
+ OUT UINT32 *Remainder
)
{
_asm {
@@ -46,4 +46,3 @@ RemainderNull:
pop edx
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/EnableCache.c b/MdePkg/Library/BaseLib/Ia32/EnableCache.c
index d5bf82f7..a6874d39 100644
--- a/MdePkg/Library/BaseLib/Ia32/EnableCache.c
+++ b/MdePkg/Library/BaseLib/Ia32/EnableCache.c
@@ -27,4 +27,3 @@ AsmEnableCache (
mov cr0, eax
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.c b/MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.c
index c8b2f76b..056815f3 100644
--- a/MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.c
+++ b/MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Enables CPU interrupts for the smallest window required to capture any
pending interrupts.
@@ -27,4 +24,3 @@ EnableDisableInterrupts (
cli
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/EnableInterrupts.c b/MdePkg/Library/BaseLib/Ia32/EnableInterrupts.c
index 015bbd9d..f2f56315 100644
--- a/MdePkg/Library/BaseLib/Ia32/EnableInterrupts.c
+++ b/MdePkg/Library/BaseLib/Ia32/EnableInterrupts.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Enables CPU interrupts.
@@ -23,4 +20,3 @@ EnableInterrupts (
sti
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/EnablePaging32.c b/MdePkg/Library/BaseLib/Ia32/EnablePaging32.c
index ee4ae6b4..c560de30 100644
--- a/MdePkg/Library/BaseLib/Ia32/EnablePaging32.c
+++ b/MdePkg/Library/BaseLib/Ia32/EnablePaging32.c
@@ -41,13 +41,13 @@
function after paging is enabled.
**/
-__declspec (naked)
+__declspec(naked)
VOID
EFIAPI
InternalX86EnablePaging32 (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
- IN VOID *Context1, OPTIONAL
- IN VOID *Context2, OPTIONAL
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL,
IN VOID *NewStack
)
{
@@ -72,4 +72,3 @@ InternalX86EnablePaging32 (
jmp $
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm b/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm
index 404991bc..81b4868d 100644
--- a/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -44,16 +44,12 @@ ASM_PFX(InternalX86EnablePaging64):
mov cr0, eax ; enable paging
retf ; topmost 2 dwords hold the address
.0:
- DB 0x67, 0x48 ; 32-bit address size, 64-bit operand size
- mov ebx, [esp] ; mov rbx, [esp]
- DB 0x67, 0x48
- mov ecx, [esp + 8] ; mov rcx, [esp + 8]
- DB 0x67, 0x48
- mov edx, [esp + 0x10] ; mov rdx, [esp + 10h]
- DB 0x67, 0x48
- mov esp, [esp + 0x18] ; mov rsp, [esp + 18h]
- DB 0x48
- add esp, -0x20 ; add rsp, -20h
- call ebx ; call rbx
+BITS 64
+ mov rbx, [esp]
+ mov rcx, [esp + 8]
+ mov rdx, [esp + 0x10]
+ mov rsp, [esp + 0x18]
+ add rsp, -0x20
+ call rbx
hlt ; no one should get here
diff --git a/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c b/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c
index f0412322..e5916e38 100644
--- a/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c
+++ b/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Flushes a cache line from all the instruction and data caches within the
coherency domain of the CPU.
@@ -27,7 +24,7 @@
VOID *
EFIAPI
AsmFlushCacheLine (
- IN VOID *LinearAddress
+ IN VOID *LinearAddress
)
{
//
@@ -49,4 +46,3 @@ Done:
return LinearAddress;
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/FxRestore.c b/MdePkg/Library/BaseLib/Ia32/FxRestore.c
index b084ec82..f0dee240 100644
--- a/MdePkg/Library/BaseLib/Ia32/FxRestore.c
+++ b/MdePkg/Library/BaseLib/Ia32/FxRestore.c
@@ -6,10 +6,8 @@
**/
-
#include "BaseLibInternals.h"
-
/**
Restores the current floating point/SSE/SSE2 context from a buffer.
@@ -23,7 +21,7 @@
VOID
EFIAPI
InternalX86FxRestore (
- IN CONST IA32_FX_BUFFER *Buffer
+ IN CONST IA32_FX_BUFFER *Buffer
)
{
_asm {
@@ -31,4 +29,3 @@ InternalX86FxRestore (
fxrstor [eax]
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/FxSave.c b/MdePkg/Library/BaseLib/Ia32/FxSave.c
index 15165f8d..7b8d7af6 100644
--- a/MdePkg/Library/BaseLib/Ia32/FxSave.c
+++ b/MdePkg/Library/BaseLib/Ia32/FxSave.c
@@ -6,10 +6,8 @@
**/
-
#include "BaseLibInternals.h"
-
/**
Save the current floating point/SSE/SSE2 context to a buffer.
@@ -23,7 +21,7 @@
VOID
EFIAPI
InternalX86FxSave (
- OUT IA32_FX_BUFFER *Buffer
+ OUT IA32_FX_BUFFER *Buffer
)
{
_asm {
@@ -31,4 +29,3 @@ InternalX86FxSave (
fxsave [eax]
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/GccInline.c b/MdePkg/Library/BaseLib/Ia32/GccInline.c
index 5bf3e42c..2ff17838 100644
--- a/MdePkg/Library/BaseLib/Ia32/GccInline.c
+++ b/MdePkg/Library/BaseLib/Ia32/GccInline.c
@@ -7,7 +7,6 @@
**/
-
#include "BaseLibInternals.h"
/**
@@ -77,13 +76,13 @@ AsmReadEflags (
VOID
)
{
- UINTN Eflags;
+ UINTN Eflags;
__asm__ __volatile__ (
"pushfl \n\t"
"popl %0 "
: "=r" (Eflags)
- );
+ );
return Eflags;
}
@@ -101,17 +100,16 @@ AsmReadEflags (
VOID
EFIAPI
InternalX86FxSave (
- OUT IA32_FX_BUFFER *Buffer
+ OUT IA32_FX_BUFFER *Buffer
)
{
__asm__ __volatile__ (
"fxsave %0"
:
: "m" (*Buffer) // %0
- );
+ );
}
-
/**
Restores the current floating point/SSE/SSE2 context from a buffer.
@@ -125,17 +123,16 @@ InternalX86FxSave (
VOID
EFIAPI
InternalX86FxRestore (
- IN CONST IA32_FX_BUFFER *Buffer
+ IN CONST IA32_FX_BUFFER *Buffer
)
{
__asm__ __volatile__ (
"fxrstor %0"
:
: "m" (*Buffer) // %0
- );
+ );
}
-
/**
Reads the current value of 64-bit MMX Register #0 (MM0).
@@ -160,12 +157,11 @@ AsmReadMm0 (
"pop %%eax \n\t"
"pop %%edx \n\t"
: "=A" (Data) // %0
- );
+ );
return Data;
}
-
/**
Reads the current value of 64-bit MMX Register #1 (MM1).
@@ -190,12 +186,11 @@ AsmReadMm1 (
"pop %%eax \n\t"
"pop %%edx \n\t"
: "=A" (Data) // %0
- );
+ );
return Data;
}
-
/**
Reads the current value of 64-bit MMX Register #2 (MM2).
@@ -220,12 +215,11 @@ AsmReadMm2 (
"pop %%eax \n\t"
"pop %%edx \n\t"
: "=A" (Data) // %0
- );
+ );
return Data;
}
-
/**
Reads the current value of 64-bit MMX Register #3 (MM3).
@@ -250,12 +244,11 @@ AsmReadMm3 (
"pop %%eax \n\t"
"pop %%edx \n\t"
: "=A" (Data) // %0
- );
+ );
return Data;
}
-
/**
Reads the current value of 64-bit MMX Register #4 (MM4).
@@ -280,12 +273,11 @@ AsmReadMm4 (
"pop %%eax \n\t"
"pop %%edx \n\t"
: "=A" (Data) // %0
- );
+ );
return Data;
}
-
/**
Reads the current value of 64-bit MMX Register #5 (MM5).
@@ -310,12 +302,11 @@ AsmReadMm5 (
"pop %%eax \n\t"
"pop %%edx \n\t"
: "=A" (Data) // %0
- );
+ );
return Data;
}
-
/**
Reads the current value of 64-bit MMX Register #6 (MM6).
@@ -340,12 +331,11 @@ AsmReadMm6 (
"pop %%eax \n\t"
"pop %%edx \n\t"
: "=A" (Data) // %0
- );
+ );
return Data;
}
-
/**
Reads the current value of 64-bit MMX Register #7 (MM7).
@@ -370,12 +360,11 @@ AsmReadMm7 (
"pop %%eax \n\t"
"pop %%edx \n\t"
: "=A" (Data) // %0
- );
+ );
return Data;
}
-
/**
Writes the current value of 64-bit MMX Register #0 (MM0).
@@ -388,17 +377,16 @@ AsmReadMm7 (
VOID
EFIAPI
AsmWriteMm0 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
__asm__ __volatile__ (
"movq %0, %%mm0" // %0
:
: "m" (Value)
- );
+ );
}
-
/**
Writes the current value of 64-bit MMX Register #1 (MM1).
@@ -411,17 +399,16 @@ AsmWriteMm0 (
VOID
EFIAPI
AsmWriteMm1 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
__asm__ __volatile__ (
"movq %0, %%mm1" // %0
:
: "m" (Value)
- );
+ );
}
-
/**
Writes the current value of 64-bit MMX Register #2 (MM2).
@@ -434,17 +421,16 @@ AsmWriteMm1 (
VOID
EFIAPI
AsmWriteMm2 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
__asm__ __volatile__ (
"movq %0, %%mm2" // %0
:
: "m" (Value)
- );
+ );
}
-
/**
Writes the current value of 64-bit MMX Register #3 (MM3).
@@ -457,17 +443,16 @@ AsmWriteMm2 (
VOID
EFIAPI
AsmWriteMm3 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
__asm__ __volatile__ (
"movq %0, %%mm3" // %0
:
: "m" (Value)
- );
+ );
}
-
/**
Writes the current value of 64-bit MMX Register #4 (MM4).
@@ -480,17 +465,16 @@ AsmWriteMm3 (
VOID
EFIAPI
AsmWriteMm4 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
__asm__ __volatile__ (
"movq %0, %%mm4" // %0
:
: "m" (Value)
- );
+ );
}
-
/**
Writes the current value of 64-bit MMX Register #5 (MM5).
@@ -503,17 +487,16 @@ AsmWriteMm4 (
VOID
EFIAPI
AsmWriteMm5 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
__asm__ __volatile__ (
"movq %0, %%mm5" // %0
:
: "m" (Value)
- );
+ );
}
-
/**
Writes the current value of 64-bit MMX Register #6 (MM6).
@@ -526,17 +509,16 @@ AsmWriteMm5 (
VOID
EFIAPI
AsmWriteMm6 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
__asm__ __volatile__ (
"movq %0, %%mm6" // %0
:
: "m" (Value)
- );
+ );
}
-
/**
Writes the current value of 64-bit MMX Register #7 (MM7).
@@ -549,17 +531,16 @@ AsmWriteMm6 (
VOID
EFIAPI
AsmWriteMm7 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
__asm__ __volatile__ (
"movq %0, %%mm7" // %0
:
: "m" (Value)
- );
+ );
}
-
/**
Reads the current value of Time Stamp Counter (TSC).
@@ -580,7 +561,7 @@ AsmReadTsc (
__asm__ __volatile__ (
"rdtsc"
: "=A" (Data)
- );
+ );
return Data;
}
diff --git a/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c b/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c
index 7cf86f0a..bb144502 100644
--- a/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c
+++ b/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c
@@ -8,7 +8,6 @@
**/
-
#include "BaseLibInternals.h"
#include
@@ -27,7 +26,6 @@ EnableInterrupts (
__asm__ __volatile__ ("sti"::: "memory");
}
-
/**
Disables CPU interrupts.
@@ -60,11 +58,11 @@ DisableInterrupts (
UINT64
EFIAPI
AsmReadMsr64 (
- IN UINT32 Index
+ IN UINT32 Index
)
{
- UINT64 Data;
- BOOLEAN Flag;
+ UINT64 Data;
+ BOOLEAN Flag;
Flag = FilterBeforeMsrRead (Index, &Data);
if (Flag) {
@@ -72,8 +70,9 @@ AsmReadMsr64 (
"rdmsr"
: "=A" (Data) // %0
: "c" (Index) // %1
- );
+ );
}
+
FilterAfterMsrRead (Index, &Data);
return Data;
@@ -99,8 +98,8 @@ AsmReadMsr64 (
UINT64
EFIAPI
AsmWriteMsr64 (
- IN UINT32 Index,
- IN UINT64 Value
+ IN UINT32 Index,
+ IN UINT64 Value
)
{
BOOLEAN Flag;
@@ -112,8 +111,9 @@ AsmWriteMsr64 (
:
: "c" (Index),
"A" (Value)
- );
+ );
}
+
FilterAfterMsrWrite (Index, &Value);
return Value;
@@ -135,17 +135,16 @@ AsmReadCr0 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"movl %%cr0,%0"
: "=a" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of the Control Register 2 (CR2).
@@ -162,12 +161,12 @@ AsmReadCr2 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"movl %%cr2, %0"
: "=r" (Data)
- );
+ );
return Data;
}
@@ -188,17 +187,16 @@ AsmReadCr3 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"movl %%cr3, %0"
: "=r" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of the Control Register 4 (CR4).
@@ -215,17 +213,16 @@ AsmReadCr4 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"movl %%cr4, %0"
: "=a" (Data)
- );
+ );
return Data;
}
-
/**
Writes a value to Control Register 0 (CR0).
@@ -247,11 +244,10 @@ AsmWriteCr0 (
"movl %0, %%cr0"
:
: "r" (Cr0)
- );
+ );
return Cr0;
}
-
/**
Writes a value to Control Register 2 (CR2).
@@ -273,11 +269,10 @@ AsmWriteCr2 (
"movl %0, %%cr2"
:
: "r" (Cr2)
- );
+ );
return Cr2;
}
-
/**
Writes a value to Control Register 3 (CR3).
@@ -299,11 +294,10 @@ AsmWriteCr3 (
"movl %0, %%cr3"
:
: "r" (Cr3)
- );
+ );
return Cr3;
}
-
/**
Writes a value to Control Register 4 (CR4).
@@ -325,11 +319,10 @@ AsmWriteCr4 (
"movl %0, %%cr4"
:
: "r" (Cr4)
- );
+ );
return Cr4;
}
-
/**
Reads the current value of Debug Register 0 (DR0).
@@ -346,17 +339,16 @@ AsmReadDr0 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"movl %%dr0, %0"
: "=r" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of Debug Register 1 (DR1).
@@ -373,17 +365,16 @@ AsmReadDr1 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"movl %%dr1, %0"
: "=r" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of Debug Register 2 (DR2).
@@ -400,17 +391,16 @@ AsmReadDr2 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"movl %%dr2, %0"
: "=r" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of Debug Register 3 (DR3).
@@ -427,17 +417,16 @@ AsmReadDr3 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"movl %%dr3, %0"
: "=r" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of Debug Register 4 (DR4).
@@ -454,17 +443,16 @@ AsmReadDr4 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"movl %%dr4, %0"
: "=r" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of Debug Register 5 (DR5).
@@ -481,17 +469,16 @@ AsmReadDr5 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"movl %%dr5, %0"
: "=r" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of Debug Register 6 (DR6).
@@ -508,17 +495,16 @@ AsmReadDr6 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"movl %%dr6, %0"
: "=r" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of Debug Register 7 (DR7).
@@ -535,17 +521,16 @@ AsmReadDr7 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"movl %%dr7, %0"
: "=r" (Data)
- );
+ );
return Data;
}
-
/**
Writes a value to Debug Register 0 (DR0).
@@ -567,11 +552,10 @@ AsmWriteDr0 (
"movl %0, %%dr0"
:
: "r" (Dr0)
- );
+ );
return Dr0;
}
-
/**
Writes a value to Debug Register 1 (DR1).
@@ -593,11 +577,10 @@ AsmWriteDr1 (
"movl %0, %%dr1"
:
: "r" (Dr1)
- );
+ );
return Dr1;
}
-
/**
Writes a value to Debug Register 2 (DR2).
@@ -619,11 +602,10 @@ AsmWriteDr2 (
"movl %0, %%dr2"
:
: "r" (Dr2)
- );
+ );
return Dr2;
}
-
/**
Writes a value to Debug Register 3 (DR3).
@@ -645,11 +627,10 @@ AsmWriteDr3 (
"movl %0, %%dr3"
:
: "r" (Dr3)
- );
+ );
return Dr3;
}
-
/**
Writes a value to Debug Register 4 (DR4).
@@ -671,11 +652,10 @@ AsmWriteDr4 (
"movl %0, %%dr4"
:
: "r" (Dr4)
- );
+ );
return Dr4;
}
-
/**
Writes a value to Debug Register 5 (DR5).
@@ -697,11 +677,10 @@ AsmWriteDr5 (
"movl %0, %%dr5"
:
: "r" (Dr5)
- );
+ );
return Dr5;
}
-
/**
Writes a value to Debug Register 6 (DR6).
@@ -723,11 +702,10 @@ AsmWriteDr6 (
"movl %0, %%dr6"
:
: "r" (Dr6)
- );
+ );
return Dr6;
}
-
/**
Writes a value to Debug Register 7 (DR7).
@@ -749,11 +727,10 @@ AsmWriteDr7 (
"movl %0, %%dr7"
:
: "r" (Dr7)
- );
+ );
return Dr7;
}
-
/**
Reads the current value of Code Segment Register (CS).
@@ -774,12 +751,11 @@ AsmReadCs (
__asm__ __volatile__ (
"mov %%cs, %0"
:"=a" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of Data Segment Register (DS).
@@ -800,12 +776,11 @@ AsmReadDs (
__asm__ __volatile__ (
"mov %%ds, %0"
:"=a" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of Extra Segment Register (ES).
@@ -826,12 +801,11 @@ AsmReadEs (
__asm__ __volatile__ (
"mov %%es, %0"
:"=a" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of FS Data Segment Register (FS).
@@ -852,12 +826,11 @@ AsmReadFs (
__asm__ __volatile__ (
"mov %%fs, %0"
:"=a" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of GS Data Segment Register (GS).
@@ -878,12 +851,11 @@ AsmReadGs (
__asm__ __volatile__ (
"mov %%gs, %0"
:"=a" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of Stack Segment Register (SS).
@@ -904,12 +876,11 @@ AsmReadSs (
__asm__ __volatile__ (
"mov %%ss, %0"
:"=a" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of Task Register (TR).
@@ -930,12 +901,11 @@ AsmReadTr (
__asm__ __volatile__ (
"str %0"
: "=a" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current Global Descriptor Table Register(GDTR) descriptor.
@@ -948,16 +918,15 @@ AsmReadTr (
VOID
EFIAPI
InternalX86ReadGdtr (
- OUT IA32_DESCRIPTOR *Gdtr
+ OUT IA32_DESCRIPTOR *Gdtr
)
{
__asm__ __volatile__ (
"sgdt %0"
: "=m" (*Gdtr)
- );
+ );
}
-
/**
Writes the current Global Descriptor Table Register (GDTR) descriptor.
@@ -970,18 +939,16 @@ InternalX86ReadGdtr (
VOID
EFIAPI
InternalX86WriteGdtr (
- IN CONST IA32_DESCRIPTOR *Gdtr
+ IN CONST IA32_DESCRIPTOR *Gdtr
)
{
__asm__ __volatile__ (
"lgdt %0"
:
: "m" (*Gdtr)
- );
-
+ );
}
-
/**
Reads the current Interrupt Descriptor Table Register(GDTR) descriptor.
@@ -994,16 +961,15 @@ InternalX86WriteGdtr (
VOID
EFIAPI
InternalX86ReadIdtr (
- OUT IA32_DESCRIPTOR *Idtr
+ OUT IA32_DESCRIPTOR *Idtr
)
{
__asm__ __volatile__ (
"sidt %0"
: "=m" (*Idtr)
- );
+ );
}
-
/**
Writes the current Interrupt Descriptor Table Register(GDTR) descriptor.
@@ -1016,17 +982,16 @@ InternalX86ReadIdtr (
VOID
EFIAPI
InternalX86WriteIdtr (
- IN CONST IA32_DESCRIPTOR *Idtr
+ IN CONST IA32_DESCRIPTOR *Idtr
)
{
__asm__ __volatile__ (
"lidt %0"
:
: "m" (*Idtr)
- );
+ );
}
-
/**
Reads the current Local Descriptor Table Register(LDTR) selector.
@@ -1047,12 +1012,11 @@ AsmReadLdtr (
__asm__ __volatile__ (
"sldt %0"
: "=g" (Data) // %0
- );
+ );
return Data;
}
-
/**
Writes the current Local Descriptor Table Register (GDTR) selector.
@@ -1065,14 +1029,14 @@ AsmReadLdtr (
VOID
EFIAPI
AsmWriteLdtr (
- IN UINT16 Ldtr
+ IN UINT16 Ldtr
)
{
__asm__ __volatile__ (
"lldtw %0"
:
: "g" (Ldtr) // %0
- );
+ );
}
/**
@@ -1089,7 +1053,7 @@ AsmWriteLdtr (
UINT64
EFIAPI
AsmReadPmc (
- IN UINT32 Index
+ IN UINT32 Index
)
{
UINT64 Data;
@@ -1098,7 +1062,7 @@ AsmReadPmc (
"rdpmc"
: "=A" (Data)
: "c" (Index)
- );
+ );
return Data;
}
@@ -1133,10 +1097,8 @@ AsmInvd (
)
{
__asm__ __volatile__ ("invd":::"memory");
-
}
-
/**
Flushes a cache line from all the instruction and data caches within the
coherency domain of the CPU.
@@ -1155,7 +1117,7 @@ AsmInvd (
VOID *
EFIAPI
AsmFlushCacheLine (
- IN VOID *LinearAddress
+ IN VOID *LinearAddress
)
{
UINT32 RegEdx;
@@ -1170,13 +1132,12 @@ AsmFlushCacheLine (
return LinearAddress;
}
-
__asm__ __volatile__ (
"clflush (%0)"
: "+a" (LinearAddress)
:
: "memory"
- );
+ );
return LinearAddress;
}
diff --git a/MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.c b/MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.c
index 8e69e773..c6845207 100644
--- a/MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.c
+++ b/MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.c
@@ -36,19 +36,19 @@ VOID
EFIAPI
InternalSwitchStack (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
- IN VOID *Context1, OPTIONAL
- IN VOID *Context2, OPTIONAL
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL,
IN VOID *NewStack,
IN VA_LIST Marker
)
{
BASE_LIBRARY_JUMP_BUFFER JumpBuffer;
- JumpBuffer.Eip = (UINTN)EntryPoint;
- JumpBuffer.Esp = (UINTN)NewStack - sizeof (VOID*);
- JumpBuffer.Esp -= sizeof (Context1) + sizeof (Context2);
- ((VOID**)JumpBuffer.Esp)[1] = Context1;
- ((VOID**)JumpBuffer.Esp)[2] = Context2;
+ JumpBuffer.Eip = (UINTN)EntryPoint;
+ JumpBuffer.Esp = (UINTN)NewStack - sizeof (VOID *);
+ JumpBuffer.Esp -= sizeof (Context1) + sizeof (Context2);
+ ((VOID **)JumpBuffer.Esp)[1] = Context1;
+ ((VOID **)JumpBuffer.Esp)[2] = Context2;
LongJump (&JumpBuffer, (UINTN)-1);
}
diff --git a/MdePkg/Library/BaseLib/Ia32/Invd.c b/MdePkg/Library/BaseLib/Ia32/Invd.c
index 25cd96e8..a14d973b 100644
--- a/MdePkg/Library/BaseLib/Ia32/Invd.c
+++ b/MdePkg/Library/BaseLib/Ia32/Invd.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Executes a INVD instruction.
@@ -26,4 +23,3 @@ AsmInvd (
invd
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/LRotU64.c b/MdePkg/Library/BaseLib/Ia32/LRotU64.c
index eb232fdb..5f646a55 100644
--- a/MdePkg/Library/BaseLib/Ia32/LRotU64.c
+++ b/MdePkg/Library/BaseLib/Ia32/LRotU64.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Rotates a 64-bit integer left between 0 and 63 bits, filling
the low bits with the high bits that were rotated.
@@ -26,8 +23,8 @@
UINT64
EFIAPI
InternalMathLRotU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
)
{
_asm {
@@ -43,7 +40,6 @@ InternalMathLRotU64 (
mov ecx, eax
mov eax, edx
mov edx, ecx
-L0:
+ L0 :
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/LShiftU64.c b/MdePkg/Library/BaseLib/Ia32/LShiftU64.c
index a3d5299e..deef4081 100644
--- a/MdePkg/Library/BaseLib/Ia32/LShiftU64.c
+++ b/MdePkg/Library/BaseLib/Ia32/LShiftU64.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Shifts a 64-bit integer left between 0 and 63 bits. The low bits
are filled with zeros. The shifted value is returned.
@@ -25,8 +22,8 @@
UINT64
EFIAPI
InternalMathLShiftU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
)
{
_asm {
@@ -42,4 +39,3 @@ L0:
shl eax, cl
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/LongJump.nasm b/MdePkg/Library/BaseLib/Ia32/LongJump.nasm
index 8b14afdd..c8c5ab83 100644
--- a/MdePkg/Library/BaseLib/Ia32/LongJump.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/LongJump.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
diff --git a/MdePkg/Library/BaseLib/Ia32/ModU64x32.c b/MdePkg/Library/BaseLib/Ia32/ModU64x32.c
index 8a5e2830..2f9ad0a9 100644
--- a/MdePkg/Library/BaseLib/Ia32/ModU64x32.c
+++ b/MdePkg/Library/BaseLib/Ia32/ModU64x32.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Divides a 64-bit unsigned integer by a 32-bit unsigned integer and
generates a 32-bit unsigned remainder.
@@ -26,8 +23,8 @@
UINT32
EFIAPI
InternalMathModU64x32 (
- IN UINT64 Dividend,
- IN UINT32 Divisor
+ IN UINT64 Dividend,
+ IN UINT32 Divisor
)
{
_asm {
diff --git a/MdePkg/Library/BaseLib/Ia32/Monitor.c b/MdePkg/Library/BaseLib/Ia32/Monitor.c
index 0469986e..fdd27b8c 100644
--- a/MdePkg/Library/BaseLib/Ia32/Monitor.c
+++ b/MdePkg/Library/BaseLib/Ia32/Monitor.c
@@ -25,9 +25,9 @@
UINTN
EFIAPI
AsmMonitor (
- IN UINTN RegisterEax,
- IN UINTN RegisterEcx,
- IN UINTN RegisterEdx
+ IN UINTN RegisterEax,
+ IN UINTN RegisterEcx,
+ IN UINTN RegisterEdx
)
{
_asm {
@@ -39,4 +39,3 @@ AsmMonitor (
_emit 0xc8
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/Monitor.nasm b/MdePkg/Library/BaseLib/Ia32/Monitor.nasm
index bde62d2e..af11808c 100644
--- a/MdePkg/Library/BaseLib/Ia32/Monitor.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/Monitor.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -31,6 +31,6 @@ ASM_PFX(AsmMonitor):
mov eax, [esp + 4]
mov ecx, [esp + 8]
mov edx, [esp + 12]
- DB 0xf, 1, 0xc8 ; monitor
+ monitor
ret
diff --git a/MdePkg/Library/BaseLib/Ia32/MultU64x32.c b/MdePkg/Library/BaseLib/Ia32/MultU64x32.c
index 9e2944e0..dc94eba7 100644
--- a/MdePkg/Library/BaseLib/Ia32/MultU64x32.c
+++ b/MdePkg/Library/BaseLib/Ia32/MultU64x32.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Multiples a 64-bit unsigned integer by a 32-bit unsigned integer
and generates a 64-bit unsigned result.
@@ -26,8 +23,8 @@
UINT64
EFIAPI
InternalMathMultU64x32 (
- IN UINT64 Multiplicand,
- IN UINT32 Multiplier
+ IN UINT64 Multiplicand,
+ IN UINT32 Multiplier
)
{
_asm {
@@ -38,4 +35,3 @@ InternalMathMultU64x32 (
add edx, ecx
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/MultU64x64.c b/MdePkg/Library/BaseLib/Ia32/MultU64x64.c
index 1ee9bbc3..16f568cc 100644
--- a/MdePkg/Library/BaseLib/Ia32/MultU64x64.c
+++ b/MdePkg/Library/BaseLib/Ia32/MultU64x64.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Multiplies a 64-bit unsigned integer by a 64-bit unsigned integer
and generates a 64-bit unsigned result.
@@ -26,8 +23,8 @@
UINT64
EFIAPI
InternalMathMultU64x64 (
- IN UINT64 Multiplicand,
- IN UINT64 Multiplier
+ IN UINT64 Multiplicand,
+ IN UINT64 Multiplier
)
{
_asm {
@@ -42,4 +39,3 @@ InternalMathMultU64x64 (
add edx, ebx
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/Mwait.c b/MdePkg/Library/BaseLib/Ia32/Mwait.c
index f1e89652..468bd4e7 100644
--- a/MdePkg/Library/BaseLib/Ia32/Mwait.c
+++ b/MdePkg/Library/BaseLib/Ia32/Mwait.c
@@ -23,8 +23,8 @@
UINTN
EFIAPI
AsmMwait (
- IN UINTN RegisterEax,
- IN UINTN RegisterEcx
+ IN UINTN RegisterEax,
+ IN UINTN RegisterEcx
)
{
_asm {
@@ -35,4 +35,3 @@ AsmMwait (
_emit 0xC9
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/Mwait.nasm b/MdePkg/Library/BaseLib/Ia32/Mwait.nasm
index ca0d96a6..490222a9 100644
--- a/MdePkg/Library/BaseLib/Ia32/Mwait.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/Mwait.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -29,6 +29,6 @@ global ASM_PFX(AsmMwait)
ASM_PFX(AsmMwait):
mov eax, [esp + 4]
mov ecx, [esp + 8]
- DB 0xf, 1, 0xc9 ; mwait
+ mwait
ret
diff --git a/MdePkg/Library/BaseLib/Ia32/Non-existing.c b/MdePkg/Library/BaseLib/Ia32/Non-existing.c
index 2669ce55..98f6d753 100644
--- a/MdePkg/Library/BaseLib/Ia32/Non-existing.c
+++ b/MdePkg/Library/BaseLib/Ia32/Non-existing.c
@@ -37,11 +37,11 @@
VOID
EFIAPI
InternalX86DisablePaging64 (
- IN UINT16 CodeSelector,
- IN UINT32 EntryPoint,
- IN UINT32 Context1, OPTIONAL
- IN UINT32 Context2, OPTIONAL
- IN UINT32 NewStack
+ IN UINT16 CodeSelector,
+ IN UINT32 EntryPoint,
+ IN UINT32 Context1 OPTIONAL,
+ IN UINT32 Context2 OPTIONAL,
+ IN UINT32 NewStack
)
{
//
diff --git a/MdePkg/Library/BaseLib/Ia32/RRotU64.c b/MdePkg/Library/BaseLib/Ia32/RRotU64.c
index 9d928dc2..844afd5d 100644
--- a/MdePkg/Library/BaseLib/Ia32/RRotU64.c
+++ b/MdePkg/Library/BaseLib/Ia32/RRotU64.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Rotates a 64-bit integer right between 0 and 63 bits, filling
the high bits with the high low bits that were rotated.
@@ -26,8 +23,8 @@
UINT64
EFIAPI
InternalMathRRotU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
)
{
_asm {
@@ -46,4 +43,3 @@ InternalMathRRotU64 (
L0:
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/RShiftU64.c b/MdePkg/Library/BaseLib/Ia32/RShiftU64.c
index 1c5d2f04..39ffb527 100644
--- a/MdePkg/Library/BaseLib/Ia32/RShiftU64.c
+++ b/MdePkg/Library/BaseLib/Ia32/RShiftU64.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Shifts a 64-bit integer right between 0 and 63 bits. This high bits
are filled with zeros. The shifted value is returned.
@@ -25,8 +22,8 @@
UINT64
EFIAPI
InternalMathRShiftU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
)
{
_asm {
@@ -42,4 +39,3 @@ L0:
shr edx, cl
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/RdRand.nasm b/MdePkg/Library/BaseLib/Ia32/RdRand.nasm
index d31ae03d..92089892 100644
--- a/MdePkg/Library/BaseLib/Ia32/RdRand.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/RdRand.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -25,9 +25,8 @@ SECTION .text
;------------------------------------------------------------------------------
global ASM_PFX(InternalX86RdRand16)
ASM_PFX(InternalX86RdRand16):
- ; rdrand ax ; generate a 16 bit RN into ax
+ rdrand eax ; generate a 16 bit RN into ax
; CF=1 if RN generated ok, otherwise CF=0
- db 0xf, 0xc7, 0xf0 ; rdrand r16: "0f c7 /6 ModRM:r/m(w)"
jc rn16_ok ; jmp if CF=1
xor eax, eax ; reg=0 if CF=0
ret ; return with failure status
@@ -45,9 +44,8 @@ rn16_ok:
;------------------------------------------------------------------------------
global ASM_PFX(InternalX86RdRand32)
ASM_PFX(InternalX86RdRand32):
- ; rdrand eax ; generate a 32 bit RN into eax
+ rdrand eax ; generate a 32 bit RN into eax
; CF=1 if RN generated ok, otherwise CF=0
- db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6 ModRM:r/m(w)"
jc rn32_ok ; jmp if CF=1
xor eax, eax ; reg=0 if CF=0
ret ; return with failure status
@@ -65,14 +63,13 @@ rn32_ok:
;------------------------------------------------------------------------------
global ASM_PFX(InternalX86RdRand64)
ASM_PFX(InternalX86RdRand64):
- ; rdrand eax ; generate a 32 bit RN into eax
+ rdrand eax ; generate a 32 bit RN into eax
; CF=1 if RN generated ok, otherwise CF=0
- db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6 ModRM:r/m(w)"
jnc rn64_ret ; jmp if CF=0
mov edx, dword [esp + 4]
mov [edx], eax
- db 0xf, 0xc7, 0xf0 ; generate another 32 bit RN
+ rdrand eax ; generate another 32 bit RN
jnc rn64_ret ; jmp if CF=0
mov [edx + 4], eax
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadCr0.c b/MdePkg/Library/BaseLib/Ia32/ReadCr0.c
index e7f25b32..0a83640d 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadCr0.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadCr0.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of the Control Register 0 (CR0).
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadCr2.c b/MdePkg/Library/BaseLib/Ia32/ReadCr2.c
index 64b3dc34..ebc30021 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadCr2.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadCr2.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of the Control Register 2 (CR2).
@@ -29,4 +26,3 @@ AsmReadCr2 (
mov eax, cr2
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadCr3.c b/MdePkg/Library/BaseLib/Ia32/ReadCr3.c
index 2b9f1a52..6e950db1 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadCr3.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadCr3.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of the Control Register 3 (CR3).
@@ -29,4 +26,3 @@ AsmReadCr3 (
mov eax, cr3
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadCr4.c b/MdePkg/Library/BaseLib/Ia32/ReadCr4.c
index d710630b..c22a145e 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadCr4.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadCr4.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of the Control Register 4 (CR4).
@@ -31,4 +28,3 @@ AsmReadCr4 (
_emit 0xE0
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadCs.c b/MdePkg/Library/BaseLib/Ia32/ReadCs.c
index ac63518c..d2fbaab3 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadCs.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadCs.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of Code Segment Register (CS).
@@ -29,4 +26,3 @@ AsmReadCs (
mov ax, cs
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadDr0.c b/MdePkg/Library/BaseLib/Ia32/ReadDr0.c
index 2cbb3a21..8a0f2ccd 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadDr0.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadDr0.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of Debug Register 0 (DR0).
@@ -29,4 +26,3 @@ AsmReadDr0 (
mov eax, dr0
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadDr1.c b/MdePkg/Library/BaseLib/Ia32/ReadDr1.c
index dd1e2c39..8657c3d8 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadDr1.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadDr1.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of Debug Register 1 (DR1).
@@ -29,4 +26,3 @@ AsmReadDr1 (
mov eax, dr1
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadDr2.c b/MdePkg/Library/BaseLib/Ia32/ReadDr2.c
index 5c0e1504..2f4c4256 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadDr2.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadDr2.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of Debug Register 2 (DR2).
@@ -29,4 +26,3 @@ AsmReadDr2 (
mov eax, dr2
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadDr3.c b/MdePkg/Library/BaseLib/Ia32/ReadDr3.c
index 8fbda7ac..d70c517c 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadDr3.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadDr3.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of Debug Register 3 (DR3).
@@ -29,4 +26,3 @@ AsmReadDr3 (
mov eax, dr3
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadDr4.c b/MdePkg/Library/BaseLib/Ia32/ReadDr4.c
index 6ce200a1..72ed1059 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadDr4.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadDr4.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of Debug Register 4 (DR4).
@@ -31,4 +28,3 @@ AsmReadDr4 (
_emit 0xe0
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm b/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm
index 36a90133..3940e656 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -31,8 +31,8 @@ ASM_PFX(AsmReadDr4):
; this register will cause a #UD exception.
;
; MS assembler doesn't support this instruction since no one would use it
- ; under normal circustances. Here opcode is used.
+ ; under normal circustances.
;
- DB 0xf, 0x21, 0xe0
+ mov eax, dr4
ret
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadDr5.c b/MdePkg/Library/BaseLib/Ia32/ReadDr5.c
index 70330274..8ee27389 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadDr5.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadDr5.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of Debug Register 5 (DR5).
@@ -31,4 +28,3 @@ AsmReadDr5 (
_emit 0xe8
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm b/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm
index dd7666cd..cc5ec9a4 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -31,8 +31,8 @@ ASM_PFX(AsmReadDr5):
; this register will cause a #UD exception.
;
; MS assembler doesn't support this instruction since no one would use it
- ; under normal circustances. Here opcode is used.
+ ; under normal circustances.
;
- DB 0xf, 0x21, 0xe8
+ mov eax, dr5
ret
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadDr6.c b/MdePkg/Library/BaseLib/Ia32/ReadDr6.c
index 851daee0..bf8b69e6 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadDr6.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadDr6.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of Debug Register 6 (DR6).
@@ -29,4 +26,3 @@ AsmReadDr6 (
mov eax, dr6
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadDr7.c b/MdePkg/Library/BaseLib/Ia32/ReadDr7.c
index 344a41e8..eda5f82f 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadDr7.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadDr7.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of Debug Register 7 (DR7).
@@ -29,4 +26,3 @@ AsmReadDr7 (
mov eax, dr7
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadDs.c b/MdePkg/Library/BaseLib/Ia32/ReadDs.c
index 1b9823c7..47aa4620 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadDs.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadDs.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of Data Segment Register (DS).
@@ -29,4 +26,3 @@ AsmReadDs (
mov ax, ds
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadEflags.c b/MdePkg/Library/BaseLib/Ia32/ReadEflags.c
index 12c57d2d..cd11588e 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadEflags.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadEflags.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of the EFLAGS register.
@@ -30,4 +27,3 @@ AsmReadEflags (
pop eax
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadEs.c b/MdePkg/Library/BaseLib/Ia32/ReadEs.c
index 760cd47b..520cba92 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadEs.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadEs.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of ES Data Segment Register (ES).
@@ -29,4 +26,3 @@ AsmReadEs (
mov ax, es
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadFs.c b/MdePkg/Library/BaseLib/Ia32/ReadFs.c
index 9cd7af73..33ae2e5e 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadFs.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadFs.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of FS Data Segment Register (FS).
@@ -29,4 +26,3 @@ AsmReadFs (
mov ax, fs
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadGdtr.c b/MdePkg/Library/BaseLib/Ia32/ReadGdtr.c
index 10da346e..fdd2ccd1 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadGdtr.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadGdtr.c
@@ -6,10 +6,8 @@
**/
-
#include "BaseLibInternals.h"
-
/**
Reads the current Global Descriptor Table Register(GDTR) descriptor.
@@ -30,4 +28,3 @@ InternalX86ReadGdtr (
sgdt fword ptr [eax]
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadGs.c b/MdePkg/Library/BaseLib/Ia32/ReadGs.c
index 75f28142..149d250e 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadGs.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadGs.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of GS Data Segment Register (GS).
@@ -29,4 +26,3 @@ AsmReadGs (
mov ax, gs
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadIdtr.c b/MdePkg/Library/BaseLib/Ia32/ReadIdtr.c
index 3fcd8b5b..0dcd6d2a 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadIdtr.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadIdtr.c
@@ -6,10 +6,8 @@
**/
-
#include "BaseLibInternals.h"
-
/**
Reads the current Interrupt Descriptor Table Register(GDTR) descriptor.
@@ -22,7 +20,7 @@
VOID
EFIAPI
InternalX86ReadIdtr (
- OUT IA32_DESCRIPTOR *Idtr
+ OUT IA32_DESCRIPTOR *Idtr
)
{
_asm {
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadLdtr.c b/MdePkg/Library/BaseLib/Ia32/ReadLdtr.c
index 7575c290..049b22e9 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadLdtr.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadLdtr.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current Local Descriptor Table Register(LDTR) selector.
@@ -28,4 +25,3 @@ AsmReadLdtr (
sldt ax
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadMm0.c b/MdePkg/Library/BaseLib/Ia32/ReadMm0.c
index 590c4f4e..d5bf41c8 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadMm0.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadMm0.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of 64-bit MMX Register #0 (MM0).
@@ -33,4 +30,3 @@ AsmReadMm0 (
emms
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadMm1.c b/MdePkg/Library/BaseLib/Ia32/ReadMm1.c
index e161bce4..b0c4251f 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadMm1.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadMm1.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of 64-bit MMX Register #1 (MM1).
@@ -33,4 +30,3 @@ AsmReadMm1 (
emms
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadMm2.c b/MdePkg/Library/BaseLib/Ia32/ReadMm2.c
index 3681737e..a03315a6 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadMm2.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadMm2.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of 64-bit MMX Register #2 (MM2).
@@ -33,4 +30,3 @@ AsmReadMm2 (
emms
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadMm3.c b/MdePkg/Library/BaseLib/Ia32/ReadMm3.c
index 272d90e6..ada729e0 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadMm3.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadMm3.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of 64-bit MMX Register #3 (MM3).
@@ -33,4 +30,3 @@ AsmReadMm3 (
emms
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadMm4.c b/MdePkg/Library/BaseLib/Ia32/ReadMm4.c
index e6f8fb6d..60d6b27f 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadMm4.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadMm4.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of 64-bit MMX Register #4 (MM4).
@@ -33,4 +30,3 @@ AsmReadMm4 (
emms
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadMm5.c b/MdePkg/Library/BaseLib/Ia32/ReadMm5.c
index da583273..24d74d3d 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadMm5.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadMm5.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of 64-bit MMX Register #5 (MM5).
@@ -33,4 +30,3 @@ AsmReadMm5 (
emms
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadMm6.c b/MdePkg/Library/BaseLib/Ia32/ReadMm6.c
index cf738e3b..2ae0b074 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadMm6.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadMm6.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of 64-bit MMX Register #6 (MM6).
@@ -33,4 +30,3 @@ AsmReadMm6 (
emms
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadMm7.c b/MdePkg/Library/BaseLib/Ia32/ReadMm7.c
index c2430654..099dffbb 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadMm7.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadMm7.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of 64-bit MMX Register #7 (MM7).
@@ -33,4 +30,3 @@ AsmReadMm7 (
emms
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c b/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c
index f3f6b0f3..adbd92af 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c
@@ -6,7 +6,6 @@
**/
-
#include
/**
@@ -54,13 +53,14 @@ AsmReadMsr64 (
IN UINT32 Index
)
{
- UINT64 Value;
- BOOLEAN Flag;
+ UINT64 Value;
+ BOOLEAN Flag;
Flag = FilterBeforeMsrRead (Index, &Value);
if (Flag) {
Value = AsmReadMsr64Internal (Index);
}
+
FilterAfterMsrRead (Index, &Value);
return Value;
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadPmc.c b/MdePkg/Library/BaseLib/Ia32/ReadPmc.c
index a74d3132..f38eda6b 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadPmc.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadPmc.c
@@ -20,7 +20,7 @@
UINT64
EFIAPI
AsmReadPmc (
- IN UINT32 Index
+ IN UINT32 Index
)
{
_asm {
@@ -28,4 +28,3 @@ AsmReadPmc (
rdpmc
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadSs.c b/MdePkg/Library/BaseLib/Ia32/ReadSs.c
index 683ff39b..be1fba02 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadSs.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadSs.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of Stack Segment Register (SS).
@@ -29,4 +26,3 @@ AsmReadSs (
mov ax, ss
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadTr.c b/MdePkg/Library/BaseLib/Ia32/ReadTr.c
index b540b75c..74845358 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadTr.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadTr.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of Task Register (TR).
@@ -28,4 +25,3 @@ AsmReadTr (
str ax
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadTsc.c b/MdePkg/Library/BaseLib/Ia32/ReadTsc.c
index ae8649fe..dbecaff3 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadTsc.c
+++ b/MdePkg/Library/BaseLib/Ia32/ReadTsc.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Reads the current value of Time Stamp Counter (TSC).
@@ -28,4 +25,3 @@ AsmReadTsc (
rdtsc
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/SetJump.nasm b/MdePkg/Library/BaseLib/Ia32/SetJump.nasm
index be66237e..56c122e8 100644
--- a/MdePkg/Library/BaseLib/Ia32/SetJump.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/SetJump.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
diff --git a/MdePkg/Library/BaseLib/Ia32/SwapBytes64.c b/MdePkg/Library/BaseLib/Ia32/SwapBytes64.c
index 2f857a4d..9c1f34a6 100644
--- a/MdePkg/Library/BaseLib/Ia32/SwapBytes64.c
+++ b/MdePkg/Library/BaseLib/Ia32/SwapBytes64.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Switches the endianess of a 64-bit integer.
@@ -24,7 +21,7 @@
UINT64
EFIAPI
InternalMathSwapBytes64 (
- IN UINT64 Operand
+ IN UINT64 Operand
)
{
_asm {
@@ -34,4 +31,3 @@ InternalMathSwapBytes64 (
bswap edx
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/Wbinvd.c b/MdePkg/Library/BaseLib/Ia32/Wbinvd.c
index 92ff861d..d6a6582a 100644
--- a/MdePkg/Library/BaseLib/Ia32/Wbinvd.c
+++ b/MdePkg/Library/BaseLib/Ia32/Wbinvd.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Executes a WBINVD instruction.
@@ -26,4 +23,3 @@ AsmWbinvd (
wbinvd
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteCr0.c b/MdePkg/Library/BaseLib/Ia32/WriteCr0.c
index 5b4ef4d9..1b565afa 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteCr0.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteCr0.c
@@ -28,4 +28,3 @@ AsmWriteCr0 (
mov cr0, eax
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteCr2.c b/MdePkg/Library/BaseLib/Ia32/WriteCr2.c
index 89e8fd36..cd424891 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteCr2.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteCr2.c
@@ -28,4 +28,3 @@ AsmWriteCr2 (
mov cr2, eax
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteCr3.c b/MdePkg/Library/BaseLib/Ia32/WriteCr3.c
index c1ef6f96..df5c084c 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteCr3.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteCr3.c
@@ -28,4 +28,3 @@ AsmWriteCr3 (
mov cr3, eax
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteCr4.c b/MdePkg/Library/BaseLib/Ia32/WriteCr4.c
index 4343a1ac..d58536b9 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteCr4.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteCr4.c
@@ -30,4 +30,3 @@ AsmWriteCr4 (
_emit 0xE0
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteDr0.c b/MdePkg/Library/BaseLib/Ia32/WriteDr0.c
index c199c841..fcba6a1d 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteDr0.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteDr0.c
@@ -20,7 +20,7 @@
UINTN
EFIAPI
AsmWriteDr0 (
- IN UINTN Value
+ IN UINTN Value
)
{
_asm {
@@ -28,4 +28,3 @@ AsmWriteDr0 (
mov dr0, eax
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteDr1.c b/MdePkg/Library/BaseLib/Ia32/WriteDr1.c
index 361b14a6..134b3b1c 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteDr1.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteDr1.c
@@ -20,7 +20,7 @@
UINTN
EFIAPI
AsmWriteDr1 (
- IN UINTN Value
+ IN UINTN Value
)
{
_asm {
@@ -28,4 +28,3 @@ AsmWriteDr1 (
mov dr1, eax
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteDr2.c b/MdePkg/Library/BaseLib/Ia32/WriteDr2.c
index 2fb544a6..0e507c49 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteDr2.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteDr2.c
@@ -20,7 +20,7 @@
UINTN
EFIAPI
AsmWriteDr2 (
- IN UINTN Value
+ IN UINTN Value
)
{
_asm {
@@ -28,4 +28,3 @@ AsmWriteDr2 (
mov dr2, eax
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteDr3.c b/MdePkg/Library/BaseLib/Ia32/WriteDr3.c
index 4a74a63f..21420b43 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteDr3.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteDr3.c
@@ -20,7 +20,7 @@
UINTN
EFIAPI
AsmWriteDr3 (
- IN UINTN Value
+ IN UINTN Value
)
{
_asm {
@@ -28,4 +28,3 @@ AsmWriteDr3 (
mov dr3, eax
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteDr4.c b/MdePkg/Library/BaseLib/Ia32/WriteDr4.c
index c9f336e6..3c50d387 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteDr4.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteDr4.c
@@ -20,7 +20,7 @@
UINTN
EFIAPI
AsmWriteDr4 (
- IN UINTN Value
+ IN UINTN Value
)
{
_asm {
@@ -30,4 +30,3 @@ AsmWriteDr4 (
_emit 0xe0
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm b/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm
index 590effba..c04712f9 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -32,8 +32,8 @@ ASM_PFX(AsmWriteDr4):
; this register will cause a #UD exception.
;
; MS assembler doesn't support this instruction since no one would use it
- ; under normal circustances. Here opcode is used.
+ ; under normal circustances.
;
- DB 0xf, 0x23, 0xe0
+ mov dr4, eax
ret
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteDr5.c b/MdePkg/Library/BaseLib/Ia32/WriteDr5.c
index c2e0f404..01e1ceb7 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteDr5.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteDr5.c
@@ -20,7 +20,7 @@
UINTN
EFIAPI
AsmWriteDr5 (
- IN UINTN Value
+ IN UINTN Value
)
{
_asm {
@@ -30,4 +30,3 @@ AsmWriteDr5 (
_emit 0xe8
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm b/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm
index e1867df2..17c08175 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -32,8 +32,8 @@ ASM_PFX(AsmWriteDr5):
; this register will cause a #UD exception.
;
; MS assembler doesn't support this instruction since no one would use it
- ; under normal circustances. Here opcode is used.
+ ; under normal circustances.
;
- DB 0xf, 0x23, 0xe8
+ mov dr5, eax
ret
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteDr6.c b/MdePkg/Library/BaseLib/Ia32/WriteDr6.c
index 30e5cd60..337f1c98 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteDr6.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteDr6.c
@@ -20,7 +20,7 @@
UINTN
EFIAPI
AsmWriteDr6 (
- IN UINTN Value
+ IN UINTN Value
)
{
_asm {
@@ -28,4 +28,3 @@ AsmWriteDr6 (
mov dr6, eax
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteDr7.c b/MdePkg/Library/BaseLib/Ia32/WriteDr7.c
index fbbbd6b3..aeadce36 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteDr7.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteDr7.c
@@ -20,7 +20,7 @@
UINTN
EFIAPI
AsmWriteDr7 (
- IN UINTN Value
+ IN UINTN Value
)
{
_asm {
@@ -28,4 +28,3 @@ AsmWriteDr7 (
mov dr7, eax
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteGdtr.c b/MdePkg/Library/BaseLib/Ia32/WriteGdtr.c
index 68fc7643..27c687fb 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteGdtr.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteGdtr.c
@@ -6,10 +6,8 @@
**/
-
#include "BaseLibInternals.h"
-
/**
Writes the current Global Descriptor Table Register (GDTR) descriptor.
@@ -22,7 +20,7 @@
VOID
EFIAPI
InternalX86WriteGdtr (
- IN CONST IA32_DESCRIPTOR *Gdtr
+ IN CONST IA32_DESCRIPTOR *Gdtr
)
{
_asm {
@@ -30,4 +28,3 @@ InternalX86WriteGdtr (
lgdt fword ptr [eax]
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteIdtr.c b/MdePkg/Library/BaseLib/Ia32/WriteIdtr.c
index d498409c..ce0ad02c 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteIdtr.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteIdtr.c
@@ -6,7 +6,6 @@
**/
-
#include "BaseLibInternals.h"
/**
@@ -21,7 +20,7 @@
VOID
EFIAPI
InternalX86WriteIdtr (
- IN CONST IA32_DESCRIPTOR *Idtr
+ IN CONST IA32_DESCRIPTOR *Idtr
)
{
_asm {
@@ -32,4 +31,3 @@ InternalX86WriteIdtr (
popfd
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteLdtr.c b/MdePkg/Library/BaseLib/Ia32/WriteLdtr.c
index 779822c6..99394e5f 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteLdtr.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteLdtr.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Writes the current Local Descriptor Table Register (GDTR) selector.
@@ -21,7 +18,7 @@
VOID
EFIAPI
AsmWriteLdtr (
- IN UINT16 Ldtr
+ IN UINT16 Ldtr
)
{
_asm {
@@ -30,4 +27,3 @@ AsmWriteLdtr (
lldt ax
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteMm0.c b/MdePkg/Library/BaseLib/Ia32/WriteMm0.c
index b762aa25..5d50dc73 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteMm0.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteMm0.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Writes the current value of 64-bit MMX Register #0 (MM0).
@@ -21,7 +18,7 @@
VOID
EFIAPI
AsmWriteMm0 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
_asm {
@@ -29,4 +26,3 @@ AsmWriteMm0 (
emms
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteMm1.c b/MdePkg/Library/BaseLib/Ia32/WriteMm1.c
index 9e34d9f7..465d8c5a 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteMm1.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteMm1.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Writes the current value of 64-bit MMX Register #1 (MM1).
@@ -21,7 +18,7 @@
VOID
EFIAPI
AsmWriteMm1 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
_asm {
@@ -29,4 +26,3 @@ AsmWriteMm1 (
emms
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteMm2.c b/MdePkg/Library/BaseLib/Ia32/WriteMm2.c
index 85474434..b1f2eb28 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteMm2.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteMm2.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Writes the current value of 64-bit MMX Register #2 (MM2).
@@ -21,7 +18,7 @@
VOID
EFIAPI
AsmWriteMm2 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
_asm {
@@ -29,4 +26,3 @@ AsmWriteMm2 (
emms
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteMm3.c b/MdePkg/Library/BaseLib/Ia32/WriteMm3.c
index c059de73..60c3cdd3 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteMm3.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteMm3.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Writes the current value of 64-bit MMX Register #3 (MM3).
@@ -21,7 +18,7 @@
VOID
EFIAPI
AsmWriteMm3 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
_asm {
@@ -29,4 +26,3 @@ AsmWriteMm3 (
emms
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteMm4.c b/MdePkg/Library/BaseLib/Ia32/WriteMm4.c
index 99c180a5..f8e98078 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteMm4.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteMm4.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Writes the current value of 64-bit MMX Register #4 (MM4).
@@ -21,7 +18,7 @@
VOID
EFIAPI
AsmWriteMm4 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
_asm {
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteMm5.c b/MdePkg/Library/BaseLib/Ia32/WriteMm5.c
index 434de397..bb4671d6 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteMm5.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteMm5.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Writes the current value of 64-bit MMX Register #5 (MM5).
@@ -21,7 +18,7 @@
VOID
EFIAPI
AsmWriteMm5 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
_asm {
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteMm6.c b/MdePkg/Library/BaseLib/Ia32/WriteMm6.c
index dcb8064c..7b1bdf3f 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteMm6.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteMm6.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Writes the current value of 64-bit MMX Register #6 (MM6).
@@ -21,7 +18,7 @@
VOID
EFIAPI
AsmWriteMm6 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
_asm {
@@ -29,4 +26,3 @@ AsmWriteMm6 (
emms
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteMm7.c b/MdePkg/Library/BaseLib/Ia32/WriteMm7.c
index 833f6451..6f573f72 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteMm7.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteMm7.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Writes the current value of 64-bit MMX Register #7 (MM7).
@@ -21,7 +18,7 @@
VOID
EFIAPI
AsmWriteMm7 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
_asm {
@@ -29,4 +26,3 @@ AsmWriteMm7 (
emms
}
}
-
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteMsr64.c b/MdePkg/Library/BaseLib/Ia32/WriteMsr64.c
index c94a79c8..73baae14 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteMsr64.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteMsr64.c
@@ -6,7 +6,6 @@
**/
-
#include
/**
@@ -33,7 +32,7 @@ AsmWriteMsr64 (
IN UINT64 Value
)
{
- BOOLEAN Flag;
+ BOOLEAN Flag;
Flag = FilterBeforeMsrWrite (Index, &Value);
if (Flag) {
@@ -44,8 +43,8 @@ AsmWriteMsr64 (
wrmsr
}
}
+
FilterAfterMsrWrite (Index, &Value);
return Value;
}
-
diff --git a/MdePkg/Library/BaseLib/IntelTdxNull.c b/MdePkg/Library/BaseLib/IntelTdxNull.c
new file mode 100644
index 00000000..b88c8718
--- /dev/null
+++ b/MdePkg/Library/BaseLib/IntelTdxNull.c
@@ -0,0 +1,83 @@
+/** @file
+
+ Null stub of TdxLib
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+
+/**
+ The TDCALL instruction causes a VM exit to the Intel TDX module. It is
+ used to call guest-side Intel TDX functions, either local or a TD exit
+ to the host VMM, as selected by Leaf.
+ Leaf functions are described at
+
+ @param[in] Leaf Leaf number of TDCALL instruction
+ @param[in] Arg1 Arg1
+ @param[in] Arg2 Arg2
+ @param[in] Arg3 Arg3
+ @param[in,out] Results Returned result of the Leaf function
+
+ @return EFI_SUCCESS
+ @return Other See individual leaf functions
+**/
+UINTN
+EFIAPI
+TdCall (
+ IN UINT64 Leaf,
+ IN UINT64 Arg1,
+ IN UINT64 Arg2,
+ IN UINT64 Arg3,
+ IN OUT VOID *Results
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ TDVMALL is a leaf function 0 for TDCALL. It helps invoke services from the
+ host VMM to pass/receive information.
+
+ @param[in] Leaf Number of sub-functions
+ @param[in] Arg1 Arg1
+ @param[in] Arg2 Arg2
+ @param[in] Arg3 Arg3
+ @param[in] Arg4 Arg4
+ @param[in,out] Results Returned result of the sub-function
+
+ @return EFI_SUCCESS
+ @return Other See individual sub-functions
+
+**/
+UINTN
+EFIAPI
+TdVmCall (
+ IN UINT64 Leaf,
+ IN UINT64 Arg1,
+ IN UINT64 Arg2,
+ IN UINT64 Arg3,
+ IN UINT64 Arg4,
+ IN OUT VOID *Results
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Probe if TD is enabled.
+
+ @return TRUE TD is enabled.
+ @return FALSE TD is not enabled.
+**/
+BOOLEAN
+EFIAPI
+TdIsEnabled (
+ )
+{
+ return FALSE;
+}
diff --git a/MdePkg/Library/BaseLib/LRotU32.c b/MdePkg/Library/BaseLib/LRotU32.c
index 6932110d..ce04b1e5 100644
--- a/MdePkg/Library/BaseLib/LRotU32.c
+++ b/MdePkg/Library/BaseLib/LRotU32.c
@@ -27,8 +27,8 @@
UINT32
EFIAPI
LRotU32 (
- IN UINT32 Operand,
- IN UINTN Count
+ IN UINT32 Operand,
+ IN UINTN Count
)
{
ASSERT (Count < 32);
diff --git a/MdePkg/Library/BaseLib/LRotU64.c b/MdePkg/Library/BaseLib/LRotU64.c
index 25ff3baa..565c45c6 100644
--- a/MdePkg/Library/BaseLib/LRotU64.c
+++ b/MdePkg/Library/BaseLib/LRotU64.c
@@ -27,8 +27,8 @@
UINT64
EFIAPI
LRotU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
)
{
ASSERT (Count < 64);
diff --git a/MdePkg/Library/BaseLib/LShiftU64.c b/MdePkg/Library/BaseLib/LShiftU64.c
index 01097e55..ff5d38e6 100644
--- a/MdePkg/Library/BaseLib/LShiftU64.c
+++ b/MdePkg/Library/BaseLib/LShiftU64.c
@@ -26,8 +26,8 @@
UINT64
EFIAPI
LShiftU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
)
{
ASSERT (Count < 64);
diff --git a/MdePkg/Library/BaseLib/LinkedList.c b/MdePkg/Library/BaseLib/LinkedList.c
index be2e628e..64110104 100644
--- a/MdePkg/Library/BaseLib/LinkedList.c
+++ b/MdePkg/Library/BaseLib/LinkedList.c
@@ -28,7 +28,7 @@
**/
#if !defined (MDEPKG_NDEBUG)
- #define ASSERT_VERIFY_NODE_IN_VALID_LIST(FirstEntry, SecondEntry, InList) \
+#define ASSERT_VERIFY_NODE_IN_VALID_LIST(FirstEntry, SecondEntry, InList) \
do { \
if (FeaturePcdGet (PcdVerifyNodeInList)) { \
ASSERT (InList == IsNodeInList ((FirstEntry), (SecondEntry))); \
@@ -37,7 +37,7 @@
} \
} while (FALSE)
#else
- #define ASSERT_VERIFY_NODE_IN_VALID_LIST(FirstEntry, SecondEntry, InList)
+#define ASSERT_VERIFY_NODE_IN_VALID_LIST(FirstEntry, SecondEntry, InList)
#endif
/**
@@ -119,8 +119,8 @@ InternalBaseLibIsListValid (
BOOLEAN
EFIAPI
IsNodeInList (
- IN CONST LIST_ENTRY *FirstEntry,
- IN CONST LIST_ENTRY *SecondEntry
+ IN CONST LIST_ENTRY *FirstEntry,
+ IN CONST LIST_ENTRY *SecondEntry
)
{
UINTN Count;
@@ -180,14 +180,14 @@ IsNodeInList (
LIST_ENTRY *
EFIAPI
InitializeListHead (
- IN OUT LIST_ENTRY *ListHead
+ IN OUT LIST_ENTRY *ListHead
)
{
ASSERT (ListHead != NULL);
ListHead->ForwardLink = ListHead;
- ListHead->BackLink = ListHead;
+ ListHead->BackLink = ListHead;
return ListHead;
}
@@ -216,8 +216,8 @@ InitializeListHead (
LIST_ENTRY *
EFIAPI
InsertHeadList (
- IN OUT LIST_ENTRY *ListHead,
- IN OUT LIST_ENTRY *Entry
+ IN OUT LIST_ENTRY *ListHead,
+ IN OUT LIST_ENTRY *Entry
)
{
//
@@ -225,10 +225,10 @@ InsertHeadList (
//
ASSERT_VERIFY_NODE_IN_VALID_LIST (ListHead, Entry, FALSE);
- Entry->ForwardLink = ListHead->ForwardLink;
- Entry->BackLink = ListHead;
+ Entry->ForwardLink = ListHead->ForwardLink;
+ Entry->BackLink = ListHead;
Entry->ForwardLink->BackLink = Entry;
- ListHead->ForwardLink = Entry;
+ ListHead->ForwardLink = Entry;
return ListHead;
}
@@ -257,8 +257,8 @@ InsertHeadList (
LIST_ENTRY *
EFIAPI
InsertTailList (
- IN OUT LIST_ENTRY *ListHead,
- IN OUT LIST_ENTRY *Entry
+ IN OUT LIST_ENTRY *ListHead,
+ IN OUT LIST_ENTRY *Entry
)
{
//
@@ -266,10 +266,10 @@ InsertTailList (
//
ASSERT_VERIFY_NODE_IN_VALID_LIST (ListHead, Entry, FALSE);
- Entry->ForwardLink = ListHead;
- Entry->BackLink = ListHead->BackLink;
+ Entry->ForwardLink = ListHead;
+ Entry->BackLink = ListHead->BackLink;
Entry->BackLink->ForwardLink = Entry;
- ListHead->BackLink = Entry;
+ ListHead->BackLink = Entry;
return ListHead;
}
@@ -296,7 +296,7 @@ InsertTailList (
LIST_ENTRY *
EFIAPI
GetFirstNode (
- IN CONST LIST_ENTRY *List
+ IN CONST LIST_ENTRY *List
)
{
//
@@ -331,8 +331,8 @@ GetFirstNode (
LIST_ENTRY *
EFIAPI
GetNextNode (
- IN CONST LIST_ENTRY *List,
- IN CONST LIST_ENTRY *Node
+ IN CONST LIST_ENTRY *List,
+ IN CONST LIST_ENTRY *Node
)
{
//
@@ -367,8 +367,8 @@ GetNextNode (
LIST_ENTRY *
EFIAPI
GetPreviousNode (
- IN CONST LIST_ENTRY *List,
- IN CONST LIST_ENTRY *Node
+ IN CONST LIST_ENTRY *List,
+ IN CONST LIST_ENTRY *Node
)
{
//
@@ -401,7 +401,7 @@ GetPreviousNode (
BOOLEAN
EFIAPI
IsListEmpty (
- IN CONST LIST_ENTRY *ListHead
+ IN CONST LIST_ENTRY *ListHead
)
{
//
@@ -441,8 +441,8 @@ IsListEmpty (
BOOLEAN
EFIAPI
IsNull (
- IN CONST LIST_ENTRY *List,
- IN CONST LIST_ENTRY *Node
+ IN CONST LIST_ENTRY *List,
+ IN CONST LIST_ENTRY *Node
)
{
//
@@ -479,8 +479,8 @@ IsNull (
BOOLEAN
EFIAPI
IsNodeAtEnd (
- IN CONST LIST_ENTRY *List,
- IN CONST LIST_ENTRY *Node
+ IN CONST LIST_ENTRY *List,
+ IN CONST LIST_ENTRY *Node
)
{
//
@@ -520,11 +520,11 @@ IsNodeAtEnd (
LIST_ENTRY *
EFIAPI
SwapListEntries (
- IN OUT LIST_ENTRY *FirstEntry,
- IN OUT LIST_ENTRY *SecondEntry
+ IN OUT LIST_ENTRY *FirstEntry,
+ IN OUT LIST_ENTRY *SecondEntry
)
{
- LIST_ENTRY *Ptr;
+ LIST_ENTRY *Ptr;
if (FirstEntry == SecondEntry) {
return SecondEntry;
@@ -588,7 +588,7 @@ SwapListEntries (
LIST_ENTRY *
EFIAPI
RemoveEntryList (
- IN CONST LIST_ENTRY *Entry
+ IN CONST LIST_ENTRY *Entry
)
{
ASSERT (!IsListEmpty (Entry));
diff --git a/MdePkg/Library/BaseLib/LongJump.c b/MdePkg/Library/BaseLib/LongJump.c
index 6fefcb36..e707ce94 100644
--- a/MdePkg/Library/BaseLib/LongJump.c
+++ b/MdePkg/Library/BaseLib/LongJump.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
diff --git a/MdePkg/Library/BaseLib/LowBitSet32.c b/MdePkg/Library/BaseLib/LowBitSet32.c
index af453367..904bcf72 100644
--- a/MdePkg/Library/BaseLib/LowBitSet32.c
+++ b/MdePkg/Library/BaseLib/LowBitSet32.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -27,15 +24,17 @@
INTN
EFIAPI
LowBitSet32 (
- IN UINT32 Operand
+ IN UINT32 Operand
)
{
- INTN BitIndex;
+ INTN BitIndex;
if (Operand == 0) {
return -1;
}
- for (BitIndex = 0; 0 == (Operand & 1); BitIndex++, Operand >>= 1);
+ for (BitIndex = 0; 0 == (Operand & 1); BitIndex++, Operand >>= 1) {
+ }
+
return BitIndex;
}
diff --git a/MdePkg/Library/BaseLib/LowBitSet64.c b/MdePkg/Library/BaseLib/LowBitSet64.c
index b1e9b4b4..afbd188e 100644
--- a/MdePkg/Library/BaseLib/LowBitSet64.c
+++ b/MdePkg/Library/BaseLib/LowBitSet64.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -28,10 +25,10 @@
INTN
EFIAPI
LowBitSet64 (
- IN UINT64 Operand
+ IN UINT64 Operand
)
{
- INTN BitIndex;
+ INTN BitIndex;
if (Operand == 0) {
return -1;
@@ -39,6 +36,9 @@ LowBitSet64 (
for (BitIndex = 0;
(Operand & 1) == 0;
- BitIndex++, Operand = RShiftU64 (Operand, 1));
+ BitIndex++, Operand = RShiftU64 (Operand, 1))
+ {
+ }
+
return BitIndex;
}
diff --git a/MdePkg/Library/BaseLib/Math64.c b/MdePkg/Library/BaseLib/Math64.c
index 7c02fe50..224d8477 100644
--- a/MdePkg/Library/BaseLib/Math64.c
+++ b/MdePkg/Library/BaseLib/Math64.c
@@ -25,8 +25,8 @@
UINT64
EFIAPI
InternalMathLShiftU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
)
{
return Operand << Count;
@@ -48,8 +48,8 @@ InternalMathLShiftU64 (
UINT64
EFIAPI
InternalMathRShiftU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
)
{
return Operand >> Count;
@@ -71,8 +71,8 @@ InternalMathRShiftU64 (
UINT64
EFIAPI
InternalMathARShiftU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
)
{
INTN TestValue;
@@ -95,7 +95,6 @@ InternalMathARShiftU64 (
((INTN)Operand < 0 ? ~((UINTN)-1 >> Count) : 0);
}
-
/**
Rotates a 64-bit integer left between 0 and 63 bits, filling
the low bits with the high bits that were rotated.
@@ -113,8 +112,8 @@ InternalMathARShiftU64 (
UINT64
EFIAPI
InternalMathLRotU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
)
{
return (Operand << Count) | (Operand >> (64 - Count));
@@ -137,8 +136,8 @@ InternalMathLRotU64 (
UINT64
EFIAPI
InternalMathRRotU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
)
{
return (Operand >> Count) | (Operand << (64 - Count));
@@ -159,14 +158,14 @@ InternalMathRRotU64 (
UINT64
EFIAPI
InternalMathSwapBytes64 (
- IN UINT64 Operand
+ IN UINT64 Operand
)
{
UINT64 LowerBytes;
UINT64 HigherBytes;
- LowerBytes = (UINT64) SwapBytes32 ((UINT32) Operand);
- HigherBytes = (UINT64) SwapBytes32 ((UINT32) (Operand >> 32));
+ LowerBytes = (UINT64)SwapBytes32 ((UINT32)Operand);
+ HigherBytes = (UINT64)SwapBytes32 ((UINT32)(Operand >> 32));
return (LowerBytes << 32 | HigherBytes);
}
@@ -188,14 +187,13 @@ InternalMathSwapBytes64 (
UINT64
EFIAPI
InternalMathMultU64x32 (
- IN UINT64 Multiplicand,
- IN UINT32 Multiplier
+ IN UINT64 Multiplicand,
+ IN UINT32 Multiplier
)
{
return Multiplicand * Multiplier;
}
-
/**
Multiplies a 64-bit unsigned integer by a 64-bit unsigned integer
and generates a 64-bit unsigned result.
@@ -213,8 +211,8 @@ InternalMathMultU64x32 (
UINT64
EFIAPI
InternalMathMultU64x64 (
- IN UINT64 Multiplicand,
- IN UINT64 Multiplier
+ IN UINT64 Multiplicand,
+ IN UINT64 Multiplier
)
{
return Multiplicand * Multiplier;
@@ -237,8 +235,8 @@ InternalMathMultU64x64 (
UINT64
EFIAPI
InternalMathDivU64x32 (
- IN UINT64 Dividend,
- IN UINT32 Divisor
+ IN UINT64 Dividend,
+ IN UINT32 Divisor
)
{
return Dividend / Divisor;
@@ -261,8 +259,8 @@ InternalMathDivU64x32 (
UINT32
EFIAPI
InternalMathModU64x32 (
- IN UINT64 Dividend,
- IN UINT32 Divisor
+ IN UINT64 Dividend,
+ IN UINT32 Divisor
)
{
return (UINT32)(Dividend % Divisor);
@@ -288,14 +286,15 @@ InternalMathModU64x32 (
UINT64
EFIAPI
InternalMathDivRemU64x32 (
- IN UINT64 Dividend,
- IN UINT32 Divisor,
- OUT UINT32 *Remainder OPTIONAL
+ IN UINT64 Dividend,
+ IN UINT32 Divisor,
+ OUT UINT32 *Remainder OPTIONAL
)
{
if (Remainder != NULL) {
*Remainder = (UINT32)(Dividend % Divisor);
}
+
return Dividend / Divisor;
}
@@ -319,14 +318,15 @@ InternalMathDivRemU64x32 (
UINT64
EFIAPI
InternalMathDivRemU64x64 (
- IN UINT64 Dividend,
- IN UINT64 Divisor,
- OUT UINT64 *Remainder OPTIONAL
+ IN UINT64 Dividend,
+ IN UINT64 Divisor,
+ OUT UINT64 *Remainder OPTIONAL
)
{
if (Remainder != NULL) {
*Remainder = Dividend % Divisor;
}
+
return Dividend / Divisor;
}
@@ -350,13 +350,14 @@ InternalMathDivRemU64x64 (
INT64
EFIAPI
InternalMathDivRemS64x64 (
- IN INT64 Dividend,
- IN INT64 Divisor,
- OUT INT64 *Remainder OPTIONAL
+ IN INT64 Dividend,
+ IN INT64 Divisor,
+ OUT INT64 *Remainder OPTIONAL
)
{
if (Remainder != NULL) {
*Remainder = Dividend % Divisor;
}
+
return Dividend / Divisor;
}
diff --git a/MdePkg/Library/BaseLib/ModU64x32.c b/MdePkg/Library/BaseLib/ModU64x32.c
index d0c38932..06f08e57 100644
--- a/MdePkg/Library/BaseLib/ModU64x32.c
+++ b/MdePkg/Library/BaseLib/ModU64x32.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -30,8 +27,8 @@
UINT32
EFIAPI
ModU64x32 (
- IN UINT64 Dividend,
- IN UINT32 Divisor
+ IN UINT64 Dividend,
+ IN UINT32 Divisor
)
{
ASSERT (Divisor != 0);
diff --git a/MdePkg/Library/BaseLib/MultS64x64.c b/MdePkg/Library/BaseLib/MultS64x64.c
index 911cad4b..a56bc46e 100644
--- a/MdePkg/Library/BaseLib/MultS64x64.c
+++ b/MdePkg/Library/BaseLib/MultS64x64.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -28,9 +25,9 @@
INT64
EFIAPI
MultS64x64 (
- IN INT64 Multiplicand,
- IN INT64 Multiplier
+ IN INT64 Multiplicand,
+ IN INT64 Multiplier
)
{
- return (INT64)MultU64x64 ((UINT64) Multiplicand, (UINT64) Multiplier);
+ return (INT64)MultU64x64 ((UINT64)Multiplicand, (UINT64)Multiplier);
}
diff --git a/MdePkg/Library/BaseLib/MultU64x32.c b/MdePkg/Library/BaseLib/MultU64x32.c
index 8155300d..803e7ce5 100644
--- a/MdePkg/Library/BaseLib/MultU64x32.c
+++ b/MdePkg/Library/BaseLib/MultU64x32.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -28,11 +25,11 @@
UINT64
EFIAPI
MultU64x32 (
- IN UINT64 Multiplicand,
- IN UINT32 Multiplier
+ IN UINT64 Multiplicand,
+ IN UINT32 Multiplier
)
{
- UINT64 Result;
+ UINT64 Result;
Result = InternalMathMultU64x32 (Multiplicand, Multiplier);
diff --git a/MdePkg/Library/BaseLib/MultU64x64.c b/MdePkg/Library/BaseLib/MultU64x64.c
index daab56f0..6d266a55 100644
--- a/MdePkg/Library/BaseLib/MultU64x64.c
+++ b/MdePkg/Library/BaseLib/MultU64x64.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -28,11 +25,11 @@
UINT64
EFIAPI
MultU64x64 (
- IN UINT64 Multiplicand,
- IN UINT64 Multiplier
+ IN UINT64 Multiplicand,
+ IN UINT64 Multiplier
)
{
- UINT64 Result;
+ UINT64 Result;
Result = InternalMathMultU64x64 (Multiplicand, Multiplier);
diff --git a/MdePkg/Library/BaseLib/QuickSort.c b/MdePkg/Library/BaseLib/QuickSort.c
index 3f8ab7e8..72dcbaf0 100644
--- a/MdePkg/Library/BaseLib/QuickSort.c
+++ b/MdePkg/Library/BaseLib/QuickSort.c
@@ -34,16 +34,16 @@
VOID
EFIAPI
QuickSort (
- IN OUT VOID *BufferToSort,
- IN CONST UINTN Count,
- IN CONST UINTN ElementSize,
- IN BASE_SORT_COMPARE CompareFunction,
- OUT VOID *BufferOneElement
+ IN OUT VOID *BufferToSort,
+ IN CONST UINTN Count,
+ IN CONST UINTN ElementSize,
+ IN BASE_SORT_COMPARE CompareFunction,
+ OUT VOID *BufferOneElement
)
{
- VOID *Pivot;
- UINTN LoopCount;
- UINTN NextSwapLocation;
+ VOID *Pivot;
+ UINTN LoopCount;
+ UINTN NextSwapLocation;
ASSERT (BufferToSort != NULL);
ASSERT (CompareFunction != NULL);
@@ -59,7 +59,7 @@ QuickSort (
//
// pick a pivot (we choose last element)
//
- Pivot = ((UINT8*) BufferToSort + ((Count - 1) * ElementSize));
+ Pivot = ((UINT8 *)BufferToSort + ((Count - 1) * ElementSize));
//
// Now get the pivot such that all on "left" are below it
@@ -69,13 +69,13 @@ QuickSort (
//
// if the element is less than or equal to the pivot
//
- if (CompareFunction ((VOID*) ((UINT8*) BufferToSort + ((LoopCount) * ElementSize)), Pivot) <= 0){
+ if (CompareFunction ((VOID *)((UINT8 *)BufferToSort + ((LoopCount) * ElementSize)), Pivot) <= 0) {
//
// swap
//
- CopyMem (BufferOneElement, (UINT8*) BufferToSort + (NextSwapLocation * ElementSize), ElementSize);
- CopyMem ((UINT8*) BufferToSort + (NextSwapLocation * ElementSize), (UINT8*) BufferToSort + ((LoopCount) * ElementSize), ElementSize);
- CopyMem ((UINT8*) BufferToSort + ((LoopCount)*ElementSize), BufferOneElement, ElementSize);
+ CopyMem (BufferOneElement, (UINT8 *)BufferToSort + (NextSwapLocation * ElementSize), ElementSize);
+ CopyMem ((UINT8 *)BufferToSort + (NextSwapLocation * ElementSize), (UINT8 *)BufferToSort + ((LoopCount) * ElementSize), ElementSize);
+ CopyMem ((UINT8 *)BufferToSort + ((LoopCount)*ElementSize), BufferOneElement, ElementSize);
//
// increment NextSwapLocation
@@ -83,12 +83,13 @@ QuickSort (
NextSwapLocation++;
}
}
+
//
// swap pivot to it's final position (NextSwapLocation)
//
CopyMem (BufferOneElement, Pivot, ElementSize);
- CopyMem (Pivot, (UINT8*) BufferToSort + (NextSwapLocation * ElementSize), ElementSize);
- CopyMem ((UINT8*) BufferToSort + (NextSwapLocation * ElementSize), BufferOneElement, ElementSize);
+ CopyMem (Pivot, (UINT8 *)BufferToSort + (NextSwapLocation * ElementSize), ElementSize);
+ CopyMem ((UINT8 *)BufferToSort + (NextSwapLocation * ElementSize), BufferOneElement, ElementSize);
//
// Now recurse on 2 partial lists. neither of these will have the 'pivot' element
diff --git a/MdePkg/Library/BaseLib/RRotU32.c b/MdePkg/Library/BaseLib/RRotU32.c
index 4207ddb1..1d12ee78 100644
--- a/MdePkg/Library/BaseLib/RRotU32.c
+++ b/MdePkg/Library/BaseLib/RRotU32.c
@@ -27,8 +27,8 @@
UINT32
EFIAPI
RRotU32 (
- IN UINT32 Operand,
- IN UINTN Count
+ IN UINT32 Operand,
+ IN UINTN Count
)
{
ASSERT (Count < 32);
diff --git a/MdePkg/Library/BaseLib/RRotU64.c b/MdePkg/Library/BaseLib/RRotU64.c
index e41d2925..a9a8be37 100644
--- a/MdePkg/Library/BaseLib/RRotU64.c
+++ b/MdePkg/Library/BaseLib/RRotU64.c
@@ -27,8 +27,8 @@
UINT64
EFIAPI
RRotU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
)
{
ASSERT (Count < 64);
diff --git a/MdePkg/Library/BaseLib/RShiftU64.c b/MdePkg/Library/BaseLib/RShiftU64.c
index 363b1588..3c98eb98 100644
--- a/MdePkg/Library/BaseLib/RShiftU64.c
+++ b/MdePkg/Library/BaseLib/RShiftU64.c
@@ -26,8 +26,8 @@
UINT64
EFIAPI
RShiftU64 (
- IN UINT64 Operand,
- IN UINTN Count
+ IN UINT64 Operand,
+ IN UINTN Count
)
{
ASSERT (Count < 64);
diff --git a/MdePkg/Library/BaseLib/SafeString.c b/MdePkg/Library/BaseLib/SafeString.c
index 454005b9..859db2ef 100644
--- a/MdePkg/Library/BaseLib/SafeString.c
+++ b/MdePkg/Library/BaseLib/SafeString.c
@@ -17,7 +17,7 @@
if (!(Expression)) { \
DEBUG ((DEBUG_VERBOSE, \
"%a(%d) %a: SAFE_STRING_CONSTRAINT_CHECK(%a) failed. Return %r\n", \
- __FILE__, DEBUG_LINE_NUMBER, __FUNCTION__, DEBUG_EXPRESSION_STRING (Expression), Status)); \
+ __FILE__, DEBUG_LINE_NUMBER, __func__, DEBUG_EXPRESSION_STRING (Expression), Status)); \
return Status; \
} \
} while (FALSE)
@@ -35,16 +35,18 @@
**/
BOOLEAN
InternalSafeStringIsOverlap (
- IN VOID *Base1,
- IN UINTN Size1,
- IN VOID *Base2,
- IN UINTN Size2
+ IN VOID *Base1,
+ IN UINTN Size1,
+ IN VOID *Base2,
+ IN UINTN Size2
)
{
if ((((UINTN)Base1 >= (UINTN)Base2) && ((UINTN)Base1 < (UINTN)Base2 + Size2)) ||
- (((UINTN)Base2 >= (UINTN)Base1) && ((UINTN)Base2 < (UINTN)Base1 + Size1))) {
+ (((UINTN)Base2 >= (UINTN)Base1) && ((UINTN)Base2 < (UINTN)Base1 + Size1)))
+ {
return TRUE;
}
+
return FALSE;
}
@@ -69,7 +71,7 @@ InternalSafeStringNoStrOverlap (
IN UINTN Size2
)
{
- return !InternalSafeStringIsOverlap (Str1, Size1 * sizeof(CHAR16), Str2, Size2 * sizeof(CHAR16));
+ return !InternalSafeStringIsOverlap (Str1, Size1 * sizeof (CHAR16), Str2, Size2 * sizeof (CHAR16));
}
/**
@@ -87,10 +89,10 @@ InternalSafeStringNoStrOverlap (
**/
BOOLEAN
InternalSafeStringNoAsciiStrOverlap (
- IN CHAR8 *Str1,
- IN UINTN Size1,
- IN CHAR8 *Str2,
- IN UINTN Size2
+ IN CHAR8 *Str1,
+ IN UINTN Size1,
+ IN CHAR8 *Str2,
+ IN UINTN Size2
)
{
return !InternalSafeStringIsOverlap (Str1, Size1, Str2, Size2);
@@ -115,13 +117,13 @@ InternalSafeStringNoAsciiStrOverlap (
UINTN
EFIAPI
StrnLenS (
- IN CONST CHAR16 *String,
- IN UINTN MaxSize
+ IN CONST CHAR16 *String,
+ IN UINTN MaxSize
)
{
- UINTN Length;
+ UINTN Length;
- ASSERT (((UINTN) String & BIT0) == 0);
+ ASSERT (((UINTN)String & BIT0) == 0);
//
// If String is a null pointer or MaxSize is 0, then the StrnLenS function returns zero.
@@ -141,8 +143,10 @@ StrnLenS (
if (Length >= MaxSize - 1) {
return MaxSize;
}
+
Length++;
}
+
return Length;
}
@@ -170,8 +174,8 @@ StrnLenS (
UINTN
EFIAPI
StrnSizeS (
- IN CONST CHAR16 *String,
- IN UINTN MaxSize
+ IN CONST CHAR16 *String,
+ IN UINTN MaxSize
)
{
//
@@ -220,15 +224,15 @@ StrnSizeS (
RETURN_STATUS
EFIAPI
StrCpyS (
- OUT CHAR16 *Destination,
- IN UINTN DestMax,
- IN CONST CHAR16 *Source
+ OUT CHAR16 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR16 *Source
)
{
- UINTN SourceLen;
+ UINTN SourceLen;
- ASSERT (((UINTN) Destination & BIT0) == 0);
- ASSERT (((UINTN) Source & BIT0) == 0);
+ ASSERT (((UINTN)Destination & BIT0) == 0);
+ ASSERT (((UINTN)Source & BIT0) == 0);
//
// 1. Neither Destination nor Source shall be a null pointer.
@@ -266,6 +270,7 @@ StrCpyS (
while (*Source != 0) {
*(Destination++) = *(Source++);
}
+
*Destination = 0;
return RETURN_SUCCESS;
@@ -303,16 +308,16 @@ StrCpyS (
RETURN_STATUS
EFIAPI
StrnCpyS (
- OUT CHAR16 *Destination,
- IN UINTN DestMax,
- IN CONST CHAR16 *Source,
- IN UINTN Length
+ OUT CHAR16 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR16 *Source,
+ IN UINTN Length
)
{
- UINTN SourceLen;
+ UINTN SourceLen;
- ASSERT (((UINTN) Destination & BIT0) == 0);
- ASSERT (((UINTN) Source & BIT0) == 0);
+ ASSERT (((UINTN)Destination & BIT0) == 0);
+ ASSERT (((UINTN)Source & BIT0) == 0);
//
// 1. Neither Destination nor Source shall be a null pointer.
@@ -347,6 +352,7 @@ StrnCpyS (
if (SourceLen > Length) {
SourceLen = Length;
}
+
SAFE_STRING_CONSTRAINT_CHECK (InternalSafeStringNoStrOverlap (Destination, DestMax, (CHAR16 *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);
//
@@ -359,6 +365,7 @@ StrnCpyS (
*(Destination++) = *(Source++);
SourceLen--;
}
+
*Destination = 0;
return RETURN_SUCCESS;
@@ -396,17 +403,17 @@ StrnCpyS (
RETURN_STATUS
EFIAPI
StrCatS (
- IN OUT CHAR16 *Destination,
- IN UINTN DestMax,
- IN CONST CHAR16 *Source
+ IN OUT CHAR16 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR16 *Source
)
{
- UINTN DestLen;
- UINTN CopyLen;
- UINTN SourceLen;
+ UINTN DestLen;
+ UINTN CopyLen;
+ UINTN SourceLen;
- ASSERT (((UINTN) Destination & BIT0) == 0);
- ASSERT (((UINTN) Source & BIT0) == 0);
+ ASSERT (((UINTN)Destination & BIT0) == 0);
+ ASSERT (((UINTN)Source & BIT0) == 0);
//
// Let CopyLen denote the value DestMax - StrnLenS(Destination, DestMax) upon entry to StrCatS.
@@ -457,6 +464,7 @@ StrCatS (
while (*Source != 0) {
*(Destination++) = *(Source++);
}
+
*Destination = 0;
return RETURN_SUCCESS;
@@ -497,18 +505,18 @@ StrCatS (
RETURN_STATUS
EFIAPI
StrnCatS (
- IN OUT CHAR16 *Destination,
- IN UINTN DestMax,
- IN CONST CHAR16 *Source,
- IN UINTN Length
+ IN OUT CHAR16 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR16 *Source,
+ IN UINTN Length
)
{
- UINTN DestLen;
- UINTN CopyLen;
- UINTN SourceLen;
+ UINTN DestLen;
+ UINTN CopyLen;
+ UINTN SourceLen;
- ASSERT (((UINTN) Destination & BIT0) == 0);
- ASSERT (((UINTN) Source & BIT0) == 0);
+ ASSERT (((UINTN)Destination & BIT0) == 0);
+ ASSERT (((UINTN)Source & BIT0) == 0);
//
// Let CopyLen denote the value DestMax - StrnLenS(Destination, DestMax) upon entry to StrnCatS.
@@ -554,6 +562,7 @@ StrnCatS (
if (SourceLen > Length) {
SourceLen = Length;
}
+
SAFE_STRING_CONSTRAINT_CHECK (InternalSafeStringNoStrOverlap (Destination, DestMax, (CHAR16 *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);
//
@@ -568,6 +577,7 @@ StrnCatS (
*(Destination++) = *(Source++);
SourceLen--;
}
+
*Destination = 0;
return RETURN_SUCCESS;
@@ -619,12 +629,12 @@ StrnCatS (
RETURN_STATUS
EFIAPI
StrDecimalToUintnS (
- IN CONST CHAR16 *String,
- OUT CHAR16 **EndPointer, OPTIONAL
- OUT UINTN *Data
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer OPTIONAL,
+ OUT UINTN *Data
)
{
- ASSERT (((UINTN) String & BIT0) == 0);
+ ASSERT (((UINTN)String & BIT0) == 0);
//
// 1. Neither String nor Data shall be a null pointer.
@@ -640,7 +650,7 @@ StrDecimalToUintnS (
}
if (EndPointer != NULL) {
- *EndPointer = (CHAR16 *) String;
+ *EndPointer = (CHAR16 *)String;
}
//
@@ -668,8 +678,9 @@ StrDecimalToUintnS (
if (*Data > ((MAX_UINTN - (*String - L'0')) / 10)) {
*Data = MAX_UINTN;
if (EndPointer != NULL) {
- *EndPointer = (CHAR16 *) String;
+ *EndPointer = (CHAR16 *)String;
}
+
return RETURN_UNSUPPORTED;
}
@@ -678,8 +689,9 @@ StrDecimalToUintnS (
}
if (EndPointer != NULL) {
- *EndPointer = (CHAR16 *) String;
+ *EndPointer = (CHAR16 *)String;
}
+
return RETURN_SUCCESS;
}
@@ -729,12 +741,12 @@ StrDecimalToUintnS (
RETURN_STATUS
EFIAPI
StrDecimalToUint64S (
- IN CONST CHAR16 *String,
- OUT CHAR16 **EndPointer, OPTIONAL
- OUT UINT64 *Data
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer OPTIONAL,
+ OUT UINT64 *Data
)
{
- ASSERT (((UINTN) String & BIT0) == 0);
+ ASSERT (((UINTN)String & BIT0) == 0);
//
// 1. Neither String nor Data shall be a null pointer.
@@ -750,7 +762,7 @@ StrDecimalToUint64S (
}
if (EndPointer != NULL) {
- *EndPointer = (CHAR16 *) String;
+ *EndPointer = (CHAR16 *)String;
}
//
@@ -778,8 +790,9 @@ StrDecimalToUint64S (
if (*Data > DivU64x32 (MAX_UINT64 - (*String - L'0'), 10)) {
*Data = MAX_UINT64;
if (EndPointer != NULL) {
- *EndPointer = (CHAR16 *) String;
+ *EndPointer = (CHAR16 *)String;
}
+
return RETURN_UNSUPPORTED;
}
@@ -788,8 +801,9 @@ StrDecimalToUint64S (
}
if (EndPointer != NULL) {
- *EndPointer = (CHAR16 *) String;
+ *EndPointer = (CHAR16 *)String;
}
+
return RETURN_SUCCESS;
}
@@ -844,12 +858,15 @@ StrDecimalToUint64S (
RETURN_STATUS
EFIAPI
StrHexToUintnS (
- IN CONST CHAR16 *String,
- OUT CHAR16 **EndPointer, OPTIONAL
- OUT UINTN *Data
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer OPTIONAL,
+ OUT UINTN *Data
)
{
- ASSERT (((UINTN) String & BIT0) == 0);
+ BOOLEAN FoundLeadingZero;
+
+ FoundLeadingZero = FALSE;
+ ASSERT (((UINTN)String & BIT0) == 0);
//
// 1. Neither String nor Data shall be a null pointer.
@@ -865,7 +882,7 @@ StrHexToUintnS (
}
if (EndPointer != NULL) {
- *EndPointer = (CHAR16 *) String;
+ *EndPointer = (CHAR16 *)String;
}
//
@@ -878,15 +895,18 @@ StrHexToUintnS (
//
// Ignore leading Zeros after the spaces
//
+
+ FoundLeadingZero = *String == L'0';
while (*String == L'0') {
String++;
}
if (CharToUpper (*String) == L'X') {
- if (*(String - 1) != L'0') {
+ if (!FoundLeadingZero) {
*Data = 0;
return RETURN_SUCCESS;
}
+
//
// Skip the 'X'
//
@@ -904,8 +924,9 @@ StrHexToUintnS (
if (*Data > ((MAX_UINTN - InternalHexCharToUintn (*String)) >> 4)) {
*Data = MAX_UINTN;
if (EndPointer != NULL) {
- *EndPointer = (CHAR16 *) String;
+ *EndPointer = (CHAR16 *)String;
}
+
return RETURN_UNSUPPORTED;
}
@@ -914,8 +935,9 @@ StrHexToUintnS (
}
if (EndPointer != NULL) {
- *EndPointer = (CHAR16 *) String;
+ *EndPointer = (CHAR16 *)String;
}
+
return RETURN_SUCCESS;
}
@@ -970,12 +992,15 @@ StrHexToUintnS (
RETURN_STATUS
EFIAPI
StrHexToUint64S (
- IN CONST CHAR16 *String,
- OUT CHAR16 **EndPointer, OPTIONAL
- OUT UINT64 *Data
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer OPTIONAL,
+ OUT UINT64 *Data
)
{
- ASSERT (((UINTN) String & BIT0) == 0);
+ BOOLEAN FoundLeadingZero;
+
+ FoundLeadingZero = FALSE;
+ ASSERT (((UINTN)String & BIT0) == 0);
//
// 1. Neither String nor Data shall be a null pointer.
@@ -991,7 +1016,7 @@ StrHexToUint64S (
}
if (EndPointer != NULL) {
- *EndPointer = (CHAR16 *) String;
+ *EndPointer = (CHAR16 *)String;
}
//
@@ -1004,15 +1029,17 @@ StrHexToUint64S (
//
// Ignore leading Zeros after the spaces
//
+ FoundLeadingZero = *String == L'0';
while (*String == L'0') {
String++;
}
if (CharToUpper (*String) == L'X') {
- if (*(String - 1) != L'0') {
+ if (!FoundLeadingZero) {
*Data = 0;
return RETURN_SUCCESS;
}
+
//
// Skip the 'X'
//
@@ -1030,8 +1057,9 @@ StrHexToUint64S (
if (*Data > RShiftU64 (MAX_UINT64 - InternalHexCharToUintn (*String), 4)) {
*Data = MAX_UINT64;
if (EndPointer != NULL) {
- *EndPointer = (CHAR16 *) String;
+ *EndPointer = (CHAR16 *)String;
}
+
return RETURN_UNSUPPORTED;
}
@@ -1040,8 +1068,9 @@ StrHexToUint64S (
}
if (EndPointer != NULL) {
- *EndPointer = (CHAR16 *) String;
+ *EndPointer = (CHAR16 *)String;
}
+
return RETURN_SUCCESS;
}
@@ -1098,27 +1127,27 @@ StrHexToUint64S (
RETURN_STATUS
EFIAPI
StrToIpv6Address (
- IN CONST CHAR16 *String,
- OUT CHAR16 **EndPointer, OPTIONAL
- OUT IPv6_ADDRESS *Address,
- OUT UINT8 *PrefixLength OPTIONAL
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer OPTIONAL,
+ OUT IPv6_ADDRESS *Address,
+ OUT UINT8 *PrefixLength OPTIONAL
)
{
- RETURN_STATUS Status;
- UINTN AddressIndex;
- UINTN Uintn;
- IPv6_ADDRESS LocalAddress;
- UINT8 LocalPrefixLength;
- CONST CHAR16 *Pointer;
- CHAR16 *End;
- UINTN CompressStart;
- BOOLEAN ExpectPrefix;
+ RETURN_STATUS Status;
+ UINTN AddressIndex;
+ UINTN Uintn;
+ IPv6_ADDRESS LocalAddress;
+ UINT8 LocalPrefixLength;
+ CONST CHAR16 *Pointer;
+ CHAR16 *End;
+ UINTN CompressStart;
+ BOOLEAN ExpectPrefix;
LocalPrefixLength = MAX_UINT8;
CompressStart = ARRAY_SIZE (Address->Addr);
ExpectPrefix = FALSE;
- ASSERT (((UINTN) String & BIT0) == 0);
+ ASSERT (((UINTN)String & BIT0) == 0);
//
// 1. None of String or Guid shall be a null pointer.
@@ -1146,7 +1175,7 @@ StrToIpv6Address (
return RETURN_UNSUPPORTED;
}
- if (CompressStart != ARRAY_SIZE (Address->Addr) || AddressIndex == ARRAY_SIZE (Address->Addr)) {
+ if ((CompressStart != ARRAY_SIZE (Address->Addr)) || (AddressIndex == ARRAY_SIZE (Address->Addr))) {
//
// "::" can only appear once.
// "::" can only appear when address is not full length.
@@ -1166,6 +1195,7 @@ StrToIpv6Address (
//
return RETURN_UNSUPPORTED;
}
+
Pointer++;
}
}
@@ -1188,33 +1218,35 @@ StrToIpv6Address (
// Get X.
//
Status = StrHexToUintnS (Pointer, &End, &Uintn);
- if (RETURN_ERROR (Status) || End - Pointer > 4) {
+ if (RETURN_ERROR (Status) || (End - Pointer > 4)) {
//
// Number of hexadecimal digit characters is no more than 4.
//
return RETURN_UNSUPPORTED;
}
+
Pointer = End;
//
// Uintn won't exceed MAX_UINT16 if number of hexadecimal digit characters is no more than 4.
//
ASSERT (AddressIndex + 1 < ARRAY_SIZE (Address->Addr));
- LocalAddress.Addr[AddressIndex] = (UINT8) ((UINT16) Uintn >> 8);
- LocalAddress.Addr[AddressIndex + 1] = (UINT8) Uintn;
- AddressIndex += 2;
+ LocalAddress.Addr[AddressIndex] = (UINT8)((UINT16)Uintn >> 8);
+ LocalAddress.Addr[AddressIndex + 1] = (UINT8)Uintn;
+ AddressIndex += 2;
} else {
//
// Get P, then exit the loop.
//
Status = StrDecimalToUintnS (Pointer, &End, &Uintn);
- if (RETURN_ERROR (Status) || End == Pointer || Uintn > 128) {
+ if (RETURN_ERROR (Status) || (End == Pointer) || (Uintn > 128)) {
//
// Prefix length should not exceed 128.
//
return RETURN_UNSUPPORTED;
}
- LocalPrefixLength = (UINT8) Uintn;
- Pointer = End;
+
+ LocalPrefixLength = (UINT8)Uintn;
+ Pointer = End;
break;
}
}
@@ -1237,18 +1269,21 @@ StrToIpv6Address (
//
break;
}
+
Pointer++;
}
- if ((AddressIndex == ARRAY_SIZE (Address->Addr) && CompressStart != ARRAY_SIZE (Address->Addr)) ||
- (AddressIndex != ARRAY_SIZE (Address->Addr) && CompressStart == ARRAY_SIZE (Address->Addr))
- ) {
+ if (((AddressIndex == ARRAY_SIZE (Address->Addr)) && (CompressStart != ARRAY_SIZE (Address->Addr))) ||
+ ((AddressIndex != ARRAY_SIZE (Address->Addr)) && (CompressStart == ARRAY_SIZE (Address->Addr)))
+ )
+ {
//
// Full length of address shall not have compressing zeros.
// Non-full length of address shall have compressing zeros.
//
return RETURN_UNSUPPORTED;
}
+
CopyMem (&Address->Addr[0], &LocalAddress.Addr[0], CompressStart);
ZeroMem (&Address->Addr[CompressStart], ARRAY_SIZE (Address->Addr) - AddressIndex);
if (AddressIndex > CompressStart) {
@@ -1262,8 +1297,9 @@ StrToIpv6Address (
if (PrefixLength != NULL) {
*PrefixLength = LocalPrefixLength;
}
+
if (EndPointer != NULL) {
- *EndPointer = (CHAR16 *) Pointer;
+ *EndPointer = (CHAR16 *)Pointer;
}
return RETURN_SUCCESS;
@@ -1313,22 +1349,22 @@ StrToIpv6Address (
RETURN_STATUS
EFIAPI
StrToIpv4Address (
- IN CONST CHAR16 *String,
- OUT CHAR16 **EndPointer, OPTIONAL
- OUT IPv4_ADDRESS *Address,
- OUT UINT8 *PrefixLength OPTIONAL
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer OPTIONAL,
+ OUT IPv4_ADDRESS *Address,
+ OUT UINT8 *PrefixLength OPTIONAL
)
{
- RETURN_STATUS Status;
- UINTN AddressIndex;
- UINTN Uintn;
- IPv4_ADDRESS LocalAddress;
- UINT8 LocalPrefixLength;
- CHAR16 *Pointer;
+ RETURN_STATUS Status;
+ UINTN AddressIndex;
+ UINTN Uintn;
+ IPv4_ADDRESS LocalAddress;
+ UINT8 LocalPrefixLength;
+ CHAR16 *Pointer;
LocalPrefixLength = MAX_UINT8;
- ASSERT (((UINTN) String & BIT0) == 0);
+ ASSERT (((UINTN)String & BIT0) == 0);
//
// 1. None of String or Guid shall be a null pointer.
@@ -1336,7 +1372,7 @@ StrToIpv4Address (
SAFE_STRING_CONSTRAINT_CHECK ((String != NULL), RETURN_INVALID_PARAMETER);
SAFE_STRING_CONSTRAINT_CHECK ((Address != NULL), RETURN_INVALID_PARAMETER);
- for (Pointer = (CHAR16 *) String, AddressIndex = 0; AddressIndex < ARRAY_SIZE (Address->Addr) + 1;) {
+ for (Pointer = (CHAR16 *)String, AddressIndex = 0; AddressIndex < ARRAY_SIZE (Address->Addr) + 1;) {
if (!InternalIsDecimalDigitCharacter (*Pointer)) {
//
// D or P contains invalid characters.
@@ -1347,10 +1383,11 @@ StrToIpv4Address (
//
// Get D or P.
//
- Status = StrDecimalToUintnS ((CONST CHAR16 *) Pointer, &Pointer, &Uintn);
+ Status = StrDecimalToUintnS ((CONST CHAR16 *)Pointer, &Pointer, &Uintn);
if (RETURN_ERROR (Status)) {
return RETURN_UNSUPPORTED;
}
+
if (AddressIndex == ARRAY_SIZE (Address->Addr)) {
//
// It's P.
@@ -1358,7 +1395,8 @@ StrToIpv4Address (
if (Uintn > 32) {
return RETURN_UNSUPPORTED;
}
- LocalPrefixLength = (UINT8) Uintn;
+
+ LocalPrefixLength = (UINT8)Uintn;
} else {
//
// It's D.
@@ -1366,7 +1404,8 @@ StrToIpv4Address (
if (Uintn > MAX_UINT8) {
return RETURN_UNSUPPORTED;
}
- LocalAddress.Addr[AddressIndex] = (UINT8) Uintn;
+
+ LocalAddress.Addr[AddressIndex] = (UINT8)Uintn;
AddressIndex++;
}
@@ -1406,6 +1445,7 @@ StrToIpv4Address (
if (PrefixLength != NULL) {
*PrefixLength = LocalPrefixLength;
}
+
if (EndPointer != NULL) {
*EndPointer = Pointer;
}
@@ -1458,14 +1498,14 @@ StrToIpv4Address (
RETURN_STATUS
EFIAPI
StrToGuid (
- IN CONST CHAR16 *String,
- OUT GUID *Guid
+ IN CONST CHAR16 *String,
+ OUT GUID *Guid
)
{
- RETURN_STATUS Status;
- GUID LocalGuid;
+ RETURN_STATUS Status;
+ GUID LocalGuid;
- ASSERT (((UINTN) String & BIT0) == 0);
+ ASSERT (((UINTN)String & BIT0) == 0);
//
// 1. None of String or Guid shall be a null pointer.
@@ -1476,49 +1516,53 @@ StrToGuid (
//
// Get aabbccdd in big-endian.
//
- Status = StrHexToBytes (String, 2 * sizeof (LocalGuid.Data1), (UINT8 *) &LocalGuid.Data1, sizeof (LocalGuid.Data1));
- if (RETURN_ERROR (Status) || String[2 * sizeof (LocalGuid.Data1)] != L'-') {
+ Status = StrHexToBytes (String, 2 * sizeof (LocalGuid.Data1), (UINT8 *)&LocalGuid.Data1, sizeof (LocalGuid.Data1));
+ if (RETURN_ERROR (Status) || (String[2 * sizeof (LocalGuid.Data1)] != L'-')) {
return RETURN_UNSUPPORTED;
}
+
//
// Convert big-endian to little-endian.
//
LocalGuid.Data1 = SwapBytes32 (LocalGuid.Data1);
- String += 2 * sizeof (LocalGuid.Data1) + 1;
+ String += 2 * sizeof (LocalGuid.Data1) + 1;
//
// Get eeff in big-endian.
//
- Status = StrHexToBytes (String, 2 * sizeof (LocalGuid.Data2), (UINT8 *) &LocalGuid.Data2, sizeof (LocalGuid.Data2));
- if (RETURN_ERROR (Status) || String[2 * sizeof (LocalGuid.Data2)] != L'-') {
+ Status = StrHexToBytes (String, 2 * sizeof (LocalGuid.Data2), (UINT8 *)&LocalGuid.Data2, sizeof (LocalGuid.Data2));
+ if (RETURN_ERROR (Status) || (String[2 * sizeof (LocalGuid.Data2)] != L'-')) {
return RETURN_UNSUPPORTED;
}
+
//
// Convert big-endian to little-endian.
//
LocalGuid.Data2 = SwapBytes16 (LocalGuid.Data2);
- String += 2 * sizeof (LocalGuid.Data2) + 1;
+ String += 2 * sizeof (LocalGuid.Data2) + 1;
//
// Get gghh in big-endian.
//
- Status = StrHexToBytes (String, 2 * sizeof (LocalGuid.Data3), (UINT8 *) &LocalGuid.Data3, sizeof (LocalGuid.Data3));
- if (RETURN_ERROR (Status) || String[2 * sizeof (LocalGuid.Data3)] != L'-') {
+ Status = StrHexToBytes (String, 2 * sizeof (LocalGuid.Data3), (UINT8 *)&LocalGuid.Data3, sizeof (LocalGuid.Data3));
+ if (RETURN_ERROR (Status) || (String[2 * sizeof (LocalGuid.Data3)] != L'-')) {
return RETURN_UNSUPPORTED;
}
+
//
// Convert big-endian to little-endian.
//
LocalGuid.Data3 = SwapBytes16 (LocalGuid.Data3);
- String += 2 * sizeof (LocalGuid.Data3) + 1;
+ String += 2 * sizeof (LocalGuid.Data3) + 1;
//
// Get iijj.
//
Status = StrHexToBytes (String, 2 * 2, &LocalGuid.Data4[0], 2);
- if (RETURN_ERROR (Status) || String[2 * 2] != L'-') {
+ if (RETURN_ERROR (Status) || (String[2 * 2] != L'-')) {
return RETURN_UNSUPPORTED;
}
+
String += 2 * 2 + 1;
//
@@ -1569,15 +1613,15 @@ StrToGuid (
RETURN_STATUS
EFIAPI
StrHexToBytes (
- IN CONST CHAR16 *String,
- IN UINTN Length,
- OUT UINT8 *Buffer,
- IN UINTN MaxBufferSize
+ IN CONST CHAR16 *String,
+ IN UINTN Length,
+ OUT UINT8 *Buffer,
+ IN UINTN MaxBufferSize
)
{
- UINTN Index;
+ UINTN Index;
- ASSERT (((UINTN) String & BIT0) == 0);
+ ASSERT (((UINTN)String & BIT0) == 0);
//
// 1. None of String or Buffer shall be a null pointer.
@@ -1610,6 +1654,7 @@ StrHexToBytes (
break;
}
}
+
if (Index != Length) {
return RETURN_UNSUPPORTED;
}
@@ -1617,18 +1662,18 @@ StrHexToBytes (
//
// Convert the hex string to bytes.
//
- for(Index = 0; Index < Length; Index++) {
-
+ for (Index = 0; Index < Length; Index++) {
//
// For even characters, write the upper nibble for each buffer byte,
// and for even characters, the lower nibble.
//
if ((Index & BIT0) == 0) {
- Buffer[Index / 2] = (UINT8) InternalHexCharToUintn (String[Index]) << 4;
+ Buffer[Index / 2] = (UINT8)InternalHexCharToUintn (String[Index]) << 4;
} else {
- Buffer[Index / 2] |= (UINT8) InternalHexCharToUintn (String[Index]);
+ Buffer[Index / 2] |= (UINT8)InternalHexCharToUintn (String[Index]);
}
}
+
return RETURN_SUCCESS;
}
@@ -1649,11 +1694,11 @@ StrHexToBytes (
UINTN
EFIAPI
AsciiStrnLenS (
- IN CONST CHAR8 *String,
- IN UINTN MaxSize
+ IN CONST CHAR8 *String,
+ IN UINTN MaxSize
)
{
- UINTN Length;
+ UINTN Length;
//
// If String is a null pointer or MaxSize is 0, then the AsciiStrnLenS function returns zero.
@@ -1673,8 +1718,10 @@ AsciiStrnLenS (
if (Length >= MaxSize - 1) {
return MaxSize;
}
+
Length++;
}
+
return Length;
}
@@ -1700,8 +1747,8 @@ AsciiStrnLenS (
UINTN
EFIAPI
AsciiStrnSizeS (
- IN CONST CHAR8 *String,
- IN UINTN MaxSize
+ IN CONST CHAR8 *String,
+ IN UINTN MaxSize
)
{
//
@@ -1753,7 +1800,7 @@ AsciiStrCpyS (
IN CONST CHAR8 *Source
)
{
- UINTN SourceLen;
+ UINTN SourceLen;
//
// 1. Neither Destination nor Source shall be a null pointer.
@@ -1791,6 +1838,7 @@ AsciiStrCpyS (
while (*Source != 0) {
*(Destination++) = *(Source++);
}
+
*Destination = 0;
return RETURN_SUCCESS;
@@ -1831,7 +1879,7 @@ AsciiStrnCpyS (
IN UINTN Length
)
{
- UINTN SourceLen;
+ UINTN SourceLen;
//
// 1. Neither Destination nor Source shall be a null pointer.
@@ -1866,6 +1914,7 @@ AsciiStrnCpyS (
if (SourceLen > Length) {
SourceLen = Length;
}
+
SAFE_STRING_CONSTRAINT_CHECK (InternalSafeStringNoAsciiStrOverlap (Destination, DestMax, (CHAR8 *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);
//
@@ -1878,6 +1927,7 @@ AsciiStrnCpyS (
*(Destination++) = *(Source++);
SourceLen--;
}
+
*Destination = 0;
return RETURN_SUCCESS;
@@ -1917,9 +1967,9 @@ AsciiStrCatS (
IN CONST CHAR8 *Source
)
{
- UINTN DestLen;
- UINTN CopyLen;
- UINTN SourceLen;
+ UINTN DestLen;
+ UINTN CopyLen;
+ UINTN SourceLen;
//
// Let CopyLen denote the value DestMax - AsciiStrnLenS(Destination, DestMax) upon entry to AsciiStrCatS.
@@ -1970,6 +2020,7 @@ AsciiStrCatS (
while (*Source != 0) {
*(Destination++) = *(Source++);
}
+
*Destination = 0;
return RETURN_SUCCESS;
@@ -2013,9 +2064,9 @@ AsciiStrnCatS (
IN UINTN Length
)
{
- UINTN DestLen;
- UINTN CopyLen;
- UINTN SourceLen;
+ UINTN DestLen;
+ UINTN CopyLen;
+ UINTN SourceLen;
//
// Let CopyLen denote the value DestMax - AsciiStrnLenS(Destination, DestMax) upon entry to AsciiStrnCatS.
@@ -2061,6 +2112,7 @@ AsciiStrnCatS (
if (SourceLen > Length) {
SourceLen = Length;
}
+
SAFE_STRING_CONSTRAINT_CHECK (InternalSafeStringNoAsciiStrOverlap (Destination, DestMax, (CHAR8 *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);
//
@@ -2075,6 +2127,7 @@ AsciiStrnCatS (
*(Destination++) = *(Source++);
SourceLen--;
}
+
*Destination = 0;
return RETURN_SUCCESS;
@@ -2124,9 +2177,9 @@ AsciiStrnCatS (
RETURN_STATUS
EFIAPI
AsciiStrDecimalToUintnS (
- IN CONST CHAR8 *String,
- OUT CHAR8 **EndPointer, OPTIONAL
- OUT UINTN *Data
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer OPTIONAL,
+ OUT UINTN *Data
)
{
//
@@ -2143,7 +2196,7 @@ AsciiStrDecimalToUintnS (
}
if (EndPointer != NULL) {
- *EndPointer = (CHAR8 *) String;
+ *EndPointer = (CHAR8 *)String;
}
//
@@ -2171,8 +2224,9 @@ AsciiStrDecimalToUintnS (
if (*Data > ((MAX_UINTN - (*String - '0')) / 10)) {
*Data = MAX_UINTN;
if (EndPointer != NULL) {
- *EndPointer = (CHAR8 *) String;
+ *EndPointer = (CHAR8 *)String;
}
+
return RETURN_UNSUPPORTED;
}
@@ -2181,8 +2235,9 @@ AsciiStrDecimalToUintnS (
}
if (EndPointer != NULL) {
- *EndPointer = (CHAR8 *) String;
+ *EndPointer = (CHAR8 *)String;
}
+
return RETURN_SUCCESS;
}
@@ -2230,9 +2285,9 @@ AsciiStrDecimalToUintnS (
RETURN_STATUS
EFIAPI
AsciiStrDecimalToUint64S (
- IN CONST CHAR8 *String,
- OUT CHAR8 **EndPointer, OPTIONAL
- OUT UINT64 *Data
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer OPTIONAL,
+ OUT UINT64 *Data
)
{
//
@@ -2249,7 +2304,7 @@ AsciiStrDecimalToUint64S (
}
if (EndPointer != NULL) {
- *EndPointer = (CHAR8 *) String;
+ *EndPointer = (CHAR8 *)String;
}
//
@@ -2277,8 +2332,9 @@ AsciiStrDecimalToUint64S (
if (*Data > DivU64x32 (MAX_UINT64 - (*String - '0'), 10)) {
*Data = MAX_UINT64;
if (EndPointer != NULL) {
- *EndPointer = (CHAR8 *) String;
+ *EndPointer = (CHAR8 *)String;
}
+
return RETURN_UNSUPPORTED;
}
@@ -2287,8 +2343,9 @@ AsciiStrDecimalToUint64S (
}
if (EndPointer != NULL) {
- *EndPointer = (CHAR8 *) String;
+ *EndPointer = (CHAR8 *)String;
}
+
return RETURN_SUCCESS;
}
@@ -2340,11 +2397,14 @@ AsciiStrDecimalToUint64S (
RETURN_STATUS
EFIAPI
AsciiStrHexToUintnS (
- IN CONST CHAR8 *String,
- OUT CHAR8 **EndPointer, OPTIONAL
- OUT UINTN *Data
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer OPTIONAL,
+ OUT UINTN *Data
)
{
+ BOOLEAN FoundLeadingZero;
+
+ FoundLeadingZero = FALSE;
//
// 1. Neither String nor Data shall be a null pointer.
//
@@ -2359,7 +2419,7 @@ AsciiStrHexToUintnS (
}
if (EndPointer != NULL) {
- *EndPointer = (CHAR8 *) String;
+ *EndPointer = (CHAR8 *)String;
}
//
@@ -2372,15 +2432,17 @@ AsciiStrHexToUintnS (
//
// Ignore leading Zeros after the spaces
//
+ FoundLeadingZero = *String == '0';
while (*String == '0') {
String++;
}
if (AsciiCharToUpper (*String) == 'X') {
- if (*(String - 1) != '0') {
+ if (!FoundLeadingZero) {
*Data = 0;
return RETURN_SUCCESS;
}
+
//
// Skip the 'X'
//
@@ -2398,8 +2460,9 @@ AsciiStrHexToUintnS (
if (*Data > ((MAX_UINTN - InternalAsciiHexCharToUintn (*String)) >> 4)) {
*Data = MAX_UINTN;
if (EndPointer != NULL) {
- *EndPointer = (CHAR8 *) String;
+ *EndPointer = (CHAR8 *)String;
}
+
return RETURN_UNSUPPORTED;
}
@@ -2408,8 +2471,9 @@ AsciiStrHexToUintnS (
}
if (EndPointer != NULL) {
- *EndPointer = (CHAR8 *) String;
+ *EndPointer = (CHAR8 *)String;
}
+
return RETURN_SUCCESS;
}
@@ -2461,11 +2525,14 @@ AsciiStrHexToUintnS (
RETURN_STATUS
EFIAPI
AsciiStrHexToUint64S (
- IN CONST CHAR8 *String,
- OUT CHAR8 **EndPointer, OPTIONAL
- OUT UINT64 *Data
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer OPTIONAL,
+ OUT UINT64 *Data
)
{
+ BOOLEAN FoundLeadingZero;
+
+ FoundLeadingZero = FALSE;
//
// 1. Neither String nor Data shall be a null pointer.
//
@@ -2480,7 +2547,7 @@ AsciiStrHexToUint64S (
}
if (EndPointer != NULL) {
- *EndPointer = (CHAR8 *) String;
+ *EndPointer = (CHAR8 *)String;
}
//
@@ -2493,15 +2560,17 @@ AsciiStrHexToUint64S (
//
// Ignore leading Zeros after the spaces
//
+ FoundLeadingZero = *String == '0';
while (*String == '0') {
String++;
}
if (AsciiCharToUpper (*String) == 'X') {
- if (*(String - 1) != '0') {
+ if (!FoundLeadingZero) {
*Data = 0;
return RETURN_SUCCESS;
}
+
//
// Skip the 'X'
//
@@ -2519,8 +2588,9 @@ AsciiStrHexToUint64S (
if (*Data > RShiftU64 (MAX_UINT64 - InternalAsciiHexCharToUintn (*String), 4)) {
*Data = MAX_UINT64;
if (EndPointer != NULL) {
- *EndPointer = (CHAR8 *) String;
+ *EndPointer = (CHAR8 *)String;
}
+
return RETURN_UNSUPPORTED;
}
@@ -2529,8 +2599,9 @@ AsciiStrHexToUint64S (
}
if (EndPointer != NULL) {
- *EndPointer = (CHAR8 *) String;
+ *EndPointer = (CHAR8 *)String;
}
+
return RETURN_SUCCESS;
}
@@ -2577,14 +2648,14 @@ AsciiStrHexToUint64S (
RETURN_STATUS
EFIAPI
UnicodeStrToAsciiStrS (
- IN CONST CHAR16 *Source,
- OUT CHAR8 *Destination,
- IN UINTN DestMax
+ IN CONST CHAR16 *Source,
+ OUT CHAR8 *Destination,
+ IN UINTN DestMax
)
{
- UINTN SourceLen;
+ UINTN SourceLen;
- ASSERT (((UINTN) Source & BIT0) == 0);
+ ASSERT (((UINTN)Source & BIT0) == 0);
//
// 1. Neither Destination nor Source shall be a null pointer.
@@ -2598,6 +2669,7 @@ UnicodeStrToAsciiStrS (
if (ASCII_RSIZE_MAX != 0) {
SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
}
+
if (RSIZE_MAX != 0) {
SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
}
@@ -2616,7 +2688,7 @@ UnicodeStrToAsciiStrS (
//
// 5. Copying shall not take place between objects that overlap.
//
- SAFE_STRING_CONSTRAINT_CHECK (!InternalSafeStringIsOverlap (Destination, DestMax, (VOID *)Source, (SourceLen + 1) * sizeof(CHAR16)), RETURN_ACCESS_DENIED);
+ SAFE_STRING_CONSTRAINT_CHECK (!InternalSafeStringIsOverlap (Destination, DestMax, (VOID *)Source, (SourceLen + 1) * sizeof (CHAR16)), RETURN_ACCESS_DENIED);
//
// convert string
@@ -2627,8 +2699,9 @@ UnicodeStrToAsciiStrS (
// non-zero value in the upper 8 bits, then ASSERT().
//
ASSERT (*Source < 0x100);
- *(Destination++) = (CHAR8) *(Source++);
+ *(Destination++) = (CHAR8)*(Source++);
}
+
*Destination = '\0';
return RETURN_SUCCESS;
@@ -2682,16 +2755,16 @@ UnicodeStrToAsciiStrS (
RETURN_STATUS
EFIAPI
UnicodeStrnToAsciiStrS (
- IN CONST CHAR16 *Source,
- IN UINTN Length,
- OUT CHAR8 *Destination,
- IN UINTN DestMax,
- OUT UINTN *DestinationLength
+ IN CONST CHAR16 *Source,
+ IN UINTN Length,
+ OUT CHAR8 *Destination,
+ IN UINTN DestMax,
+ OUT UINTN *DestinationLength
)
{
- UINTN SourceLen;
+ UINTN SourceLen;
- ASSERT (((UINTN) Source & BIT0) == 0);
+ ASSERT (((UINTN)Source & BIT0) == 0);
//
// 1. None of Destination, Source or DestinationLength shall be a null
@@ -2709,6 +2782,7 @@ UnicodeStrnToAsciiStrS (
SAFE_STRING_CONSTRAINT_CHECK ((Length <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
}
+
if (RSIZE_MAX != 0) {
SAFE_STRING_CONSTRAINT_CHECK ((Length <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
@@ -2734,7 +2808,8 @@ UnicodeStrnToAsciiStrS (
if (SourceLen > Length) {
SourceLen = Length;
}
- SAFE_STRING_CONSTRAINT_CHECK (!InternalSafeStringIsOverlap (Destination, DestMax, (VOID *)Source, (SourceLen + 1) * sizeof(CHAR16)), RETURN_ACCESS_DENIED);
+
+ SAFE_STRING_CONSTRAINT_CHECK (!InternalSafeStringIsOverlap (Destination, DestMax, (VOID *)Source, (SourceLen + 1) * sizeof (CHAR16)), RETURN_ACCESS_DENIED);
*DestinationLength = 0;
@@ -2747,10 +2822,11 @@ UnicodeStrnToAsciiStrS (
// 8 bits, then ASSERT().
//
ASSERT (*Source < 0x100);
- *(Destination++) = (CHAR8) *(Source++);
+ *(Destination++) = (CHAR8)*(Source++);
SourceLen--;
(*DestinationLength)++;
}
+
*Destination = 0;
return RETURN_SUCCESS;
@@ -2795,14 +2871,14 @@ UnicodeStrnToAsciiStrS (
RETURN_STATUS
EFIAPI
AsciiStrToUnicodeStrS (
- IN CONST CHAR8 *Source,
- OUT CHAR16 *Destination,
- IN UINTN DestMax
+ IN CONST CHAR8 *Source,
+ OUT CHAR16 *Destination,
+ IN UINTN DestMax
)
{
- UINTN SourceLen;
+ UINTN SourceLen;
- ASSERT (((UINTN) Destination & BIT0) == 0);
+ ASSERT (((UINTN)Destination & BIT0) == 0);
//
// 1. Neither Destination nor Source shall be a null pointer.
@@ -2816,6 +2892,7 @@ AsciiStrToUnicodeStrS (
if (RSIZE_MAX != 0) {
SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
}
+
if (ASCII_RSIZE_MAX != 0) {
SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
}
@@ -2834,7 +2911,7 @@ AsciiStrToUnicodeStrS (
//
// 5. Copying shall not take place between objects that overlap.
//
- SAFE_STRING_CONSTRAINT_CHECK (!InternalSafeStringIsOverlap (Destination, DestMax * sizeof(CHAR16), (VOID *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);
+ SAFE_STRING_CONSTRAINT_CHECK (!InternalSafeStringIsOverlap (Destination, DestMax * sizeof (CHAR16), (VOID *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);
//
// Convert string
@@ -2842,6 +2919,7 @@ AsciiStrToUnicodeStrS (
while (*Source != '\0') {
*(Destination++) = (CHAR16)(UINT8)*(Source++);
}
+
*Destination = '\0';
return RETURN_SUCCESS;
@@ -2892,16 +2970,16 @@ AsciiStrToUnicodeStrS (
RETURN_STATUS
EFIAPI
AsciiStrnToUnicodeStrS (
- IN CONST CHAR8 *Source,
- IN UINTN Length,
- OUT CHAR16 *Destination,
- IN UINTN DestMax,
- OUT UINTN *DestinationLength
+ IN CONST CHAR8 *Source,
+ IN UINTN Length,
+ OUT CHAR16 *Destination,
+ IN UINTN DestMax,
+ OUT UINTN *DestinationLength
)
{
- UINTN SourceLen;
+ UINTN SourceLen;
- ASSERT (((UINTN) Destination & BIT0) == 0);
+ ASSERT (((UINTN)Destination & BIT0) == 0);
//
// 1. None of Destination, Source or DestinationLength shall be a null
@@ -2919,6 +2997,7 @@ AsciiStrnToUnicodeStrS (
SAFE_STRING_CONSTRAINT_CHECK ((Length <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= RSIZE_MAX), RETURN_INVALID_PARAMETER);
}
+
if (ASCII_RSIZE_MAX != 0) {
SAFE_STRING_CONSTRAINT_CHECK ((Length <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);
@@ -2944,7 +3023,8 @@ AsciiStrnToUnicodeStrS (
if (SourceLen > Length) {
SourceLen = Length;
}
- SAFE_STRING_CONSTRAINT_CHECK (!InternalSafeStringIsOverlap (Destination, DestMax * sizeof(CHAR16), (VOID *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);
+
+ SAFE_STRING_CONSTRAINT_CHECK (!InternalSafeStringIsOverlap (Destination, DestMax * sizeof (CHAR16), (VOID *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);
*DestinationLength = 0;
@@ -2956,6 +3036,7 @@ AsciiStrnToUnicodeStrS (
SourceLen--;
(*DestinationLength)++;
}
+
*Destination = 0;
return RETURN_SUCCESS;
@@ -3012,21 +3093,21 @@ AsciiStrnToUnicodeStrS (
RETURN_STATUS
EFIAPI
AsciiStrToIpv6Address (
- IN CONST CHAR8 *String,
- OUT CHAR8 **EndPointer, OPTIONAL
- OUT IPv6_ADDRESS *Address,
- OUT UINT8 *PrefixLength OPTIONAL
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer OPTIONAL,
+ OUT IPv6_ADDRESS *Address,
+ OUT UINT8 *PrefixLength OPTIONAL
)
{
- RETURN_STATUS Status;
- UINTN AddressIndex;
- UINTN Uintn;
- IPv6_ADDRESS LocalAddress;
- UINT8 LocalPrefixLength;
- CONST CHAR8 *Pointer;
- CHAR8 *End;
- UINTN CompressStart;
- BOOLEAN ExpectPrefix;
+ RETURN_STATUS Status;
+ UINTN AddressIndex;
+ UINTN Uintn;
+ IPv6_ADDRESS LocalAddress;
+ UINT8 LocalPrefixLength;
+ CONST CHAR8 *Pointer;
+ CHAR8 *End;
+ UINTN CompressStart;
+ BOOLEAN ExpectPrefix;
LocalPrefixLength = MAX_UINT8;
CompressStart = ARRAY_SIZE (Address->Addr);
@@ -3058,7 +3139,7 @@ AsciiStrToIpv6Address (
return RETURN_UNSUPPORTED;
}
- if (CompressStart != ARRAY_SIZE (Address->Addr) || AddressIndex == ARRAY_SIZE (Address->Addr)) {
+ if ((CompressStart != ARRAY_SIZE (Address->Addr)) || (AddressIndex == ARRAY_SIZE (Address->Addr))) {
//
// "::" can only appear once.
// "::" can only appear when address is not full length.
@@ -3078,6 +3159,7 @@ AsciiStrToIpv6Address (
//
return RETURN_UNSUPPORTED;
}
+
Pointer++;
}
}
@@ -3100,33 +3182,35 @@ AsciiStrToIpv6Address (
// Get X.
//
Status = AsciiStrHexToUintnS (Pointer, &End, &Uintn);
- if (RETURN_ERROR (Status) || End - Pointer > 4) {
+ if (RETURN_ERROR (Status) || (End - Pointer > 4)) {
//
// Number of hexadecimal digit characters is no more than 4.
//
return RETURN_UNSUPPORTED;
}
+
Pointer = End;
//
// Uintn won't exceed MAX_UINT16 if number of hexadecimal digit characters is no more than 4.
//
ASSERT (AddressIndex + 1 < ARRAY_SIZE (Address->Addr));
- LocalAddress.Addr[AddressIndex] = (UINT8) ((UINT16) Uintn >> 8);
- LocalAddress.Addr[AddressIndex + 1] = (UINT8) Uintn;
- AddressIndex += 2;
+ LocalAddress.Addr[AddressIndex] = (UINT8)((UINT16)Uintn >> 8);
+ LocalAddress.Addr[AddressIndex + 1] = (UINT8)Uintn;
+ AddressIndex += 2;
} else {
//
// Get P, then exit the loop.
//
Status = AsciiStrDecimalToUintnS (Pointer, &End, &Uintn);
- if (RETURN_ERROR (Status) || End == Pointer || Uintn > 128) {
+ if (RETURN_ERROR (Status) || (End == Pointer) || (Uintn > 128)) {
//
// Prefix length should not exceed 128.
//
return RETURN_UNSUPPORTED;
}
- LocalPrefixLength = (UINT8) Uintn;
- Pointer = End;
+
+ LocalPrefixLength = (UINT8)Uintn;
+ Pointer = End;
break;
}
}
@@ -3149,18 +3233,21 @@ AsciiStrToIpv6Address (
//
break;
}
+
Pointer++;
}
- if ((AddressIndex == ARRAY_SIZE (Address->Addr) && CompressStart != ARRAY_SIZE (Address->Addr)) ||
- (AddressIndex != ARRAY_SIZE (Address->Addr) && CompressStart == ARRAY_SIZE (Address->Addr))
- ) {
+ if (((AddressIndex == ARRAY_SIZE (Address->Addr)) && (CompressStart != ARRAY_SIZE (Address->Addr))) ||
+ ((AddressIndex != ARRAY_SIZE (Address->Addr)) && (CompressStart == ARRAY_SIZE (Address->Addr)))
+ )
+ {
//
// Full length of address shall not have compressing zeros.
// Non-full length of address shall have compressing zeros.
//
return RETURN_UNSUPPORTED;
}
+
CopyMem (&Address->Addr[0], &LocalAddress.Addr[0], CompressStart);
ZeroMem (&Address->Addr[CompressStart], ARRAY_SIZE (Address->Addr) - AddressIndex);
if (AddressIndex > CompressStart) {
@@ -3169,14 +3256,14 @@ AsciiStrToIpv6Address (
&LocalAddress.Addr[CompressStart],
AddressIndex - CompressStart
);
-
}
if (PrefixLength != NULL) {
*PrefixLength = LocalPrefixLength;
}
+
if (EndPointer != NULL) {
- *EndPointer = (CHAR8 *) Pointer;
+ *EndPointer = (CHAR8 *)Pointer;
}
return RETURN_SUCCESS;
@@ -3224,18 +3311,18 @@ AsciiStrToIpv6Address (
RETURN_STATUS
EFIAPI
AsciiStrToIpv4Address (
- IN CONST CHAR8 *String,
- OUT CHAR8 **EndPointer, OPTIONAL
- OUT IPv4_ADDRESS *Address,
- OUT UINT8 *PrefixLength OPTIONAL
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer OPTIONAL,
+ OUT IPv4_ADDRESS *Address,
+ OUT UINT8 *PrefixLength OPTIONAL
)
{
- RETURN_STATUS Status;
- UINTN AddressIndex;
- UINTN Uintn;
- IPv4_ADDRESS LocalAddress;
- UINT8 LocalPrefixLength;
- CHAR8 *Pointer;
+ RETURN_STATUS Status;
+ UINTN AddressIndex;
+ UINTN Uintn;
+ IPv4_ADDRESS LocalAddress;
+ UINT8 LocalPrefixLength;
+ CHAR8 *Pointer;
LocalPrefixLength = MAX_UINT8;
@@ -3245,7 +3332,7 @@ AsciiStrToIpv4Address (
SAFE_STRING_CONSTRAINT_CHECK ((String != NULL), RETURN_INVALID_PARAMETER);
SAFE_STRING_CONSTRAINT_CHECK ((Address != NULL), RETURN_INVALID_PARAMETER);
- for (Pointer = (CHAR8 *) String, AddressIndex = 0; AddressIndex < ARRAY_SIZE (Address->Addr) + 1;) {
+ for (Pointer = (CHAR8 *)String, AddressIndex = 0; AddressIndex < ARRAY_SIZE (Address->Addr) + 1;) {
if (!InternalAsciiIsDecimalDigitCharacter (*Pointer)) {
//
// D or P contains invalid characters.
@@ -3256,10 +3343,11 @@ AsciiStrToIpv4Address (
//
// Get D or P.
//
- Status = AsciiStrDecimalToUintnS ((CONST CHAR8 *) Pointer, &Pointer, &Uintn);
+ Status = AsciiStrDecimalToUintnS ((CONST CHAR8 *)Pointer, &Pointer, &Uintn);
if (RETURN_ERROR (Status)) {
return RETURN_UNSUPPORTED;
}
+
if (AddressIndex == ARRAY_SIZE (Address->Addr)) {
//
// It's P.
@@ -3267,7 +3355,8 @@ AsciiStrToIpv4Address (
if (Uintn > 32) {
return RETURN_UNSUPPORTED;
}
- LocalPrefixLength = (UINT8) Uintn;
+
+ LocalPrefixLength = (UINT8)Uintn;
} else {
//
// It's D.
@@ -3275,7 +3364,8 @@ AsciiStrToIpv4Address (
if (Uintn > MAX_UINT8) {
return RETURN_UNSUPPORTED;
}
- LocalAddress.Addr[AddressIndex] = (UINT8) Uintn;
+
+ LocalAddress.Addr[AddressIndex] = (UINT8)Uintn;
AddressIndex++;
}
@@ -3315,6 +3405,7 @@ AsciiStrToIpv4Address (
if (PrefixLength != NULL) {
*PrefixLength = LocalPrefixLength;
}
+
if (EndPointer != NULL) {
*EndPointer = Pointer;
}
@@ -3365,12 +3456,12 @@ AsciiStrToIpv4Address (
RETURN_STATUS
EFIAPI
AsciiStrToGuid (
- IN CONST CHAR8 *String,
- OUT GUID *Guid
+ IN CONST CHAR8 *String,
+ OUT GUID *Guid
)
{
- RETURN_STATUS Status;
- GUID LocalGuid;
+ RETURN_STATUS Status;
+ GUID LocalGuid;
//
// None of String or Guid shall be a null pointer.
@@ -3381,49 +3472,53 @@ AsciiStrToGuid (
//
// Get aabbccdd in big-endian.
//
- Status = AsciiStrHexToBytes (String, 2 * sizeof (LocalGuid.Data1), (UINT8 *) &LocalGuid.Data1, sizeof (LocalGuid.Data1));
- if (RETURN_ERROR (Status) || String[2 * sizeof (LocalGuid.Data1)] != '-') {
+ Status = AsciiStrHexToBytes (String, 2 * sizeof (LocalGuid.Data1), (UINT8 *)&LocalGuid.Data1, sizeof (LocalGuid.Data1));
+ if (RETURN_ERROR (Status) || (String[2 * sizeof (LocalGuid.Data1)] != '-')) {
return RETURN_UNSUPPORTED;
}
+
//
// Convert big-endian to little-endian.
//
LocalGuid.Data1 = SwapBytes32 (LocalGuid.Data1);
- String += 2 * sizeof (LocalGuid.Data1) + 1;
+ String += 2 * sizeof (LocalGuid.Data1) + 1;
//
// Get eeff in big-endian.
//
- Status = AsciiStrHexToBytes (String, 2 * sizeof (LocalGuid.Data2), (UINT8 *) &LocalGuid.Data2, sizeof (LocalGuid.Data2));
- if (RETURN_ERROR (Status) || String[2 * sizeof (LocalGuid.Data2)] != '-') {
+ Status = AsciiStrHexToBytes (String, 2 * sizeof (LocalGuid.Data2), (UINT8 *)&LocalGuid.Data2, sizeof (LocalGuid.Data2));
+ if (RETURN_ERROR (Status) || (String[2 * sizeof (LocalGuid.Data2)] != '-')) {
return RETURN_UNSUPPORTED;
}
+
//
// Convert big-endian to little-endian.
//
LocalGuid.Data2 = SwapBytes16 (LocalGuid.Data2);
- String += 2 * sizeof (LocalGuid.Data2) + 1;
+ String += 2 * sizeof (LocalGuid.Data2) + 1;
//
// Get gghh in big-endian.
//
- Status = AsciiStrHexToBytes (String, 2 * sizeof (LocalGuid.Data3), (UINT8 *) &LocalGuid.Data3, sizeof (LocalGuid.Data3));
- if (RETURN_ERROR (Status) || String[2 * sizeof (LocalGuid.Data3)] != '-') {
+ Status = AsciiStrHexToBytes (String, 2 * sizeof (LocalGuid.Data3), (UINT8 *)&LocalGuid.Data3, sizeof (LocalGuid.Data3));
+ if (RETURN_ERROR (Status) || (String[2 * sizeof (LocalGuid.Data3)] != '-')) {
return RETURN_UNSUPPORTED;
}
+
//
// Convert big-endian to little-endian.
//
LocalGuid.Data3 = SwapBytes16 (LocalGuid.Data3);
- String += 2 * sizeof (LocalGuid.Data3) + 1;
+ String += 2 * sizeof (LocalGuid.Data3) + 1;
//
// Get iijj.
//
Status = AsciiStrHexToBytes (String, 2 * 2, &LocalGuid.Data4[0], 2);
- if (RETURN_ERROR (Status) || String[2 * 2] != '-') {
+ if (RETURN_ERROR (Status) || (String[2 * 2] != '-')) {
return RETURN_UNSUPPORTED;
}
+
String += 2 * 2 + 1;
//
@@ -3472,13 +3567,13 @@ AsciiStrToGuid (
RETURN_STATUS
EFIAPI
AsciiStrHexToBytes (
- IN CONST CHAR8 *String,
- IN UINTN Length,
- OUT UINT8 *Buffer,
- IN UINTN MaxBufferSize
+ IN CONST CHAR8 *String,
+ IN UINTN Length,
+ OUT UINT8 *Buffer,
+ IN UINTN MaxBufferSize
)
{
- UINTN Index;
+ UINTN Index;
//
// 1. None of String or Buffer shall be a null pointer.
@@ -3511,6 +3606,7 @@ AsciiStrHexToBytes (
break;
}
}
+
if (Index != Length) {
return RETURN_UNSUPPORTED;
}
@@ -3518,18 +3614,17 @@ AsciiStrHexToBytes (
//
// Convert the hex string to bytes.
//
- for(Index = 0; Index < Length; Index++) {
-
+ for (Index = 0; Index < Length; Index++) {
//
// For even characters, write the upper nibble for each buffer byte,
// and for even characters, the lower nibble.
//
if ((Index & BIT0) == 0) {
- Buffer[Index / 2] = (UINT8) InternalAsciiHexCharToUintn (String[Index]) << 4;
+ Buffer[Index / 2] = (UINT8)InternalAsciiHexCharToUintn (String[Index]) << 4;
} else {
- Buffer[Index / 2] |= (UINT8) InternalAsciiHexCharToUintn (String[Index]);
+ Buffer[Index / 2] |= (UINT8)InternalAsciiHexCharToUintn (String[Index]);
}
}
+
return RETURN_SUCCESS;
}
-
diff --git a/MdePkg/Library/BaseLib/SetJump.c b/MdePkg/Library/BaseLib/SetJump.c
index 7edd9f13..0722cf2f 100644
--- a/MdePkg/Library/BaseLib/SetJump.c
+++ b/MdePkg/Library/BaseLib/SetJump.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
diff --git a/MdePkg/Library/BaseLib/String.c b/MdePkg/Library/BaseLib/String.c
index 08c8d40c..acd79643 100644
--- a/MdePkg/Library/BaseLib/String.c
+++ b/MdePkg/Library/BaseLib/String.c
@@ -8,7 +8,6 @@
#include "BaseLibInternals.h"
-
/**
Returns the length of a Null-terminated Unicode string.
@@ -29,13 +28,13 @@
UINTN
EFIAPI
StrLen (
- IN CONST CHAR16 *String
+ IN CONST CHAR16 *String
)
{
- UINTN Length;
+ UINTN Length;
ASSERT (String != NULL);
- ASSERT (((UINTN) String & BIT0) == 0);
+ ASSERT (((UINTN)String & BIT0) == 0);
for (Length = 0; *String != L'\0'; String++, Length++) {
//
@@ -46,6 +45,7 @@ StrLen (
ASSERT (Length < PcdGet32 (PcdMaximumUnicodeStringLength));
}
}
+
return Length;
}
@@ -70,7 +70,7 @@ StrLen (
UINTN
EFIAPI
StrSize (
- IN CONST CHAR16 *String
+ IN CONST CHAR16 *String
)
{
return (StrLen (String) + 1) * sizeof (*String);
@@ -107,8 +107,8 @@ StrSize (
INTN
EFIAPI
StrCmp (
- IN CONST CHAR16 *FirstString,
- IN CONST CHAR16 *SecondString
+ IN CONST CHAR16 *FirstString,
+ IN CONST CHAR16 *SecondString
)
{
//
@@ -121,6 +121,7 @@ StrCmp (
FirstString++;
SecondString++;
}
+
return *FirstString - *SecondString;
}
@@ -159,9 +160,9 @@ StrCmp (
INTN
EFIAPI
StrnCmp (
- IN CONST CHAR16 *FirstString,
- IN CONST CHAR16 *SecondString,
- IN UINTN Length
+ IN CONST CHAR16 *FirstString,
+ IN CONST CHAR16 *SecondString,
+ IN UINTN Length
)
{
if (Length == 0) {
@@ -182,7 +183,8 @@ StrnCmp (
while ((*FirstString != L'\0') &&
(*SecondString != L'\0') &&
(*FirstString == *SecondString) &&
- (Length > 1)) {
+ (Length > 1))
+ {
FirstString++;
SecondString++;
Length--;
@@ -191,7 +193,6 @@ StrnCmp (
return *FirstString - *SecondString;
}
-
/**
Returns the first occurrence of a Null-terminated Unicode sub-string
in a Null-terminated Unicode string.
@@ -221,12 +222,12 @@ StrnCmp (
CHAR16 *
EFIAPI
StrStr (
- IN CONST CHAR16 *String,
- IN CONST CHAR16 *SearchString
+ IN CONST CHAR16 *String,
+ IN CONST CHAR16 *SearchString
)
{
- CONST CHAR16 *FirstMatch;
- CONST CHAR16 *SearchStringTmp;
+ CONST CHAR16 *FirstMatch;
+ CONST CHAR16 *SearchStringTmp;
//
// ASSERT both strings are less long than PcdMaximumUnicodeStringLength.
@@ -236,21 +237,22 @@ StrStr (
ASSERT (StrSize (SearchString) != 0);
if (*SearchString == L'\0') {
- return (CHAR16 *) String;
+ return (CHAR16 *)String;
}
while (*String != L'\0') {
SearchStringTmp = SearchString;
- FirstMatch = String;
+ FirstMatch = String;
- while ((*String == *SearchStringTmp)
- && (*String != L'\0')) {
+ while ( (*String == *SearchStringTmp)
+ && (*String != L'\0'))
+ {
String++;
SearchStringTmp++;
}
if (*SearchStringTmp == L'\0') {
- return (CHAR16 *) FirstMatch;
+ return (CHAR16 *)FirstMatch;
}
if (*String == L'\0') {
@@ -279,10 +281,10 @@ StrStr (
BOOLEAN
EFIAPI
InternalIsDecimalDigitCharacter (
- IN CHAR16 Char
+ IN CHAR16 Char
)
{
- return (BOOLEAN) (Char >= L'0' && Char <= L'9');
+ return (BOOLEAN)(Char >= L'0' && Char <= L'9');
}
/**
@@ -303,11 +305,11 @@ InternalIsDecimalDigitCharacter (
CHAR16
EFIAPI
CharToUpper (
- IN CHAR16 Char
+ IN CHAR16 Char
)
{
- if (Char >= L'a' && Char <= L'z') {
- return (CHAR16) (Char - (L'a' - L'A'));
+ if ((Char >= L'a') && (Char <= L'z')) {
+ return (CHAR16)(Char - (L'a' - L'A'));
}
return Char;
@@ -329,7 +331,7 @@ CharToUpper (
UINTN
EFIAPI
InternalHexCharToUintn (
- IN CHAR16 Char
+ IN CHAR16 Char
)
{
if (InternalIsDecimalDigitCharacter (Char)) {
@@ -356,13 +358,12 @@ InternalHexCharToUintn (
BOOLEAN
EFIAPI
InternalIsHexaDecimalDigitCharacter (
- IN CHAR16 Char
+ IN CHAR16 Char
)
{
-
- return (BOOLEAN) (InternalIsDecimalDigitCharacter (Char) ||
- (Char >= L'A' && Char <= L'F') ||
- (Char >= L'a' && Char <= L'f'));
+ return (BOOLEAN)(InternalIsDecimalDigitCharacter (Char) ||
+ (Char >= L'A' && Char <= L'F') ||
+ (Char >= L'a' && Char <= L'f'));
}
/**
@@ -402,16 +403,18 @@ InternalIsHexaDecimalDigitCharacter (
UINTN
EFIAPI
StrDecimalToUintn (
- IN CONST CHAR16 *String
+ IN CONST CHAR16 *String
)
{
- UINTN Result;
+ UINTN Result;
+
+ if (RETURN_ERROR (StrDecimalToUintnS (String, (CHAR16 **)NULL, &Result))) {
+ return MAX_UINTN;
+ }
- StrDecimalToUintnS (String, (CHAR16 **) NULL, &Result);
return Result;
}
-
/**
Convert a Null-terminated Unicode decimal string to a value of
type UINT64.
@@ -449,12 +452,15 @@ StrDecimalToUintn (
UINT64
EFIAPI
StrDecimalToUint64 (
- IN CONST CHAR16 *String
+ IN CONST CHAR16 *String
)
{
- UINT64 Result;
+ UINT64 Result;
+
+ if (RETURN_ERROR (StrDecimalToUint64S (String, (CHAR16 **)NULL, &Result))) {
+ return MAX_UINT64;
+ }
- StrDecimalToUint64S (String, (CHAR16 **) NULL, &Result);
return Result;
}
@@ -496,16 +502,18 @@ StrDecimalToUint64 (
UINTN
EFIAPI
StrHexToUintn (
- IN CONST CHAR16 *String
+ IN CONST CHAR16 *String
)
{
- UINTN Result;
+ UINTN Result;
+
+ if (RETURN_ERROR (StrHexToUintnS (String, (CHAR16 **)NULL, &Result))) {
+ return MAX_UINTN;
+ }
- StrHexToUintnS (String, (CHAR16 **) NULL, &Result);
return Result;
}
-
/**
Convert a Null-terminated Unicode hexadecimal string to a value of type UINT64.
@@ -544,12 +552,15 @@ StrHexToUintn (
UINT64
EFIAPI
StrHexToUint64 (
- IN CONST CHAR16 *String
+ IN CONST CHAR16 *String
)
{
- UINT64 Result;
+ UINT64 Result;
+
+ if (RETURN_ERROR (StrHexToUint64S (String, (CHAR16 **)NULL, &Result))) {
+ return MAX_UINT64;
+ }
- StrHexToUint64S (String, (CHAR16 **) NULL, &Result);
return Result;
}
@@ -569,10 +580,10 @@ StrHexToUint64 (
BOOLEAN
EFIAPI
InternalAsciiIsDecimalDigitCharacter (
- IN CHAR8 Char
+ IN CHAR8 Char
)
{
- return (BOOLEAN) (Char >= '0' && Char <= '9');
+ return (BOOLEAN)(Char >= '0' && Char <= '9');
}
/**
@@ -592,16 +603,14 @@ InternalAsciiIsDecimalDigitCharacter (
BOOLEAN
EFIAPI
InternalAsciiIsHexaDecimalDigitCharacter (
- IN CHAR8 Char
+ IN CHAR8 Char
)
{
-
- return (BOOLEAN) (InternalAsciiIsDecimalDigitCharacter (Char) ||
- (Char >= 'A' && Char <= 'F') ||
- (Char >= 'a' && Char <= 'f'));
+ return (BOOLEAN)(InternalAsciiIsDecimalDigitCharacter (Char) ||
+ (Char >= 'A' && Char <= 'F') ||
+ (Char >= 'a' && Char <= 'f'));
}
-
/**
Returns the length of a Null-terminated ASCII string.
@@ -622,10 +631,10 @@ InternalAsciiIsHexaDecimalDigitCharacter (
UINTN
EFIAPI
AsciiStrLen (
- IN CONST CHAR8 *String
+ IN CONST CHAR8 *String
)
{
- UINTN Length;
+ UINTN Length;
ASSERT (String != NULL);
@@ -638,6 +647,7 @@ AsciiStrLen (
ASSERT (Length < PcdGet32 (PcdMaximumAsciiStringLength));
}
}
+
return Length;
}
@@ -661,7 +671,7 @@ AsciiStrLen (
UINTN
EFIAPI
AsciiStrSize (
- IN CONST CHAR8 *String
+ IN CONST CHAR8 *String
)
{
return (AsciiStrLen (String) + 1) * sizeof (*String);
@@ -696,8 +706,8 @@ AsciiStrSize (
INTN
EFIAPI
AsciiStrCmp (
- IN CONST CHAR8 *FirstString,
- IN CONST CHAR8 *SecondString
+ IN CONST CHAR8 *FirstString,
+ IN CONST CHAR8 *SecondString
)
{
//
@@ -730,10 +740,10 @@ AsciiStrCmp (
CHAR8
EFIAPI
AsciiCharToUpper (
- IN CHAR8 Chr
+ IN CHAR8 Chr
)
{
- return (UINT8) ((Chr >= 'a' && Chr <= 'z') ? Chr - ('a' - 'A') : Chr);
+ return (UINT8)((Chr >= 'a' && Chr <= 'z') ? Chr - ('a' - 'A') : Chr);
}
/**
@@ -752,7 +762,7 @@ AsciiCharToUpper (
UINTN
EFIAPI
InternalAsciiHexCharToUintn (
- IN CHAR8 Char
+ IN CHAR8 Char
)
{
if (InternalIsDecimalDigitCharacter (Char)) {
@@ -762,7 +772,6 @@ InternalAsciiHexCharToUintn (
return (10 + AsciiCharToUpper (Char) - 'A');
}
-
/**
Performs a case insensitive comparison of two Null-terminated ASCII strings,
and returns the difference between the first mismatched ASCII characters.
@@ -795,8 +804,8 @@ InternalAsciiHexCharToUintn (
INTN
EFIAPI
AsciiStriCmp (
- IN CONST CHAR8 *FirstString,
- IN CONST CHAR8 *SecondString
+ IN CONST CHAR8 *FirstString,
+ IN CONST CHAR8 *SecondString
)
{
CHAR8 UpperFirstString;
@@ -853,9 +862,9 @@ AsciiStriCmp (
INTN
EFIAPI
AsciiStrnCmp (
- IN CONST CHAR8 *FirstString,
- IN CONST CHAR8 *SecondString,
- IN UINTN Length
+ IN CONST CHAR8 *FirstString,
+ IN CONST CHAR8 *SecondString,
+ IN UINTN Length
)
{
if (Length == 0) {
@@ -875,15 +884,16 @@ AsciiStrnCmp (
while ((*FirstString != '\0') &&
(*SecondString != '\0') &&
(*FirstString == *SecondString) &&
- (Length > 1)) {
+ (Length > 1))
+ {
FirstString++;
SecondString++;
Length--;
}
+
return *FirstString - *SecondString;
}
-
/**
Returns the first occurrence of a Null-terminated ASCII sub-string
in a Null-terminated ASCII string.
@@ -911,12 +921,12 @@ AsciiStrnCmp (
CHAR8 *
EFIAPI
AsciiStrStr (
- IN CONST CHAR8 *String,
- IN CONST CHAR8 *SearchString
+ IN CONST CHAR8 *String,
+ IN CONST CHAR8 *SearchString
)
{
- CONST CHAR8 *FirstMatch;
- CONST CHAR8 *SearchStringTmp;
+ CONST CHAR8 *FirstMatch;
+ CONST CHAR8 *SearchStringTmp;
//
// ASSERT both strings are less long than PcdMaximumAsciiStringLength
@@ -925,21 +935,22 @@ AsciiStrStr (
ASSERT (AsciiStrSize (SearchString) != 0);
if (*SearchString == '\0') {
- return (CHAR8 *) String;
+ return (CHAR8 *)String;
}
while (*String != '\0') {
SearchStringTmp = SearchString;
- FirstMatch = String;
+ FirstMatch = String;
- while ((*String == *SearchStringTmp)
- && (*String != '\0')) {
+ while ( (*String == *SearchStringTmp)
+ && (*String != '\0'))
+ {
String++;
SearchStringTmp++;
}
if (*SearchStringTmp == '\0') {
- return (CHAR8 *) FirstMatch;
+ return (CHAR8 *)FirstMatch;
}
if (*String == '\0') {
@@ -985,16 +996,18 @@ AsciiStrStr (
UINTN
EFIAPI
AsciiStrDecimalToUintn (
- IN CONST CHAR8 *String
+ IN CONST CHAR8 *String
)
{
- UINTN Result;
+ UINTN Result;
+
+ if (RETURN_ERROR (AsciiStrDecimalToUintnS (String, (CHAR8 **)NULL, &Result))) {
+ return MAX_UINTN;
+ }
- AsciiStrDecimalToUintnS (String, (CHAR8 **) NULL, &Result);
return Result;
}
-
/**
Convert a Null-terminated ASCII decimal string to a value of type
UINT64.
@@ -1028,12 +1041,15 @@ AsciiStrDecimalToUintn (
UINT64
EFIAPI
AsciiStrDecimalToUint64 (
- IN CONST CHAR8 *String
+ IN CONST CHAR8 *String
)
{
- UINT64 Result;
+ UINT64 Result;
+
+ if (RETURN_ERROR (AsciiStrDecimalToUint64S (String, (CHAR8 **)NULL, &Result))) {
+ return MAX_UINT64;
+ }
- AsciiStrDecimalToUint64S (String, (CHAR8 **) NULL, &Result);
return Result;
}
@@ -1074,16 +1090,18 @@ AsciiStrDecimalToUint64 (
UINTN
EFIAPI
AsciiStrHexToUintn (
- IN CONST CHAR8 *String
+ IN CONST CHAR8 *String
)
{
- UINTN Result;
+ UINTN Result;
+
+ if (RETURN_ERROR (AsciiStrHexToUintnS (String, (CHAR8 **)NULL, &Result))) {
+ return MAX_UINTN;
+ }
- AsciiStrHexToUintnS (String, (CHAR8 **) NULL, &Result);
return Result;
}
-
/**
Convert a Null-terminated ASCII hexadecimal string to a value of type UINT64.
@@ -1121,17 +1139,19 @@ AsciiStrHexToUintn (
UINT64
EFIAPI
AsciiStrHexToUint64 (
- IN CONST CHAR8 *String
+ IN CONST CHAR8 *String
)
{
- UINT64 Result;
+ UINT64 Result;
+
+ if (RETURN_ERROR (AsciiStrHexToUint64S (String, (CHAR8 **)NULL, &Result))) {
+ return MAX_UINT64;
+ }
- AsciiStrHexToUint64S (String, (CHAR8 **) NULL, &Result);
return Result;
}
-
-STATIC CHAR8 EncodingTable[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
+STATIC CHAR8 EncodingTable[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
"abcdefghijklmnopqrstuvwxyz"
"0123456789+/";
@@ -1158,14 +1178,13 @@ RETURN_STATUS
EFIAPI
Base64Encode (
IN CONST UINT8 *Source,
- IN UINTN SourceLength,
+ IN UINTN SourceLength,
OUT CHAR8 *Destination OPTIONAL,
IN OUT UINTN *DestinationSize
)
{
-
- UINTN RequiredSize;
- UINTN Left;
+ UINTN RequiredSize;
+ UINTN Left;
//
// Check pointers, and SourceLength is valid
@@ -1182,15 +1201,16 @@ Base64Encode (
*DestinationSize = 1;
return RETURN_BUFFER_TOO_SMALL;
}
+
*DestinationSize = 1;
- *Destination = '\0';
+ *Destination = '\0';
return RETURN_SUCCESS;
}
//
// Check if SourceLength or DestinationSize is valid
//
- if ((SourceLength >= (MAX_ADDRESS - (UINTN)Source)) || (*DestinationSize >= (MAX_ADDRESS - (UINTN)Destination))){
+ if ((SourceLength >= (MAX_ADDRESS - (UINTN)Source)) || (*DestinationSize >= (MAX_ADDRESS - (UINTN)Destination))) {
return RETURN_INVALID_PARAMETER;
}
@@ -1198,7 +1218,7 @@ Base64Encode (
// 4 ascii per 3 bytes + NULL
//
RequiredSize = ((SourceLength + 2) / 3) * 4 + 1;
- if ((Destination == NULL) || *DestinationSize < RequiredSize) {
+ if ((Destination == NULL) || (*DestinationSize < RequiredSize)) {
*DestinationSize = RequiredSize;
return RETURN_BUFFER_TOO_SMALL;
}
@@ -1209,13 +1229,12 @@ Base64Encode (
// Encode 24 bits (three bytes) into 4 ascii characters
//
while (Left >= 3) {
-
- *Destination++ = EncodingTable[( Source[0] & 0xfc) >> 2 ];
+ *Destination++ = EncodingTable[(Source[0] & 0xfc) >> 2];
*Destination++ = EncodingTable[((Source[0] & 0x03) << 4) + ((Source[1] & 0xf0) >> 4)];
*Destination++ = EncodingTable[((Source[1] & 0x0f) << 2) + ((Source[2] & 0xc0) >> 6)];
- *Destination++ = EncodingTable[( Source[2] & 0x3f)];
- Left -= 3;
- Source += 3;
+ *Destination++ = EncodingTable[(Source[2] & 0x3f)];
+ Left -= 3;
+ Source += 3;
}
//
@@ -1233,7 +1252,7 @@ Base64Encode (
//
// One more data byte, two pad characters
//
- *Destination++ = EncodingTable[( Source[0] & 0xfc) >> 2];
+ *Destination++ = EncodingTable[(Source[0] & 0xfc) >> 2];
*Destination++ = EncodingTable[((Source[0] & 0x03) << 4)];
*Destination++ = '=';
*Destination++ = '=';
@@ -1243,12 +1262,13 @@ Base64Encode (
//
// Two more data bytes, and one pad character
//
- *Destination++ = EncodingTable[( Source[0] & 0xfc) >> 2];
+ *Destination++ = EncodingTable[(Source[0] & 0xfc) >> 2];
*Destination++ = EncodingTable[((Source[0] & 0x03) << 4) + ((Source[1] & 0xf0) >> 4)];
*Destination++ = EncodingTable[((Source[1] & 0x0f) << 2)];
*Destination++ = '=';
break;
- }
+ }
+
//
// Add terminating NULL
//
@@ -1341,20 +1361,20 @@ Base64Encode (
RETURN_STATUS
EFIAPI
Base64Decode (
- IN CONST CHAR8 *Source OPTIONAL,
- IN UINTN SourceSize,
- OUT UINT8 *Destination OPTIONAL,
- IN OUT UINTN *DestinationSize
+ IN CONST CHAR8 *Source OPTIONAL,
+ IN UINTN SourceSize,
+ OUT UINT8 *Destination OPTIONAL,
+ IN OUT UINTN *DestinationSize
)
{
- BOOLEAN PaddingMode;
- UINTN SixBitGroupsConsumed;
- UINT32 Accumulator;
- UINTN OriginalDestinationSize;
- UINTN SourceIndex;
- CHAR8 SourceChar;
- UINT32 Base64Value;
- UINT8 DestinationOctet;
+ BOOLEAN PaddingMode;
+ UINTN SixBitGroupsConsumed;
+ UINT32 Accumulator;
+ UINTN OriginalDestinationSize;
+ UINTN SourceIndex;
+ CHAR8 SourceChar;
+ UINT32 Base64Value;
+ UINT8 DestinationOctet;
if (DestinationSize == NULL) {
return RETURN_INVALID_PARAMETER;
@@ -1397,7 +1417,7 @@ Base64Decode (
//
// Check for overlap.
//
- if (Source != NULL && Destination != NULL) {
+ if ((Source != NULL) && (Destination != NULL)) {
//
// Both arrays have been provided, and we know from earlier that each array
// is valid in itself.
@@ -1436,8 +1456,9 @@ Base64Decode (
//
// Whitespace is ignored at all positions (regardless of padding mode).
//
- if (SourceChar == '\t' || SourceChar == '\n' || SourceChar == '\v' ||
- SourceChar == '\f' || SourceChar == '\r' || SourceChar == ' ') {
+ if ((SourceChar == '\t') || (SourceChar == '\n') || (SourceChar == '\v') ||
+ (SourceChar == '\f') || (SourceChar == '\r') || (SourceChar == ' '))
+ {
continue;
}
@@ -1451,10 +1472,11 @@ Base64Decode (
// "=" padding characters.
//
if (PaddingMode) {
- if (SourceChar == '=' && SixBitGroupsConsumed == 3) {
+ if ((SourceChar == '=') && (SixBitGroupsConsumed == 3)) {
SixBitGroupsConsumed = 0;
continue;
}
+
return RETURN_INVALID_PARAMETER;
}
@@ -1462,11 +1484,11 @@ Base64Decode (
// When not in padding mode, decode Base64Value based on RFC4648, "Table 1:
// The Base 64 Alphabet".
//
- if ('A' <= SourceChar && SourceChar <= 'Z') {
+ if (('A' <= SourceChar) && (SourceChar <= 'Z')) {
Base64Value = SourceChar - 'A';
- } else if ('a' <= SourceChar && SourceChar <= 'z') {
+ } else if (('a' <= SourceChar) && (SourceChar <= 'z')) {
Base64Value = 26 + (SourceChar - 'a');
- } else if ('0' <= SourceChar && SourceChar <= '9') {
+ } else if (('0' <= SourceChar) && (SourceChar <= '9')) {
Base64Value = 52 + (SourceChar - '0');
} else if (SourceChar == '+') {
Base64Value = 62;
@@ -1530,38 +1552,38 @@ Base64Decode (
Accumulator = (Accumulator << 6) | Base64Value;
SixBitGroupsConsumed++;
switch (SixBitGroupsConsumed) {
- case 1:
- //
- // No octet to spill after consuming the first 6-bit group of the
- // quantum; advance to the next source character.
- //
- continue;
- case 2:
- //
- // 12 bits accumulated (6 pending + 6 new); prepare for spilling an
- // octet. 4 bits remain pending.
- //
- DestinationOctet = (UINT8)(Accumulator >> 4);
- Accumulator &= 0xF;
- break;
- case 3:
- //
- // 10 bits accumulated (4 pending + 6 new); prepare for spilling an
- // octet. 2 bits remain pending.
- //
- DestinationOctet = (UINT8)(Accumulator >> 2);
- Accumulator &= 0x3;
- break;
- default:
- ASSERT (SixBitGroupsConsumed == 4);
- //
- // 8 bits accumulated (2 pending + 6 new); prepare for spilling an octet.
- // The quantum is complete, 0 bits remain pending.
- //
- DestinationOctet = (UINT8)Accumulator;
- Accumulator = 0;
- SixBitGroupsConsumed = 0;
- break;
+ case 1:
+ //
+ // No octet to spill after consuming the first 6-bit group of the
+ // quantum; advance to the next source character.
+ //
+ continue;
+ case 2:
+ //
+ // 12 bits accumulated (6 pending + 6 new); prepare for spilling an
+ // octet. 4 bits remain pending.
+ //
+ DestinationOctet = (UINT8)(Accumulator >> 4);
+ Accumulator &= 0xF;
+ break;
+ case 3:
+ //
+ // 10 bits accumulated (4 pending + 6 new); prepare for spilling an
+ // octet. 2 bits remain pending.
+ //
+ DestinationOctet = (UINT8)(Accumulator >> 2);
+ Accumulator &= 0x3;
+ break;
+ default:
+ ASSERT (SixBitGroupsConsumed == 4);
+ //
+ // 8 bits accumulated (2 pending + 6 new); prepare for spilling an octet.
+ // The quantum is complete, 0 bits remain pending.
+ //
+ DestinationOctet = (UINT8)Accumulator;
+ Accumulator = 0;
+ SixBitGroupsConsumed = 0;
+ break;
}
//
@@ -1572,6 +1594,7 @@ Base64Decode (
ASSERT (Destination != NULL);
Destination[*DestinationSize] = DestinationOctet;
}
+
(*DestinationSize)++;
//
@@ -1592,6 +1615,7 @@ Base64Decode (
if (*DestinationSize <= OriginalDestinationSize) {
return RETURN_SUCCESS;
}
+
return RETURN_BUFFER_TOO_SMALL;
}
@@ -1611,11 +1635,11 @@ Base64Decode (
UINT8
EFIAPI
DecimalToBcd8 (
- IN UINT8 Value
+ IN UINT8 Value
)
{
ASSERT (Value < 100);
- return (UINT8) (((Value / 10) << 4) | (Value % 10));
+ return (UINT8)(((Value / 10) << 4) | (Value % 10));
}
/**
@@ -1635,10 +1659,10 @@ DecimalToBcd8 (
UINT8
EFIAPI
BcdToDecimal8 (
- IN UINT8 Value
+ IN UINT8 Value
)
{
ASSERT (Value < 0xa0);
ASSERT ((Value & 0xf) < 0xa);
- return (UINT8) ((Value >> 4) * 10 + (Value & 0xf));
+ return (UINT8)((Value >> 4) * 10 + (Value & 0xf));
}
diff --git a/MdePkg/Library/BaseLib/SwapBytes16.c b/MdePkg/Library/BaseLib/SwapBytes16.c
index 0822e431..c797f9ed 100644
--- a/MdePkg/Library/BaseLib/SwapBytes16.c
+++ b/MdePkg/Library/BaseLib/SwapBytes16.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -26,8 +23,8 @@
UINT16
EFIAPI
SwapBytes16 (
- IN UINT16 Value
+ IN UINT16 Value
)
{
- return (UINT16) ((Value<< 8) | (Value>> 8));
+ return (UINT16)((Value<< 8) | (Value>> 8));
}
diff --git a/MdePkg/Library/BaseLib/SwapBytes32.c b/MdePkg/Library/BaseLib/SwapBytes32.c
index e801eb91..dd0d2b35 100644
--- a/MdePkg/Library/BaseLib/SwapBytes32.c
+++ b/MdePkg/Library/BaseLib/SwapBytes32.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -26,14 +23,14 @@
UINT32
EFIAPI
SwapBytes32 (
- IN UINT32 Value
+ IN UINT32 Value
)
{
UINT32 LowerBytes;
UINT32 HigherBytes;
- LowerBytes = (UINT32) SwapBytes16 ((UINT16) Value);
- HigherBytes = (UINT32) SwapBytes16 ((UINT16) (Value >> 16));
+ LowerBytes = (UINT32)SwapBytes16 ((UINT16)Value);
+ HigherBytes = (UINT32)SwapBytes16 ((UINT16)(Value >> 16));
return (LowerBytes << 16 | HigherBytes);
}
diff --git a/MdePkg/Library/BaseLib/SwapBytes64.c b/MdePkg/Library/BaseLib/SwapBytes64.c
index 6f325296..214e746c 100644
--- a/MdePkg/Library/BaseLib/SwapBytes64.c
+++ b/MdePkg/Library/BaseLib/SwapBytes64.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -26,7 +23,7 @@
UINT64
EFIAPI
SwapBytes64 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
return InternalMathSwapBytes64 (Value);
diff --git a/MdePkg/Library/BaseLib/SwitchStack.c b/MdePkg/Library/BaseLib/SwitchStack.c
index f1920550..79cf929b 100644
--- a/MdePkg/Library/BaseLib/SwitchStack.c
+++ b/MdePkg/Library/BaseLib/SwitchStack.c
@@ -41,13 +41,13 @@ VOID
EFIAPI
SwitchStack (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
- IN VOID *Context1, OPTIONAL
- IN VOID *Context2, OPTIONAL
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL,
IN VOID *NewStack,
...
)
{
- VA_LIST Marker;
+ VA_LIST Marker;
ASSERT (EntryPoint != NULL);
ASSERT (NewStack != NULL);
diff --git a/MdePkg/Library/BaseLib/Unaligned.c b/MdePkg/Library/BaseLib/Unaligned.c
index b58b3e22..afdb1461 100644
--- a/MdePkg/Library/BaseLib/Unaligned.c
+++ b/MdePkg/Library/BaseLib/Unaligned.c
@@ -6,10 +6,8 @@
**/
-
#include "BaseLibInternals.h"
-
/**
Reads a 16-bit value from memory that may be unaligned.
@@ -26,7 +24,7 @@
UINT16
EFIAPI
ReadUnaligned16 (
- IN CONST UINT16 *Buffer
+ IN CONST UINT16 *Buffer
)
{
ASSERT (Buffer != NULL);
@@ -52,8 +50,8 @@ ReadUnaligned16 (
UINT16
EFIAPI
WriteUnaligned16 (
- OUT UINT16 *Buffer,
- IN UINT16 Value
+ OUT UINT16 *Buffer,
+ IN UINT16 Value
)
{
ASSERT (Buffer != NULL);
@@ -77,7 +75,7 @@ WriteUnaligned16 (
UINT32
EFIAPI
ReadUnaligned24 (
- IN CONST UINT32 *Buffer
+ IN CONST UINT32 *Buffer
)
{
ASSERT (Buffer != NULL);
@@ -103,8 +101,8 @@ ReadUnaligned24 (
UINT32
EFIAPI
WriteUnaligned24 (
- OUT UINT32 *Buffer,
- IN UINT32 Value
+ OUT UINT32 *Buffer,
+ IN UINT32 Value
)
{
ASSERT (Buffer != NULL);
@@ -129,7 +127,7 @@ WriteUnaligned24 (
UINT32
EFIAPI
ReadUnaligned32 (
- IN CONST UINT32 *Buffer
+ IN CONST UINT32 *Buffer
)
{
ASSERT (Buffer != NULL);
@@ -155,8 +153,8 @@ ReadUnaligned32 (
UINT32
EFIAPI
WriteUnaligned32 (
- OUT UINT32 *Buffer,
- IN UINT32 Value
+ OUT UINT32 *Buffer,
+ IN UINT32 Value
)
{
ASSERT (Buffer != NULL);
@@ -180,7 +178,7 @@ WriteUnaligned32 (
UINT64
EFIAPI
ReadUnaligned64 (
- IN CONST UINT64 *Buffer
+ IN CONST UINT64 *Buffer
)
{
ASSERT (Buffer != NULL);
@@ -206,8 +204,8 @@ ReadUnaligned64 (
UINT64
EFIAPI
WriteUnaligned64 (
- OUT UINT64 *Buffer,
- IN UINT64 Value
+ OUT UINT64 *Buffer,
+ IN UINT64 Value
)
{
ASSERT (Buffer != NULL);
diff --git a/MdePkg/Library/BaseLib/UnitTestHost.c b/MdePkg/Library/BaseLib/UnitTestHost.c
new file mode 100644
index 00000000..071a3d49
--- /dev/null
+++ b/MdePkg/Library/BaseLib/UnitTestHost.c
@@ -0,0 +1,140 @@
+/** @file
+ Common Unit Test Host functions.
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "UnitTestHost.h"
+
+///
+/// Module global variable for simple system emulation of interrupt state
+///
+STATIC BOOLEAN mUnitTestHostBaseLibInterruptState;
+
+/**
+ Enables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibEnableInterrupts (
+ VOID
+ )
+{
+ mUnitTestHostBaseLibInterruptState = TRUE;
+}
+
+/**
+ Disables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibDisableInterrupts (
+ VOID
+ )
+{
+ mUnitTestHostBaseLibInterruptState = FALSE;
+}
+
+/**
+ Enables CPU interrupts for the smallest window required to capture any
+ pending interrupts.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibEnableDisableInterrupts (
+ VOID
+ )
+{
+ mUnitTestHostBaseLibInterruptState = FALSE;
+}
+
+/**
+ Set the current CPU interrupt state.
+
+ Sets the current CPU interrupt state to the state specified by
+ InterruptState. If InterruptState is TRUE, then interrupts are enabled. If
+ InterruptState is FALSE, then interrupts are disabled. InterruptState is
+ returned.
+
+ @param InterruptState TRUE if interrupts should enabled. FALSE if
+ interrupts should be disabled.
+
+ @return InterruptState
+
+**/
+BOOLEAN
+EFIAPI
+UnitTestHostBaseLibGetInterruptState (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibInterruptState;
+}
+
+/**
+ Enables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+EnableInterrupts (
+ VOID
+ )
+{
+ gUnitTestHostBaseLib.Common->EnableInterrupts ();
+}
+
+/**
+ Disables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+DisableInterrupts (
+ VOID
+ )
+{
+ gUnitTestHostBaseLib.Common->DisableInterrupts ();
+}
+
+/**
+ Enables CPU interrupts for the smallest window required to capture any
+ pending interrupts.
+
+**/
+VOID
+EFIAPI
+EnableDisableInterrupts (
+ VOID
+ )
+{
+ gUnitTestHostBaseLib.Common->EnableDisableInterrupts ();
+}
+
+/**
+ Set the current CPU interrupt state.
+
+ Sets the current CPU interrupt state to the state specified by
+ InterruptState. If InterruptState is TRUE, then interrupts are enabled. If
+ InterruptState is FALSE, then interrupts are disabled. InterruptState is
+ returned.
+
+ @param InterruptState TRUE if interrupts should enabled. FALSE if
+ interrupts should be disabled.
+
+ @return InterruptState
+
+**/
+BOOLEAN
+EFIAPI
+GetInterruptState (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.Common->GetInterruptState ();
+}
diff --git a/MdePkg/Library/BaseLib/UnitTestHost.h b/MdePkg/Library/BaseLib/UnitTestHost.h
new file mode 100644
index 00000000..f7667e94
--- /dev/null
+++ b/MdePkg/Library/BaseLib/UnitTestHost.h
@@ -0,0 +1,66 @@
+/** @file
+ Unit Test Host functions.
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __UNIT_TEST_HOST_H__
+#define __UNIT_TEST_HOST_H__
+
+#include "BaseLibInternals.h"
+#include
+
+/**
+ Enables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibEnableInterrupts (
+ VOID
+ );
+
+/**
+ Disables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibDisableInterrupts (
+ VOID
+ );
+
+/**
+ Enables CPU interrupts for the smallest window required to capture any
+ pending interrupts.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibEnableDisableInterrupts (
+ VOID
+ );
+
+/**
+ Set the current CPU interrupt state.
+
+ Sets the current CPU interrupt state to the state specified by
+ InterruptState. If InterruptState is TRUE, then interrupts are enabled. If
+ InterruptState is FALSE, then interrupts are disabled. InterruptState is
+ returned.
+
+ @param InterruptState TRUE if interrupts should enabled. FALSE if
+ interrupts should be disabled.
+
+ @return InterruptState
+
+**/
+BOOLEAN
+EFIAPI
+UnitTestHostBaseLibGetInterruptState (
+ VOID
+ );
+
+#endif
diff --git a/MdePkg/Library/BaseLib/UnitTestHostBaseLib.inf b/MdePkg/Library/BaseLib/UnitTestHostBaseLib.inf
new file mode 100644
index 00000000..ab7567a5
--- /dev/null
+++ b/MdePkg/Library/BaseLib/UnitTestHostBaseLib.inf
@@ -0,0 +1,247 @@
+## @file
+# Base Library implementation for use with host based unit tests, and
+# can also be used by emulation platforms such as EmulatorPkg.
+#
+# Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = UnitTestHostBaseLib
+ MODULE_UNI_FILE = UnitTestHostBaseLib.uni
+ FILE_GUID = 9555A0D3-09BA-46C4-A51A-45198E3C765E
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.1
+ LIBRARY_CLASS = BaseLib
+ LIBRARY_CLASS = UnitTestHostBaseLib|HOST_APPLICATION
+
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources]
+ CheckSum.c
+ SwitchStack.c
+ SwapBytes64.c
+ SwapBytes32.c
+ SwapBytes16.c
+ LongJump.c
+ SetJump.c
+ QuickSort.c
+ RShiftU64.c
+ RRotU64.c
+ RRotU32.c
+ MultU64x64.c
+ MultU64x32.c
+ MultS64x64.c
+ ModU64x32.c
+ LShiftU64.c
+ LRotU64.c
+ LRotU32.c
+ LowBitSet64.c
+ LowBitSet32.c
+ HighBitSet64.c
+ HighBitSet32.c
+ GetPowerOfTwo64.c
+ GetPowerOfTwo32.c
+ DivU64x64Remainder.c
+ DivU64x32Remainder.c
+ DivU64x32.c
+ DivS64x64Remainder.c
+ ARShiftU64.c
+ BitField.c
+ CpuDeadLoop.c
+ Cpu.c
+ LinkedList.c
+ SafeString.c
+ String.c
+ FilePaths.c
+ BaseLibInternals.h
+ UnitTestHost.c
+ UnitTestHost.h
+
+[Sources.Ia32]
+ Ia32/WriteMm7.c | MSFT
+ Ia32/WriteMm6.c | MSFT
+ Ia32/WriteMm5.c | MSFT
+ Ia32/WriteMm4.c | MSFT
+ Ia32/WriteMm3.c | MSFT
+ Ia32/WriteMm2.c | MSFT
+ Ia32/WriteMm1.c | MSFT
+ Ia32/WriteMm0.c | MSFT
+ Ia32/ReadMm7.c | MSFT
+ Ia32/ReadMm6.c | MSFT
+ Ia32/ReadMm5.c | MSFT
+ Ia32/ReadMm4.c | MSFT
+ Ia32/ReadMm3.c | MSFT
+ Ia32/ReadMm2.c | MSFT
+ Ia32/ReadMm1.c | MSFT
+ Ia32/ReadMm0.c | MSFT
+ Ia32/SwapBytes64.c | MSFT
+ Ia32/RRotU64.c | MSFT
+ Ia32/RShiftU64.c | MSFT
+ Ia32/ReadTsc.c | MSFT
+ Ia32/ReadEflags.c | MSFT
+ Ia32/ModU64x32.c | MSFT
+ Ia32/MultU64x64.c | MSFT
+ Ia32/MultU64x32.c | MSFT
+ Ia32/LShiftU64.c | MSFT
+ Ia32/LRotU64.c | MSFT
+ Ia32/FxRestore.c | MSFT
+ Ia32/FxSave.c | MSFT
+ Ia32/DivU64x32Remainder.c | MSFT
+ Ia32/DivU64x32.c | MSFT
+ Ia32/CpuPause.c | MSFT
+ Ia32/CpuBreakpoint.c | MSFT
+ Ia32/ARShiftU64.c | MSFT
+ Ia32/GccInline.c | GCC
+ Ia32/LongJump.nasm
+ Ia32/SetJump.nasm
+ Ia32/SwapBytes64.nasm| GCC
+ Ia32/DivU64x64Remainder.nasm
+ Ia32/DivU64x32Remainder.nasm| GCC
+ Ia32/ModU64x32.nasm| GCC
+ Ia32/DivU64x32.nasm| GCC
+ Ia32/MultU64x64.nasm| GCC
+ Ia32/MultU64x32.nasm| GCC
+ Ia32/RRotU64.nasm| GCC
+ Ia32/LRotU64.nasm| GCC
+ Ia32/ARShiftU64.nasm| GCC
+ Ia32/RShiftU64.nasm| GCC
+ Ia32/LShiftU64.nasm| GCC
+ Ia32/RdRand.nasm
+ Ia32/DivS64x64Remainder.c
+ Ia32/InternalSwitchStack.c | MSFT
+ Ia32/InternalSwitchStack.nasm | GCC
+ Ia32/Non-existing.c
+ Unaligned.c
+ X86MemoryFence.c | MSFT
+ X86FxSave.c
+ X86FxRestore.c
+ X86Msr.c
+ X86RdRand.c
+ X86SpeculationBarrier.c
+ X86UnitTestHost.c
+ IntelTdxNull.c
+
+[Sources.X64]
+ X64/LongJump.nasm
+ X64/SetJump.nasm
+ X64/SwitchStack.nasm
+ X64/CpuBreakpoint.c | MSFT
+ X64/CpuPause.nasm| MSFT
+ X64/ReadTsc.nasm| MSFT
+ X64/WriteMm7.nasm| MSFT
+ X64/WriteMm6.nasm| MSFT
+ X64/WriteMm5.nasm| MSFT
+ X64/WriteMm4.nasm| MSFT
+ X64/WriteMm3.nasm| MSFT
+ X64/WriteMm2.nasm| MSFT
+ X64/WriteMm1.nasm| MSFT
+ X64/WriteMm0.nasm| MSFT
+ X64/ReadMm7.nasm| MSFT
+ X64/ReadMm6.nasm| MSFT
+ X64/ReadMm5.nasm| MSFT
+ X64/ReadMm4.nasm| MSFT
+ X64/ReadMm3.nasm| MSFT
+ X64/ReadMm2.nasm| MSFT
+ X64/ReadMm1.nasm| MSFT
+ X64/ReadMm0.nasm| MSFT
+ X64/FxRestore.nasm| MSFT
+ X64/FxSave.nasm| MSFT
+ X64/ReadEflags.nasm| MSFT
+ X64/Non-existing.c
+ Math64.c
+ Unaligned.c
+ X86MemoryFence.c | MSFT
+ X86FxSave.c
+ X86FxRestore.c
+ X86Msr.c
+ X86RdRand.c
+ X86SpeculationBarrier.c
+ X64/GccInline.c | GCC
+ X64/RdRand.nasm
+ ChkStkGcc.c | GCC
+ X86UnitTestHost.c
+ IntelTdxNull.c
+
+[Sources.EBC]
+ Ebc/CpuBreakpoint.c
+ Ebc/SetJumpLongJump.c
+ Ebc/SwitchStack.c
+ Ebc/SpeculationBarrier.c
+ Unaligned.c
+ Math64.c
+
+[Sources.ARM]
+ Arm/InternalSwitchStack.c
+ Arm/Unaligned.c
+ Math64.c | MSFT
+
+ Arm/SwitchStack.asm | MSFT
+ Arm/SetJumpLongJump.asm | MSFT
+ Arm/CpuPause.asm | MSFT
+ Arm/CpuBreakpoint.asm | MSFT
+ Arm/MemoryFence.asm | MSFT
+ Arm/SpeculationBarrier.asm | MSFT
+
+ Arm/Math64.S | GCC
+ Arm/SwitchStack.S | GCC
+ Arm/SetJumpLongJump.S | GCC
+ Arm/CpuBreakpoint.S | GCC
+ Arm/MemoryFence.S | GCC
+ Arm/SpeculationBarrier.S | GCC
+
+[Sources.AARCH64]
+ Arm/InternalSwitchStack.c
+ Arm/Unaligned.c
+ Math64.c
+
+ AArch64/MemoryFence.S | GCC
+ AArch64/SwitchStack.S | GCC
+ AArch64/SetJumpLongJump.S | GCC
+ AArch64/CpuBreakpoint.S | GCC
+ AArch64/SpeculationBarrier.S | GCC
+
+ AArch64/MemoryFence.asm | MSFT
+ AArch64/SwitchStack.asm | MSFT
+ AArch64/SetJumpLongJump.asm | MSFT
+ AArch64/CpuBreakpoint.asm | MSFT
+ AArch64/SpeculationBarrier.asm | MSFT
+
+[Sources.RISCV64]
+ Math64.c
+ Unaligned.c
+ RiscV64/InternalSwitchStack.c
+ RiscV64/CpuBreakpoint.c
+ RiscV64/CpuPause.c
+ RiscV64/RiscVSetJumpLongJump.S | GCC
+ RiscV64/RiscVCpuBreakpoint.S | GCC
+ RiscV64/RiscVCpuPause.S | GCC
+ RiscV64/RiscVInterrupt.S | GCC
+ RiscV64/FlushCache.S | GCC
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ PcdLib
+ DebugLib
+ BaseMemoryLib
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength ## SOMETIMES_CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength ## SOMETIMES_CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength ## SOMETIMES_CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask ## SOMETIMES_CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdSpeculationBarrierType ## SOMETIMES_CONSUMES
+
+[FeaturePcd]
+ gEfiMdePkgTokenSpaceGuid.PcdVerifyNodeInList ## CONSUMES
diff --git a/MdePkg/Library/BaseLib/X64/CpuBreakpoint.c b/MdePkg/Library/BaseLib/X64/CpuBreakpoint.c
index d538d63c..e6e5141b 100644
--- a/MdePkg/Library/BaseLib/X64/CpuBreakpoint.c
+++ b/MdePkg/Library/BaseLib/X64/CpuBreakpoint.c
@@ -6,12 +6,14 @@
**/
-
/**
Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
**/
-void __debugbreak (VOID);
+void
+__debugbreak (
+ VOID
+ );
#pragma intrinsic(__debugbreak)
@@ -30,4 +32,3 @@ CpuBreakpoint (
{
__debugbreak ();
}
-
diff --git a/MdePkg/Library/BaseLib/X64/DisablePaging64.nasm b/MdePkg/Library/BaseLib/X64/DisablePaging64.nasm
index 7b9f2c62..f98283a7 100644
--- a/MdePkg/Library/BaseLib/X64/DisablePaging64.nasm
+++ b/MdePkg/Library/BaseLib/X64/DisablePaging64.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -51,8 +51,7 @@ ASM_PFX(InternalX86DisablePaging64):
sub eax, 4 ; eax <- One slot below transition code on the stack
push rcx ; push Cs to stack
push r10 ; push address of tansition code on stack
- DB 0x48 ; prefix to composite "retq" with next "retf"
- retf ; Use far return to load CS register from stack
+ retfq
; Start of transition code
.0:
diff --git a/MdePkg/Library/BaseLib/X64/GccInline.c b/MdePkg/Library/BaseLib/X64/GccInline.c
index 69ec93ca..86c38126 100644
--- a/MdePkg/Library/BaseLib/X64/GccInline.c
+++ b/MdePkg/Library/BaseLib/X64/GccInline.c
@@ -7,12 +7,8 @@
**/
-
#include "BaseLibInternals.h"
-
-
-
/**
Used to serialize load and store operations.
@@ -32,7 +28,6 @@ MemoryFence (
__asm__ __volatile__ ("":::"memory");
}
-
/**
Requests CPU to pause for a short period of time.
@@ -49,7 +44,6 @@ CpuPause (
__asm__ __volatile__ ("pause");
}
-
/**
Generates a breakpoint on the CPU.
@@ -66,7 +60,6 @@ CpuBreakpoint (
__asm__ __volatile__ ("int $3");
}
-
/**
Reads the current value of the EFLAGS register.
@@ -83,13 +76,13 @@ AsmReadEflags (
VOID
)
{
- UINTN Eflags;
+ UINTN Eflags;
__asm__ __volatile__ (
"pushfq \n\t"
"pop %0 "
: "=r" (Eflags) // %0
- );
+ );
return Eflags;
}
@@ -107,17 +100,16 @@ AsmReadEflags (
VOID
EFIAPI
InternalX86FxSave (
- OUT IA32_FX_BUFFER *Buffer
+ OUT IA32_FX_BUFFER *Buffer
)
{
__asm__ __volatile__ (
"fxsave %0"
:
: "m" (*Buffer) // %0
- );
+ );
}
-
/**
Restores the current floating point/SSE/SSE2 context from a buffer.
@@ -131,17 +123,16 @@ InternalX86FxSave (
VOID
EFIAPI
InternalX86FxRestore (
- IN CONST IA32_FX_BUFFER *Buffer
+ IN CONST IA32_FX_BUFFER *Buffer
)
{
__asm__ __volatile__ (
"fxrstor %0"
:
: "m" (*Buffer) // %0
- );
+ );
}
-
/**
Reads the current value of 64-bit MMX Register #0 (MM0).
@@ -162,12 +153,11 @@ AsmReadMm0 (
__asm__ __volatile__ (
"movd %%mm0, %0 \n\t"
: "=r" (Data) // %0
- );
+ );
return Data;
}
-
/**
Reads the current value of 64-bit MMX Register #1 (MM1).
@@ -188,12 +178,11 @@ AsmReadMm1 (
__asm__ __volatile__ (
"movd %%mm1, %0 \n\t"
: "=r" (Data) // %0
- );
+ );
return Data;
}
-
/**
Reads the current value of 64-bit MMX Register #2 (MM2).
@@ -214,12 +203,11 @@ AsmReadMm2 (
__asm__ __volatile__ (
"movd %%mm2, %0 \n\t"
: "=r" (Data) // %0
- );
+ );
return Data;
}
-
/**
Reads the current value of 64-bit MMX Register #3 (MM3).
@@ -240,12 +228,11 @@ AsmReadMm3 (
__asm__ __volatile__ (
"movd %%mm3, %0 \n\t"
: "=r" (Data) // %0
- );
+ );
return Data;
}
-
/**
Reads the current value of 64-bit MMX Register #4 (MM4).
@@ -266,12 +253,11 @@ AsmReadMm4 (
__asm__ __volatile__ (
"movd %%mm4, %0 \n\t"
: "=r" (Data) // %0
- );
+ );
return Data;
}
-
/**
Reads the current value of 64-bit MMX Register #5 (MM5).
@@ -292,12 +278,11 @@ AsmReadMm5 (
__asm__ __volatile__ (
"movd %%mm5, %0 \n\t"
: "=r" (Data) // %0
- );
+ );
return Data;
}
-
/**
Reads the current value of 64-bit MMX Register #6 (MM6).
@@ -318,12 +303,11 @@ AsmReadMm6 (
__asm__ __volatile__ (
"movd %%mm6, %0 \n\t"
: "=r" (Data) // %0
- );
+ );
return Data;
}
-
/**
Reads the current value of 64-bit MMX Register #7 (MM7).
@@ -344,12 +328,11 @@ AsmReadMm7 (
__asm__ __volatile__ (
"movd %%mm7, %0 \n\t"
: "=r" (Data) // %0
- );
+ );
return Data;
}
-
/**
Writes the current value of 64-bit MMX Register #0 (MM0).
@@ -362,17 +345,16 @@ AsmReadMm7 (
VOID
EFIAPI
AsmWriteMm0 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
__asm__ __volatile__ (
"movd %0, %%mm0" // %0
:
: "m" (Value)
- );
+ );
}
-
/**
Writes the current value of 64-bit MMX Register #1 (MM1).
@@ -385,17 +367,16 @@ AsmWriteMm0 (
VOID
EFIAPI
AsmWriteMm1 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
__asm__ __volatile__ (
"movd %0, %%mm1" // %0
:
: "m" (Value)
- );
+ );
}
-
/**
Writes the current value of 64-bit MMX Register #2 (MM2).
@@ -408,17 +389,16 @@ AsmWriteMm1 (
VOID
EFIAPI
AsmWriteMm2 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
__asm__ __volatile__ (
"movd %0, %%mm2" // %0
:
: "m" (Value)
- );
+ );
}
-
/**
Writes the current value of 64-bit MMX Register #3 (MM3).
@@ -431,17 +411,16 @@ AsmWriteMm2 (
VOID
EFIAPI
AsmWriteMm3 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
__asm__ __volatile__ (
"movd %0, %%mm3" // %0
:
: "m" (Value)
- );
+ );
}
-
/**
Writes the current value of 64-bit MMX Register #4 (MM4).
@@ -454,17 +433,16 @@ AsmWriteMm3 (
VOID
EFIAPI
AsmWriteMm4 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
__asm__ __volatile__ (
"movd %0, %%mm4" // %0
:
: "m" (Value)
- );
+ );
}
-
/**
Writes the current value of 64-bit MMX Register #5 (MM5).
@@ -477,17 +455,16 @@ AsmWriteMm4 (
VOID
EFIAPI
AsmWriteMm5 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
__asm__ __volatile__ (
"movd %0, %%mm5" // %0
:
: "m" (Value)
- );
+ );
}
-
/**
Writes the current value of 64-bit MMX Register #6 (MM6).
@@ -500,17 +477,16 @@ AsmWriteMm5 (
VOID
EFIAPI
AsmWriteMm6 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
__asm__ __volatile__ (
"movd %0, %%mm6" // %0
:
: "m" (Value)
- );
+ );
}
-
/**
Writes the current value of 64-bit MMX Register #7 (MM7).
@@ -523,17 +499,16 @@ AsmWriteMm6 (
VOID
EFIAPI
AsmWriteMm7 (
- IN UINT64 Value
+ IN UINT64 Value
)
{
__asm__ __volatile__ (
"movd %0, %%mm7" // %0
:
: "m" (Value)
- );
+ );
}
-
/**
Reads the current value of Time Stamp Counter (TSC).
@@ -556,7 +531,7 @@ AsmReadTsc (
"rdtsc"
: "=a" (LowData),
"=d" (HiData)
- );
+ );
return (((UINT64)HiData) << 32) | LowData;
}
diff --git a/MdePkg/Library/BaseLib/X64/GccInlinePriv.c b/MdePkg/Library/BaseLib/X64/GccInlinePriv.c
index 4f7bb3ae..db61a21e 100644
--- a/MdePkg/Library/BaseLib/X64/GccInlinePriv.c
+++ b/MdePkg/Library/BaseLib/X64/GccInlinePriv.c
@@ -8,7 +8,6 @@
**/
-
#include "BaseLibInternals.h"
#include
@@ -27,7 +26,6 @@ EnableInterrupts (
__asm__ __volatile__ ("sti"::: "memory");
}
-
/**
Disables CPU interrupts.
@@ -60,13 +58,13 @@ DisableInterrupts (
UINT64
EFIAPI
AsmReadMsr64 (
- IN UINT32 Index
+ IN UINT32 Index
)
{
- UINT32 LowData;
- UINT32 HighData;
- UINT64 Value;
- BOOLEAN Flag;
+ UINT32 LowData;
+ UINT32 HighData;
+ UINT64 Value;
+ BOOLEAN Flag;
Flag = FilterBeforeMsrRead (Index, &Value);
if (Flag) {
@@ -75,9 +73,10 @@ AsmReadMsr64 (
: "=a" (LowData), // %0
"=d" (HighData) // %1
: "c" (Index) // %2
- );
+ );
Value = (((UINT64)HighData) << 32) | LowData;
}
+
FilterAfterMsrRead (Index, &Value);
return Value;
@@ -103,13 +102,13 @@ AsmReadMsr64 (
UINT64
EFIAPI
AsmWriteMsr64 (
- IN UINT32 Index,
- IN UINT64 Value
+ IN UINT32 Index,
+ IN UINT64 Value
)
{
- UINT32 LowData;
- UINT32 HighData;
- BOOLEAN Flag;
+ UINT32 LowData;
+ UINT32 HighData;
+ BOOLEAN Flag;
Flag = FilterBeforeMsrWrite (Index, &Value);
if (Flag) {
@@ -121,8 +120,9 @@ AsmWriteMsr64 (
: "c" (Index),
"a" (LowData),
"d" (HighData)
- );
+ );
}
+
FilterAfterMsrWrite (Index, &Value);
return Value;
@@ -144,17 +144,16 @@ AsmReadCr0 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"mov %%cr0,%0"
: "=r" (Data) // %0
- );
+ );
return Data;
}
-
/**
Reads the current value of the Control Register 2 (CR2).
@@ -171,12 +170,12 @@ AsmReadCr2 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"mov %%cr2, %0"
: "=r" (Data) // %0
- );
+ );
return Data;
}
@@ -197,17 +196,16 @@ AsmReadCr3 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"mov %%cr3, %0"
: "=r" (Data) // %0
- );
+ );
return Data;
}
-
/**
Reads the current value of the Control Register 4 (CR4).
@@ -224,17 +222,16 @@ AsmReadCr4 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"mov %%cr4, %0"
: "=r" (Data) // %0
- );
+ );
return Data;
}
-
/**
Writes a value to Control Register 0 (CR0).
@@ -256,11 +253,10 @@ AsmWriteCr0 (
"mov %0, %%cr0"
:
: "r" (Cr0)
- );
+ );
return Cr0;
}
-
/**
Writes a value to Control Register 2 (CR2).
@@ -282,11 +278,10 @@ AsmWriteCr2 (
"mov %0, %%cr2"
:
: "r" (Cr2)
- );
+ );
return Cr2;
}
-
/**
Writes a value to Control Register 3 (CR3).
@@ -308,11 +303,10 @@ AsmWriteCr3 (
"mov %0, %%cr3"
:
: "r" (Cr3)
- );
+ );
return Cr3;
}
-
/**
Writes a value to Control Register 4 (CR4).
@@ -334,11 +328,10 @@ AsmWriteCr4 (
"mov %0, %%cr4"
:
: "r" (Cr4)
- );
+ );
return Cr4;
}
-
/**
Reads the current value of Debug Register 0 (DR0).
@@ -355,17 +348,16 @@ AsmReadDr0 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"mov %%dr0, %0"
: "=r" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of Debug Register 1 (DR1).
@@ -382,17 +374,16 @@ AsmReadDr1 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"mov %%dr1, %0"
: "=r" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of Debug Register 2 (DR2).
@@ -409,17 +400,16 @@ AsmReadDr2 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"mov %%dr2, %0"
: "=r" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of Debug Register 3 (DR3).
@@ -436,17 +426,16 @@ AsmReadDr3 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"mov %%dr3, %0"
: "=r" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of Debug Register 4 (DR4).
@@ -463,17 +452,16 @@ AsmReadDr4 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"mov %%dr4, %0"
: "=r" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of Debug Register 5 (DR5).
@@ -490,17 +478,16 @@ AsmReadDr5 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"mov %%dr5, %0"
: "=r" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of Debug Register 6 (DR6).
@@ -517,17 +504,16 @@ AsmReadDr6 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"mov %%dr6, %0"
: "=r" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of Debug Register 7 (DR7).
@@ -544,17 +530,16 @@ AsmReadDr7 (
VOID
)
{
- UINTN Data;
+ UINTN Data;
__asm__ __volatile__ (
"mov %%dr7, %0"
: "=r" (Data)
- );
+ );
return Data;
}
-
/**
Writes a value to Debug Register 0 (DR0).
@@ -576,11 +561,10 @@ AsmWriteDr0 (
"mov %0, %%dr0"
:
: "r" (Dr0)
- );
+ );
return Dr0;
}
-
/**
Writes a value to Debug Register 1 (DR1).
@@ -602,11 +586,10 @@ AsmWriteDr1 (
"mov %0, %%dr1"
:
: "r" (Dr1)
- );
+ );
return Dr1;
}
-
/**
Writes a value to Debug Register 2 (DR2).
@@ -628,11 +611,10 @@ AsmWriteDr2 (
"mov %0, %%dr2"
:
: "r" (Dr2)
- );
+ );
return Dr2;
}
-
/**
Writes a value to Debug Register 3 (DR3).
@@ -654,11 +636,10 @@ AsmWriteDr3 (
"mov %0, %%dr3"
:
: "r" (Dr3)
- );
+ );
return Dr3;
}
-
/**
Writes a value to Debug Register 4 (DR4).
@@ -680,11 +661,10 @@ AsmWriteDr4 (
"mov %0, %%dr4"
:
: "r" (Dr4)
- );
+ );
return Dr4;
}
-
/**
Writes a value to Debug Register 5 (DR5).
@@ -706,11 +686,10 @@ AsmWriteDr5 (
"mov %0, %%dr5"
:
: "r" (Dr5)
- );
+ );
return Dr5;
}
-
/**
Writes a value to Debug Register 6 (DR6).
@@ -732,11 +711,10 @@ AsmWriteDr6 (
"mov %0, %%dr6"
:
: "r" (Dr6)
- );
+ );
return Dr6;
}
-
/**
Writes a value to Debug Register 7 (DR7).
@@ -758,11 +736,10 @@ AsmWriteDr7 (
"mov %0, %%dr7"
:
: "r" (Dr7)
- );
+ );
return Dr7;
}
-
/**
Reads the current value of Code Segment Register (CS).
@@ -783,12 +760,11 @@ AsmReadCs (
__asm__ __volatile__ (
"mov %%cs, %0"
:"=a" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of Data Segment Register (DS).
@@ -809,12 +785,11 @@ AsmReadDs (
__asm__ __volatile__ (
"mov %%ds, %0"
:"=a" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of Extra Segment Register (ES).
@@ -835,12 +810,11 @@ AsmReadEs (
__asm__ __volatile__ (
"mov %%es, %0"
:"=a" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of FS Data Segment Register (FS).
@@ -861,12 +835,11 @@ AsmReadFs (
__asm__ __volatile__ (
"mov %%fs, %0"
:"=a" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of GS Data Segment Register (GS).
@@ -887,12 +860,11 @@ AsmReadGs (
__asm__ __volatile__ (
"mov %%gs, %0"
:"=a" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of Stack Segment Register (SS).
@@ -913,12 +885,11 @@ AsmReadSs (
__asm__ __volatile__ (
"mov %%ss, %0"
:"=a" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current value of Task Register (TR).
@@ -939,12 +910,11 @@ AsmReadTr (
__asm__ __volatile__ (
"str %0"
: "=r" (Data)
- );
+ );
return Data;
}
-
/**
Reads the current Global Descriptor Table Register(GDTR) descriptor.
@@ -957,16 +927,15 @@ AsmReadTr (
VOID
EFIAPI
InternalX86ReadGdtr (
- OUT IA32_DESCRIPTOR *Gdtr
+ OUT IA32_DESCRIPTOR *Gdtr
)
{
__asm__ __volatile__ (
"sgdt %0"
: "=m" (*Gdtr)
- );
+ );
}
-
/**
Writes the current Global Descriptor Table Register (GDTR) descriptor.
@@ -979,18 +948,16 @@ InternalX86ReadGdtr (
VOID
EFIAPI
InternalX86WriteGdtr (
- IN CONST IA32_DESCRIPTOR *Gdtr
+ IN CONST IA32_DESCRIPTOR *Gdtr
)
{
__asm__ __volatile__ (
"lgdt %0"
:
: "m" (*Gdtr)
- );
-
+ );
}
-
/**
Reads the current Interrupt Descriptor Table Register(GDTR) descriptor.
@@ -1003,16 +970,15 @@ InternalX86WriteGdtr (
VOID
EFIAPI
InternalX86ReadIdtr (
- OUT IA32_DESCRIPTOR *Idtr
+ OUT IA32_DESCRIPTOR *Idtr
)
{
__asm__ __volatile__ (
"sidt %0"
: "=m" (*Idtr)
- );
+ );
}
-
/**
Writes the current Interrupt Descriptor Table Register(GDTR) descriptor.
@@ -1025,17 +991,16 @@ InternalX86ReadIdtr (
VOID
EFIAPI
InternalX86WriteIdtr (
- IN CONST IA32_DESCRIPTOR *Idtr
+ IN CONST IA32_DESCRIPTOR *Idtr
)
{
__asm__ __volatile__ (
"lidt %0"
:
: "m" (*Idtr)
- );
+ );
}
-
/**
Reads the current Local Descriptor Table Register(LDTR) selector.
@@ -1056,12 +1021,11 @@ AsmReadLdtr (
__asm__ __volatile__ (
"sldt %0"
: "=g" (Data) // %0
- );
+ );
return Data;
}
-
/**
Writes the current Local Descriptor Table Register (GDTR) selector.
@@ -1074,14 +1038,14 @@ AsmReadLdtr (
VOID
EFIAPI
AsmWriteLdtr (
- IN UINT16 Ldtr
+ IN UINT16 Ldtr
)
{
__asm__ __volatile__ (
"lldtw %0"
:
: "g" (Ldtr) // %0
- );
+ );
}
/**
@@ -1098,7 +1062,7 @@ AsmWriteLdtr (
UINT64
EFIAPI
AsmReadPmc (
- IN UINT32 Index
+ IN UINT32 Index
)
{
UINT32 LowData;
@@ -1109,7 +1073,7 @@ AsmReadPmc (
: "=a" (LowData),
"=d" (HiData)
: "c" (Index)
- );
+ );
return (((UINT64)HiData) << 32) | LowData;
}
@@ -1133,9 +1097,9 @@ AsmReadPmc (
UINTN
EFIAPI
AsmMonitor (
- IN UINTN Eax,
- IN UINTN Ecx,
- IN UINTN Edx
+ IN UINTN Eax,
+ IN UINTN Ecx,
+ IN UINTN Edx
)
{
__asm__ __volatile__ (
@@ -1144,7 +1108,7 @@ AsmMonitor (
: "a" (Eax),
"c" (Ecx),
"d" (Edx)
- );
+ );
return Eax;
}
@@ -1166,8 +1130,8 @@ AsmMonitor (
UINTN
EFIAPI
AsmMwait (
- IN UINTN Eax,
- IN UINTN Ecx
+ IN UINTN Eax,
+ IN UINTN Ecx
)
{
__asm__ __volatile__ (
@@ -1175,7 +1139,7 @@ AsmMwait (
:
: "a" (Eax),
"c" (Ecx)
- );
+ );
return Eax;
}
@@ -1210,10 +1174,8 @@ AsmInvd (
)
{
__asm__ __volatile__ ("invd":::"memory");
-
}
-
/**
Flushes a cache line from all the instruction and data caches within the
coherency domain of the CPU.
@@ -1232,7 +1194,7 @@ AsmInvd (
VOID *
EFIAPI
AsmFlushCacheLine (
- IN VOID *LinearAddress
+ IN VOID *LinearAddress
)
{
__asm__ __volatile__ (
@@ -1240,7 +1202,7 @@ AsmFlushCacheLine (
:
: "r" (LinearAddress)
: "memory"
- );
+ );
- return LinearAddress;
+ return LinearAddress;
}
diff --git a/MdePkg/Library/BaseLib/X64/LongJump.nasm b/MdePkg/Library/BaseLib/X64/LongJump.nasm
index 67c67ae8..16b40ea3 100644
--- a/MdePkg/Library/BaseLib/X64/LongJump.nasm
+++ b/MdePkg/Library/BaseLib/X64/LongJump.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -41,7 +41,7 @@ ASM_PFX(InternalLongJump):
push rdx ; save rdx
mov rdx, [rcx + 0xF8] ; rdx = target SSP
- READSSP_RAX
+ READSSP_RAS
sub rdx, rax ; rdx = delta
mov rax, rdx ; rax = delta
diff --git a/MdePkg/Library/BaseLib/X64/Monitor.nasm b/MdePkg/Library/BaseLib/X64/Monitor.nasm
index 642dc804..d8b56126 100644
--- a/MdePkg/Library/BaseLib/X64/Monitor.nasm
+++ b/MdePkg/Library/BaseLib/X64/Monitor.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -32,6 +32,6 @@ ASM_PFX(AsmMonitor):
mov eax, ecx
mov ecx, edx
mov edx, r8d
- DB 0xf, 1, 0xc8 ; monitor
+ monitor
ret
diff --git a/MdePkg/Library/BaseLib/X64/Mwait.nasm b/MdePkg/Library/BaseLib/X64/Mwait.nasm
index 10303c43..a49e73a5 100644
--- a/MdePkg/Library/BaseLib/X64/Mwait.nasm
+++ b/MdePkg/Library/BaseLib/X64/Mwait.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -30,6 +30,6 @@ global ASM_PFX(AsmMwait)
ASM_PFX(AsmMwait):
mov eax, ecx
mov ecx, edx
- DB 0xf, 1, 0xc9 ; mwait
+ mwait
ret
diff --git a/MdePkg/Library/BaseLib/X64/Non-existing.c b/MdePkg/Library/BaseLib/X64/Non-existing.c
index ca95ebbd..df04500e 100644
--- a/MdePkg/Library/BaseLib/X64/Non-existing.c
+++ b/MdePkg/Library/BaseLib/X64/Non-existing.c
@@ -46,8 +46,8 @@ VOID
EFIAPI
InternalX86EnablePaging32 (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
- IN VOID *Context1, OPTIONAL
- IN VOID *Context2, OPTIONAL
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL,
IN VOID *NewStack
)
{
@@ -91,8 +91,8 @@ VOID
EFIAPI
InternalX86DisablePaging32 (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
- IN VOID *Context1, OPTIONAL
- IN VOID *Context2, OPTIONAL
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL,
IN VOID *NewStack
)
{
@@ -102,7 +102,6 @@ InternalX86DisablePaging32 (
ASSERT (FALSE);
}
-
/**
Enables the 64-bit paging mode on the CPU.
@@ -133,11 +132,11 @@ InternalX86DisablePaging32 (
VOID
EFIAPI
InternalX86EnablePaging64 (
- IN UINT16 Cs,
- IN UINT64 EntryPoint,
- IN UINT64 Context1, OPTIONAL
- IN UINT64 Context2, OPTIONAL
- IN UINT64 NewStack
+ IN UINT16 Cs,
+ IN UINT64 EntryPoint,
+ IN UINT64 Context1 OPTIONAL,
+ IN UINT64 Context2 OPTIONAL,
+ IN UINT64 NewStack
)
{
//
diff --git a/MdePkg/Library/BaseLib/X64/RdRand.nasm b/MdePkg/Library/BaseLib/X64/RdRand.nasm
index 12ae1740..feda77be 100644
--- a/MdePkg/Library/BaseLib/X64/RdRand.nasm
+++ b/MdePkg/Library/BaseLib/X64/RdRand.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -26,9 +26,8 @@
;------------------------------------------------------------------------------
global ASM_PFX(InternalX86RdRand16)
ASM_PFX(InternalX86RdRand16):
- ; rdrand ax ; generate a 16 bit RN into eax,
+ rdrand eax ; generate a 16 bit RN into eax,
; CF=1 if RN generated ok, otherwise CF=0
- db 0xf, 0xc7, 0xf0 ; rdrand r16: "0f c7 /6 ModRM:r/m(w)"
jc rn16_ok ; jmp if CF=1
xor rax, rax ; reg=0 if CF=0
ret ; return with failure status
@@ -45,9 +44,8 @@ rn16_ok:
;------------------------------------------------------------------------------
global ASM_PFX(InternalX86RdRand32)
ASM_PFX(InternalX86RdRand32):
- ; rdrand eax ; generate a 32 bit RN into eax,
+ rdrand eax ; generate a 32 bit RN into eax,
; CF=1 if RN generated ok, otherwise CF=0
- db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6 ModRM:r/m(w)"
jc rn32_ok ; jmp if CF=1
xor rax, rax ; reg=0 if CF=0
ret ; return with failure status
@@ -64,9 +62,8 @@ rn32_ok:
;------------------------------------------------------------------------------
global ASM_PFX(InternalX86RdRand64)
ASM_PFX(InternalX86RdRand64):
- ; rdrand rax ; generate a 64 bit RN into rax,
+ rdrand rax ; generate a 64 bit RN into rax,
; CF=1 if RN generated ok, otherwise CF=0
- db 0x48, 0xf, 0xc7, 0xf0 ; rdrand r64: "REX.W + 0f c7 /6 ModRM:r/m(w)"
jc rn64_ok ; jmp if CF=1
xor rax, rax ; reg=0 if CF=0
ret ; return with failure status
diff --git a/MdePkg/Library/BaseLib/X64/ReadDr4.nasm b/MdePkg/Library/BaseLib/X64/ReadDr4.nasm
index 9c656930..f92b90f3 100644
--- a/MdePkg/Library/BaseLib/X64/ReadDr4.nasm
+++ b/MdePkg/Library/BaseLib/X64/ReadDr4.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -31,6 +31,6 @@ ASM_PFX(AsmReadDr4):
; There's no obvious reason to access this register, since it's aliased to
; DR7 when DE=0 or an exception generated when DE=1
;
- DB 0xf, 0x21, 0xe0
+ mov rax, dr4
ret
diff --git a/MdePkg/Library/BaseLib/X64/ReadDr5.nasm b/MdePkg/Library/BaseLib/X64/ReadDr5.nasm
index da24b489..2798a853 100644
--- a/MdePkg/Library/BaseLib/X64/ReadDr5.nasm
+++ b/MdePkg/Library/BaseLib/X64/ReadDr5.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -31,6 +31,6 @@ ASM_PFX(AsmReadDr5):
; There's no obvious reason to access this register, since it's aliased to
; DR7 when DE=0 or an exception generated when DE=1
;
- DB 0xf, 0x21, 0xe8
+ mov rax, dr5
ret
diff --git a/MdePkg/Library/BaseLib/X64/ReadMm0.nasm b/MdePkg/Library/BaseLib/X64/ReadMm0.nasm
index a604ddf8..d38bf4e6 100644
--- a/MdePkg/Library/BaseLib/X64/ReadMm0.nasm
+++ b/MdePkg/Library/BaseLib/X64/ReadMm0.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -27,9 +27,6 @@
;------------------------------------------------------------------------------
global ASM_PFX(AsmReadMm0)
ASM_PFX(AsmReadMm0):
- ;
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here
- ;
- DB 0x48, 0xf, 0x7e, 0xc0
+ movq rax, mm0
ret
diff --git a/MdePkg/Library/BaseLib/X64/ReadMm1.nasm b/MdePkg/Library/BaseLib/X64/ReadMm1.nasm
index b534a3f3..69f3d7e8 100644
--- a/MdePkg/Library/BaseLib/X64/ReadMm1.nasm
+++ b/MdePkg/Library/BaseLib/X64/ReadMm1.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -27,9 +27,6 @@
;------------------------------------------------------------------------------
global ASM_PFX(AsmReadMm1)
ASM_PFX(AsmReadMm1):
- ;
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here
- ;
- DB 0x48, 0xf, 0x7e, 0xc8
+ movq rax, mm1
ret
diff --git a/MdePkg/Library/BaseLib/X64/ReadMm2.nasm b/MdePkg/Library/BaseLib/X64/ReadMm2.nasm
index 27612fd1..1027ee1d 100644
--- a/MdePkg/Library/BaseLib/X64/ReadMm2.nasm
+++ b/MdePkg/Library/BaseLib/X64/ReadMm2.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -27,9 +27,6 @@
;------------------------------------------------------------------------------
global ASM_PFX(AsmReadMm2)
ASM_PFX(AsmReadMm2):
- ;
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here
- ;
- DB 0x48, 0xf, 0x7e, 0xd0
+ movq rax, mm2
ret
diff --git a/MdePkg/Library/BaseLib/X64/ReadMm3.nasm b/MdePkg/Library/BaseLib/X64/ReadMm3.nasm
index 87b6e649..264e1e6e 100644
--- a/MdePkg/Library/BaseLib/X64/ReadMm3.nasm
+++ b/MdePkg/Library/BaseLib/X64/ReadMm3.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -27,9 +27,6 @@
;------------------------------------------------------------------------------
global ASM_PFX(AsmReadMm3)
ASM_PFX(AsmReadMm3):
- ;
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here
- ;
- DB 0x48, 0xf, 0x7e, 0xd8
+ movq rax, mm3
ret
diff --git a/MdePkg/Library/BaseLib/X64/ReadMm4.nasm b/MdePkg/Library/BaseLib/X64/ReadMm4.nasm
index 461910bd..24da5e21 100644
--- a/MdePkg/Library/BaseLib/X64/ReadMm4.nasm
+++ b/MdePkg/Library/BaseLib/X64/ReadMm4.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -27,9 +27,6 @@
;------------------------------------------------------------------------------
global ASM_PFX(AsmReadMm4)
ASM_PFX(AsmReadMm4):
- ;
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here
- ;
- DB 0x48, 0xf, 0x7e, 0xe0
+ movq rax, mm4
ret
diff --git a/MdePkg/Library/BaseLib/X64/ReadMm5.nasm b/MdePkg/Library/BaseLib/X64/ReadMm5.nasm
index ef4ac782..338d708a 100644
--- a/MdePkg/Library/BaseLib/X64/ReadMm5.nasm
+++ b/MdePkg/Library/BaseLib/X64/ReadMm5.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -27,9 +27,6 @@
;------------------------------------------------------------------------------
global ASM_PFX(AsmReadMm5)
ASM_PFX(AsmReadMm5):
- ;
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here
- ;
- DB 0x48, 0xf, 0x7e, 0xe8
+ movq rax, mm5
ret
diff --git a/MdePkg/Library/BaseLib/X64/ReadMm6.nasm b/MdePkg/Library/BaseLib/X64/ReadMm6.nasm
index 12742826..c1cb0b83 100644
--- a/MdePkg/Library/BaseLib/X64/ReadMm6.nasm
+++ b/MdePkg/Library/BaseLib/X64/ReadMm6.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -27,9 +27,6 @@
;------------------------------------------------------------------------------
global ASM_PFX(AsmReadMm6)
ASM_PFX(AsmReadMm6):
- ;
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here
- ;
- DB 0x48, 0xf, 0x7e, 0xf0
+ movq rax, mm6
ret
diff --git a/MdePkg/Library/BaseLib/X64/ReadMm7.nasm b/MdePkg/Library/BaseLib/X64/ReadMm7.nasm
index a4882344..3b7fdd74 100644
--- a/MdePkg/Library/BaseLib/X64/ReadMm7.nasm
+++ b/MdePkg/Library/BaseLib/X64/ReadMm7.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -27,9 +27,6 @@
;------------------------------------------------------------------------------
global ASM_PFX(AsmReadMm7)
ASM_PFX(AsmReadMm7):
- ;
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here
- ;
- DB 0x48, 0xf, 0x7e, 0xf8
+ movq rax, mm7
ret
diff --git a/MdePkg/Library/BaseLib/X64/ReadMsr64.c b/MdePkg/Library/BaseLib/X64/ReadMsr64.c
index 8222ab15..e357c436 100644
--- a/MdePkg/Library/BaseLib/X64/ReadMsr64.c
+++ b/MdePkg/Library/BaseLib/X64/ReadMsr64.c
@@ -12,7 +12,10 @@
#include
-unsigned __int64 __readmsr (int register);
+unsigned __int64
+__readmsr (
+ int register
+ );
#pragma intrinsic(__readmsr)
@@ -30,15 +33,15 @@ AsmReadMsr64 (
IN UINT32 Index
)
{
- UINT64 Value;
- BOOLEAN Flag;
+ UINT64 Value;
+ BOOLEAN Flag;
Flag = FilterBeforeMsrRead (Index, &Value);
if (Flag) {
Value = __readmsr (Index);
}
+
FilterAfterMsrRead (Index, &Value);
return Value;
}
-
diff --git a/MdePkg/Library/BaseLib/X64/SetJump.nasm b/MdePkg/Library/BaseLib/X64/SetJump.nasm
index 4b00bea5..8313adcd 100644
--- a/MdePkg/Library/BaseLib/X64/SetJump.nasm
+++ b/MdePkg/Library/BaseLib/X64/SetJump.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
diff --git a/MdePkg/Library/BaseLib/X64/TdCall.nasm b/MdePkg/Library/BaseLib/X64/TdCall.nasm
new file mode 100644
index 00000000..7c64b9b3
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X64/TdCall.nasm
@@ -0,0 +1,85 @@
+;------------------------------------------------------------------------------
+;*
+;* Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+;* SPDX-License-Identifier: BSD-2-Clause-Patent
+;*
+;*
+;------------------------------------------------------------------------------
+
+DEFAULT REL
+SECTION .text
+
+%macro tdcall 0
+ db 0x66,0x0f,0x01,0xcc
+%endmacro
+
+%macro tdcall_push_regs 0
+ push rbp
+ mov rbp, rsp
+ push r15
+ push r14
+ push r13
+ push r12
+ push rbx
+ push rsi
+ push rdi
+%endmacro
+
+%macro tdcall_pop_regs 0
+ pop rdi
+ pop rsi
+ pop rbx
+ pop r12
+ pop r13
+ pop r14
+ pop r15
+ pop rbp
+%endmacro
+
+%define number_of_regs_pushed 8
+%define number_of_parameters 4
+
+;
+; Keep these in sync for push_regs/pop_regs, code below
+; uses them to find 5th or greater parameters
+;
+%define first_variable_on_stack_offset \
+ ((number_of_regs_pushed * 8) + (number_of_parameters * 8) + 8)
+%define second_variable_on_stack_offset \
+ ((first_variable_on_stack_offset) + 8)
+
+; TdCall (
+; UINT64 Leaf, // Rcx
+; UINT64 P1, // Rdx
+; UINT64 P2, // R8
+; UINT64 P3, // R9
+; UINT64 Results, // rsp + 0x28
+; )
+global ASM_PFX(TdCall)
+ASM_PFX(TdCall):
+ tdcall_push_regs
+
+ mov rax, rcx
+ mov rcx, rdx
+ mov rdx, r8
+ mov r8, r9
+
+ tdcall
+
+ ; exit if tdcall reports failure.
+ test rax, rax
+ jnz .exit
+
+ ; test if caller wanted results
+ mov r12, [rsp + first_variable_on_stack_offset ]
+ test r12, r12
+ jz .exit
+ mov [r12 + 0 ], rcx
+ mov [r12 + 8 ], rdx
+ mov [r12 + 16], r8
+ mov [r12 + 24], r9
+ mov [r12 + 32], r10
+ mov [r12 + 40], r11
+.exit:
+ tdcall_pop_regs
+ ret
diff --git a/MdePkg/Library/BaseLib/X64/TdProbe.c b/MdePkg/Library/BaseLib/X64/TdProbe.c
new file mode 100644
index 00000000..9325cc83
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X64/TdProbe.c
@@ -0,0 +1,63 @@
+/** @file
+
+ Copyright (c) 2020-2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+
+/**
+ Probe if TD is enabled.
+
+ @return TRUE TD is enabled.
+ @return FALSE TD is not enabled.
+**/
+BOOLEAN
+EFIAPI
+TdIsEnabled (
+ )
+{
+ UINT32 Eax;
+ UINT32 Ebx;
+ UINT32 Ecx;
+ UINT32 Edx;
+ UINT32 LargestEax;
+ BOOLEAN TdEnabled;
+ CPUID_VERSION_INFO_ECX CpuIdVersionInfoEcx;
+
+ TdEnabled = FALSE;
+
+ do {
+ AsmCpuid (CPUID_SIGNATURE, &LargestEax, &Ebx, &Ecx, &Edx);
+
+ if ( (Ebx != CPUID_SIGNATURE_GENUINE_INTEL_EBX)
+ || (Edx != CPUID_SIGNATURE_GENUINE_INTEL_EDX)
+ || (Ecx != CPUID_SIGNATURE_GENUINE_INTEL_ECX))
+ {
+ break;
+ }
+
+ AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, &CpuIdVersionInfoEcx.Uint32, NULL);
+ if (CpuIdVersionInfoEcx.Bits.ParaVirtualized == 0) {
+ break;
+ }
+
+ if (LargestEax < CPUID_GUESTTD_RUNTIME_ENVIRONMENT) {
+ break;
+ }
+
+ AsmCpuidEx (CPUID_GUESTTD_RUNTIME_ENVIRONMENT, 0, &Eax, &Ebx, &Ecx, &Edx);
+ if ( (Ebx != CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_EBX)
+ || (Edx != CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_EDX)
+ || (Ecx != CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_ECX))
+ {
+ break;
+ }
+
+ TdEnabled = TRUE;
+ } while (FALSE);
+
+ return TdEnabled;
+}
diff --git a/MdePkg/Library/BaseLib/X64/TdVmcall.nasm b/MdePkg/Library/BaseLib/X64/TdVmcall.nasm
new file mode 100644
index 00000000..440307e3
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X64/TdVmcall.nasm
@@ -0,0 +1,143 @@
+;------------------------------------------------------------------------------
+;*
+;* Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+;* SPDX-License-Identifier: BSD-2-Clause-Patent
+;*
+;*
+;------------------------------------------------------------------------------
+
+DEFAULT REL
+SECTION .text
+
+%define TDVMCALL_EXPOSE_REGS_MASK 0xffec
+%define TDVMCALL 0x0
+
+%macro tdcall 0
+ db 0x66,0x0f,0x01,0xcc
+%endmacro
+
+%macro tdcall_push_regs 0
+ push rbp
+ mov rbp, rsp
+ push r15
+ push r14
+ push r13
+ push r12
+ push rbx
+ push rsi
+ push rdi
+%endmacro
+
+%macro tdcall_pop_regs 0
+ pop rdi
+ pop rsi
+ pop rbx
+ pop r12
+ pop r13
+ pop r14
+ pop r15
+ pop rbp
+%endmacro
+
+%define number_of_regs_pushed 8
+%define number_of_parameters 4
+
+;
+; Keep these in sync for push_regs/pop_regs, code below
+; uses them to find 5th or greater parameters
+;
+%define first_variable_on_stack_offset \
+ ((number_of_regs_pushed * 8) + (number_of_parameters * 8) + 8)
+%define second_variable_on_stack_offset \
+ ((first_variable_on_stack_offset) + 8)
+
+%macro tdcall_regs_preamble 2
+ mov rax, %1
+
+ xor rcx, rcx
+ mov ecx, %2
+
+ ; R10 = 0 (standard TDVMCALL)
+
+ xor r10d, r10d
+
+ ; Zero out unused (for standard TDVMCALL) registers to avoid leaking
+ ; secrets to the VMM.
+
+ xor ebx, ebx
+ xor esi, esi
+ xor edi, edi
+
+ xor edx, edx
+ xor ebp, ebp
+ xor r8d, r8d
+ xor r9d, r9d
+%endmacro
+
+%macro tdcall_regs_postamble 0
+ xor ebx, ebx
+ xor esi, esi
+ xor edi, edi
+
+ xor ecx, ecx
+ xor edx, edx
+ xor r8d, r8d
+ xor r9d, r9d
+ xor r10d, r10d
+ xor r11d, r11d
+%endmacro
+
+;------------------------------------------------------------------------------
+; 0 => RAX = TDCALL leaf
+; M => RCX = TDVMCALL register behavior
+; 1 => R10 = standard vs. vendor
+; RDI => R11 = TDVMCALL function / nr
+; RSI = R12 = p1
+; RDX => R13 = p2
+; RCX => R14 = p3
+; R8 => R15 = p4
+
+; UINT64
+; EFIAPI
+; TdVmCall (
+; UINT64 Leaf, // Rcx
+; UINT64 P1, // Rdx
+; UINT64 P2, // R8
+; UINT64 P3, // R9
+; UINT64 P4, // rsp + 0x28
+; UINT64 *Val // rsp + 0x30
+; )
+global ASM_PFX(TdVmCall)
+ASM_PFX(TdVmCall):
+ tdcall_push_regs
+
+ mov r11, rcx
+ mov r12, rdx
+ mov r13, r8
+ mov r14, r9
+ mov r15, [rsp + first_variable_on_stack_offset ]
+
+ tdcall_regs_preamble TDVMCALL, TDVMCALL_EXPOSE_REGS_MASK
+
+ tdcall
+
+ ; ignore return dataif TDCALL reports failure.
+ test rax, rax
+ jnz .no_return_data
+
+ ; Propagate TDVMCALL success/failure to return value.
+ mov rax, r10
+
+ ; Retrieve the Val pointer.
+ mov r9, [rsp + second_variable_on_stack_offset ]
+ test r9, r9
+ jz .no_return_data
+
+ ; Propagate TDVMCALL output value to output param
+ mov [r9], r11
+.no_return_data:
+ tdcall_regs_postamble
+
+ tdcall_pop_regs
+
+ ret
diff --git a/MdePkg/Library/BaseLib/X64/WriteDr4.nasm b/MdePkg/Library/BaseLib/X64/WriteDr4.nasm
index 0bf0c4fb..6ac1d007 100644
--- a/MdePkg/Library/BaseLib/X64/WriteDr4.nasm
+++ b/MdePkg/Library/BaseLib/X64/WriteDr4.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -31,7 +31,7 @@ ASM_PFX(AsmWriteDr4):
; There's no obvious reason to access this register, since it's aliased to
; DR6 when DE=0 or an exception generated when DE=1
;
- DB 0xf, 0x23, 0xe1
+ mov dr4, rcx
mov rax, rcx
ret
diff --git a/MdePkg/Library/BaseLib/X64/WriteDr5.nasm b/MdePkg/Library/BaseLib/X64/WriteDr5.nasm
index e38d7ac7..1d97434a 100644
--- a/MdePkg/Library/BaseLib/X64/WriteDr5.nasm
+++ b/MdePkg/Library/BaseLib/X64/WriteDr5.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -31,7 +31,7 @@ ASM_PFX(AsmWriteDr5):
; There's no obvious reason to access this register, since it's aliased to
; DR7 when DE=0 or an exception generated when DE=1
;
- DB 0xf, 0x23, 0xe9
+ mov dr5, rcx
mov rax, rcx
ret
diff --git a/MdePkg/Library/BaseLib/X64/WriteMm0.nasm b/MdePkg/Library/BaseLib/X64/WriteMm0.nasm
index f18e4d51..54276b3a 100644
--- a/MdePkg/Library/BaseLib/X64/WriteMm0.nasm
+++ b/MdePkg/Library/BaseLib/X64/WriteMm0.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -27,9 +27,6 @@
;------------------------------------------------------------------------------
global ASM_PFX(AsmWriteMm0)
ASM_PFX(AsmWriteMm0):
- ;
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here
- ;
- DB 0x48, 0xf, 0x6e, 0xc1
+ movq mm0, rcx
ret
diff --git a/MdePkg/Library/BaseLib/X64/WriteMm1.nasm b/MdePkg/Library/BaseLib/X64/WriteMm1.nasm
index 536daa70..b56a498c 100644
--- a/MdePkg/Library/BaseLib/X64/WriteMm1.nasm
+++ b/MdePkg/Library/BaseLib/X64/WriteMm1.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -27,9 +27,6 @@
;------------------------------------------------------------------------------
global ASM_PFX(AsmWriteMm1)
ASM_PFX(AsmWriteMm1):
- ;
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here
- ;
- DB 0x48, 0xf, 0x6e, 0xc9
+ movq mm1, rcx
ret
diff --git a/MdePkg/Library/BaseLib/X64/WriteMm2.nasm b/MdePkg/Library/BaseLib/X64/WriteMm2.nasm
index 543cdf44..2f703bb0 100644
--- a/MdePkg/Library/BaseLib/X64/WriteMm2.nasm
+++ b/MdePkg/Library/BaseLib/X64/WriteMm2.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -27,9 +27,6 @@
;------------------------------------------------------------------------------
global ASM_PFX(AsmWriteMm2)
ASM_PFX(AsmWriteMm2):
- ;
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here
- ;
- DB 0x48, 0xf, 0x6e, 0xd1
+ movq mm2, rcx
ret
diff --git a/MdePkg/Library/BaseLib/X64/WriteMm3.nasm b/MdePkg/Library/BaseLib/X64/WriteMm3.nasm
index fa269acd..76bd6dc0 100644
--- a/MdePkg/Library/BaseLib/X64/WriteMm3.nasm
+++ b/MdePkg/Library/BaseLib/X64/WriteMm3.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -27,9 +27,6 @@
;------------------------------------------------------------------------------
global ASM_PFX(AsmWriteMm3)
ASM_PFX(AsmWriteMm3):
- ;
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here
- ;
- DB 0x48, 0xf, 0x6e, 0xd9
+ movq mm3, rcx
ret
diff --git a/MdePkg/Library/BaseLib/X64/WriteMm4.nasm b/MdePkg/Library/BaseLib/X64/WriteMm4.nasm
index e6c1bb28..962df8c8 100644
--- a/MdePkg/Library/BaseLib/X64/WriteMm4.nasm
+++ b/MdePkg/Library/BaseLib/X64/WriteMm4.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -27,9 +27,6 @@
;------------------------------------------------------------------------------
global ASM_PFX(AsmWriteMm4)
ASM_PFX(AsmWriteMm4):
- ;
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here
- ;
- DB 0x48, 0xf, 0x6e, 0xe1
+ movq mm4, rcx
ret
diff --git a/MdePkg/Library/BaseLib/X64/WriteMm5.nasm b/MdePkg/Library/BaseLib/X64/WriteMm5.nasm
index 477cbe3c..b6fad650 100644
--- a/MdePkg/Library/BaseLib/X64/WriteMm5.nasm
+++ b/MdePkg/Library/BaseLib/X64/WriteMm5.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -27,9 +27,6 @@
;------------------------------------------------------------------------------
global ASM_PFX(AsmWriteMm5)
ASM_PFX(AsmWriteMm5):
- ;
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here
- ;
- DB 0x48, 0xf, 0x6e, 0xe9
+ movq mm5, rcx
ret
diff --git a/MdePkg/Library/BaseLib/X64/WriteMm6.nasm b/MdePkg/Library/BaseLib/X64/WriteMm6.nasm
index c58c762d..f85ae349 100644
--- a/MdePkg/Library/BaseLib/X64/WriteMm6.nasm
+++ b/MdePkg/Library/BaseLib/X64/WriteMm6.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -27,9 +27,6 @@
;------------------------------------------------------------------------------
global ASM_PFX(AsmWriteMm6)
ASM_PFX(AsmWriteMm6):
- ;
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here
- ;
- DB 0x48, 0xf, 0x6e, 0xf1
+ movq mm6, rcx
ret
diff --git a/MdePkg/Library/BaseLib/X64/WriteMm7.nasm b/MdePkg/Library/BaseLib/X64/WriteMm7.nasm
index 7a50db79..cf4cd882 100644
--- a/MdePkg/Library/BaseLib/X64/WriteMm7.nasm
+++ b/MdePkg/Library/BaseLib/X64/WriteMm7.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -27,9 +27,6 @@
;------------------------------------------------------------------------------
global ASM_PFX(AsmWriteMm7)
ASM_PFX(AsmWriteMm7):
- ;
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here
- ;
- DB 0x48, 0xf, 0x6e, 0xf9
+ movq mm7, rcx
ret
diff --git a/MdePkg/Library/BaseLib/X64/WriteMsr64.c b/MdePkg/Library/BaseLib/X64/WriteMsr64.c
index 50a8adfc..75af72da 100644
--- a/MdePkg/Library/BaseLib/X64/WriteMsr64.c
+++ b/MdePkg/Library/BaseLib/X64/WriteMsr64.c
@@ -12,7 +12,11 @@
#include
-void __writemsr (unsigned long Register, unsigned __int64 Value);
+void
+__writemsr (
+ unsigned long Register,
+ unsigned __int64 Value
+ );
#pragma intrinsic(__writemsr)
@@ -32,14 +36,14 @@ AsmWriteMsr64 (
IN UINT64 Value
)
{
- BOOLEAN Flag;
+ BOOLEAN Flag;
Flag = FilterBeforeMsrWrite (Index, &Value);
if (Flag) {
__writemsr (Index, Value);
}
+
FilterAfterMsrWrite (Index, &Value);
return Value;
}
-
diff --git a/MdePkg/Library/BaseLib/X86DisablePaging32.c b/MdePkg/Library/BaseLib/X86DisablePaging32.c
index 3cb4b210..278efebc 100644
--- a/MdePkg/Library/BaseLib/X86DisablePaging32.c
+++ b/MdePkg/Library/BaseLib/X86DisablePaging32.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -49,8 +46,8 @@ VOID
EFIAPI
AsmDisablePaging32 (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
- IN VOID *Context1, OPTIONAL
- IN VOID *Context2, OPTIONAL
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL,
IN VOID *NewStack
)
{
diff --git a/MdePkg/Library/BaseLib/X86DisablePaging64.c b/MdePkg/Library/BaseLib/X86DisablePaging64.c
index 6ce34162..5065faaa 100644
--- a/MdePkg/Library/BaseLib/X86DisablePaging64.c
+++ b/MdePkg/Library/BaseLib/X86DisablePaging64.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -44,11 +41,11 @@
VOID
EFIAPI
AsmDisablePaging64 (
- IN UINT16 Cs,
- IN UINT32 EntryPoint,
- IN UINT32 Context1, OPTIONAL
- IN UINT32 Context2, OPTIONAL
- IN UINT32 NewStack
+ IN UINT16 Cs,
+ IN UINT32 EntryPoint,
+ IN UINT32 Context1 OPTIONAL,
+ IN UINT32 Context2 OPTIONAL,
+ IN UINT32 NewStack
)
{
ASSERT (EntryPoint != 0);
diff --git a/MdePkg/Library/BaseLib/X86EnablePaging32.c b/MdePkg/Library/BaseLib/X86EnablePaging32.c
index 22882e91..47d1d64d 100644
--- a/MdePkg/Library/BaseLib/X86EnablePaging32.c
+++ b/MdePkg/Library/BaseLib/X86EnablePaging32.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -52,8 +49,8 @@ VOID
EFIAPI
AsmEnablePaging32 (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
- IN VOID *Context1, OPTIONAL
- IN VOID *Context2, OPTIONAL
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL,
IN VOID *NewStack
)
{
diff --git a/MdePkg/Library/BaseLib/X86EnablePaging64.c b/MdePkg/Library/BaseLib/X86EnablePaging64.c
index 901046f7..ef433e43 100644
--- a/MdePkg/Library/BaseLib/X86EnablePaging64.c
+++ b/MdePkg/Library/BaseLib/X86EnablePaging64.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -46,11 +43,11 @@
VOID
EFIAPI
AsmEnablePaging64 (
- IN UINT16 Cs,
- IN UINT64 EntryPoint,
- IN UINT64 Context1, OPTIONAL
- IN UINT64 Context2, OPTIONAL
- IN UINT64 NewStack
+ IN UINT16 Cs,
+ IN UINT64 EntryPoint,
+ IN UINT64 Context1 OPTIONAL,
+ IN UINT64 Context2 OPTIONAL,
+ IN UINT64 NewStack
)
{
ASSERT (EntryPoint != 0);
diff --git a/MdePkg/Library/BaseLib/X86FxRestore.c b/MdePkg/Library/BaseLib/X86FxRestore.c
index ff08a503..c4c0b606 100644
--- a/MdePkg/Library/BaseLib/X86FxRestore.c
+++ b/MdePkg/Library/BaseLib/X86FxRestore.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -28,7 +25,7 @@
VOID
EFIAPI
AsmFxRestore (
- IN CONST IA32_FX_BUFFER *Buffer
+ IN CONST IA32_FX_BUFFER *Buffer
)
{
ASSERT (Buffer != NULL);
@@ -37,7 +34,7 @@ AsmFxRestore (
//
// Check the flag recorded by AsmFxSave()
//
- ASSERT (0xAA5555AA == *(UINT32 *) (&Buffer->Buffer[sizeof (Buffer->Buffer) - 4]));
+ ASSERT (0xAA5555AA == *(UINT32 *)(&Buffer->Buffer[sizeof (Buffer->Buffer) - 4]));
InternalX86FxRestore (Buffer);
}
diff --git a/MdePkg/Library/BaseLib/X86FxSave.c b/MdePkg/Library/BaseLib/X86FxSave.c
index 48700f0f..39990b45 100644
--- a/MdePkg/Library/BaseLib/X86FxSave.c
+++ b/MdePkg/Library/BaseLib/X86FxSave.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -27,7 +24,7 @@
VOID
EFIAPI
AsmFxSave (
- OUT IA32_FX_BUFFER *Buffer
+ OUT IA32_FX_BUFFER *Buffer
)
{
ASSERT (Buffer != NULL);
@@ -38,5 +35,5 @@ AsmFxSave (
//
// Mark one flag at end of Buffer, it will be check by AsmFxRestor()
//
- *(UINT32 *) (&Buffer->Buffer[sizeof (Buffer->Buffer) - 4]) = 0xAA5555AA;
+ *(UINT32 *)(&Buffer->Buffer[sizeof (Buffer->Buffer) - 4]) = 0xAA5555AA;
}
diff --git a/MdePkg/Library/BaseLib/X86GetInterruptState.c b/MdePkg/Library/BaseLib/X86GetInterruptState.c
index 13ed4718..23323b03 100644
--- a/MdePkg/Library/BaseLib/X86GetInterruptState.c
+++ b/MdePkg/Library/BaseLib/X86GetInterruptState.c
@@ -6,10 +6,8 @@
**/
-
#include "BaseLibInternals.h"
-
/**
Retrieves the current CPU interrupt state.
@@ -26,10 +24,8 @@ GetInterruptState (
VOID
)
{
- IA32_EFLAGS32 EFlags;
+ IA32_EFLAGS32 EFlags;
EFlags.UintN = AsmReadEflags ();
return (BOOLEAN)(1 == EFlags.Bits.IF);
}
-
-
diff --git a/MdePkg/Library/BaseLib/X86MemoryFence.c b/MdePkg/Library/BaseLib/X86MemoryFence.c
index 3ec2c1bf..ad9d33e1 100644
--- a/MdePkg/Library/BaseLib/X86MemoryFence.c
+++ b/MdePkg/Library/BaseLib/X86MemoryFence.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Used to serialize load and store operations.
diff --git a/MdePkg/Library/BaseLib/X86Msr.c b/MdePkg/Library/BaseLib/X86Msr.c
index 408dea47..422eb8c5 100644
--- a/MdePkg/Library/BaseLib/X86Msr.c
+++ b/MdePkg/Library/BaseLib/X86Msr.c
@@ -6,10 +6,8 @@
**/
-
#include "BaseLibInternals.h"
-
/**
Returns the lower 32-bits of a Machine Specific Register(MSR).
@@ -27,7 +25,7 @@
UINT32
EFIAPI
AsmReadMsr32 (
- IN UINT32 Index
+ IN UINT32 Index
)
{
return (UINT32)AsmReadMsr64 (Index);
@@ -53,8 +51,8 @@ AsmReadMsr32 (
UINT32
EFIAPI
AsmWriteMsr32 (
- IN UINT32 Index,
- IN UINT32 Value
+ IN UINT32 Index,
+ IN UINT32 Value
)
{
return (UINT32)AsmWriteMsr64 (Index, Value);
@@ -82,8 +80,8 @@ AsmWriteMsr32 (
UINT32
EFIAPI
AsmMsrOr32 (
- IN UINT32 Index,
- IN UINT32 OrData
+ IN UINT32 Index,
+ IN UINT32 OrData
)
{
return (UINT32)AsmMsrOr64 (Index, OrData);
@@ -111,8 +109,8 @@ AsmMsrOr32 (
UINT32
EFIAPI
AsmMsrAnd32 (
- IN UINT32 Index,
- IN UINT32 AndData
+ IN UINT32 Index,
+ IN UINT32 AndData
)
{
return (UINT32)AsmMsrAnd64 (Index, AndData);
@@ -143,9 +141,9 @@ AsmMsrAnd32 (
UINT32
EFIAPI
AsmMsrAndThenOr32 (
- IN UINT32 Index,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINT32 Index,
+ IN UINT32 AndData,
+ IN UINT32 OrData
)
{
return (UINT32)AsmMsrAndThenOr64 (Index, AndData, OrData);
@@ -176,9 +174,9 @@ AsmMsrAndThenOr32 (
UINT32
EFIAPI
AsmMsrBitFieldRead32 (
- IN UINT32 Index,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
return BitFieldRead32 (AsmReadMsr32 (Index), StartBit, EndBit);
@@ -212,10 +210,10 @@ AsmMsrBitFieldRead32 (
UINT32
EFIAPI
AsmMsrBitFieldWrite32 (
- IN UINT32 Index,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
)
{
ASSERT (EndBit < sizeof (Value) * 8);
@@ -253,10 +251,10 @@ AsmMsrBitFieldWrite32 (
UINT32
EFIAPI
AsmMsrBitFieldOr32 (
- IN UINT32 Index,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
)
{
ASSERT (EndBit < sizeof (OrData) * 8);
@@ -294,10 +292,10 @@ AsmMsrBitFieldOr32 (
UINT32
EFIAPI
AsmMsrBitFieldAnd32 (
- IN UINT32 Index,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
)
{
ASSERT (EndBit < sizeof (AndData) * 8);
@@ -339,11 +337,11 @@ AsmMsrBitFieldAnd32 (
UINT32
EFIAPI
AsmMsrBitFieldAndThenOr32 (
- IN UINT32 Index,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
)
{
ASSERT (EndBit < sizeof (AndData) * 8);
@@ -378,8 +376,8 @@ AsmMsrBitFieldAndThenOr32 (
UINT64
EFIAPI
AsmMsrOr64 (
- IN UINT32 Index,
- IN UINT64 OrData
+ IN UINT32 Index,
+ IN UINT64 OrData
)
{
return AsmWriteMsr64 (Index, AsmReadMsr64 (Index) | OrData);
@@ -406,8 +404,8 @@ AsmMsrOr64 (
UINT64
EFIAPI
AsmMsrAnd64 (
- IN UINT32 Index,
- IN UINT64 AndData
+ IN UINT32 Index,
+ IN UINT64 AndData
)
{
return AsmWriteMsr64 (Index, AsmReadMsr64 (Index) & AndData);
@@ -437,9 +435,9 @@ AsmMsrAnd64 (
UINT64
EFIAPI
AsmMsrAndThenOr64 (
- IN UINT32 Index,
- IN UINT64 AndData,
- IN UINT64 OrData
+ IN UINT32 Index,
+ IN UINT64 AndData,
+ IN UINT64 OrData
)
{
return AsmWriteMsr64 (Index, (AsmReadMsr64 (Index) & AndData) | OrData);
@@ -470,9 +468,9 @@ AsmMsrAndThenOr64 (
UINT64
EFIAPI
AsmMsrBitFieldRead64 (
- IN UINT32 Index,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
return BitFieldRead64 (AsmReadMsr64 (Index), StartBit, EndBit);
@@ -505,10 +503,10 @@ AsmMsrBitFieldRead64 (
UINT64
EFIAPI
AsmMsrBitFieldWrite64 (
- IN UINT32 Index,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 Value
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 Value
)
{
return AsmWriteMsr64 (
@@ -547,10 +545,10 @@ AsmMsrBitFieldWrite64 (
UINT64
EFIAPI
AsmMsrBitFieldOr64 (
- IN UINT32 Index,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 OrData
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 OrData
)
{
return AsmWriteMsr64 (
@@ -589,10 +587,10 @@ AsmMsrBitFieldOr64 (
UINT64
EFIAPI
AsmMsrBitFieldAnd64 (
- IN UINT32 Index,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 AndData
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData
)
{
return AsmWriteMsr64 (
@@ -634,11 +632,11 @@ AsmMsrBitFieldAnd64 (
UINT64
EFIAPI
AsmMsrBitFieldAndThenOr64 (
- IN UINT32 Index,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 AndData,
- IN UINT64 OrData
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData,
+ IN UINT64 OrData
)
{
return AsmWriteMsr64 (
diff --git a/MdePkg/Library/BaseLib/X86PatchInstruction.c b/MdePkg/Library/BaseLib/X86PatchInstruction.c
index 8add767c..1a2359fc 100644
--- a/MdePkg/Library/BaseLib/X86PatchInstruction.c
+++ b/MdePkg/Library/BaseLib/X86PatchInstruction.c
@@ -46,9 +46,9 @@
VOID
EFIAPI
PatchInstructionX86 (
- OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
- IN UINT64 PatchValue,
- IN UINTN ValueSize
+ OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
+ IN UINT64 PatchValue,
+ IN UINTN ValueSize
)
{
//
@@ -58,26 +58,26 @@ PatchInstructionX86 (
ASSERT ((UINTN)InstructionEnd > ValueSize);
switch (ValueSize) {
- case 1:
- ASSERT (PatchValue <= MAX_UINT8);
- *((UINT8 *)(UINTN)InstructionEnd - 1) = (UINT8)PatchValue;
- break;
+ case 1:
+ ASSERT (PatchValue <= MAX_UINT8);
+ *((UINT8 *)(UINTN)InstructionEnd - 1) = (UINT8)PatchValue;
+ break;
- case 2:
- ASSERT (PatchValue <= MAX_UINT16);
- WriteUnaligned16 ((UINT16 *)(UINTN)InstructionEnd - 1, (UINT16)PatchValue);
- break;
+ case 2:
+ ASSERT (PatchValue <= MAX_UINT16);
+ WriteUnaligned16 ((UINT16 *)(UINTN)InstructionEnd - 1, (UINT16)PatchValue);
+ break;
- case 4:
- ASSERT (PatchValue <= MAX_UINT32);
- WriteUnaligned32 ((UINT32 *)(UINTN)InstructionEnd - 1, (UINT32)PatchValue);
- break;
+ case 4:
+ ASSERT (PatchValue <= MAX_UINT32);
+ WriteUnaligned32 ((UINT32 *)(UINTN)InstructionEnd - 1, (UINT32)PatchValue);
+ break;
- case 8:
- WriteUnaligned64 ((UINT64 *)(UINTN)InstructionEnd - 1, PatchValue);
- break;
+ case 8:
+ WriteUnaligned64 ((UINT64 *)(UINTN)InstructionEnd - 1, PatchValue);
+ break;
- default:
- ASSERT (FALSE);
+ default:
+ ASSERT (FALSE);
}
}
diff --git a/MdePkg/Library/BaseLib/X86RdRand.c b/MdePkg/Library/BaseLib/X86RdRand.c
index 6c7c4aee..d9fd01af 100644
--- a/MdePkg/Library/BaseLib/X86RdRand.c
+++ b/MdePkg/Library/BaseLib/X86RdRand.c
@@ -23,7 +23,7 @@
BOOLEAN
EFIAPI
AsmRdRand16 (
- OUT UINT16 *Rand
+ OUT UINT16 *Rand
)
{
ASSERT (Rand != NULL);
@@ -44,7 +44,7 @@ AsmRdRand16 (
BOOLEAN
EFIAPI
AsmRdRand32 (
- OUT UINT32 *Rand
+ OUT UINT32 *Rand
)
{
ASSERT (Rand != NULL);
@@ -65,7 +65,7 @@ AsmRdRand32 (
BOOLEAN
EFIAPI
AsmRdRand64 (
- OUT UINT64 *Rand
+ OUT UINT64 *Rand
)
{
ASSERT (Rand != NULL);
diff --git a/MdePkg/Library/BaseLib/X86ReadGdtr.c b/MdePkg/Library/BaseLib/X86ReadGdtr.c
index 9d78e5c2..1209de53 100644
--- a/MdePkg/Library/BaseLib/X86ReadGdtr.c
+++ b/MdePkg/Library/BaseLib/X86ReadGdtr.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -25,7 +22,7 @@
VOID
EFIAPI
AsmReadGdtr (
- OUT IA32_DESCRIPTOR *Gdtr
+ OUT IA32_DESCRIPTOR *Gdtr
)
{
ASSERT (Gdtr != NULL);
diff --git a/MdePkg/Library/BaseLib/X86ReadIdtr.c b/MdePkg/Library/BaseLib/X86ReadIdtr.c
index 7b27f610..dc770bd3 100644
--- a/MdePkg/Library/BaseLib/X86ReadIdtr.c
+++ b/MdePkg/Library/BaseLib/X86ReadIdtr.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -25,7 +22,7 @@
VOID
EFIAPI
AsmReadIdtr (
- OUT IA32_DESCRIPTOR *Idtr
+ OUT IA32_DESCRIPTOR *Idtr
)
{
ASSERT (Idtr != NULL);
diff --git a/MdePkg/Library/BaseLib/X86Thunk.c b/MdePkg/Library/BaseLib/X86Thunk.c
index eec3d941..6cd1a1f1 100644
--- a/MdePkg/Library/BaseLib/X86Thunk.c
+++ b/MdePkg/Library/BaseLib/X86Thunk.c
@@ -6,15 +6,14 @@
**/
-
#include "BaseLibInternals.h"
-extern CONST UINT8 m16Start;
-extern CONST UINT16 m16Size;
-extern CONST UINT16 mThunk16Attr;
-extern CONST UINT16 m16Gdt;
-extern CONST UINT16 m16GdtrBase;
-extern CONST UINT16 mTransition;
+extern CONST UINT8 m16Start;
+extern CONST UINT16 m16Size;
+extern CONST UINT16 mThunk16Attr;
+extern CONST UINT16 m16Gdt;
+extern CONST UINT16 m16GdtrBase;
+extern CONST UINT16 mTransition;
/**
Invokes 16-bit code in big real mode and returns the updated register set.
@@ -33,8 +32,8 @@ extern CONST UINT16 mTransition;
IA32_REGISTER_SET *
EFIAPI
InternalAsmThunk16 (
- IN IA32_REGISTER_SET *RegisterSet,
- IN OUT VOID *Transition
+ IN IA32_REGISTER_SET *RegisterSet,
+ IN OUT VOID *Transition
);
/**
@@ -61,8 +60,8 @@ InternalAsmThunk16 (
VOID
EFIAPI
AsmGetThunk16Properties (
- OUT UINT32 *RealModeBufferSize,
- OUT UINT32 *ExtraStackSize
+ OUT UINT32 *RealModeBufferSize,
+ OUT UINT32 *ExtraStackSize
)
{
ASSERT (RealModeBufferSize != NULL);
@@ -93,10 +92,10 @@ AsmGetThunk16Properties (
VOID
EFIAPI
AsmPrepareThunk16 (
- IN OUT THUNK_CONTEXT *ThunkContext
+ IN OUT THUNK_CONTEXT *ThunkContext
)
{
- IA32_SEGMENT_DESCRIPTOR *RealModeGdt;
+ IA32_SEGMENT_DESCRIPTOR *RealModeGdt;
ASSERT (ThunkContext != NULL);
ASSERT ((UINTN)ThunkContext->RealModeBuffer < 0x100000);
@@ -113,8 +112,8 @@ AsmPrepareThunk16 (
// RealModeGdt[2]: Data Segment
// RealModeGdt[3]: Call Gate
//
- RealModeGdt = (IA32_SEGMENT_DESCRIPTOR*)(
- (UINTN)ThunkContext->RealModeBuffer + m16Gdt);
+ RealModeGdt = (IA32_SEGMENT_DESCRIPTOR *)(
+ (UINTN)ThunkContext->RealModeBuffer + m16Gdt);
//
// Update Code & Data Segment Descriptor
@@ -127,7 +126,7 @@ AsmPrepareThunk16 (
//
// Update transition code entry point offset
//
- *(UINT32*)((UINTN)ThunkContext->RealModeBuffer + mTransition) +=
+ *(UINT32 *)((UINTN)ThunkContext->RealModeBuffer + mTransition) +=
(UINT32)(UINTN)ThunkContext->RealModeBuffer & 0xf;
//
@@ -138,20 +137,20 @@ AsmPrepareThunk16 (
// Set segment limits to 64KB
//
RealModeGdt[1].Bits.LimitHigh = 0;
- RealModeGdt[1].Bits.G = 0;
+ RealModeGdt[1].Bits.G = 0;
RealModeGdt[2].Bits.LimitHigh = 0;
- RealModeGdt[2].Bits.G = 0;
+ RealModeGdt[2].Bits.G = 0;
}
//
// Update GDTBASE for this thunk context
//
- *(VOID**)((UINTN)ThunkContext->RealModeBuffer + m16GdtrBase) = RealModeGdt;
+ *(VOID **)((UINTN)ThunkContext->RealModeBuffer + m16GdtrBase) = RealModeGdt;
//
// Update Thunk Attributes
//
- *(UINT32*)((UINTN)ThunkContext->RealModeBuffer + mThunk16Attr) =
+ *(UINT32 *)((UINTN)ThunkContext->RealModeBuffer + mThunk16Attr) =
ThunkContext->ThunkAttributes;
}
@@ -211,17 +210,19 @@ AsmPrepareThunk16 (
VOID
EFIAPI
AsmThunk16 (
- IN OUT THUNK_CONTEXT *ThunkContext
+ IN OUT THUNK_CONTEXT *ThunkContext
)
{
- IA32_REGISTER_SET *UpdatedRegs;
+ IA32_REGISTER_SET *UpdatedRegs;
ASSERT (ThunkContext != NULL);
ASSERT ((UINTN)ThunkContext->RealModeBuffer < 0x100000);
ASSERT (ThunkContext->RealModeBufferSize >= m16Size);
ASSERT ((UINTN)ThunkContext->RealModeBuffer + m16Size <= 0x100000);
- ASSERT (((ThunkContext->ThunkAttributes & (THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 | THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL)) != \
- (THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 | THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL)));
+ ASSERT (
+ ((ThunkContext->ThunkAttributes & (THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 | THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL)) != \
+ (THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 | THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL))
+ );
UpdatedRegs = InternalAsmThunk16 (
ThunkContext->RealModeState,
@@ -254,7 +255,7 @@ AsmThunk16 (
VOID
EFIAPI
AsmPrepareAndThunk16 (
- IN OUT THUNK_CONTEXT *ThunkContext
+ IN OUT THUNK_CONTEXT *ThunkContext
)
{
AsmPrepareThunk16 (ThunkContext);
diff --git a/MdePkg/Library/BaseLib/X86UnitTestHost.c b/MdePkg/Library/BaseLib/X86UnitTestHost.c
new file mode 100644
index 00000000..f6316b91
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X86UnitTestHost.c
@@ -0,0 +1,2989 @@
+/** @file
+ IA32/X64 specific Unit Test Host functions.
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "UnitTestHost.h"
+
+///
+/// Defines for mUnitTestHostBaseLibSegment indexes
+///
+#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS 0
+#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS 1
+#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES 2
+#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS 3
+#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS 4
+#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS 5
+#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR 6
+#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR 7
+
+///
+/// Module global variables for simple system emulation of MSRs, CRx, DRx,
+/// GDTR, IDTR, and Segment Selectors.
+///
+STATIC UINT64 mUnitTestHostBaseLibMsr[2][0x1000];
+STATIC UINTN mUnitTestHostBaseLibCr[5];
+STATIC UINTN mUnitTestHostBaseLibDr[8];
+STATIC UINT16 mUnitTestHostBaseLibSegment[8];
+STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibGdtr;
+STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibIdtr;
+
+/**
+ Retrieves CPUID information.
+
+ Executes the CPUID instruction with EAX set to the value specified by Index.
+ This function always returns Index.
+ If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
+ If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
+ If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
+ If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
+ This function is only available on IA-32 and x64.
+
+ @param Index The 32-bit value to load into EAX prior to invoking the CPUID
+ instruction.
+ @param Eax The pointer to the 32-bit EAX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+ @param Ebx The pointer to the 32-bit EBX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+ @param Ecx The pointer to the 32-bit ECX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+ @param Edx The pointer to the 32-bit EDX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+
+ @return Index.
+
+**/
+UINT32
+EFIAPI
+UnitTestHostBaseLibAsmCpuid (
+ IN UINT32 Index,
+ OUT UINT32 *Eax OPTIONAL,
+ OUT UINT32 *Ebx OPTIONAL,
+ OUT UINT32 *Ecx OPTIONAL,
+ OUT UINT32 *Edx OPTIONAL
+ )
+{
+ if (Eax != NULL) {
+ *Eax = 0;
+ }
+
+ if (Ebx != NULL) {
+ *Ebx = 0;
+ }
+
+ if (Ecx != NULL) {
+ *Ecx = 0;
+ }
+
+ if (Edx != NULL) {
+ *Edx = 0;
+ }
+
+ return Index;
+}
+
+/**
+ Retrieves CPUID information using an extended leaf identifier.
+
+ Executes the CPUID instruction with EAX set to the value specified by Index
+ and ECX set to the value specified by SubIndex. This function always returns
+ Index. This function is only available on IA-32 and x64.
+
+ If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
+ If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
+ If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
+ If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
+
+ @param Index The 32-bit value to load into EAX prior to invoking the
+ CPUID instruction.
+ @param SubIndex The 32-bit value to load into ECX prior to invoking the
+ CPUID instruction.
+ @param Eax The pointer to the 32-bit EAX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+ @param Ebx The pointer to the 32-bit EBX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+ @param Ecx The pointer to the 32-bit ECX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+ @param Edx The pointer to the 32-bit EDX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+
+ @return Index.
+
+**/
+UINT32
+EFIAPI
+UnitTestHostBaseLibAsmCpuidEx (
+ IN UINT32 Index,
+ IN UINT32 SubIndex,
+ OUT UINT32 *Eax OPTIONAL,
+ OUT UINT32 *Ebx OPTIONAL,
+ OUT UINT32 *Ecx OPTIONAL,
+ OUT UINT32 *Edx OPTIONAL
+ )
+{
+ if (Eax != NULL) {
+ *Eax = 0;
+ }
+
+ if (Ebx != NULL) {
+ *Ebx = 0;
+ }
+
+ if (Ecx != NULL) {
+ *Ecx = 0;
+ }
+
+ if (Edx != NULL) {
+ *Edx = 0;
+ }
+
+ return Index;
+}
+
+/**
+ Set CD bit and clear NW bit of CR0 followed by a WBINVD.
+
+ Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0,
+ and executing a WBINVD instruction. This function is only available on IA-32 and x64.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmDisableCache (
+ VOID
+ )
+{
+}
+
+/**
+ Perform a WBINVD and clear both the CD and NW bits of CR0.
+
+ Enables the caches by executing a WBINVD instruction and then clear both the CD and NW
+ bits of CR0 to 0. This function is only available on IA-32 and x64.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmEnableCache (
+ VOID
+ )
+{
+}
+
+/**
+ Returns a 64-bit Machine Specific Register(MSR).
+
+ Reads and returns the 64-bit MSR specified by Index. No parameter checking is
+ performed on Index, and some Index values may cause CPU exceptions. The
+ caller must either guarantee that Index is valid, or the caller must set up
+ exception handlers to catch the exceptions. This function is only available
+ on IA-32 and x64.
+
+ @param Index The 32-bit MSR index to read.
+
+ @return The value of the MSR identified by Index.
+
+**/
+UINT64
+EFIAPI
+UnitTestHostBaseLibAsmReadMsr64 (
+ IN UINT32 Index
+ )
+{
+ if (Index < 0x1000) {
+ return mUnitTestHostBaseLibMsr[0][Index];
+ }
+
+ if ((Index >= 0xC0000000) && (Index < 0xC0001000)) {
+ return mUnitTestHostBaseLibMsr[1][Index];
+ }
+
+ return 0;
+}
+
+/**
+ Writes a 64-bit value to a Machine Specific Register(MSR), and returns the
+ value.
+
+ Writes the 64-bit value specified by Value to the MSR specified by Index. The
+ 64-bit value written to the MSR is returned. No parameter checking is
+ performed on Index or Value, and some of these may cause CPU exceptions. The
+ caller must either guarantee that Index and Value are valid, or the caller
+ must establish proper exception handlers. This function is only available on
+ IA-32 and x64.
+
+ @param Index The 32-bit MSR index to write.
+ @param Value The 64-bit value to write to the MSR.
+
+ @return Value
+
+**/
+UINT64
+EFIAPI
+UnitTestHostBaseLibAsmWriteMsr64 (
+ IN UINT32 Index,
+ IN UINT64 Value
+ )
+{
+ if (Index < 0x1000) {
+ mUnitTestHostBaseLibMsr[0][Index] = Value;
+ }
+
+ if ((Index >= 0xC0000000) && (Index < 0xC0001000)) {
+ mUnitTestHostBaseLibMsr[1][Index - 0xC00000000] = Value;
+ }
+
+ return Value;
+}
+
+/**
+ Reads the current value of the Control Register 0 (CR0).
+
+ Reads and returns the current value of CR0. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 0 (CR0).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadCr0 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibCr[0];
+}
+
+/**
+ Reads the current value of the Control Register 2 (CR2).
+
+ Reads and returns the current value of CR2. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 2 (CR2).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadCr2 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibCr[2];
+}
+
+/**
+ Reads the current value of the Control Register 3 (CR3).
+
+ Reads and returns the current value of CR3. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 3 (CR3).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadCr3 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibCr[3];
+}
+
+/**
+ Reads the current value of the Control Register 4 (CR4).
+
+ Reads and returns the current value of CR4. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 4 (CR4).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadCr4 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibCr[4];
+}
+
+/**
+ Writes a value to Control Register 0 (CR0).
+
+ Writes and returns a new value to CR0. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Cr0 The value to write to CR0.
+
+ @return The value written to CR0.
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteCr0 (
+ UINTN Cr0
+ )
+{
+ mUnitTestHostBaseLibCr[0] = Cr0;
+ return Cr0;
+}
+
+/**
+ Writes a value to Control Register 2 (CR2).
+
+ Writes and returns a new value to CR2. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Cr2 The value to write to CR2.
+
+ @return The value written to CR2.
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteCr2 (
+ UINTN Cr2
+ )
+{
+ mUnitTestHostBaseLibCr[2] = Cr2;
+ return Cr2;
+}
+
+/**
+ Writes a value to Control Register 3 (CR3).
+
+ Writes and returns a new value to CR3. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Cr3 The value to write to CR3.
+
+ @return The value written to CR3.
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteCr3 (
+ UINTN Cr3
+ )
+{
+ mUnitTestHostBaseLibCr[3] = Cr3;
+ return Cr3;
+}
+
+/**
+ Writes a value to Control Register 4 (CR4).
+
+ Writes and returns a new value to CR4. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Cr4 The value to write to CR4.
+
+ @return The value written to CR4.
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteCr4 (
+ UINTN Cr4
+ )
+{
+ mUnitTestHostBaseLibCr[4] = Cr4;
+ return Cr4;
+}
+
+/**
+ Reads the current value of Debug Register 0 (DR0).
+
+ Reads and returns the current value of DR0. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 0 (DR0).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadDr0 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibDr[0];
+}
+
+/**
+ Reads the current value of Debug Register 1 (DR1).
+
+ Reads and returns the current value of DR1. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 1 (DR1).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadDr1 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibDr[1];
+}
+
+/**
+ Reads the current value of Debug Register 2 (DR2).
+
+ Reads and returns the current value of DR2. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 2 (DR2).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadDr2 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibDr[2];
+}
+
+/**
+ Reads the current value of Debug Register 3 (DR3).
+
+ Reads and returns the current value of DR3. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 3 (DR3).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadDr3 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibDr[3];
+}
+
+/**
+ Reads the current value of Debug Register 4 (DR4).
+
+ Reads and returns the current value of DR4. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 4 (DR4).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadDr4 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibDr[4];
+}
+
+/**
+ Reads the current value of Debug Register 5 (DR5).
+
+ Reads and returns the current value of DR5. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 5 (DR5).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadDr5 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibDr[5];
+}
+
+/**
+ Reads the current value of Debug Register 6 (DR6).
+
+ Reads and returns the current value of DR6. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 6 (DR6).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadDr6 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibDr[6];
+}
+
+/**
+ Reads the current value of Debug Register 7 (DR7).
+
+ Reads and returns the current value of DR7. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 7 (DR7).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmReadDr7 (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibDr[7];
+}
+
+/**
+ Writes a value to Debug Register 0 (DR0).
+
+ Writes and returns a new value to DR0. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr0 The value to write to Dr0.
+
+ @return The value written to Debug Register 0 (DR0).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteDr0 (
+ UINTN Dr0
+ )
+{
+ mUnitTestHostBaseLibDr[0] = Dr0;
+ return Dr0;
+}
+
+/**
+ Writes a value to Debug Register 1 (DR1).
+
+ Writes and returns a new value to DR1. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr1 The value to write to Dr1.
+
+ @return The value written to Debug Register 1 (DR1).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteDr1 (
+ UINTN Dr1
+ )
+{
+ mUnitTestHostBaseLibDr[1] = Dr1;
+ return Dr1;
+}
+
+/**
+ Writes a value to Debug Register 2 (DR2).
+
+ Writes and returns a new value to DR2. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr2 The value to write to Dr2.
+
+ @return The value written to Debug Register 2 (DR2).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteDr2 (
+ UINTN Dr2
+ )
+{
+ mUnitTestHostBaseLibDr[2] = Dr2;
+ return Dr2;
+}
+
+/**
+ Writes a value to Debug Register 3 (DR3).
+
+ Writes and returns a new value to DR3. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr3 The value to write to Dr3.
+
+ @return The value written to Debug Register 3 (DR3).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteDr3 (
+ UINTN Dr3
+ )
+{
+ mUnitTestHostBaseLibDr[3] = Dr3;
+ return Dr3;
+}
+
+/**
+ Writes a value to Debug Register 4 (DR4).
+
+ Writes and returns a new value to DR4. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr4 The value to write to Dr4.
+
+ @return The value written to Debug Register 4 (DR4).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteDr4 (
+ UINTN Dr4
+ )
+{
+ mUnitTestHostBaseLibDr[4] = Dr4;
+ return Dr4;
+}
+
+/**
+ Writes a value to Debug Register 5 (DR5).
+
+ Writes and returns a new value to DR5. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr5 The value to write to Dr5.
+
+ @return The value written to Debug Register 5 (DR5).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteDr5 (
+ UINTN Dr5
+ )
+{
+ mUnitTestHostBaseLibDr[5] = Dr5;
+ return Dr5;
+}
+
+/**
+ Writes a value to Debug Register 6 (DR6).
+
+ Writes and returns a new value to DR6. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr6 The value to write to Dr6.
+
+ @return The value written to Debug Register 6 (DR6).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteDr6 (
+ UINTN Dr6
+ )
+{
+ mUnitTestHostBaseLibDr[6] = Dr6;
+ return Dr6;
+}
+
+/**
+ Writes a value to Debug Register 7 (DR7).
+
+ Writes and returns a new value to DR7. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr7 The value to write to Dr7.
+
+ @return The value written to Debug Register 7 (DR7).
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmWriteDr7 (
+ UINTN Dr7
+ )
+{
+ mUnitTestHostBaseLibDr[7] = Dr7;
+ return Dr7;
+}
+
+/**
+ Reads the current value of Code Segment Register (CS).
+
+ Reads and returns the current value of CS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of CS.
+
+**/
+UINT16
+EFIAPI
+UnitTestHostBaseLibAsmReadCs (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS];
+}
+
+/**
+ Reads the current value of Data Segment Register (DS).
+
+ Reads and returns the current value of DS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of DS.
+
+**/
+UINT16
+EFIAPI
+UnitTestHostBaseLibAsmReadDs (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS];
+}
+
+/**
+ Reads the current value of Extra Segment Register (ES).
+
+ Reads and returns the current value of ES. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of ES.
+
+**/
+UINT16
+EFIAPI
+UnitTestHostBaseLibAsmReadEs (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES];
+}
+
+/**
+ Reads the current value of FS Data Segment Register (FS).
+
+ Reads and returns the current value of FS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of FS.
+
+**/
+UINT16
+EFIAPI
+UnitTestHostBaseLibAsmReadFs (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS];
+}
+
+/**
+ Reads the current value of GS Data Segment Register (GS).
+
+ Reads and returns the current value of GS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of GS.
+
+**/
+UINT16
+EFIAPI
+UnitTestHostBaseLibAsmReadGs (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS];
+}
+
+/**
+ Reads the current value of Stack Segment Register (SS).
+
+ Reads and returns the current value of SS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of SS.
+
+**/
+UINT16
+EFIAPI
+UnitTestHostBaseLibAsmReadSs (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS];
+}
+
+/**
+ Reads the current value of Task Register (TR).
+
+ Reads and returns the current value of TR. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of TR.
+
+**/
+UINT16
+EFIAPI
+UnitTestHostBaseLibAsmReadTr (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR];
+}
+
+/**
+ Reads the current Global Descriptor Table Register(GDTR) descriptor.
+
+ Reads and returns the current GDTR descriptor and returns it in Gdtr. This
+ function is only available on IA-32 and x64.
+
+ If Gdtr is NULL, then ASSERT().
+
+ @param Gdtr The pointer to a GDTR descriptor.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmReadGdtr (
+ OUT IA32_DESCRIPTOR *Gdtr
+ )
+{
+ Gdtr = &mUnitTestHostBaseLibGdtr;
+}
+
+/**
+ Writes the current Global Descriptor Table Register (GDTR) descriptor.
+
+ Writes and the current GDTR descriptor specified by Gdtr. This function is
+ only available on IA-32 and x64.
+
+ If Gdtr is NULL, then ASSERT().
+
+ @param Gdtr The pointer to a GDTR descriptor.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmWriteGdtr (
+ IN CONST IA32_DESCRIPTOR *Gdtr
+ )
+{
+ CopyMem (&mUnitTestHostBaseLibGdtr, Gdtr, sizeof (IA32_DESCRIPTOR));
+}
+
+/**
+ Reads the current Interrupt Descriptor Table Register(IDTR) descriptor.
+
+ Reads and returns the current IDTR descriptor and returns it in Idtr. This
+ function is only available on IA-32 and x64.
+
+ If Idtr is NULL, then ASSERT().
+
+ @param Idtr The pointer to a IDTR descriptor.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmReadIdtr (
+ OUT IA32_DESCRIPTOR *Idtr
+ )
+{
+ Idtr = &mUnitTestHostBaseLibIdtr;
+}
+
+/**
+ Writes the current Interrupt Descriptor Table Register(IDTR) descriptor.
+
+ Writes the current IDTR descriptor and returns it in Idtr. This function is
+ only available on IA-32 and x64.
+
+ If Idtr is NULL, then ASSERT().
+
+ @param Idtr The pointer to a IDTR descriptor.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmWriteIdtr (
+ IN CONST IA32_DESCRIPTOR *Idtr
+ )
+{
+ CopyMem (&mUnitTestHostBaseLibIdtr, Idtr, sizeof (IA32_DESCRIPTOR));
+}
+
+/**
+ Reads the current Local Descriptor Table Register(LDTR) selector.
+
+ Reads and returns the current 16-bit LDTR descriptor value. This function is
+ only available on IA-32 and x64.
+
+ @return The current selector of LDT.
+
+**/
+UINT16
+EFIAPI
+UnitTestHostBaseLibAsmReadLdtr (
+ VOID
+ )
+{
+ return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR];
+}
+
+/**
+ Writes the current Local Descriptor Table Register (LDTR) selector.
+
+ Writes and the current LDTR descriptor specified by Ldtr. This function is
+ only available on IA-32 and x64.
+
+ @param Ldtr 16-bit LDTR selector value.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmWriteLdtr (
+ IN UINT16 Ldtr
+ )
+{
+ mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR] = Ldtr;
+}
+
+/**
+ Reads the current value of a Performance Counter (PMC).
+
+ Reads and returns the current value of performance counter specified by
+ Index. This function is only available on IA-32 and x64.
+
+ @param Index The 32-bit Performance Counter index to read.
+
+ @return The value of the PMC specified by Index.
+
+**/
+UINT64
+EFIAPI
+UnitTestHostBaseLibAsmReadPmc (
+ IN UINT32 Index
+ )
+{
+ return 0;
+}
+
+/**
+ Sets up a monitor buffer that is used by AsmMwait().
+
+ Executes a MONITOR instruction with the register state specified by Eax, Ecx
+ and Edx. Returns Eax. This function is only available on IA-32 and x64.
+
+ @param Eax The value to load into EAX or RAX before executing the MONITOR
+ instruction.
+ @param Ecx The value to load into ECX or RCX before executing the MONITOR
+ instruction.
+ @param Edx The value to load into EDX or RDX before executing the MONITOR
+ instruction.
+
+ @return Eax
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmMonitor (
+ IN UINTN Eax,
+ IN UINTN Ecx,
+ IN UINTN Edx
+ )
+{
+ return Eax;
+}
+
+/**
+ Executes an MWAIT instruction.
+
+ Executes an MWAIT instruction with the register state specified by Eax and
+ Ecx. Returns Eax. This function is only available on IA-32 and x64.
+
+ @param Eax The value to load into EAX or RAX before executing the MONITOR
+ instruction.
+ @param Ecx The value to load into ECX or RCX before executing the MONITOR
+ instruction.
+
+ @return Eax
+
+**/
+UINTN
+EFIAPI
+UnitTestHostBaseLibAsmMwait (
+ IN UINTN Eax,
+ IN UINTN Ecx
+ )
+{
+ return Eax;
+}
+
+/**
+ Executes a WBINVD instruction.
+
+ Executes a WBINVD instruction. This function is only available on IA-32 and
+ x64.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmWbinvd (
+ VOID
+ )
+{
+}
+
+/**
+ Executes a INVD instruction.
+
+ Executes a INVD instruction. This function is only available on IA-32 and
+ x64.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmInvd (
+ VOID
+ )
+{
+}
+
+/**
+ Flushes a cache line from all the instruction and data caches within the
+ coherency domain of the CPU.
+
+ Flushed the cache line specified by LinearAddress, and returns LinearAddress.
+ This function is only available on IA-32 and x64.
+
+ @param LinearAddress The address of the cache line to flush. If the CPU is
+ in a physical addressing mode, then LinearAddress is a
+ physical address. If the CPU is in a virtual
+ addressing mode, then LinearAddress is a virtual
+ address.
+
+ @return LinearAddress.
+**/
+VOID *
+EFIAPI
+UnitTestHostBaseLibAsmFlushCacheLine (
+ IN VOID *LinearAddress
+ )
+{
+ return LinearAddress;
+}
+
+/**
+ Enables the 32-bit paging mode on the CPU.
+
+ Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
+ must be properly initialized prior to calling this service. This function
+ assumes the current execution mode is 32-bit protected mode. This function is
+ only available on IA-32. After the 32-bit paging mode is enabled, control is
+ transferred to the function specified by EntryPoint using the new stack
+ specified by NewStack and passing in the parameters specified by Context1 and
+ Context2. Context1 and Context2 are optional and may be NULL. The function
+ EntryPoint must never return.
+
+ If the current execution mode is not 32-bit protected mode, then ASSERT().
+ If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+
+ There are a number of constraints that must be followed before calling this
+ function:
+ 1) Interrupts must be disabled.
+ 2) The caller must be in 32-bit protected mode with flat descriptors. This
+ means all descriptors must have a base of 0 and a limit of 4GB.
+ 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat
+ descriptors.
+ 4) CR3 must point to valid page tables that will be used once the transition
+ is complete, and those page tables must guarantee that the pages for this
+ function and the stack are identity mapped.
+
+ @param EntryPoint A pointer to function to call with the new stack after
+ paging is enabled.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function as the first parameter after paging is enabled.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function as the second parameter after paging is enabled.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function after paging is enabled.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmEnablePaging32 (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL,
+ IN VOID *NewStack
+ )
+{
+ EntryPoint (Context1, Context2);
+}
+
+/**
+ Disables the 32-bit paging mode on the CPU.
+
+ Disables the 32-bit paging mode on the CPU and returns to 32-bit protected
+ mode. This function assumes the current execution mode is 32-paged protected
+ mode. This function is only available on IA-32. After the 32-bit paging mode
+ is disabled, control is transferred to the function specified by EntryPoint
+ using the new stack specified by NewStack and passing in the parameters
+ specified by Context1 and Context2. Context1 and Context2 are optional and
+ may be NULL. The function EntryPoint must never return.
+
+ If the current execution mode is not 32-bit paged mode, then ASSERT().
+ If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+
+ There are a number of constraints that must be followed before calling this
+ function:
+ 1) Interrupts must be disabled.
+ 2) The caller must be in 32-bit paged mode.
+ 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.
+ 4) CR3 must point to valid page tables that guarantee that the pages for
+ this function and the stack are identity mapped.
+
+ @param EntryPoint A pointer to function to call with the new stack after
+ paging is disabled.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function as the first parameter after paging is disabled.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function as the second parameter after paging is
+ disabled.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function after paging is disabled.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmDisablePaging32 (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL,
+ IN VOID *NewStack
+ )
+{
+ EntryPoint (Context1, Context2);
+}
+
+/**
+ Enables the 64-bit paging mode on the CPU.
+
+ Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
+ must be properly initialized prior to calling this service. This function
+ assumes the current execution mode is 32-bit protected mode with flat
+ descriptors. This function is only available on IA-32. After the 64-bit
+ paging mode is enabled, control is transferred to the function specified by
+ EntryPoint using the new stack specified by NewStack and passing in the
+ parameters specified by Context1 and Context2. Context1 and Context2 are
+ optional and may be 0. The function EntryPoint must never return.
+
+ If the current execution mode is not 32-bit protected mode with flat
+ descriptors, then ASSERT().
+ If EntryPoint is 0, then ASSERT().
+ If NewStack is 0, then ASSERT().
+
+ @param Cs The 16-bit selector to load in the CS before EntryPoint
+ is called. The descriptor in the GDT that this selector
+ references must be setup for long mode.
+ @param EntryPoint The 64-bit virtual address of the function to call with
+ the new stack after paging is enabled.
+ @param Context1 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the first parameter after
+ paging is enabled.
+ @param Context2 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the second parameter after
+ paging is enabled.
+ @param NewStack The 64-bit virtual address of the new stack to use for
+ the EntryPoint function after paging is enabled.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmEnablePaging64 (
+ IN UINT16 Cs,
+ IN UINT64 EntryPoint,
+ IN UINT64 Context1 OPTIONAL,
+ IN UINT64 Context2 OPTIONAL,
+ IN UINT64 NewStack
+ )
+{
+ SWITCH_STACK_ENTRY_POINT NewEntryPoint;
+
+ NewEntryPoint = (SWITCH_STACK_ENTRY_POINT)(UINTN)(EntryPoint);
+ NewEntryPoint ((VOID *)(UINTN)Context1, (VOID *)(UINTN)Context2);
+}
+
+/**
+ Disables the 64-bit paging mode on the CPU.
+
+ Disables the 64-bit paging mode on the CPU and returns to 32-bit protected
+ mode. This function assumes the current execution mode is 64-paging mode.
+ This function is only available on x64. After the 64-bit paging mode is
+ disabled, control is transferred to the function specified by EntryPoint
+ using the new stack specified by NewStack and passing in the parameters
+ specified by Context1 and Context2. Context1 and Context2 are optional and
+ may be 0. The function EntryPoint must never return.
+
+ If the current execution mode is not 64-bit paged mode, then ASSERT().
+ If EntryPoint is 0, then ASSERT().
+ If NewStack is 0, then ASSERT().
+
+ @param Cs The 16-bit selector to load in the CS before EntryPoint
+ is called. The descriptor in the GDT that this selector
+ references must be setup for 32-bit protected mode.
+ @param EntryPoint The 64-bit virtual address of the function to call with
+ the new stack after paging is disabled.
+ @param Context1 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the first parameter after
+ paging is disabled.
+ @param Context2 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the second parameter after
+ paging is disabled.
+ @param NewStack The 64-bit virtual address of the new stack to use for
+ the EntryPoint function after paging is disabled.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmDisablePaging64 (
+ IN UINT16 Cs,
+ IN UINT32 EntryPoint,
+ IN UINT32 Context1 OPTIONAL,
+ IN UINT32 Context2 OPTIONAL,
+ IN UINT32 NewStack
+ )
+{
+ SWITCH_STACK_ENTRY_POINT NewEntryPoint;
+
+ NewEntryPoint = (SWITCH_STACK_ENTRY_POINT)(UINTN)(EntryPoint);
+ NewEntryPoint ((VOID *)(UINTN)Context1, (VOID *)(UINTN)Context2);
+}
+
+/**
+ Retrieves the properties for 16-bit thunk functions.
+
+ Computes the size of the buffer and stack below 1MB required to use the
+ AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This
+ buffer size is returned in RealModeBufferSize, and the stack size is returned
+ in ExtraStackSize. If parameters are passed to the 16-bit real mode code,
+ then the actual minimum stack size is ExtraStackSize plus the maximum number
+ of bytes that need to be passed to the 16-bit real mode code.
+
+ If RealModeBufferSize is NULL, then ASSERT().
+ If ExtraStackSize is NULL, then ASSERT().
+
+ @param RealModeBufferSize A pointer to the size of the buffer below 1MB
+ required to use the 16-bit thunk functions.
+ @param ExtraStackSize A pointer to the extra size of stack below 1MB
+ that the 16-bit thunk functions require for
+ temporary storage in the transition to and from
+ 16-bit real mode.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmGetThunk16Properties (
+ OUT UINT32 *RealModeBufferSize,
+ OUT UINT32 *ExtraStackSize
+ )
+{
+ *RealModeBufferSize = 0;
+ *ExtraStackSize = 0;
+}
+
+/**
+ Prepares all structures a code required to use AsmThunk16().
+
+ Prepares all structures and code required to use AsmThunk16().
+
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
+ virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.
+
+ If ThunkContext is NULL, then ASSERT().
+
+ @param ThunkContext A pointer to the context structure that describes the
+ 16-bit real mode code to call.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmPrepareThunk16 (
+ IN OUT THUNK_CONTEXT *ThunkContext
+ )
+{
+}
+
+/**
+ Transfers control to a 16-bit real mode entry point and returns the results.
+
+ Transfers control to a 16-bit real mode entry point and returns the results.
+ AsmPrepareThunk16() must be called with ThunkContext before this function is used.
+ This function must be called with interrupts disabled.
+
+ The register state from the RealModeState field of ThunkContext is restored just prior
+ to calling the 16-bit real mode entry point. This includes the EFLAGS field of RealModeState,
+ which is used to set the interrupt state when a 16-bit real mode entry point is called.
+ Control is transferred to the 16-bit real mode entry point specified by the CS and Eip fields of RealModeState.
+ The stack is initialized to the SS and ESP fields of RealModeState. Any parameters passed to
+ the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function.
+ The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instruction,
+ so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment
+ and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry
+ point must exit with a RETF instruction. The register state is captured into RealModeState immediately
+ after the RETF instruction is executed.
+
+ If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,
+ or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure
+ the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode.
+
+ If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,
+ then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode.
+ This includes the base vectors, the interrupt masks, and the edge/level trigger mode.
+
+ If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code
+ is invoked in big real mode. Otherwise, the user code is invoked in 16-bit real mode with 64KB segment limits.
+
+ If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in
+ ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to
+ disable the A20 mask.
+
+ If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in
+ ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask. If this INT 15 call fails,
+ then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.
+
+ If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in
+ ThunkAttributes, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.
+
+ If ThunkContext is NULL, then ASSERT().
+ If AsmPrepareThunk16() was not previously called with ThunkContext, then ASSERT().
+ If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in
+ ThunkAttributes, then ASSERT().
+
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
+ virtual to physical mappings for ThunkContext.RealModeBuffer are mapped 1:1.
+
+ @param ThunkContext A pointer to the context structure that describes the
+ 16-bit real mode code to call.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmThunk16 (
+ IN OUT THUNK_CONTEXT *ThunkContext
+ )
+{
+}
+
+/**
+ Prepares all structures and code for a 16-bit real mode thunk, transfers
+ control to a 16-bit real mode entry point, and returns the results.
+
+ Prepares all structures and code for a 16-bit real mode thunk, transfers
+ control to a 16-bit real mode entry point, and returns the results. If the
+ caller only need to perform a single 16-bit real mode thunk, then this
+ service should be used. If the caller intends to make more than one 16-bit
+ real mode thunk, then it is more efficient if AsmPrepareThunk16() is called
+ once and AsmThunk16() can be called for each 16-bit real mode thunk.
+
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
+ virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.
+
+ See AsmPrepareThunk16() and AsmThunk16() for the detailed description and ASSERT() conditions.
+
+ @param ThunkContext A pointer to the context structure that describes the
+ 16-bit real mode code to call.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmPrepareAndThunk16 (
+ IN OUT THUNK_CONTEXT *ThunkContext
+ )
+{
+}
+
+/**
+ Load given selector into TR register.
+
+ @param[in] Selector Task segment selector
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmWriteTr (
+ IN UINT16 Selector
+ )
+{
+ mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR] = Selector;
+}
+
+/**
+ Performs a serializing operation on all load-from-memory instructions that
+ were issued prior the AsmLfence function.
+
+ Executes a LFENCE instruction. This function is only available on IA-32 and x64.
+
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibAsmLfence (
+ VOID
+ )
+{
+}
+
+/**
+ Patch the immediate operand of an IA32 or X64 instruction such that the byte,
+ word, dword or qword operand is encoded at the end of the instruction's
+ binary representation.
+
+ This function should be used to update object code that was compiled with
+ NASM from assembly source code. Example:
+
+ NASM source code:
+
+ mov eax, strict dword 0 ; the imm32 zero operand will be patched
+ ASM_PFX(gPatchCr3):
+ mov cr3, eax
+
+ C source code:
+
+ X86_ASSEMBLY_PATCH_LABEL gPatchCr3;
+ PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);
+
+ @param[out] InstructionEnd Pointer right past the instruction to patch. The
+ immediate operand to patch is expected to
+ comprise the trailing bytes of the instruction.
+ If InstructionEnd is closer to address 0 than
+ ValueSize permits, then ASSERT().
+
+ @param[in] PatchValue The constant to write to the immediate operand.
+ The caller is responsible for ensuring that
+ PatchValue can be represented in the byte, word,
+ dword or qword operand (as indicated through
+ ValueSize); otherwise ASSERT().
+
+ @param[in] ValueSize The size of the operand in bytes; must be 1, 2,
+ 4, or 8. ASSERT() otherwise.
+**/
+VOID
+EFIAPI
+UnitTestHostBaseLibPatchInstructionX86 (
+ OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
+ IN UINT64 PatchValue,
+ IN UINTN ValueSize
+ )
+{
+}
+
+/**
+ Retrieves CPUID information.
+
+ Executes the CPUID instruction with EAX set to the value specified by Index.
+ This function always returns Index.
+ If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
+ If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
+ If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
+ If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
+ This function is only available on IA-32 and x64.
+
+ @param Index The 32-bit value to load into EAX prior to invoking the CPUID
+ instruction.
+ @param Eax The pointer to the 32-bit EAX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+ @param Ebx The pointer to the 32-bit EBX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+ @param Ecx The pointer to the 32-bit ECX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+ @param Edx The pointer to the 32-bit EDX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+
+ @return Index.
+
+**/
+UINT32
+EFIAPI
+AsmCpuid (
+ IN UINT32 Index,
+ OUT UINT32 *Eax OPTIONAL,
+ OUT UINT32 *Ebx OPTIONAL,
+ OUT UINT32 *Ecx OPTIONAL,
+ OUT UINT32 *Edx OPTIONAL
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmCpuid (Index, Eax, Ebx, Ecx, Edx);
+}
+
+/**
+ Retrieves CPUID information using an extended leaf identifier.
+
+ Executes the CPUID instruction with EAX set to the value specified by Index
+ and ECX set to the value specified by SubIndex. This function always returns
+ Index. This function is only available on IA-32 and x64.
+
+ If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
+ If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
+ If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
+ If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
+
+ @param Index The 32-bit value to load into EAX prior to invoking the
+ CPUID instruction.
+ @param SubIndex The 32-bit value to load into ECX prior to invoking the
+ CPUID instruction.
+ @param Eax The pointer to the 32-bit EAX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+ @param Ebx The pointer to the 32-bit EBX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+ @param Ecx The pointer to the 32-bit ECX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+ @param Edx The pointer to the 32-bit EDX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+
+ @return Index.
+
+**/
+UINT32
+EFIAPI
+AsmCpuidEx (
+ IN UINT32 Index,
+ IN UINT32 SubIndex,
+ OUT UINT32 *Eax OPTIONAL,
+ OUT UINT32 *Ebx OPTIONAL,
+ OUT UINT32 *Ecx OPTIONAL,
+ OUT UINT32 *Edx OPTIONAL
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmCpuidEx (Index, SubIndex, Eax, Ebx, Ecx, Edx);
+}
+
+/**
+ Set CD bit and clear NW bit of CR0 followed by a WBINVD.
+
+ Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0,
+ and executing a WBINVD instruction. This function is only available on IA-32 and x64.
+
+**/
+VOID
+EFIAPI
+AsmDisableCache (
+ VOID
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmDisableCache ();
+}
+
+/**
+ Perform a WBINVD and clear both the CD and NW bits of CR0.
+
+ Enables the caches by executing a WBINVD instruction and then clear both the CD and NW
+ bits of CR0 to 0. This function is only available on IA-32 and x64.
+
+**/
+VOID
+EFIAPI
+AsmEnableCache (
+ VOID
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmEnableCache ();
+}
+
+/**
+ Returns a 64-bit Machine Specific Register(MSR).
+
+ Reads and returns the 64-bit MSR specified by Index. No parameter checking is
+ performed on Index, and some Index values may cause CPU exceptions. The
+ caller must either guarantee that Index is valid, or the caller must set up
+ exception handlers to catch the exceptions. This function is only available
+ on IA-32 and x64.
+
+ @param Index The 32-bit MSR index to read.
+
+ @return The value of the MSR identified by Index.
+
+**/
+UINT64
+EFIAPI
+AsmReadMsr64 (
+ IN UINT32 Index
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadMsr64 (Index);
+}
+
+/**
+ Writes a 64-bit value to a Machine Specific Register(MSR), and returns the
+ value.
+
+ Writes the 64-bit value specified by Value to the MSR specified by Index. The
+ 64-bit value written to the MSR is returned. No parameter checking is
+ performed on Index or Value, and some of these may cause CPU exceptions. The
+ caller must either guarantee that Index and Value are valid, or the caller
+ must establish proper exception handlers. This function is only available on
+ IA-32 and x64.
+
+ @param Index The 32-bit MSR index to write.
+ @param Value The 64-bit value to write to the MSR.
+
+ @return Value
+
+**/
+UINT64
+EFIAPI
+AsmWriteMsr64 (
+ IN UINT32 Index,
+ IN UINT64 Value
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteMsr64 (Index, Value);
+}
+
+/**
+ Reads the current value of the Control Register 0 (CR0).
+
+ Reads and returns the current value of CR0. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 0 (CR0).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr0 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadCr0 ();
+}
+
+/**
+ Reads the current value of the Control Register 2 (CR2).
+
+ Reads and returns the current value of CR2. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 2 (CR2).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr2 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadCr2 ();
+}
+
+/**
+ Reads the current value of the Control Register 3 (CR3).
+
+ Reads and returns the current value of CR3. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 3 (CR3).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr3 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadCr3 ();
+}
+
+/**
+ Reads the current value of the Control Register 4 (CR4).
+
+ Reads and returns the current value of CR4. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 4 (CR4).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr4 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadCr4 ();
+}
+
+/**
+ Writes a value to Control Register 0 (CR0).
+
+ Writes and returns a new value to CR0. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Cr0 The value to write to CR0.
+
+ @return The value written to CR0.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr0 (
+ UINTN Cr0
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteCr0 (Cr0);
+}
+
+/**
+ Writes a value to Control Register 2 (CR2).
+
+ Writes and returns a new value to CR2. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Cr2 The value to write to CR2.
+
+ @return The value written to CR2.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr2 (
+ UINTN Cr2
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteCr2 (Cr2);
+}
+
+/**
+ Writes a value to Control Register 3 (CR3).
+
+ Writes and returns a new value to CR3. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Cr3 The value to write to CR3.
+
+ @return The value written to CR3.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr3 (
+ UINTN Cr3
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteCr3 (Cr3);
+}
+
+/**
+ Writes a value to Control Register 4 (CR4).
+
+ Writes and returns a new value to CR4. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Cr4 The value to write to CR4.
+
+ @return The value written to CR4.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr4 (
+ UINTN Cr4
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteCr4 (Cr4);
+}
+
+/**
+ Reads the current value of Debug Register 0 (DR0).
+
+ Reads and returns the current value of DR0. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 0 (DR0).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr0 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadDr0 ();
+}
+
+/**
+ Reads the current value of Debug Register 1 (DR1).
+
+ Reads and returns the current value of DR1. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 1 (DR1).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr1 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadDr1 ();
+}
+
+/**
+ Reads the current value of Debug Register 2 (DR2).
+
+ Reads and returns the current value of DR2. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 2 (DR2).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr2 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadDr2 ();
+}
+
+/**
+ Reads the current value of Debug Register 3 (DR3).
+
+ Reads and returns the current value of DR3. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 3 (DR3).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr3 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadDr3 ();
+}
+
+/**
+ Reads the current value of Debug Register 4 (DR4).
+
+ Reads and returns the current value of DR4. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 4 (DR4).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr4 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadDr4 ();
+}
+
+/**
+ Reads the current value of Debug Register 5 (DR5).
+
+ Reads and returns the current value of DR5. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 5 (DR5).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr5 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadDr5 ();
+}
+
+/**
+ Reads the current value of Debug Register 6 (DR6).
+
+ Reads and returns the current value of DR6. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 6 (DR6).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr6 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadDr6 ();
+}
+
+/**
+ Reads the current value of Debug Register 7 (DR7).
+
+ Reads and returns the current value of DR7. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 7 (DR7).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr7 (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadDr7 ();
+}
+
+/**
+ Writes a value to Debug Register 0 (DR0).
+
+ Writes and returns a new value to DR0. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr0 The value to write to Dr0.
+
+ @return The value written to Debug Register 0 (DR0).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr0 (
+ UINTN Dr0
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteDr0 (Dr0);
+}
+
+/**
+ Writes a value to Debug Register 1 (DR1).
+
+ Writes and returns a new value to DR1. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr1 The value to write to Dr1.
+
+ @return The value written to Debug Register 1 (DR1).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr1 (
+ UINTN Dr1
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteDr1 (Dr1);
+}
+
+/**
+ Writes a value to Debug Register 2 (DR2).
+
+ Writes and returns a new value to DR2. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr2 The value to write to Dr2.
+
+ @return The value written to Debug Register 2 (DR2).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr2 (
+ UINTN Dr2
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteDr2 (Dr2);
+}
+
+/**
+ Writes a value to Debug Register 3 (DR3).
+
+ Writes and returns a new value to DR3. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr3 The value to write to Dr3.
+
+ @return The value written to Debug Register 3 (DR3).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr3 (
+ UINTN Dr3
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteDr3 (Dr3);
+}
+
+/**
+ Writes a value to Debug Register 4 (DR4).
+
+ Writes and returns a new value to DR4. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr4 The value to write to Dr4.
+
+ @return The value written to Debug Register 4 (DR4).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr4 (
+ UINTN Dr4
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteDr4 (Dr4);
+}
+
+/**
+ Writes a value to Debug Register 5 (DR5).
+
+ Writes and returns a new value to DR5. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr5 The value to write to Dr5.
+
+ @return The value written to Debug Register 5 (DR5).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr5 (
+ UINTN Dr5
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteDr5 (Dr5);
+}
+
+/**
+ Writes a value to Debug Register 6 (DR6).
+
+ Writes and returns a new value to DR6. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr6 The value to write to Dr6.
+
+ @return The value written to Debug Register 6 (DR6).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr6 (
+ UINTN Dr6
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteDr6 (Dr6);
+}
+
+/**
+ Writes a value to Debug Register 7 (DR7).
+
+ Writes and returns a new value to DR7. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr7 The value to write to Dr7.
+
+ @return The value written to Debug Register 7 (DR7).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr7 (
+ UINTN Dr7
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmWriteDr7 (Dr7);
+}
+
+/**
+ Reads the current value of Code Segment Register (CS).
+
+ Reads and returns the current value of CS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of CS.
+
+**/
+UINT16
+EFIAPI
+AsmReadCs (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadCs ();
+}
+
+/**
+ Reads the current value of Data Segment Register (DS).
+
+ Reads and returns the current value of DS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of DS.
+
+**/
+UINT16
+EFIAPI
+AsmReadDs (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadDs ();
+}
+
+/**
+ Reads the current value of Extra Segment Register (ES).
+
+ Reads and returns the current value of ES. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of ES.
+
+**/
+UINT16
+EFIAPI
+AsmReadEs (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadEs ();
+}
+
+/**
+ Reads the current value of FS Data Segment Register (FS).
+
+ Reads and returns the current value of FS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of FS.
+
+**/
+UINT16
+EFIAPI
+AsmReadFs (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadFs ();
+}
+
+/**
+ Reads the current value of GS Data Segment Register (GS).
+
+ Reads and returns the current value of GS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of GS.
+
+**/
+UINT16
+EFIAPI
+AsmReadGs (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadGs ();
+}
+
+/**
+ Reads the current value of Stack Segment Register (SS).
+
+ Reads and returns the current value of SS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of SS.
+
+**/
+UINT16
+EFIAPI
+AsmReadSs (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadSs ();
+}
+
+/**
+ Reads the current value of Task Register (TR).
+
+ Reads and returns the current value of TR. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of TR.
+
+**/
+UINT16
+EFIAPI
+AsmReadTr (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadTr ();
+}
+
+/**
+ Reads the current Global Descriptor Table Register(GDTR) descriptor.
+
+ Reads and returns the current GDTR descriptor and returns it in Gdtr. This
+ function is only available on IA-32 and x64.
+
+ If Gdtr is NULL, then ASSERT().
+
+ @param Gdtr The pointer to a GDTR descriptor.
+
+**/
+VOID
+EFIAPI
+AsmReadGdtr (
+ OUT IA32_DESCRIPTOR *Gdtr
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmReadGdtr (Gdtr);
+}
+
+/**
+ Writes the current Global Descriptor Table Register (GDTR) descriptor.
+
+ Writes and the current GDTR descriptor specified by Gdtr. This function is
+ only available on IA-32 and x64.
+
+ If Gdtr is NULL, then ASSERT().
+
+ @param Gdtr The pointer to a GDTR descriptor.
+
+**/
+VOID
+EFIAPI
+AsmWriteGdtr (
+ IN CONST IA32_DESCRIPTOR *Gdtr
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmWriteGdtr (Gdtr);
+}
+
+/**
+ Reads the current Interrupt Descriptor Table Register(IDTR) descriptor.
+
+ Reads and returns the current IDTR descriptor and returns it in Idtr. This
+ function is only available on IA-32 and x64.
+
+ If Idtr is NULL, then ASSERT().
+
+ @param Idtr The pointer to a IDTR descriptor.
+
+**/
+VOID
+EFIAPI
+AsmReadIdtr (
+ OUT IA32_DESCRIPTOR *Idtr
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmReadIdtr (Idtr);
+}
+
+/**
+ Writes the current Interrupt Descriptor Table Register(IDTR) descriptor.
+
+ Writes the current IDTR descriptor and returns it in Idtr. This function is
+ only available on IA-32 and x64.
+
+ If Idtr is NULL, then ASSERT().
+
+ @param Idtr The pointer to a IDTR descriptor.
+
+**/
+VOID
+EFIAPI
+AsmWriteIdtr (
+ IN CONST IA32_DESCRIPTOR *Idtr
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmWriteIdtr (Idtr);
+}
+
+/**
+ Reads the current Local Descriptor Table Register(LDTR) selector.
+
+ Reads and returns the current 16-bit LDTR descriptor value. This function is
+ only available on IA-32 and x64.
+
+ @return The current selector of LDT.
+
+**/
+UINT16
+EFIAPI
+AsmReadLdtr (
+ VOID
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadLdtr ();
+}
+
+/**
+ Writes the current Local Descriptor Table Register (LDTR) selector.
+
+ Writes and the current LDTR descriptor specified by Ldtr. This function is
+ only available on IA-32 and x64.
+
+ @param Ldtr 16-bit LDTR selector value.
+
+**/
+VOID
+EFIAPI
+AsmWriteLdtr (
+ IN UINT16 Ldtr
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmWriteLdtr (Ldtr);
+}
+
+/**
+ Reads the current value of a Performance Counter (PMC).
+
+ Reads and returns the current value of performance counter specified by
+ Index. This function is only available on IA-32 and x64.
+
+ @param Index The 32-bit Performance Counter index to read.
+
+ @return The value of the PMC specified by Index.
+
+**/
+UINT64
+EFIAPI
+AsmReadPmc (
+ IN UINT32 Index
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmReadPmc (Index);
+}
+
+/**
+ Sets up a monitor buffer that is used by AsmMwait().
+
+ Executes a MONITOR instruction with the register state specified by Eax, Ecx
+ and Edx. Returns Eax. This function is only available on IA-32 and x64.
+
+ @param Eax The value to load into EAX or RAX before executing the MONITOR
+ instruction.
+ @param Ecx The value to load into ECX or RCX before executing the MONITOR
+ instruction.
+ @param Edx The value to load into EDX or RDX before executing the MONITOR
+ instruction.
+
+ @return Eax
+
+**/
+UINTN
+EFIAPI
+AsmMonitor (
+ IN UINTN Eax,
+ IN UINTN Ecx,
+ IN UINTN Edx
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmMonitor (Eax, Ecx, Edx);
+}
+
+/**
+ Executes an MWAIT instruction.
+
+ Executes an MWAIT instruction with the register state specified by Eax and
+ Ecx. Returns Eax. This function is only available on IA-32 and x64.
+
+ @param Eax The value to load into EAX or RAX before executing the MONITOR
+ instruction.
+ @param Ecx The value to load into ECX or RCX before executing the MONITOR
+ instruction.
+
+ @return Eax
+
+**/
+UINTN
+EFIAPI
+AsmMwait (
+ IN UINTN Eax,
+ IN UINTN Ecx
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmMwait (Eax, Ecx);
+}
+
+/**
+ Executes a WBINVD instruction.
+
+ Executes a WBINVD instruction. This function is only available on IA-32 and
+ x64.
+
+**/
+VOID
+EFIAPI
+AsmWbinvd (
+ VOID
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmWbinvd ();
+}
+
+/**
+ Executes a INVD instruction.
+
+ Executes a INVD instruction. This function is only available on IA-32 and
+ x64.
+
+**/
+VOID
+EFIAPI
+AsmInvd (
+ VOID
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmInvd ();
+}
+
+/**
+ Flushes a cache line from all the instruction and data caches within the
+ coherency domain of the CPU.
+
+ Flushed the cache line specified by LinearAddress, and returns LinearAddress.
+ This function is only available on IA-32 and x64.
+
+ @param LinearAddress The address of the cache line to flush. If the CPU is
+ in a physical addressing mode, then LinearAddress is a
+ physical address. If the CPU is in a virtual
+ addressing mode, then LinearAddress is a virtual
+ address.
+
+ @return LinearAddress.
+**/
+VOID *
+EFIAPI
+AsmFlushCacheLine (
+ IN VOID *LinearAddress
+ )
+{
+ return gUnitTestHostBaseLib.X86->AsmFlushCacheLine (LinearAddress);
+}
+
+/**
+ Enables the 32-bit paging mode on the CPU.
+
+ Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
+ must be properly initialized prior to calling this service. This function
+ assumes the current execution mode is 32-bit protected mode. This function is
+ only available on IA-32. After the 32-bit paging mode is enabled, control is
+ transferred to the function specified by EntryPoint using the new stack
+ specified by NewStack and passing in the parameters specified by Context1 and
+ Context2. Context1 and Context2 are optional and may be NULL. The function
+ EntryPoint must never return.
+
+ If the current execution mode is not 32-bit protected mode, then ASSERT().
+ If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+
+ There are a number of constraints that must be followed before calling this
+ function:
+ 1) Interrupts must be disabled.
+ 2) The caller must be in 32-bit protected mode with flat descriptors. This
+ means all descriptors must have a base of 0 and a limit of 4GB.
+ 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat
+ descriptors.
+ 4) CR3 must point to valid page tables that will be used once the transition
+ is complete, and those page tables must guarantee that the pages for this
+ function and the stack are identity mapped.
+
+ @param EntryPoint A pointer to function to call with the new stack after
+ paging is enabled.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function as the first parameter after paging is enabled.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function as the second parameter after paging is enabled.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function after paging is enabled.
+
+**/
+VOID
+EFIAPI
+AsmEnablePaging32 (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL,
+ IN VOID *NewStack
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmEnablePaging32 (EntryPoint, Context1, Context2, NewStack);
+}
+
+/**
+ Disables the 32-bit paging mode on the CPU.
+
+ Disables the 32-bit paging mode on the CPU and returns to 32-bit protected
+ mode. This function assumes the current execution mode is 32-paged protected
+ mode. This function is only available on IA-32. After the 32-bit paging mode
+ is disabled, control is transferred to the function specified by EntryPoint
+ using the new stack specified by NewStack and passing in the parameters
+ specified by Context1 and Context2. Context1 and Context2 are optional and
+ may be NULL. The function EntryPoint must never return.
+
+ If the current execution mode is not 32-bit paged mode, then ASSERT().
+ If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+
+ There are a number of constraints that must be followed before calling this
+ function:
+ 1) Interrupts must be disabled.
+ 2) The caller must be in 32-bit paged mode.
+ 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.
+ 4) CR3 must point to valid page tables that guarantee that the pages for
+ this function and the stack are identity mapped.
+
+ @param EntryPoint A pointer to function to call with the new stack after
+ paging is disabled.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function as the first parameter after paging is disabled.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function as the second parameter after paging is
+ disabled.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function after paging is disabled.
+
+**/
+VOID
+EFIAPI
+AsmDisablePaging32 (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL,
+ IN VOID *NewStack
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmDisablePaging32 (EntryPoint, Context1, Context2, NewStack);
+}
+
+/**
+ Enables the 64-bit paging mode on the CPU.
+
+ Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
+ must be properly initialized prior to calling this service. This function
+ assumes the current execution mode is 32-bit protected mode with flat
+ descriptors. This function is only available on IA-32. After the 64-bit
+ paging mode is enabled, control is transferred to the function specified by
+ EntryPoint using the new stack specified by NewStack and passing in the
+ parameters specified by Context1 and Context2. Context1 and Context2 are
+ optional and may be 0. The function EntryPoint must never return.
+
+ If the current execution mode is not 32-bit protected mode with flat
+ descriptors, then ASSERT().
+ If EntryPoint is 0, then ASSERT().
+ If NewStack is 0, then ASSERT().
+
+ @param Cs The 16-bit selector to load in the CS before EntryPoint
+ is called. The descriptor in the GDT that this selector
+ references must be setup for long mode.
+ @param EntryPoint The 64-bit virtual address of the function to call with
+ the new stack after paging is enabled.
+ @param Context1 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the first parameter after
+ paging is enabled.
+ @param Context2 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the second parameter after
+ paging is enabled.
+ @param NewStack The 64-bit virtual address of the new stack to use for
+ the EntryPoint function after paging is enabled.
+
+**/
+VOID
+EFIAPI
+AsmEnablePaging64 (
+ IN UINT16 Cs,
+ IN UINT64 EntryPoint,
+ IN UINT64 Context1 OPTIONAL,
+ IN UINT64 Context2 OPTIONAL,
+ IN UINT64 NewStack
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmEnablePaging64 (Cs, EntryPoint, Context1, Context2, NewStack);
+}
+
+/**
+ Disables the 64-bit paging mode on the CPU.
+
+ Disables the 64-bit paging mode on the CPU and returns to 32-bit protected
+ mode. This function assumes the current execution mode is 64-paging mode.
+ This function is only available on x64. After the 64-bit paging mode is
+ disabled, control is transferred to the function specified by EntryPoint
+ using the new stack specified by NewStack and passing in the parameters
+ specified by Context1 and Context2. Context1 and Context2 are optional and
+ may be 0. The function EntryPoint must never return.
+
+ If the current execution mode is not 64-bit paged mode, then ASSERT().
+ If EntryPoint is 0, then ASSERT().
+ If NewStack is 0, then ASSERT().
+
+ @param Cs The 16-bit selector to load in the CS before EntryPoint
+ is called. The descriptor in the GDT that this selector
+ references must be setup for 32-bit protected mode.
+ @param EntryPoint The 64-bit virtual address of the function to call with
+ the new stack after paging is disabled.
+ @param Context1 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the first parameter after
+ paging is disabled.
+ @param Context2 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the second parameter after
+ paging is disabled.
+ @param NewStack The 64-bit virtual address of the new stack to use for
+ the EntryPoint function after paging is disabled.
+
+**/
+VOID
+EFIAPI
+AsmDisablePaging64 (
+ IN UINT16 Cs,
+ IN UINT32 EntryPoint,
+ IN UINT32 Context1 OPTIONAL,
+ IN UINT32 Context2 OPTIONAL,
+ IN UINT32 NewStack
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmDisablePaging64 (Cs, EntryPoint, Context1, Context2, NewStack);
+}
+
+/**
+ Retrieves the properties for 16-bit thunk functions.
+
+ Computes the size of the buffer and stack below 1MB required to use the
+ AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This
+ buffer size is returned in RealModeBufferSize, and the stack size is returned
+ in ExtraStackSize. If parameters are passed to the 16-bit real mode code,
+ then the actual minimum stack size is ExtraStackSize plus the maximum number
+ of bytes that need to be passed to the 16-bit real mode code.
+
+ If RealModeBufferSize is NULL, then ASSERT().
+ If ExtraStackSize is NULL, then ASSERT().
+
+ @param RealModeBufferSize A pointer to the size of the buffer below 1MB
+ required to use the 16-bit thunk functions.
+ @param ExtraStackSize A pointer to the extra size of stack below 1MB
+ that the 16-bit thunk functions require for
+ temporary storage in the transition to and from
+ 16-bit real mode.
+
+**/
+VOID
+EFIAPI
+AsmGetThunk16Properties (
+ OUT UINT32 *RealModeBufferSize,
+ OUT UINT32 *ExtraStackSize
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmGetThunk16Properties (RealModeBufferSize, ExtraStackSize);
+}
+
+/**
+ Prepares all structures a code required to use AsmThunk16().
+
+ Prepares all structures and code required to use AsmThunk16().
+
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
+ virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.
+
+ If ThunkContext is NULL, then ASSERT().
+
+ @param ThunkContext A pointer to the context structure that describes the
+ 16-bit real mode code to call.
+
+**/
+VOID
+EFIAPI
+AsmPrepareThunk16 (
+ IN OUT THUNK_CONTEXT *ThunkContext
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmPrepareThunk16 (ThunkContext);
+}
+
+/**
+ Transfers control to a 16-bit real mode entry point and returns the results.
+
+ Transfers control to a 16-bit real mode entry point and returns the results.
+ AsmPrepareThunk16() must be called with ThunkContext before this function is used.
+ This function must be called with interrupts disabled.
+
+ The register state from the RealModeState field of ThunkContext is restored just prior
+ to calling the 16-bit real mode entry point. This includes the EFLAGS field of RealModeState,
+ which is used to set the interrupt state when a 16-bit real mode entry point is called.
+ Control is transferred to the 16-bit real mode entry point specified by the CS and Eip fields of RealModeState.
+ The stack is initialized to the SS and ESP fields of RealModeState. Any parameters passed to
+ the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function.
+ The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instruction,
+ so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment
+ and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry
+ point must exit with a RETF instruction. The register state is captured into RealModeState immediately
+ after the RETF instruction is executed.
+
+ If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,
+ or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure
+ the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode.
+
+ If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,
+ then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode.
+ This includes the base vectors, the interrupt masks, and the edge/level trigger mode.
+
+ If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code
+ is invoked in big real mode. Otherwise, the user code is invoked in 16-bit real mode with 64KB segment limits.
+
+ If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in
+ ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to
+ disable the A20 mask.
+
+ If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in
+ ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask. If this INT 15 call fails,
+ then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.
+
+ If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in
+ ThunkAttributes, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.
+
+ If ThunkContext is NULL, then ASSERT().
+ If AsmPrepareThunk16() was not previously called with ThunkContext, then ASSERT().
+ If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in
+ ThunkAttributes, then ASSERT().
+
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
+ virtual to physical mappings for ThunkContext.RealModeBuffer are mapped 1:1.
+
+ @param ThunkContext A pointer to the context structure that describes the
+ 16-bit real mode code to call.
+
+**/
+VOID
+EFIAPI
+AsmThunk16 (
+ IN OUT THUNK_CONTEXT *ThunkContext
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmThunk16 (ThunkContext);
+}
+
+/**
+ Prepares all structures and code for a 16-bit real mode thunk, transfers
+ control to a 16-bit real mode entry point, and returns the results.
+
+ Prepares all structures and code for a 16-bit real mode thunk, transfers
+ control to a 16-bit real mode entry point, and returns the results. If the
+ caller only need to perform a single 16-bit real mode thunk, then this
+ service should be used. If the caller intends to make more than one 16-bit
+ real mode thunk, then it is more efficient if AsmPrepareThunk16() is called
+ once and AsmThunk16() can be called for each 16-bit real mode thunk.
+
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
+ virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.
+
+ See AsmPrepareThunk16() and AsmThunk16() for the detailed description and ASSERT() conditions.
+
+ @param ThunkContext A pointer to the context structure that describes the
+ 16-bit real mode code to call.
+
+**/
+VOID
+EFIAPI
+AsmPrepareAndThunk16 (
+ IN OUT THUNK_CONTEXT *ThunkContext
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmPrepareAndThunk16 (ThunkContext);
+}
+
+/**
+ Load given selector into TR register.
+
+ @param[in] Selector Task segment selector
+**/
+VOID
+EFIAPI
+AsmWriteTr (
+ IN UINT16 Selector
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmWriteTr (Selector);
+}
+
+/**
+ Performs a serializing operation on all load-from-memory instructions that
+ were issued prior the AsmLfence function.
+
+ Executes a LFENCE instruction. This function is only available on IA-32 and x64.
+
+**/
+VOID
+EFIAPI
+AsmLfence (
+ VOID
+ )
+{
+ gUnitTestHostBaseLib.X86->AsmLfence ();
+}
+
+/**
+ Patch the immediate operand of an IA32 or X64 instruction such that the byte,
+ word, dword or qword operand is encoded at the end of the instruction's
+ binary representation.
+
+ This function should be used to update object code that was compiled with
+ NASM from assembly source code. Example:
+
+ NASM source code:
+
+ mov eax, strict dword 0 ; the imm32 zero operand will be patched
+ ASM_PFX(gPatchCr3):
+ mov cr3, eax
+
+ C source code:
+
+ X86_ASSEMBLY_PATCH_LABEL gPatchCr3;
+ PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);
+
+ @param[out] InstructionEnd Pointer right past the instruction to patch. The
+ immediate operand to patch is expected to
+ comprise the trailing bytes of the instruction.
+ If InstructionEnd is closer to address 0 than
+ ValueSize permits, then ASSERT().
+
+ @param[in] PatchValue The constant to write to the immediate operand.
+ The caller is responsible for ensuring that
+ PatchValue can be represented in the byte, word,
+ dword or qword operand (as indicated through
+ ValueSize); otherwise ASSERT().
+
+ @param[in] ValueSize The size of the operand in bytes; must be 1, 2,
+ 4, or 8. ASSERT() otherwise.
+**/
+VOID
+EFIAPI
+PatchInstructionX86 (
+ OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
+ IN UINT64 PatchValue,
+ IN UINTN ValueSize
+ )
+{
+ gUnitTestHostBaseLib.X86->PatchInstructionX86 (InstructionEnd, PatchValue, ValueSize);
+}
+
+///
+/// Common services
+///
+STATIC UNIT_TEST_HOST_BASE_LIB_COMMON mUnitTestHostBaseLibCommon = {
+ UnitTestHostBaseLibEnableInterrupts,
+ UnitTestHostBaseLibDisableInterrupts,
+ UnitTestHostBaseLibEnableDisableInterrupts,
+ UnitTestHostBaseLibGetInterruptState,
+};
+
+///
+/// IA32/X64 services
+///
+STATIC UNIT_TEST_HOST_BASE_LIB_X86 mUnitTestHostBaseLibX86 = {
+ UnitTestHostBaseLibAsmCpuid,
+ UnitTestHostBaseLibAsmCpuidEx,
+ UnitTestHostBaseLibAsmDisableCache,
+ UnitTestHostBaseLibAsmEnableCache,
+ UnitTestHostBaseLibAsmReadMsr64,
+ UnitTestHostBaseLibAsmWriteMsr64,
+ UnitTestHostBaseLibAsmReadCr0,
+ UnitTestHostBaseLibAsmReadCr2,
+ UnitTestHostBaseLibAsmReadCr3,
+ UnitTestHostBaseLibAsmReadCr4,
+ UnitTestHostBaseLibAsmWriteCr0,
+ UnitTestHostBaseLibAsmWriteCr2,
+ UnitTestHostBaseLibAsmWriteCr3,
+ UnitTestHostBaseLibAsmWriteCr4,
+ UnitTestHostBaseLibAsmReadDr0,
+ UnitTestHostBaseLibAsmReadDr1,
+ UnitTestHostBaseLibAsmReadDr2,
+ UnitTestHostBaseLibAsmReadDr3,
+ UnitTestHostBaseLibAsmReadDr4,
+ UnitTestHostBaseLibAsmReadDr5,
+ UnitTestHostBaseLibAsmReadDr6,
+ UnitTestHostBaseLibAsmReadDr7,
+ UnitTestHostBaseLibAsmWriteDr0,
+ UnitTestHostBaseLibAsmWriteDr1,
+ UnitTestHostBaseLibAsmWriteDr2,
+ UnitTestHostBaseLibAsmWriteDr3,
+ UnitTestHostBaseLibAsmWriteDr4,
+ UnitTestHostBaseLibAsmWriteDr5,
+ UnitTestHostBaseLibAsmWriteDr6,
+ UnitTestHostBaseLibAsmWriteDr7,
+ UnitTestHostBaseLibAsmReadCs,
+ UnitTestHostBaseLibAsmReadDs,
+ UnitTestHostBaseLibAsmReadEs,
+ UnitTestHostBaseLibAsmReadFs,
+ UnitTestHostBaseLibAsmReadGs,
+ UnitTestHostBaseLibAsmReadSs,
+ UnitTestHostBaseLibAsmReadTr,
+ UnitTestHostBaseLibAsmReadGdtr,
+ UnitTestHostBaseLibAsmWriteGdtr,
+ UnitTestHostBaseLibAsmReadIdtr,
+ UnitTestHostBaseLibAsmWriteIdtr,
+ UnitTestHostBaseLibAsmReadLdtr,
+ UnitTestHostBaseLibAsmWriteLdtr,
+ UnitTestHostBaseLibAsmReadPmc,
+ UnitTestHostBaseLibAsmMonitor,
+ UnitTestHostBaseLibAsmMwait,
+ UnitTestHostBaseLibAsmWbinvd,
+ UnitTestHostBaseLibAsmInvd,
+ UnitTestHostBaseLibAsmFlushCacheLine,
+ UnitTestHostBaseLibAsmEnablePaging32,
+ UnitTestHostBaseLibAsmDisablePaging32,
+ UnitTestHostBaseLibAsmEnablePaging64,
+ UnitTestHostBaseLibAsmDisablePaging64,
+ UnitTestHostBaseLibAsmGetThunk16Properties,
+ UnitTestHostBaseLibAsmPrepareThunk16,
+ UnitTestHostBaseLibAsmThunk16,
+ UnitTestHostBaseLibAsmPrepareAndThunk16,
+ UnitTestHostBaseLibAsmWriteTr,
+ UnitTestHostBaseLibAsmLfence,
+ UnitTestHostBaseLibPatchInstructionX86
+};
+
+///
+/// Structure of hook functions for BaseLib functions that can not be used from
+/// a host application. A simple emulation of these function is provided by
+/// default. A specific unit test can provide its own implementation for any
+/// of these functions.
+///
+UNIT_TEST_HOST_BASE_LIB gUnitTestHostBaseLib = {
+ &mUnitTestHostBaseLibCommon,
+ &mUnitTestHostBaseLibX86
+};
diff --git a/MdePkg/Library/BaseLib/X86WriteGdtr.c b/MdePkg/Library/BaseLib/X86WriteGdtr.c
index f3f982da..bc212f5a 100644
--- a/MdePkg/Library/BaseLib/X86WriteGdtr.c
+++ b/MdePkg/Library/BaseLib/X86WriteGdtr.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -25,7 +22,7 @@
VOID
EFIAPI
AsmWriteGdtr (
- IN CONST IA32_DESCRIPTOR *Gdtr
+ IN CONST IA32_DESCRIPTOR *Gdtr
)
{
ASSERT (Gdtr != NULL);
diff --git a/MdePkg/Library/BaseLib/X86WriteIdtr.c b/MdePkg/Library/BaseLib/X86WriteIdtr.c
index a175a204..d7de8255 100644
--- a/MdePkg/Library/BaseLib/X86WriteIdtr.c
+++ b/MdePkg/Library/BaseLib/X86WriteIdtr.c
@@ -6,9 +6,6 @@
**/
-
-
-
#include "BaseLibInternals.h"
/**
@@ -25,7 +22,7 @@
VOID
EFIAPI
AsmWriteIdtr (
- IN CONST IA32_DESCRIPTOR *Idtr
+ IN CONST IA32_DESCRIPTOR *Idtr
)
{
ASSERT (Idtr != NULL);
diff --git a/MdePkg/Library/BaseMemoryLibRepStr/CompareMemWrapper.c b/MdePkg/Library/BaseMemoryLibRepStr/CompareMemWrapper.c
index c19d2140..2100dd52 100644
--- a/MdePkg/Library/BaseMemoryLibRepStr/CompareMemWrapper.c
+++ b/MdePkg/Library/BaseMemoryLibRepStr/CompareMemWrapper.c
@@ -48,9 +48,10 @@ CompareMem (
IN UINTN Length
)
{
- if (Length == 0 || DestinationBuffer == SourceBuffer) {
+ if ((Length == 0) || (DestinationBuffer == SourceBuffer)) {
return 0;
}
+
ASSERT (DestinationBuffer != NULL);
ASSERT (SourceBuffer != NULL);
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)DestinationBuffer));
diff --git a/MdePkg/Library/BaseMemoryLibRepStr/CopyMemWrapper.c b/MdePkg/Library/BaseMemoryLibRepStr/CopyMemWrapper.c
index 9db53b0b..91dcad29 100644
--- a/MdePkg/Library/BaseMemoryLibRepStr/CopyMemWrapper.c
+++ b/MdePkg/Library/BaseMemoryLibRepStr/CopyMemWrapper.c
@@ -47,11 +47,13 @@ CopyMem (
if (Length == 0) {
return DestinationBuffer;
}
+
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)DestinationBuffer));
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)SourceBuffer));
if (DestinationBuffer == SourceBuffer) {
return DestinationBuffer;
}
+
return InternalMemCopyMem (DestinationBuffer, SourceBuffer, Length);
}
diff --git a/MdePkg/Library/BaseMemoryLibRepStr/MemLibGuid.c b/MdePkg/Library/BaseMemoryLibRepStr/MemLibGuid.c
index e214695a..1462b0e9 100644
--- a/MdePkg/Library/BaseMemoryLibRepStr/MemLibGuid.c
+++ b/MdePkg/Library/BaseMemoryLibRepStr/MemLibGuid.c
@@ -42,12 +42,12 @@ CopyGuid (
)
{
WriteUnaligned64 (
- (UINT64*)DestinationGuid,
- ReadUnaligned64 ((CONST UINT64*)SourceGuid)
+ (UINT64 *)DestinationGuid,
+ ReadUnaligned64 ((CONST UINT64 *)SourceGuid)
);
WriteUnaligned64 (
- (UINT64*)DestinationGuid + 1,
- ReadUnaligned64 ((CONST UINT64*)SourceGuid + 1)
+ (UINT64 *)DestinationGuid + 1,
+ ReadUnaligned64 ((CONST UINT64 *)SourceGuid + 1)
);
return DestinationGuid;
}
@@ -80,12 +80,12 @@ CompareGuid (
UINT64 HighPartOfGuid1;
UINT64 HighPartOfGuid2;
- LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1);
- LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2);
- HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1 + 1);
- HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2 + 1);
+ LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64 *)Guid1);
+ LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64 *)Guid2);
+ HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64 *)Guid1 + 1);
+ HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64 *)Guid2 + 1);
- return (BOOLEAN) (LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);
+ return (BOOLEAN)(LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);
}
/**
@@ -118,20 +118,22 @@ ScanGuid (
IN CONST GUID *Guid
)
{
- CONST GUID *GuidPtr;
+ CONST GUID *GuidPtr;
ASSERT (((UINTN)Buffer & (sizeof (Guid->Data1) - 1)) == 0);
ASSERT (Length <= (MAX_ADDRESS - (UINTN)Buffer + 1));
ASSERT ((Length & (sizeof (*GuidPtr) - 1)) == 0);
- GuidPtr = (GUID*)Buffer;
+ GuidPtr = (GUID *)Buffer;
Buffer = GuidPtr + Length / sizeof (*GuidPtr);
- while (GuidPtr < (CONST GUID*)Buffer) {
+ while (GuidPtr < (CONST GUID *)Buffer) {
if (CompareGuid (GuidPtr, Guid)) {
- return (VOID*)GuidPtr;
+ return (VOID *)GuidPtr;
}
+
GuidPtr++;
}
+
return NULL;
}
@@ -158,8 +160,8 @@ IsZeroGuid (
UINT64 LowPartOfGuid;
UINT64 HighPartOfGuid;
- LowPartOfGuid = ReadUnaligned64 ((CONST UINT64*) Guid);
- HighPartOfGuid = ReadUnaligned64 ((CONST UINT64*) Guid + 1);
+ LowPartOfGuid = ReadUnaligned64 ((CONST UINT64 *)Guid);
+ HighPartOfGuid = ReadUnaligned64 ((CONST UINT64 *)Guid + 1);
- return (BOOLEAN) (LowPartOfGuid == 0 && HighPartOfGuid == 0);
+ return (BOOLEAN)(LowPartOfGuid == 0 && HighPartOfGuid == 0);
}
diff --git a/MdePkg/Library/BaseMemoryLibRepStr/MemLibInternals.h b/MdePkg/Library/BaseMemoryLibRepStr/MemLibInternals.h
index ec1c440f..ba3175c6 100644
--- a/MdePkg/Library/BaseMemoryLibRepStr/MemLibInternals.h
+++ b/MdePkg/Library/BaseMemoryLibRepStr/MemLibInternals.h
@@ -35,9 +35,9 @@
VOID *
EFIAPI
InternalMemCopyMem (
- OUT VOID *DestinationBuffer,
- IN CONST VOID *SourceBuffer,
- IN UINTN Length
+ OUT VOID *DestinationBuffer,
+ IN CONST VOID *SourceBuffer,
+ IN UINTN Length
);
/**
@@ -53,9 +53,9 @@ InternalMemCopyMem (
VOID *
EFIAPI
InternalMemSetMem (
- OUT VOID *Buffer,
- IN UINTN Length,
- IN UINT8 Value
+ OUT VOID *Buffer,
+ IN UINTN Length,
+ IN UINT8 Value
);
/**
@@ -71,9 +71,9 @@ InternalMemSetMem (
VOID *
EFIAPI
InternalMemSetMem16 (
- OUT VOID *Buffer,
- IN UINTN Length,
- IN UINT16 Value
+ OUT VOID *Buffer,
+ IN UINTN Length,
+ IN UINT16 Value
);
/**
@@ -89,9 +89,9 @@ InternalMemSetMem16 (
VOID *
EFIAPI
InternalMemSetMem32 (
- OUT VOID *Buffer,
- IN UINTN Length,
- IN UINT32 Value
+ OUT VOID *Buffer,
+ IN UINTN Length,
+ IN UINT32 Value
);
/**
@@ -107,9 +107,9 @@ InternalMemSetMem32 (
VOID *
EFIAPI
InternalMemSetMem64 (
- OUT VOID *Buffer,
- IN UINTN Length,
- IN UINT64 Value
+ OUT VOID *Buffer,
+ IN UINTN Length,
+ IN UINT64 Value
);
/**
@@ -124,8 +124,8 @@ InternalMemSetMem64 (
VOID *
EFIAPI
InternalMemZeroMem (
- OUT VOID *Buffer,
- IN UINTN Length
+ OUT VOID *Buffer,
+ IN UINTN Length
);
/**
@@ -144,9 +144,9 @@ InternalMemZeroMem (
INTN
EFIAPI
InternalMemCompareMem (
- IN CONST VOID *DestinationBuffer,
- IN CONST VOID *SourceBuffer,
- IN UINTN Length
+ IN CONST VOID *DestinationBuffer,
+ IN CONST VOID *SourceBuffer,
+ IN UINTN Length
);
/**
@@ -163,9 +163,9 @@ InternalMemCompareMem (
CONST VOID *
EFIAPI
InternalMemScanMem8 (
- IN CONST VOID *Buffer,
- IN UINTN Length,
- IN UINT8 Value
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN UINT8 Value
);
/**
@@ -182,9 +182,9 @@ InternalMemScanMem8 (
CONST VOID *
EFIAPI
InternalMemScanMem16 (
- IN CONST VOID *Buffer,
- IN UINTN Length,
- IN UINT16 Value
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN UINT16 Value
);
/**
@@ -201,9 +201,9 @@ InternalMemScanMem16 (
CONST VOID *
EFIAPI
InternalMemScanMem32 (
- IN CONST VOID *Buffer,
- IN UINTN Length,
- IN UINT32 Value
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN UINT32 Value
);
/**
@@ -220,9 +220,9 @@ InternalMemScanMem32 (
CONST VOID *
EFIAPI
InternalMemScanMem64 (
- IN CONST VOID *Buffer,
- IN UINTN Length,
- IN UINT64 Value
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN UINT64 Value
);
/**
diff --git a/MdePkg/Library/BaseMemoryLibRepStr/ScanMem16Wrapper.c b/MdePkg/Library/BaseMemoryLibRepStr/ScanMem16Wrapper.c
index 1e284f5f..dfddb961 100644
--- a/MdePkg/Library/BaseMemoryLibRepStr/ScanMem16Wrapper.c
+++ b/MdePkg/Library/BaseMemoryLibRepStr/ScanMem16Wrapper.c
@@ -57,5 +57,5 @@ ScanMem16 (
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));
ASSERT ((Length & (sizeof (Value) - 1)) == 0);
- return (VOID*)InternalMemScanMem16 (Buffer, Length / sizeof (Value), Value);
+ return (VOID *)InternalMemScanMem16 (Buffer, Length / sizeof (Value), Value);
}
diff --git a/MdePkg/Library/BaseMemoryLibRepStr/ScanMem32Wrapper.c b/MdePkg/Library/BaseMemoryLibRepStr/ScanMem32Wrapper.c
index 758c1428..63b774c4 100644
--- a/MdePkg/Library/BaseMemoryLibRepStr/ScanMem32Wrapper.c
+++ b/MdePkg/Library/BaseMemoryLibRepStr/ScanMem32Wrapper.c
@@ -56,5 +56,5 @@ ScanMem32 (
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));
ASSERT ((Length & (sizeof (Value) - 1)) == 0);
- return (VOID*)InternalMemScanMem32 (Buffer, Length / sizeof (Value), Value);
+ return (VOID *)InternalMemScanMem32 (Buffer, Length / sizeof (Value), Value);
}
diff --git a/MdePkg/Library/BaseMemoryLibRepStr/ScanMem64Wrapper.c b/MdePkg/Library/BaseMemoryLibRepStr/ScanMem64Wrapper.c
index 89a82fc5..ecd6b5a4 100644
--- a/MdePkg/Library/BaseMemoryLibRepStr/ScanMem64Wrapper.c
+++ b/MdePkg/Library/BaseMemoryLibRepStr/ScanMem64Wrapper.c
@@ -57,5 +57,5 @@ ScanMem64 (
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));
ASSERT ((Length & (sizeof (Value) - 1)) == 0);
- return (VOID*)InternalMemScanMem64 (Buffer, Length / sizeof (Value), Value);
+ return (VOID *)InternalMemScanMem64 (Buffer, Length / sizeof (Value), Value);
}
diff --git a/MdePkg/Library/BaseMemoryLibRepStr/ScanMem8Wrapper.c b/MdePkg/Library/BaseMemoryLibRepStr/ScanMem8Wrapper.c
index 7f1c7d22..973edca9 100644
--- a/MdePkg/Library/BaseMemoryLibRepStr/ScanMem8Wrapper.c
+++ b/MdePkg/Library/BaseMemoryLibRepStr/ScanMem8Wrapper.c
@@ -49,10 +49,11 @@ ScanMem8 (
if (Length == 0) {
return NULL;
}
+
ASSERT (Buffer != NULL);
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));
- return (VOID*)InternalMemScanMem8 (Buffer, Length, Value);
+ return (VOID *)InternalMemScanMem8 (Buffer, Length, Value);
}
/**
@@ -90,4 +91,3 @@ ScanMemN (
return ScanMem32 (Buffer, Length, (UINT32)Value);
}
}
-
diff --git a/MdePkg/Library/BaseMemoryLibSse2/CompareMemWrapper.c b/MdePkg/Library/BaseMemoryLibSse2/CompareMemWrapper.c
index c19d2140..2100dd52 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/CompareMemWrapper.c
+++ b/MdePkg/Library/BaseMemoryLibSse2/CompareMemWrapper.c
@@ -48,9 +48,10 @@ CompareMem (
IN UINTN Length
)
{
- if (Length == 0 || DestinationBuffer == SourceBuffer) {
+ if ((Length == 0) || (DestinationBuffer == SourceBuffer)) {
return 0;
}
+
ASSERT (DestinationBuffer != NULL);
ASSERT (SourceBuffer != NULL);
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)DestinationBuffer));
diff --git a/MdePkg/Library/BaseMemoryLibSse2/CopyMemWrapper.c b/MdePkg/Library/BaseMemoryLibSse2/CopyMemWrapper.c
index 9db53b0b..91dcad29 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/CopyMemWrapper.c
+++ b/MdePkg/Library/BaseMemoryLibSse2/CopyMemWrapper.c
@@ -47,11 +47,13 @@ CopyMem (
if (Length == 0) {
return DestinationBuffer;
}
+
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)DestinationBuffer));
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)SourceBuffer));
if (DestinationBuffer == SourceBuffer) {
return DestinationBuffer;
}
+
return InternalMemCopyMem (DestinationBuffer, SourceBuffer, Length);
}
diff --git a/MdePkg/Library/BaseMemoryLibSse2/MemLibGuid.c b/MdePkg/Library/BaseMemoryLibSse2/MemLibGuid.c
index e214695a..1462b0e9 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/MemLibGuid.c
+++ b/MdePkg/Library/BaseMemoryLibSse2/MemLibGuid.c
@@ -42,12 +42,12 @@ CopyGuid (
)
{
WriteUnaligned64 (
- (UINT64*)DestinationGuid,
- ReadUnaligned64 ((CONST UINT64*)SourceGuid)
+ (UINT64 *)DestinationGuid,
+ ReadUnaligned64 ((CONST UINT64 *)SourceGuid)
);
WriteUnaligned64 (
- (UINT64*)DestinationGuid + 1,
- ReadUnaligned64 ((CONST UINT64*)SourceGuid + 1)
+ (UINT64 *)DestinationGuid + 1,
+ ReadUnaligned64 ((CONST UINT64 *)SourceGuid + 1)
);
return DestinationGuid;
}
@@ -80,12 +80,12 @@ CompareGuid (
UINT64 HighPartOfGuid1;
UINT64 HighPartOfGuid2;
- LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1);
- LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2);
- HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1 + 1);
- HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2 + 1);
+ LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64 *)Guid1);
+ LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64 *)Guid2);
+ HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64 *)Guid1 + 1);
+ HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64 *)Guid2 + 1);
- return (BOOLEAN) (LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);
+ return (BOOLEAN)(LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);
}
/**
@@ -118,20 +118,22 @@ ScanGuid (
IN CONST GUID *Guid
)
{
- CONST GUID *GuidPtr;
+ CONST GUID *GuidPtr;
ASSERT (((UINTN)Buffer & (sizeof (Guid->Data1) - 1)) == 0);
ASSERT (Length <= (MAX_ADDRESS - (UINTN)Buffer + 1));
ASSERT ((Length & (sizeof (*GuidPtr) - 1)) == 0);
- GuidPtr = (GUID*)Buffer;
+ GuidPtr = (GUID *)Buffer;
Buffer = GuidPtr + Length / sizeof (*GuidPtr);
- while (GuidPtr < (CONST GUID*)Buffer) {
+ while (GuidPtr < (CONST GUID *)Buffer) {
if (CompareGuid (GuidPtr, Guid)) {
- return (VOID*)GuidPtr;
+ return (VOID *)GuidPtr;
}
+
GuidPtr++;
}
+
return NULL;
}
@@ -158,8 +160,8 @@ IsZeroGuid (
UINT64 LowPartOfGuid;
UINT64 HighPartOfGuid;
- LowPartOfGuid = ReadUnaligned64 ((CONST UINT64*) Guid);
- HighPartOfGuid = ReadUnaligned64 ((CONST UINT64*) Guid + 1);
+ LowPartOfGuid = ReadUnaligned64 ((CONST UINT64 *)Guid);
+ HighPartOfGuid = ReadUnaligned64 ((CONST UINT64 *)Guid + 1);
- return (BOOLEAN) (LowPartOfGuid == 0 && HighPartOfGuid == 0);
+ return (BOOLEAN)(LowPartOfGuid == 0 && HighPartOfGuid == 0);
}
diff --git a/MdePkg/Library/BaseMemoryLibSse2/MemLibInternals.h b/MdePkg/Library/BaseMemoryLibSse2/MemLibInternals.h
index bb032dff..958f3004 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/MemLibInternals.h
+++ b/MdePkg/Library/BaseMemoryLibSse2/MemLibInternals.h
@@ -35,9 +35,9 @@
VOID *
EFIAPI
InternalMemCopyMem (
- OUT VOID *DestinationBuffer,
- IN CONST VOID *SourceBuffer,
- IN UINTN Length
+ OUT VOID *DestinationBuffer,
+ IN CONST VOID *SourceBuffer,
+ IN UINTN Length
);
/**
@@ -53,9 +53,9 @@ InternalMemCopyMem (
VOID *
EFIAPI
InternalMemSetMem (
- OUT VOID *Buffer,
- IN UINTN Length,
- IN UINT8 Value
+ OUT VOID *Buffer,
+ IN UINTN Length,
+ IN UINT8 Value
);
/**
@@ -71,9 +71,9 @@ InternalMemSetMem (
VOID *
EFIAPI
InternalMemSetMem16 (
- OUT VOID *Buffer,
- IN UINTN Length,
- IN UINT16 Value
+ OUT VOID *Buffer,
+ IN UINTN Length,
+ IN UINT16 Value
);
/**
@@ -89,9 +89,9 @@ InternalMemSetMem16 (
VOID *
EFIAPI
InternalMemSetMem32 (
- OUT VOID *Buffer,
- IN UINTN Length,
- IN UINT32 Value
+ OUT VOID *Buffer,
+ IN UINTN Length,
+ IN UINT32 Value
);
/**
@@ -107,9 +107,9 @@ InternalMemSetMem32 (
VOID *
EFIAPI
InternalMemSetMem64 (
- OUT VOID *Buffer,
- IN UINTN Length,
- IN UINT64 Value
+ OUT VOID *Buffer,
+ IN UINTN Length,
+ IN UINT64 Value
);
/**
@@ -124,8 +124,8 @@ InternalMemSetMem64 (
VOID *
EFIAPI
InternalMemZeroMem (
- OUT VOID *Buffer,
- IN UINTN Length
+ OUT VOID *Buffer,
+ IN UINTN Length
);
/**
@@ -144,9 +144,9 @@ InternalMemZeroMem (
INTN
EFIAPI
InternalMemCompareMem (
- IN CONST VOID *DestinationBuffer,
- IN CONST VOID *SourceBuffer,
- IN UINTN Length
+ IN CONST VOID *DestinationBuffer,
+ IN CONST VOID *SourceBuffer,
+ IN UINTN Length
);
/**
@@ -163,9 +163,9 @@ InternalMemCompareMem (
CONST VOID *
EFIAPI
InternalMemScanMem8 (
- IN CONST VOID *Buffer,
- IN UINTN Length,
- IN UINT8 Value
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN UINT8 Value
);
/**
@@ -182,9 +182,9 @@ InternalMemScanMem8 (
CONST VOID *
EFIAPI
InternalMemScanMem16 (
- IN CONST VOID *Buffer,
- IN UINTN Length,
- IN UINT16 Value
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN UINT16 Value
);
/**
@@ -201,9 +201,9 @@ InternalMemScanMem16 (
CONST VOID *
EFIAPI
InternalMemScanMem32 (
- IN CONST VOID *Buffer,
- IN UINTN Length,
- IN UINT32 Value
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN UINT32 Value
);
/**
@@ -220,9 +220,9 @@ InternalMemScanMem32 (
CONST VOID *
EFIAPI
InternalMemScanMem64 (
- IN CONST VOID *Buffer,
- IN UINTN Length,
- IN UINT64 Value
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN UINT64 Value
);
/**
diff --git a/MdePkg/Library/BaseMemoryLibSse2/ScanMem16Wrapper.c b/MdePkg/Library/BaseMemoryLibSse2/ScanMem16Wrapper.c
index 1e284f5f..dfddb961 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/ScanMem16Wrapper.c
+++ b/MdePkg/Library/BaseMemoryLibSse2/ScanMem16Wrapper.c
@@ -57,5 +57,5 @@ ScanMem16 (
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));
ASSERT ((Length & (sizeof (Value) - 1)) == 0);
- return (VOID*)InternalMemScanMem16 (Buffer, Length / sizeof (Value), Value);
+ return (VOID *)InternalMemScanMem16 (Buffer, Length / sizeof (Value), Value);
}
diff --git a/MdePkg/Library/BaseMemoryLibSse2/ScanMem32Wrapper.c b/MdePkg/Library/BaseMemoryLibSse2/ScanMem32Wrapper.c
index 758c1428..63b774c4 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/ScanMem32Wrapper.c
+++ b/MdePkg/Library/BaseMemoryLibSse2/ScanMem32Wrapper.c
@@ -56,5 +56,5 @@ ScanMem32 (
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));
ASSERT ((Length & (sizeof (Value) - 1)) == 0);
- return (VOID*)InternalMemScanMem32 (Buffer, Length / sizeof (Value), Value);
+ return (VOID *)InternalMemScanMem32 (Buffer, Length / sizeof (Value), Value);
}
diff --git a/MdePkg/Library/BaseMemoryLibSse2/ScanMem64Wrapper.c b/MdePkg/Library/BaseMemoryLibSse2/ScanMem64Wrapper.c
index 89a82fc5..ecd6b5a4 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/ScanMem64Wrapper.c
+++ b/MdePkg/Library/BaseMemoryLibSse2/ScanMem64Wrapper.c
@@ -57,5 +57,5 @@ ScanMem64 (
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));
ASSERT ((Length & (sizeof (Value) - 1)) == 0);
- return (VOID*)InternalMemScanMem64 (Buffer, Length / sizeof (Value), Value);
+ return (VOID *)InternalMemScanMem64 (Buffer, Length / sizeof (Value), Value);
}
diff --git a/MdePkg/Library/BaseMemoryLibSse2/ScanMem8Wrapper.c b/MdePkg/Library/BaseMemoryLibSse2/ScanMem8Wrapper.c
index 7f1c7d22..973edca9 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/ScanMem8Wrapper.c
+++ b/MdePkg/Library/BaseMemoryLibSse2/ScanMem8Wrapper.c
@@ -49,10 +49,11 @@ ScanMem8 (
if (Length == 0) {
return NULL;
}
+
ASSERT (Buffer != NULL);
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));
- return (VOID*)InternalMemScanMem8 (Buffer, Length, Value);
+ return (VOID *)InternalMemScanMem8 (Buffer, Length, Value);
}
/**
@@ -90,4 +91,3 @@ ScanMemN (
return ScanMem32 (Buffer, Length, (UINT32)Value);
}
}
-
diff --git a/MdePkg/Library/BasePcdLibNull/PcdLib.c b/MdePkg/Library/BasePcdLibNull/PcdLib.c
index 9fd345b9..79f3ac6d 100644
--- a/MdePkg/Library/BasePcdLibNull/PcdLib.c
+++ b/MdePkg/Library/BasePcdLibNull/PcdLib.c
@@ -12,7 +12,6 @@
#include
#include
-
/**
This function provides a means by which SKU support can be established in the PCD infrastructure.
@@ -27,7 +26,7 @@
UINTN
EFIAPI
LibPcdSetSku (
- IN UINTN SkuId
+ IN UINTN SkuId
)
{
ASSERT (FALSE);
@@ -48,7 +47,7 @@ LibPcdSetSku (
UINT8
EFIAPI
LibPcdGet8 (
- IN UINTN TokenNumber
+ IN UINTN TokenNumber
)
{
ASSERT (FALSE);
@@ -56,8 +55,6 @@ LibPcdGet8 (
return 0;
}
-
-
/**
This function provides a means by which to retrieve a value for a given PCD token.
@@ -71,7 +68,7 @@ LibPcdGet8 (
UINT16
EFIAPI
LibPcdGet16 (
- IN UINTN TokenNumber
+ IN UINTN TokenNumber
)
{
ASSERT (FALSE);
@@ -79,8 +76,6 @@ LibPcdGet16 (
return 0;
}
-
-
/**
This function provides a means by which to retrieve a value for a given PCD token.
@@ -94,7 +89,7 @@ LibPcdGet16 (
UINT32
EFIAPI
LibPcdGet32 (
- IN UINTN TokenNumber
+ IN UINTN TokenNumber
)
{
ASSERT (FALSE);
@@ -102,8 +97,6 @@ LibPcdGet32 (
return 0;
}
-
-
/**
This function provides a means by which to retrieve a value for a given PCD token.
@@ -117,7 +110,7 @@ LibPcdGet32 (
UINT64
EFIAPI
LibPcdGet64 (
- IN UINTN TokenNumber
+ IN UINTN TokenNumber
)
{
ASSERT (FALSE);
@@ -125,8 +118,6 @@ LibPcdGet64 (
return 0;
}
-
-
/**
This function provides a means by which to retrieve a value for a given PCD token.
@@ -140,7 +131,7 @@ LibPcdGet64 (
VOID *
EFIAPI
LibPcdGetPtr (
- IN UINTN TokenNumber
+ IN UINTN TokenNumber
)
{
ASSERT (FALSE);
@@ -148,8 +139,6 @@ LibPcdGetPtr (
return 0;
}
-
-
/**
This function provides a means by which to retrieve a value for a given PCD token.
@@ -163,7 +152,7 @@ LibPcdGetPtr (
BOOLEAN
EFIAPI
LibPcdGetBool (
- IN UINTN TokenNumber
+ IN UINTN TokenNumber
)
{
ASSERT (FALSE);
@@ -171,8 +160,6 @@ LibPcdGetBool (
return 0;
}
-
-
/**
This function provides a means by which to retrieve the size of a given PCD token.
@@ -184,7 +171,7 @@ LibPcdGetBool (
UINTN
EFIAPI
LibPcdGetSize (
- IN UINTN TokenNumber
+ IN UINTN TokenNumber
)
{
ASSERT (FALSE);
@@ -192,8 +179,6 @@ LibPcdGetSize (
return 0;
}
-
-
/**
This function provides a means by which to retrieve a value for a given PCD token.
@@ -211,8 +196,8 @@ LibPcdGetSize (
UINT8
EFIAPI
LibPcdGetEx8 (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber
)
{
ASSERT (FALSE);
@@ -220,8 +205,6 @@ LibPcdGetEx8 (
return 0;
}
-
-
/**
This function provides a means by which to retrieve a value for a given PCD token.
@@ -239,8 +222,8 @@ LibPcdGetEx8 (
UINT16
EFIAPI
LibPcdGetEx16 (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber
)
{
ASSERT (FALSE);
@@ -248,8 +231,6 @@ LibPcdGetEx16 (
return 0;
}
-
-
/**
Returns the 32-bit value for the token specified by TokenNumber and Guid.
If Guid is NULL, then ASSERT().
@@ -264,8 +245,8 @@ LibPcdGetEx16 (
UINT32
EFIAPI
LibPcdGetEx32 (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber
)
{
ASSERT (FALSE);
@@ -273,8 +254,6 @@ LibPcdGetEx32 (
return 0;
}
-
-
/**
This function provides a means by which to retrieve a value for a given PCD token.
@@ -292,8 +271,8 @@ LibPcdGetEx32 (
UINT64
EFIAPI
LibPcdGetEx64 (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber
)
{
ASSERT (FALSE);
@@ -301,8 +280,6 @@ LibPcdGetEx64 (
return 0;
}
-
-
/**
This function provides a means by which to retrieve a value for a given PCD token.
@@ -320,8 +297,8 @@ LibPcdGetEx64 (
VOID *
EFIAPI
LibPcdGetExPtr (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber
)
{
ASSERT (FALSE);
@@ -329,8 +306,6 @@ LibPcdGetExPtr (
return 0;
}
-
-
/**
This function provides a means by which to retrieve a value for a given PCD token.
@@ -348,8 +323,8 @@ LibPcdGetExPtr (
BOOLEAN
EFIAPI
LibPcdGetExBool (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber
)
{
ASSERT (FALSE);
@@ -357,8 +332,6 @@ LibPcdGetExBool (
return 0;
}
-
-
/**
This function provides a means by which to retrieve the size of a given PCD token.
@@ -376,8 +349,8 @@ LibPcdGetExBool (
UINTN
EFIAPI
LibPcdGetExSize (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber
)
{
ASSERT (FALSE);
@@ -385,7 +358,6 @@ LibPcdGetExSize (
return 0;
}
-
/**
This function provides a means by which to set a value for a given PCD token.
@@ -401,8 +373,8 @@ LibPcdGetExSize (
RETURN_STATUS
EFIAPI
LibPcdSet8S (
- IN UINTN TokenNumber,
- IN UINT8 Value
+ IN UINTN TokenNumber,
+ IN UINT8 Value
)
{
ASSERT (FALSE);
@@ -425,8 +397,8 @@ LibPcdSet8S (
RETURN_STATUS
EFIAPI
LibPcdSet16S (
- IN UINTN TokenNumber,
- IN UINT16 Value
+ IN UINTN TokenNumber,
+ IN UINT16 Value
)
{
ASSERT (FALSE);
@@ -449,8 +421,8 @@ LibPcdSet16S (
RETURN_STATUS
EFIAPI
LibPcdSet32S (
- IN UINTN TokenNumber,
- IN UINT32 Value
+ IN UINTN TokenNumber,
+ IN UINT32 Value
)
{
ASSERT (FALSE);
@@ -473,8 +445,8 @@ LibPcdSet32S (
RETURN_STATUS
EFIAPI
LibPcdSet64S (
- IN UINTN TokenNumber,
- IN UINT64 Value
+ IN UINTN TokenNumber,
+ IN UINT64 Value
)
{
ASSERT (FALSE);
@@ -507,9 +479,9 @@ LibPcdSet64S (
RETURN_STATUS
EFIAPI
LibPcdSetPtrS (
- IN UINTN TokenNumber,
- IN OUT UINTN *SizeOfBuffer,
- IN CONST VOID *Buffer
+ IN UINTN TokenNumber,
+ IN OUT UINTN *SizeOfBuffer,
+ IN CONST VOID *Buffer
)
{
ASSERT (FALSE);
@@ -532,8 +504,8 @@ LibPcdSetPtrS (
RETURN_STATUS
EFIAPI
LibPcdSetBoolS (
- IN UINTN TokenNumber,
- IN BOOLEAN Value
+ IN UINTN TokenNumber,
+ IN BOOLEAN Value
)
{
ASSERT (FALSE);
@@ -560,9 +532,9 @@ LibPcdSetBoolS (
RETURN_STATUS
EFIAPI
LibPcdSetEx8S (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber,
- IN UINT8 Value
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber,
+ IN UINT8 Value
)
{
ASSERT (FALSE);
@@ -589,9 +561,9 @@ LibPcdSetEx8S (
RETURN_STATUS
EFIAPI
LibPcdSetEx16S (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber,
- IN UINT16 Value
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber,
+ IN UINT16 Value
)
{
ASSERT (FALSE);
@@ -618,9 +590,9 @@ LibPcdSetEx16S (
RETURN_STATUS
EFIAPI
LibPcdSetEx32S (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber,
- IN UINT32 Value
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber,
+ IN UINT32 Value
)
{
ASSERT (FALSE);
@@ -647,9 +619,9 @@ LibPcdSetEx32S (
RETURN_STATUS
EFIAPI
LibPcdSetEx64S (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber,
- IN UINT64 Value
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber,
+ IN UINT64 Value
)
{
ASSERT (FALSE);
@@ -682,10 +654,10 @@ LibPcdSetEx64S (
RETURN_STATUS
EFIAPI
LibPcdSetExPtrS (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber,
- IN OUT UINTN *SizeOfBuffer,
- IN VOID *Buffer
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber,
+ IN OUT UINTN *SizeOfBuffer,
+ IN VOID *Buffer
)
{
ASSERT (FALSE);
@@ -712,9 +684,9 @@ LibPcdSetExPtrS (
RETURN_STATUS
EFIAPI
LibPcdSetExBoolS (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber,
- IN BOOLEAN Value
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber,
+ IN BOOLEAN Value
)
{
ASSERT (FALSE);
@@ -742,16 +714,14 @@ LibPcdSetExBoolS (
VOID
EFIAPI
LibPcdCallbackOnSet (
- IN CONST GUID *Guid, OPTIONAL
- IN UINTN TokenNumber,
- IN PCD_CALLBACK NotificationFunction
+ IN CONST GUID *Guid OPTIONAL,
+ IN UINTN TokenNumber,
+ IN PCD_CALLBACK NotificationFunction
)
{
ASSERT (FALSE);
}
-
-
/**
Disable a notification function that was established with LibPcdCallbackonSet().
@@ -769,16 +739,14 @@ LibPcdCallbackOnSet (
VOID
EFIAPI
LibPcdCancelCallback (
- IN CONST GUID *Guid, OPTIONAL
- IN UINTN TokenNumber,
- IN PCD_CALLBACK NotificationFunction
+ IN CONST GUID *Guid OPTIONAL,
+ IN UINTN TokenNumber,
+ IN PCD_CALLBACK NotificationFunction
)
{
ASSERT (FALSE);
}
-
-
/**
Retrieves the next token in a token space.
@@ -801,8 +769,8 @@ LibPcdCancelCallback (
UINTN
EFIAPI
LibPcdGetNextToken (
- IN CONST GUID *Guid, OPTIONAL
- IN UINTN TokenNumber
+ IN CONST GUID *Guid OPTIONAL,
+ IN UINTN TokenNumber
)
{
ASSERT (FALSE);
@@ -810,8 +778,6 @@ LibPcdGetNextToken (
return 0;
}
-
-
/**
Used to retrieve the list of available PCD token space GUIDs.
@@ -836,7 +802,6 @@ LibPcdGetNextTokenSpace (
return NULL;
}
-
/**
Sets a value of a patchable PCD entry that is type pointer.
@@ -863,10 +828,10 @@ LibPcdGetNextTokenSpace (
VOID *
EFIAPI
LibPatchPcdSetPtr (
- OUT VOID *PatchVariable,
- IN UINTN MaximumDatumSize,
- IN OUT UINTN *SizeOfBuffer,
- IN CONST VOID *Buffer
+ OUT VOID *PatchVariable,
+ IN UINTN MaximumDatumSize,
+ IN OUT UINTN *SizeOfBuffer,
+ IN CONST VOID *Buffer
)
{
ASSERT (PatchVariable != NULL);
@@ -877,14 +842,15 @@ LibPatchPcdSetPtr (
}
if ((*SizeOfBuffer > MaximumDatumSize) ||
- (*SizeOfBuffer == MAX_ADDRESS)) {
+ (*SizeOfBuffer == MAX_ADDRESS))
+ {
*SizeOfBuffer = MaximumDatumSize;
return NULL;
}
CopyMem (PatchVariable, Buffer, *SizeOfBuffer);
- return (VOID *) Buffer;
+ return (VOID *)Buffer;
}
/**
@@ -913,10 +879,10 @@ LibPatchPcdSetPtr (
RETURN_STATUS
EFIAPI
LibPatchPcdSetPtrS (
- OUT VOID *PatchVariable,
- IN UINTN MaximumDatumSize,
- IN OUT UINTN *SizeOfBuffer,
- IN CONST VOID *Buffer
+ OUT VOID *PatchVariable,
+ IN UINTN MaximumDatumSize,
+ IN OUT UINTN *SizeOfBuffer,
+ IN CONST VOID *Buffer
)
{
ASSERT (PatchVariable != NULL);
@@ -927,7 +893,8 @@ LibPatchPcdSetPtrS (
}
if ((*SizeOfBuffer > MaximumDatumSize) ||
- (*SizeOfBuffer == MAX_ADDRESS)) {
+ (*SizeOfBuffer == MAX_ADDRESS))
+ {
*SizeOfBuffer = MaximumDatumSize;
return RETURN_INVALID_PARAMETER;
}
@@ -965,11 +932,11 @@ LibPatchPcdSetPtrS (
VOID *
EFIAPI
LibPatchPcdSetPtrAndSize (
- OUT VOID *PatchVariable,
- OUT UINTN *SizeOfPatchVariable,
- IN UINTN MaximumDatumSize,
- IN OUT UINTN *SizeOfBuffer,
- IN CONST VOID *Buffer
+ OUT VOID *PatchVariable,
+ OUT UINTN *SizeOfPatchVariable,
+ IN UINTN MaximumDatumSize,
+ IN OUT UINTN *SizeOfBuffer,
+ IN CONST VOID *Buffer
)
{
ASSERT (PatchVariable != NULL);
@@ -981,7 +948,8 @@ LibPatchPcdSetPtrAndSize (
}
if ((*SizeOfBuffer > MaximumDatumSize) ||
- (*SizeOfBuffer == MAX_ADDRESS)) {
+ (*SizeOfBuffer == MAX_ADDRESS))
+ {
*SizeOfBuffer = MaximumDatumSize;
return NULL;
}
@@ -989,7 +957,7 @@ LibPatchPcdSetPtrAndSize (
CopyMem (PatchVariable, Buffer, *SizeOfBuffer);
*SizeOfPatchVariable = *SizeOfBuffer;
- return (VOID *) Buffer;
+ return (VOID *)Buffer;
}
/**
@@ -1020,11 +988,11 @@ LibPatchPcdSetPtrAndSize (
RETURN_STATUS
EFIAPI
LibPatchPcdSetPtrAndSizeS (
- OUT VOID *PatchVariable,
- OUT UINTN *SizeOfPatchVariable,
- IN UINTN MaximumDatumSize,
- IN OUT UINTN *SizeOfBuffer,
- IN CONST VOID *Buffer
+ OUT VOID *PatchVariable,
+ OUT UINTN *SizeOfPatchVariable,
+ IN UINTN MaximumDatumSize,
+ IN OUT UINTN *SizeOfBuffer,
+ IN CONST VOID *Buffer
)
{
ASSERT (PatchVariable != NULL);
@@ -1036,7 +1004,8 @@ LibPatchPcdSetPtrAndSizeS (
}
if ((*SizeOfBuffer > MaximumDatumSize) ||
- (*SizeOfBuffer == MAX_ADDRESS)) {
+ (*SizeOfBuffer == MAX_ADDRESS))
+ {
*SizeOfBuffer = MaximumDatumSize;
return RETURN_INVALID_PARAMETER;
}
@@ -1062,8 +1031,8 @@ LibPatchPcdSetPtrAndSizeS (
VOID
EFIAPI
LibPcdGetInfo (
- IN UINTN TokenNumber,
- OUT PCD_INFO *PcdInfo
+ IN UINTN TokenNumber,
+ OUT PCD_INFO *PcdInfo
)
{
ASSERT (FALSE);
@@ -1085,9 +1054,9 @@ LibPcdGetInfo (
VOID
EFIAPI
LibPcdGetInfoEx (
- IN CONST GUID *Guid,
- IN UINTN TokenNumber,
- OUT PCD_INFO *PcdInfo
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber,
+ OUT PCD_INFO *PcdInfo
)
{
ASSERT (FALSE);
@@ -1110,4 +1079,3 @@ LibPcdGetSku (
return 0;
}
-
diff --git a/MdePkg/Library/BasePciCf8Lib/PciCf8Lib.c b/MdePkg/Library/BasePciCf8Lib/PciCf8Lib.c
index 7d858711..49171231 100644
--- a/MdePkg/Library/BasePciCf8Lib/PciCf8Lib.c
+++ b/MdePkg/Library/BasePciCf8Lib/PciCf8Lib.c
@@ -7,7 +7,6 @@
**/
-
#include
#include
@@ -51,7 +50,7 @@
@param M Additional bits to assert to be zero.
**/
-#define ASSERT_INVALID_PCI_ADDRESS(A,M) \
+#define ASSERT_INVALID_PCI_ADDRESS(A, M) \
ASSERT (((A) & (~0xffff0ff | (M))) == 0)
/**
@@ -105,7 +104,7 @@ PciCf8RegisterForRuntimeAccess (
UINT8
EFIAPI
PciCf8Read8 (
- IN UINTN Address
+ IN UINTN Address
)
{
BOOLEAN InterruptState;
@@ -114,7 +113,7 @@ PciCf8Read8 (
ASSERT_INVALID_PCI_ADDRESS (Address, 0);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoRead8 (PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3));
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
@@ -142,8 +141,8 @@ PciCf8Read8 (
UINT8
EFIAPI
PciCf8Write8 (
- IN UINTN Address,
- IN UINT8 Value
+ IN UINTN Address,
+ IN UINT8 Value
)
{
BOOLEAN InterruptState;
@@ -152,7 +151,7 @@ PciCf8Write8 (
ASSERT_INVALID_PCI_ADDRESS (Address, 0);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoWrite8 (
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
@@ -187,8 +186,8 @@ PciCf8Write8 (
UINT8
EFIAPI
PciCf8Or8 (
- IN UINTN Address,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINT8 OrData
)
{
BOOLEAN InterruptState;
@@ -197,7 +196,7 @@ PciCf8Or8 (
ASSERT_INVALID_PCI_ADDRESS (Address, 0);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoOr8 (
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
@@ -232,8 +231,8 @@ PciCf8Or8 (
UINT8
EFIAPI
PciCf8And8 (
- IN UINTN Address,
- IN UINT8 AndData
+ IN UINTN Address,
+ IN UINT8 AndData
)
{
BOOLEAN InterruptState;
@@ -242,7 +241,7 @@ PciCf8And8 (
ASSERT_INVALID_PCI_ADDRESS (Address, 0);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoAnd8 (
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
@@ -279,9 +278,9 @@ PciCf8And8 (
UINT8
EFIAPI
PciCf8AndThenOr8 (
- IN UINTN Address,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
)
{
BOOLEAN InterruptState;
@@ -290,7 +289,7 @@ PciCf8AndThenOr8 (
ASSERT_INVALID_PCI_ADDRESS (Address, 0);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoAndThenOr8 (
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
@@ -327,9 +326,9 @@ PciCf8AndThenOr8 (
UINT8
EFIAPI
PciCf8BitFieldRead8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
BOOLEAN InterruptState;
@@ -338,7 +337,7 @@ PciCf8BitFieldRead8 (
ASSERT_INVALID_PCI_ADDRESS (Address, 0);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoBitFieldRead8 (
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
@@ -378,10 +377,10 @@ PciCf8BitFieldRead8 (
UINT8
EFIAPI
PciCf8BitFieldWrite8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
)
{
BOOLEAN InterruptState;
@@ -390,7 +389,7 @@ PciCf8BitFieldWrite8 (
ASSERT_INVALID_PCI_ADDRESS (Address, 0);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoBitFieldWrite8 (
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
@@ -434,10 +433,10 @@ PciCf8BitFieldWrite8 (
UINT8
EFIAPI
PciCf8BitFieldOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
)
{
BOOLEAN InterruptState;
@@ -446,7 +445,7 @@ PciCf8BitFieldOr8 (
ASSERT_INVALID_PCI_ADDRESS (Address, 0);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoBitFieldOr8 (
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
@@ -490,10 +489,10 @@ PciCf8BitFieldOr8 (
UINT8
EFIAPI
PciCf8BitFieldAnd8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
)
{
BOOLEAN InterruptState;
@@ -502,7 +501,7 @@ PciCf8BitFieldAnd8 (
ASSERT_INVALID_PCI_ADDRESS (Address, 0);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoBitFieldAnd8 (
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
@@ -549,12 +548,12 @@ PciCf8BitFieldAnd8 (
**/
UINT8
EFIAPI
-PciCf8BitFieldAndThenOr8(
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData,
- IN UINT8 OrData
+PciCf8BitFieldAndThenOr8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
)
{
BOOLEAN InterruptState;
@@ -563,7 +562,7 @@ PciCf8BitFieldAndThenOr8(
ASSERT_INVALID_PCI_ADDRESS (Address, 0);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoBitFieldAndThenOr8 (
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
@@ -597,7 +596,7 @@ PciCf8BitFieldAndThenOr8(
UINT16
EFIAPI
PciCf8Read16 (
- IN UINTN Address
+ IN UINTN Address
)
{
BOOLEAN InterruptState;
@@ -606,7 +605,7 @@ PciCf8Read16 (
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoRead16 (PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2));
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
@@ -635,8 +634,8 @@ PciCf8Read16 (
UINT16
EFIAPI
PciCf8Write16 (
- IN UINTN Address,
- IN UINT16 Value
+ IN UINTN Address,
+ IN UINT16 Value
)
{
BOOLEAN InterruptState;
@@ -645,7 +644,7 @@ PciCf8Write16 (
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoWrite16 (
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
@@ -681,8 +680,8 @@ PciCf8Write16 (
UINT16
EFIAPI
PciCf8Or16 (
- IN UINTN Address,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINT16 OrData
)
{
BOOLEAN InterruptState;
@@ -691,7 +690,7 @@ PciCf8Or16 (
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoOr16 (
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
@@ -727,8 +726,8 @@ PciCf8Or16 (
UINT16
EFIAPI
PciCf8And16 (
- IN UINTN Address,
- IN UINT16 AndData
+ IN UINTN Address,
+ IN UINT16 AndData
)
{
BOOLEAN InterruptState;
@@ -737,7 +736,7 @@ PciCf8And16 (
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoAnd16 (
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
@@ -775,9 +774,9 @@ PciCf8And16 (
UINT16
EFIAPI
PciCf8AndThenOr16 (
- IN UINTN Address,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
)
{
BOOLEAN InterruptState;
@@ -786,7 +785,7 @@ PciCf8AndThenOr16 (
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoAndThenOr16 (
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
@@ -824,9 +823,9 @@ PciCf8AndThenOr16 (
UINT16
EFIAPI
PciCf8BitFieldRead16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
BOOLEAN InterruptState;
@@ -835,7 +834,7 @@ PciCf8BitFieldRead16 (
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoBitFieldRead16 (
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
@@ -876,10 +875,10 @@ PciCf8BitFieldRead16 (
UINT16
EFIAPI
PciCf8BitFieldWrite16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
)
{
BOOLEAN InterruptState;
@@ -888,7 +887,7 @@ PciCf8BitFieldWrite16 (
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoBitFieldWrite16 (
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
@@ -933,10 +932,10 @@ PciCf8BitFieldWrite16 (
UINT16
EFIAPI
PciCf8BitFieldOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
)
{
BOOLEAN InterruptState;
@@ -945,7 +944,7 @@ PciCf8BitFieldOr16 (
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoBitFieldOr16 (
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
@@ -990,10 +989,10 @@ PciCf8BitFieldOr16 (
UINT16
EFIAPI
PciCf8BitFieldAnd16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
)
{
BOOLEAN InterruptState;
@@ -1002,7 +1001,7 @@ PciCf8BitFieldAnd16 (
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoBitFieldAnd16 (
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
@@ -1050,12 +1049,12 @@ PciCf8BitFieldAnd16 (
**/
UINT16
EFIAPI
-PciCf8BitFieldAndThenOr16(
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData,
- IN UINT16 OrData
+PciCf8BitFieldAndThenOr16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
)
{
BOOLEAN InterruptState;
@@ -1064,7 +1063,7 @@ PciCf8BitFieldAndThenOr16(
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoBitFieldAndThenOr16 (
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
@@ -1098,7 +1097,7 @@ PciCf8BitFieldAndThenOr16(
UINT32
EFIAPI
PciCf8Read32 (
- IN UINTN Address
+ IN UINTN Address
)
{
BOOLEAN InterruptState;
@@ -1107,7 +1106,7 @@ PciCf8Read32 (
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoRead32 (PCI_CONFIGURATION_DATA_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
@@ -1136,8 +1135,8 @@ PciCf8Read32 (
UINT32
EFIAPI
PciCf8Write32 (
- IN UINTN Address,
- IN UINT32 Value
+ IN UINTN Address,
+ IN UINT32 Value
)
{
BOOLEAN InterruptState;
@@ -1146,7 +1145,7 @@ PciCf8Write32 (
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoWrite32 (
PCI_CONFIGURATION_DATA_PORT,
@@ -1182,8 +1181,8 @@ PciCf8Write32 (
UINT32
EFIAPI
PciCf8Or32 (
- IN UINTN Address,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINT32 OrData
)
{
BOOLEAN InterruptState;
@@ -1192,7 +1191,7 @@ PciCf8Or32 (
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoOr32 (
PCI_CONFIGURATION_DATA_PORT,
@@ -1228,8 +1227,8 @@ PciCf8Or32 (
UINT32
EFIAPI
PciCf8And32 (
- IN UINTN Address,
- IN UINT32 AndData
+ IN UINTN Address,
+ IN UINT32 AndData
)
{
BOOLEAN InterruptState;
@@ -1238,7 +1237,7 @@ PciCf8And32 (
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoAnd32 (
PCI_CONFIGURATION_DATA_PORT,
@@ -1276,9 +1275,9 @@ PciCf8And32 (
UINT32
EFIAPI
PciCf8AndThenOr32 (
- IN UINTN Address,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
)
{
BOOLEAN InterruptState;
@@ -1287,7 +1286,7 @@ PciCf8AndThenOr32 (
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoAndThenOr32 (
PCI_CONFIGURATION_DATA_PORT,
@@ -1325,9 +1324,9 @@ PciCf8AndThenOr32 (
UINT32
EFIAPI
PciCf8BitFieldRead32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
BOOLEAN InterruptState;
@@ -1336,7 +1335,7 @@ PciCf8BitFieldRead32 (
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoBitFieldRead32 (
PCI_CONFIGURATION_DATA_PORT,
@@ -1377,10 +1376,10 @@ PciCf8BitFieldRead32 (
UINT32
EFIAPI
PciCf8BitFieldWrite32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
)
{
BOOLEAN InterruptState;
@@ -1389,7 +1388,7 @@ PciCf8BitFieldWrite32 (
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoBitFieldWrite32 (
PCI_CONFIGURATION_DATA_PORT,
@@ -1434,10 +1433,10 @@ PciCf8BitFieldWrite32 (
UINT32
EFIAPI
PciCf8BitFieldOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
)
{
BOOLEAN InterruptState;
@@ -1446,7 +1445,7 @@ PciCf8BitFieldOr32 (
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoBitFieldOr32 (
PCI_CONFIGURATION_DATA_PORT,
@@ -1491,10 +1490,10 @@ PciCf8BitFieldOr32 (
UINT32
EFIAPI
PciCf8BitFieldAnd32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
)
{
BOOLEAN InterruptState;
@@ -1503,7 +1502,7 @@ PciCf8BitFieldAnd32 (
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoBitFieldAnd32 (
PCI_CONFIGURATION_DATA_PORT,
@@ -1551,12 +1550,12 @@ PciCf8BitFieldAnd32 (
**/
UINT32
EFIAPI
-PciCf8BitFieldAndThenOr32(
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
+PciCf8BitFieldAndThenOr32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
)
{
BOOLEAN InterruptState;
@@ -1565,15 +1564,15 @@ PciCf8BitFieldAndThenOr32(
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
InterruptState = SaveAndDisableInterrupts ();
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
Result = IoBitFieldAndThenOr32 (
- PCI_CONFIGURATION_DATA_PORT,
- StartBit,
- EndBit,
- AndData,
- OrData
- );
+ PCI_CONFIGURATION_DATA_PORT,
+ StartBit,
+ EndBit,
+ AndData,
+ OrData
+ );
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
SetInterruptState (InterruptState);
return Result;
@@ -1606,12 +1605,12 @@ PciCf8BitFieldAndThenOr32(
UINTN
EFIAPI
PciCf8ReadBuffer (
- IN UINTN StartAddress,
- IN UINTN Size,
- OUT VOID *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
)
{
- UINTN ReturnValue;
+ UINTN ReturnValue;
ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);
@@ -1632,40 +1631,40 @@ PciCf8ReadBuffer (
// Read a byte if StartAddress is byte aligned
//
*(volatile UINT8 *)Buffer = PciCf8Read8 (StartAddress);
- StartAddress += sizeof (UINT8);
- Size -= sizeof (UINT8);
- Buffer = (UINT8*)Buffer + 1;
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8 *)Buffer + 1;
}
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {
//
// Read a word if StartAddress is word aligned
//
- WriteUnaligned16 ((UINT16 *)Buffer, (UINT16) PciCf8Read16 (StartAddress));
+ WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciCf8Read16 (StartAddress));
StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
}
while (Size >= sizeof (UINT32)) {
//
// Read as many double words as possible
//
- WriteUnaligned32 ((UINT32 *)Buffer, (UINT32) PciCf8Read32 (StartAddress));
+ WriteUnaligned32 ((UINT32 *)Buffer, (UINT32)PciCf8Read32 (StartAddress));
StartAddress += sizeof (UINT32);
- Size -= sizeof (UINT32);
- Buffer = (UINT32*)Buffer + 1;
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32 *)Buffer + 1;
}
if (Size >= sizeof (UINT16)) {
//
// Read the last remaining word if exist
//
- WriteUnaligned16 ((UINT16 *)Buffer, (UINT16) PciCf8Read16 (StartAddress));
+ WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciCf8Read16 (StartAddress));
StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
}
if (Size >= sizeof (UINT8)) {
@@ -1706,12 +1705,12 @@ PciCf8ReadBuffer (
UINTN
EFIAPI
PciCf8WriteBuffer (
- IN UINTN StartAddress,
- IN UINTN Size,
- IN VOID *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
)
{
- UINTN ReturnValue;
+ UINTN ReturnValue;
ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);
@@ -1731,47 +1730,47 @@ PciCf8WriteBuffer (
//
// Write a byte if StartAddress is byte aligned
//
- PciCf8Write8 (StartAddress, *(UINT8*)Buffer);
+ PciCf8Write8 (StartAddress, *(UINT8 *)Buffer);
StartAddress += sizeof (UINT8);
- Size -= sizeof (UINT8);
- Buffer = (UINT8*)Buffer + 1;
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8 *)Buffer + 1;
}
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {
//
// Write a word if StartAddress is word aligned
//
- PciCf8Write16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));
+ PciCf8Write16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));
StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
}
while (Size >= sizeof (UINT32)) {
//
// Write as many double words as possible
//
- PciCf8Write32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));
+ PciCf8Write32 (StartAddress, ReadUnaligned32 ((UINT32 *)Buffer));
StartAddress += sizeof (UINT32);
- Size -= sizeof (UINT32);
- Buffer = (UINT32*)Buffer + 1;
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32 *)Buffer + 1;
}
if (Size >= sizeof (UINT16)) {
//
// Write the last remaining word if exist
//
- PciCf8Write16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));
+ PciCf8Write16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));
StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
}
if (Size >= sizeof (UINT8)) {
//
// Write the last remaining byte if exist
//
- PciCf8Write8 (StartAddress, *(UINT8*)Buffer);
+ PciCf8Write8 (StartAddress, *(UINT8 *)Buffer);
}
return ReturnValue;
diff --git a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c b/MdePkg/Library/BasePciExpressLib/PciExpressLib.c
index 5ad349b8..bc2ac9b9 100644
--- a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c
+++ b/MdePkg/Library/BasePciExpressLib/PciExpressLib.c
@@ -10,7 +10,6 @@
**/
-
#include
#include
@@ -19,7 +18,6 @@
#include
#include
-
/**
Assert the validity of a PCI address. A valid PCI address should contain 1's
only in the low 28 bits. PcdPciExpressBaseSize limits the size to the real
@@ -72,12 +70,12 @@ PciExpressRegisterForRuntimeAccess (
@return The base address of PCI Express.
**/
-VOID*
+VOID *
GetPciExpressBaseAddress (
VOID
)
{
- return (VOID*)(UINTN) PcdGet64 (PcdPciExpressBaseAddress);
+ return (VOID *)(UINTN)PcdGet64 (PcdPciExpressBaseAddress);
}
/**
@@ -95,7 +93,7 @@ PcdPciExpressBaseSize (
VOID
)
{
- return (UINTN) PcdGet64 (PcdPciExpressBaseSize);
+ return (UINTN)PcdGet64 (PcdPciExpressBaseSize);
}
/**
@@ -117,14 +115,15 @@ PcdPciExpressBaseSize (
UINT8
EFIAPI
PciExpressRead8 (
- IN UINTN Address
+ IN UINTN Address
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT8) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT8)-1;
}
- return MmioRead8 ((UINTN) GetPciExpressBaseAddress () + Address);
+
+ return MmioRead8 ((UINTN)GetPciExpressBaseAddress () + Address);
}
/**
@@ -147,15 +146,16 @@ PciExpressRead8 (
UINT8
EFIAPI
PciExpressWrite8 (
- IN UINTN Address,
- IN UINT8 Value
+ IN UINTN Address,
+ IN UINT8 Value
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT8) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT8)-1;
}
- return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Address, Value);
+
+ return MmioWrite8 ((UINTN)GetPciExpressBaseAddress () + Address, Value);
}
/**
@@ -182,15 +182,16 @@ PciExpressWrite8 (
UINT8
EFIAPI
PciExpressOr8 (
- IN UINTN Address,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINT8 OrData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT8) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT8)-1;
}
- return MmioOr8 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);
+
+ return MmioOr8 ((UINTN)GetPciExpressBaseAddress () + Address, OrData);
}
/**
@@ -217,15 +218,16 @@ PciExpressOr8 (
UINT8
EFIAPI
PciExpressAnd8 (
- IN UINTN Address,
- IN UINT8 AndData
+ IN UINTN Address,
+ IN UINT8 AndData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT8) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT8)-1;
}
- return MmioAnd8 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);
+
+ return MmioAnd8 ((UINTN)GetPciExpressBaseAddress () + Address, AndData);
}
/**
@@ -254,17 +256,18 @@ PciExpressAnd8 (
UINT8
EFIAPI
PciExpressAndThenOr8 (
- IN UINTN Address,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT8) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT8)-1;
}
+
return MmioAndThenOr8 (
- (UINTN) GetPciExpressBaseAddress () + Address,
+ (UINTN)GetPciExpressBaseAddress () + Address,
AndData,
OrData
);
@@ -296,17 +299,18 @@ PciExpressAndThenOr8 (
UINT8
EFIAPI
PciExpressBitFieldRead8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT8) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT8)-1;
}
+
return MmioBitFieldRead8 (
- (UINTN) GetPciExpressBaseAddress () + Address,
+ (UINTN)GetPciExpressBaseAddress () + Address,
StartBit,
EndBit
);
@@ -340,18 +344,19 @@ PciExpressBitFieldRead8 (
UINT8
EFIAPI
PciExpressBitFieldWrite8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT8) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT8)-1;
}
+
return MmioBitFieldWrite8 (
- (UINTN) GetPciExpressBaseAddress () + Address,
+ (UINTN)GetPciExpressBaseAddress () + Address,
StartBit,
EndBit,
Value
@@ -389,18 +394,19 @@ PciExpressBitFieldWrite8 (
UINT8
EFIAPI
PciExpressBitFieldOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT8) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT8)-1;
}
+
return MmioBitFieldOr8 (
- (UINTN) GetPciExpressBaseAddress () + Address,
+ (UINTN)GetPciExpressBaseAddress () + Address,
StartBit,
EndBit,
OrData
@@ -438,18 +444,19 @@ PciExpressBitFieldOr8 (
UINT8
EFIAPI
PciExpressBitFieldAnd8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT8) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT8)-1;
}
+
return MmioBitFieldAnd8 (
- (UINTN) GetPciExpressBaseAddress () + Address,
+ (UINTN)GetPciExpressBaseAddress () + Address,
StartBit,
EndBit,
AndData
@@ -491,19 +498,20 @@ PciExpressBitFieldAnd8 (
UINT8
EFIAPI
PciExpressBitFieldAndThenOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT8) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT8)-1;
}
+
return MmioBitFieldAndThenOr8 (
- (UINTN) GetPciExpressBaseAddress () + Address,
+ (UINTN)GetPciExpressBaseAddress () + Address,
StartBit,
EndBit,
AndData,
@@ -531,14 +539,15 @@ PciExpressBitFieldAndThenOr8 (
UINT16
EFIAPI
PciExpressRead16 (
- IN UINTN Address
+ IN UINTN Address
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT16) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT16)-1;
}
- return MmioRead16 ((UINTN) GetPciExpressBaseAddress () + Address);
+
+ return MmioRead16 ((UINTN)GetPciExpressBaseAddress () + Address);
}
/**
@@ -562,15 +571,16 @@ PciExpressRead16 (
UINT16
EFIAPI
PciExpressWrite16 (
- IN UINTN Address,
- IN UINT16 Value
+ IN UINTN Address,
+ IN UINT16 Value
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT16) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT16)-1;
}
- return MmioWrite16 ((UINTN) GetPciExpressBaseAddress () + Address, Value);
+
+ return MmioWrite16 ((UINTN)GetPciExpressBaseAddress () + Address, Value);
}
/**
@@ -598,15 +608,16 @@ PciExpressWrite16 (
UINT16
EFIAPI
PciExpressOr16 (
- IN UINTN Address,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINT16 OrData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT16) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT16)-1;
}
- return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);
+
+ return MmioOr16 ((UINTN)GetPciExpressBaseAddress () + Address, OrData);
}
/**
@@ -634,15 +645,16 @@ PciExpressOr16 (
UINT16
EFIAPI
PciExpressAnd16 (
- IN UINTN Address,
- IN UINT16 AndData
+ IN UINTN Address,
+ IN UINT16 AndData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT16) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT16)-1;
}
- return MmioAnd16 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);
+
+ return MmioAnd16 ((UINTN)GetPciExpressBaseAddress () + Address, AndData);
}
/**
@@ -672,17 +684,18 @@ PciExpressAnd16 (
UINT16
EFIAPI
PciExpressAndThenOr16 (
- IN UINTN Address,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT16) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT16)-1;
}
+
return MmioAndThenOr16 (
- (UINTN) GetPciExpressBaseAddress () + Address,
+ (UINTN)GetPciExpressBaseAddress () + Address,
AndData,
OrData
);
@@ -715,17 +728,18 @@ PciExpressAndThenOr16 (
UINT16
EFIAPI
PciExpressBitFieldRead16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT16) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT16)-1;
}
+
return MmioBitFieldRead16 (
- (UINTN) GetPciExpressBaseAddress () + Address,
+ (UINTN)GetPciExpressBaseAddress () + Address,
StartBit,
EndBit
);
@@ -760,18 +774,19 @@ PciExpressBitFieldRead16 (
UINT16
EFIAPI
PciExpressBitFieldWrite16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT16) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT16)-1;
}
+
return MmioBitFieldWrite16 (
- (UINTN) GetPciExpressBaseAddress () + Address,
+ (UINTN)GetPciExpressBaseAddress () + Address,
StartBit,
EndBit,
Value
@@ -810,18 +825,19 @@ PciExpressBitFieldWrite16 (
UINT16
EFIAPI
PciExpressBitFieldOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT16) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT16)-1;
}
+
return MmioBitFieldOr16 (
- (UINTN) GetPciExpressBaseAddress () + Address,
+ (UINTN)GetPciExpressBaseAddress () + Address,
StartBit,
EndBit,
OrData
@@ -860,18 +876,19 @@ PciExpressBitFieldOr16 (
UINT16
EFIAPI
PciExpressBitFieldAnd16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT16) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT16)-1;
}
+
return MmioBitFieldAnd16 (
- (UINTN) GetPciExpressBaseAddress () + Address,
+ (UINTN)GetPciExpressBaseAddress () + Address,
StartBit,
EndBit,
AndData
@@ -914,19 +931,20 @@ PciExpressBitFieldAnd16 (
UINT16
EFIAPI
PciExpressBitFieldAndThenOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT16) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT16)-1;
}
+
return MmioBitFieldAndThenOr16 (
- (UINTN) GetPciExpressBaseAddress () + Address,
+ (UINTN)GetPciExpressBaseAddress () + Address,
StartBit,
EndBit,
AndData,
@@ -954,14 +972,15 @@ PciExpressBitFieldAndThenOr16 (
UINT32
EFIAPI
PciExpressRead32 (
- IN UINTN Address
+ IN UINTN Address
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT32) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT32)-1;
}
- return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Address);
+
+ return MmioRead32 ((UINTN)GetPciExpressBaseAddress () + Address);
}
/**
@@ -985,15 +1004,16 @@ PciExpressRead32 (
UINT32
EFIAPI
PciExpressWrite32 (
- IN UINTN Address,
- IN UINT32 Value
+ IN UINTN Address,
+ IN UINT32 Value
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT32) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT32)-1;
}
- return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, Value);
+
+ return MmioWrite32 ((UINTN)GetPciExpressBaseAddress () + Address, Value);
}
/**
@@ -1021,15 +1041,16 @@ PciExpressWrite32 (
UINT32
EFIAPI
PciExpressOr32 (
- IN UINTN Address,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINT32 OrData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT32) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT32)-1;
}
- return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);
+
+ return MmioOr32 ((UINTN)GetPciExpressBaseAddress () + Address, OrData);
}
/**
@@ -1057,15 +1078,16 @@ PciExpressOr32 (
UINT32
EFIAPI
PciExpressAnd32 (
- IN UINTN Address,
- IN UINT32 AndData
+ IN UINTN Address,
+ IN UINT32 AndData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT32) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT32)-1;
}
- return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);
+
+ return MmioAnd32 ((UINTN)GetPciExpressBaseAddress () + Address, AndData);
}
/**
@@ -1095,17 +1117,18 @@ PciExpressAnd32 (
UINT32
EFIAPI
PciExpressAndThenOr32 (
- IN UINTN Address,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT32) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT32)-1;
}
+
return MmioAndThenOr32 (
- (UINTN) GetPciExpressBaseAddress () + Address,
+ (UINTN)GetPciExpressBaseAddress () + Address,
AndData,
OrData
);
@@ -1138,17 +1161,18 @@ PciExpressAndThenOr32 (
UINT32
EFIAPI
PciExpressBitFieldRead32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT32) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT32)-1;
}
+
return MmioBitFieldRead32 (
- (UINTN) GetPciExpressBaseAddress () + Address,
+ (UINTN)GetPciExpressBaseAddress () + Address,
StartBit,
EndBit
);
@@ -1183,18 +1207,19 @@ PciExpressBitFieldRead32 (
UINT32
EFIAPI
PciExpressBitFieldWrite32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT32) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT32)-1;
}
+
return MmioBitFieldWrite32 (
- (UINTN) GetPciExpressBaseAddress () + Address,
+ (UINTN)GetPciExpressBaseAddress () + Address,
StartBit,
EndBit,
Value
@@ -1233,18 +1258,19 @@ PciExpressBitFieldWrite32 (
UINT32
EFIAPI
PciExpressBitFieldOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT32) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT32)-1;
}
+
return MmioBitFieldOr32 (
- (UINTN) GetPciExpressBaseAddress () + Address,
+ (UINTN)GetPciExpressBaseAddress () + Address,
StartBit,
EndBit,
OrData
@@ -1283,18 +1309,19 @@ PciExpressBitFieldOr32 (
UINT32
EFIAPI
PciExpressBitFieldAnd32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT32) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT32)-1;
}
+
return MmioBitFieldAnd32 (
- (UINTN) GetPciExpressBaseAddress () + Address,
+ (UINTN)GetPciExpressBaseAddress () + Address,
StartBit,
EndBit,
AndData
@@ -1337,19 +1364,20 @@ PciExpressBitFieldAnd32 (
UINT32
EFIAPI
PciExpressBitFieldAndThenOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
- if (Address >= PcdPciExpressBaseSize()) {
- return (UINT32) -1;
+ if (Address >= PcdPciExpressBaseSize ()) {
+ return (UINT32)-1;
}
+
return MmioBitFieldAndThenOr32 (
- (UINTN) GetPciExpressBaseAddress () + Address,
+ (UINTN)GetPciExpressBaseAddress () + Address,
StartBit,
EndBit,
AndData,
@@ -1384,17 +1412,18 @@ PciExpressBitFieldAndThenOr32 (
UINTN
EFIAPI
PciExpressReadBuffer (
- IN UINTN StartAddress,
- IN UINTN Size,
- OUT VOID *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
)
{
- UINTN ReturnValue;
+ UINTN ReturnValue;
ASSERT_INVALID_PCI_ADDRESS (StartAddress);
- if (StartAddress >= PcdPciExpressBaseSize()) {
- return (UINTN) -1;
+ if (StartAddress >= PcdPciExpressBaseSize ()) {
+ return (UINTN)-1;
}
+
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
if (Size == 0) {
@@ -1413,41 +1442,41 @@ PciExpressReadBuffer (
// Read a byte if StartAddress is byte aligned
//
*(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
- StartAddress += sizeof (UINT8);
- Size -= sizeof (UINT8);
- Buffer = (UINT8*)Buffer + 1;
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8 *)Buffer + 1;
}
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {
//
// Read a word if StartAddress is word aligned
//
- WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));
+ WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAddress));
StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
}
while (Size >= sizeof (UINT32)) {
//
// Read as many double words as possible
//
- WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));
+ WriteUnaligned32 ((UINT32 *)Buffer, (UINT32)PciExpressRead32 (StartAddress));
StartAddress += sizeof (UINT32);
- Size -= sizeof (UINT32);
- Buffer = (UINT32*)Buffer + 1;
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32 *)Buffer + 1;
}
if (Size >= sizeof (UINT16)) {
//
// Read the last remaining word if exist
//
- WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));
+ WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAddress));
StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
}
if (Size >= sizeof (UINT8)) {
@@ -1488,17 +1517,18 @@ PciExpressReadBuffer (
UINTN
EFIAPI
PciExpressWriteBuffer (
- IN UINTN StartAddress,
- IN UINTN Size,
- IN VOID *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
)
{
- UINTN ReturnValue;
+ UINTN ReturnValue;
ASSERT_INVALID_PCI_ADDRESS (StartAddress);
- if (StartAddress >= PcdPciExpressBaseSize()) {
- return (UINTN) -1;
+ if (StartAddress >= PcdPciExpressBaseSize ()) {
+ return (UINTN)-1;
}
+
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
if (Size == 0) {
@@ -1516,47 +1546,47 @@ PciExpressWriteBuffer (
//
// Write a byte if StartAddress is byte aligned
//
- PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
+ PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer);
StartAddress += sizeof (UINT8);
- Size -= sizeof (UINT8);
- Buffer = (UINT8*)Buffer + 1;
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8 *)Buffer + 1;
}
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {
//
// Write a word if StartAddress is word aligned
//
- PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));
+ PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));
StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
}
while (Size >= sizeof (UINT32)) {
//
// Write as many double words as possible
//
- PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));
+ PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32 *)Buffer));
StartAddress += sizeof (UINT32);
- Size -= sizeof (UINT32);
- Buffer = (UINT32*)Buffer + 1;
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32 *)Buffer + 1;
}
if (Size >= sizeof (UINT16)) {
//
// Write the last remaining word if exist
//
- PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));
+ PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));
StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
}
if (Size >= sizeof (UINT8)) {
//
// Write the last remaining byte if exist
//
- PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
+ PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer);
}
return ReturnValue;
diff --git a/MdePkg/Library/BasePciLibPciExpress/PciLib.c b/MdePkg/Library/BasePciLibPciExpress/PciLib.c
index 0b49d710..83c953b9 100644
--- a/MdePkg/Library/BasePciLibPciExpress/PciLib.c
+++ b/MdePkg/Library/BasePciLibPciExpress/PciLib.c
@@ -7,7 +7,6 @@
**/
-
#include
#include
@@ -61,7 +60,7 @@ PciRegisterForRuntimeAccess (
UINT8
EFIAPI
PciRead8 (
- IN UINTN Address
+ IN UINTN Address
)
{
return PciExpressRead8 (Address);
@@ -86,8 +85,8 @@ PciRead8 (
UINT8
EFIAPI
PciWrite8 (
- IN UINTN Address,
- IN UINT8 Value
+ IN UINTN Address,
+ IN UINT8 Value
)
{
return PciExpressWrite8 (Address, Value);
@@ -116,8 +115,8 @@ PciWrite8 (
UINT8
EFIAPI
PciOr8 (
- IN UINTN Address,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINT8 OrData
)
{
return PciExpressOr8 (Address, OrData);
@@ -146,8 +145,8 @@ PciOr8 (
UINT8
EFIAPI
PciAnd8 (
- IN UINTN Address,
- IN UINT8 AndData
+ IN UINTN Address,
+ IN UINT8 AndData
)
{
return PciExpressAnd8 (Address, AndData);
@@ -178,9 +177,9 @@ PciAnd8 (
UINT8
EFIAPI
PciAndThenOr8 (
- IN UINTN Address,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
)
{
return PciExpressAndThenOr8 (Address, AndData, OrData);
@@ -210,9 +209,9 @@ PciAndThenOr8 (
UINT8
EFIAPI
PciBitFieldRead8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
return PciExpressBitFieldRead8 (Address, StartBit, EndBit);
@@ -245,10 +244,10 @@ PciBitFieldRead8 (
UINT8
EFIAPI
PciBitFieldWrite8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
)
{
return PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value);
@@ -284,10 +283,10 @@ PciBitFieldWrite8 (
UINT8
EFIAPI
PciBitFieldOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
)
{
return PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData);
@@ -323,10 +322,10 @@ PciBitFieldOr8 (
UINT8
EFIAPI
PciBitFieldAnd8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
)
{
return PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData);
@@ -366,11 +365,11 @@ PciBitFieldAnd8 (
UINT8
EFIAPI
PciBitFieldAndThenOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
)
{
return PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData);
@@ -395,7 +394,7 @@ PciBitFieldAndThenOr8 (
UINT16
EFIAPI
PciRead16 (
- IN UINTN Address
+ IN UINTN Address
)
{
return PciExpressRead16 (Address);
@@ -421,8 +420,8 @@ PciRead16 (
UINT16
EFIAPI
PciWrite16 (
- IN UINTN Address,
- IN UINT16 Value
+ IN UINTN Address,
+ IN UINT16 Value
)
{
return PciExpressWrite16 (Address, Value);
@@ -452,8 +451,8 @@ PciWrite16 (
UINT16
EFIAPI
PciOr16 (
- IN UINTN Address,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINT16 OrData
)
{
return PciExpressOr16 (Address, OrData);
@@ -483,8 +482,8 @@ PciOr16 (
UINT16
EFIAPI
PciAnd16 (
- IN UINTN Address,
- IN UINT16 AndData
+ IN UINTN Address,
+ IN UINT16 AndData
)
{
return PciExpressAnd16 (Address, AndData);
@@ -516,9 +515,9 @@ PciAnd16 (
UINT16
EFIAPI
PciAndThenOr16 (
- IN UINTN Address,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
)
{
return PciExpressAndThenOr16 (Address, AndData, OrData);
@@ -549,9 +548,9 @@ PciAndThenOr16 (
UINT16
EFIAPI
PciBitFieldRead16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
return PciExpressBitFieldRead16 (Address, StartBit, EndBit);
@@ -585,10 +584,10 @@ PciBitFieldRead16 (
UINT16
EFIAPI
PciBitFieldWrite16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
)
{
return PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value);
@@ -625,10 +624,10 @@ PciBitFieldWrite16 (
UINT16
EFIAPI
PciBitFieldOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
)
{
return PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData);
@@ -665,10 +664,10 @@ PciBitFieldOr16 (
UINT16
EFIAPI
PciBitFieldAnd16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
)
{
return PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData);
@@ -709,11 +708,11 @@ PciBitFieldAnd16 (
UINT16
EFIAPI
PciBitFieldAndThenOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
)
{
return PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);
@@ -738,7 +737,7 @@ PciBitFieldAndThenOr16 (
UINT32
EFIAPI
PciRead32 (
- IN UINTN Address
+ IN UINTN Address
)
{
return PciExpressRead32 (Address);
@@ -764,8 +763,8 @@ PciRead32 (
UINT32
EFIAPI
PciWrite32 (
- IN UINTN Address,
- IN UINT32 Value
+ IN UINTN Address,
+ IN UINT32 Value
)
{
return PciExpressWrite32 (Address, Value);
@@ -795,8 +794,8 @@ PciWrite32 (
UINT32
EFIAPI
PciOr32 (
- IN UINTN Address,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINT32 OrData
)
{
return PciExpressOr32 (Address, OrData);
@@ -826,8 +825,8 @@ PciOr32 (
UINT32
EFIAPI
PciAnd32 (
- IN UINTN Address,
- IN UINT32 AndData
+ IN UINTN Address,
+ IN UINT32 AndData
)
{
return PciExpressAnd32 (Address, AndData);
@@ -859,9 +858,9 @@ PciAnd32 (
UINT32
EFIAPI
PciAndThenOr32 (
- IN UINTN Address,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
)
{
return PciExpressAndThenOr32 (Address, AndData, OrData);
@@ -892,9 +891,9 @@ PciAndThenOr32 (
UINT32
EFIAPI
PciBitFieldRead32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
return PciExpressBitFieldRead32 (Address, StartBit, EndBit);
@@ -928,10 +927,10 @@ PciBitFieldRead32 (
UINT32
EFIAPI
PciBitFieldWrite32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
)
{
return PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value);
@@ -968,10 +967,10 @@ PciBitFieldWrite32 (
UINT32
EFIAPI
PciBitFieldOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
)
{
return PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData);
@@ -1008,10 +1007,10 @@ PciBitFieldOr32 (
UINT32
EFIAPI
PciBitFieldAnd32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
)
{
return PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData);
@@ -1052,11 +1051,11 @@ PciBitFieldAnd32 (
UINT32
EFIAPI
PciBitFieldAndThenOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
)
{
return PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData);
@@ -1088,9 +1087,9 @@ PciBitFieldAndThenOr32 (
UINTN
EFIAPI
PciReadBuffer (
- IN UINTN StartAddress,
- IN UINTN Size,
- OUT VOID *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
)
{
return PciExpressReadBuffer (StartAddress, Size, Buffer);
@@ -1123,9 +1122,9 @@ PciReadBuffer (
UINTN
EFIAPI
PciWriteBuffer (
- IN UINTN StartAddress,
- IN UINTN Size,
- IN VOID *Buffer
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
)
{
return PciExpressWriteBuffer (StartAddress, Size, Buffer);
diff --git a/MdePkg/Library/BasePciSegmentLibPci/PciSegmentLib.c b/MdePkg/Library/BasePciSegmentLibPci/PciSegmentLib.c
index 721eebfd..4f554626 100644
--- a/MdePkg/Library/BasePciSegmentLibPci/PciSegmentLib.c
+++ b/MdePkg/Library/BasePciSegmentLibPci/PciSegmentLib.c
@@ -22,7 +22,7 @@
@param M Additional bits to assert to be zero.
**/
-#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
+#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A, M) \
ASSERT (((A) & (0xfffffffff0000000ULL | (M))) == 0)
/**
@@ -30,7 +30,7 @@
@param A The address to convert.
**/
-#define PCI_SEGMENT_TO_PCI_ADDRESS(A) ((UINTN) (UINT32) A)
+#define PCI_SEGMENT_TO_PCI_ADDRESS(A) ((UINTN) (UINT32) A)
/**
Register a PCI device so PCI configuration registers may be accessed after
@@ -76,7 +76,7 @@ PciSegmentRegisterForRuntimeAccess (
UINT8
EFIAPI
PciSegmentRead8 (
- IN UINT64 Address
+ IN UINT64 Address
)
{
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
@@ -101,8 +101,8 @@ PciSegmentRead8 (
UINT8
EFIAPI
PciSegmentWrite8 (
- IN UINT64 Address,
- IN UINT8 Value
+ IN UINT64 Address,
+ IN UINT8 Value
)
{
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
@@ -130,11 +130,11 @@ PciSegmentWrite8 (
UINT8
EFIAPI
PciSegmentOr8 (
- IN UINT64 Address,
- IN UINT8 OrData
+ IN UINT64 Address,
+ IN UINT8 OrData
)
{
- return PciWrite8 (PCI_SEGMENT_TO_PCI_ADDRESS (Address), (UINT8) (PciSegmentRead8 (Address) | OrData));
+ return PciWrite8 (PCI_SEGMENT_TO_PCI_ADDRESS (Address), (UINT8)(PciSegmentRead8 (Address) | OrData));
}
/**
@@ -156,11 +156,11 @@ PciSegmentOr8 (
UINT8
EFIAPI
PciSegmentAnd8 (
- IN UINT64 Address,
- IN UINT8 AndData
+ IN UINT64 Address,
+ IN UINT8 AndData
)
{
- return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));
+ return PciSegmentWrite8 (Address, (UINT8)(PciSegmentRead8 (Address) & AndData));
}
/**
@@ -186,12 +186,12 @@ PciSegmentAnd8 (
UINT8
EFIAPI
PciSegmentAndThenOr8 (
- IN UINT64 Address,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINT64 Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
)
{
- return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));
+ return PciSegmentWrite8 (Address, (UINT8)((PciSegmentRead8 (Address) & AndData) | OrData));
}
/**
@@ -218,9 +218,9 @@ PciSegmentAndThenOr8 (
UINT8
EFIAPI
PciSegmentBitFieldRead8 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);
@@ -253,10 +253,10 @@ PciSegmentBitFieldRead8 (
UINT8
EFIAPI
PciSegmentBitFieldWrite8 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 Value
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
)
{
return PciSegmentWrite8 (
@@ -295,10 +295,10 @@ PciSegmentBitFieldWrite8 (
UINT8
EFIAPI
PciSegmentBitFieldOr8 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 OrData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
)
{
return PciSegmentWrite8 (
@@ -337,10 +337,10 @@ PciSegmentBitFieldOr8 (
UINT8
EFIAPI
PciSegmentBitFieldAnd8 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
)
{
return PciSegmentWrite8 (
@@ -382,11 +382,11 @@ PciSegmentBitFieldAnd8 (
UINT8
EFIAPI
PciSegmentBitFieldAndThenOr8 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
)
{
return PciSegmentWrite8 (
@@ -412,7 +412,7 @@ PciSegmentBitFieldAndThenOr8 (
UINT16
EFIAPI
PciSegmentRead16 (
- IN UINT64 Address
+ IN UINT64 Address
)
{
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
@@ -438,8 +438,8 @@ PciSegmentRead16 (
UINT16
EFIAPI
PciSegmentWrite16 (
- IN UINT64 Address,
- IN UINT16 Value
+ IN UINT64 Address,
+ IN UINT16 Value
)
{
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
@@ -470,11 +470,11 @@ PciSegmentWrite16 (
UINT16
EFIAPI
PciSegmentOr16 (
- IN UINT64 Address,
- IN UINT16 OrData
+ IN UINT64 Address,
+ IN UINT16 OrData
)
{
- return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));
+ return PciSegmentWrite16 (Address, (UINT16)(PciSegmentRead16 (Address) | OrData));
}
/**
@@ -498,11 +498,11 @@ PciSegmentOr16 (
UINT16
EFIAPI
PciSegmentAnd16 (
- IN UINT64 Address,
- IN UINT16 AndData
+ IN UINT64 Address,
+ IN UINT16 AndData
)
{
- return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));
+ return PciSegmentWrite16 (Address, (UINT16)(PciSegmentRead16 (Address) & AndData));
}
/**
@@ -529,12 +529,12 @@ PciSegmentAnd16 (
UINT16
EFIAPI
PciSegmentAndThenOr16 (
- IN UINT64 Address,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINT64 Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
)
{
- return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));
+ return PciSegmentWrite16 (Address, (UINT16)((PciSegmentRead16 (Address) & AndData) | OrData));
}
/**
@@ -562,9 +562,9 @@ PciSegmentAndThenOr16 (
UINT16
EFIAPI
PciSegmentBitFieldRead16 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);
@@ -598,10 +598,10 @@ PciSegmentBitFieldRead16 (
UINT16
EFIAPI
PciSegmentBitFieldWrite16 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 Value
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
)
{
return PciSegmentWrite16 (
@@ -641,10 +641,10 @@ PciSegmentBitFieldWrite16 (
UINT16
EFIAPI
PciSegmentBitFieldOr16 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 OrData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
)
{
return PciSegmentWrite16 (
@@ -684,10 +684,10 @@ PciSegmentBitFieldOr16 (
UINT16
EFIAPI
PciSegmentBitFieldAnd16 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
)
{
return PciSegmentWrite16 (
@@ -730,11 +730,11 @@ PciSegmentBitFieldAnd16 (
UINT16
EFIAPI
PciSegmentBitFieldAndThenOr16 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
)
{
return PciSegmentWrite16 (
@@ -760,7 +760,7 @@ PciSegmentBitFieldAndThenOr16 (
UINT32
EFIAPI
PciSegmentRead32 (
- IN UINT64 Address
+ IN UINT64 Address
)
{
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
@@ -786,8 +786,8 @@ PciSegmentRead32 (
UINT32
EFIAPI
PciSegmentWrite32 (
- IN UINT64 Address,
- IN UINT32 Value
+ IN UINT64 Address,
+ IN UINT32 Value
)
{
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
@@ -816,8 +816,8 @@ PciSegmentWrite32 (
UINT32
EFIAPI
PciSegmentOr32 (
- IN UINT64 Address,
- IN UINT32 OrData
+ IN UINT64 Address,
+ IN UINT32 OrData
)
{
return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);
@@ -844,8 +844,8 @@ PciSegmentOr32 (
UINT32
EFIAPI
PciSegmentAnd32 (
- IN UINT64 Address,
- IN UINT32 AndData
+ IN UINT64 Address,
+ IN UINT32 AndData
)
{
return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);
@@ -875,9 +875,9 @@ PciSegmentAnd32 (
UINT32
EFIAPI
PciSegmentAndThenOr32 (
- IN UINT64 Address,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINT64 Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
)
{
return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);
@@ -908,9 +908,9 @@ PciSegmentAndThenOr32 (
UINT32
EFIAPI
PciSegmentBitFieldRead32 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);
@@ -944,10 +944,10 @@ PciSegmentBitFieldRead32 (
UINT32
EFIAPI
PciSegmentBitFieldWrite32 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
)
{
return PciSegmentWrite32 (
@@ -986,10 +986,10 @@ PciSegmentBitFieldWrite32 (
UINT32
EFIAPI
PciSegmentBitFieldOr32 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
)
{
return PciSegmentWrite32 (
@@ -1028,10 +1028,10 @@ PciSegmentBitFieldOr32 (
UINT32
EFIAPI
PciSegmentBitFieldAnd32 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
)
{
return PciSegmentWrite32 (
@@ -1074,11 +1074,11 @@ PciSegmentBitFieldAnd32 (
UINT32
EFIAPI
PciSegmentBitFieldAndThenOr32 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
)
{
return PciSegmentWrite32 (
@@ -1113,12 +1113,12 @@ PciSegmentBitFieldAndThenOr32 (
UINTN
EFIAPI
PciSegmentReadBuffer (
- IN UINT64 StartAddress,
- IN UINTN Size,
- OUT VOID *Buffer
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
)
{
- UINTN ReturnValue;
+ UINTN ReturnValue;
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
@@ -1139,19 +1139,19 @@ PciSegmentReadBuffer (
// Read a byte if StartAddress is byte aligned
//
*(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
- StartAddress += sizeof (UINT8);
- Size -= sizeof (UINT8);
- Buffer = (UINT8*)Buffer + 1;
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8 *)Buffer + 1;
}
- if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {
//
// Read a word if StartAddress is word aligned
//
WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
}
while (Size >= sizeof (UINT32)) {
@@ -1160,8 +1160,8 @@ PciSegmentReadBuffer (
//
WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
StartAddress += sizeof (UINT32);
- Size -= sizeof (UINT32);
- Buffer = (UINT32*)Buffer + 1;
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32 *)Buffer + 1;
}
if (Size >= sizeof (UINT16)) {
@@ -1170,8 +1170,8 @@ PciSegmentReadBuffer (
//
WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
}
if (Size >= sizeof (UINT8)) {
@@ -1211,12 +1211,12 @@ PciSegmentReadBuffer (
UINTN
EFIAPI
PciSegmentWriteBuffer (
- IN UINT64 StartAddress,
- IN UINTN Size,
- IN VOID *Buffer
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
)
{
- UINTN ReturnValue;
+ UINTN ReturnValue;
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
@@ -1236,20 +1236,20 @@ PciSegmentWriteBuffer (
//
// Write a byte if StartAddress is byte aligned
//
- PciSegmentWrite8 (StartAddress, *(UINT8*) Buffer);
+ PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer);
StartAddress += sizeof (UINT8);
- Size -= sizeof (UINT8);
- Buffer = (UINT8*) Buffer + 1;
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8 *)Buffer + 1;
}
- if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {
//
// Write a word if StartAddress is word aligned
//
PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*) Buffer + 1;
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
}
while (Size >= sizeof (UINT32)) {
@@ -1258,8 +1258,8 @@ PciSegmentWriteBuffer (
//
PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
StartAddress += sizeof (UINT32);
- Size -= sizeof (UINT32);
- Buffer = (UINT32*) Buffer + 1;
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32 *)Buffer + 1;
}
if (Size >= sizeof (UINT16)) {
@@ -1268,15 +1268,15 @@ PciSegmentWriteBuffer (
//
PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*) Buffer + 1;
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
}
if (Size >= sizeof (UINT8)) {
//
// Write the last remaining byte if exist
//
- PciSegmentWrite8 (StartAddress, *(UINT8*) Buffer);
+ PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer);
}
return ReturnValue;
diff --git a/MdePkg/Library/BasePrintLib/PrintLib.c b/MdePkg/Library/BasePrintLib/PrintLib.c
index 7df0f165..6e8db744 100644
--- a/MdePkg/Library/BasePrintLib/PrintLib.c
+++ b/MdePkg/Library/BasePrintLib/PrintLib.c
@@ -15,9 +15,9 @@
// A NULL VA_LIST can not be passed into BasePrintLibSPrintMarker() because some
// compilers define VA_LIST to be a structure.
//
-VA_LIST gNullVaList;
+VA_LIST gNullVaList;
-#define ASSERT_UNICODE_BUFFER(Buffer) ASSERT ((((UINTN) (Buffer)) & 0x01) == 0)
+#define ASSERT_UNICODE_BUFFER(Buffer) ASSERT ((((UINTN) (Buffer)) & 0x01) == 0)
/**
Produces a Null-terminated Unicode string in an output buffer based on
@@ -174,8 +174,8 @@ UnicodeSPrint (
...
)
{
- VA_LIST Marker;
- UINTN NumberOfPrinted;
+ VA_LIST Marker;
+ UINTN NumberOfPrinted;
VA_START (Marker, FormatString);
NumberOfPrinted = UnicodeVSPrint (StartOfBuffer, BufferSize, FormatString, Marker);
@@ -334,8 +334,8 @@ UnicodeSPrintAsciiFormat (
...
)
{
- VA_LIST Marker;
- UINTN NumberOfPrinted;
+ VA_LIST Marker;
+ UINTN NumberOfPrinted;
VA_START (Marker, FormatString);
NumberOfPrinted = UnicodeVSPrintAsciiFormat (StartOfBuffer, BufferSize, FormatString, Marker);
@@ -343,7 +343,6 @@ UnicodeSPrintAsciiFormat (
return NumberOfPrinted;
}
-
/**
Converts a decimal value to a Null-terminated Unicode string.
@@ -405,7 +404,7 @@ UnicodeValueToStringS (
IN UINTN Width
)
{
- ASSERT_UNICODE_BUFFER(Buffer);
+ ASSERT_UNICODE_BUFFER (Buffer);
return BasePrintLibConvertValueToStringS ((CHAR8 *)Buffer, BufferSize, Flags, Value, Width, 2);
}
@@ -449,10 +448,10 @@ UnicodeValueToStringS (
UINTN
EFIAPI
AsciiVSPrint (
- OUT CHAR8 *StartOfBuffer,
- IN UINTN BufferSize,
- IN CONST CHAR8 *FormatString,
- IN VA_LIST Marker
+ OUT CHAR8 *StartOfBuffer,
+ IN UINTN BufferSize,
+ IN CONST CHAR8 *FormatString,
+ IN VA_LIST Marker
)
{
return BasePrintLibSPrintMarker (StartOfBuffer, BufferSize, 0, FormatString, Marker, NULL);
@@ -496,10 +495,10 @@ AsciiVSPrint (
UINTN
EFIAPI
AsciiBSPrint (
- OUT CHAR8 *StartOfBuffer,
- IN UINTN BufferSize,
- IN CONST CHAR8 *FormatString,
- IN BASE_LIST Marker
+ OUT CHAR8 *StartOfBuffer,
+ IN UINTN BufferSize,
+ IN CONST CHAR8 *FormatString,
+ IN BASE_LIST Marker
)
{
return BasePrintLibSPrintMarker (StartOfBuffer, BufferSize, 0, FormatString, gNullVaList, Marker);
@@ -552,8 +551,8 @@ AsciiSPrint (
...
)
{
- VA_LIST Marker;
- UINTN NumberOfPrinted;
+ VA_LIST Marker;
+ UINTN NumberOfPrinted;
VA_START (Marker, FormatString);
NumberOfPrinted = AsciiVSPrint (StartOfBuffer, BufferSize, FormatString, Marker);
@@ -712,8 +711,8 @@ AsciiSPrintUnicodeFormat (
...
)
{
- VA_LIST Marker;
- UINTN NumberOfPrinted;
+ VA_LIST Marker;
+ UINTN NumberOfPrinted;
VA_START (Marker, FormatString);
NumberOfPrinted = AsciiVSPrintUnicodeFormat (StartOfBuffer, BufferSize, FormatString, Marker);
@@ -773,11 +772,11 @@ AsciiSPrintUnicodeFormat (
RETURN_STATUS
EFIAPI
AsciiValueToStringS (
- IN OUT CHAR8 *Buffer,
- IN UINTN BufferSize,
- IN UINTN Flags,
- IN INT64 Value,
- IN UINTN Width
+ IN OUT CHAR8 *Buffer,
+ IN UINTN BufferSize,
+ IN UINTN Flags,
+ IN INT64 Value,
+ IN UINTN Width
)
{
return BasePrintLibConvertValueToStringS (Buffer, BufferSize, Flags, Value, Width, 1);
@@ -803,7 +802,7 @@ AsciiValueToStringS (
UINTN
EFIAPI
SPrintLength (
- IN CONST CHAR16 *FormatString,
+ IN CONST CHAR16 *FormatString,
IN VA_LIST Marker
)
{
@@ -829,8 +828,8 @@ SPrintLength (
UINTN
EFIAPI
SPrintLengthAsciiFormat (
- IN CONST CHAR8 *FormatString,
- IN VA_LIST Marker
+ IN CONST CHAR8 *FormatString,
+ IN VA_LIST Marker
)
{
return BasePrintLibSPrintMarker (NULL, 0, OUTPUT_UNICODE | COUNT_ONLY_NO_PRINT, (CHAR8 *)FormatString, Marker, NULL);
diff --git a/MdePkg/Library/BasePrintLib/PrintLibInternal.c b/MdePkg/Library/BasePrintLib/PrintLibInternal.c
index bda82332..a990668d 100644
--- a/MdePkg/Library/BasePrintLib/PrintLibInternal.c
+++ b/MdePkg/Library/BasePrintLib/PrintLibInternal.c
@@ -8,14 +8,14 @@
#include "PrintLibInternal.h"
-#define WARNING_STATUS_NUMBER 5
-#define ERROR_STATUS_NUMBER 33
+#define WARNING_STATUS_NUMBER 7
+#define ERROR_STATUS_NUMBER 35
//
// Safe print checks
//
-#define RSIZE_MAX (PcdGet32 (PcdMaximumUnicodeStringLength))
-#define ASCII_RSIZE_MAX (PcdGet32 (PcdMaximumAsciiStringLength))
+#define RSIZE_MAX (PcdGet32 (PcdMaximumUnicodeStringLength))
+#define ASCII_RSIZE_MAX (PcdGet32 (PcdMaximumAsciiStringLength))
#define SAFE_PRINT_CONSTRAINT_CHECK(Expression, RetVal) \
do { \
@@ -25,24 +25,26 @@
} \
} while (FALSE)
-GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 mHexStr[] = {'0','1','2','3','4','5','6','7','8','9','A','B','C','D','E','F'};
+GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 mHexStr[] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };
//
// Longest string: RETURN_WARN_BUFFER_TOO_SMALL => 24 characters plus NUL byte
//
-GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 mWarningString[][24+1] = {
+GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 mWarningString[][24+1] = {
"Success", // RETURN_SUCCESS = 0
"Warning Unknown Glyph", // RETURN_WARN_UNKNOWN_GLYPH = 1
"Warning Delete Failure", // RETURN_WARN_DELETE_FAILURE = 2
"Warning Write Failure", // RETURN_WARN_WRITE_FAILURE = 3
"Warning Buffer Too Small", // RETURN_WARN_BUFFER_TOO_SMALL = 4
"Warning Stale Data", // RETURN_WARN_STALE_DATA = 5
+ "Warning File System", // RETURN_WARN_FILE_SYSTEM = 6
+ "Warning Reset Required", // RETURN_WARN_RESET_REQUIRED = 7
};
//
// Longest string: RETURN_INCOMPATIBLE_VERSION => 20 characters plus NUL byte
//
-GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 mErrorString[][20+1] = {
+GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 mErrorString[][20+1] = {
"Load Error", // RETURN_LOAD_ERROR = 1 | MAX_BIT
"Invalid Parameter", // RETURN_INVALID_PARAMETER = 2 | MAX_BIT
"Unsupported", // RETURN_UNSUPPORTED = 3 | MAX_BIT
@@ -75,10 +77,11 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 mErrorString[][20+1] = {
"Reserved (30)", // RESERVED = 30 | MAX_BIT
"End of File", // RETURN_END_OF_FILE = 31 | MAX_BIT
"Invalid Language", // RETURN_INVALID_LANGUAGE = 32 | MAX_BIT
- "Compromised Data" // RETURN_COMPROMISED_DATA = 33 | MAX_BIT
+ "Compromised Data", // RETURN_COMPROMISED_DATA = 33 | MAX_BIT
+ "IP Address Conflict", // RETURN_IP_ADDRESS_CONFLICT = 34 | MAX_BIT
+ "HTTP Error" // RETURN_HTTP_ERROR = 35 | MAX_BIT
};
-
/**
Internal function that places the character into the Buffer.
@@ -97,20 +100,21 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 mErrorString[][20+1] = {
**/
CHAR8 *
BasePrintLibFillBuffer (
- OUT CHAR8 *Buffer,
- IN CHAR8 *EndBuffer,
- IN INTN Length,
- IN UINTN Character,
- IN INTN Increment
+ OUT CHAR8 *Buffer,
+ IN CHAR8 *EndBuffer,
+ IN INTN Length,
+ IN UINTN Character,
+ IN INTN Increment
)
{
INTN Index;
for (Index = 0; Index < Length && Buffer < EndBuffer; Index++) {
- *Buffer = (CHAR8) Character;
+ *Buffer = (CHAR8)Character;
if (Increment != 1) {
*(Buffer + 1) = (CHAR8)(Character >> 8);
}
+
Buffer += Increment;
}
@@ -143,7 +147,7 @@ BasePrintLibValueToString (
//
*Buffer = 0;
do {
- Value = (INT64)DivU64x32Remainder ((UINT64)Value, (UINT32)Radix, &Remainder);
+ Value = (INT64)DivU64x32Remainder ((UINT64)Value, (UINT32)Radix, &Remainder);
*(++Buffer) = mHexStr[Remainder];
} while (Value != 0);
@@ -193,11 +197,11 @@ BasePrintLibValueToString (
**/
UINTN
BasePrintLibConvertValueToString (
- IN OUT CHAR8 *Buffer,
- IN UINTN Flags,
- IN INT64 Value,
- IN UINTN Width,
- IN UINTN Increment
+ IN OUT CHAR8 *Buffer,
+ IN UINTN Flags,
+ IN INT64 Value,
+ IN UINTN Width,
+ IN UINTN Increment
)
{
CHAR8 *OriginalBuffer;
@@ -229,15 +233,17 @@ BasePrintLibConvertValueToString (
//
// Width is 0 or COMMA_TYPE is set, PREFIX_ZERO is ignored.
//
- if (Width == 0 || (Flags & COMMA_TYPE) != 0) {
- Flags &= ~((UINTN) PREFIX_ZERO);
+ if ((Width == 0) || ((Flags & COMMA_TYPE) != 0)) {
+ Flags &= ~((UINTN)PREFIX_ZERO);
}
+
//
// If Width is 0 then a width of MAXIMUM_VALUE_CHARACTERS is assumed.
//
if (Width == 0) {
Width = MAXIMUM_VALUE_CHARACTERS - 1;
}
+
//
// Set the tag for the end of the input Buffer.
//
@@ -247,7 +253,7 @@ BasePrintLibConvertValueToString (
// Convert decimal negative
//
if ((Value < 0) && ((Flags & RADIX_HEX) == 0)) {
- Value = -Value;
+ Value = -Value;
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, 1, '-', Increment);
Width--;
}
@@ -255,9 +261,9 @@ BasePrintLibConvertValueToString (
//
// Count the length of the value string.
//
- Radix = ((Flags & RADIX_HEX) == 0)? 10 : 16;
+ Radix = ((Flags & RADIX_HEX) == 0) ? 10 : 16;
ValueBufferPtr = BasePrintLibValueToString (ValueBuffer, Value, Radix);
- Count = ValueBufferPtr - ValueBuffer;
+ Count = ValueBufferPtr - ValueBuffer;
//
// Append Zero
@@ -273,6 +279,7 @@ BasePrintLibConvertValueToString (
if (Digits != 0) {
Digits = 3 - Digits;
}
+
for (Index = 0; Index < Count; Index++) {
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, 1, *ValueBufferPtr--, Increment);
if ((Flags & COMMA_TYPE) != 0) {
@@ -347,12 +354,12 @@ BasePrintLibConvertValueToString (
**/
RETURN_STATUS
BasePrintLibConvertValueToStringS (
- IN OUT CHAR8 *Buffer,
- IN UINTN BufferSize,
- IN UINTN Flags,
- IN INT64 Value,
- IN UINTN Width,
- IN UINTN Increment
+ IN OUT CHAR8 *Buffer,
+ IN UINTN BufferSize,
+ IN UINTN Flags,
+ IN INT64 Value,
+ IN UINTN Width,
+ IN UINTN Increment
)
{
CHAR8 *EndBuffer;
@@ -403,9 +410,10 @@ BasePrintLibConvertValueToStringS (
//
// Width is 0 or COMMA_TYPE is set, PREFIX_ZERO is ignored.
//
- if (Width == 0 || (Flags & COMMA_TYPE) != 0) {
- Flags &= ~((UINTN) PREFIX_ZERO);
+ if ((Width == 0) || ((Flags & COMMA_TYPE) != 0)) {
+ Flags &= ~((UINTN)PREFIX_ZERO);
}
+
//
// If Width is 0 then a width of MAXIMUM_VALUE_CHARACTERS is assumed.
//
@@ -417,7 +425,7 @@ BasePrintLibConvertValueToStringS (
// Count the characters of the output string.
//
Count = 0;
- Radix = ((Flags & RADIX_HEX) == 0)? 10 : 16;
+ Radix = ((Flags & RADIX_HEX) == 0) ? 10 : 16;
if ((Flags & PREFIX_ZERO) != 0) {
Count = Width;
@@ -428,6 +436,7 @@ BasePrintLibConvertValueToStringS (
} else {
ValueBufferPtr = BasePrintLibValueToString (ValueBuffer, Value, Radix);
}
+
Digits = ValueBufferPtr - ValueBuffer;
Count += Digits;
@@ -452,7 +461,7 @@ BasePrintLibConvertValueToStringS (
// Convert decimal negative
//
if ((Value < 0) && ((Flags & RADIX_HEX) == 0)) {
- Value = -Value;
+ Value = -Value;
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, 1, '-', Increment);
Width--;
}
@@ -461,7 +470,7 @@ BasePrintLibConvertValueToStringS (
// Count the length of the value string.
//
ValueBufferPtr = BasePrintLibValueToString (ValueBuffer, Value, Radix);
- Count = ValueBufferPtr - ValueBuffer;
+ Count = ValueBufferPtr - ValueBuffer;
//
// Append Zero
@@ -477,6 +486,7 @@ BasePrintLibConvertValueToStringS (
if (Digits != 0) {
Digits = 3 - Digits;
}
+
for (Index = 0; Index < Count; Index++) {
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, 1, *ValueBufferPtr--, Increment);
if ((Flags & COMMA_TYPE) != 0) {
@@ -532,40 +542,40 @@ BasePrintLibSPrintMarker (
IN UINTN BufferSize,
IN UINTN Flags,
IN CONST CHAR8 *Format,
- IN VA_LIST VaListMarker, OPTIONAL
+ IN VA_LIST VaListMarker OPTIONAL,
IN BASE_LIST BaseListMarker OPTIONAL
)
{
- CHAR8 *OriginalBuffer;
- CHAR8 *EndBuffer;
- CHAR8 ValueBuffer[MAXIMUM_VALUE_CHARACTERS];
- UINT32 BytesPerOutputCharacter;
- UINTN BytesPerFormatCharacter;
- UINTN FormatMask;
- UINTN FormatCharacter;
- UINTN Width;
- UINTN Precision;
- INT64 Value;
- CONST CHAR8 *ArgumentString;
- UINTN Character;
- GUID *TmpGuid;
- TIME *TmpTime;
- UINTN Count;
- UINTN ArgumentMask;
- INTN BytesPerArgumentCharacter;
- UINTN ArgumentCharacter;
- BOOLEAN Done;
- UINTN Index;
- CHAR8 Prefix;
- BOOLEAN ZeroPad;
- BOOLEAN Comma;
- UINTN Digits;
- UINTN Radix;
- RETURN_STATUS Status;
- UINT32 GuidData1;
- UINT16 GuidData2;
- UINT16 GuidData3;
- UINTN LengthToReturn;
+ CHAR8 *OriginalBuffer;
+ CHAR8 *EndBuffer;
+ CHAR8 ValueBuffer[MAXIMUM_VALUE_CHARACTERS];
+ UINT32 BytesPerOutputCharacter;
+ UINTN BytesPerFormatCharacter;
+ UINTN FormatMask;
+ UINTN FormatCharacter;
+ UINTN Width;
+ UINTN Precision;
+ INT64 Value;
+ CONST CHAR8 *ArgumentString;
+ UINTN Character;
+ GUID *TmpGuid;
+ TIME *TmpTime;
+ UINTN Count;
+ UINTN ArgumentMask;
+ INTN BytesPerArgumentCharacter;
+ UINTN ArgumentCharacter;
+ BOOLEAN Done;
+ UINTN Index;
+ CHAR8 Prefix;
+ BOOLEAN ZeroPad;
+ BOOLEAN Comma;
+ UINTN Digits;
+ UINTN Radix;
+ RETURN_STATUS Status;
+ UINT32 GuidData1;
+ UINT16 GuidData2;
+ UINT16 GuidData3;
+ UINTN LengthToReturn;
//
// If you change this code be sure to match the 2 versions of this function.
@@ -597,11 +607,13 @@ BasePrintLibSPrintMarker (
if (RSIZE_MAX != 0) {
SAFE_PRINT_CONSTRAINT_CHECK ((BufferSize <= RSIZE_MAX), 0);
}
+
BytesPerOutputCharacter = 2;
} else {
if (ASCII_RSIZE_MAX != 0) {
SAFE_PRINT_CONSTRAINT_CHECK ((BufferSize <= ASCII_RSIZE_MAX), 0);
}
+
BytesPerOutputCharacter = 1;
}
@@ -613,14 +625,16 @@ BasePrintLibSPrintMarker (
if (RSIZE_MAX != 0) {
SAFE_PRINT_CONSTRAINT_CHECK ((StrnLenS ((CHAR16 *)Format, RSIZE_MAX + 1) <= RSIZE_MAX), 0);
}
+
BytesPerFormatCharacter = 2;
- FormatMask = 0xffff;
+ FormatMask = 0xffff;
} else {
if (ASCII_RSIZE_MAX != 0) {
SAFE_PRINT_CONSTRAINT_CHECK ((AsciiStrnLenS (Format, ASCII_RSIZE_MAX + 1) <= ASCII_RSIZE_MAX), 0);
}
+
BytesPerFormatCharacter = 1;
- FormatMask = 0xff;
+ FormatMask = 0xff;
}
if ((Flags & COUNT_ONLY_NO_PRINT) != 0) {
@@ -637,7 +651,7 @@ BasePrintLibSPrintMarker (
}
LengthToReturn = 0;
- EndBuffer = NULL;
+ EndBuffer = NULL;
OriginalBuffer = NULL;
//
@@ -665,10 +679,11 @@ BasePrintLibSPrintMarker (
if ((Buffer != NULL) && (Buffer >= EndBuffer)) {
break;
}
+
//
// Clear all the flag bits except those that may have been passed in
//
- Flags &= (UINTN) (OUTPUT_UNICODE | FORMAT_UNICODE | COUNT_ONLY_NO_PRINT);
+ Flags &= (UINTN)(OUTPUT_UNICODE | FORMAT_UNICODE | COUNT_ONLY_NO_PRINT);
//
// Set the default width to zero, and the default precision to 1
@@ -682,348 +697,418 @@ BasePrintLibSPrintMarker (
Digits = 0;
switch (FormatCharacter) {
- case '%':
- //
- // Parse Flags and Width
- //
- for (Done = FALSE; !Done; ) {
- Format += BytesPerFormatCharacter;
- FormatCharacter = ((*Format & 0xff) | ((BytesPerFormatCharacter == 1) ? 0 : (*(Format + 1) << 8))) & FormatMask;
- switch (FormatCharacter) {
- case '.':
- Flags |= PRECISION;
- break;
- case '-':
- Flags |= LEFT_JUSTIFY;
- break;
- case '+':
- Flags |= PREFIX_SIGN;
- break;
- case ' ':
- Flags |= PREFIX_BLANK;
- break;
- case ',':
- Flags |= COMMA_TYPE;
- break;
- case 'L':
- case 'l':
- Flags |= LONG_TYPE;
- break;
- case '*':
- if ((Flags & PRECISION) == 0) {
- Flags |= PAD_TO_WIDTH;
- if (BaseListMarker == NULL) {
- Width = VA_ARG (VaListMarker, UINTN);
- } else {
- Width = BASE_ARG (BaseListMarker, UINTN);
- }
- } else {
- if (BaseListMarker == NULL) {
- Precision = VA_ARG (VaListMarker, UINTN);
- } else {
- Precision = BASE_ARG (BaseListMarker, UINTN);
- }
- }
- break;
- case '0':
- if ((Flags & PRECISION) == 0) {
- Flags |= PREFIX_ZERO;
- }
- case '1':
- case '2':
- case '3':
- case '4':
- case '5':
- case '6':
- case '7':
- case '8':
- case '9':
- for (Count = 0; ((FormatCharacter >= '0') && (FormatCharacter <= '9')); ){
- Count = (Count * 10) + FormatCharacter - '0';
- Format += BytesPerFormatCharacter;
- FormatCharacter = ((*Format & 0xff) | ((BytesPerFormatCharacter == 1) ? 0 : (*(Format + 1) << 8))) & FormatMask;
- }
- Format -= BytesPerFormatCharacter;
- if ((Flags & PRECISION) == 0) {
- Flags |= PAD_TO_WIDTH;
- Width = Count;
- } else {
- Precision = Count;
- }
- break;
-
- case '\0':
- //
- // Make no output if Format string terminates unexpectedly when
- // looking up for flag, width, precision and type.
- //
- Format -= BytesPerFormatCharacter;
- Precision = 0;
- //
- // break skipped on purpose.
- //
- default:
- Done = TRUE;
- break;
- }
- }
-
- //
- // Handle each argument type
- //
- switch (FormatCharacter) {
- case 'p':
+ case '%':
//
- // Flag space, +, 0, L & l are invalid for type p.
+ // Parse Flags and Width
//
- Flags &= ~((UINTN) (PREFIX_BLANK | PREFIX_SIGN | PREFIX_ZERO | LONG_TYPE));
- if (sizeof (VOID *) > 4) {
- Flags |= LONG_TYPE;
- }
- //
- // break skipped on purpose
- //
-#ifdef LITE_PRINT
- case 'r':
- Status = 0;
-#endif
- case 'X':
- Flags |= PREFIX_ZERO;
- //
- // break skipped on purpose
- //
- case 'x':
- Flags |= RADIX_HEX;
- //
- // break skipped on purpose
- //
- case 'u':
- if ((Flags & RADIX_HEX) == 0) {
- Flags &= ~((UINTN) (PREFIX_SIGN));
- Flags |= UNSIGNED_TYPE;
- }
- //
- // break skipped on purpose
- //
- case 'd':
- if ((Flags & LONG_TYPE) == 0) {
- //
- // 'd', 'u', 'x', and 'X' that are not preceded by 'l' or 'L' are assumed to be type "int".
- // This assumption is made so the format string definition is compatible with the ANSI C
- // Specification for formatted strings. It is recommended that the Base Types be used
- // everywhere, but in this one case, compliance with ANSI C is more important, and
- // provides an implementation that is compatible with that largest possible set of CPU
- // architectures. This is why the type "int" is used in this one case.
- //
- if (BaseListMarker == NULL) {
- Value = VA_ARG (VaListMarker, int);
- } else {
- Value = BASE_ARG (BaseListMarker, int);
- }
- } else {
- if (BaseListMarker == NULL) {
- Value = VA_ARG (VaListMarker, INT64);
- } else {
- Value = BASE_ARG (BaseListMarker, INT64);
- }
- }
- if ((Flags & PREFIX_BLANK) != 0) {
- Prefix = ' ';
- }
- if ((Flags & PREFIX_SIGN) != 0) {
- Prefix = '+';
- }
- if ((Flags & COMMA_TYPE) != 0) {
- Comma = TRUE;
- }
- if ((Flags & RADIX_HEX) == 0) {
- Radix = 10;
- if (Comma) {
- Flags &= ~((UINTN) PREFIX_ZERO);
- Precision = 1;
- }
- if (Value < 0 && (Flags & UNSIGNED_TYPE) == 0) {
- Flags |= PREFIX_SIGN;
- Prefix = '-';
- Value = -Value;
- } else if ((Flags & UNSIGNED_TYPE) != 0 && (Flags & LONG_TYPE) == 0) {
- //
- // 'd', 'u', 'x', and 'X' that are not preceded by 'l' or 'L' are assumed to be type "int".
- // This assumption is made so the format string definition is compatible with the ANSI C
- // Specification for formatted strings. It is recommended that the Base Types be used
- // everywhere, but in this one case, compliance with ANSI C is more important, and
- // provides an implementation that is compatible with that largest possible set of CPU
- // architectures. This is why the type "unsigned int" is used in this one case.
- //
- Value = (unsigned int)Value;
- }
- } else {
- Radix = 16;
- Comma = FALSE;
- if ((Flags & LONG_TYPE) == 0 && Value < 0) {
- //
- // 'd', 'u', 'x', and 'X' that are not preceded by 'l' or 'L' are assumed to be type "int".
- // This assumption is made so the format string definition is compatible with the ANSI C
- // Specification for formatted strings. It is recommended that the Base Types be used
- // everywhere, but in this one case, compliance with ANSI C is more important, and
- // provides an implementation that is compatible with that largest possible set of CPU
- // architectures. This is why the type "unsigned int" is used in this one case.
- //
- Value = (unsigned int)Value;
- }
- }
- //
- // Convert Value to a reversed string
- //
- Count = BasePrintLibValueToString (ValueBuffer, Value, Radix) - ValueBuffer;
- if (Value == 0 && Precision == 0) {
- Count = 0;
- }
- ArgumentString = (CHAR8 *)ValueBuffer + Count;
-
- Digits = Count % 3;
- if (Digits != 0) {
- Digits = 3 - Digits;
- }
- if (Comma && Count != 0) {
- Count += ((Count - 1) / 3);
- }
- if (Prefix != 0) {
- Count++;
- Precision++;
- }
- Flags |= ARGUMENT_REVERSED;
- ZeroPad = TRUE;
- if ((Flags & PREFIX_ZERO) != 0) {
- if ((Flags & LEFT_JUSTIFY) == 0) {
- if ((Flags & PAD_TO_WIDTH) != 0) {
+ for (Done = FALSE; !Done; ) {
+ Format += BytesPerFormatCharacter;
+ FormatCharacter = ((*Format & 0xff) | ((BytesPerFormatCharacter == 1) ? 0 : (*(Format + 1) << 8))) & FormatMask;
+ switch (FormatCharacter) {
+ case '.':
+ Flags |= PRECISION;
+ break;
+ case '-':
+ Flags |= LEFT_JUSTIFY;
+ break;
+ case '+':
+ Flags |= PREFIX_SIGN;
+ break;
+ case ' ':
+ Flags |= PREFIX_BLANK;
+ break;
+ case ',':
+ Flags |= COMMA_TYPE;
+ break;
+ case 'L':
+ case 'l':
+ Flags |= LONG_TYPE;
+ break;
+ case '*':
if ((Flags & PRECISION) == 0) {
- Precision = Width;
+ Flags |= PAD_TO_WIDTH;
+ if (BaseListMarker == NULL) {
+ Width = VA_ARG (VaListMarker, UINTN);
+ } else {
+ Width = BASE_ARG (BaseListMarker, UINTN);
+ }
+ } else {
+ if (BaseListMarker == NULL) {
+ Precision = VA_ARG (VaListMarker, UINTN);
+ } else {
+ Precision = BASE_ARG (BaseListMarker, UINTN);
+ }
+ }
+
+ break;
+ case '0':
+ if ((Flags & PRECISION) == 0) {
+ Flags |= PREFIX_ZERO;
+ }
+
+ case '1':
+ case '2':
+ case '3':
+ case '4':
+ case '5':
+ case '6':
+ case '7':
+ case '8':
+ case '9':
+ for (Count = 0; ((FormatCharacter >= '0') && (FormatCharacter <= '9')); ) {
+ Count = (Count * 10) + FormatCharacter - '0';
+ Format += BytesPerFormatCharacter;
+ FormatCharacter = ((*Format & 0xff) | ((BytesPerFormatCharacter == 1) ? 0 : (*(Format + 1) << 8))) & FormatMask;
+ }
+
+ Format -= BytesPerFormatCharacter;
+ if ((Flags & PRECISION) == 0) {
+ Flags |= PAD_TO_WIDTH;
+ Width = Count;
+ } else {
+ Precision = Count;
+ }
+
+ break;
+
+ case '\0':
+ //
+ // Make no output if Format string terminates unexpectedly when
+ // looking up for flag, width, precision and type.
+ //
+ Format -= BytesPerFormatCharacter;
+ Precision = 0;
+ //
+ // break skipped on purpose.
+ //
+ default:
+ Done = TRUE;
+ break;
+ }
+ }
+
+ //
+ // Handle each argument type
+ //
+ switch (FormatCharacter) {
+ case 'p':
+ //
+ // Flag space, +, 0, L & l are invalid for type p.
+ //
+ Flags &= ~((UINTN)(PREFIX_BLANK | PREFIX_SIGN | PREFIX_ZERO | LONG_TYPE));
+ if (sizeof (VOID *) > 4) {
+ Flags |= LONG_TYPE;
+ }
+#ifdef LITE_PRINT
+ case 'r':
+ Status = 0;
+#endif
+ //
+ // break skipped on purpose
+ //
+ case 'X':
+ Flags |= PREFIX_ZERO;
+ //
+ // break skipped on purpose
+ //
+ case 'x':
+ Flags |= RADIX_HEX;
+ //
+ // break skipped on purpose
+ //
+ case 'u':
+ if ((Flags & RADIX_HEX) == 0) {
+ Flags &= ~((UINTN)(PREFIX_SIGN));
+ Flags |= UNSIGNED_TYPE;
+ }
+
+ //
+ // break skipped on purpose
+ //
+ case 'd':
+ if ((Flags & LONG_TYPE) == 0) {
+ //
+ // 'd', 'u', 'x', and 'X' that are not preceded by 'l' or 'L' are assumed to be type "int".
+ // This assumption is made so the format string definition is compatible with the ANSI C
+ // Specification for formatted strings. It is recommended that the Base Types be used
+ // everywhere, but in this one case, compliance with ANSI C is more important, and
+ // provides an implementation that is compatible with that largest possible set of CPU
+ // architectures. This is why the type "int" is used in this one case.
+ //
+ if (BaseListMarker == NULL) {
+ Value = VA_ARG (VaListMarker, int);
+ } else {
+ Value = BASE_ARG (BaseListMarker, int);
+ }
+ } else {
+ if (BaseListMarker == NULL) {
+ Value = VA_ARG (VaListMarker, INT64);
+ } else {
+ Value = BASE_ARG (BaseListMarker, INT64);
}
}
- }
- }
- break;
- case 's':
- case 'S':
- Flags |= ARGUMENT_UNICODE;
- //
- // break skipped on purpose
- //
- case 'a':
- if (BaseListMarker == NULL) {
- ArgumentString = VA_ARG (VaListMarker, CHAR8 *);
- } else {
- ArgumentString = BASE_ARG (BaseListMarker, CHAR8 *);
- }
- if (ArgumentString == NULL) {
- Flags &= ~((UINTN) ARGUMENT_UNICODE);
- ArgumentString = "";
- }
- //
- // Set the default precision for string to be zero if not specified.
- //
- if ((Flags & PRECISION) == 0) {
- Precision = 0;
- }
- break;
+ if ((Flags & PREFIX_BLANK) != 0) {
+ Prefix = ' ';
+ }
- case 'c':
- if (BaseListMarker == NULL) {
- Character = VA_ARG (VaListMarker, UINTN) & 0xffff;
- } else {
- Character = BASE_ARG (BaseListMarker, UINTN) & 0xffff;
- }
- ArgumentString = (CHAR8 *)&Character;
- Flags |= ARGUMENT_UNICODE;
- break;
+ if ((Flags & PREFIX_SIGN) != 0) {
+ Prefix = '+';
+ }
- case 'g':
- if (BaseListMarker == NULL) {
- TmpGuid = VA_ARG (VaListMarker, GUID *);
- } else {
- TmpGuid = BASE_ARG (BaseListMarker, GUID *);
- }
- if (TmpGuid == NULL) {
- ArgumentString = "";
- } else {
- GuidData1 = ReadUnaligned32 (&(TmpGuid->Data1));
- GuidData2 = ReadUnaligned16 (&(TmpGuid->Data2));
- GuidData3 = ReadUnaligned16 (&(TmpGuid->Data3));
- BasePrintLibSPrint (
- ValueBuffer,
- MAXIMUM_VALUE_CHARACTERS,
- 0,
- "%08x-%04x-%04x-%02x%02x-%02x%02x%02x%02x%02x%02x",
- GuidData1,
- GuidData2,
- GuidData3,
- TmpGuid->Data4[0],
- TmpGuid->Data4[1],
- TmpGuid->Data4[2],
- TmpGuid->Data4[3],
- TmpGuid->Data4[4],
- TmpGuid->Data4[5],
- TmpGuid->Data4[6],
- TmpGuid->Data4[7]
- );
- ArgumentString = ValueBuffer;
- }
- break;
+ if ((Flags & COMMA_TYPE) != 0) {
+ Comma = TRUE;
+ }
- case 't':
- if (BaseListMarker == NULL) {
- TmpTime = VA_ARG (VaListMarker, TIME *);
- } else {
- TmpTime = BASE_ARG (BaseListMarker, TIME *);
- }
- if (TmpTime == NULL) {
- ArgumentString = "";
- } else {
- BasePrintLibSPrint (
- ValueBuffer,
- MAXIMUM_VALUE_CHARACTERS,
- 0,
- "%02d/%02d/%04d %02d:%02d",
- TmpTime->Month,
- TmpTime->Day,
- TmpTime->Year,
- TmpTime->Hour,
- TmpTime->Minute
- );
- ArgumentString = ValueBuffer;
- }
- break;
+ if ((Flags & RADIX_HEX) == 0) {
+ Radix = 10;
+ if (Comma) {
+ Flags &= ~((UINTN)PREFIX_ZERO);
+ Precision = 1;
+ }
+
+ if ((Value < 0) && ((Flags & UNSIGNED_TYPE) == 0)) {
+ Flags |= PREFIX_SIGN;
+ Prefix = '-';
+ Value = -Value;
+ } else if (((Flags & UNSIGNED_TYPE) != 0) && ((Flags & LONG_TYPE) == 0)) {
+ //
+ // 'd', 'u', 'x', and 'X' that are not preceded by 'l' or 'L' are assumed to be type "int".
+ // This assumption is made so the format string definition is compatible with the ANSI C
+ // Specification for formatted strings. It is recommended that the Base Types be used
+ // everywhere, but in this one case, compliance with ANSI C is more important, and
+ // provides an implementation that is compatible with that largest possible set of CPU
+ // architectures. This is why the type "unsigned int" is used in this one case.
+ //
+ Value = (unsigned int)Value;
+ }
+ } else {
+ Radix = 16;
+ Comma = FALSE;
+ if (((Flags & LONG_TYPE) == 0) && (Value < 0)) {
+ //
+ // 'd', 'u', 'x', and 'X' that are not preceded by 'l' or 'L' are assumed to be type "int".
+ // This assumption is made so the format string definition is compatible with the ANSI C
+ // Specification for formatted strings. It is recommended that the Base Types be used
+ // everywhere, but in this one case, compliance with ANSI C is more important, and
+ // provides an implementation that is compatible with that largest possible set of CPU
+ // architectures. This is why the type "unsigned int" is used in this one case.
+ //
+ Value = (unsigned int)Value;
+ }
+ }
+
+ //
+ // Convert Value to a reversed string
+ //
+ Count = BasePrintLibValueToString (ValueBuffer, Value, Radix) - ValueBuffer;
+ if ((Value == 0) && (Precision == 0)) {
+ Count = 0;
+ }
+
+ ArgumentString = (CHAR8 *)ValueBuffer + Count;
+
+ Digits = Count % 3;
+ if (Digits != 0) {
+ Digits = 3 - Digits;
+ }
+
+ if (Comma && (Count != 0)) {
+ Count += ((Count - 1) / 3);
+ }
+
+ if (Prefix != 0) {
+ Count++;
+ Precision++;
+ }
+
+ Flags |= ARGUMENT_REVERSED;
+ ZeroPad = TRUE;
+ if ((Flags & PREFIX_ZERO) != 0) {
+ if ((Flags & LEFT_JUSTIFY) == 0) {
+ if ((Flags & PAD_TO_WIDTH) != 0) {
+ if ((Flags & PRECISION) == 0) {
+ Precision = Width;
+ }
+ }
+ }
+ }
+
+ break;
+
+ case 's':
+ case 'S':
+ Flags |= ARGUMENT_UNICODE;
+ //
+ // break skipped on purpose
+ //
+ case 'a':
+ if (BaseListMarker == NULL) {
+ ArgumentString = VA_ARG (VaListMarker, CHAR8 *);
+ } else {
+ ArgumentString = BASE_ARG (BaseListMarker, CHAR8 *);
+ }
+
+ if (ArgumentString == NULL) {
+ Flags &= ~((UINTN)ARGUMENT_UNICODE);
+ ArgumentString = "";
+ }
+
+ //
+ // Set the default precision for string to be zero if not specified.
+ //
+ if ((Flags & PRECISION) == 0) {
+ Precision = 0;
+ }
+
+ break;
+
+ case 'c':
+ if (BaseListMarker == NULL) {
+ Character = VA_ARG (VaListMarker, UINTN) & 0xffff;
+ } else {
+ Character = BASE_ARG (BaseListMarker, UINTN) & 0xffff;
+ }
+
+ ArgumentString = (CHAR8 *)&Character;
+ Flags |= ARGUMENT_UNICODE;
+ break;
+
+ case 'g':
+ if (BaseListMarker == NULL) {
+ TmpGuid = VA_ARG (VaListMarker, GUID *);
+ } else {
+ TmpGuid = BASE_ARG (BaseListMarker, GUID *);
+ }
+
+ if (TmpGuid == NULL) {
+ ArgumentString = "";
+ } else {
+ GuidData1 = ReadUnaligned32 (&(TmpGuid->Data1));
+ GuidData2 = ReadUnaligned16 (&(TmpGuid->Data2));
+ GuidData3 = ReadUnaligned16 (&(TmpGuid->Data3));
+ BasePrintLibSPrint (
+ ValueBuffer,
+ MAXIMUM_VALUE_CHARACTERS,
+ 0,
+ "%08x-%04x-%04x-%02x%02x-%02x%02x%02x%02x%02x%02x",
+ GuidData1,
+ GuidData2,
+ GuidData3,
+ TmpGuid->Data4[0],
+ TmpGuid->Data4[1],
+ TmpGuid->Data4[2],
+ TmpGuid->Data4[3],
+ TmpGuid->Data4[4],
+ TmpGuid->Data4[5],
+ TmpGuid->Data4[6],
+ TmpGuid->Data4[7]
+ );
+ ArgumentString = ValueBuffer;
+ }
+
+ break;
+
+ case 't':
+ if (BaseListMarker == NULL) {
+ TmpTime = VA_ARG (VaListMarker, TIME *);
+ } else {
+ TmpTime = BASE_ARG (BaseListMarker, TIME *);
+ }
+
+ if (TmpTime == NULL) {
+ ArgumentString = "";
+ } else {
+ BasePrintLibSPrint (
+ ValueBuffer,
+ MAXIMUM_VALUE_CHARACTERS,
+ 0,
+ "%02d/%02d/%04d %02d:%02d",
+ TmpTime->Month,
+ TmpTime->Day,
+ TmpTime->Year,
+ TmpTime->Hour,
+ TmpTime->Minute
+ );
+ ArgumentString = ValueBuffer;
+ }
+
+ break;
#ifndef LITE_PRINT
- case 'r':
- if (BaseListMarker == NULL) {
- Status = VA_ARG (VaListMarker, RETURN_STATUS);
- } else {
- Status = BASE_ARG (BaseListMarker, RETURN_STATUS);
- }
- ArgumentString = ValueBuffer;
- if (RETURN_ERROR (Status)) {
- //
- // Clear error bit
- //
- Index = Status & ~MAX_BIT;
- if (Index > 0 && Index <= ERROR_STATUS_NUMBER) {
- ArgumentString = mErrorString [Index - 1];
- }
- } else {
- Index = Status;
- if (Index <= WARNING_STATUS_NUMBER) {
- ArgumentString = mWarningString [Index];
- }
- }
- if (ArgumentString == ValueBuffer) {
- BasePrintLibSPrint ((CHAR8 *) ValueBuffer, MAXIMUM_VALUE_CHARACTERS, 0, "%08X", Status);
- }
- break;
+ case 'r':
+ if (BaseListMarker == NULL) {
+ Status = VA_ARG (VaListMarker, RETURN_STATUS);
+ } else {
+ Status = BASE_ARG (BaseListMarker, RETURN_STATUS);
+ }
+
+ ArgumentString = ValueBuffer;
+ if (RETURN_ERROR (Status)) {
+ //
+ // Clear error bit
+ //
+ Index = Status & ~MAX_BIT;
+ if ((Index > 0) && (Index <= ERROR_STATUS_NUMBER)) {
+ ArgumentString = mErrorString[Index - 1];
+ }
+ } else {
+ Index = Status;
+ if (Index <= WARNING_STATUS_NUMBER) {
+ ArgumentString = mWarningString[Index];
+ }
+ }
+
+ if (ArgumentString == ValueBuffer) {
+ BasePrintLibSPrint ((CHAR8 *)ValueBuffer, MAXIMUM_VALUE_CHARACTERS, 0, "%08X", Status);
+ }
+
+ break;
#endif
+ case '\r':
+ Format += BytesPerFormatCharacter;
+ FormatCharacter = ((*Format & 0xff) | ((BytesPerFormatCharacter == 1) ? 0 : (*(Format + 1) << 8))) & FormatMask;
+ if (FormatCharacter == '\n') {
+ //
+ // Translate '\r\n' to '\r\n'
+ //
+ ArgumentString = "\r\n";
+ } else {
+ //
+ // Translate '\r' to '\r'
+ //
+ ArgumentString = "\r";
+ Format -= BytesPerFormatCharacter;
+ }
+
+ break;
+
+ case '\n':
+ //
+ // Translate '\n' to '\r\n' and '\n\r' to '\r\n'
+ //
+ ArgumentString = "\r\n";
+ Format += BytesPerFormatCharacter;
+ FormatCharacter = ((*Format & 0xff) | ((BytesPerFormatCharacter == 1) ? 0 : (*(Format + 1) << 8))) & FormatMask;
+ if (FormatCharacter != '\r') {
+ Format -= BytesPerFormatCharacter;
+ }
+
+ break;
+
+ case '%':
+ default:
+ //
+ // if the type is '%' or unknown, then print it to the screen
+ //
+ ArgumentString = (CHAR8 *)&FormatCharacter;
+ Flags |= ARGUMENT_UNICODE;
+ break;
+ }
+
+ break;
+
case '\r':
- Format += BytesPerFormatCharacter;
+ Format += BytesPerFormatCharacter;
FormatCharacter = ((*Format & 0xff) | ((BytesPerFormatCharacter == 1) ? 0 : (*(Format + 1) << 8))) & FormatMask;
if (FormatCharacter == '\n') {
//
@@ -1035,78 +1120,41 @@ BasePrintLibSPrintMarker (
// Translate '\r' to '\r'
//
ArgumentString = "\r";
- Format -= BytesPerFormatCharacter;
+ Format -= BytesPerFormatCharacter;
}
+
break;
case '\n':
//
// Translate '\n' to '\r\n' and '\n\r' to '\r\n'
//
- ArgumentString = "\r\n";
- Format += BytesPerFormatCharacter;
+ ArgumentString = "\r\n";
+ Format += BytesPerFormatCharacter;
FormatCharacter = ((*Format & 0xff) | ((BytesPerFormatCharacter == 1) ? 0 : (*(Format + 1) << 8))) & FormatMask;
if (FormatCharacter != '\r') {
- Format -= BytesPerFormatCharacter;
+ Format -= BytesPerFormatCharacter;
}
+
break;
- case '%':
default:
- //
- // if the type is '%' or unknown, then print it to the screen
- //
ArgumentString = (CHAR8 *)&FormatCharacter;
- Flags |= ARGUMENT_UNICODE;
+ Flags |= ARGUMENT_UNICODE;
break;
- }
- break;
-
- case '\r':
- Format += BytesPerFormatCharacter;
- FormatCharacter = ((*Format & 0xff) | ((BytesPerFormatCharacter == 1) ? 0 : (*(Format + 1) << 8))) & FormatMask;
- if (FormatCharacter == '\n') {
- //
- // Translate '\r\n' to '\r\n'
- //
- ArgumentString = "\r\n";
- } else {
- //
- // Translate '\r' to '\r'
- //
- ArgumentString = "\r";
- Format -= BytesPerFormatCharacter;
- }
- break;
-
- case '\n':
- //
- // Translate '\n' to '\r\n' and '\n\r' to '\r\n'
- //
- ArgumentString = "\r\n";
- Format += BytesPerFormatCharacter;
- FormatCharacter = ((*Format & 0xff) | ((BytesPerFormatCharacter == 1) ? 0 : (*(Format + 1) << 8))) & FormatMask;
- if (FormatCharacter != '\r') {
- Format -= BytesPerFormatCharacter;
- }
- break;
-
- default:
- ArgumentString = (CHAR8 *)&FormatCharacter;
- Flags |= ARGUMENT_UNICODE;
- break;
}
//
// Retrieve the ArgumentString attriubutes
//
if ((Flags & ARGUMENT_UNICODE) != 0) {
- ArgumentMask = 0xffff;
+ ArgumentMask = 0xffff;
BytesPerArgumentCharacter = 2;
} else {
- ArgumentMask = 0xff;
+ ArgumentMask = 0xff;
BytesPerArgumentCharacter = 1;
}
+
if ((Flags & ARGUMENT_REVERSED) != 0) {
BytesPerArgumentCharacter = -BytesPerArgumentCharacter;
} else {
@@ -1115,11 +1163,12 @@ BasePrintLibSPrintMarker (
// ArgumentString is either null-terminated, or it contains Precision characters
//
for (Count = 0;
- (ArgumentString[Count * BytesPerArgumentCharacter] != '\0' ||
- (BytesPerArgumentCharacter > 1 &&
- ArgumentString[Count * BytesPerArgumentCharacter + 1]!= '\0')) &&
- (Count < Precision || ((Flags & PRECISION) == 0));
- Count++) {
+ (ArgumentString[Count * BytesPerArgumentCharacter] != '\0' ||
+ (BytesPerArgumentCharacter > 1 &&
+ ArgumentString[Count * BytesPerArgumentCharacter + 1] != '\0')) &&
+ (Count < Precision || ((Flags & PRECISION) == 0));
+ Count++)
+ {
ArgumentCharacter = ((ArgumentString[Count * BytesPerArgumentCharacter] & 0xff) | ((ArgumentString[Count * BytesPerArgumentCharacter + 1]) << 8)) & ArgumentMask;
if (ArgumentCharacter == 0) {
break;
@@ -1136,7 +1185,7 @@ BasePrintLibSPrintMarker (
//
if ((Flags & (PAD_TO_WIDTH | LEFT_JUSTIFY)) == (PAD_TO_WIDTH)) {
LengthToReturn += ((Width - Precision) * BytesPerOutputCharacter);
- if ((Flags & COUNT_ONLY_NO_PRINT) == 0 && Buffer != NULL) {
+ if (((Flags & COUNT_ONLY_NO_PRINT) == 0) && (Buffer != NULL)) {
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, Width - Precision, ' ', BytesPerOutputCharacter);
}
}
@@ -1144,22 +1193,24 @@ BasePrintLibSPrintMarker (
if (ZeroPad) {
if (Prefix != 0) {
LengthToReturn += (1 * BytesPerOutputCharacter);
- if ((Flags & COUNT_ONLY_NO_PRINT) == 0 && Buffer != NULL) {
+ if (((Flags & COUNT_ONLY_NO_PRINT) == 0) && (Buffer != NULL)) {
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, 1, Prefix, BytesPerOutputCharacter);
}
}
+
LengthToReturn += ((Precision - Count) * BytesPerOutputCharacter);
- if ((Flags & COUNT_ONLY_NO_PRINT) == 0 && Buffer != NULL) {
+ if (((Flags & COUNT_ONLY_NO_PRINT) == 0) && (Buffer != NULL)) {
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, Precision - Count, '0', BytesPerOutputCharacter);
}
} else {
LengthToReturn += ((Precision - Count) * BytesPerOutputCharacter);
- if ((Flags & COUNT_ONLY_NO_PRINT) == 0 && Buffer != NULL) {
+ if (((Flags & COUNT_ONLY_NO_PRINT) == 0) && (Buffer != NULL)) {
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, Precision - Count, ' ', BytesPerOutputCharacter);
}
+
if (Prefix != 0) {
LengthToReturn += (1 * BytesPerOutputCharacter);
- if ((Flags & COUNT_ONLY_NO_PRINT) == 0 && Buffer != NULL) {
+ if (((Flags & COUNT_ONLY_NO_PRINT) == 0) && (Buffer != NULL)) {
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, 1, Prefix, BytesPerOutputCharacter);
}
}
@@ -1178,14 +1229,16 @@ BasePrintLibSPrintMarker (
//
while (Index < Count &&
(ArgumentString[0] != '\0' ||
- (BytesPerArgumentCharacter > 1 && ArgumentString[1] != '\0'))) {
+ (BytesPerArgumentCharacter > 1 && ArgumentString[1] != '\0')))
+ {
ArgumentCharacter = ((*ArgumentString & 0xff) | (((UINT8)*(ArgumentString + 1)) << 8)) & ArgumentMask;
LengthToReturn += (1 * BytesPerOutputCharacter);
- if ((Flags & COUNT_ONLY_NO_PRINT) == 0 && Buffer != NULL) {
+ if (((Flags & COUNT_ONLY_NO_PRINT) == 0) && (Buffer != NULL)) {
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, 1, ArgumentCharacter, BytesPerOutputCharacter);
}
- ArgumentString += BytesPerArgumentCharacter;
+
+ ArgumentString += BytesPerArgumentCharacter;
Index++;
if (Comma) {
Digits++;
@@ -1194,7 +1247,7 @@ BasePrintLibSPrintMarker (
Index++;
if (Index < Count) {
LengthToReturn += (1 * BytesPerOutputCharacter);
- if ((Flags & COUNT_ONLY_NO_PRINT) == 0 && Buffer != NULL) {
+ if (((Flags & COUNT_ONLY_NO_PRINT) == 0) && (Buffer != NULL)) {
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, 1, ',', BytesPerOutputCharacter);
}
}
@@ -1207,7 +1260,7 @@ BasePrintLibSPrintMarker (
//
if ((Flags & (PAD_TO_WIDTH | LEFT_JUSTIFY)) == (PAD_TO_WIDTH | LEFT_JUSTIFY)) {
LengthToReturn += ((Width - Precision) * BytesPerOutputCharacter);
- if ((Flags & COUNT_ONLY_NO_PRINT) == 0 && Buffer != NULL) {
+ if (((Flags & COUNT_ONLY_NO_PRINT) == 0) && (Buffer != NULL)) {
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, Width - Precision, ' ', BytesPerOutputCharacter);
}
}
diff --git a/MdePkg/Library/BasePrintLib/PrintLibInternal.h b/MdePkg/Library/BasePrintLib/PrintLibInternal.h
index 86b98233..8a5062d1 100644
--- a/MdePkg/Library/BasePrintLib/PrintLibInternal.h
+++ b/MdePkg/Library/BasePrintLib/PrintLibInternal.h
@@ -15,37 +15,36 @@
#include
#include
-
//
// Print primitives
//
-#define PREFIX_SIGN BIT1
-#define PREFIX_BLANK BIT2
-#define LONG_TYPE BIT4
-#define OUTPUT_UNICODE BIT6
-#define FORMAT_UNICODE BIT8
-#define PAD_TO_WIDTH BIT9
-#define ARGUMENT_UNICODE BIT10
-#define PRECISION BIT11
-#define ARGUMENT_REVERSED BIT12
-#define COUNT_ONLY_NO_PRINT BIT13
-#define UNSIGNED_TYPE BIT14
+#define PREFIX_SIGN BIT1
+#define PREFIX_BLANK BIT2
+#define LONG_TYPE BIT4
+#define OUTPUT_UNICODE BIT6
+#define FORMAT_UNICODE BIT8
+#define PAD_TO_WIDTH BIT9
+#define ARGUMENT_UNICODE BIT10
+#define PRECISION BIT11
+#define ARGUMENT_REVERSED BIT12
+#define COUNT_ONLY_NO_PRINT BIT13
+#define UNSIGNED_TYPE BIT14
//
// Record date and time information
//
typedef struct {
- UINT16 Year;
- UINT8 Month;
- UINT8 Day;
- UINT8 Hour;
- UINT8 Minute;
- UINT8 Second;
- UINT8 Pad1;
- UINT32 Nanosecond;
- INT16 TimeZone;
- UINT8 Daylight;
- UINT8 Pad2;
+ UINT16 Year;
+ UINT8 Month;
+ UINT8 Day;
+ UINT8 Hour;
+ UINT8 Minute;
+ UINT8 Second;
+ UINT8 Pad1;
+ UINT32 Nanosecond;
+ INT16 TimeZone;
+ UINT8 Daylight;
+ UINT8 Pad2;
} TIME;
/**
@@ -82,7 +81,7 @@ BasePrintLibSPrintMarker (
IN UINTN BufferSize,
IN UINTN Flags,
IN CONST CHAR8 *Format,
- IN VA_LIST VaListMarker, OPTIONAL
+ IN VA_LIST VaListMarker OPTIONAL,
IN BASE_LIST BaseListMarker OPTIONAL
);
@@ -134,11 +133,11 @@ BasePrintLibSPrint (
**/
CHAR8 *
BasePrintLibFillBuffer (
- OUT CHAR8 *Buffer,
- IN CHAR8 *EndBuffer,
- IN INTN Length,
- IN UINTN Character,
- IN INTN Increment
+ OUT CHAR8 *Buffer,
+ IN CHAR8 *EndBuffer,
+ IN INTN Length,
+ IN UINTN Character,
+ IN INTN Increment
);
/**
@@ -200,11 +199,11 @@ BasePrintLibValueToString (
**/
UINTN
BasePrintLibConvertValueToString (
- IN OUT CHAR8 *Buffer,
- IN UINTN Flags,
- IN INT64 Value,
- IN UINTN Width,
- IN UINTN Increment
+ IN OUT CHAR8 *Buffer,
+ IN UINTN Flags,
+ IN INT64 Value,
+ IN UINTN Width,
+ IN UINTN Increment
);
/**
@@ -260,12 +259,12 @@ BasePrintLibConvertValueToString (
**/
RETURN_STATUS
BasePrintLibConvertValueToStringS (
- IN OUT CHAR8 *Buffer,
- IN UINTN BufferSize,
- IN UINTN Flags,
- IN INT64 Value,
- IN UINTN Width,
- IN UINTN Increment
+ IN OUT CHAR8 *Buffer,
+ IN UINTN BufferSize,
+ IN UINTN Flags,
+ IN INT64 Value,
+ IN UINTN Width,
+ IN UINTN Increment
);
#endif
diff --git a/MdePkg/Library/BaseRngLib/BaseRng.c b/MdePkg/Library/BaseRngLib/BaseRng.c
index e6573e42..7bc4ede7 100644
--- a/MdePkg/Library/BaseRngLib/BaseRng.c
+++ b/MdePkg/Library/BaseRngLib/BaseRng.c
@@ -19,8 +19,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// Uses the recommended value defined in Section 7.3.17 of "Intel 64 and IA-32
// Architectures Software Developer's Manual".
//
-#define GETRANDOM_RETRY_LIMIT 10
-
+#define GETRANDOM_RETRY_LIMIT 10
/**
Generates a 16-bit random number.
@@ -36,7 +35,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
BOOLEAN
EFIAPI
GetRandomNumber16 (
- OUT UINT16 *Rand
+ OUT UINT16 *Rand
)
{
UINT32 Index;
@@ -77,7 +76,7 @@ GetRandomNumber16 (
BOOLEAN
EFIAPI
GetRandomNumber32 (
- OUT UINT32 *Rand
+ OUT UINT32 *Rand
)
{
UINT32 Index;
@@ -118,7 +117,7 @@ GetRandomNumber32 (
BOOLEAN
EFIAPI
GetRandomNumber64 (
- OUT UINT64 *Rand
+ OUT UINT64 *Rand
)
{
UINT32 Index;
@@ -159,7 +158,7 @@ GetRandomNumber64 (
BOOLEAN
EFIAPI
GetRandomNumber128 (
- OUT UINT64 *Rand
+ OUT UINT64 *Rand
)
{
ASSERT (Rand != NULL);
diff --git a/MdePkg/Library/BaseRngLib/BaseRngLib.inf b/MdePkg/Library/BaseRngLib/BaseRngLib.inf
index e546efe9..f72c037c 100644
--- a/MdePkg/Library/BaseRngLib/BaseRngLib.inf
+++ b/MdePkg/Library/BaseRngLib/BaseRngLib.inf
@@ -4,6 +4,7 @@
# BaseRng Library that uses CPU RNG instructions (e.g. RdRand) to
# provide random numbers.
#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
# Copyright (c) 2021, NUVIA Inc. All rights reserved.
# Copyright (c) 2015, Intel Corporation. All rights reserved.
#
@@ -43,9 +44,18 @@
AArch64/ArmReadIdIsar0.asm | MSFT
AArch64/ArmRng.asm | MSFT
+[Guids.AARCH64]
+ gEfiRngAlgorithmArmRndr
+
+[Guids.Ia32, Guids.X64]
+ gEfiRngAlgorithmSp80090Ctr256Guid
+
[Packages]
MdePkg/MdePkg.dec
+[Pcd.AARCH64]
+ gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm
+
[LibraryClasses]
BaseLib
DebugLib
diff --git a/MdePkg/Library/BaseRngLib/BaseRngLibInternals.h b/MdePkg/Library/BaseRngLib/BaseRngLibInternals.h
index 93d107ab..221f1580 100644
--- a/MdePkg/Library/BaseRngLib/BaseRngLibInternals.h
+++ b/MdePkg/Library/BaseRngLib/BaseRngLibInternals.h
@@ -9,6 +9,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef BASE_RNGLIB_INTERNALS_H_
+#define BASE_RNGLIB_INTERNALS_H_
/**
Generates a 16-bit random number.
@@ -22,7 +23,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
BOOLEAN
EFIAPI
ArchGetRandomNumber16 (
- OUT UINT16 *Rand
+ OUT UINT16 *Rand
);
/**
@@ -37,7 +38,7 @@ ArchGetRandomNumber16 (
BOOLEAN
EFIAPI
ArchGetRandomNumber32 (
- OUT UINT32 *Rand
+ OUT UINT32 *Rand
);
/**
@@ -52,7 +53,7 @@ ArchGetRandomNumber32 (
BOOLEAN
EFIAPI
ArchGetRandomNumber64 (
- OUT UINT64 *Rand
+ OUT UINT64 *Rand
);
/**
@@ -71,8 +72,8 @@ ArchIsRngSupported (
#if defined (MDE_CPU_AARCH64)
// RNDR, Random Number
-#define RNDR S3_3_C2_C4_0
+#define RNDR S3_3_C2_C4_0
#endif
-#endif // BASE_RNGLIB_INTERNALS_H_
+#endif // BASE_RNGLIB_INTERNALS_H_
diff --git a/MdePkg/Library/BaseRngLib/Rand/RdRand.c b/MdePkg/Library/BaseRngLib/Rand/RdRand.c
index d8834ab9..1444e50f 100644
--- a/MdePkg/Library/BaseRngLib/Rand/RdRand.c
+++ b/MdePkg/Library/BaseRngLib/Rand/RdRand.c
@@ -2,6 +2,7 @@
Random number generator services that uses RdRand instruction access
to provide high-quality random numbers.
+Copyright (c) 2023, Arm Limited. All rights reserved.
Copyright (c) 2021, NUVIA Inc. All rights reserved.
Copyright (c) 2015, Intel Corporation. All rights reserved.
@@ -11,6 +12,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include
#include
+#include
#include
#include "BaseRngLibInternals.h"
@@ -18,10 +20,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// Bit mask used to determine if RdRand instruction is supported.
//
-#define RDRAND_MASK BIT30
+#define RDRAND_MASK BIT30
-
-STATIC BOOLEAN mRdRandSupported;
+STATIC BOOLEAN mRdRandSupported;
/**
The constructor function checks whether or not RDRAND instruction is supported
@@ -66,7 +67,7 @@ BaseRngLibConstructor (
BOOLEAN
EFIAPI
ArchGetRandomNumber16 (
- OUT UINT16 *Rand
+ OUT UINT16 *Rand
)
{
return AsmRdRand16 (Rand);
@@ -84,7 +85,7 @@ ArchGetRandomNumber16 (
BOOLEAN
EFIAPI
ArchGetRandomNumber32 (
- OUT UINT32 *Rand
+ OUT UINT32 *Rand
)
{
return AsmRdRand32 (Rand);
@@ -102,7 +103,7 @@ ArchGetRandomNumber32 (
BOOLEAN
EFIAPI
ArchGetRandomNumber64 (
- OUT UINT64 *Rand
+ OUT UINT64 *Rand
)
{
return AsmRdRand64 (Rand);
@@ -129,3 +130,27 @@ ArchIsRngSupported (
*/
return TRUE;
}
+
+/**
+ Get a GUID identifying the RNG algorithm implementation.
+
+ @param [out] RngGuid If success, contains the GUID identifying
+ the RNG algorithm implementation.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_UNSUPPORTED Not supported.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+**/
+EFI_STATUS
+EFIAPI
+GetRngGuid (
+ GUID *RngGuid
+ )
+{
+ if (RngGuid == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ CopyMem (RngGuid, &gEfiRngAlgorithmSp80090Ctr256Guid, sizeof (*RngGuid));
+ return EFI_SUCCESS;
+}
diff --git a/MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.c b/MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.c
index 44d114b7..559d5597 100644
--- a/MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.c
+++ b/MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.c
@@ -6,7 +6,6 @@
**/
-
#include
#include
@@ -50,14 +49,13 @@ SerialPortInitialize (
UINTN
EFIAPI
SerialPortWrite (
- IN UINT8 *Buffer,
- IN UINTN NumberOfBytes
-)
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ )
{
return 0;
}
-
/**
Read data from serial device and save the datas in buffer.
@@ -77,9 +75,9 @@ SerialPortWrite (
UINTN
EFIAPI
SerialPortRead (
- OUT UINT8 *Buffer,
- IN UINTN NumberOfBytes
-)
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ )
{
return 0;
}
@@ -117,7 +115,7 @@ SerialPortPoll (
RETURN_STATUS
EFIAPI
SerialPortSetControl (
- IN UINT32 Control
+ IN UINT32 Control
)
{
return RETURN_UNSUPPORTED;
@@ -136,7 +134,7 @@ SerialPortSetControl (
RETURN_STATUS
EFIAPI
SerialPortGetControl (
- OUT UINT32 *Control
+ OUT UINT32 *Control
)
{
return RETURN_UNSUPPORTED;
@@ -178,14 +176,13 @@ SerialPortGetControl (
RETURN_STATUS
EFIAPI
SerialPortSetAttributes (
- IN OUT UINT64 *BaudRate,
- IN OUT UINT32 *ReceiveFifoDepth,
- IN OUT UINT32 *Timeout,
- IN OUT EFI_PARITY_TYPE *Parity,
- IN OUT UINT8 *DataBits,
- IN OUT EFI_STOP_BITS_TYPE *StopBits
+ IN OUT UINT64 *BaudRate,
+ IN OUT UINT32 *ReceiveFifoDepth,
+ IN OUT UINT32 *Timeout,
+ IN OUT EFI_PARITY_TYPE *Parity,
+ IN OUT UINT8 *DataBits,
+ IN OUT EFI_STOP_BITS_TYPE *StopBits
)
{
return RETURN_UNSUPPORTED;
}
-
diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
index 327bef03..38901c91 100644
--- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
@@ -4,6 +4,7 @@
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -71,7 +72,6 @@
[Sources.ARM]
Synchronization.c
- Arm/Synchronization.asm | RVCT
Arm/Synchronization.S | GCC
[Sources.AARCH64]
@@ -81,7 +81,12 @@
[Sources.RISCV64]
Synchronization.c
- RiscV64/Synchronization.S
+ RiscV64/Synchronization.S | GCC
+
+[Sources.LOONGARCH64]
+ Synchronization.c
+ LoongArch64/Synchronization.c | GCC
+ LoongArch64/AsmSynchronization.S | GCC
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLibInternals.h b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLibInternals.h
index c24701e6..837e5fa1 100644
--- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLibInternals.h
+++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLibInternals.h
@@ -31,10 +31,9 @@
UINT32
EFIAPI
InternalSyncIncrement (
- IN volatile UINT32 *Value
+ IN volatile UINT32 *Value
);
-
/**
Performs an atomic decrement of an 32-bit unsigned integer.
@@ -50,10 +49,9 @@ InternalSyncIncrement (
UINT32
EFIAPI
InternalSyncDecrement (
- IN volatile UINT32 *Value
+ IN volatile UINT32 *Value
);
-
/**
Performs an atomic compare exchange operation on a 16-bit unsigned integer.
@@ -74,12 +72,11 @@ InternalSyncDecrement (
UINT16
EFIAPI
InternalSyncCompareExchange16 (
- IN volatile UINT16 *Value,
- IN UINT16 CompareValue,
- IN UINT16 ExchangeValue
+ IN volatile UINT16 *Value,
+ IN UINT16 CompareValue,
+ IN UINT16 ExchangeValue
);
-
/**
Performs an atomic compare exchange operation on a 32-bit unsigned integer.
@@ -100,12 +97,11 @@ InternalSyncCompareExchange16 (
UINT32
EFIAPI
InternalSyncCompareExchange32 (
- IN volatile UINT32 *Value,
- IN UINT32 CompareValue,
- IN UINT32 ExchangeValue
+ IN volatile UINT32 *Value,
+ IN UINT32 CompareValue,
+ IN UINT32 ExchangeValue
);
-
/**
Performs an atomic compare exchange operation on a 64-bit unsigned integer.
@@ -125,9 +121,9 @@ InternalSyncCompareExchange32 (
UINT64
EFIAPI
InternalSyncCompareExchange64 (
- IN volatile UINT64 *Value,
- IN UINT64 CompareValue,
- IN UINT64 ExchangeValue
+ IN volatile UINT64 *Value,
+ IN UINT64 CompareValue,
+ IN UINT64 ExchangeValue
);
/**
diff --git a/MdePkg/Library/BaseSynchronizationLib/Ia32/GccInline.c b/MdePkg/Library/BaseSynchronizationLib/Ia32/GccInline.c
index 7c9f1673..49283ba4 100644
--- a/MdePkg/Library/BaseSynchronizationLib/Ia32/GccInline.c
+++ b/MdePkg/Library/BaseSynchronizationLib/Ia32/GccInline.c
@@ -7,8 +7,6 @@
**/
-
-
/**
Performs an atomic increment of an 32-bit unsigned integer.
@@ -24,7 +22,7 @@
UINT32
EFIAPI
InternalSyncIncrement (
- IN volatile UINT32 *Value
+ IN volatile UINT32 *Value
)
{
UINT32 Result;
@@ -39,12 +37,11 @@ InternalSyncIncrement (
: // no inputs that aren't also outputs
: "memory",
"cc"
- );
+ );
return Result;
}
-
/**
Performs an atomic decrement of an 32-bit unsigned integer.
@@ -60,10 +57,10 @@ InternalSyncIncrement (
UINT32
EFIAPI
InternalSyncDecrement (
- IN volatile UINT32 *Value
+ IN volatile UINT32 *Value
)
{
- UINT32 Result;
+ UINT32 Result;
__asm__ __volatile__ (
"movl $-1, %%eax \n\t"
@@ -75,12 +72,11 @@ InternalSyncDecrement (
: // no inputs that aren't also outputs
: "memory",
"cc"
- );
+ );
return Result;
}
-
/**
Performs an atomic compare exchange operation on a 16-bit unsigned integer.
@@ -102,9 +98,9 @@ InternalSyncDecrement (
UINT16
EFIAPI
InternalSyncCompareExchange16 (
- IN OUT volatile UINT16 *Value,
- IN UINT16 CompareValue,
- IN UINT16 ExchangeValue
+ IN OUT volatile UINT16 *Value,
+ IN UINT16 CompareValue,
+ IN UINT16 ExchangeValue
)
{
__asm__ __volatile__ (
@@ -115,12 +111,11 @@ InternalSyncCompareExchange16 (
: "q" (ExchangeValue) // %2
: "memory",
"cc"
- );
+ );
return CompareValue;
}
-
/**
Performs an atomic compare exchange operation on a 32-bit unsigned integer.
@@ -142,9 +137,9 @@ InternalSyncCompareExchange16 (
UINT32
EFIAPI
InternalSyncCompareExchange32 (
- IN OUT volatile UINT32 *Value,
- IN UINT32 CompareValue,
- IN UINT32 ExchangeValue
+ IN OUT volatile UINT32 *Value,
+ IN UINT32 CompareValue,
+ IN UINT32 ExchangeValue
)
{
__asm__ __volatile__ (
@@ -155,12 +150,11 @@ InternalSyncCompareExchange32 (
: "q" (ExchangeValue) // %2
: "memory",
"cc"
- );
+ );
return CompareValue;
}
-
/**
Performs an atomic compare exchange operation on a 64-bit unsigned integer.
@@ -181,9 +175,9 @@ InternalSyncCompareExchange32 (
UINT64
EFIAPI
InternalSyncCompareExchange64 (
- IN OUT volatile UINT64 *Value,
- IN UINT64 CompareValue,
- IN UINT64 ExchangeValue
+ IN OUT volatile UINT64 *Value,
+ IN UINT64 CompareValue,
+ IN UINT64 ExchangeValue
)
{
__asm__ __volatile__ (
@@ -195,7 +189,7 @@ InternalSyncCompareExchange64 (
"c" ((UINT32) (ExchangeValue >> 32)) // %3
: "memory",
"cc"
- );
+ );
return CompareValue;
}
diff --git a/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange16.c b/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange16.c
index 6680a551..17d74aa0 100644
--- a/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange16.c
+++ b/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange16.c
@@ -7,9 +7,6 @@
**/
-
-
-
/**
Performs an atomic compare exchange operation on a 16-bit unsigned integer.
@@ -30,9 +27,9 @@
UINT16
EFIAPI
InternalSyncCompareExchange16 (
- IN volatile UINT16 *Value,
- IN UINT16 CompareValue,
- IN UINT16 ExchangeValue
+ IN volatile UINT16 *Value,
+ IN UINT16 CompareValue,
+ IN UINT16 ExchangeValue
)
{
_asm {
@@ -42,4 +39,3 @@ InternalSyncCompareExchange16 (
lock cmpxchg [ecx], dx
}
}
-
diff --git a/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange32.c b/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange32.c
index 21b02095..91d7ff18 100644
--- a/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange32.c
+++ b/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange32.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Performs an atomic compare exchange operation on a 32-bit unsigned integer.
@@ -29,9 +26,9 @@
UINT32
EFIAPI
InternalSyncCompareExchange32 (
- IN volatile UINT32 *Value,
- IN UINT32 CompareValue,
- IN UINT32 ExchangeValue
+ IN volatile UINT32 *Value,
+ IN UINT32 CompareValue,
+ IN UINT32 ExchangeValue
)
{
_asm {
@@ -41,4 +38,3 @@ InternalSyncCompareExchange32 (
lock cmpxchg [ecx], edx
}
}
-
diff --git a/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange64.c b/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange64.c
index 9c0572ce..10590543 100644
--- a/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange64.c
+++ b/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange64.c
@@ -6,9 +6,6 @@
**/
-
-
-
/**
Performs an atomic compare exchange operation on a 64-bit unsigned integer.
@@ -28,9 +25,9 @@
UINT64
EFIAPI
InternalSyncCompareExchange64 (
- IN volatile UINT64 *Value,
- IN UINT64 CompareValue,
- IN UINT64 ExchangeValue
+ IN volatile UINT64 *Value,
+ IN UINT64 CompareValue,
+ IN UINT64 ExchangeValue
)
{
_asm {
diff --git a/MdePkg/Library/BaseSynchronizationLib/Ia32/InternalGetSpinLockProperties.c b/MdePkg/Library/BaseSynchronizationLib/Ia32/InternalGetSpinLockProperties.c
index 7b0de3dc..e8c3a9ec 100644
--- a/MdePkg/Library/BaseSynchronizationLib/Ia32/InternalGetSpinLockProperties.c
+++ b/MdePkg/Library/BaseSynchronizationLib/Ia32/InternalGetSpinLockProperties.c
@@ -44,7 +44,7 @@ InternalGetSpinLockProperties (
// In processors based on Intel NetBurst microarchitecture, use two cache lines
//
ModelId = ModelId | ((RegEax >> 12) & 0xf0);
- if (ModelId <= 0x04 || ModelId == 0x06) {
+ if ((ModelId <= 0x04) || (ModelId == 0x06)) {
CacheLineSize *= 2;
}
}
@@ -55,4 +55,3 @@ InternalGetSpinLockProperties (
return CacheLineSize;
}
-
diff --git a/MdePkg/Library/BaseSynchronizationLib/InterlockedDecrementMsc.c b/MdePkg/Library/BaseSynchronizationLib/InterlockedDecrementMsc.c
index eef8783c..23ac6d7a 100644
--- a/MdePkg/Library/BaseSynchronizationLib/InterlockedDecrementMsc.c
+++ b/MdePkg/Library/BaseSynchronizationLib/InterlockedDecrementMsc.c
@@ -10,9 +10,10 @@
Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
**/
-long _InterlockedDecrement(
- long * lpAddend
-);
+long
+_InterlockedDecrement (
+ long *lpAddend
+ );
#pragma intrinsic(_InterlockedDecrement)
@@ -32,9 +33,8 @@ long _InterlockedDecrement(
UINT32
EFIAPI
InternalSyncDecrement (
- IN volatile UINT32 *Value
+ IN volatile UINT32 *Value
)
{
return _InterlockedDecrement ((long *)(Value));
}
-
diff --git a/MdePkg/Library/BaseSynchronizationLib/InterlockedIncrementMsc.c b/MdePkg/Library/BaseSynchronizationLib/InterlockedIncrementMsc.c
index ebd9349c..29203246 100644
--- a/MdePkg/Library/BaseSynchronizationLib/InterlockedIncrementMsc.c
+++ b/MdePkg/Library/BaseSynchronizationLib/InterlockedIncrementMsc.c
@@ -10,9 +10,10 @@
Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
**/
-long _InterlockedIncrement(
- long * lpAddend
-);
+long
+_InterlockedIncrement (
+ long *lpAddend
+ );
#pragma intrinsic(_InterlockedIncrement)
@@ -32,9 +33,8 @@ long _InterlockedIncrement(
UINT32
EFIAPI
InternalSyncIncrement (
- IN volatile UINT32 *Value
+ IN volatile UINT32 *Value
)
{
return _InterlockedIncrement ((long *)(Value));
}
-
diff --git a/MdePkg/Library/BaseSynchronizationLib/Synchronization.c b/MdePkg/Library/BaseSynchronizationLib/Synchronization.c
index 8ea2843c..4f402b03 100644
--- a/MdePkg/Library/BaseSynchronizationLib/Synchronization.c
+++ b/MdePkg/Library/BaseSynchronizationLib/Synchronization.c
@@ -8,8 +8,8 @@
#include "BaseSynchronizationLibInternals.h"
-#define SPIN_LOCK_RELEASED ((UINTN) 1)
-#define SPIN_LOCK_ACQUIRED ((UINTN) 2)
+#define SPIN_LOCK_RELEASED ((UINTN) 1)
+#define SPIN_LOCK_ACQUIRED ((UINTN) 2)
/**
Retrieves the architecture specific spin lock alignment requirements for
@@ -55,7 +55,7 @@ GetSpinLockProperties (
SPIN_LOCK *
EFIAPI
InitializeSpinLock (
- OUT SPIN_LOCK *SpinLock
+ OUT SPIN_LOCK *SpinLock
)
{
ASSERT (SpinLock != NULL);
@@ -86,7 +86,7 @@ InitializeSpinLock (
SPIN_LOCK *
EFIAPI
AcquireSpinLock (
- IN OUT SPIN_LOCK *SpinLock
+ IN OUT SPIN_LOCK *SpinLock
)
{
UINT64 Current;
@@ -106,7 +106,7 @@ AcquireSpinLock (
//
// Get the current timer value
//
- Current = GetPerformanceCounter();
+ Current = GetPerformanceCounter ();
//
// Initialize local variables
@@ -130,23 +130,27 @@ AcquireSpinLock (
if (Cycle < 0) {
Cycle = -Cycle;
}
+
Cycle++;
while (!AcquireSpinLockOrFail (SpinLock)) {
CpuPause ();
Previous = Current;
- Current = GetPerformanceCounter();
- Delta = (INT64) (Current - Previous);
+ Current = GetPerformanceCounter ();
+ Delta = (INT64)(Current - Previous);
if (Start > End) {
Delta = -Delta;
}
+
if (Delta < 0) {
Delta += Cycle;
}
+
Total += Delta;
ASSERT (Total < Timeout);
}
}
+
return SpinLock;
}
@@ -170,10 +174,10 @@ AcquireSpinLock (
BOOLEAN
EFIAPI
AcquireSpinLockOrFail (
- IN OUT SPIN_LOCK *SpinLock
+ IN OUT SPIN_LOCK *SpinLock
)
{
- SPIN_LOCK LockValue;
+ SPIN_LOCK LockValue;
ASSERT (SpinLock != NULL);
@@ -181,12 +185,12 @@ AcquireSpinLockOrFail (
ASSERT (SPIN_LOCK_ACQUIRED == LockValue || SPIN_LOCK_RELEASED == LockValue);
return (BOOLEAN)(
- InterlockedCompareExchangePointer (
- (VOID**)SpinLock,
- (VOID*)SPIN_LOCK_RELEASED,
- (VOID*)SPIN_LOCK_ACQUIRED
- ) == (VOID*)SPIN_LOCK_RELEASED
- );
+ InterlockedCompareExchangePointer (
+ (VOID **)SpinLock,
+ (VOID *)SPIN_LOCK_RELEASED,
+ (VOID *)SPIN_LOCK_ACQUIRED
+ ) == (VOID *)SPIN_LOCK_RELEASED
+ );
}
/**
@@ -206,10 +210,10 @@ AcquireSpinLockOrFail (
SPIN_LOCK *
EFIAPI
ReleaseSpinLock (
- IN OUT SPIN_LOCK *SpinLock
+ IN OUT SPIN_LOCK *SpinLock
)
{
- SPIN_LOCK LockValue;
+ SPIN_LOCK LockValue;
ASSERT (SpinLock != NULL);
@@ -237,7 +241,7 @@ ReleaseSpinLock (
UINT32
EFIAPI
InterlockedIncrement (
- IN volatile UINT32 *Value
+ IN volatile UINT32 *Value
)
{
ASSERT (Value != NULL);
@@ -261,7 +265,7 @@ InterlockedIncrement (
UINT32
EFIAPI
InterlockedDecrement (
- IN volatile UINT32 *Value
+ IN volatile UINT32 *Value
)
{
ASSERT (Value != NULL);
@@ -290,9 +294,9 @@ InterlockedDecrement (
UINT16
EFIAPI
InterlockedCompareExchange16 (
- IN OUT volatile UINT16 *Value,
- IN UINT16 CompareValue,
- IN UINT16 ExchangeValue
+ IN OUT volatile UINT16 *Value,
+ IN UINT16 CompareValue,
+ IN UINT16 ExchangeValue
)
{
ASSERT (Value != NULL);
@@ -321,9 +325,9 @@ InterlockedCompareExchange16 (
UINT32
EFIAPI
InterlockedCompareExchange32 (
- IN OUT volatile UINT32 *Value,
- IN UINT32 CompareValue,
- IN UINT32 ExchangeValue
+ IN OUT volatile UINT32 *Value,
+ IN UINT32 CompareValue,
+ IN UINT32 ExchangeValue
)
{
ASSERT (Value != NULL);
@@ -351,9 +355,9 @@ InterlockedCompareExchange32 (
UINT64
EFIAPI
InterlockedCompareExchange64 (
- IN OUT volatile UINT64 *Value,
- IN UINT64 CompareValue,
- IN UINT64 ExchangeValue
+ IN OUT volatile UINT64 *Value,
+ IN UINT64 CompareValue,
+ IN UINT64 ExchangeValue
)
{
ASSERT (Value != NULL);
@@ -381,9 +385,9 @@ InterlockedCompareExchange64 (
VOID *
EFIAPI
InterlockedCompareExchangePointer (
- IN OUT VOID * volatile *Value,
- IN VOID *CompareValue,
- IN VOID *ExchangeValue
+ IN OUT VOID *volatile *Value,
+ IN VOID *CompareValue,
+ IN VOID *ExchangeValue
)
{
UINT8 SizeOfValue;
@@ -392,17 +396,17 @@ InterlockedCompareExchangePointer (
switch (SizeOfValue) {
case sizeof (UINT32):
- return (VOID*)(UINTN)InterlockedCompareExchange32 (
- (volatile UINT32 *)Value,
- (UINT32)(UINTN)CompareValue,
- (UINT32)(UINTN)ExchangeValue
- );
+ return (VOID *)(UINTN)InterlockedCompareExchange32 (
+ (volatile UINT32 *)Value,
+ (UINT32)(UINTN)CompareValue,
+ (UINT32)(UINTN)ExchangeValue
+ );
case sizeof (UINT64):
- return (VOID*)(UINTN)InterlockedCompareExchange64 (
- (volatile UINT64 *)Value,
- (UINT64)(UINTN)CompareValue,
- (UINT64)(UINTN)ExchangeValue
- );
+ return (VOID *)(UINTN)InterlockedCompareExchange64 (
+ (volatile UINT64 *)Value,
+ (UINT64)(UINTN)CompareValue,
+ (UINT64)(UINTN)ExchangeValue
+ );
default:
ASSERT (FALSE);
return NULL;
diff --git a/MdePkg/Library/BaseSynchronizationLib/SynchronizationGcc.c b/MdePkg/Library/BaseSynchronizationLib/SynchronizationGcc.c
index 5ea87c17..753d0327 100644
--- a/MdePkg/Library/BaseSynchronizationLib/SynchronizationGcc.c
+++ b/MdePkg/Library/BaseSynchronizationLib/SynchronizationGcc.c
@@ -12,10 +12,10 @@
//
// GCC inline assembly for Read Write Barrier
//
-#define _ReadWriteBarrier() do { __asm__ __volatile__ ("": : : "memory"); } while(0)
+#define _ReadWriteBarrier() do { __asm__ __volatile__ ("": : : "memory"); } while(0)
-#define SPIN_LOCK_RELEASED ((UINTN) 1)
-#define SPIN_LOCK_ACQUIRED ((UINTN) 2)
+#define SPIN_LOCK_RELEASED ((UINTN) 1)
+#define SPIN_LOCK_ACQUIRED ((UINTN) 2)
/**
Retrieves the architecture specific spin lock alignment requirements for
@@ -61,14 +61,14 @@ GetSpinLockProperties (
SPIN_LOCK *
EFIAPI
InitializeSpinLock (
- OUT SPIN_LOCK *SpinLock
+ OUT SPIN_LOCK *SpinLock
)
{
ASSERT (SpinLock != NULL);
- _ReadWriteBarrier();
+ _ReadWriteBarrier ();
*SpinLock = SPIN_LOCK_RELEASED;
- _ReadWriteBarrier();
+ _ReadWriteBarrier ();
return SpinLock;
}
@@ -96,7 +96,7 @@ InitializeSpinLock (
SPIN_LOCK *
EFIAPI
AcquireSpinLock (
- IN OUT SPIN_LOCK *SpinLock
+ IN OUT SPIN_LOCK *SpinLock
)
{
UINT64 Current;
@@ -116,7 +116,7 @@ AcquireSpinLock (
//
// Get the current timer value
//
- Current = GetPerformanceCounter();
+ Current = GetPerformanceCounter ();
//
// Initialize local variables
@@ -140,23 +140,27 @@ AcquireSpinLock (
if (Cycle < 0) {
Cycle = -Cycle;
}
+
Cycle++;
while (!AcquireSpinLockOrFail (SpinLock)) {
CpuPause ();
Previous = Current;
- Current = GetPerformanceCounter();
- Delta = (INT64) (Current - Previous);
+ Current = GetPerformanceCounter ();
+ Delta = (INT64)(Current - Previous);
if (Start > End) {
Delta = -Delta;
}
+
if (Delta < 0) {
Delta += Cycle;
}
+
Total += Delta;
ASSERT (Total < Timeout);
}
}
+
return SpinLock;
}
@@ -180,11 +184,11 @@ AcquireSpinLock (
BOOLEAN
EFIAPI
AcquireSpinLockOrFail (
- IN OUT SPIN_LOCK *SpinLock
+ IN OUT SPIN_LOCK *SpinLock
)
{
- SPIN_LOCK LockValue;
- VOID *Result;
+ SPIN_LOCK LockValue;
+ VOID *Result;
ASSERT (SpinLock != NULL);
@@ -193,13 +197,13 @@ AcquireSpinLockOrFail (
_ReadWriteBarrier ();
Result = InterlockedCompareExchangePointer (
- (VOID**)SpinLock,
- (VOID*)SPIN_LOCK_RELEASED,
- (VOID*)SPIN_LOCK_ACQUIRED
- );
+ (VOID **)SpinLock,
+ (VOID *)SPIN_LOCK_RELEASED,
+ (VOID *)SPIN_LOCK_ACQUIRED
+ );
_ReadWriteBarrier ();
- return (BOOLEAN) (Result == (VOID*) SPIN_LOCK_RELEASED);
+ return (BOOLEAN)(Result == (VOID *)SPIN_LOCK_RELEASED);
}
/**
@@ -219,10 +223,10 @@ AcquireSpinLockOrFail (
SPIN_LOCK *
EFIAPI
ReleaseSpinLock (
- IN OUT SPIN_LOCK *SpinLock
+ IN OUT SPIN_LOCK *SpinLock
)
{
- SPIN_LOCK LockValue;
+ SPIN_LOCK LockValue;
ASSERT (SpinLock != NULL);
@@ -253,7 +257,7 @@ ReleaseSpinLock (
UINT32
EFIAPI
InterlockedIncrement (
- IN volatile UINT32 *Value
+ IN volatile UINT32 *Value
)
{
ASSERT (Value != NULL);
@@ -277,7 +281,7 @@ InterlockedIncrement (
UINT32
EFIAPI
InterlockedDecrement (
- IN volatile UINT32 *Value
+ IN volatile UINT32 *Value
)
{
ASSERT (Value != NULL);
@@ -306,9 +310,9 @@ InterlockedDecrement (
UINT16
EFIAPI
InterlockedCompareExchange16 (
- IN OUT volatile UINT16 *Value,
- IN UINT16 CompareValue,
- IN UINT16 ExchangeValue
+ IN OUT volatile UINT16 *Value,
+ IN UINT16 CompareValue,
+ IN UINT16 ExchangeValue
)
{
ASSERT (Value != NULL);
@@ -337,9 +341,9 @@ InterlockedCompareExchange16 (
UINT32
EFIAPI
InterlockedCompareExchange32 (
- IN OUT volatile UINT32 *Value,
- IN UINT32 CompareValue,
- IN UINT32 ExchangeValue
+ IN OUT volatile UINT32 *Value,
+ IN UINT32 CompareValue,
+ IN UINT32 ExchangeValue
)
{
ASSERT (Value != NULL);
@@ -367,9 +371,9 @@ InterlockedCompareExchange32 (
UINT64
EFIAPI
InterlockedCompareExchange64 (
- IN OUT volatile UINT64 *Value,
- IN UINT64 CompareValue,
- IN UINT64 ExchangeValue
+ IN OUT volatile UINT64 *Value,
+ IN UINT64 CompareValue,
+ IN UINT64 ExchangeValue
)
{
ASSERT (Value != NULL);
@@ -397,9 +401,9 @@ InterlockedCompareExchange64 (
VOID *
EFIAPI
InterlockedCompareExchangePointer (
- IN OUT VOID * volatile *Value,
- IN VOID *CompareValue,
- IN VOID *ExchangeValue
+ IN OUT VOID *volatile *Value,
+ IN VOID *CompareValue,
+ IN VOID *ExchangeValue
)
{
UINT8 SizeOfValue;
@@ -408,17 +412,17 @@ InterlockedCompareExchangePointer (
switch (SizeOfValue) {
case sizeof (UINT32):
- return (VOID*)(UINTN)InterlockedCompareExchange32 (
- (volatile UINT32 *)Value,
- (UINT32)(UINTN)CompareValue,
- (UINT32)(UINTN)ExchangeValue
- );
+ return (VOID *)(UINTN)InterlockedCompareExchange32 (
+ (volatile UINT32 *)Value,
+ (UINT32)(UINTN)CompareValue,
+ (UINT32)(UINTN)ExchangeValue
+ );
case sizeof (UINT64):
- return (VOID*)(UINTN)InterlockedCompareExchange64 (
- (volatile UINT64 *)Value,
- (UINT64)(UINTN)CompareValue,
- (UINT64)(UINTN)ExchangeValue
- );
+ return (VOID *)(UINTN)InterlockedCompareExchange64 (
+ (volatile UINT64 *)Value,
+ (UINT64)(UINTN)CompareValue,
+ (UINT64)(UINTN)ExchangeValue
+ );
default:
ASSERT (FALSE);
return NULL;
diff --git a/MdePkg/Library/BaseSynchronizationLib/SynchronizationMsc.c b/MdePkg/Library/BaseSynchronizationLib/SynchronizationMsc.c
index 3e136576..5acef573 100644
--- a/MdePkg/Library/BaseSynchronizationLib/SynchronizationMsc.c
+++ b/MdePkg/Library/BaseSynchronizationLib/SynchronizationMsc.c
@@ -12,12 +12,15 @@
Microsoft Visual Studio 7.1 Function Prototypes for read write barrier Intrinsics.
**/
-void _ReadWriteBarrier (void);
+void
+_ReadWriteBarrier (
+ void
+ );
+
#pragma intrinsic(_ReadWriteBarrier)
-
-#define SPIN_LOCK_RELEASED ((UINTN) 1)
-#define SPIN_LOCK_ACQUIRED ((UINTN) 2)
+#define SPIN_LOCK_RELEASED ((UINTN) 1)
+#define SPIN_LOCK_ACQUIRED ((UINTN) 2)
/**
Retrieves the architecture specific spin lock alignment requirements for
@@ -63,14 +66,14 @@ GetSpinLockProperties (
SPIN_LOCK *
EFIAPI
InitializeSpinLock (
- OUT SPIN_LOCK *SpinLock
+ OUT SPIN_LOCK *SpinLock
)
{
ASSERT (SpinLock != NULL);
- _ReadWriteBarrier();
+ _ReadWriteBarrier ();
*SpinLock = SPIN_LOCK_RELEASED;
- _ReadWriteBarrier();
+ _ReadWriteBarrier ();
return SpinLock;
}
@@ -98,7 +101,7 @@ InitializeSpinLock (
SPIN_LOCK *
EFIAPI
AcquireSpinLock (
- IN OUT SPIN_LOCK *SpinLock
+ IN OUT SPIN_LOCK *SpinLock
)
{
UINT64 Current;
@@ -118,7 +121,7 @@ AcquireSpinLock (
//
// Get the current timer value
//
- Current = GetPerformanceCounter();
+ Current = GetPerformanceCounter ();
//
// Initialize local variables
@@ -142,23 +145,27 @@ AcquireSpinLock (
if (Cycle < 0) {
Cycle = -Cycle;
}
+
Cycle++;
while (!AcquireSpinLockOrFail (SpinLock)) {
CpuPause ();
Previous = Current;
- Current = GetPerformanceCounter();
- Delta = (INT64) (Current - Previous);
+ Current = GetPerformanceCounter ();
+ Delta = (INT64)(Current - Previous);
if (Start > End) {
Delta = -Delta;
}
+
if (Delta < 0) {
Delta += Cycle;
}
+
Total += Delta;
ASSERT (Total < Timeout);
}
}
+
return SpinLock;
}
@@ -182,11 +189,11 @@ AcquireSpinLock (
BOOLEAN
EFIAPI
AcquireSpinLockOrFail (
- IN OUT SPIN_LOCK *SpinLock
+ IN OUT SPIN_LOCK *SpinLock
)
{
- SPIN_LOCK LockValue;
- VOID *Result;
+ SPIN_LOCK LockValue;
+ VOID *Result;
ASSERT (SpinLock != NULL);
@@ -195,13 +202,13 @@ AcquireSpinLockOrFail (
_ReadWriteBarrier ();
Result = InterlockedCompareExchangePointer (
- (VOID**)SpinLock,
- (VOID*)SPIN_LOCK_RELEASED,
- (VOID*)SPIN_LOCK_ACQUIRED
- );
+ (VOID **)SpinLock,
+ (VOID *)SPIN_LOCK_RELEASED,
+ (VOID *)SPIN_LOCK_ACQUIRED
+ );
_ReadWriteBarrier ();
- return (BOOLEAN) (Result == (VOID*) SPIN_LOCK_RELEASED);
+ return (BOOLEAN)(Result == (VOID *)SPIN_LOCK_RELEASED);
}
/**
@@ -221,10 +228,10 @@ AcquireSpinLockOrFail (
SPIN_LOCK *
EFIAPI
ReleaseSpinLock (
- IN OUT SPIN_LOCK *SpinLock
+ IN OUT SPIN_LOCK *SpinLock
)
{
- SPIN_LOCK LockValue;
+ SPIN_LOCK LockValue;
ASSERT (SpinLock != NULL);
@@ -255,7 +262,7 @@ ReleaseSpinLock (
UINT32
EFIAPI
InterlockedIncrement (
- IN volatile UINT32 *Value
+ IN volatile UINT32 *Value
)
{
ASSERT (Value != NULL);
@@ -279,7 +286,7 @@ InterlockedIncrement (
UINT32
EFIAPI
InterlockedDecrement (
- IN volatile UINT32 *Value
+ IN volatile UINT32 *Value
)
{
ASSERT (Value != NULL);
@@ -308,9 +315,9 @@ InterlockedDecrement (
UINT16
EFIAPI
InterlockedCompareExchange16 (
- IN OUT volatile UINT16 *Value,
- IN UINT16 CompareValue,
- IN UINT16 ExchangeValue
+ IN OUT volatile UINT16 *Value,
+ IN UINT16 CompareValue,
+ IN UINT16 ExchangeValue
)
{
ASSERT (Value != NULL);
@@ -339,9 +346,9 @@ InterlockedCompareExchange16 (
UINT32
EFIAPI
InterlockedCompareExchange32 (
- IN OUT volatile UINT32 *Value,
- IN UINT32 CompareValue,
- IN UINT32 ExchangeValue
+ IN OUT volatile UINT32 *Value,
+ IN UINT32 CompareValue,
+ IN UINT32 ExchangeValue
)
{
ASSERT (Value != NULL);
@@ -369,9 +376,9 @@ InterlockedCompareExchange32 (
UINT64
EFIAPI
InterlockedCompareExchange64 (
- IN OUT volatile UINT64 *Value,
- IN UINT64 CompareValue,
- IN UINT64 ExchangeValue
+ IN OUT volatile UINT64 *Value,
+ IN UINT64 CompareValue,
+ IN UINT64 ExchangeValue
)
{
ASSERT (Value != NULL);
@@ -399,28 +406,28 @@ InterlockedCompareExchange64 (
VOID *
EFIAPI
InterlockedCompareExchangePointer (
- IN OUT VOID * volatile *Value,
- IN VOID *CompareValue,
- IN VOID *ExchangeValue
+ IN OUT VOID *volatile *Value,
+ IN VOID *CompareValue,
+ IN VOID *ExchangeValue
)
{
UINT8 SizeOfValue;
- SizeOfValue = (UINT8) sizeof (*Value);
+ SizeOfValue = (UINT8)sizeof (*Value);
switch (SizeOfValue) {
case sizeof (UINT32):
- return (VOID*)(UINTN)InterlockedCompareExchange32 (
- (volatile UINT32*)Value,
- (UINT32)(UINTN)CompareValue,
- (UINT32)(UINTN)ExchangeValue
- );
+ return (VOID *)(UINTN)InterlockedCompareExchange32 (
+ (volatile UINT32 *)Value,
+ (UINT32)(UINTN)CompareValue,
+ (UINT32)(UINTN)ExchangeValue
+ );
case sizeof (UINT64):
- return (VOID*)(UINTN)InterlockedCompareExchange64 (
- (volatile UINT64*)Value,
- (UINT64)(UINTN)CompareValue,
- (UINT64)(UINTN)ExchangeValue
- );
+ return (VOID *)(UINTN)InterlockedCompareExchange64 (
+ (volatile UINT64 *)Value,
+ (UINT64)(UINTN)CompareValue,
+ (UINT64)(UINTN)ExchangeValue
+ );
default:
ASSERT (FALSE);
return NULL;
diff --git a/MdePkg/Library/BaseSynchronizationLib/X64/GccInline.c b/MdePkg/Library/BaseSynchronizationLib/X64/GccInline.c
index ee9d6a4a..920b69cb 100644
--- a/MdePkg/Library/BaseSynchronizationLib/X64/GccInline.c
+++ b/MdePkg/Library/BaseSynchronizationLib/X64/GccInline.c
@@ -7,8 +7,6 @@
**/
-
-
/**
Performs an atomic increment of an 32-bit unsigned integer.
@@ -24,7 +22,7 @@
UINT32
EFIAPI
InternalSyncIncrement (
- IN volatile UINT32 *Value
+ IN volatile UINT32 *Value
)
{
UINT32 Result;
@@ -39,12 +37,11 @@ InternalSyncIncrement (
: // no inputs that aren't also outputs
: "memory",
"cc"
- );
+ );
return Result;
}
-
/**
Performs an atomic decrement of an 32-bit unsigned integer.
@@ -60,10 +57,10 @@ InternalSyncIncrement (
UINT32
EFIAPI
InternalSyncDecrement (
- IN volatile UINT32 *Value
+ IN volatile UINT32 *Value
)
{
- UINT32 Result;
+ UINT32 Result;
__asm__ __volatile__ (
"movl $-1, %%eax \n\t"
@@ -75,12 +72,11 @@ InternalSyncDecrement (
: // no inputs that aren't also outputs
: "memory",
"cc"
- );
+ );
return Result;
}
-
/**
Performs an atomic compare exchange operation on a 16-bit unsigned integer.
@@ -102,9 +98,9 @@ InternalSyncDecrement (
UINT16
EFIAPI
InternalSyncCompareExchange16 (
- IN OUT volatile UINT16 *Value,
- IN UINT16 CompareValue,
- IN UINT16 ExchangeValue
+ IN OUT volatile UINT16 *Value,
+ IN UINT16 CompareValue,
+ IN UINT16 ExchangeValue
)
{
__asm__ __volatile__ (
@@ -115,12 +111,11 @@ InternalSyncCompareExchange16 (
: "r" (ExchangeValue) // %2
: "memory",
"cc"
- );
+ );
return CompareValue;
}
-
/**
Performs an atomic compare exchange operation on a 32-bit unsigned integer.
@@ -142,9 +137,9 @@ InternalSyncCompareExchange16 (
UINT32
EFIAPI
InternalSyncCompareExchange32 (
- IN OUT volatile UINT32 *Value,
- IN UINT32 CompareValue,
- IN UINT32 ExchangeValue
+ IN OUT volatile UINT32 *Value,
+ IN UINT32 CompareValue,
+ IN UINT32 ExchangeValue
)
{
__asm__ __volatile__ (
@@ -155,12 +150,11 @@ InternalSyncCompareExchange32 (
: "r" (ExchangeValue) // %2
: "memory",
"cc"
- );
+ );
return CompareValue;
}
-
/**
Performs an atomic compare exchange operation on a 64-bit unsigned integer.
@@ -181,9 +175,9 @@ InternalSyncCompareExchange32 (
UINT64
EFIAPI
InternalSyncCompareExchange64 (
- IN OUT volatile UINT64 *Value,
- IN UINT64 CompareValue,
- IN UINT64 ExchangeValue
+ IN OUT volatile UINT64 *Value,
+ IN UINT64 CompareValue,
+ IN UINT64 ExchangeValue
)
{
__asm__ __volatile__ (
@@ -194,7 +188,7 @@ InternalSyncCompareExchange64 (
: "r" (ExchangeValue) // %2
: "memory",
"cc"
- );
+ );
return CompareValue;
}
diff --git a/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange16.c b/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange16.c
index ab8e5031..226fb522 100644
--- a/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange16.c
+++ b/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange16.c
@@ -11,11 +11,12 @@
Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
**/
-__int16 _InterlockedCompareExchange16(
- __int16 volatile * Destination,
- __int16 Exchange,
- __int16 Comperand
-);
+__int16
+_InterlockedCompareExchange16 (
+ __int16 volatile *Destination,
+ __int16 Exchange,
+ __int16 Comperand
+ );
#pragma intrinsic(_InterlockedCompareExchange16)
@@ -38,11 +39,10 @@ __int16 _InterlockedCompareExchange16(
UINT16
EFIAPI
InternalSyncCompareExchange16 (
- IN volatile UINT16 *Value,
- IN UINT16 CompareValue,
- IN UINT16 ExchangeValue
+ IN volatile UINT16 *Value,
+ IN UINT16 CompareValue,
+ IN UINT16 ExchangeValue
)
{
return _InterlockedCompareExchange16 (Value, ExchangeValue, CompareValue);
}
-
diff --git a/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange32.c b/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange32.c
index 0b7212ca..e1e9512f 100644
--- a/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange32.c
+++ b/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange32.c
@@ -10,11 +10,12 @@
Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
**/
-long _InterlockedCompareExchange(
- long volatile * Destination,
- long Exchange,
- long Comperand
-);
+long
+_InterlockedCompareExchange (
+ long volatile *Destination,
+ long Exchange,
+ long Comperand
+ );
#pragma intrinsic(_InterlockedCompareExchange)
@@ -38,11 +39,10 @@ long _InterlockedCompareExchange(
UINT32
EFIAPI
InternalSyncCompareExchange32 (
- IN volatile UINT32 *Value,
- IN UINT32 CompareValue,
- IN UINT32 ExchangeValue
+ IN volatile UINT32 *Value,
+ IN UINT32 CompareValue,
+ IN UINT32 ExchangeValue
)
{
return _InterlockedCompareExchange (Value, ExchangeValue, CompareValue);
}
-
diff --git a/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange64.c b/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange64.c
index f737b630..27feeca7 100644
--- a/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange64.c
+++ b/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange64.c
@@ -10,11 +10,12 @@
Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
**/
-__int64 _InterlockedCompareExchange64(
- __int64 volatile * Destination,
- __int64 Exchange,
- __int64 Comperand
-);
+__int64
+_InterlockedCompareExchange64 (
+ __int64 volatile *Destination,
+ __int64 Exchange,
+ __int64 Comperand
+ );
#pragma intrinsic(_InterlockedCompareExchange64)
@@ -37,11 +38,10 @@ __int64 _InterlockedCompareExchange64(
UINT64
EFIAPI
InternalSyncCompareExchange64 (
- IN volatile UINT64 *Value,
- IN UINT64 CompareValue,
- IN UINT64 ExchangeValue
+ IN volatile UINT64 *Value,
+ IN UINT64 CompareValue,
+ IN UINT64 ExchangeValue
)
{
return _InterlockedCompareExchange64 (Value, ExchangeValue, CompareValue);
}
-
diff --git a/MdePkg/Library/RegisterFilterLibNull/RegisterFilterLibNull.c b/MdePkg/Library/RegisterFilterLibNull/RegisterFilterLibNull.c
index 5fe27dcf..410c96d7 100644
--- a/MdePkg/Library/RegisterFilterLibNull/RegisterFilterLibNull.c
+++ b/MdePkg/Library/RegisterFilterLibNull/RegisterFilterLibNull.c
@@ -81,13 +81,13 @@ FilterBeforeIoWrite (
return TRUE;
}
- /**
- Trace IO Write operation after wirte IO port.
- It is used to trace IO operation.
+/**
+Trace IO Write operation after wirte IO port.
+It is used to trace IO operation.
- @param[in] Width Signifies the width of the I/O operation.
- @param[in] Address The base address of the I/O operation.
- @param[in] Buffer The source buffer from which to Write data.
+@param[in] Width Signifies the width of the I/O operation.
+@param[in] Address The base address of the I/O operation.
+@param[in] Buffer The source buffer from which to Write data.
**/
VOID
@@ -205,8 +205,8 @@ FilterAfterMmIoWrite (
BOOLEAN
EFIAPI
FilterBeforeMsrRead (
- IN UINT32 Index,
- IN OUT UINT64 *Value
+ IN UINT32 Index,
+ IN OUT UINT64 *Value
)
{
return TRUE;
@@ -222,8 +222,8 @@ FilterBeforeMsrRead (
VOID
EFIAPI
FilterAfterMsrRead (
- IN UINT32 Index,
- IN UINT64 *Value
+ IN UINT32 Index,
+ IN UINT64 *Value
)
{
return;
@@ -245,8 +245,8 @@ FilterAfterMsrRead (
BOOLEAN
EFIAPI
FilterBeforeMsrWrite (
- IN UINT32 Index,
- IN UINT64 *Value
+ IN UINT32 Index,
+ IN UINT64 *Value
)
{
return TRUE;
@@ -262,10 +262,9 @@ FilterBeforeMsrWrite (
VOID
EFIAPI
FilterAfterMsrWrite (
- IN UINT32 Index,
- IN UINT64 *Value
+ IN UINT32 Index,
+ IN UINT64 *Value
)
{
return;
}
-
diff --git a/MdePkg/Library/RegisterFilterLibNull/RegisterFilterLibNull.uni b/MdePkg/Library/RegisterFilterLibNull/RegisterFilterLibNull.uni
deleted file mode 100644
index 41571357..00000000
--- a/MdePkg/Library/RegisterFilterLibNull/RegisterFilterLibNull.uni
+++ /dev/null
@@ -1,13 +0,0 @@
-// /** @file
-// Null instance of RegisterFilterLib.
-//
-// Copyright (c) 2021, Intel Corporation. All rights reserved.
-//
-// SPDX-License-Identifier: BSD-2-Clause-Patent
-//
-// **/
-
-
-#string STR_MODULE_ABSTRACT #language en-US "Null instance of RegisterFilterLib."
-#string STR_MODULE_DESCRIPTION #language en-US "Null instance of RegisterFilterLib."
-
diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index 1d60bc63..511c5560 100755
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -4,9 +4,13 @@
# It also provides the definitions(including PPIs/PROTOCOLs/GUIDs) of
# EFI1.10/UEFI2.7/PI1.7 and some Industry Standards.
#
-# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# (C) Copyright 2016 - 2021 Hewlett Packard Enterprise Development LP
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+# Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (c) 2023, Ampere Computing LLC. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -39,6 +43,12 @@
[Includes.AARCH64]
Include/AArch64
+[Includes.RISCV64]
+ Include/RiscV64
+
+[Includes.LOONGARCH64]
+ Include/LoongArch64
+
[LibraryClasses]
## @libraryclass Provides most usb APIs to support the Hid requests defined in Usb Hid 1.1 spec
# and the standard requests defined in Usb 1.1 spec.
@@ -244,6 +254,18 @@
## @libraryclass Module entry point library for standalone MM drivers.
StandaloneMmDriverEntryPoint|Include/Library/StandaloneMmDriverEntryPoint.h
+ ## @libraryclass Provides a unit test framework
+ #
+ UnitTestLib|Include/Library/UnitTestLib.h
+
+ ## @libraryclass Provides service to get the manufacturer given JEP106 bytes.
+ JedecJep106Lib|Include/Library/JedecJep106Lib.h
+
+ ## @libraryclass Extension to BaseLib for host based unit tests that allows a
+ # subset of BaseLib services to be hooked for emulation.
+ #
+ UnitTestHostBaseLib|Test/UnitTest/Include/Library/UnitTestHostBaseLib.h
+
## @libraryclass This library provides an interface to request non-MMRAM pages to be mapped
# or unblocked from inside MM environment.
#
@@ -254,6 +276,30 @@
#
RegisterFilterLib|Include/Library/RegisterFilterLib.h
+ ## @libraryclass This library provides interfances to probe ConfidentialComputing guest type.
+ #
+ #
+ CcProbeLib|Include/Library/CcProbeLib.h
+
+ ## @libraryclass Provides function for SMM CPU Rendezvous Library.
+ SmmCpuRendezvousLib|Include/Library/SmmCpuRendezvousLib.h
+
+ ## @libraryclass Provides services to generate Entropy using a TRNG.
+ #
+ ArmTrngLib|Include/Library/ArmTrngLib.h
+
+ ## @libraryclass Provides APIs for third-party library libfdt.
+ #
+ FdtLib|Include/Library/FdtLib.h
+
+ ## @libraryclass Provides general mipi sys-T services.
+ #
+ MipiSysTLib|Include/Library/MipiSysTLib.h
+
+ ## @libraryclass Provides API to output Trace Hub debug message.
+ #
+ TraceHubDebugSysTLib|Include/Library/TraceHubDebugSysTLib.h
+
[LibraryClasses.IA32, LibraryClasses.X64, LibraryClasses.AARCH64]
## @libraryclass Provides services to generate random number.
#
@@ -283,6 +329,13 @@
## @libraryclass Provides services to log the SMI handler registration.
SmiHandlerProfileLib|Include/Library/SmiHandlerProfileLib.h
+ ## @libraryclass Provides function to support TDX processing.
+ TdxLib|Include/Library/TdxLib.h
+
+[LibraryClasses.RISCV64]
+ ## @libraryclass Provides function to make ecalls to SBI
+ BaseRiscVSbiLib|Include/Library/BaseRiscVSbiLib.h
+
[Guids]
#
# GUID defined in UEFI2.1/UEFI2.0/EFI1.1
@@ -380,11 +433,17 @@
## Include/Guid/EventGroup.h
gEfiEventReadyToBootGuid = { 0x7CE88FB3, 0x4BD7, 0x4679, { 0x87, 0xA8, 0xA8, 0xD8, 0xDE, 0xE5, 0x0D, 0x2B }}
+ ## Include/Guid/EventGroup.h
+ gEfiEventAfterReadyToBootGuid = { 0x3a2a00ad, 0x98b9, 0x4cdf, { 0xa4, 0x78, 0x70, 0x27, 0x77, 0xf1, 0xc1, 0x0b }}
+
## Include/Guid/EventGroup.h
gEfiEventMemoryMapChangeGuid = { 0x78BEE926, 0x692F, 0x48FD, { 0x9E, 0xDB, 0x01, 0x42, 0x2E, 0xF0, 0xD7, 0xAB }}
## Include/Guid/EventGroup.h
- gEfiEventVirtualAddressChangeGuid = { 0x13FA7698, 0xC831, 0x49C7, { 0x87, 0xEA, 0x8F, 0x43, 0xFC, 0xC2, 0x51, 0x96 }}
+ gEfiEventVirtualAddressChangeGuid = { 0x13FA7698, 0xC831, 0x49C7, { 0x87, 0xEA, 0x8F, 0x43, 0xFC, 0xC2, 0x51, 0x96 }}
+
+ ## Include/Guid/EventGroup.h
+ gEfiEventBeforeExitBootServicesGuid = { 0x8BE0E274, 0x3970, 0x4B44, { 0x80, 0xC5, 0x1A, 0xB9, 0x50, 0x2F, 0x3B, 0xFC }}
## Include/Guid/EventGroup.h
gEfiEventExitBootServicesGuid = { 0x27ABF055, 0xB1B8, 0x4C26, { 0x80, 0x48, 0x74, 0x8F, 0x37, 0xBA, 0xA2, 0xDF }}
@@ -581,6 +640,7 @@
gEfiRngAlgorithmX9313DesGuid = { 0x63c4785a, 0xca34, 0x4012, {0xa3, 0xc8, 0x0b, 0x6a, 0x32, 0x4f, 0x55, 0x46 }}
gEfiRngAlgorithmX931AesGuid = { 0xacd03321, 0x777e, 0x4d3d, {0xb1, 0xc8, 0x20, 0xcf, 0xd8, 0x88, 0x20, 0xc9 }}
gEfiRngAlgorithmRaw = { 0xe43176d7, 0xb6e8, 0x4827, {0xb7, 0x84, 0x7f, 0xfd, 0xc4, 0xb6, 0x85, 0x61 }}
+ gEfiRngAlgorithmArmRndr = { 0x43d2fde3, 0x9d4e, 0x4d79, {0x02, 0x96, 0xa8, 0x9b, 0xca, 0x78, 0x08, 0x41 }}
## Include/Protocol/AdapterInformation.h
gEfiAdapterInfoMediaStateGuid = { 0xD7C74207, 0xA831, 0x4A26, {0xB1, 0xF5, 0xD1, 0x93, 0x06, 0x5C, 0xE8, 0xB6 }}
@@ -810,6 +870,9 @@
#
gLinuxEfiInitrdMediaGuid = {0x5568e427, 0x68fc, 0x4f3d, {0xac, 0x74, 0xca, 0x55, 0x52, 0x31, 0xcc, 0x68}}
+ ## Include/Protocol/CcMeasurement.h
+ gEfiCcFinalEventsTableGuid = { 0xdd4a4648, 0x2de7, 0x4665, { 0x96, 0x4d, 0x21, 0xd9, 0xef, 0x5f, 0xb4, 0x46 }}
+
[Guids.IA32, Guids.X64]
## Include/Guid/Cper.h
gEfiIa32X64ErrorTypeCacheCheckGuid = { 0xA55701F5, 0xE3EF, 0x43de, { 0xAC, 0x72, 0x24, 0x9B, 0x57, 0x3F, 0xAD, 0x2C }}
@@ -992,12 +1055,18 @@
gEfiPeiDelayedDispatchPpiGuid = { 0x869c711d, 0x649c, 0x44fe, { 0x8b, 0x9e, 0x2c, 0xbb, 0x29, 0x11, 0xc3, 0xe6 }}
[Protocols]
+ ## Include/Protocol/MemoryAccept.h
+ gEdkiiMemoryAcceptProtocolGuid = { 0x38c74800, 0x5590, 0x4db4, { 0xa0, 0xf3, 0x67, 0x5d, 0x9b, 0x8e, 0x80, 0x26 }}
+
## Include/Protocol/Pcd.h
gPcdProtocolGuid = { 0x11B34006, 0xD85B, 0x4D0A, { 0xA2, 0x90, 0xD5, 0xA5, 0x71, 0x31, 0x0E, 0xF7 }}
## Include/Protocol/PcdInfo.h
gGetPcdInfoProtocolGuid = { 0x5be40f57, 0xfa68, 0x4610, { 0xbb, 0xbf, 0xe9, 0xc5, 0xfc, 0xda, 0xd3, 0x65 } }
+ ## Include/Protocol/CcMeasurement.h
+ gEfiCcMeasurementProtocolGuid = { 0x96751a3d, 0x72f4, 0x41a6, { 0xa7, 0x94, 0xed, 0x5d, 0x0e, 0x67, 0xae, 0x6b }}
+
#
# Protocols defined in PI1.0.
#
@@ -1870,6 +1939,9 @@
## Include/Protocol/RedfishDiscover.h
gEfiRedfishDiscoverProtocolGuid = { 0x5db12509, 0x4550, 0x4347, { 0x96, 0xb3, 0x73, 0xc0, 0xff, 0x6e, 0x86, 0x9f }}
+ ## Include/Protocol/MemoryAttribute.h
+ gEfiMemoryAttributeProtocolGuid = { 0xf4560cf6, 0x40ec, 0x4b4a, { 0xa1, 0x92, 0xbf, 0x1d, 0x57, 0xd0, 0xb1, 0x89 }}
+
#
# Protocols defined in Shell2.0
#
@@ -2222,6 +2294,7 @@
# BIT20 - Global Coherency Database changes message.
# BIT21 - Memory range cachability changes message.
# BIT22 - Detailed debug message.
+ # BIT23 - Manageability messages.
# BIT31 - Error message.
# @Prompt Debug Message Print Level.
# @Expression 0x80000002 | (gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel & 0x7F84AA00) == 0
@@ -2287,6 +2360,42 @@
# @Prompt Memory Address of GuidedExtractHandler Table.
gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|0x1000000|UINT64|0x30001015
+ ## This value is the IPMI KCS Interface I/O base address used to transmit IPMI commands.
+ # The value of 0xca2 is the default I/O base address defined in IPMI specification.
+ # @Prompt IPMI KCS Interface I/O Base Address
+ gEfiMdePkgTokenSpaceGuid.PcdIpmiKcsIoBaseAddress|0xca2|UINT16|0x00000031
+
+ ## This is SMBus slave address for the SSIF to the BMC.
+ # The recommended value defined by IPMI specification is 0x20 (section 12.12).
+ # @Prompt IPMI SSIF SMBus slave address
+ gEfiMdePkgTokenSpaceGuid.PcdIpmiSsifSmbusSlaveAddr|0x20|UINT8|0x00000032
+
+ ## This is the maximum number of IPMI SSIF request retries.
+ # The IPMI specification specified min value is 5 (section 12.17).
+ # @Prompt Number of IPMI SSIF request retries.
+ gEfiMdePkgTokenSpaceGuid.PcdIpmiSsifRequestRetryCount|0x05|UINT8|0x00000033
+
+ ## This is the required interval for each IPMI request retry.
+ # The IPMI specification specified a time range of 60ms to 250ms (section 12.17).
+ # The default setting is min.
+ # @Prompt Time between IPMI SSIF request retries.
+ gEfiMdePkgTokenSpaceGuid.PcdIpmiSsifRequestRetryIntervalMicrosecond|60000|UINT32|0x00000034
+
+ ## This value is the maximum retries of an IPMI SSIF response
+ # The default value is the same as the Linux Kernel ipmi_ssif driver.
+ # @Prompt Number of IPMI SSIF response retries.
+ gEfiMdePkgTokenSpaceGuid.PcdIpmiSsifResponseRetryCount|250|UINT8|0x00000035
+
+ ## This is the required interval for each IPMI response retry.
+ # The IPMI specification specified min value is 60ms (section 12.17).
+ # @Prompt Time-out for a response, internal
+ gEfiMdePkgTokenSpaceGuid.PcdIpmiSsifResponseRetryIntervalMicrosecond|60000|UINT32|0x00000036
+
+[PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AARCH64]
+ ## GUID identifying the Rng algorithm implemented by CPU instruction.
+ # @Prompt CPU Rng algorithm's GUID.
+ gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x00000037
+
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
## This value is used to set the base address of PCI express hierarchy.
# @Prompt PCI Express Base Address.
@@ -2383,5 +2492,9 @@
# @Prompt FSB Clock.
gEfiMdePkgTokenSpaceGuid.PcdFSBClock|200000000|UINT32|0x0000000c
+ ## This dynamic PCD indicates the memory encryption attribute of the guest.
+ # @Prompt Memory encryption attribute
+ gEfiMdePkgTokenSpaceGuid.PcdConfidentialComputingGuestAttr|0|UINT64|0x0000002e
+
[UserExtensions.TianoCore."ExtraFiles"]
MdePkgExtra.uni
diff --git a/PayloadPkg/OsLoader/OsLoader.h b/PayloadPkg/OsLoader/OsLoader.h
index 49a09c57..71a4f1b5 100644
--- a/PayloadPkg/OsLoader/OsLoader.h
+++ b/PayloadPkg/OsLoader/OsLoader.h
@@ -63,7 +63,7 @@
#include
#include "BlockIoTest.h"
#include
-#include
+#include
#include
#include
diff --git a/Platform/AlderlakeBoardPkg/AcpiTables/Dptf/Dptf.asl b/Platform/AlderlakeBoardPkg/AcpiTables/Dptf/Dptf.asl
index 27f8601e..bfc8d34b 100644
--- a/Platform/AlderlakeBoardPkg/AcpiTables/Dptf/Dptf.asl
+++ b/Platform/AlderlakeBoardPkg/AcpiTables/Dptf/Dptf.asl
@@ -608,14 +608,8 @@ Scope(\_SB.PC00.LPCB.H_EC) // Open scope to Embedded Controller
//
// Participants using device sensors.
//
- Include("ChrgParticipant.asl")
Include("TPwrParticipant.asl")
-//
-// Participants using battery.
-//
- Include("BatteryParticipant.asl")
-
//
// Participants using motherboard sensors.
//
@@ -624,7 +618,6 @@ Scope(\_SB.PC00.LPCB.H_EC) // Open scope to Embedded Controller
Include("Sen3Participant.asl")
Include("Sen4Participant.asl")
Include("Sen5Participant.asl")
- Include("dGpuSensor.asl")
//
// Policy support files
diff --git a/Platform/AlderlakeBoardPkg/AcpiTables/Dsdt/IteSio.asl b/Platform/AlderlakeBoardPkg/AcpiTables/Dsdt/IteSio.asl
index 8d087b6d..54d5ccb8 100644
--- a/Platform/AlderlakeBoardPkg/AcpiTables/Dsdt/IteSio.asl
+++ b/Platform/AlderlakeBoardPkg/AcpiTables/Dsdt/IteSio.asl
@@ -125,7 +125,6 @@ Device(ITE8)
Include ("Sen2Particip.asl")
Include ("Sen3Particip.asl")
} Else {
- Include ("IteHwMonAutoFan2.asl")
Include ("IteHwMonAuto.asl")
}
Include ("IteCom.asl")
diff --git a/Platform/AlderlakeBoardPkg/AcpiTables/Ssdt/AdlNDdr5CrbRtd3.asl b/Platform/AlderlakeBoardPkg/AcpiTables/Ssdt/AdlNDdr5CrbRtd3.asl
index d1479584..11a51727 100644
--- a/Platform/AlderlakeBoardPkg/AcpiTables/Ssdt/AdlNDdr5CrbRtd3.asl
+++ b/Platform/AlderlakeBoardPkg/AcpiTables/Ssdt/AdlNDdr5CrbRtd3.asl
@@ -142,7 +142,6 @@ External(\_SB.PC00.SAT0.PRT0.PRES, MethodObj)
Name(WAKG, 0)
Store(WWKP, WAKG)
Name(SCLK, 2)
- Include("Rtd3PcieWwan.asl")
}
}
///
@@ -221,7 +220,7 @@ External(\_SB.PC00.SAT0.PRT0.PRES, MethodObj)
Store(STPP, Index(PWRG, 1))
}
}
- Include("Rtd3Sata.asl")
+
}
@@ -439,7 +438,6 @@ If (LNotEqual(GBES,0)) {
Alias(IC0D, TD_D) // TD_D - Touch Device power on delay
Alias(\_SB.PC00.I2C0.ONTM, TD_C) // TD_C - Touch Device I2C controller power on timestamp
- Include("Rtd3I2cTouchDev.asl")
Method(_PS0) { PS0X() }
Method(_PS3) { PS3X() }
}// End Of Scope(TPD0)
@@ -452,7 +450,6 @@ If (LNotEqual(GBES,0)) {
Alias(IC1D, TD_D) // TD_D - Touch Device power on delay
Alias(\_SB.PC00.I2C0.ONTM, TD_C) // TD_C - Touch Device I2C controller power on timestamp
- Include("Rtd3I2cTouchDev.asl")
Method(_PS0) { PS0X() }
Method(_PS3) { PS3X() }
}// End Of Scope(TPL1)
diff --git a/Platform/AlderlakeBoardPkg/AcpiTables/Ssdt/AdlNRvpRtd3.asl b/Platform/AlderlakeBoardPkg/AcpiTables/Ssdt/AdlNRvpRtd3.asl
index f4f1fece..ffce5f0f 100644
--- a/Platform/AlderlakeBoardPkg/AcpiTables/Ssdt/AdlNRvpRtd3.asl
+++ b/Platform/AlderlakeBoardPkg/AcpiTables/Ssdt/AdlNRvpRtd3.asl
@@ -131,7 +131,6 @@ External(\_SB.PC00.SAT0.PRT0.PRES, MethodObj)
Name(WAKG, 0)
Store(WWKP, WAKG)
Name(SCLK, 1)
- Include("Rtd3PcieWwan.asl")
}
}
///
@@ -183,7 +182,6 @@ External(\_SB.PC00.SAT0.PRT0.PRES, MethodObj)
Store(STPP, Index(PWRG, 1))
}
}
- Include("Rtd3Sata.asl")
}
@@ -401,7 +399,6 @@ If (LNotEqual(GBES,0)) {
Alias(IC0D, TD_D) // TD_D - Touch Device power on delay
Alias(\_SB.PC00.I2C0.ONTM, TD_C) // TD_C - Touch Device I2C controller power on timestamp
- Include("Rtd3I2cTouchDev.asl")
Method(_PS0) { PS0X() }
Method(_PS3) { PS3X() }
}// End Of Scope(TPD0)
@@ -414,7 +411,6 @@ If (LNotEqual(GBES,0)) {
Alias(IC1D, TD_D) // TD_D - Touch Device power on delay
Alias(\_SB.PC00.I2C0.ONTM, TD_C) // TD_C - Touch Device I2C controller power on timestamp
- Include("Rtd3I2cTouchDev.asl")
Method(_PS0) { PS0X() }
Method(_PS3) { PS3X() }
}// End Of Scope(TPL1)
diff --git a/Platform/AlderlakeBoardPkg/AcpiTables/Ssdt/AdlPRvpRtd3.asl b/Platform/AlderlakeBoardPkg/AcpiTables/Ssdt/AdlPRvpRtd3.asl
index 01c2c12f..74d29a9b 100644
--- a/Platform/AlderlakeBoardPkg/AcpiTables/Ssdt/AdlPRvpRtd3.asl
+++ b/Platform/AlderlakeBoardPkg/AcpiTables/Ssdt/AdlPRvpRtd3.asl
@@ -235,10 +235,6 @@ External(\_SB.PC00.HDAS.VDID)
Store(P1WP, WAKG)
// Note: IPC1 Command Timeout need to increase for dGPU only.
Name (TMCS, 3000) // IPC Command Timeout Increase to 3 Secs.
- If(LNotEqual (DGBA, 0)) {
- Include ("PcieRpDiscreteGraphicsDeviceRtd3Hook.asl")
- Include ("PcieRpDiscreteGraphicsHpdAsD3WakeHook.asl")
- }
Scope (\_SB.PC00.PEG1.PEGP) {
Include ("PcieRpSsdStorageRtd3Hook.asl")
}
@@ -446,7 +442,6 @@ If (LNotEqual(GBES,0)) {
Alias(IC0D, TD_D) // TD_D - Touch Device power on delay
Alias(\_SB.PC00.I2C0.ONTM, TD_C) // TD_C - Touch Device I2C controller power on timestamp
- Include("Rtd3I2cTouchDev.asl")
Method(_PS0) { PS0X() }
Method(_PS3) { PS3X() }
}// End Of Scope(TPD0)
@@ -460,7 +455,6 @@ If (LNotEqual(GBES,0)) {
Alias(IC1D, TD_D) // TD_D - Touch Device power on delay
Alias(\_SB.PC00.I2C0.ONTM, TD_C) // TD_C - Touch Device I2C controller power on timestamp
- Include("Rtd3I2cTouchDev.asl")
Method(_PS0) { PS0X() }
Method(_PS3) { PS3X() }
}// End Of Scope(TPL1)
diff --git a/Platform/AlderlakeBoardPkg/BoardConfigAdlPs.py b/Platform/AlderlakeBoardPkg/BoardConfigAdlPs.py
index f8886ad4..e91c0e01 100644
--- a/Platform/AlderlakeBoardPkg/BoardConfigAdlPs.py
+++ b/Platform/AlderlakeBoardPkg/BoardConfigAdlPs.py
@@ -37,5 +37,5 @@ class Board(AlderlakeBoardConfig.Board):
# 0 - PCH UART0, 1 - PCH UART1, 2 - PCH UART2, 0xFF - EC UART 0x3F8
self.DEBUG_PORT_NUMBER = 0x0
- self.OS_LOADER_FD_SIZE = 0x00058000
+ self.OS_LOADER_FD_SIZE = 0x00059000
self.OS_LOADER_FD_NUMBLK = self.OS_LOADER_FD_SIZE // self.FLASH_BLOCK_SIZE
diff --git a/Platform/ApollolakeBoardPkg/BoardConfig.py b/Platform/ApollolakeBoardPkg/BoardConfig.py
index 8aafb10d..bcbcc388 100755
--- a/Platform/ApollolakeBoardPkg/BoardConfig.py
+++ b/Platform/ApollolakeBoardPkg/BoardConfig.py
@@ -116,7 +116,7 @@ class Board(BaseBoard):
if self.ENABLE_SOURCE_DEBUG:
self.STAGE1B_SIZE += 0x2000
self.STAGE2_SIZE = 0x00033000
- self.PAYLOAD_SIZE = 0x00021000
+ self.PAYLOAD_SIZE = 0x00022000
if len(self._PAYLOAD_NAME.split(';')) > 1:
# EPAYLOAD is specified
diff --git a/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/Connectivity.asl b/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/Connectivity.asl
index 5e69e8a6..4ff9173f 100644
--- a/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/Connectivity.asl
+++ b/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/Connectivity.asl
@@ -29,18 +29,6 @@ Scope(\_SB)
}
}
-//
-// Report thermal & regulatory methods if CNVi WiFi is present
-//
-If (\_SB.PC00.CNIP ()) {
- Scope (\_SB.PC00.CNVW) {
- Include("WifiThermal.asl")
- Include("WifiRegulatory.asl")
- Include("AntennaDiversity.asl")
- Include("GeneralPurposeConfig.asl")
- }
-}
-
Scope(\_SB.PC00.UA00)
{
//
@@ -93,6 +81,5 @@ Scope(\_SB.PC00.UA00)
}
Name (_S0W, 2) // Required to put the device to D2 during S0 idle
} // Device BTH0
- Include("BtRegulatory.asl")
- Include("GeneralPurposeConfig.asl")
+
} // End of Scope(\_SB.PC00.UART0)
diff --git a/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/DiscreteConnectivity.asl b/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/DiscreteConnectivity.asl
index 17696502..48bd635d 100644
--- a/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/DiscreteConnectivity.asl
+++ b/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/DiscreteConnectivity.asl
@@ -80,27 +80,3 @@ Method(WWST,0,Serialized)
Return(0)
}
}
-
-//
-// Load Wifi/BT/WiGig tables only the Vendor ID, Device ID matches
-//
-If (WIST())
-{
- Include("Wifi.asl")
-}
-
-//
-// Load WWAN tables only the Vendor ID, Device ID matches
-//
-If(WWST())
-{
- Include("Wwan.asl")
-}
-
-//
-// Load Platform-level device reset tables only the Vendor ID, Device ID matches
-//
-If (LOr(WIST(),WWST()))
-{
- Include("DiscreteConnectivityReset.asl")
-}
diff --git a/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/Dsdt.asl b/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/Dsdt.asl
index 1c46c885..f47dbae1 100644
--- a/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/Dsdt.asl
+++ b/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/Dsdt.asl
@@ -202,7 +202,6 @@ DefinitionBlock (
Include ("HdaDspModules.asl")
Include ("HIDWakeDSM.asl")
Include ("PinDriverLib.asl")
- Include ("Pld.asl")
Include ("Lid.asl")
Include ("FwuWmi.asl")
diff --git a/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/Pch.asl b/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/Pch.asl
index 30b7e6d0..553084c2 100644
--- a/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/Pch.asl
+++ b/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/Pch.asl
@@ -610,11 +610,6 @@ Include ("PchTsn.asl")
//
Include ("PchIsi.asl")
-//
-// Touch Host Controllers definition
-//
-Include ("Thc.asl")
-
//
// MEI 1 definition
//
diff --git a/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/Platform.asl b/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/Platform.asl
index 69c3d0f5..3a23ee45 100644
--- a/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/Platform.asl
+++ b/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/Platform.asl
@@ -84,9 +84,6 @@ External(MMTB, MethodObj)
External(TBFF, MethodObj)
External(FFTB, MethodObj)
External(IPCS, MethodObj)
-include("DTbt.asl")
-// Comms Hub module support
-include("CommsHub.asl")
// Create a Global MUTEX.
diff --git a/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/SerialIoDevices.asl b/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/SerialIoDevices.asl
index 5116c010..29c02a0b 100644
--- a/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/SerialIoDevices.asl
+++ b/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/SerialIoDevices.asl
@@ -194,8 +194,6 @@ Scope(\_SB.PC00.I2C0) {
Name(I2CX, 0)
Store (SDS0, I2CN)
Store (SERIAL_IO_I2C0, I2CX)
- Include ("I2cTouchPad.asl")
- Include ("I2cTouchPanel.asl")
}
//-----------------------------
@@ -206,8 +204,6 @@ Scope(\_SB.PC00.I2C1) {
Name(I2CX, 0)
Store (SDS1, I2CN)
Store (SERIAL_IO_I2C1, I2CX)
- Include ("I2cTouchPad.asl")
- Include ("I2cTouchPanel.asl")
}
//-----------------------------
@@ -218,8 +214,6 @@ Scope(\_SB.PC00.I2C2) {
Name(I2CX, 0)
Store (SDS2, I2CN)
Store (SERIAL_IO_I2C2, I2CX)
- Include ("I2cTouchPad.asl")
- Include ("I2cTouchPanel.asl")
}
//-----------------------------
@@ -230,8 +224,6 @@ Scope(\_SB.PC00.I2C3) {
Name(I2CX, 0)
Store (SDS3, I2CN)
Store (SERIAL_IO_I2C3, I2CX)
- Include ("I2cTouchPad.asl")
- Include ("I2cTouchPanel.asl")
}
//-----------------------------
@@ -243,7 +235,6 @@ Scope(\_SB.PC00.SPI1)
Name(SPIX, 0)
Store (SDS7, SPIP)
Store (SERIAL_IO_SPI1, SPIX)
- Include ("PostCode.asl")
}
//-----------------------------
@@ -255,6 +246,5 @@ Scope(\_SB.PC00.SPI2)
Name(SPIX, 0)
Store (SDS8, SPIP)
Store (SERIAL_IO_SPI2, SPIX)
- Include ("SpiFingerprint.asl")
}
diff --git a/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/WifiDynamicSar.asl b/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/WifiDynamicSar.asl
index b1eccf89..fa52d7e9 100644
--- a/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/WifiDynamicSar.asl
+++ b/Platform/ElkhartlakeBoardPkg/AcpiTables/Dsdt/WifiDynamicSar.asl
@@ -83,10 +83,6 @@
Return(Zero)
}
- Name(WQCC, Buffer() //Compiled WMI MOF
- {
- Include ("MofSampleDev.h")
- })
}//End of Device(WFDE)
//-----------------------------------------
@@ -122,10 +118,6 @@
Return(Zero)
}
- Name(WQCC, Buffer() //Compiled WMI MOF
- {
- Include ("MofTestDev.h")
- })
}
//-----------------------------------------
// Test Device - End (Used for test purpose alone)
diff --git a/Platform/ElkhartlakeBoardPkg/AcpiTables/Ssdt/Sa.asl b/Platform/ElkhartlakeBoardPkg/AcpiTables/Ssdt/Sa.asl
index d6f420af..01fc1d8f 100644
--- a/Platform/ElkhartlakeBoardPkg/AcpiTables/Ssdt/Sa.asl
+++ b/Platform/ElkhartlakeBoardPkg/AcpiTables/Ssdt/Sa.asl
@@ -24,8 +24,3 @@ Scope (\_SB.PC00.GFX0)
{
include("Igfx.asl")
} // end I.G.D
-
-///
-/// IPU Device
-///
-include("Ipu.asl")
diff --git a/Platform/ElkhartlakeBoardPkg/AcpiTables/SsdtRtd3/Rtd3Common.asl b/Platform/ElkhartlakeBoardPkg/AcpiTables/SsdtRtd3/Rtd3Common.asl
index debcbe44..93edc8af 100644
--- a/Platform/ElkhartlakeBoardPkg/AcpiTables/SsdtRtd3/Rtd3Common.asl
+++ b/Platform/ElkhartlakeBoardPkg/AcpiTables/SsdtRtd3/Rtd3Common.asl
@@ -113,7 +113,6 @@ External(\_SB.CSD0, MethodObj)
External(\_SB.CSD3, MethodObj)
External(DVID)
-include("GpioAcpiDefinesVer1.h")
include("HsioDefine.asl")
#define RCG1_RTD3_PRT0_ENABLED 0x01
diff --git a/Platform/ElkhartlakeBoardPkg/AcpiTables/SsdtXhci/UsbPortXhciEhlLp4xCrb.asl b/Platform/ElkhartlakeBoardPkg/AcpiTables/SsdtXhci/UsbPortXhciEhlLp4xCrb.asl
index 296b41f8..8d9148cd 100644
--- a/Platform/ElkhartlakeBoardPkg/AcpiTables/SsdtXhci/UsbPortXhciEhlLp4xCrb.asl
+++ b/Platform/ElkhartlakeBoardPkg/AcpiTables/SsdtXhci/UsbPortXhciEhlLp4xCrb.asl
@@ -227,13 +227,6 @@ DefinitionBlock (
}
}
}
- If (\_SB.PC00.RP07.PXSX.WIST()) {
- Scope (\_SB.PC00.XHCI.RHUB.HS10) {
- Include("AntennaDiversity.asl")
- Include("BtRegulatory.asl")
- Include("GeneralPurposeConfig.asl")
- }
- }
Scope (\_SB.PC00.XHCI.RHUB.HS11) {
// Unused
diff --git a/Platform/MeteorlakeBoardPkg/AcpiTables/Dsdt/DiscreteConnectivity.asl b/Platform/MeteorlakeBoardPkg/AcpiTables/Dsdt/DiscreteConnectivity.asl
index 62130e03..2b59b577 100644
--- a/Platform/MeteorlakeBoardPkg/AcpiTables/Dsdt/DiscreteConnectivity.asl
+++ b/Platform/MeteorlakeBoardPkg/AcpiTables/Dsdt/DiscreteConnectivity.asl
@@ -92,28 +92,3 @@ Method (WWST,0,Serialized)
Return (0)
}
}
-
-//
-// Load Wifi/BT/WiGig tables only the Vendor ID, Device ID matches
-//
-If (WIST ())
-{
- Include ("Wifi.asl")
-}
-
-//
-// Load WWAN tables only the Vendor ID, Device ID matches
-//
-If (LAnd (LNotEqual (WWEN, 0), LEqual (WWRP, SLOT)))
-{
- Include ("Wwan.asl")
-}
-
-//
-// Load Platform-level device reset tables only the Vendor ID, Device ID matches
-//
-If (LOr (WIST (), LAnd (LNotEqual (WWEN, 0), LEqual (WWRP, SLOT))))
-{
- Include ("DiscreteConnectivityReset.asl")
- Include ("DiscreteConnectivityDsm.asl")
-}
\ No newline at end of file
diff --git a/Platform/MeteorlakeBoardPkg/AcpiTables/Ssdt/MtlPRvpRtd3.asl b/Platform/MeteorlakeBoardPkg/AcpiTables/Ssdt/MtlPRvpRtd3.asl
index 7feb5378..d690fbf4 100644
--- a/Platform/MeteorlakeBoardPkg/AcpiTables/Ssdt/MtlPRvpRtd3.asl
+++ b/Platform/MeteorlakeBoardPkg/AcpiTables/Ssdt/MtlPRvpRtd3.asl
@@ -230,7 +230,6 @@ External(\_SB.PC00.HDAS.VDID)
Name(WAKG, 0)
Store(WWKP, WAKG)
Name(SCLK, 1)
- Include("Rtd3PcieWwan.asl")
}
}
@@ -323,9 +322,6 @@ External(\_SB.PC00.HDAS.VDID)
Name(SCLK, 6)
Name(WAKP, 0) // must be defined due to compiler bug, will be removed when fixed https://bugs.acpica.org/show_bug.cgi?id=1432
Include("PcieRpGenericPcieDeviceRtd3.asl")
- If(LNotEqual (DGBA, 0)) {
- Include ("PcieRpDiscreteGraphicsDeviceRtd3Hook.asl")
- }
}
// USB - END
diff --git a/Platform/MeteorlakeBoardPkg/AcpiTables/Ssdt/MtlPSCrbRtd3.asl b/Platform/MeteorlakeBoardPkg/AcpiTables/Ssdt/MtlPSCrbRtd3.asl
index 0ed7d1dd..bb519fce 100644
--- a/Platform/MeteorlakeBoardPkg/AcpiTables/Ssdt/MtlPSCrbRtd3.asl
+++ b/Platform/MeteorlakeBoardPkg/AcpiTables/Ssdt/MtlPSCrbRtd3.asl
@@ -201,7 +201,6 @@ External(\_SB.PC00.HDAS.VDID)
Name(WAKG, 0)
Store(WWKP, WAKG)
Name(SCLK, 1)
- Include("Rtd3PcieWwan.asl")
}
}
diff --git a/Platform/TigerlakeBoardPkg/AcpiTables/Dsdt/DiscreteConnectivity.asl b/Platform/TigerlakeBoardPkg/AcpiTables/Dsdt/DiscreteConnectivity.asl
index b894ebfe..70a4b972 100644
--- a/Platform/TigerlakeBoardPkg/AcpiTables/Dsdt/DiscreteConnectivity.asl
+++ b/Platform/TigerlakeBoardPkg/AcpiTables/Dsdt/DiscreteConnectivity.asl
@@ -83,19 +83,3 @@ Method(WWST,0,Serialized)
Return(0)
}
}
-
-//
-// Load Wifi/BT/WiGig tables only the Vendor ID, Device ID matches
-//
-If (WIST())
-{
- Include("Wifi.asl")
-}
-
-//
-// Load WWAN tables only the Vendor ID, Device ID matches
-//
-If(LAnd(LNotEqual(WWEN, 0), LEqual(WWRP, SLOT)))
-{
- Include("Wwan.asl")
-}
diff --git a/Platform/TigerlakeBoardPkg/AcpiTables/Dsdt/Dsdt.asl b/Platform/TigerlakeBoardPkg/AcpiTables/Dsdt/Dsdt.asl
index ab9296f3..6073ea09 100644
--- a/Platform/TigerlakeBoardPkg/AcpiTables/Dsdt/Dsdt.asl
+++ b/Platform/TigerlakeBoardPkg/AcpiTables/Dsdt/Dsdt.asl
@@ -194,7 +194,6 @@ DefinitionBlock (
Include ("FwuWmi.asl")
Include ("Gpe.asl")
Include ("Pep.asl")
- Include ("Connectivity.asl")
Include ("PchRpPxsxWrapper.asl")
Include ("SerialIoDevices.asl")
Include ("SerialIoTimingParametersEmbedded.asl")
@@ -202,10 +201,6 @@ DefinitionBlock (
Include ("HIDWakeDSM.asl")
Include ("PinDriverLib.asl")
- If(LEqual(CVFS,1)) {
- Include("Cvf.asl")
- }
-
If (LAnd(LNotEqual(PSWP, 0), LEqual(RPNB, 0x05))) {
Scope(\_SB.PC00.RP05) {
Method (PPRW, 0) {