From 33e18bc1bcbf508e7aaa06d7a58f6f3436111b33 Mon Sep 17 00:00:00 2001
From: Aiden Park <aiden.park@intel.com>
Date: Mon, 21 Oct 2019 09:30:51 -0700
Subject: [PATCH] Silicon init with eMMC HS400 mode config (#407)

This patch is a follow-up patch of #380. If a platform disables HS400 mode,
silicon init code will configure eMMC in HS200. Other modes not in scope.

This will also fix #406.

Signed-off-by: Aiden Park <aiden.park@intel.com>
---
 .../Library/Stage2BoardInitLib/Stage2BoardInitLib.c            | 3 +++
 .../Library/Stage2BoardInitLib/Stage2BoardInitLib.inf          | 1 +
 .../Library/Stage2BoardInitLib/Stage2BoardInitLib.c            | 2 +-
 .../Library/Stage2BoardInitLib/Stage2BoardInitLib.inf          | 3 ++-
 4 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/Platform/ApollolakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c b/Platform/ApollolakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
index 3e265fa1..2ba05fcc 100644
--- a/Platform/ApollolakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
+++ b/Platform/ApollolakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
@@ -1019,6 +1019,9 @@ UpdateFspConfig (
   FspsConfig->SdioEnabled                 = (UINT8)DevEnCfgData->DevEnControl1.SdioEnable;
   FspsConfig->SmbusEnable                 = (UINT8)DevEnCfgData->DevEnControl1.SmbusEnable;
 
+  // Set HS200 if HS400 is disabled. No DDR50 in scope.
+  FspsConfig->eMMCHostMaxSpeed            = (UINT8)((FeaturePcdGet (PcdEmmcHs400SupportEnabled) != 0) ? 0 : 1);
+
   FspsConfig->PortUsb20Enable[0]          = (UINT8)DevEnCfgData->DevEnControl2.Usb20Port0Enable;
   FspsConfig->PortUsb20Enable[1]          = (UINT8)DevEnCfgData->DevEnControl2.Usb20Port1Enable;
   FspsConfig->PortUsb20Enable[2]          = (UINT8)DevEnCfgData->DevEnControl2.Usb20Port2Enable;
diff --git a/Platform/ApollolakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.inf b/Platform/ApollolakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.inf
index 948c608b..a883d23c 100644
--- a/Platform/ApollolakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.inf
+++ b/Platform/ApollolakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.inf
@@ -98,3 +98,4 @@
   gPlatformModuleTokenSpaceGuid.PcdSmramTsegBase
   gPlatformModuleTokenSpaceGuid.PcdSmramTsegSize
   gPlatformModuleTokenSpaceGuid.PcdFuncCpuInitHook
+  gPlatformCommonLibTokenSpaceGuid.PcdEmmcHs400SupportEnabled
diff --git a/Platform/CoffeelakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c b/Platform/CoffeelakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
index 151d0e41..9be826e8 100644
--- a/Platform/CoffeelakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
+++ b/Platform/CoffeelakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
@@ -1327,7 +1327,7 @@ UpdateFspConfig (
   FspsUpd->FspsConfig.Enable8254ClockGatingOnS3 = 0;
 
   FspsUpd->FspsConfig.ScsEmmcEnabled      = 1;
-  FspsUpd->FspsConfig.ScsEmmcHs400Enabled = 1;
+  FspsUpd->FspsConfig.ScsEmmcHs400Enabled = (UINT8)((FeaturePcdGet (PcdEmmcHs400SupportEnabled) != 0) ? 1 : 0);
   FspsUpd->FspsConfig.ScsSdCardEnabled    = 0;
   FspsUpd->FspsConfig.ScsUfsEnabled       = 0;
 
diff --git a/Platform/CoffeelakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.inf b/Platform/CoffeelakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.inf
index 3f730771..5947786b 100644
--- a/Platform/CoffeelakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.inf
+++ b/Platform/CoffeelakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.inf
@@ -80,4 +80,5 @@
   gPlatformModuleTokenSpaceGuid.PcdSmbiosStringsPtr
   gPlatformModuleTokenSpaceGuid.PcdSmbiosStringsCnt
   gPlatformModuleTokenSpaceGuid.PcdSmbiosTablesBase
-  gPlatformModuleTokenSpaceGuid.PcdSmbiosEnabled
\ No newline at end of file
+  gPlatformModuleTokenSpaceGuid.PcdSmbiosEnabled
+  gPlatformCommonLibTokenSpaceGuid.PcdEmmcHs400SupportEnabled