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<section id="rplp-rki-board">
<span id="id1"></span><h1>Rock Island Board<a class="headerlink" href="#rplp-rki-board" title="Permalink to this heading"></a></h1>
<p>The Rock Island Reference Design is a platform developed by Intel, featuring the 13th Gen Intel® Core™ Mobile Processor, specifically tailored for network and edge applications.</p>
<section id="prerequisites">
<h2>Prerequisites<a class="headerlink" href="#prerequisites" title="Permalink to this heading"></a></h2>
<p>To start developing SBL, the following equipment, software and environments are required:</p>
<ul class="simple">
<li><p><a href="https://www.seavo.com/en/products/products-info_itemid_482.html" target="_blank">Rock Island Reference Design Board</a></p></li>
<li><p>DediProg SF600 Programmer and 1.27mm 2x4 Cable with Female Header</p></li>
<li><p>USB to UART TTL Cable 4 Pins</p></li>
<li><p>Windows host or Linux host (see <a class="reference internal" href="../getting-started/build-host-setup.html#running-on-windows"><span class="std std-ref">Building on Windows</span></a> or <a class="reference internal" href="../getting-started/build-host-setup.html#running-on-linux"><span class="std std-ref">Building on Linux</span></a> for details)</p></li>
<li><p>Internet access</p></li>
</ul>
</section>
<section id="board-setup">
<h2>Board Setup<a class="headerlink" href="#board-setup" title="Permalink to this heading"></a></h2>
<a class="reference internal image-reference" href="../_images/rki-setup.jpg"><img alt="Rock Island Board Setup" class="align-center" src="../_images/rki-setup.jpg" style="width: 600px;" /></a>
</section>
<section id="before-you-start">
<h2>Before You Start<a class="headerlink" href="#before-you-start" title="Permalink to this heading"></a></h2>
<div class="admonition warning">
<p class="admonition-title">Warning</p>
<p>As you plan to reprogram the SPI flash, it’s a good idea to backup the pre-installed BIOS image first.</p>
</div>
<p>Boot the board and enter BIOS setup menu to get familiar with the board features and settings.</p>
</section>
<section id="debug-uart">
<h2>Debug UART<a class="headerlink" href="#debug-uart" title="Permalink to this heading"></a></h2>
<p>Early boot serial debug console can be reached via UART0 located on J9M1 header. Make sure you can observe serial output message running the factory BIOS first.</p>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>To make your own UART debug adapter by direct wiring, refer to J9M1 header pinout for UART0:</p>
<table class="docutils align-default">
<tbody>
<tr class="row-odd"><td><p>Pin</p></td>
<td><p>Signal</p></td>
</tr>
<tr class="row-even"><td><p>1</p></td>
<td><p>UART0_TXD</p></td>
</tr>
<tr class="row-odd"><td><p>2</p></td>
<td><p>UART0_RXD</p></td>
</tr>
<tr class="row-even"><td><p>5</p></td>
<td><p>GND</p></td>
</tr>
</tbody>
</table>
</div>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>Configure host PuTTY or minicom to 115200bps, 8N1, no hardware flow control.</p>
</div>
</section>
<section id="building">
<h2>Building<a class="headerlink" href="#building" title="Permalink to this heading"></a></h2>
<p><a href="https://www.seavo.com/en/products/products-info_itemid_482.html" target="_blank">Rock Island Reference Design Board</a> is based on Intel Raptor Lake-P. To build:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">python</span> <span class="n">BuildLoader</span><span class="o">.</span><span class="n">py</span> <span class="n">build</span> <span class="n">rplp</span>
</pre></div>
</div>
<p>The output image is generated under <code class="docutils literal notranslate"><span class="pre">Outputs\rplp</span></code> directory.</p>
</section>
<section id="stitching">
<h2>Stitching<a class="headerlink" href="#stitching" title="Permalink to this heading"></a></h2>
<p>Option 1: Stitch SBL image with factory BIOS IFWI image using <code class="docutils literal notranslate"><span class="pre">StitchLoader.py</span></code>:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">python</span> <span class="n">Platform</span>\<span class="n">RaptorlakeBoardPkg</span>\<span class="n">Script</span>\<span class="n">StitchLoader</span><span class="o">.</span><span class="n">py</span> <span class="o">-</span><span class="n">i</span> <span class="o">&lt;</span><span class="n">BIOS_IFWI_IMAGE</span><span class="o">&gt;</span> <span class="o">-</span><span class="n">s</span> <span class="n">Outputs</span>\<span class="n">rplp</span>\<span class="n">SlimBootloader</span><span class="o">.</span><span class="n">bin</span> <span class="o">-</span><span class="n">o</span> <span class="o">&lt;</span><span class="n">SBL_IFWI_IMAGE</span><span class="o">&gt;</span> <span class="o">-</span><span class="n">p</span> <span class="mh">0xAA00001F</span>
<span class="o">&lt;</span><span class="n">BIOS_IFWI_IMAGE</span><span class="o">&gt;</span> <span class="p">:</span> <span class="n">Input</span> <span class="n">file</span><span class="o">.</span> <span class="n">Factory</span> <span class="n">BIOS</span> <span class="n">extracted</span> <span class="kn">from</span> <span class="nn">Rock</span> <span class="n">Island</span> <span class="n">board</span><span class="o">.</span>
<span class="o">&lt;</span><span class="n">SBL_IFWI_IMAGE</span><span class="o">&gt;</span> <span class="p">:</span> <span class="n">Output</span> <span class="n">file</span><span class="o">.</span> <span class="n">New</span> <span class="n">IFWI</span> <span class="n">image</span> <span class="k">with</span> <span class="n">SBL</span> <span class="ow">in</span> <span class="n">BIOS</span> <span class="n">region</span><span class="o">.</span>
<span class="o">-</span><span class="n">p</span> <span class="o">&lt;</span><span class="n">value</span><span class="o">&gt;</span> <span class="p">:</span> <span class="mi">4</span><span class="o">-</span><span class="n">byte</span> <span class="n">platform</span> <span class="n">data</span> <span class="k">for</span> <span class="n">platform</span> <span class="n">ID</span> <span class="p">(</span><span class="n">e</span><span class="o">.</span><span class="n">g</span><span class="o">.</span> <span class="mi">1</span><span class="n">F</span><span class="p">)</span> <span class="ow">and</span> <span class="n">debug</span> <span class="n">UART</span> <span class="n">port</span> <span class="n">index</span> <span class="p">(</span><span class="n">e</span><span class="o">.</span><span class="n">g</span><span class="o">.</span> <span class="mi">00</span><span class="p">)</span><span class="o">.</span>
</pre></div>
</div>
<p>Refer to <a class="reference internal" href="../tools/StitchTool.html#stitch-tool"><span class="std std-ref">Stitch Tool</span></a> for more details.</p>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>StitchLoader.py script works only if Boot Guard in the base image is not enabled, and the silicon is not fused with Boot Guard enabled.
If Boot Guard is enabled, please use StitchIfwi.py script instead.</p>
</div>
<p>Option 2: Stitch SBL image with firmware ingredients using <code class="docutils literal notranslate"><span class="pre">StitchIfwi.py</span></code>:</p>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>Ensure all the stitch components are ready in the stitching folder.</p>
</div>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">python</span> <span class="n">Platform</span>\<span class="n">RaptorlakeBoardPkg</span>\<span class="n">Script</span>\<span class="n">StitchIfwi</span><span class="o">.</span><span class="n">py</span> <span class="o">-</span><span class="n">b</span> <span class="n">fvme</span> <span class="o">-</span><span class="n">s</span> <span class="n">Outputs</span>\<span class="n">rplp</span>\<span class="n">Stitch_Components</span><span class="o">.</span><span class="n">zip</span> <span class="o">-</span><span class="n">c</span> <span class="n">Platform</span>\<span class="n">RaptorlakeBoardPkg</span>\<span class="n">Script</span>\<span class="n">StitchIfwiConfig_rplp</span><span class="o">.</span><span class="n">py</span> <span class="o">-</span><span class="n">w</span> <span class="n">stitching</span> <span class="o">-</span><span class="n">p</span> <span class="n">rplp</span> <span class="o">-</span><span class="n">o</span> <span class="n">rki</span> <span class="o">-</span><span class="n">d</span> <span class="mh">0xAA00001F</span>
</pre></div>
</div>
<p>The output image is generated under current working directory.</p>
</section>
<section id="flashing">
<h2>Flashing<a class="headerlink" href="#flashing" title="Permalink to this heading"></a></h2>
<p>Flash the generated SBL_IFWI_IMAGE to Rock Island board using a SPI programmer. Header J7Y2 on the board should be used.</p>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>Please ensure:</p>
<ol class="arabic simple">
<li><p>The alignment/polarity when connecting Dediprog to the board.</p></li>
<li><p>The power to the board is turned <strong>off</strong> while the programmer is connected (even when not in use).</p></li>
<li><p>The programmer is set to update the flash from offset 0x0.</p></li>
</ol>
</div>
</section>
<section id="slimbootloader-binary-for-capsule-image">
<h2>SlimBootloader Binary for Capsule Image<a class="headerlink" href="#slimbootloader-binary-for-capsule-image" title="Permalink to this heading"></a></h2>
<p>The <code class="docutils literal notranslate"><span class="pre">SlimBootloader.bin</span></code> image generated from the build steps above can be used to create a capsule image for firmware update:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">python</span> <span class="n">BootloaderCorePkg</span>\<span class="n">Tools</span>\<span class="n">GenCapsuleFirmware</span><span class="o">.</span><span class="n">py</span> <span class="o">-</span><span class="n">p</span> <span class="n">BIOS</span> <span class="n">Outputs</span>\<span class="n">rplp</span>\<span class="n">SlimBootloader</span><span class="o">.</span><span class="n">bin</span> <span class="o">-</span><span class="n">k</span> <span class="o">&lt;</span><span class="n">priv_key</span><span class="o">&gt;</span> <span class="o">-</span><span class="n">o</span> <span class="n">FwuImage</span><span class="o">.</span><span class="n">bin</span>
</pre></div>
</div>
<p>Refer to <a class="reference internal" href="../security/firmware-update.html#generate-capsule"><span class="std std-ref">Generating capsule</span></a> for more details.</p>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>Boot Guard would not work if directly using <code class="docutils literal notranslate"><span class="pre">Outputs\rplp\SlimBootloader.bin</span></code> for capsule image.</p>
</div>
</section>
<section id="triggering-firmware-update">
<h2>Triggering Firmware Update<a class="headerlink" href="#triggering-firmware-update" title="Permalink to this heading"></a></h2>
<p>Refer to <a class="reference internal" href="../security/firmware-update.html#firmware-update"><span class="std std-ref">Firmware Update</span></a> on how to trigger firmware update flow.</p>
<p>Below is an example to trigger firmware update in SBL shell:</p>
<ol class="arabic simple">
<li><p>Copy <code class="docutils literal notranslate"><span class="pre">FwuImage.bin</span></code> into root directory on FAT partition of a USB drive</p></li>
<li><p>Boot and press any key to enter SBL shell</p></li>
<li><p>Type command <code class="docutils literal notranslate"><span class="pre">fwupdate</span></code> from shell</p></li>
</ol>
<p>Observe SBL resets the platform and performs update flow. It resets <em>multiple</em> times to complete the update process.</p>
</section>
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