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<section id="configure-memory-down">
<span id="config-memory-down"></span><h1>Configure Memory Down<a class="headerlink" href="#configure-memory-down" title="Permalink to this heading"></a></h1>
<p>The term of <strong>Memory Down</strong> is used to describe when memory components such as DRAM devices are physically soldered onto a Printed Circuit Board (PCB). This is an alternative to using mechanical connectors to attach memory modules (DIMM) onto a system. Memory down configuration is often found in the embedded platforms due to the variety of constraints and usage models.</p>
<p>SBL supports memory down configuration via FSP UPDs. This guide provides some basic steps to configure SBL before calling FSP-M to initialize system memory.</p>
<p>Step 1 - Read schematic and understand DDR memory layout and model from datasheet.</p>
<p>Step 2 - Configure the following memory parameters in SBL</p>
<p>Start with <code class="docutils literal notranslate"><span class="pre">&lt;platform&gt;\CfgData\CfgData_Memory.yaml</span></code> to understand the possible values for memory parameters</p>
<p>For UP<sup>2</sup>, open <code class="docutils literal notranslate"><span class="pre">CfgData_Ext_Up2.dlt</span></code> and customize values that match the actual memory parameters. Given an example for 8GB LPDDR4 memory:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">...</span>
<span class="n">PLATFORMID_CFG_DATA</span><span class="o">.</span><span class="n">PlatformId</span> <span class="o">|</span> <span class="mh">0x000E</span> <span class="o">&lt;--</span> <span class="n">Match</span> <span class="n">actual</span> <span class="n">Board</span> <span class="n">ID</span>
<span class="n">MEMORY_CFG_DATA</span><span class="o">.</span><span class="n">DualRankSupportEnable</span> <span class="o">|</span> <span class="mh">0x1</span>
<span class="n">MEMORY_CFG_DATA</span><span class="o">.</span><span class="n">RmtMode</span> <span class="o">|</span> <span class="mh">0x0</span>
<span class="n">MEMORY_CFG_DATA</span><span class="o">.</span><span class="n">MemorySizeLimit</span> <span class="o">|</span> <span class="mh">0x0</span>
<span class="n">MEMORY_CFG_DATA</span><span class="o">.</span><span class="n">Ch0_RankEnable</span> <span class="o">|</span> <span class="mh">0x3</span> <span class="o">&lt;--</span> <span class="n">bit</span> <span class="n">masks</span> <span class="k">for</span> <span class="n">dual</span> <span class="n">Rank</span><span class="o">.</span> <span class="mh">0x1</span> <span class="k">for</span> <span class="n">single</span> <span class="n">rank</span><span class="p">;</span> <span class="mh">0x0</span> <span class="k">for</span> <span class="n">no</span> <span class="n">rank</span> <span class="p">(</span><span class="n">no</span> <span class="n">memory</span> <span class="n">chip</span><span class="p">)</span>
<span class="n">MEMORY_CFG_DATA</span><span class="o">.</span><span class="n">Ch0_DramDensity</span> <span class="o">|</span> <span class="mh">0x2</span> <span class="o">&lt;--</span> <span class="mi">8</span><span class="n">Gb</span> <span class="p">(</span><span class="n">check</span> <span class="n">datasheet</span><span class="p">)</span>
<span class="n">MEMORY_CFG_DATA</span><span class="o">.</span><span class="n">Ch1_RankEnable</span> <span class="o">|</span> <span class="mh">0x3</span>
<span class="n">MEMORY_CFG_DATA</span><span class="o">.</span><span class="n">Ch1_DramDensity</span> <span class="o">|</span> <span class="mh">0x2</span>
<span class="n">MEMORY_CFG_DATA</span><span class="o">.</span><span class="n">Ch2_RankEnable</span> <span class="o">|</span> <span class="mh">0x3</span>
<span class="n">MEMORY_CFG_DATA</span><span class="o">.</span><span class="n">Ch2_DramDensity</span> <span class="o">|</span> <span class="mh">0x2</span>
<span class="n">MEMORY_CFG_DATA</span><span class="o">.</span><span class="n">Ch3_RankEnable</span> <span class="o">|</span> <span class="mh">0x3</span>
<span class="n">MEMORY_CFG_DATA</span><span class="o">.</span><span class="n">Ch3_DramDensity</span> <span class="o">|</span> <span class="mh">0x2</span>
<span class="n">MEMORY_CFG_DATA</span><span class="o">.</span><span class="n">RmtCheckRun</span> <span class="o">|</span> <span class="mh">0x3</span>
<span class="o">...</span>
</pre></div>
</div>
<p>Optionally, you can use Configuration Editor to graphically view and modify configurations. See <a class="reference external" href="https://slimbootloader.github.io/developer-guides/configuration.html">https://slimbootloader.github.io/developer-guides/configuration.html</a> for details.</p>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>If FSP UPD implementation supports hardcoded SPD table, simply replacing the SPD binary file under <code class="docutils literal notranslate"><span class="pre">&lt;platform&gt;\CfgData</span></code>. The file name of a SPD binary can be found in <code class="docutils literal notranslate"><span class="pre">&lt;platform&gt;\CfgData\CfgData_MemSpd.yaml</span></code>. If a platform supports more than one type of memory configuration, the <code class="docutils literal notranslate"><span class="pre">MEMORY_CFG_DATA.SpdDataSel</span></code> must be carefully set. Take Tiger Lake as an example: Spd_Ddrlp4.bin and Spd_Ddrlp5.bin are for LPDDR4 and LPDDR5 respectivly. The index of Spd_Ddrlp4.bin is 1, and it is 2 for Spd_Ddrlp5.bin.</p>
<p>In a board dlt file:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">MEMORY_CFG_DATA</span><span class="o">.</span><span class="n">SpdAddressTable</span> <span class="o">|</span> <span class="p">{</span><span class="o">...</span><span class="p">,</span> <span class="mi">0</span><span class="p">,</span> <span class="o">...</span> <span class="p">}</span> <span class="o">&lt;--</span> <span class="n">when</span> <span class="mi">0</span><span class="p">,</span> <span class="n">FSP</span> <span class="n">will</span> <span class="n">use</span> <span class="n">hardcoded</span> <span class="n">SPD</span> <span class="k">for</span> <span class="n">the</span> <span class="n">memory</span> <span class="n">slot</span> <span class="p">(</span><span class="n">mem</span> <span class="n">controller</span> <span class="n">X</span><span class="p">,</span> <span class="n">channel</span> <span class="n">Y</span><span class="p">,</span> <span class="n">Dimm</span> <span class="n">Z</span><span class="p">)</span><span class="o">.</span> <span class="n">Otherwise</span><span class="p">,</span> <span class="n">FSP</span> <span class="n">reads</span> <span class="n">its</span> <span class="n">SPD</span> <span class="kn">from</span> <span class="nn">the</span> <span class="n">smbus</span> <span class="n">address</span><span class="o">.</span>
<span class="n">MEMORY_CFG_DATA</span><span class="o">.</span><span class="n">SpdDataSelXYZ</span> <span class="o">|</span> <span class="mi">1</span> <span class="o">&lt;--</span> <span class="n">using</span> <span class="n">LPDDR4</span> <span class="n">hardcoded</span> <span class="n">SPD</span> <span class="k">for</span> <span class="n">memory</span> <span class="n">slot</span> <span class="n">XYZ</span><span class="o">.</span> <span class="n">Or</span>
<span class="n">MEMORY_CFG_DATA</span><span class="o">.</span><span class="n">SpdDataSelXYZ</span> <span class="o">|</span> <span class="mi">2</span> <span class="o">&lt;--</span> <span class="n">using</span> <span class="n">LPDDR5</span>
</pre></div>
</div>
</div>
<p>Step 3 - Build, stitch and test</p>
<p>If the memory configuration is correct, SBL should boot all the way to the shell. Verify the memory map information from the log to ensure the memory size matches with hardware.</p>
<p>Otherwise, SBL may hang after calling FSP-M and never returns. In this case, you have two troubleshooting options:</p>
<ol class="arabic simple">
<li><p>Re-examine the configuration values, make changes and repeat.</p></li>
<li><p>Object FSP debug build and get debugging output message during memory training flow.</p></li>
</ol>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>Please contact Intel representatives for how to obtain FSP source code.</p>
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