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<li class="toctree-l3"><a class="reference internal" href="#stage-1a">Stage 1A</a></li>
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<li class="toctree-l3"><a class="reference internal" href="#stage-1b">Stage 1B</a></li>
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<li class="toctree-l2"><a class="reference internal" href="#ldrglobal-loader-global-data">LdrGlobal - Loader Global Data</a></li>
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<section id="boot-flow">
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<span id="id1"></span><h1>Boot Flow<a class="headerlink" href="#boot-flow" title="Permalink to this heading"></a></h1>
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<p>SBL uses a linear staged boot flow to initialize platform and launch OS. It consists of four stages:</p>
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<table class="docutils align-default">
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<thead>
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<tr class="row-odd"><th class="head"><p>Stage</p></th>
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<th class="head"><p>Description</p></th>
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</tr>
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</thead>
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<tbody>
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<tr class="row-even"><td><p>Stage 1A</p></td>
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<td><p>Pre-memory initialization</p></td>
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</tr>
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<tr class="row-odd"><td><p>Stage 1B</p></td>
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<td><p>Initialize main memory</p></td>
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</tr>
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<tr class="row-even"><td><p>Stage 2</p></td>
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<td><p>Post memory initialization: initialize CPU, I/O controllers, devices etc.</p></td>
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</tr>
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<tr class="row-odd"><td><p>Payload</p></td>
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<td><p>Load, verify and launch OS images; or perform firmware update</p></td>
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</tr>
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</tbody>
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</table>
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<div class="graphviz"><img src="../_images/graphviz-37fe79f57f3e9ad6b66fd4b50c1d12ac27eba0e0.png" alt="digraph bootflow {
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bgcolor="transparent";
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rankdir=LR;
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compound=true;
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node [fontsize=10, shape=record, style=rounded];
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edge [fontsize=10];
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subgraph cluster_stages {
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label="Boot Stages"; fontsize=11;
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style="filled,rounded"; color="#F0F0F0";
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"Stage 1A" -> "Stage 1B" -> "Stage 2" -> "Payload";
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}
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}" class="graphviz" /></div>
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<div class="admonition note">
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<p class="admonition-title">Note</p>
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<p>When verified boot is enabled, each current stage verifies the next stage before transferring control to the next.
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If verification fails, one of two things occurs. If resiliency is enabled, the boot is swapped over to the alternate partition
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to recover the broken partition (see <a class="reference internal" href="../security/firmware-resiliency-and-recovery.html#firmware-resiliency-and-recovery"><span class="std std-ref">Firmware Resiliency and Recovery</span></a>). Otherwise, the boot is halted.</p>
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</div>
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<section id="stage-1a">
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<h2>Stage 1A<a class="headerlink" href="#stage-1a" title="Permalink to this heading"></a></h2>
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<p>After coming out of reset, Stage 1A sets up the initial exectution environment to support the
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execution of the following stages. When the processor starts executing from the reset vector,
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writeable memory may not be available and a stack might have not been setup. So, the reset vector
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code is typically implemented using assembly language instructions. Stage 1A is also excuted from
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the flash (Read-only memory) and the lack of writeable memory prevents the usage of global variables.</p>
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<p>Stage 1A contains a module called VTF (Volume Top File) which is placed at the top within the Stage 1A FV.
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The VTF contains the reset vector code and hence the VTF needs to be placed at an appropriate
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address so that the reset vector code in the the Vtf0 file (Identified by the GUID <code class="docutils literal notranslate"><span class="pre">1BA0062E-C779-4582-8566-336AE8F78F09</span></code>)
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aligns with the reset vector of Intel x86 architecture.</p>
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<p>The entry point for the Stage1A module within the Stage1A FV (<code class="docutils literal notranslate"><span class="pre">_ModuleEntryPoint</span></code>) is placed as
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the first DWORD of the built FV. The reset vector code from the Vtf0 jumps to this address and continues
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from the <code class="docutils literal notranslate"><span class="pre">_ModuleEntryPoint</span></code> defined in <code class="docutils literal notranslate"><span class="pre">SecEntry.nasm</span></code>.</p>
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<p>After coming out of reset, Stage 1A performs the following initialization steps:</p>
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<ul>
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<li><p>Switch from 16-bit real mode to 32-bit protected mode to provide full 32-bit memory addressibility</p></li>
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<li><p>Calls the FSP-T provided <code class="docutils literal notranslate"><span class="pre">TempRamInit()</span></code> API which configures a temporary writeable memory</p></li>
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<li><p>Sets up a stack in the Temporary memory initialized by FSP’s <code class="docutils literal notranslate"><span class="pre">TempRamInit()</span></code> API</p></li>
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<li><p>Initializes Stage 1A parameters, jumps to C code</p></li>
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<li><p>Initializes Global Data structures (<code class="docutils literal notranslate"><span class="pre">LdrGlobal</span></code>) to be used by the Bootloader</p></li>
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<li><p>Initializes the configured debug port by calling into Board-specific initialization functions</p></li>
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<li><p>Loads and jumps to Stage 1B</p>
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<blockquote>
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<div><ul class="simple">
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<li><p>The Stage 1B entry point is defined by the <code class="docutils literal notranslate"><span class="pre">_ModuleEntryPoint</span></code> (provided by <code class="docutils literal notranslate"><span class="pre">ModuleEntryLib</span></code>).</p></li>
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</ul>
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</div></blockquote>
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</li>
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</ul>
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<p><strong>Data Passed from Stage 1A assembly to Stage 1A C code</strong> –</p>
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<ul class="simple">
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<li><p>Stage 1A C code expects the struct <code class="docutils literal notranslate"><span class="pre">STAGE1A_ASM_PARAM</span></code> to be on the stack</p></li>
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<li><p><code class="docutils literal notranslate"><span class="pre">SecEntry.nasm</span></code> pushes the elements of the struct on the stack in the expected order</p></li>
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</ul>
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<p><strong>Data Passed from Stage 1A to Stage 1B</strong> –</p>
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<ul class="simple">
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<li><p><code class="docutils literal notranslate"><span class="pre">Stage1A_PARAM</span></code> struct</p></li>
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</ul>
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</section>
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<section id="stage-1b">
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<h2>Stage 1B<a class="headerlink" href="#stage-1b" title="Permalink to this heading"></a></h2>
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<p>The primary purpose of Stage1B is to bring up the system memory and performs the following
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initialization steps:</p>
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<ul>
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<li><p>Early platform init</p></li>
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<li><p>Load and build configuration database</p></li>
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<li><p>Calls FSP-M provided <code class="docutils literal notranslate"><span class="pre">FspMemoryInit()</span></code> which initializes the system’s main memory</p></li>
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<li><p>Sets up the global data structures in RAM and migrates LdrGlobal from the stack in temporary memory to the main memory</p></li>
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<li><p>Saves system memory information like - TOLUM (Top of low usable memory), TOUUM (Top of upper usable memory), etc.</p></li>
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<li><p>Switches from the stack in temporary memory to the one in the main memory</p></li>
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<li><p>Calls FSP-M provided <code class="docutils literal notranslate"><span class="pre">TempRamExit()</span></code> API to tear down the temporary memory set up in the
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cache and returns the cache to its normal operating mode</p></li>
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<li><p>Loads and jumps to Stage2</p>
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<blockquote>
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<div><ul class="simple">
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<li><p>The Stage 2 entry point is defined by the <code class="docutils literal notranslate"><span class="pre">_ModuleEntryPoint</span></code> (provided by <code class="docutils literal notranslate"><span class="pre">ModuleEntryLib</span></code>).</p></li>
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</ul>
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</div></blockquote>
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</li>
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</ul>
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<p>Data Passed from Stage 1B to Stage 2</p>
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<ul class="simple">
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<li><p><code class="docutils literal notranslate"><span class="pre">STAGE2_PARAM</span></code> struct</p></li>
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</ul>
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</section>
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<section id="stage-2">
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<h2>Stage 2<a class="headerlink" href="#stage-2" title="Permalink to this heading"></a></h2>
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<p>Stage 2 is the “post-memory” stage and is responsible for completing system initialization after
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main memory is available. Stage 2 code is run from main memory and may be compressed. Stage 2 includes
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relocation information which allows Stage 2 to be run from the main memory.</p>
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<p>Stage 2 performs the following initialization steps:</p>
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<ul>
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<li><p>Completes remaning GPIO initialization</p></li>
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<li><p>Calls FSP-S provided <code class="docutils literal notranslate"><span class="pre">FspSiliconInit()</span></code> API to initialize the chipset and I/O controllers</p></li>
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<li><p>PCI Enumeration and resource allocation</p></li>
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<li><p>ACPI initlization</p></li>
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<li><p>Prepares HOBs required by the payload</p></li>
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<li><p>Calls FSP-S provided <code class="docutils literal notranslate"><span class="pre">FspNotifyPhase</span></code> APIs - <code class="docutils literal notranslate"><span class="pre">ReadyToBoot</span></code>, <code class="docutils literal notranslate"><span class="pre">EndOfFirmware</span></code></p></li>
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<li><p>Loads and jumps to the payload. Stage 2 passes the HOB List pointer, and the Payload executable base to the payload.</p>
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<div class="highlight-C notranslate"><div class="highlight"><pre><span></span><span class="c1">// Payload Entry Point</span>
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<span class="n">VOID</span>
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<span class="n">EFIAPI</span>
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<span class="n">SecStartup</span><span class="w"> </span><span class="p">(</span>
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<span class="w"> </span><span class="n">IN</span><span class="w"> </span><span class="n">VOID</span><span class="w"> </span><span class="o">*</span><span class="n">HobListPtr</span><span class="p">,</span>
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<span class="w"> </span><span class="n">IN</span><span class="w"> </span><span class="n">VOID</span><span class="w"> </span><span class="o">*</span><span class="n">PldBase</span>
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<span class="w"> </span><span class="p">)</span>
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</pre></div>
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</div>
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</li>
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||
</ul>
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||
</section>
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||
</section>
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<section id="ldrglobal-loader-global-data">
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<h1>LdrGlobal - Loader Global Data<a class="headerlink" href="#ldrglobal-loader-global-data" title="Permalink to this heading"></a></h1>
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<p>The Loader Global Data structure is used to store important information throughout the different
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execution phases of the bootloader. It consists of information like available memory start and
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end addresses, top of stack address, performance data, HOB pointers, Config data pointers,
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Payload ID, etc. The entire list can be seen in <code class="docutils literal notranslate"><span class="pre">BootloaderCoreGlobal.h</span></code> - <code class="docutils literal notranslate"><span class="pre">LOADER_GLOBAL_DATA</span></code>
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struct. This data is passed from stage to stage until the bootloader passes control to the
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||
payload. <code class="docutils literal notranslate"><span class="pre">LdrGlobal</span></code> is not passed to the payload. The data is however still maintained within
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||
the bootloader reserved memory to be used for S3 resume.</p>
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||
<p>Stage 1A creates the data structure (<code class="docutils literal notranslate"><span class="pre">LOADER_GLOBAL_DATA</span></code>) and a pointer to this structure on
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the stack. Stage 1A adds the following info to <code class="docutils literal notranslate"><span class="pre">LdrGlobal</span></code>: Stack information, Available memory
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top and bottom, temporary memory top and bottom, debug level.</p>
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<p>Stage 1B retrieves the <code class="docutils literal notranslate"><span class="pre">LdrGlobal</span></code> pointer and appends more information to the data
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(Key Hash Store, Config Database). Once Stage 1B has initialized main memory using FSP-M,
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it creates the data structure in the memory reserved for the bootloader by FSP-M and copies
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over the data from the earlier temporary memory. Stage 1B adds and updates several fields
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in <code class="docutils literal notranslate"><span class="pre">LdrGlobal</span></code> like available memory top & bottom, DMA buffer pointer, S3 data pointer.</p>
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<p>Stage 2 again retrieves the <code class="docutils literal notranslate"><span class="pre">LdrGlobal</span></code> pointer and appends the <code class="docutils literal notranslate"><span class="pre">HobList</span></code> pointer to the global
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data struct to be used by S3 resume functionality.</p>
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<p>Since <code class="docutils literal notranslate"><span class="pre">LdrGlobal</span></code> data is used across all stages of Slim Bootloader, a predefined or consistent
|
||
way to retrieve the <code class="docutils literal notranslate"><span class="pre">LdrGlobal</span></code> data is required. As interrupts are not used in the bootloader,
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the <code class="docutils literal notranslate"><span class="pre">IDTR</span></code> is used to store the pointer to the <code class="docutils literal notranslate"><span class="pre">LdrGlobal</span></code> struct. <code class="docutils literal notranslate"><span class="pre">BootloaderCoreLib</span></code> abstracts this
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location by providing <code class="docutils literal notranslate"><span class="pre">GetLoaderGlobalDataPointer()</span></code> and <code class="docutils literal notranslate"><span class="pre">SetLoaderGlobalDataPointer()</span></code> functions.
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||
After creating the <code class="docutils literal notranslate"><span class="pre">LdrGlobal</span></code>, Stage 1A then saves the pointer to the structure by calling the
|
||
<code class="docutils literal notranslate"><span class="pre">SetLoaderGlobalDataPointer()</span></code> function. Stage 1B and Stage 2 use the <code class="docutils literal notranslate"><span class="pre">GetLoaderGlobalDataPointer()</span></code>
|
||
function to retrieve the location.</p>
|
||
</section>
|
||
<section id="end-to-end-call-graph">
|
||
<span id="call-graph"></span><h1>End-to-End Call Graph<a class="headerlink" href="#end-to-end-call-graph" title="Permalink to this heading"></a></h1>
|
||
<p>The function call graph in SBL code from reset vector to OS launch.</p>
|
||
<a class="reference internal image-reference" href="../_images/call_graph.png"><img alt="|SPN| Calling Graph" class="align-center" src="../_images/call_graph.png" style="width: 600px;" /></a>
|
||
<div class="admonition note">
|
||
<p class="admonition-title">Note</p>
|
||
<p>This call graph changes if resiliency is enabled and recovery is attempted (see <a class="reference internal" href="../security/firmware-resiliency-and-recovery.html#firmware-resiliency-and-recovery"><span class="std std-ref">Firmware Resiliency and Recovery</span></a>).</p>
|
||
</div>
|
||
</section>
|
||
<section id="platform-initialization">
|
||
<h1>Platform Initialization<a class="headerlink" href="#platform-initialization" title="Permalink to this heading"></a></h1>
|
||
<p>In SBL, board initialization code is located in <code class="docutils literal notranslate"><span class="pre">Platform/<platform_foo></span></code> directory. Each stage provides a ‘hook point’ for board specific code. To port a new board, one should implement changes in <code class="docutils literal notranslate"><span class="pre">BoardInit()</span></code> function for each stage under <code class="docutils literal notranslate"><span class="pre">Platform/<platform_foo>/Library</span></code> directory:</p>
|
||
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">VOID</span>
|
||
<span class="n">BoardInit</span> <span class="p">(</span>
|
||
<span class="n">IN</span> <span class="n">BOARD_INIT_PHASE</span> <span class="n">InitPhase</span>
|
||
<span class="p">);</span>
|
||
</pre></div>
|
||
</div>
|
||
<p>During board initialization, SBL further divides the flow into multiple phases to provide a fine granularity control. These phases are defined in <code class="docutils literal notranslate"><span class="pre">PlatformService.h</span></code>:</p>
|
||
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">typedef</span> <span class="n">enum</span> <span class="p">{</span>
|
||
<span class="n">PreTempRamInit</span> <span class="o">=</span> <span class="mh">0x10</span><span class="p">,</span>
|
||
<span class="n">PostTempRamInit</span> <span class="o">=</span> <span class="mh">0x20</span><span class="p">,</span>
|
||
<span class="n">PreConfigInit</span> <span class="o">=</span> <span class="mh">0x30</span><span class="p">,</span>
|
||
<span class="n">PostConfigInit</span> <span class="o">=</span> <span class="mh">0x40</span><span class="p">,</span>
|
||
<span class="n">PreMemoryInit</span> <span class="o">=</span> <span class="mh">0x50</span><span class="p">,</span>
|
||
<span class="n">PostMemoryInit</span> <span class="o">=</span> <span class="mh">0x60</span><span class="p">,</span>
|
||
<span class="n">PreTempRamExit</span> <span class="o">=</span> <span class="mh">0x70</span><span class="p">,</span>
|
||
<span class="n">PostTempRamExit</span> <span class="o">=</span> <span class="mh">0x80</span><span class="p">,</span>
|
||
<span class="n">PreSiliconInit</span> <span class="o">=</span> <span class="mh">0x90</span><span class="p">,</span>
|
||
<span class="n">PostSiliconInit</span> <span class="o">=</span> <span class="mh">0xA0</span><span class="p">,</span>
|
||
<span class="n">PrePciEnumeration</span> <span class="o">=</span> <span class="mh">0xB0</span><span class="p">,</span>
|
||
<span class="n">PostPciEnumeration</span> <span class="o">=</span> <span class="mh">0xC0</span><span class="p">,</span>
|
||
<span class="n">PrePayloadLoading</span> <span class="o">=</span> <span class="mh">0xD0</span><span class="p">,</span>
|
||
<span class="n">PostPayloadLoading</span> <span class="o">=</span> <span class="mh">0xE0</span><span class="p">,</span>
|
||
<span class="n">EndOfStages</span> <span class="o">=</span> <span class="mh">0xF0</span><span class="p">,</span>
|
||
<span class="n">ReadyToBoot</span> <span class="o">=</span> <span class="mh">0xF8</span><span class="p">,</span>
|
||
<span class="n">EndOfFirmware</span> <span class="o">=</span> <span class="mh">0xFF</span>
|
||
<span class="p">}</span> <span class="n">BOARD_INIT_PHASE</span><span class="p">;</span>
|
||
</pre></div>
|
||
</div>
|
||
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|
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