diff --git a/_images/mcl-setup.jpg b/_images/mcl-setup.jpg new file mode 100644 index 0000000..9d164fc Binary files /dev/null and b/_images/mcl-setup.jpg differ diff --git a/_images/upxi12rplp_setup.jpg b/_images/upxi12rplp_setup.jpg new file mode 100644 index 0000000..3391788 Binary files /dev/null and b/_images/upxi12rplp_setup.jpg differ diff --git a/_sources/getting-started/build-host-setup.rst.txt b/_sources/getting-started/build-host-setup.rst.txt index f8fe228..fae448f 100644 --- a/_sources/getting-started/build-host-setup.rst.txt +++ b/_sources/getting-started/build-host-setup.rst.txt @@ -30,7 +30,7 @@ Build Tools Download - Ubuntu Install required packages on Ubuntu:: - $ sudo apt-get install -y build-essential python uuid-dev openssl gcc-multilib qemu git + $ sudo apt install -y build-essential python3 uuid-dev openssl gcc-multilib qemu-system git iasl nasm Build using Dockers (Optional) @@ -133,6 +133,8 @@ LLVM 15.0.7 **Require:** Install to C:\\LLVM +.. note:: + Add an environment variable: CLANG_BIN=C:\LLVM\bin\ Openssl (latest) diff --git a/_sources/supported-hardware/mtl-mcl.rst.txt b/_sources/supported-hardware/mtl-mcl.rst.txt new file mode 100644 index 0000000..bd8f68a --- /dev/null +++ b/_sources/supported-hardware/mtl-mcl.rst.txt @@ -0,0 +1,124 @@ +.. MTL-MCL-board: + +|MTL-MCL| Board +--------------------------------- + +The Intel McLaren Island Reference Design Board (|mtl-mcl|) is an x86 maker board based on Intel platform Meteor Lake. The boards are used in IoT, industrial automation, digital signage areas, etc. + +Prerequisites +^^^^^^^^^^^^^^^^ + +|SPN| supports |Intel McLaren Island Reference Design Board|. To start developing |SPN|, the following equipment, software and environments are required: + +* |Intel McLaren Island Reference Design Board| +* DediProg SF600 programmer +* Linux host or windows host (see :ref:`running-on-linux` or :ref:`running-on-windows` for details) +* Internet access + +.. |Intel McLaren Island Reference Design Board| raw:: html + + Intel McLaren Island Reference Design Board + +.. |instructions| raw:: html + + instructions + +Board Setup +^^^^^^^^^^^^^^^^^ + +.. image:: /images/mcl-setup.jpg + :width: 600 + :alt: |MTL-MCL| Board Setup + :align: center + + +Before You Start +^^^^^^^^^^^^^^^^^ + +.. warning:: As you plan to reprogram the SPI flash, it's a good idea to backup the pre-installed BIOS image first. + + +Boot the board and enter BIOS setup menu to get familiar with the board features and settings. + +Debug UART +^^^^^^^^^^^ + +Serial port connector is the micro-usb connector, the location is near the sata port. + +.. note:: Configure host PuTTY or minicom to 115200bps, 8N1, no hardware flow control. + +Building +^^^^^^^^^^ + +|Intel McLaren Island Reference Design Board| is based on Intel |MTL|. To build:: + + python BuildLoader.py build mtl + +The output images are generated under ``Outputs`` directory. + +Stitching +^^^^^^^^^^ + +Stitch |SPN| images with factory BIOS image using the stitch tool:: + + python Platform/MeteorlakeBoardPkg/Script/StitchLoader.py -i -s Outputs/mtl/SlimBootloader.bin -o -p 0xAA00001F + + : Input file. Factory BIOS extracted from McLaren Island board. + : Output file. New IFWI image with SBL in BIOS region. + -p : 4-byte platform data for platform ID (e.g. 1F) and debug UART port index (e.g. 00). + +See :ref:`stitch-tool` on how to stitch the IFWI image with |SPN|. + +Stitch SBL images with IFWI ingredients:: + + python Platform/MeteorlakeBoardPkg/Script/StitchIfwi.py -b fvme + -s Outputs/mtl/Stitch_Components.zip + -c Platform/MeteorlakeBoardPkg/Script/StitchIfwiConfig_mcl.py + -w /Stitchifwi_components_mtl -p mtlp -d 0xAA00001F + +.. Note:: StitchLoader.py script works only if Boot Guard in the base image is not enabled, and the silicon is not fused with Boot Guard enabled. + If Boot Guard is enabled, please use StitchIfwi.py script instead. + + +Slimbootloader binary for capsule +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The Slimbootloader.bin image generated from the build steps above can be used to create a capsule image. +Please refer to :ref:`build-tool` on generating |SPN| image. + +For all |MTL| platforms, the below command can be used:: + + python ./BootloaderCorePkg/Tools/GenCapsuleFirmware.py -p BIOS Outputs//SlimBootloader.bin -k -o FwuImage.bin + +For more details on generating capsule image, please refer :ref:`generate-capsule`. + +Triggering Firmware Update +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Please refer to :ref:`firmware-update` on how to trigger firmware update flow. +Below is an example: + +To trigger firmware update in |SPN| shell: + +1. Copy ``FwuImage.bin`` into root directory on FAT partition of a USB key + +2. Boot and press any key to enter |SPN| shell + +3. Type command ``fwupdate`` from shell + + Observe |SPN| resets the platform and performs update flow. It resets *multiple* times to complete the update process. + +Flashing +^^^^^^^^^ + +Flash the generated SBL_IFWI_IMAGE_NAME to the target board using a DediProg SF600 programmer. + +.. note:: Refer the table above to identify the connector on the target board for SPI flash programmer. When using such device, please ensure: + + + #. The alignment/polarity when connecting Dediprog to the board. + #. The power to the board is turned **off** while the programmer is connected (even when not in use). + #. The programmer is set to update the flash from offset 0x0. + + +**Good Luck!** diff --git a/_sources/supported-hardware/upxtremei12rplp.rst.txt b/_sources/supported-hardware/upxtremei12rplp.rst.txt new file mode 100644 index 0000000..1da0c73 --- /dev/null +++ b/_sources/supported-hardware/upxtremei12rplp.rst.txt @@ -0,0 +1,153 @@ +.. _upx12-13th-board: + +|UPX12RPLP| Board +--------------------- + +The |UP Xtreme i12 13th board| (|UPX12RPLP|) is an x86 maker board based on Intel platform Raptor Lake-P. The UP boards are used in IoT, industrial automation, digital signage areas, etc. + +Prerequisites +^^^^^^^^^^^^^^^^ + +|SPN| supports |UPX12RPLP| maker board. To start developing |SPN|, the following equipment, software and environments are required: + +* |UP Xtreme i12 13th board| +* Custom SPI flashing cable (|instructions|). +* |USB 2.0 pin header cable| for debug uart output. OR `Make your own `_. +* DediProg SF100 or SF600 programmer +* Linux host (see :ref:`running-on-linux` for details) +* Internet access + +.. |UP Xtreme i12 13th board| raw:: html + + UP Xtreme i12 13th board + +.. |instructions| raw:: html + + instructions + +.. |USB 2.0 pin header cable| raw:: html + + USB 2.0 pin header cable + + +Board Setup +^^^^^^^^^^^^^^^^^ + +.. image:: /images/upxi12rplp_setup.jpg + :width: 600 + :alt: |UPX12RPLP| Board Setup + :align: center + + +Before You Start +^^^^^^^^^^^^^^^^^ + +.. warning:: As you plan to reprogram the SPI flash, it's a good idea to backup the pre-installed BIOS image first. + + +Boot the board and enter BIOS setup menu to get familiar with the board features and settings. + +.. _upx12-debug-uart-pinout: + +Early boot serial debug console can be reached via UART1 located on CN9 header on the |UPX12RPLP| board. Make sure you can observe serial output message running the factory BIOS first. + +.. note:: To make your own UART debug adapter by direct wiring, refer to CN9 Header Pinout for UART1: + + +--------+--------------+ + | Pin | Signal | + +--------+--------------+ + | 8 | GND | + +--------+--------------+ + | 9 | UART_RX | + +--------+--------------+ + | 10 | UART_TX | + +--------+--------------+ + + +Building +^^^^^^^^^^ + +|UPX12RPLP| board is based on Intel |RPLP|. To build:: + + python BuildLoader.py build rplp + +The output images are generated under ``Outputs`` directory. + + +Stitching +^^^^^^^^^^ + +Stitch |SPN| images with factory BIOS image using the stitch tool:: + + python Platform/AlderlakeBoardPkg/Script/StitchLoader.py -i -s Outputs/rplp/SlimBootloader.bin -o -p 0xAA000114 + + : Input file. Factory BIOS extracted from UP Xtreme i12 13th board. + : Output file. New IFWI image with SBL in BIOS region. + -p : 4-byte platform data for platform ID (e.g. 14) and debug UART port index (e.g. 01). + +.. Note:: StitchLoader.py script works only if Boot Guard in the base image is not enabled, and the silicon is not fused with Boot Guard enabled. + If Boot Guard is enabled, please use StitchIfwi.py script instead. + +See :ref:`stitch-tool` on how to stitch the IFWI image with |SPN|. + +Slimbootloader binary for capsule +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +A capsule image could ecapsulate a Slimbootloader image to be used in firmware update mechanism. More information is described in :ref:`firmware-update`. + +For the process running properly, an IFWI image programmed on board with TOP SWAP size configuration is required. + +.. note:: Enabling TOP SWAP size configuration requires additional firmware components and tools. + +Creating Slimbootloader binary for capsule image requires the following steps: + +Build |SPN| for |UPX12RPLP|:: + + python BuildLoader.py build rplp + +Edit the 4-byte platform data in Slimbootloader image by *Hexedit* or equivalent hexdecimal editor. + +Go to top of TOP SWAP A at address 0xCFFFF4, edit ``14 01 00 AA`` as below +:: + + 00CFFFF0 90 90 EB B9 14 01 00 AA A4 50 FF FF 00 50 FF FF ................ + +Go to top of TOP SWAP B at address 0xC7FFF4, edit ``14 01 00 AA`` as below +:: + + 00C7FFF0 90 90 EB B9 14 01 00 AA A4 50 FF FF 00 50 FF FF ................ + +For more details on TOP SWAP regions, please refer :ref:`flash-layout` + +Generate capsule update image ``FwuImage.bin``:: + + python BootloaderCorePkg/Tools/GenCapsuleFirmware.py -p BIOS Outputs/rplp/SlimBootloader.bin -k KEY_ID_FIRMWAREUPDATE_RSA3072 -o FwuImage.bin + +For more details on generating capsule image, please refer :ref:`generate-capsule`. + +Triggering Firmware Update +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Please refer to :ref:`firmware-update` on how to trigger firmware update flow. +Below is an example: + +To trigger firmware update in |SPN| shell: + +1. Copy ``FwuImage.bin`` into root directory on FAT partition of a USB key + +2. Boot and press any key to enter |SPN| shell + +3. Type command ``fwupdate`` from shell + + Observe |SPN| resets the platform and performs update flow. It resets *multiple* times to complete the update process. + +Flashing +^^^^^^^^^ + +Flash the IFWI image to |UPX12RPLP| board using a SPI programmer. Header CN19 on the board should be used, see |BIOS_CHIP_FLASHING| for additional details. + + +.. |BIOS_CHIP_FLASHING| raw:: html + + instructions + +**Good Luck!** diff --git a/getting-started/build-host-setup.html b/getting-started/build-host-setup.html index 898de6c..d1fa3dc 100644 --- a/getting-started/build-host-setup.html +++ b/getting-started/build-host-setup.html @@ -123,7 +123,7 @@

Build Tools Download - Ubuntu

Install required packages on Ubuntu:

-
$ sudo apt-get install -y build-essential python uuid-dev openssl gcc-multilib qemu git
+
$ sudo apt install -y build-essential python3 uuid-dev openssl gcc-multilib qemu-system git iasl nasm
 

 

 

@@ -183,6 +183,10 @@ Please ensure to install Dekstop Development with C++ along wit
 
LLVM 15.0.7

 
https://github.com/llvm/llvm-project/releases/tag/llvmorg-15.0.7/

 
Require: Install to C:\LLVM

+

+
Note

+
Add an environment variable: CLANG_BIN=C:\LLVM\bin\

+

 
Openssl (latest)

 
Download latest win64 version from https://wiki.openssl.org/index.php/Binaries)

 
Require: Install to C:\Openssl

@@ -217,7 +221,7 @@ For example: set OPENSSL_PATH=C:\Openssl\bin

 
   

     
© Copyright 2018 - 2024, Intel Corporation.
-      Last updated on Jun 07, 2024.
+      Last updated on Nov 15, 2024.
       

   

 
diff --git a/supported-hardware/index.html b/supported-hardware/index.html
index 4429178..8303c5f 100644
--- a/supported-hardware/index.html
+++ b/supported-hardware/index.html
@@ -59,6 +59,7 @@
 
  • Comet Lake RVP Board
    • 
 
  • Elkhart Lake CRB Board
    • 
 
  • Ice Lake -D CRB Boards
    • 
+
  • McLaren Island Board
    • 
 
  • Meteor Lake Platforms
    • 
 
  • QEMU Virtual Platform
    • 
 
  • Simics® QSP Virtual Platform
    • 
@@ -70,6 +71,7 @@
 
  • UP Xtreme Board
    • 
 
  • UP Xtreme i11 Board
    • 
 
  • UP Xtreme i12 Board
    • 
+
  • UP Xtreme i12 13th Board
    • 
 
  • Whiskey Lake CRB Board
    • 
 
 
@@ -116,6 +118,7 @@
 
  • Comet Lake RVP Board
    • 
 
  • Elkhart Lake CRB Board
    • 
 
  • Ice Lake -D CRB Boards
    • 
+
  • McLaren Island Board
    • 
 
  • Meteor Lake Platforms
    • 
 
  • QEMU Virtual Platform
    • 
 
  • Simics® QSP Virtual Platform
    • 
@@ -127,6 +130,7 @@
 
  • UP Xtreme Board
    • 
 
  • UP Xtreme i11 Board
    • 
 
  • UP Xtreme i12 Board
    • 
+
  • UP Xtreme i12 13th Board
    • 
 
  • Whiskey Lake CRB Board
    •
    @@ -144,7 +148,7 @@

    © Copyright 2018 - 2024, Intel Corporation. - Last updated on Jun 07, 2024. + Last updated on Nov 15, 2024.

    diff --git a/supported-hardware/mtl-mcl.html b/supported-hardware/mtl-mcl.html new file mode 100644 index 0000000..49e4a62 --- /dev/null +++ b/supported-hardware/mtl-mcl.html @@ -0,0 +1,263 @@ + + + + + + + McLaren Island Board — Slim Bootloader 1.0 documentation + + + + + + + + + + + + + + + + + + + + + + +
    + + +
    + +
    +
    +
    + +
    +
    +
    +
    + +
    +

    McLaren Island Board

    +

    The Intel McLaren Island Reference Design Board (McLaren Island) is an x86 maker board based on Intel platform Meteor Lake. The boards are used in IoT, industrial automation, digital signage areas, etc.

    +
    +

    Prerequisites

    +

    SBL supports Intel McLaren Island Reference Design Board. To start developing SBL, the following equipment, software and environments are required:

    + +
    +
    +

    Board Setup

    +|MTL-MCL| Board Setup + +
    +
    +

    Before You Start

    +
    +

    Warning

    +

    As you plan to reprogram the SPI flash, it’s a good idea to backup the pre-installed BIOS image first.

    +
    +

    Boot the board and enter BIOS setup menu to get familiar with the board features and settings.

    +
    +
    +

    Debug UART

    +

    Serial port connector is the micro-usb connector, the location is near the sata port.

    +
    +

    Note

    +

    Configure host PuTTY or minicom to 115200bps, 8N1, no hardware flow control.

    +
    +
    +
    +

    Building

    +

    Intel McLaren Island Reference Design Board is based on Intel Meteor Lake. To build:

    +
    python BuildLoader.py build mtl
+
    +
    +

    The output images are generated under Outputs directory.

    +
    +
    +

    Stitching

    +

    Stitch SBL images with factory BIOS image using the stitch tool:

    +
    python Platform/MeteorlakeBoardPkg/Script/StitchLoader.py -i <BIOS_IMAGE_NAME> -s Outputs/mtl/SlimBootloader.bin -o <SBL_IFWI_IMAGE_NAME> -p 0xAA00001F
+
+<BIOS_IMAGE>     : Input file. Factory BIOS extracted from McLaren Island board.
+<SBL_IFWI_IMAGE> : Output file. New IFWI image with SBL in BIOS region.
+-p <value>       : 4-byte platform data for platform ID (e.g. 1F) and debug UART port index (e.g. 00).
+
    +
    +

    See Stitch Tool on how to stitch the IFWI image with SBL.

    +

    Stitch SBL images with IFWI ingredients:

    +
    python Platform/MeteorlakeBoardPkg/Script/StitchIfwi.py  -b fvme
+-s Outputs/mtl/Stitch_Components.zip
+-c Platform/MeteorlakeBoardPkg/Script/StitchIfwiConfig_mcl.py
+-w /Stitchifwi_components_mtl -p mtlp -d 0xAA00001F
+
    +
    +
    +

    Note

    +

    StitchLoader.py script works only if Boot Guard in the base image is not enabled, and the silicon is not fused with Boot Guard enabled. +If Boot Guard is enabled, please use StitchIfwi.py script instead.

    +
    +
    +
    +

    Slimbootloader binary for capsule

    +

    The Slimbootloader.bin image generated from the build steps above can be used to create a capsule image. +Please refer to Build Tool on generating SBL image.

    +

    For all Meteor Lake platforms, the below command can be used:

    +
    python ./BootloaderCorePkg/Tools/GenCapsuleFirmware.py -p BIOS Outputs/<plat>/SlimBootloader.bin -k <Keys> -o FwuImage.bin
+
    +
    +

    For more details on generating capsule image, please refer Generating capsule.

    +
    +
    +

    Triggering Firmware Update

    +

    Please refer to Firmware Update on how to trigger firmware update flow. +Below is an example:

    +

    To trigger firmware update in SBL shell:

    +
      +

    1. Copy FwuImage.bin into root directory on FAT partition of a USB key

      2. +

    2. Boot and press any key to enter SBL shell

      3. +

    3. Type command fwupdate from shell

      +

      Observe SBL resets the platform and performs update flow. It resets multiple times to complete the update process.

      +
      4. +
    +
    +
    +

    Flashing

    +

    Flash the generated SBL_IFWI_IMAGE_NAME to the target board using a DediProg SF600 programmer.

    +
    +

    Note

    +

    Refer the table above to identify the connector on the target board for SPI flash programmer. When using such device, please ensure:

    +
      +

    1. The alignment/polarity when connecting Dediprog to the board.

      2. +

    2. The power to the board is turned off while the programmer is connected (even when not in use).

      3. +

    3. The programmer is set to update the flash from offset 0x0.

      4. +
    +
    +

    Good Luck!

    +
    +
    + + +
    +
    + +
    +
    +
    +
    + + + + \ No newline at end of file diff --git a/supported-hardware/upxtremei12rplp.html b/supported-hardware/upxtremei12rplp.html new file mode 100644 index 0000000..a266ab3 --- /dev/null +++ b/supported-hardware/upxtremei12rplp.html @@ -0,0 +1,280 @@ + + + + + + + UP Xtreme i12 13th Board — Slim Bootloader 1.0 documentation + + + + + + + + + + + + + + + + + + + + + + +
    + + +
    + +
    +
    +
    + +
    +
    +
    +
    + +
    +

    UP Xtreme i12 13th Board

    +

    The UP Xtreme i12 13th board (UP Xtreme i12 13th) is an x86 maker board based on Intel platform Raptor Lake-P. The UP boards are used in IoT, industrial automation, digital signage areas, etc.

    +
    +

    Prerequisites

    +

    SBL supports UP Xtreme i12 13th maker board. To start developing SBL, the following equipment, software and environments are required:

    + +
    +
    +

    Board Setup

    +|UPX12RPLP| Board Setup + +
    +
    +

    Before You Start

    +
    +

    Warning

    +

    As you plan to reprogram the SPI flash, it’s a good idea to backup the pre-installed BIOS image first.

    +
    +

    Boot the board and enter BIOS setup menu to get familiar with the board features and settings.

    +

    Early boot serial debug console can be reached via UART1 located on CN9 header on the UP Xtreme i12 13th board. Make sure you can observe serial output message running the factory BIOS first.

    +
    +

    Note

    +

    To make your own UART debug adapter by direct wiring, refer to CN9 Header Pinout for UART1:

    + + + + + + + + + + + + + + + +

    Pin

    Signal

    8

    GND

    9

    UART_RX

    10

    UART_TX

    +
    +
    +
    +

    Building

    +

    UP Xtreme i12 13th board is based on Intel Raptor Lake-P. To build:

    +
    python BuildLoader.py build rplp
+
    +
    +

    The output images are generated under Outputs directory.

    +
    +
    +

    Stitching

    +

    Stitch SBL images with factory BIOS image using the stitch tool:

    +
    python Platform/AlderlakeBoardPkg/Script/StitchLoader.py -i <BIOS_IMAGE_NAME> -s Outputs/rplp/SlimBootloader.bin -o <SBL_IFWI_IMAGE_NAME> -p 0xAA000114
+
+<BIOS_IMAGE>     : Input file. Factory BIOS extracted from UP Xtreme i12 13th board.
+<SBL_IFWI_IMAGE> : Output file. New IFWI image with SBL in BIOS region.
+-p <value>       : 4-byte platform data for platform ID (e.g. 14) and debug UART port index (e.g. 01).
+
    +
    +
    +

    Note

    +

    StitchLoader.py script works only if Boot Guard in the base image is not enabled, and the silicon is not fused with Boot Guard enabled. +If Boot Guard is enabled, please use StitchIfwi.py script instead.

    +
    +

    See Stitch Tool on how to stitch the IFWI image with SBL.

    +
    +
    +

    Slimbootloader binary for capsule

    +

    A capsule image could ecapsulate a Slimbootloader image to be used in firmware update mechanism. More information is described in Firmware Update.

    +

    For the process running properly, an IFWI image programmed on board with TOP SWAP size configuration is required.

    +
    +

    Note

    +

    Enabling TOP SWAP size configuration requires additional firmware components and tools.

    +
    +

    Creating Slimbootloader binary for capsule image requires the following steps:

    +

    Build SBL for UP Xtreme i12 13th:

    +
    python BuildLoader.py build rplp
+
    +
    +

    Edit the 4-byte platform data in Slimbootloader image by Hexedit or equivalent hexdecimal editor.

    +

    Go to top of TOP SWAP A at address 0xCFFFF4, edit 14 01 00 AA as below

    +
    00CFFFF0   90 90 EB B9  14 01 00 AA  A4 50 FF FF  00 50 FF FF  ................
+
    +
    +

    Go to top of TOP SWAP B at address 0xC7FFF4, edit 14 01 00 AA as below

    +
    00C7FFF0   90 90 EB B9  14 01 00 AA  A4 50 FF FF  00 50 FF FF  ................
+
    +
    +

    For more details on TOP SWAP regions, please refer Flash Layout

    +

    Generate capsule update image FwuImage.bin:

    +
    python BootloaderCorePkg/Tools/GenCapsuleFirmware.py -p BIOS Outputs/rplp/SlimBootloader.bin -k KEY_ID_FIRMWAREUPDATE_RSA3072 -o FwuImage.bin
+
    +
    +

    For more details on generating capsule image, please refer Generating capsule.

    +
    +
    +

    Triggering Firmware Update

    +

    Please refer to Firmware Update on how to trigger firmware update flow. +Below is an example:

    +

    To trigger firmware update in SBL shell:

    +
      +

    1. Copy FwuImage.bin into root directory on FAT partition of a USB key

      2. +

    2. Boot and press any key to enter SBL shell

      3. +

    3. Type command fwupdate from shell

      +

      Observe SBL resets the platform and performs update flow. It resets multiple times to complete the update process.

      +
      4. +
    +
    +
    +

    Flashing

    +

    Flash the IFWI image to UP Xtreme i12 13th board using a SPI programmer. Header CN19 on the board should be used, see instructions for additional details.

    +

    Good Luck!

    +
    +
    + + +
    +
    + +
    +
    +
    +
    + + + + \ No newline at end of file