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Christophe Lombard
8baea29fde
Configure early PAU Global MMIO BAR registers to allow PAU MMIO register accesses. This is done for each PAU. Enable the Powerbus interface is mandatory for MMIO accesses. For each OpenCAPI device, configure the bar registers to access to the AFU MMIO and to the AFU Config Addr/Data registers. AFU Config/Data registers = GENID_ADDR (from phy_map file) + 320K (= 0x50000) Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
71 lines
1.2 KiB
C
71 lines
1.2 KiB
C
// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
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/* Copyright 2017-2019 IBM Corp. */
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#ifndef __PHYS_MAP_H
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#define __PHYS_MAP_H
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#include <compiler.h>
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#include <stdint.h>
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#include <processor.h>
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#include <ccan/endian/endian.h>
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#include <chip.h>
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enum phys_map_type {
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NULL_MAP,
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SYSTEM_MEM,
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GPU_MEM_4T_DOWN,
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GPU_MEM_4T_UP,
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OCAPI_MEM,
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PHB4_64BIT_MMIO,
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PHB4_32BIT_MMIO,
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PHB4_XIVE_ESB,
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PHB4_REG_SPC,
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PHB5_64BIT_MMIO,
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PHB5_32BIT_MMIO,
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PHB5_XIVE_ESB,
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PHB5_REG_SPC,
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NPU_OCAPI_MMIO,
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XIVE_VC,
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XIVE_PC,
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VAS_USER_WIN,
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VAS_HYP_WIN,
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OCAB_XIVE_ESB,
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LPC_BUS,
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FSP_MMIO,
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NPU_REGS,
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NPU_USR,
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NPU_PHY,
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NPU_NTL,
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NPU_GENID,
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PSIHB_REG,
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XIVE_IC,
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XIVE_TM,
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PSIHB_ESB,
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NX_RNG,
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CENTAUR_SCOM,
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MC_OCMB_CFG,
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MC_OCMB_MMIO,
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XSCOM,
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RESV,
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XIVE_NVC,
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XIVE_NVPG,
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XIVE_ESB,
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XIVE_END,
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PAU_OCAPI_MMIO,
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PAU_REGS,
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PAU_GENID,
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PAU_NTL,
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};
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extern void phys_map_get(uint64_t gcid, enum phys_map_type type,
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int index, uint64_t *addr, uint64_t *size);
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extern void __phys_map_get(uint64_t topology_idx, uint64_t gcid,
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enum phys_map_type type, int index, uint64_t *addr, uint64_t *size);
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extern void phys_map_init(unsigned long pvr);
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#endif /* __PHYS_MAP_H */
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//TODO self test overlaps and alignemnt and size.
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