mirror of
https://github.com/Dasharo/skiboot.git
synced 2026-03-06 14:50:44 -08:00
Stewart Smith
49496485fe
SPDX makes it a simpler diff. I have audited the commit history of each file to ensure that they are exclusively authored by IBM and thus we have the right to relicense. The motivation behind this is twofold: 1) We want to enable experiments with coreboot, which is GPLv2 licensed 2) An upcoming firmware component wants to incorporate code from skiboot and code from the Linux kernel, which is GPLv2 licensed. I have gone through the IBM internal way of gaining approval for this. The following files are not exclusively authored by IBM, so are *not* included in this update (I will be seeking approval from contributors): core/direct-controls.c core/flash.c core/pcie-slot.c external/common/arch_flash_unknown.c external/common/rules.mk external/gard/Makefile external/gard/rules.mk external/opal-prd/Makefile external/pflash/Makefile external/xscom-utils/Makefile hdata/vpd.c hw/dts.c hw/ipmi/ipmi-watchdog.c hw/phb4.c include/cpu.h include/phb4.h include/platform.h libflash/libffs.c libstb/mbedtls/sha512.c libstb/mbedtls/sha512.h platforms/astbmc/barreleye.c platforms/astbmc/garrison.c platforms/astbmc/mihawk.c platforms/astbmc/nicole.c platforms/astbmc/p8dnu.c platforms/astbmc/p8dtu.c platforms/astbmc/p9dsu.c platforms/astbmc/vesnin.c platforms/rhesus/ec/config.h platforms/rhesus/ec/gpio.h platforms/rhesus/gpio.c platforms/rhesus/rhesus.c platforms/astbmc/talos.c platforms/astbmc/romulus.c Signed-off-by: Stewart Smith <stewart@linux.ibm.com> [oliver: fixed up the drift] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
99 lines
2.3 KiB
C
99 lines
2.3 KiB
C
// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
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/* Copyright 2013-2019 IBM Corp. */
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#ifndef __CAPP_H
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#define __CAPP_H
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/*
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* eyecatcher PHB3: 'CAPPLIDH' in ASCII
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* eyecatcher PHB4: 'CAPPLIDH' in ASCII
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*/
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struct capp_lid_hdr {
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be64 eyecatcher;
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be64 version;
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be64 lid_no;
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be64 pad;
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be64 ucode_offset;
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be64 total_size;
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};
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struct capp_ucode_data_hdr {
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be64 eyecatcher; /* 'CAPPUCOD' in ASCII */
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u8 version;
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u8 reg;
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u8 reserved[2];
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be32 chunk_count; /* Num of 8-byte chunks that follow */
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};
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struct capp_ucode_data {
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struct capp_ucode_data_hdr hdr;
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be64 data[];
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};
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struct capp_ucode_lid {
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be64 eyecatcher; /* 'CAPPULID' in ASCII */
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be64 version;
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be64 data_size; /* Total size of all capp microcode data */
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u8 reserved[40];
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struct capp_ucode_data data; /* This repeats */
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};
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enum capp_reg {
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apc_master_cresp = 0x1,
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apc_master_uop_table = 0x2,
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snp_ttype = 0x3,
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snp_uop_table = 0x4,
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apt_master_capi_ctrl = 0x5,
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snoop_capi_cnfg = 0x6,
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canned_presp_map0 = 0x7,
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canned_presp_map1 = 0x8,
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canned_presp_map2 = 0x9,
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flush_sue_state_map = 0xA,
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apc_master_powerbus_ctrl = 0xB
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};
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struct capp_info {
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unsigned int capp_index;
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unsigned int phb_index;
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uint64_t capp_fir_reg;
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uint64_t capp_fir_mask_reg;
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uint64_t capp_fir_action0_reg;
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uint64_t capp_fir_action1_reg;
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uint64_t capp_err_status_ctrl_reg;
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};
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struct capp_ops {
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int64_t (*get_capp_info)(int, struct phb *, struct capp_info *);
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};
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struct capp {
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struct phb *phb;
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unsigned int capp_index;
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uint64_t capp_xscom_offset;
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uint64_t attached_pe;
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uint64_t chip_id;
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};
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struct proc_chip;
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extern struct lock capi_lock;
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extern struct capp_ops capi_ops;
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extern bool capp_ucode_loaded(struct proc_chip *chip, unsigned int index);
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extern int64_t capp_load_ucode(unsigned int chip_id, uint32_t opal_id,
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unsigned int index, u64 lid_eyecatcher,
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uint32_t reg_offset,
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uint64_t apc_master_addr,
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uint64_t apc_master_write,
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uint64_t snp_array_addr,
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uint64_t snp_array_write);
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extern int64_t capp_get_info(int chip_id, struct phb *phb,
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struct capp_info *info);
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/* Helpers to read/write capp registers */
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extern int64_t capp_xscom_read(struct capp *capp, int64_t off, uint64_t *val);
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extern int64_t capp_xscom_write(struct capp *capp, int64_t off, uint64_t val);
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#endif /* __CAPP_H */
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