mirror of
https://github.com/Dasharo/skiboot.git
synced 2026-03-06 14:50:44 -08:00
Stewart Smith
49496485fe
SPDX makes it a simpler diff. I have audited the commit history of each file to ensure that they are exclusively authored by IBM and thus we have the right to relicense. The motivation behind this is twofold: 1) We want to enable experiments with coreboot, which is GPLv2 licensed 2) An upcoming firmware component wants to incorporate code from skiboot and code from the Linux kernel, which is GPLv2 licensed. I have gone through the IBM internal way of gaining approval for this. The following files are not exclusively authored by IBM, so are *not* included in this update (I will be seeking approval from contributors): core/direct-controls.c core/flash.c core/pcie-slot.c external/common/arch_flash_unknown.c external/common/rules.mk external/gard/Makefile external/gard/rules.mk external/opal-prd/Makefile external/pflash/Makefile external/xscom-utils/Makefile hdata/vpd.c hw/dts.c hw/ipmi/ipmi-watchdog.c hw/phb4.c include/cpu.h include/phb4.h include/platform.h libflash/libffs.c libstb/mbedtls/sha512.c libstb/mbedtls/sha512.h platforms/astbmc/barreleye.c platforms/astbmc/garrison.c platforms/astbmc/mihawk.c platforms/astbmc/nicole.c platforms/astbmc/p8dnu.c platforms/astbmc/p8dtu.c platforms/astbmc/p9dsu.c platforms/astbmc/vesnin.c platforms/rhesus/ec/config.h platforms/rhesus/ec/gpio.h platforms/rhesus/gpio.c platforms/rhesus/rhesus.c platforms/astbmc/talos.c platforms/astbmc/romulus.c Signed-off-by: Stewart Smith <stewart@linux.ibm.com> [oliver: fixed up the drift] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
109 lines
2.9 KiB
C
109 lines
2.9 KiB
C
// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
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/* Copyright 2013-2019 IBM Corp. */
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#ifndef __AST_H
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#define __AST_H
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/*
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* AHB bus registers
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*/
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/* SPI Flash controller #1 (BMC) */
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#define BMC_SPI_FCTL_BASE 0x1E620000
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#define BMC_SPI_FCTL_CE_CTRL (BMC_SPI_FCTL_BASE + 0x04)
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#define BMC_SPI_FCTL_CTRL (BMC_SPI_FCTL_BASE + 0x10)
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#define BMC_SPI_FREAD_TIMING (BMC_SPI_FCTL_BASE + 0x94)
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#define BMC_FLASH_BASE 0x20000000
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/* SPI Flash controller #2 (PNOR) */
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#define PNOR_SPI_FCTL_BASE 0x1E630000
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#define PNOR_SPI_FCTL_CONF (PNOR_SPI_FCTL_BASE + 0x00)
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#define PNOR_SPI_FCTL_CTRL (PNOR_SPI_FCTL_BASE + 0x04)
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#define PNOR_SPI_FREAD_TIMING (PNOR_SPI_FCTL_BASE + 0x14)
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#define PNOR_FLASH_BASE 0x30000000
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/* LPC registers */
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#define LPC_BASE 0x1e789000
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#define LPC_HICR6 (LPC_BASE + 0x80)
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#define LPC_HICR7 (LPC_BASE + 0x88)
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#define LPC_HICR8 (LPC_BASE + 0x8c)
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#define LPC_HICRB (LPC_BASE + 0x100)
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#define LPC_HICRB_ILPC_DISABLE (1 << 6)
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#define LPC_iBTCR0 (LPC_BASE + 0x140)
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/* VUART1 */
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#define VUART1_BASE 0x1e787000
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#define VUART1_GCTRLA (VUART1_BASE + 0x20)
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#define VUART1_GCTRLB (VUART1_BASE + 0x24)
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#define VUART1_ADDRL (VUART1_BASE + 0x28)
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#define VUART1_ADDRH (VUART1_BASE + 0x2c)
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/* SCU registers */
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#define SCU_BASE 0x1e6e2000
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#define SCU_HW_STRAPPING (SCU_BASE + 0x70)
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#define SCU_STRAP_SIO_DECODE_DISABLE (1 << 20)
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#define SCU_REVISION_ID (SCU_BASE + 0x7C)
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#define SCU_REVISION_SOC_FAMILY(x) (((x) >> 24) & 0xff)
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#define SCU_REVISION_SOC_FAMILY_2400 0x02
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#define SCU_REVISION_SOC_FAMILY_2500 0x04
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#define SCU_REVISION_HW_REVISION_ID(x) (((x) >> 16) & 0xff)
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#define SCU_REVISION_CHIP_BONDING(x) (((x) >> 8) & 0x3)
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/* MCR registers */
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#define MCR_BASE 0x1e6e0000
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#define MCR_CONFIGURATION (MCR_BASE + 0x04)
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#define MCR_SCU_MPLL (MCR_BASE + 0x120)
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#define MCR_SCU_STRAP (MCR_BASE + 0x170)
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/*
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* AHB Accessors
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*/
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#ifndef __SKIBOOT__
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#include "io.h"
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#else
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/*
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* Register accessors, return byteswapped values
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* (IE. LE registers)
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*/
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void ast_ahb_writel(uint32_t val, uint32_t reg);
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uint32_t ast_ahb_readl(uint32_t reg);
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bool ast_sio_is_enabled(void);
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bool ast_sio_init(void);
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bool ast_io_init(void);
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bool ast_io_is_rw(void);
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bool ast_lpc_fw_maps_flash(void);
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bool ast_lpc_fw_ipmi_hiomap(void);
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bool ast_lpc_fw_mbox_hiomap(void);
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bool ast_scratch_reg_is_mbox(void);
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/* UART configuration */
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bool ast_is_vuart1_enabled(void);
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void ast_setup_vuart1(uint16_t io_base, uint8_t irq);
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void ast_setup_sio_uart1(uint16_t io_base, uint8_t irq);
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void ast_disable_sio_uart1(void);
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/* BT configuration */
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void ast_setup_ibt(uint16_t io_base, uint8_t irq);
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/* MBOX configuration */
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void ast_setup_sio_mbox(uint16_t io_base, uint8_t irq);
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#endif /* __SKIBOOT__ */
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/*
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* SPI Flash controllers
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*/
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#define AST_SF_TYPE_PNOR 0
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#define AST_SF_TYPE_BMC 1
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#define AST_SF_TYPE_MEM 2
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struct spi_flash_ctrl;
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int ast_sf_open(uint8_t type, struct spi_flash_ctrl **ctrl);
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void ast_sf_close(struct spi_flash_ctrl *ctrl);
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#endif /* __AST_H */
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