mirror of
https://github.com/Dasharo/skiboot.git
synced 2026-03-06 14:50:44 -08:00
Nicholas Piggin
9b85f7d961
This adds ibm,mmu-pid-bits and a new ibm,mmu-lpid-bits to POWER10 CPUs. POWER9 Linux has some workarounds for processors bugs that means it's probably safer to not add the entries there. Linux already hard codes these values correctly on these processors, but this allows more flexibility to change things. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
358 lines
12 KiB
C
358 lines
12 KiB
C
// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
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/* Copyright 2013-2019 IBM Corp. */
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#include <skiboot.h>
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#include "spira.h"
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#include <cpu.h>
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#include <ccan/str/str.h>
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#include <device.h>
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#include "hdata.h"
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struct dt_node * add_core_common(struct dt_node *cpus,
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const struct sppcia_cpu_cache *cache,
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const struct sppcia_cpu_timebase *tb,
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uint32_t int_server, bool okay)
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{
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const char *name;
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struct dt_node *cpu;
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uint32_t version;
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uint64_t freq;
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const uint8_t pa_features_p8[] = {
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24, 0,
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0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xd0, 0x80, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
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};
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const uint8_t pa_features_p9n_dd20[] = {
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64, 0,
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0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xd0, 0x80, 0x00, /* 0 .. 7 */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 8 .. 15 */
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0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 16 .. 23 */
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0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 24 .. 31 */
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0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, /* 32 .. 39 */
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0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 40 .. 47 */
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0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 .. 55 */
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0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 56 .. 63 */
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};
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const uint8_t pa_features_p9[] = {
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64, 0,
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0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xd0, 0x80, 0x00, /* 0 .. 7 */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 8 .. 15 */
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0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 16 .. 23 */
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0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 24 .. 31 */
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0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, /* 32 .. 39 */
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0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 40 .. 47 */
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0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 .. 55 */
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0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 56 .. 63 */
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};
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const uint8_t pa_features_p10[] = {
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66, 0,
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0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xd0, 0x80, 0x00, /* 0 .. 7 */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 8 .. 15 */
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0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 16 .. 23 */
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0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 24 .. 31 */
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0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, /* 32 .. 39 */
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0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 40 .. 47 */
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0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 .. 55 */
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0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 56 .. 63 */
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0x80, 0x00, /* 64 .. 65 */
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};
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const uint8_t *pa_features;
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size_t pa_features_size;
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prlog(PR_INFO, " Cache: I=%u D=%u/%u/%u/%u\n",
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be32_to_cpu(cache->icache_size_kb),
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be32_to_cpu(cache->l1_dcache_size_kb),
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be32_to_cpu(cache->l2_dcache_size_kb),
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be32_to_cpu(cache->l3_dcache_size_kb),
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be32_to_cpu(cache->l35_dcache_size_kb));
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/* Use the boot CPU PVR to make up a CPU name in the device-tree
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* since the HDAT doesn't seem to tell....
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*/
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version = mfspr(SPR_PVR);
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switch(PVR_TYPE(version)) {
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case PVR_TYPE_P8E:
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case PVR_TYPE_P8:
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case PVR_TYPE_P8NVL:
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name = "PowerPC,POWER8";
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pa_features = pa_features_p8;
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pa_features_size = sizeof(pa_features_p8);
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break;
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case PVR_TYPE_P9:
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case PVR_TYPE_P9P:
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name = "PowerPC,POWER9";
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if (is_power9n(version) &&
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(PVR_VERS_MAJ(version) == 2) &&
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(PVR_VERS_MIN(version) == 0)) {
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/* P9N DD2.0 */
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pa_features = pa_features_p9n_dd20;
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pa_features_size = sizeof(pa_features_p9n_dd20);
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} else {
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pa_features = pa_features_p9;
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pa_features_size = sizeof(pa_features_p9);
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}
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break;
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case PVR_TYPE_P10:
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name = "PowerPC,POWER10";
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pa_features = pa_features_p10;
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pa_features_size = sizeof(pa_features_p10);
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break;
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default:
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name = "PowerPC,Unknown";
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pa_features = NULL;
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}
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cpu = dt_new_addr(cpus, name, int_server);
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assert(cpu);
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dt_add_property_string(cpu, "device_type", "cpu");
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dt_add_property_string(cpu, "status", okay ? "okay" : "bad");
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dt_add_property_cells(cpu, "reg", int_server);
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dt_add_property_cells(cpu, "cpu-version", version);
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dt_add_property(cpu, "64-bit", NULL, 0);
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dt_add_property(cpu, "32-64-bridge", NULL, 0);
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dt_add_property(cpu, "graphics", NULL, 0);
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dt_add_property(cpu, "general-purpose", NULL, 0);
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dt_add_property_cells(cpu, "ibm,processor-segment-sizes",
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0x1c, 0x28, 0xffffffff, 0xffffffff);
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dt_add_property_cells(cpu, "ibm,processor-page-sizes",
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0xc, 0x10, 0x18, 0x22);
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if (proc_gen >= proc_gen_p9)
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dt_add_property_cells(cpu, "ibm,processor-radix-AP-encodings",
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0x0000000c, 0xa0000010, 0x20000015, 0x4000001e);
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if (proc_gen >= proc_gen_p10) {
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dt_add_property_cells(cpu, "ibm,mmu-pid-bits", 20);
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dt_add_property_cells(cpu, "ibm,mmu-lpid-bits", 12);
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}
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/* HPT segment page size encodings, common to all supported CPUs */
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dt_add_property_cells(cpu, "ibm,segment-page-sizes",
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0x0c, 0x000, 3, 0x0c, 0x0000, /* 4K seg 4k pages */
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0x10, 0x0007, /* 4K seg 64k pages */
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0x18, 0x0038, /* 4K seg 16M pages */
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0x10, 0x110, 2, 0x10, 0x0001, /* 64K seg 64k pages */
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0x18, 0x0008, /* 64K seg 16M pages */
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0x18, 0x100, 1, 0x18, 0x0000, /* 16M seg 16M pages */
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0x22, 0x120, 1, 0x22, 0x0003); /* 16G seg 16G pages */
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if (pa_features) {
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dt_add_property(cpu, "ibm,pa-features",
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pa_features, pa_features_size);
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}
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dt_add_property_cells(cpu, "ibm,slb-size", 0x20);
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dt_add_property_cells(cpu, "ibm,vmx", 0x2);
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dt_add_property_cells(cpu, "ibm,dfp", 0x2);
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dt_add_property_cells(cpu, "ibm,purr", 0x1);
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dt_add_property_cells(cpu, "ibm,spurr", 0x1);
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/*
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* Do not create "clock-frequency" if the frequency doesn't
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* fit in a single cell
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*/
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freq = ((uint64_t)be32_to_cpu(tb->actual_clock_speed)) * 1000000ul;
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if (freq <= 0xfffffffful)
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dt_add_property_cells(cpu, "clock-frequency", freq);
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dt_add_property_u64(cpu, "ibm,extended-clock-frequency", freq);
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/* FIXME: Hardcoding is bad. */
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dt_add_property_cells(cpu, "timebase-frequency", 512000000);
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dt_add_property_cells(cpu, "ibm,extended-timebase-frequency",
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0, 512000000);
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dt_add_property_cells(cpu, "reservation-granule-size",
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be32_to_cpu(cache->reservation_size));
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dt_add_property_cells(cpu, "d-tlb-size",
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be32_to_cpu(cache->dtlb_entries));
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dt_add_property_cells(cpu, "i-tlb-size",
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be32_to_cpu(cache->itlb_entries));
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/* Assume unified TLB */
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dt_add_property_cells(cpu, "tlb-size",
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be32_to_cpu(cache->dtlb_entries));
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dt_add_property_cells(cpu, "d-tlb-sets",
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be32_to_cpu(cache->dtlb_assoc_sets));
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dt_add_property_cells(cpu, "i-tlb-sets",
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be32_to_cpu(cache->itlb_assoc_sets));
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dt_add_property_cells(cpu, "tlb-sets",
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be32_to_cpu(cache->dtlb_assoc_sets));
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dt_add_property_cells(cpu, "d-cache-block-size",
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be32_to_cpu(cache->dcache_block_size));
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dt_add_property_cells(cpu, "i-cache-block-size",
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be32_to_cpu(cache->icache_block_size));
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dt_add_property_cells(cpu, "d-cache-size",
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be32_to_cpu(cache->l1_dcache_size_kb)*1024);
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dt_add_property_cells(cpu, "i-cache-size",
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be32_to_cpu(cache->icache_size_kb)*1024);
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dt_add_property_cells(cpu, "i-cache-sets",
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be32_to_cpu(cache->icache_assoc_sets));
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dt_add_property_cells(cpu, "d-cache-sets",
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be32_to_cpu(cache->dcache_assoc_sets));
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if (cache->icache_line_size != cache->icache_block_size)
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dt_add_property_cells(cpu, "i-cache-line-size",
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be32_to_cpu(cache->icache_line_size));
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if (cache->l1_dcache_line_size != cache->dcache_block_size)
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dt_add_property_cells(cpu, "d-cache-line-size",
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be32_to_cpu(cache->l1_dcache_line_size));
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return cpu;
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}
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void add_core_attr(struct dt_node *cpu, uint32_t attr)
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{
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if (attr & CPU_ATTR_UNIFIED_PL1)
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dt_add_property(cpu, "cache-unified", NULL, 0);
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if (attr & CPU_ATTR_SPLIT_TLB)
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dt_add_property(cpu, "tlb-split", NULL, 0);
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if (attr & CPU_ATTR_TLBIA)
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dt_add_property(cpu, "tlbia", NULL, 0);
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if (attr & CPU_ATTR_PERF_MONITOR)
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dt_add_property_cells(cpu, "performance-monitor", 0, 1);
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if (attr & CPU_ATTR_EXTERN_CONT)
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dt_add_property(cpu, "external-control", NULL, 0);
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}
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static struct dt_node *create_cache_node(struct dt_node *cpus,
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const struct sppcia_cpu_cache *cache,
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const char *name, uint32_t unit_addr,
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int okay)
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{
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struct dt_node *node;
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node = dt_new_addr(cpus, name, unit_addr);
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assert(node);
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dt_add_property_string(node, "device_type", "cache");
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dt_add_property_cells(node, "reg", unit_addr);
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dt_add_property_string(node, "status", okay ? "okay" : "bad");
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dt_add_property(node, "cache-unified", NULL, 0);
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/* Assume cache associavitity sets is same for L2, L3 and L3.5 */
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dt_add_property_cells(node, "d-cache-sets",
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be32_to_cpu(cache->l2_cache_assoc_sets));
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dt_add_property_cells(node, "i-cache-sets",
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be32_to_cpu(cache->l2_cache_assoc_sets));
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return node;
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}
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static struct dt_node *l35_cache_node(struct dt_node *cpus,
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const struct sppcia_cpu_cache *cache,
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uint32_t unit_addr, int okay)
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{
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struct dt_node *node;
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node = create_cache_node(cpus, cache, "l35-cache", unit_addr, okay);
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dt_add_property_cells(node, "d-cache-size",
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be32_to_cpu(cache->l35_dcache_size_kb) * 1024);
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dt_add_property_cells(node, "i-cache-size",
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be32_to_cpu(cache->l35_dcache_size_kb) * 1024);
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if (cache->icache_line_size != cache->icache_block_size)
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dt_add_property_cells(node, "i-cache-line-size",
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be32_to_cpu(cache->icache_line_size));
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if (cache->l35_cache_line_size != cache->dcache_block_size)
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dt_add_property_cells(node, "d-cache-line-size",
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be32_to_cpu(cache->l35_cache_line_size));
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return node;
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}
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static struct dt_node *l3_cache_node(struct dt_node *cpus,
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const struct sppcia_cpu_cache *cache,
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uint32_t unit_addr, int okay)
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{
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struct dt_node *node;
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node = create_cache_node(cpus, cache, "l3-cache", unit_addr, okay);
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dt_add_property_cells(node, "d-cache-size",
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be32_to_cpu(cache->l3_dcache_size_kb) * 1024);
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dt_add_property_cells(node, "i-cache-size",
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be32_to_cpu(cache->l3_dcache_size_kb) * 1024);
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if (cache->icache_line_size != cache->icache_block_size)
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dt_add_property_cells(node, "i-cache-line-size",
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be32_to_cpu(cache->icache_line_size));
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if (cache->l3_line_size != cache->dcache_block_size)
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dt_add_property_cells(node, "d-cache-line-size",
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be32_to_cpu(cache->l3_line_size));
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return node;
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}
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static struct dt_node *l2_cache_node(struct dt_node *cpus,
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const struct sppcia_cpu_cache *cache,
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uint32_t unit_addr, int okay)
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{
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struct dt_node *node;
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node = create_cache_node(cpus, cache, "l2-cache", unit_addr, okay);
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dt_add_property_cells(node, "d-cache-size",
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be32_to_cpu(cache->l2_dcache_size_kb) * 1024);
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dt_add_property_cells(node, "i-cache-size",
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be32_to_cpu(cache->l2_dcache_size_kb) * 1024);
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if (cache->icache_line_size != cache->icache_block_size)
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dt_add_property_cells(node, "i-cache-line-size",
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be32_to_cpu(cache->icache_line_size));
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if (cache->l2_line_size != cache->dcache_block_size)
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dt_add_property_cells(node, "d-cache-line-size",
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be32_to_cpu(cache->l2_line_size));
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return node;
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}
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static struct dt_node *find_l2_node(struct dt_node *cpus, u32 unit_addr)
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{
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char name[32];
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snprintf(name, sizeof(name), "l2-cache@%.08x", unit_addr);
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return dt_find_by_name(cpus, name);
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}
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uint32_t add_core_cache_info(struct dt_node *cpus,
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const struct sppcia_cpu_cache *cache,
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uint32_t core_pir, int okay)
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{
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struct dt_node *l2_node, *l3_node, *l35_node;
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uint32_t unit_addr;
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/*
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* On P9 the L2 is shared by pairs of SMT=4 cores. We only want
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* to create a cache node for the first of these so we mask off
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* the low PIR bits to get the unit address of the shared cache.
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*/
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if (proc_gen == proc_gen_p9) {
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core_pir &= ~0x7;
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l2_node = find_l2_node(cpus, 0x20 << 24 | core_pir);
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if (l2_node)
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return l2_node->phandle;
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}
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unit_addr = 0x20 << 24 | core_pir;
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l2_node = l2_cache_node(cpus, cache, unit_addr, okay);
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unit_addr = 0x30 << 24 | core_pir;
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l3_node = l3_cache_node(cpus, cache, unit_addr, okay);
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/* Represents the next level of cache in the memory hierarchy */
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dt_add_property_cells(l2_node, "l2-cache", l3_node->phandle);
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if (be32_to_cpu(cache->l35_dcache_size_kb)) {
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unit_addr = 0x35 << 24 | core_pir;
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l35_node = l35_cache_node(cpus, cache, unit_addr, okay);
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dt_add_property_cells(l3_node, "l2-cache", l35_node->phandle);
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}
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return l2_node->phandle;
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}
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