Resolve : "Missing #interrupt-cells" warning duriing dts(device tree source) compilation
hdata/test/p81-811.spira.dts:1434.37-1442.4: Warning (interrupt_provider): /interrupt-controller@3ffff80030000: Missing #interrupt-cells in interrupt provider
An #interrupt-cells added to both reference dts for testing and source code to generate dtb from hdata.
Signed-off-by: Abhishek Singh Tomar <abhishek@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Resolves : the warray bounds warning during compilation
/build/libc/include/string.h:34:16: warning: '__builtin_memset' offset [0, 2097151] is out of the bounds [0, 0] [-Warray-bounds]
34 | #define memset __builtin_memset
hw/fsp/fsp.c:1855:9: note: in expansion of macro 'memset'
1855 | memset(fsp_tce_table, 0, PSI_TCE_TABLE_SIZE);
use volatile pointer to avoid optimization introduced with gcc-11 on constant
address assignment to pointer.
Signed-off-by: Abhishek Singh Tomar <abhishek@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This adds ibm,mmu-pid-bits and a new ibm,mmu-lpid-bits to POWER10 CPUs.
POWER9 Linux has some workarounds for processors bugs that means it's
probably safer to not add the entries there.
Linux already hard codes these values correctly on these processors, but
this allows more flexibility to change things.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
OpenCapi for P10 is included in the P10 chip. This requires OCAPI capable
PHYs, Datalink Layer Logic and Transaction Layer Logic to be included.
The PHYs are the physical connection to the OCAPI interconnect.
The Datalink Layer provides link training.
The Transaction Layer executes the cache coherent and data movement
commands on the P10 chip.
The PAU provides the Transaction Layer functionality for the OCAPI
link(s) on the P10 chip.
The P10 PAU supports two OCAPI links. Six accelerator units PAUs are
instantiated on the P10 chip for a total of twelve OCAPI links.
This patch adds PAU opencapi structure for supporting OpenCapi5.
hw/pau.c file contains main of PAU management functions.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Denali is P10 system. But FSP interaction (MBOX protocol) is same as ZZ.
Hence add denali platform detection code inside zz.c for now. We can think
of adding separate platform later.
Also enable :
- P10 TCE mapping support
- Detect PHBs
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
HDAT spec added fields to define the equalization settings for PCI
Gen5 link. Format is the same as PCI Gen4, so we just need to add
extra fields in the "ibm,lane-eq" in the device tree.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
This fixes multipchip rainier boot issue.
for Rainer:
chip0: ibm,primary-topology-index = < 0x0>;
chip1: ibm,primary-topology-index = < 0x4>;
chip2: ibm,primary-topology-index = < 0x8>;
chip3: ibm,primary-topology-index = < 0xc>;
for Denali:
node0:
chip0: ibm,primary-topology-index = < 0x0>;
chip1: ibm,primary-topology-index = < 0x1>;
chip2: ibm,primary-topology-index = < 0x2>;
chip3: ibm,primary-topology-index = < 0x3>;
node1:
chip0: ibm,primary-topology-index = < 0x4>;
chip1: ibm,primary-topology-index = < 0x5>;
chip2: ibm,primary-topology-index = < 0x6>;
chip3: ibm,primary-topology-index = < 0x7>;
Note that bmc_create_node() gets called very early in the boot process.
Hence we have to traverse through HDAT ntuple to get right topology index.
May be we can optimize pcid_to_topology_idx() function as its pretty
much duplicate of pcid_to_chip_id(). But for now lets keep it as
separate function.
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Ryan Grimm <grimm@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
`xscom_id` is deprecated in P10. Instead we should use topology ID's
("Primary topology table index") to calculate xscom address. Also
use ("Processor fabric topology id") for "ibm,chip-id" property.
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
VAS SCOM base address and paste address format are changed on P10.
This patch adds ibm,power10-vas-x string to compatible property per
each VAS node. This compatible string is used to define the paste
base address later during VAS initialization.
Also enables NX on P10 without adding any compatible string since
the NX SCOM base address is not changed.
Signed-off-by: Haren Myneni <haren@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
HDAT provides Topology ID table and the primary topology location on
P10. This primary location points to primary topology entry in ID table
which contains the primary topology index and this index is used to
define the paste base address per chip.
This patch reads Topology ID table and the primary topology location
from hdata and retrieves the primary topology index in the ID table.
Make this primaty topology index value available with
ibm,primary-topology-index property per chip. VAS reads this property
to setup paste base address for each chip.
Signed-off-by: Haren Myneni <haren@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Initial P10 support
- LPC : This contains two useful information:
LPC MCTP Memory Window Base Address
Second vUART console details
- Enable memory-buffer mmio
- Fix ipmi sensors
IPMI sensors are deprecated in P10. Hence do not parse ipmi sensors.
- I2C support
- Detect PHB5
- Create p10 xscom, xive, chiptod nodes
- Set pa-features bit for 2nd DAWR
Availability of 2nd DAWR depends on 0th bit of 64th byte of
ibm,pa-features property. Set it for p10.
Co-authored-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Co-authored-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Co-authored-by: Reza Arbab <arbab@linux.ibm.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
Co-authored-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
We've got functions to instantiate I2C buses at various places inside of
the skiboot code base (in hdat, firenze-pci, and in witherspoon). The
HDAT ones are the most generic so re-work those a bit and export the
functions used to add DT nodes for I2C masters and the ports below them.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Looks like HBRT sets top bit in pcbaddress before making OCMB SCOM request.
We have to clear that bit so that we can find proper address range
for SCOM operation.
Sample failure:
[ 2578.156011925,3] OCMB: no matching address range!
[ 2578.156044481,3] scom_read: to 80000028 off: 8006430d4008c000 rc = -26
Also move HRMOR_BIT macro to common include file (hdata/spira.h -> skiboot.h).
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
If we have duplicate xscom nodes then it will fail to attach xscom
node to device tree and we will fail eventully. Better to call assert()
and fail here.
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
This patch reads the hdata bits to check for physical presence
assertion, and creates device tree entries to be consumed later in the
boot.
Signed-off-by: Nayna Jain <nayna@linux.ibm.com>
Signed-off-by: Eric Richter <erichte@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
P9 cores can be configured into fused core mode where two core chiplets
function as an 8-threaded, single core. So, bump four to eight in boot_entry
when in fused core mode and cpu_thread_count in init_boot_cpu.
The HID, AMOR, TSCR, RPR require the first active thread on that core chiplet
to load the copy for that core chiplet. So, send thread 1 of a fused core to
init_shared_sprs in boot_entry.
The code checks for fused core mode in the core thead state register and puts a
field in struct cpu_thread. This flag is checked when updating the HID and in
XIVE code when setting the special bar.
For XSCOM, the core ID is the non-fused EX. So, create macros to arrange the
bits. It's fairly verbose but somewhat readable.
This was tested on a P9 ZZ with 16 fused cores and ran HTX for over 24 hours.
Signed-off-by: Ryan Grimm <grimm@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Older versions of opal-prd (i.e. most of them shipped by distros)
expect the HBRT image to have the PRD label of "ibm,hbrt-code-image".
Commit c3bfa32095 ("hdata: Fix reserved node label search") made
opal-prd check for both strings, but since opal-prd itself is the only
component interested in locating the hbrt-code-image we might as well
just add the prefix in firmware.
Cc: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
add_memory_buffer_mmio() should be exclusive to P9P (AXONE).
Running it on non P9P systems resulted in warnings such as:
MS AREA: Inconsistent MSAREA version 40 for P9P system
So check for PVR and quietly return if not P9P.
Fixes: 38b5c3179 (Add support for memory-buffer mmio)
Cc: skiboot-stable@lists.ozlabs.org
Cc: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Abhishek Singh Tomar
Nicholas Piggin
Christophe Lombard
Vasant Hegde
Frederic Barrat
Haren Myneni
Oliver O'Halloran
Philippe Mathieu-Daudé
Nayna Jain
Ryan Grimm
Klaus Heinrich Kiwi
Thiago Jung Bauermann