mirror of
https://github.com/Dasharo/skiboot.git
synced 2026-03-06 14:50:44 -08:00
fix simple sparse warnings
Should be no real code change, these mostly update type declarations that sparse complains about. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
This commit is contained in:
committed by
Oliver O'Halloran
parent
5178691d0a
commit
e04a34af20
+2
-2
@@ -531,7 +531,7 @@ static int64_t cpu_disable_ME_RI_all(void)
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return OPAL_SUCCESS;
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}
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void *fdt;
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static void *fdt;
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void __noreturn load_and_boot_kernel(bool is_reboot)
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{
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@@ -828,7 +828,7 @@ static void setup_branch_null_catcher(void)
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* ABI v1 (ie. big endian). This will be broken if we ever
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* move to ABI v2 (ie little endian)
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*/
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memcpy_null(0, bn, 16);
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memcpy_null((void *)0, bn, 16);
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}
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#endif
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+1
-1
@@ -1349,7 +1349,7 @@ void pci_std_swizzle_irq_map(struct dt_node *np,
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dt_add_property_cells(np, "interrupt-map-mask",
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0xf800, 0, 0, 7);
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}
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map_size = esize * edevcount * 4 * sizeof(uint32_t);
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map_size = esize * edevcount * 4 * sizeof(u32);
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map = p = zalloc(map_size);
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if (!map) {
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prerror("Failed to allocate interrupt-map-mask !\n");
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+1
-1
@@ -184,7 +184,7 @@ static int generic_start_preload_resource(enum resource_id id, uint32_t subid,
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}
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/* These values will work for a ZZ booted using BML */
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const struct platform_ocapi generic_ocapi = {
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static const struct platform_ocapi generic_ocapi = {
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.i2c_engine = 1,
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.i2c_port = 4,
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.i2c_reset_addr = 0x20,
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+1
-1
@@ -118,7 +118,7 @@ static struct dt_node *get_hb_reserved_memory(const char *label)
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return NULL;
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}
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struct {
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static struct {
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uint32_t type;
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const char *compat;
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} cvc_services[] = {
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+1
-1
@@ -18,7 +18,7 @@
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#define DPO_CMD_SGN_BYTE1 0x20 /* Byte[1] signature */
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#define DPO_TIMEOUT 2700 /* 45 minutes in seconds */
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bool fsp_dpo_pending;
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static bool fsp_dpo_pending;
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static unsigned long fsp_dpo_init_tb;
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/*
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@@ -455,8 +455,8 @@ static void imc_dt_update_nest_node(struct dt_node *dev)
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const struct dt_property *type;
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/* Add the base_addr and chip-id properties for the nest node */
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base_addr = malloc(sizeof(uint64_t) * nr_chip);
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chipids = malloc(sizeof(uint32_t) * nr_chip);
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base_addr = malloc(sizeof(u64) * nr_chip);
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chipids = malloc(sizeof(u32) * nr_chip);
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for_each_chip(chip) {
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base_addr[i] = cpu_to_be64(chip->homer_base);
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chipids[i] = cpu_to_be32(chip->id);
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@@ -494,7 +494,7 @@ static int init_vas_inst(struct dt_node *np, bool enable)
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}
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void vas_init()
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void vas_init(void)
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{
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bool enabled;
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struct dt_node *np;
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+2
-1
@@ -118,7 +118,8 @@ struct dt_property *__dt_add_property_u64s(struct dt_node *node,
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static inline struct dt_property *dt_add_property_u64(struct dt_node *node,
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const char *name, u64 val)
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{
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return dt_add_property_cells(node, name, (u32)(val >> 32), (u32)val);
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return dt_add_property_cells(node, name, (u32)(val >> 32),
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(u32)(val & 0xffffffffUL));
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}
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void dt_del_property(struct dt_node *node, struct dt_property *prop);
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+1
-1
@@ -318,7 +318,7 @@ extern void fake_rtc_init(void);
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struct stack_frame;
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extern void exception_entry(struct stack_frame *stack);
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extern void exception_entry_pm_sreset(void);
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extern void exception_entry_pm_mce(void);
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extern void __noreturn exception_entry_pm_mce(void);
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/* Assembly in head.S */
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extern void disable_machine_check(void);
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+1
-1
@@ -19,7 +19,7 @@
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* Returns the absolute value of the long integer argument
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*/
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long int labs(long int n)
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long int __attribute__((const)) labs(long int n)
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{
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return (n > 0) ? n : -n;
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}
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@@ -503,13 +503,13 @@ void astbmc_exit(void)
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ipmi_wdt_final_reset();
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}
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const struct bmc_sw_config bmc_sw_ami = {
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static const struct bmc_sw_config bmc_sw_ami = {
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.ipmi_oem_partial_add_esel = IPMI_CODE(0x3a, 0xf0),
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.ipmi_oem_pnor_access_status = IPMI_CODE(0x3a, 0x07),
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.ipmi_oem_hiomap_cmd = IPMI_CODE(0x3a, 0x5a),
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};
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const struct bmc_sw_config bmc_sw_openbmc = {
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static const struct bmc_sw_config bmc_sw_openbmc = {
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.ipmi_oem_partial_add_esel = IPMI_CODE(0x3a, 0xf0),
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.ipmi_oem_hiomap_cmd = IPMI_CODE(0x3a, 0x5a),
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};
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@@ -223,7 +223,7 @@ static const struct bmc_sw_config bmc_sw_smc = {
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};
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/* Provided by Eric Chen (SMC) */
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const struct bmc_hw_config p8dtu_bmc_hw = {
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static const struct bmc_hw_config p8dtu_bmc_hw = {
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.scu_revision_id = 0x02010303,
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.mcr_configuration = 0x00000577,
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.mcr_scu_mpll = 0x000050c0,
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@@ -695,7 +695,7 @@ static const struct bmc_sw_config bmc_sw_smc = {
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};
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/* Provided by Eric Chen (SMC) */
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const struct bmc_hw_config p9dsu_bmc_hw = {
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static const struct bmc_hw_config p9dsu_bmc_hw = {
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.scu_revision_id = 0x04030303,
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.mcr_configuration = 0x11000756,
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.mcr_scu_mpll = 0x000071c1,
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@@ -325,7 +325,7 @@ i2c_failed:
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return;
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}
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const struct platform_ocapi witherspoon_ocapi = {
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static const struct platform_ocapi witherspoon_ocapi = {
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.i2c_engine = 1,
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.i2c_port = 4,
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.odl_phy_swap = false,
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@@ -370,8 +370,8 @@ static int gpu_slot_to_num(const char *slot)
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static void npu2_phb_nvlink_dt(struct phb *npuphb)
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{
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struct dt_node *g[3] = { 0 }; /* Current maximum is 3 GPUs per 1 NPU */
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struct dt_node *n[6] = { 0 };
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struct dt_node *g[3] = { NULL }; /* Current maximum 3 GPUs per 1 NPU */
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struct dt_node *n[6] = { NULL };
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int max_gpus, i, gpuid, first, last;
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struct npu2 *npu2_phb = phb_to_npu2_nvlink(npuphb);
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struct pci_device *npd;
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