Florent Kermarrec a6acfb9a37 stream/Buffer: Integrate PipeValid/PipeReady (both configurable) and add tests. ...

Allow selecting pipelining of valid/data or/and ready and creating a full Skid Buffer
(Pipeline of both valid/data and ready).

2022-09-07 08:59:37 +02:00

..

__init__.py

add test directory with test_code_8b10b.py (from misoc)

2017-04-24 18:46:55 +02:00

test_axi_lite.py

test/axi_lite: parametrize address and data width in another test; add another test call with 64b data width

2022-07-20 02:44:57 +02:00

test_axi.py

test/test_axi/test_axi_width_converter: Switch to DUT_ref (To avoid breaking CI).

2022-07-25 12:34:38 +02:00

test_bitbang.py

test: add SPDX License identifier to header and specify file is part of LiteX.

2020-08-23 15:40:21 +02:00

test_clock.py

cores/clocks/lattice_ecp5: Rename ECP5Delay to ECP5DynamicDelay and adapt style for consistency.

2022-01-25 11:09:15 +01:00

test_code_8b10b.py

soc/cores/code_8b10b: add StreamEncoder/Decoder (to be used with LiteX's streams).

2020-10-21 09:29:21 +02:00

test_cpu.py

test/test_cpu: Re-enable cv32e40p/marocchino.

2022-06-29 11:15:48 +02:00

test_csr.py

soc/interconnect/csr: Fix CSRConstant read method (And add test_csr_constant to test_csr).

2022-03-21 15:21:08 +01:00

test_ecc.py

test: add SPDX License identifier to header and specify file is part of LiteX.

2020-08-23 15:40:21 +02:00

test_emif.py

test: add SPDX License identifier to header and specify file is part of LiteX.

2020-08-23 15:40:21 +02:00

test_fifosyncmacro.py

test: FifoSyncMacro: Use F4PGA instead of deprecated Symbiflow

2022-06-17 16:27:25 +02:00

test_gearbox.py

inteconnect/stream: Increase io_lcm size when io_lcm/i_dw or io_lcm/o_dw < 2.

2021-03-18 13:47:10 +01:00

test_hyperbus.py

soc/cores: Re-integrated generic/portable HyperBus/HyperRAM core from LiteHyperBus.

2022-03-01 09:11:55 +01:00

test_i2s.py

test: add SPDX License identifier to header and specify file is part of LiteX.

2020-08-23 15:40:21 +02:00

test_icap.py

cores/icap/ICAP: Add Register read capability.

2021-10-04 17:22:57 +02:00

test_led.py

soc/cores/led: Review/Rework #1265.

2022-04-04 15:24:54 +02:00

test_packet.py

test: Rename new test_packet/stream to test_packet2/stream2 and revert old tests.

2021-10-23 17:40:41 +02:00

test_prbs.py

test: add SPDX License identifier to header and specify file is part of LiteX.

2020-08-23 15:40:21 +02:00

test_spi_opi.py

test: add SPDX License identifier to header and specify file is part of LiteX.

2020-08-23 15:40:21 +02:00

test_spi.py

test: add SPDX License identifier to header and specify file is part of LiteX.

2020-08-23 15:40:21 +02:00

test_stream.py

stream/Buffer: Integrate PipeValid/PipeReady (both configurable) and add tests.

2022-09-07 08:59:37 +02:00

test_timer.py

test/test_timer: Update.

2021-05-27 19:37:51 +02:00

test_wishbone.py

soc/interconnect/wishbone: Cleanup in burst cycles support logic

2022-04-12 15:32:29 +02:00