Sebastien Bourdeauducq f4adb0fe9c examples: remove outdated wb_intercon simulation

2012-03-08 18:17:56 +01:00

..

basic_sim.py

sim: make initialization cycle optional (selectable by function attribute)

2012-03-06 19:43:59 +01:00

corelogic_conv.py

Use meaningful class names

2012-01-20 23:07:32 +01:00

dataflow_dma.py

actorlib/control: 'for' generator

2012-01-15 22:08:33 +01:00

dataflow.py

flow: simplify actor fragment interface

2012-01-10 15:54:51 +01:00

fsm.py

Use double quotes for all strings

2012-02-14 13:12:43 +01:00

lm32_inst.py

fhdl: support forwarding of bidirectional signals from instance ports

2012-02-16 18:34:32 +01:00

memory_sim.py

examples: small cleanup

2012-03-08 15:55:02 +01:00

memory.py

fhdl: support memory read enable

2012-01-27 21:39:23 +01:00

simple_gpio.py

bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY

2012-02-15 18:23:31 +01:00

using_record.py

record: support aligned flattening

2012-01-09 19:16:11 +01:00

wb_initiator.py

bus: generic transaction model

2012-03-08 18:14:06 +01:00