Andrew Dennison
e10643bfd5
yosys: add command line arg to be quiet
2023-06-06 08:51:22 +02:00
Andrew Dennison
4eed62143c
litex_client: remove duplicate read
2023-06-06 08:49:54 +02:00
Andrew Dennison
5e667f17d7
csr: fix field access check
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* Broken in 5dc440e80d
2023-06-06 08:49:32 +02:00
Richard Tucker
88ec1b3f5e
tools: include LITESD in zephyr dts generator
2023-06-06 08:42:49 +02:00
Andrew Dennison
eb67197a46
tools/linux: fix dts warning: missing #address-cells
2023-06-06 08:42:35 +02:00
Andrew Dennison
9b67898e99
tools/linux: add sys_clk to device tree
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* required for using standard devm_clk_get() clock mechanism in linux drivers
2023-06-06 08:41:58 +02:00
Andrew Dennison
200a1a18ee
soc/software: move helpers to hw/common.h
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Fixes warning:
liblitespi/spiflash.c: In function 'spiflash_erase_range':
liblitespi/spiflash.c:202:4: warning: implicit declaration of function 'cdelay' [-Wimplicit-function-declaration]
cdelay(CONFIG_CLOCK_FREQUENCY/25);
^~~~~~
Fixes link failure with spiflash and without liblitedram after commit: 118dd6ed08
2023-06-06 08:41:35 +02:00
Florent Kermarrec
d8ba2e8f65
build/xilinx/vivado: Add project commands to add commands just after project creation.
2023-06-05 14:20:59 +02:00
Florent Kermarrec
a1106b997e
soc/add_spi_sdcard: Fix broken/useless add_module.
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Was already useless before and raise a valid assertion.
2023-06-04 08:19:15 +02:00
enjoy-digital
e5f790f29f
Merge pull request #1699 from bjonnh/fix_lattice_programmer
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Fix frequency specification for ECPDAP on Lattice
2023-05-30 10:41:23 +02:00
Florent Kermarrec
93b45a687f
interconnect/stream/Pipeline: Finalize Pipeline if modules are provided during __init__ (for retro-compatibility).
2023-05-30 08:25:08 +02:00
Jonathan Bisson
eb8e43359d
Fix frequency specification for ECPDAP on Lattice
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It was given as kHz but it takes Hz
2023-05-27 18:59:07 -05:00
Florent Kermarrec
2a27ca18ea
stream/Pipeline: Allow Pipeline to be created dynamically.
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Ex:
self.submodules.pipeline = Pipeline()
self.pipeline.add(m0)
self.pipeline.add(m1)
self.pipeline.add(m3)
2023-05-26 10:17:02 +02:00
enjoy-digital
c6ccb626e8
Merge pull request #1673 from jiegec/vcu128
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Add support for clam shell topology
2023-05-25 22:22:56 +02:00
enjoy-digital
57bffbbb92
Merge pull request #1697 from hansfbaier/master
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AvalonMM/AvalonMM2Wishbone: fix read bursts (readdatavalid one cycle too short)
2023-05-22 19:22:56 +02:00
Hans Baier
6ad14ef644
AvalonMM/AvalonMM2Wishbone: fix read bursts (readdatavalid one cycle too short)
2023-05-22 10:04:38 +07:00
Florent Kermarrec
54192651d8
build/xilinx/ise/add_period_constraint: Add keep parameter.
2023-05-21 09:33:19 +02:00
Florent Kermarrec
f5a9efd8ba
build/add_period_constraint: Fix trellis (thanks bjonnh and zyp) and avoid specific add_period_constraint in libero_soc.
2023-05-21 09:06:20 +02:00
Gwenhael Goavec-Merou
60537fc39f
build/xilinx/yosys_nextpnr: fix f4pga_device for xc7a100 : xc7a35t -> xc7a100t
2023-05-18 12:13:29 +02:00
Florent Kermarrec
9c890a0a27
gen/fhdl/verilog: Simplify/Rename registers initialization parameter.
2023-05-17 17:24:06 +02:00
enjoy-digital
be1d64acaf
Merge pull request #1690 from bunnie/asic-target
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add an option to generate without reg initializers (asic targets)
2023-05-17 16:53:51 +02:00
Florent Kermarrec
fb0c9e846d
build/add_period_constraint: Simplify by using new integrated cases in generic add_period_constraint.
2023-05-17 16:45:45 +02:00
Florent Kermarrec
53a0bc92e4
build/generic_toolchain: Directly handle specific cases with clk None and differential clk.
2023-05-17 16:44:35 +02:00
enjoy-digital
a4eac2d360
Merge pull request #1691 from jersey99/clock-keep-optional
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Clock keep optional for XilinxPlatform
2023-05-17 16:36:47 +02:00
enjoy-digital
5115ec3513
Merge pull request #1692 from zyp/fix_dispatcher_single
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soc/interconnect/packet: Don’t bypass dispatcher with a single slave if it can be deselected.
2023-05-17 16:31:09 +02:00
