Gwenhael Goavec-Merou
1a74854e55
litex_setup: fix software build when liteeth or/and litesata is set (riscv toolchain issue)
2023-07-30 15:37:51 +02:00
Gwenhael Goavec-Merou
64a1ecda6e
litex_setup: explain how to update permanently PATH env variable ( #1589 )
2023-02-08 18:59:46 +01:00
awyxx
fa28d70e62
added powerpc via AUR repository
2023-01-11 23:48:17 +00:00
awyxx
2f2a1e8947
Removed debug print
2023-01-10 21:42:49 +00:00
awyxx
fec8bbe42c
added arch linux support for riscv and openrisc toolchains
2023-01-10 21:41:35 +00:00
Florent Kermarrec
3dee741bac
litex_setup.py: Add --release argument to create a LiteX release with a specific tag.
2023-01-02 09:21:49 +01:00
Florent Kermarrec
dd91c55c36
litex_setup.py: Switch GCC toolchain install to distro install (When available).
2022-11-21 09:17:13 +01:00
Joel Stanley
8b7c569fac
litex_setup: Update Microwatt to latest
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Signed-off-by: Joel Stanley <joel@jms.id.au >
2022-11-21 14:41:01 +10:30
Florent Kermarrec
507ffb72b5
colorer: Avoid duplication and move it to litex/gen.
2022-11-03 09:49:51 +01:00
Joel Stanley
d45d3532fe
microwatt: Update to latest
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Add the new source files and bump the revision used.
Signed-off-by: Joel Stanley <joel@jms.id.au >
2022-10-26 17:03:47 +10:30
Florent Kermarrec
1a90549fa3
interconnect/axi/axi_full: Switch to our own AXI Interconnect (Shared & Crossbar).
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We were not able to simulate verilog_axi interconnect/crossbar correctly since to what
seems to be a simulation mismatch. The code also seems to requires fixing some synthesis
issues with Yosys. When tested with Vivado, the SoC was also miss-behaving (not booting
correctly).
The simulation mismatch issue is logged here: https://github.com/enjoy-digital/litex_verilog_axi_test/issues/1
Since we already had our own AXI-Lite interconnect, creating our AXI interconnect can be
largely based on it with only minor modifications, so switch to it. This also allow simplification
in the interconnect selection/instance.
2022-06-20 19:51:31 +02:00
Florent Kermarrec
b66bd171cc
litex_setup: Use recursive clone for litex_verilog_axi.
2022-06-20 11:23:00 +02:00
Florent Kermarrec
32d1589fb8
litex_setup: Move valentyusb to Misc Cores and also install litex_verilog_axi.
2022-06-20 11:01:47 +02:00
Florent Kermarrec
9b6c9e6630
litex_setup: Switch to specific branch when initializing repositories.
2022-06-20 10:43:30 +02:00
Ben Stobbs
ca97d91424
clone correct valentyusb branch
2022-06-19 12:58:01 +01:00
Ben Stobbs
db3fa1efc7
move valentyusb install to litex_setup.py
2022-06-19 12:51:14 +01:00
Florent Kermarrec
b88bcd8e87
litex_setup: Bump RISC-V GCC toolchain to 10.1.
2022-06-03 14:34:01 +02:00
Florent Kermarrec
ae89c6bfa4
litex_setup: Only include CVA5 with full install.
2022-05-25 15:20:56 +02:00
enjoy-digital
ffcf2fca49
Merge branch 'master' into cva5
2022-05-25 15:18:17 +02:00
Florent Kermarrec
db407b973c
litex_setup: Switch CVA6 to litex-hub and order CPU list per ISA.
2022-05-25 09:29:23 +02:00
enjoy-digital
b033d91738
Merge pull request #1294 from suppamax/cva6
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add cva6 cpu
2022-05-24 19:28:57 +02:00
Tony McDowell
2e9b0331db
litex_setup: fix path reference for python3 binary on non-Linux hosts
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the python binary is stored in the "Program Files" directory. without
delimiting the path the calls to the binary will fail on Windows hosts.
2022-05-19 12:50:50 -06:00
Eric Matthews
5c617d139c
Add initial CVA5 support
2022-05-17 20:19:17 -04:00
Massimiliano Giacometti
48b523cf7e
add cva6 cpu
2022-05-09 21:12:08 +02:00
Florent Kermarrec
36ea82546f
litex_setup: Allow specifying tag for --init --update.
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Allow installing from release tags, ex to install 2022.04 from scratch:
./litex_setup.py --tag=2022.04 --init --install --user.
To update to 2022.04 from a previous installation:
./litex_setup.py --tag=2022.04 --update
To update to latest (dev):
./litex_setup.py --updatelitex_setup: Allow specifying tag for --init --update.
2022-05-04 19:26:22 +02:00
