scripts/Makefile.build and arch/s390/boot/Makefile use the same
command (thin archiving with symbol table creation).
Avoid the code duplication, and move it to scripts/Makefile.lib.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The genksyms source was integrated into the kernel tree in 2003.
I do not expect anybody still using the external /sbin/genksyms.
Kbuild does not need to provide the ability to override GENKSYMS.
Let's remove the GENKSYMS variable, and use the hardcoded path.
Since it occurred in the pre-git era, I attached the commit message
in case somebody is interested in the historical background.
| Author: Kai Germaschewski <kai@tp1.ruhr-uni-bochum.de>
| Date: Wed Feb 19 04:17:28 2003 -0600
|
| kbuild: [PATCH] put genksyms in scripts dir
|
| This puts genksyms into scripts/genksyms/.
|
| genksyms used to be maintained externally, though the only possible user
| was the kernel build. Moving it into the kernel sources makes it easier to
| keep it uptodate, like for example updating it to generate linker scripts
| directly instead of postprocessing the generated header file fragments
| with sed, as we do currently.
|
| Also, genksyms does not handle __typeof__, which needs to be fixed since
| some of the exported symbol in the kernel are defined using __typeof__.
|
| (Rusty Russell/me)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The commands surrounded by ( ) are executed in a subshell, but in
most cases, we do not need to spawn an extra subshell.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
In Kbuild, if_changed and friends must have FORCE as a prerequisite.
Hence, $(filter-out FORCE,$^) or $(filter-out $(PHONY),$^) is a common
idiom to get the names of all the prerequisites except phony targets.
Add real-prereqs as a shorthand.
Note:
We cannot replace $(filter %.o,$^) in cmd_link_multi-m because $^ may
include auto-generated dependencies from the .*.cmd file when a single
object module is changed into a multi object module. Refer to commit
69ea912fda ("kbuild: remove unneeded link_multi_deps"). I added some
comment to avoid accidental breakage.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
The symbol table in the final archive is unneeded; the linker does not
require the symbol table after the --whole-archive option. Every object
file in the archive is included in the link anyway.
Pass thin archives from subdirectories directly to the linker, and
remove the final archiving step.
Fix up the document and comments as well.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Nicholas Piggin <npiggin@gmail.com>
part-of-module and quiet_modtag are set for the same targets.
Define quiet_modtag based on part-of-module.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
All objects in $(obj-m) are contained in $(real-obj-m) as well.
It is true composite objects are only contained in $(obj-m),
but [M] is hard-coded in quiet_cmd_link_multi-m.
This line is redundant.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
In commit 54a702f705 ("kbuild: mark $(targets) as .SECONDARY and
remove .PRECIOUS markers"), I missed one important feature of the
.SECONDARY target:
.SECONDARY with no prerequisites causes all targets to be
treated as secondary.
... which agrees with the policy of Kbuild.
Let's move it to scripts/Kbuild.include, with no prerequisites.
Note:
If an intermediate file is generated by $(call if_changed,...), you
still need to add it to "targets" so its .*.cmd file is included.
The arm/arm64 crypto files are generated by $(call cmd,shipped),
so they do not need to be added to "targets", but need to be added
to "clean-files" so "make clean" can properly clean them away.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
These three cmd_* are invoked in the $(call cmd,*) form.
Now that 'set -e' moved to the 'cmd' macro, they do not need to
explicitly give 'set -e'.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
With the change of rule_cc_o_c / rule_as_o_S in the last commit, each
command is executed in a separate subshell. Rip off unneeded semicolons.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The 'define' ... 'endef' directive is useful to confine a series of
shell commands into a single macro:
define foo
[action1]
[action2]
[action3]
endif
Each action is executed in a separate subshell.
However, rule_cc_o_c and rule_as_o_S in scripts/Makefile.build are
written as follows (with a trailing semicolon in each cmd_*):
define rule_cc_o_c
[action1] ; \
[action2] ; \
[action3] ;
endef
All shell commands are concatenated with '; \' so that it looks like
a single command from the Makefile point of view. This does not
exploit the benefits of 'define' ... 'endef' form because a single
shell command can be more simply written, like this:
rule_cc_o_c = \
[action1] ; \
[action2] ; \
[action3] ;
I guess the intention for the command concatenation was to let the
'@set -e' in if_changed_rule cover all the commands.
We can improve the readability by moving '@set -e' to the 'cmd' macro.
The combo of $(call echo-cmd,*) $(cmd_*) in rule_cc_o_c and rule_as_o_S
have been replaced with $(call cmd,*). The trailing back-slashes have
been removed.
Here is a note about the performance: the commands in rule_cc_o_c and
rule_as_o_S were previously executed all together in a single subshell,
but now each line in a separate subshell. This means Make will spawn
extra subshells [1]. I measured the build performance for
x86_64_defconfig + CONFIG_MODVERSIONS + CONFIG_TRIM_UNUSED_KSYMS
and I saw slight performance regression, but I believe code readability
and maintainability wins.
[1] Precisely, GNU Make may optimize this by executing the command
directly instead of forking a subshell, if no shell special
characters are found in the command line and omitting the subshell
will not change the behavior.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
My main motivation of this commit is to clean up scripts/Kbuild.include
and scripts/Makefile.build.
Currently, CONFIG_TRIM_UNUSED_KSYMS works with a tricky gimmick;
possibly exported symbols are detected by letting $(CPP) replace
EXPORT_SYMBOL* with a special string '=== __KSYM_*===', which is
post-processed by sed, and passed to fixdep. The extra preprocessing
is costly, and hacking cmd_and_fixdep is ugly.
I came up with a new way to find exported symbols; insert a dummy
symbol __ksym_marker_* to each potentially exported symbol. Those
dummy symbols are picked up by $(NM), post-processed by sed, then
appended to .*.cmd files. I collected the post-process part to a
new shell script scripts/gen_ksymdeps.sh for readability. The dummy
symbols are put into the .discard.* section so that the linker
script rips them off the final vmlinux or modules.
A nice side-effect is building with CONFIG_TRIM_UNUSED_KSYMS will
be much faster.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Let $(CC) compile objects into normal files *.o instead of .tmp_*.o
whether CONFIG_MODVERSIONS is enabled or not. With this, the input
file for objtool is always *.o so objtool_o can go away.
I guess the reason of using .tmp_*.o for intermediate objects was
to avoid leaving incomplete *.o file (, whose timestamp says it is
up-to-date) when the genksyms tool failed for some reasons.
It no longer matters because any targets are deleted on errors since
commit 9c2af1c737 ("kbuild: add .DELETE_ON_ERROR special target").
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, fixdep writes dependencies to .*.tmp, which is renamed to
.*.cmd after everything succeeds. This is a very safe way to avoid
corrupted .*.cmd files. The if_changed_dep has carried this safety
mechanism since it was added in 2002.
If fixdep fails for some reasons or a user terminates the build while
fixdep is running, the incomplete output from the fixdep could be
troublesome.
This is my insight about some bad scenarios:
[1] If the compiler succeeds to generate *.o file, but fixdep fails
to write necessary dependencies to .*.cmd file, Make will miss
to rebuild the object when headers or CONFIG options are changed.
In this case, fixdep should not generate .*.cmd file at all so
that 'arg-check' will surely trigger the rebuild of the object.
[2] A partially constructed .*.cmd file may not be a syntactically
correct makefile. The next time Make runs, it would include it,
then fail to parse it. Once this happens, 'make clean' is be the
only way to fix it.
In fact, [1] is no longer a problem since commit 9c2af1c737 ("kbuild:
add .DELETE_ON_ERROR special target"). Make deletes a target file on
any failure in its recipe. Because fixdep is a part of the recipe of
*.o target, if it fails, the *.o is deleted anyway. However, I am a
bit worried about the slight possibility of [2].
So, here is a solution. Let fixdep directly write to a .*.cmd file,
but allow makefiles to include it only when its corresponding target
exists.
This effectively reverts commit 2982c95357 ("kbuild: remove redundant
$(wildcard ...) for cmd_files calculation"), and commit 00d78ab2ba
("kbuild: remove dead code in cmd_files calculation in top Makefile")
because now we must check the presence of targets.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Pull Kbuild updates from Masahiro Yamada:
- optimize kallsyms slightly
- remove check for old CFLAGS usage
- add some compiler flags unconditionally instead of evaluating
$(call cc-option,...)
- fix variable shadowing in host tools
- refactor scripts/mkmakefile
- refactor various makefiles
* tag 'kbuild-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild:
modpost: Create macro to avoid variable shadowing
ASN.1: Remove unnecessary shadowed local variable
kbuild: use 'else ifeq' for checksrc to improve readability
kbuild: remove unneeded link_multi_deps
kbuild: add -Wno-unused-but-set-variable flag unconditionally
kbuild: add -Wdeclaration-after-statement flag unconditionally
kbuild: add -Wno-pointer-sign flag unconditionally
modpost: remove leftover symbol prefix handling for module device table
kbuild: simplify command line creation in scripts/mkmakefile
kbuild: do not pass $(objtree) to scripts/mkmakefile
kbuild: remove user ID check in scripts/mkmakefile
kbuild: remove VERSION and PATCHLEVEL from $(objtree)/Makefile
kbuild: add --include-dir flag only for out-of-tree build
kbuild: remove dead code in cmd_files calculation in top Makefile
kbuild: hide most of targets when running config or mixed targets
kbuild: remove old check for CFLAGS use
kbuild: prefix Makefile.dtbinst path with $(srctree) unconditionally
kallsyms: remove left-over Blackfin code
kallsyms: reduce size a little on 64-bit
'ifeq ... else ifeq ... endif' notation is supported by GNU Make 3.81
or later, which is the requirement for building the kernel since
commit 37d69ee308 ("docs: bump minimal GNU Make version to 3.81").
Use it to improve the readability.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Since commit c8589d1e9e ("kbuild: handle multi-objs dependency
appropriately"), $^ really represents all the prerequisite of the
composite object being built.
Hence, $(filter %.o,$^) contains all the objects to link together,
which is much simpler than link_multi_deps calculation.
Please note $(filter-out FORCE,$^) does not work here. When a single
object module is turned into a multi object module, $^ will contain
header files that were previously included for building the single
object, and recorded in the .*.cmd file. To filter out such headers,
$(filter %.o,$^) should be used here.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
When building to record the mcount locations the kernel uses
KBUILD_CFLAGS but not KBUILD_CPPFLAGS. This means it lacks
-Qunused-arguments when building with clang, resulting in a lot of
noisy warnings.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
