This patch adds basic support for the new 405EX and the AMCC eval board
Kilauea to arch/powerpc.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
I get a compilation error in sglist-arch branch
with BLK_DEV_IO_TRACE=n:
CC block/compat_ioctl.o
/usr0/export/dev/bharrosh/git/pub/linux-2.6-block/block/compat_ioctl.c: In
function ?compat_blk_trace_setup?:
/usr0/export/dev/bharrosh/git/pub/linux-2.6-block/block/compat_ioctl.c:568:
error: expected expression before ?do?
make[2]: *** [block/compat_ioctl.o] Error 1
Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
We were intending to put the previous instance of delegation->cred
before setting a new one.
Thanks to David Howells for spotting this.
Signed-off-by: Trond Myklebust <Trond.Myklebust@netapp.com>
All ppc32 systems except PReP and 8xx are capable of handling 3G of user
address space. Old legacy had set this to 2GB and no one has bothered to
fix it.
8xx could be bumped up to 3GB if its SW TLB miss handlers were fixed up
to properly determine kernel/user addresses.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Move to using PAGE_OFFSET instead of TASK_SIZE or KERNELBASE value on
6xx/40x/44x/fsl-booke to determine if the faulting address is a kernel or
user space address. This mimics how the macro is_kernel_addr() works.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Using weight32() to determine if a value is a power of 2 is a rather
heavi weight solution. The classic idiom is (x & (x - 1)) == 0, but
the kernel already provide a is_power_of_2 function for it.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
Change the $(ARCH) dependency to $(SRCARCH) to honor the x86
namespace for i386 and x86_64.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
asm-powerpc/mpc85xx.h was really a hold over from arch/ppc. Now that
more decoupling has occurred we can remove <asm/mpc85xx.h> and some of
its legacy.
As part of this we moved the definition of CPM_MAP_ADDR into cpm2.h
for 85xx platforms. This is a stop gap until drivers stop using
CPM_MAP_ADDR.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We don't use any CPM devices on these boards, but the muram node on these
chips is different from the 8560, so it's helpful to people working with
custom boards based on these chips.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch adds a new merged driver for FSC sensor chips, it merges the fscher
and fscpos drivers and adds support for the FSC Scylla, Heracles and Heimdall
chips.
Signed-off-by: Hans de Goede <j.w.r.degoede@hhs.nl>
Acked-by: Jean Delvare <khali@linux-fr.org>
Signed-off-by: Mark M. Hoffman <mhoffman@lightlink.com>
In testing the new clocksource and clockevent code on a PPC601
processor, I discovered that the clockevent multiplier value for the
decrementer clockevent was overflowing. Because the RTCL register in
the 601 effectively counts at 1GHz (it doesn't actually, but it
increases by 128 every 128ns), and the shift value was 32, that meant
the multiplier value had to be 2^32, which won't fit in an unsigned
long on 32-bit. The same problem would arise on any platform where
the timebase frequency was 1GHz or more (not that we actually have any
such machines today).
This fixes it by reducing the shift value to 16. Doing the
calculations with a resolution of 2^-16 nanoseconds (15 femtoseconds)
should be quite adequate. :)
Signed-off-by: Paul Mackerras <paulus@samba.org>
On old powermacs, we sometimes set the decrementer to 1 in order to
trigger a decrementer interrupt, which we use to handle an interrupt
that was pending at the time when it was re-enabled. This was causing
the decrementer clock event device to call the event function for the
next event early, which was causing problems when high-res timers were
not enabled.
This fixes the problem by recording the timebase value at which the
next event should occur, and checking the current timebase against the
recorded value in timer_interrupt. If it isn't time for the next
event, it just reprograms the decrementer and returns.
This also subtracts 1 from the value stored into the decrementer,
which is appropriate because the decrementer interrupts on the
transition from 0 to -1, not when the decrementer reaches 0.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Some IBM machines supply a "logical" PVR (processor version register)
value in the device tree in the cpu nodes rather than the real PVR.
This is used for instance to indicate that the processors in a POWER6
partition have been configured by the hypervisor to run in POWER5+
mode rather than POWER6 mode. To cope with this, we call identify_cpu
a second time with the logical PVR value (the first call is with the
real PVR value in the very early setup code).
However, POWER5+ machines can also supply a logical PVR value, and use
the same value (the value that indicates a v2.04 architecture
compliant processor). This causes problems for code that uses the
performance monitor (such as oprofile), because the PMU registers are
different in POWER6 (even in POWER5+ mode) from the real POWER5+.
This change works around this problem by taking out the PMU
information from the cputable entries for the logical PVR values, and
changing identify_cpu so that the second call to it won't overwrite
the PMU information that was established by the first call (the one
with the real PVR), but does update the other fields. Specifically,
if the cputable entry for the logical PVR value has num_pmcs == 0,
none of the PMU-related fields get used.
So that we can create a mixed cputable entry, we now make cur_cpu_spec
point to a single static struct cpu_spec, and copy stuff from
cpu_specs[i] into it. This has the side-effect that we can now make
cpu_specs[] be initdata.
Ultimately it would be good to move the PMU-related fields out to a
separate structure, pointed to by the cputable entries, and change
identify_cpu so that it saves the PMU info pointer, copies the whole
structure, and restores the PMU info pointer, rather than identify_cpu
having to list all the fields that are *not* PMU-related.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
As explained on:
http://www.avrfreaks.net/index.php?nameÿphpBB2&fileÿewtopic&tS307
If the current process is preempted before it can copy RAR_SUP and
RSR_SUP both register are lost and the process will segfault as soon
as it return from the syscall since the return adress will be
corrupted.
This patch disable IRQ as soon as we enter the syscall path and
reenable them when the copy is done.
In the interrupt handlers, check if we are interrupting the srrf
instruction, if so disable interrupts and return. The interrupt
handler will be re-called immediatly when the interrupts are
reenabled.
After some stressing workload:
- find / > /dev/null in loop
- top (in ssh)
- ping -f avr32
The segfaults are not seen anymore.
Signed-off-by: Philippe Rétornaz <philippe.retornaz@epfl.ch>
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
The implementation of __builtin_xchg() in at least some versions of
avr32 gcc is buggy. Rather than find out exactly which versions that
have this bug, let's just avoid the problem altogether by implementing
xchg() in inline assembly.
Also, in most architectures, xchg() seems to imply a memory barrier,
while the existing avr32 implementation did not. This patch also fixes
that discrepancy.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Make the NGW100 bitbang i2c use open drain signaling.
Also, speed it up, so it's closer to 100 kHz ... the code paths seem
to be long enough that the udelay isn't dominating bit times. The
peak bit rate I observed was around 125 kHz, but that's with large
delays (usually before ACK/NAK) which hold the overall rate down to
around 80 kHz (call it 100 usec/byte on average).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
