Imran Shaik
0e193cc558
dt-bindings: clock: qcom: Add CAMCC clocks for QCS8300
...
The QCS8300 camera clock controller is a derivative of SA8775P, but has
an additional clock and minor differences. Hence, reuse the SA8775P
camera bindings and add additional clock required for QCS8300.
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org >
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com >
Link: https://lore.kernel.org/r/20250109-qcs8300-mm-patches-new-v4-3-63e8ac268b02@quicinc.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org >
2025-02-02 20:59:04 -06:00
Imran Shaik
f0ada00a9b
dt-bindings: clock: qcom: Add GPU clocks for QCS8300
...
The QCS8300 GPU clock controller is a derivative of SA8775P, but has few
additional clocks and minor differences. Hence, reuse gpucc bindings of
SA8775P and add additional clocks required for QCS8300.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com >
Link: https://lore.kernel.org/r/20250109-qcs8300-mm-patches-new-v4-1-63e8ac268b02@quicinc.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org >
2025-02-02 20:59:04 -06:00
Stephen Boyd
1d2da923fb
Merge branches 'clk-airoha', 'clk-rockchip', 'clk-stm', 'clk-thead' and 'clk-bcm' into clk-next
...
* clk-airoha:
clk: en7523: Add clock for eMMC for EN7581
dt-bindings: clock: add ID for eMMC for EN7581
dt-bindings: clock: drop NUM_CLOCKS define for EN7581
clk: en7523: Rework clock handling for different clock numbers
clk: en7523: Initialize num before accessing hws in en7523_register_clocks()
clk: en7523: Fix wrong BUS clock for EN7581
clk: amlogic: axg-audio: revert reset implementation
Revert "clk: Fix invalid execution of clk_set_rate"
* clk-rockchip:
clk: rockchip: rk3588: make refclko25m_ethX critical
clk: rockchip: rk3588: drop RK3588_LINKED_CLK
clk: rockchip: implement linked gate clock support
clk: rockchip: expose rockchip_clk_set_lookup
clk: rockchip: rk3588: register GATE_LINK later
clk: rockchip: support clocks registered late
* clk-stm:
clk: stm32f4: support spread spectrum clock generation
clk: stm32f4: use FIELD helpers to access the PLLCFGR fields
dt-bindings: clock: st,stm32-rcc: support spread spectrum clocking
dt-bindings: clock: convert stm32 rcc bindings to json-schema
* clk-thead:
clk: thead: Fix cpu2vp_clk for TH1520 AP_SUBSYS clocks
clk: thead: Add CLK_IGNORE_UNUSED to fix TH1520 boot
clk: thead: Fix clk gate registration to pass flags
* clk-bcm:
clk: bcm: rpi: Add disp clock
clk: bcm: rpi: Create helper to retrieve private data
clk: bcm: rpi: Enable minimize for all firmware clocks
clk: bcm: rpi: Allow cpufreq driver to also adjust gpu clocks
clk: bcm: rpi: Add ISP to exported clocks
2025-01-21 11:22:26 -08:00
Stephen Boyd
b2fee97e6f
Merge branches 'clk-microchip', 'clk-xilinx', 'clk-allwinner', 'clk-imx' and 'clk-qcom' into clk-next
...
* clk-microchip:
clk: at91: sama7d65: add sama7d65 pmc driver
dt-bindings: clock: Add SAMA7D65 PMC compatible string
dt-bindings: clocks: atmel,at91sam9x5-sckc: add sama7d65
clk: at91: sckc: Use SCKC_{TD, MD}_SLCK IDs for clk32k clocks
dt-bindings: clk: at91: Add clock IDs for the slow clock controller
* clk-xilinx:
clk: clocking-wizard: calculate dividers fractional parts
dt-bindings: clock: xilinx: Add reset GPIO for VCU
dt-bindings: clock: xilinx: Convert VCU bindings to dtschema
* clk-allwinner:
clk: sunxi-ng: h616: Reparent CPU clock during frequency changes
clk: sunxi-ng: a64: stop force-selecting PLL-MIPI as TCON0 parent
clk: sunxi-ng: a64: drop redundant CLK_PLL_VIDEO0_2X and CLK_PLL_MIPI
dt-bindings: clock: sunxi: Export PLL_VIDEO_2X and PLL_MIPI
* clk-imx:
clk: imx: Apply some clks only for i.MX93
arm64: dts: imx93: Use IMX93_CLK_SPDIF_IPG as SPDIF IPG clock
clk: imx93: Add IMX93_CLK_SPDIF_IPG clock
dt-bindings: clock: imx93: Add SPDIF IPG clk
clk: imx: pll14xx: Add 208 MHz and 416 MHz entries for PLL1416x
clk: imx8mp: Fix clkout1/2 support
* clk-qcom: (63 commits)
clk: qcom: Select CLK_X1E80100_GCC in config CLK_X1P42100_GPUCC
dt-bindings: clock: move qcom,x1e80100-camcc to its own file
clk: qcom: smd-rpm: Add clocks for MSM8940
dt-bindings: clock: qcom,rpmcc: Add MSM8940 compatible
clk: qcom: smd-rpm: Add clocks for MSM8937
dt-bindings: clock: qcom,rpmcc: Add MSM8937 compatible
clk: qcom: ipq5424: Use icc-clk for enabling NoC related clocks
dt-bindings: interconnect: Add Qualcomm IPQ5424 support
clk: qcom: Add SM6115 LPASSCC
dt-bindings: clock: Add Qualcomm SM6115 LPASS clock controller
clk: qcom: gcc-sdm845: Do not use shared clk_ops for QUPs
clk: qcom: gcc-sdm845: Add general purpose clock ops
clk: qcom: clk-rcg2: split __clk_rcg2_configure function
clk: qcom: clk-rcg2: document calc_rate function
clk: qcom: gcc-x1e80100: Do not turn off usb_2 controller GDSC
clk: qcom: ipq5424: add gcc_xo_clk
dt-bindings: clock: qcom: gcc-ipq5424: add gcc_xo_clk macro
dt-bindings: clock: qcom: gcc-ipq5424: remove apss_dbg clock macro
clk: qcom: ipq5424: remove apss_dbg clock
dt-bindings: clock: qcom,sdm845-camcc: add sdm670 compatible
...
2025-01-21 11:22:19 -08:00
Stephen Boyd
70741cc384
Merge branches 'clk-cleanup', 'clk-renesas', 'clk-mediatek', 'clk-samsung' and 'clk-socfpga' into clk-next
...
- Support for 5L35023 variant of Versa 3 clock generator
* clk-cleanup:
clk: analogbits: Fix incorrect calculation of vco rate delta
clk: Use str_enable_disable-like helpers
clk: clk-loongson2: Switch to use devm_clk_hw_register_fixed_rate_parent_data()
clk: starfive: Make _clk_get become a common helper function
clk: ep93xx: make const read-only arrays static
clk: lmk04832: make read-only const arrays static
clk: ti: use kcalloc() instead of kzalloc()
dt-bindings: clock: st,stm32mp1-rcc: complete the reference path
dt-bindings: clock: st,stm32mp1-rcc: fix reference paths
dt-bindings: clock: ti: Convert composite.txt to json-schema
dt-bindings: clock: ti: Convert gate.txt to json-schema
clk: Drop obsolete devm_clk_bulk_get_all_enable() helper
PCI: exynos: Switch to devm_clk_bulk_get_all_enabled()
soc: mediatek: pwrap: Switch to devm_clk_bulk_get_all_enabled()
clk: davinci: remove platform data struct
clk: fix an OF node reference leak in of_clk_get_parent_name()
clk: mmp: pxa1908-apbc: Fix NULL vs IS_ERR() check
clk: mmp: pxa1908-apbcp: Fix a NULL vs IS_ERR() check
clk: mmp: pxa1908-mpmu: Fix a NULL vs IS_ERR() check
* clk-renesas: (24 commits)
dt-bindings: clock: renesas,r9a08g045-vbattb: Fix include guard
clk: renesas: r9a09g057: Add clock and reset entries for GIC
clk: renesas: r9a09g057: Add reset entry for SYS
clk: renesas: r8a779g0: Add VSPX clocks
clk: renesas: r8a779g0: Add FCPVX clocks
clk: renesas: r9a09g047: Add I2C clocks/resets
clk: renesas: r9a09g047: Add CA55 core clocks
clk: renesas: rzv2h: Add support for RZ/G3E SoC
clk: renesas: rzv2h: Add MSTOP support
dt-bindings: clock: renesas: Document RZ/G3E SoC CPG
dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK
dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants
clk: versaclock3: Add support for the 5L35023 variant
dt-bindings: clock: versaclock3: Document 5L35023 Versa3 clock generator
clk: versaclock3: Prepare for the addition of 5L35023 device
clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ADC IP
clk: renesas: r8a779h0: Add display clocks
clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets
clk: renesas: rzv2h: Add selective Runtime PM support for clocks
clk: renesas: r9a06g032: Use BIT macro consistently
...
* clk-mediatek:
clk: ralink: mtmips: remove duplicated 'xtal' clock for Ralink SoC RT3883
clk: mediatek: mt2701-img: add missing dummy clk
clk: mediatek: mt2701-mm: add missing dummy clk
clk: mediatek: mt2701-bdp: add missing dummy clk
clk: mediatek: mt2701-aud: fix conversion to mtk_clk_simple_probe
clk: mediatek: mt2701-vdec: fix conversion to mtk_clk_simple_probe
* clk-samsung:
clk: samsung: Introduce Exynos990 clock controller driver
clk: samsung: clk-pll: Add support for pll_{0717x, 0718x, 0732x}
dt-bindings: clock: samsung: Add Exynos990 SoC CMU bindings
* clk-socfpga:
clk: socfpga: arria10: Optimize local variables in clk_pll_recalc_rate()
2025-01-21 11:22:03 -08:00
Dario Binacchi
ebca39700f
dt-bindings: clock: convert stm32 rcc bindings to json-schema
...
The patch converts st,stm32-rcc.txt to the JSON schema, but it does more
than that. The old bindings, in fact, only covered the stm32f{4,7}
platforms and not the stm32h7. Therefore, to avoid patch submission tests
failing, it was necessary to add the corresponding compatible (i. e.
st,stm32h743-rcc) and specify that, in this case, 3 are the clocks instead
of the 2 required for the stm32f{4,7} platforms.
Additionally, the old bindings made no mention of the st,syscfg property,
which is used by both the stm32f{4,7} and the stm32h7 platforms.
The patch also fixes the files referencing to the old st,stm32-rcc.txt.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com >
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Link: https://lore.kernel.org/r/20250114182021.670435-2-dario.binacchi@amarulasolutions.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2025-01-15 15:17:05 -08:00
Christian Marangi
82108ad328
dt-bindings: clock: add ID for eMMC for EN7581
...
Add ID for eMMC for EN7581. This is to control clock selection of eMMC
between 200MHz and 150MHz.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com >
Acked-by: Conor Dooley <conor.dooley@microchip.com >
Link: https://lore.kernel.org/r/20250113231030.6735-4-ansuelsmth@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2025-01-13 15:24:12 -08:00
Christian Marangi
02d3b7557c
dt-bindings: clock: drop NUM_CLOCKS define for EN7581
...
Drop NUM_CLOCKS define for EN7581 include. This is not a binding and
should not be placed here. Value is derived internally in the user
driver.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com >
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Link: https://lore.kernel.org/r/20250113231030.6735-3-ansuelsmth@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2025-01-13 15:24:12 -08:00
Konrad Dybcio
030de8eafd
dt-bindings: clock: Add Qualcomm SM6115 LPASS clock controller
...
SM6115 (and its derivatives or similar SoCs) has an LPASS clock
controller block which provides audio-related resets.
Add bindings for it.
Cc: Konrad Dybcio <konradybcio@kernel.org >
Cc: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com >
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org >
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
[alexey.klimov slightly changed the commit message]
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org >
Link: https://lore.kernel.org/r/20241212002551.2902954-2-alexey.klimov@linaro.org
[bjorn: Adjusted Konrad's address]
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2025-01-07 20:29:27 -06:00
Geert Uytterhoeven
e91609f1c3
dt-bindings: clock: renesas,r9a08g045-vbattb: Fix include guard
...
Add the missing "RENESAS" part to the include guard.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
Link: https://lore.kernel.org/34953d1e9f472e4f29533ed06cf092dd3c0d1178.1736238939.git.geert+renesas@glider.be
2025-01-07 17:03:01 +01:00
Manikanta Mylavarapu
a8b56cb27d
dt-bindings: clock: qcom: gcc-ipq5424: add gcc_xo_clk macro
...
The GCC_XO_CLK is required for the functionality of the WiFi
copy engine block. Therefore, add the GCC_XO_CLK macro.
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com >
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Link: https://lore.kernel.org/r/20241210064110.130466-2-quic_mmanikan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2025-01-06 18:33:11 -06:00
Manikanta Mylavarapu
46e6075287
dt-bindings: clock: qcom: gcc-ipq5424: remove apss_dbg clock macro
...
The gcc_apss_dbg clk is access protected by trust zone, and accessing
it results in a kernel crash. Therefore remove the gcc_apss_dbg_clk macro.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com >
Link: https://lore.kernel.org/r/20241217113909.3522305-3-quic_mmanikan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2025-01-06 18:11:19 -06:00
Dmitry Baryshkov
0a0693fb26
dt-bindings: clock: qcom,mmcc-msm8960: add LCDC-related clocks
...
APQ8064 / MSM8960 have separate LVDS / LCDC clock, driving the MDP4 LCD
controller. Add corresponding indices to clock controller bindings.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Link: https://lore.kernel.org/r/20241224-apq8064-fix-mmcc-v1-2-c95d2e2bf143@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2025-01-06 18:05:27 -06:00
Bjorn Andersson
62ede76a7b
Merge branch '20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com' into clk-for-6.14
...
Merge the IPQ CMN PLL clock binding through a topic branch to make it
available to DeviceTree source branches as well.
2025-01-06 17:41:49 -06:00
Luo Jie
c0f1cbf795
dt-bindings: clock: qcom: Add CMN PLL clock controller for IPQ SoC
...
The CMN PLL controller provides clocks to networking hardware blocks
and to GCC on Qualcomm IPQ9574 SoC. It receives input clock from the
on-chip Wi-Fi, and produces output clocks at fixed rates. These output
rates are predetermined, and are unrelated to the input clock rate.
The primary purpose of CMN PLL is to supply clocks to the networking
hardware such as PPE (packet process engine), PCS and the externally
connected switch or PHY device. The CMN PLL block also outputs fixed
rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep
clock supplied to GCC.
Signed-off-by: Luo Jie <quic_luoj@quicinc.com >
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2025-01-06 17:41:39 -06:00
Bjorn Andersson
9d46289f18
Merge branch '20250106-sm8750-dispcc-v2-1-6f42beda6317@linaro.org' into clk-for-6.14
...
Merge SM8750 display clock controller bindings through topic branch, to
make available to DeviceTree source branch as well.
2025-01-06 10:30:24 -06:00
Krzysztof Kozlowski
4f1a62e2b3
dt-bindings: clock: qcom,sm8550-dispcc: Add SM8750 DISPCC
...
Add bindings for the Qualcomm SM8750 Display Clock Controller (DISPCC).
Bindings are similar to existing SM8550 and SM8650 (same clock inputs),
but the clock hierarchy is quite different and these are not compatible
devices.
The binding header was copied from downstream sources, so I retained
original copyrights.
Acked-by: Conor Dooley <conor.dooley@microchip.com >
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Link: https://lore.kernel.org/r/20250106-sm8750-dispcc-v2-1-6f42beda6317@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2025-01-06 10:30:00 -06:00
Bjorn Andersson
4188e51685
Merge branch '20241204-sm8750_master_clks-v3-0-1a8f31a53a86@quicinc.com' into clk-for-6.14
...
Merge the SM8750 GCC and TCSR clock bindings through topic branch, to
allow merging into DeviceTree source branch as well.
2025-01-06 10:27:11 -06:00
Taniya Das
8817c21a45
dt-bindings: clock: qcom: Document the SM8750 TCSR Clock Controller
...
Add bindings documentation for the SM8750 Clock Controller.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com >
Signed-off-by: Taniya Das <quic_tdas@quicinc.com >
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-7-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2025-01-06 10:27:00 -06:00
Taniya Das
42b00f4456
dt-bindings: clock: qcom: Add SM8750 GCC
...
Add device tree bindings for the global clock controller on Qualcomm
SM8750 platform.
Signed-off-by: Taniya Das <quic_tdas@quicinc.com >
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com >
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-5-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2025-01-06 10:27:00 -06:00
Vasily Khoruzhick
9897831de6
dt-bindings: clock: sunxi: Export PLL_VIDEO_2X and PLL_MIPI
...
Export PLL_VIDEO_2X and PLL_MIPI, these will be used to explicitly
select TCON0 clock parent in dts
Fixes: ca1170b699dsimic@manjaro.org >
Reviewed-by: Chen-Yu Tsai <wens@csie.org >
Tested-by: Frank Oltmanns <frank@oltmanns.dev > # on PinePhone
Tested-by: Stuart Gathman <stuart@gathman.org > # on OG Pinebook
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com >
Acked-by: Krzysztof Kozlowski <krzk@kernel.org >
Link: https://patch.msgid.link/20250104074035.1611136-2-anarsoul@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org >
2025-01-04 19:09:31 +08:00
Shengjiu Wang
32e9dea264
dt-bindings: clock: imx93: Add SPDIF IPG clk
...
Add SPDIF IPG clk. The SPDIF IPG clock and root clock
share same clock gate.
Fixes: 1c4a4f7362shengjiu.wang@nxp.com >
Reviewed-by: Frank Li <Frank.Li@nxp.com >
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Link: https://lore.kernel.org/r/20241119015805.3840606-2-shengjiu.wang@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org >
2024-12-26 16:41:33 +02:00
Bjorn Andersson
75c5cb35a8
Merge branch '20241221-topic-x1p4_clk-v1-2-dbaeccb74884@oss.qualcomm.com' into clk-for-6.14
...
Merge the X1P42100 GPUCC binding through a topic branch to make
available for the DeviceTree branch as well.
2024-12-25 21:56:50 -06:00
Konrad Dybcio
e8f81b5613
dt-bindings: clock: qcom,x1e80100-gpucc: Extend for X1P42100
...
To make it easier for X1P4 and X1E to share a common device tree base,
extend the existing latter's GPUCC bindings and reuse them on the
former platform.
While not in the same file, it only makes sense to introduce the new
compatible in this commit as well.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com >
Link: https://lore.kernel.org/r/20241221-topic-x1p4_clk-v1-2-dbaeccb74884@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2024-12-25 21:56:30 -06:00
Dharma Balasubiramani
1c9eb9e684
dt-bindings: clock: Add SAMA7D65 PMC compatible string
...
Add the `microchip,sama7d65-pmc` compatible string to the existing binding,
since the SAMA7D65 PMC shares the same properties and clock requirements
as the SAMA7G5.
Export MCK3 and MCK5 to be accessed and referenced in DT to assign to
the clocks property for sama7d65 SoC.
Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com >
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com >
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev >
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Link: https://lore.kernel.org/r/5252a28531deaee67af1edd8e72d45ca57783464.1733505542.git.Ryan.Wanner@microchip.com
[claudiu.beznea: use tabs instead of spaces in
include/dt-bindings/clock/at91.h]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev >
2024-12-17 10:10:21 +02:00
