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ice: Align E810T GPIO to other products

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Instead of having separate PTP GPIO implementation for E810T, use
existing one from all other products.

Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
This commit is contained in:
Karol Kolacinski
2024-08-30 13:07:19 +02:00
committed by Tony Nguyen
parent 1d86cca479
commit e4291b64e1
5 changed files with 151 additions and 401 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/net/ethernet/intel/ice/ice_gnss.c
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@@ -397,8 +397,8 @@ bool ice_gnss_is_gps_present(struct ice_hw *hw)
int err;
u8 data;
err = ice_read_pca9575_reg_e810t(hw, ICE_PCA9575_P0_IN, &data);
if (err || !!(data & ICE_E810T_P0_GNSS_PRSNT_N))
err = ice_read_pca9575_reg(hw, ICE_PCA9575_P0_IN, &data);
if (err || !!(data & ICE_P0_GNSS_PRSNT_N))
return false;
} else {
return false;

460
drivers/net/ethernet/intel/ice/ice_ptp.c
View File

File diff suppressed because it is too large Load Diff

29
drivers/net/ethernet/intel/ice/ice_ptp.h
View File

@@ -8,24 +8,6 @@
#include <linux/kthread.h>
#include "ice_ptp_hw.h"
enum ice_ptp_pin_e810 {
GPIO_20 = 0,
GPIO_21,
GPIO_22,
GPIO_23,
NUM_PTP_PIN_E810
};
enum ice_ptp_pin_e810t {
GNSS = 0,
SMA1,
UFL1,
SMA2,
UFL2,
NUM_PTP_PINS_E810T
};
struct ice_perout_channel {
bool ena;
u32 gpio_pin;
@@ -230,6 +212,14 @@ enum ice_ptp_pin {
ONE_PPS
};
enum ice_ptp_pin_e810t {
GNSS = 0,
SMA1,
UFL1,
SMA2,
UFL2
};
/* Per-channel register definitions */
#define GLTSYN_AUX_OUT(_chan, _idx) (GLTSYN_AUX_OUT_0(_idx) + ((_chan) * 8))
#define GLTSYN_AUX_IN(_chan, _idx) (GLTSYN_AUX_IN_0(_idx) + ((_chan) * 8))
@@ -241,9 +231,8 @@ enum ice_ptp_pin {
#define GLTSYN_EVNT_H_IDX_MAX 3
/* Pin definitions for PTP */
#define PPS_CLK_GEN_CHAN 3
#define PPS_PIN_INDEX 5
#define ICE_N_PINS_MAX 6
#define ICE_SMA_PINS_NUM 4
#define ICE_PIN_DESC_ARR_LEN(_arr) (sizeof(_arr) / \
sizeof(struct ice_ptp_pin_desc))

20
drivers/net/ethernet/intel/ice/ice_ptp_hw.c
View File

@@ -5150,9 +5150,9 @@ ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready)
return 0;
}
/* E810T SMA functions
/* E810 SMA functions
*
* The following functions operate specifically on E810T hardware and are used
* The following functions operate specifically on E810 hardware and are used
* to access the extended GPIOs available.
*/
@@ -5219,14 +5219,14 @@ ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle)
}
/**
* ice_read_sma_ctrl_e810t
* ice_read_sma_ctrl
* @hw: pointer to the hw struct
* @data: pointer to data to be read from the GPIO controller
*
* Read the SMA controller state. It is connected to pins 3-7 of Port 1 of the
* PCA9575 expander, so only bits 3-7 in data are valid.
*/
int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data)
int ice_read_sma_ctrl(struct ice_hw *hw, u8 *data)
{
int status;
u16 handle;
@@ -5238,7 +5238,7 @@ int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data)
*data = 0;
for (i = ICE_SMA_MIN_BIT_E810T; i <= ICE_SMA_MAX_BIT_E810T; i++) {
for (i = ICE_SMA_MIN_BIT; i <= ICE_SMA_MAX_BIT; i++) {
bool pin;
status = ice_aq_get_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET,
@@ -5252,14 +5252,14 @@ int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data)
}
/**
* ice_write_sma_ctrl_e810t
* ice_write_sma_ctrl
* @hw: pointer to the hw struct
* @data: data to be written to the GPIO controller
*
* Write the data to the SMA controller. It is connected to pins 3-7 of Port 1
* of the PCA9575 expander, so only bits 3-7 in data are valid.
*/
int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data)
int ice_write_sma_ctrl(struct ice_hw *hw, u8 data)
{
int status;
u16 handle;
@@ -5269,7 +5269,7 @@ int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data)
if (status)
return status;
for (i = ICE_SMA_MIN_BIT_E810T; i <= ICE_SMA_MAX_BIT_E810T; i++) {
for (i = ICE_SMA_MIN_BIT; i <= ICE_SMA_MAX_BIT; i++) {
bool pin;
pin = !(data & (1 << i));
@@ -5283,14 +5283,14 @@ int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data)
}
/**
* ice_read_pca9575_reg_e810t
* ice_read_pca9575_reg
* @hw: pointer to the hw struct
* @offset: GPIO controller register offset
* @data: pointer to data to be read from the GPIO controller
*
* Read the register from the GPIO controller
*/
int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data)
int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data)
{
struct ice_aqc_link_topo_addr link_topo;
__le16 addr;

39
drivers/net/ethernet/intel/ice/ice_ptp_hw.h
View File

@@ -400,9 +400,9 @@ int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port);
int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold);
/* E810 family functions */
int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);
int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);
int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data);
int ice_read_sma_ctrl(struct ice_hw *hw, u8 *data);
int ice_write_sma_ctrl(struct ice_hw *hw, u8 data);
int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data);
bool ice_is_pca9575_present(struct ice_hw *hw);
enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input);
struct dpll_pin_frequency *
@@ -688,30 +688,27 @@ static inline u64 ice_get_base_incval(struct ice_hw *hw)
#define LOW_TX_MEMORY_BANK_START 0x03090000
#define HIGH_TX_MEMORY_BANK_START 0x03090004
/* E810T SMA controller pin control */
#define ICE_SMA1_DIR_EN_E810T BIT(4)
#define ICE_SMA1_TX_EN_E810T BIT(5)
#define ICE_SMA2_UFL2_RX_DIS_E810T BIT(3)
#define ICE_SMA2_DIR_EN_E810T BIT(6)
#define ICE_SMA2_TX_EN_E810T BIT(7)
/* SMA controller pin control */
#define ICE_SMA1_DIR_EN BIT(4)
#define ICE_SMA1_TX_EN BIT(5)
#define ICE_SMA2_UFL2_RX_DIS BIT(3)
#define ICE_SMA2_DIR_EN BIT(6)
#define ICE_SMA2_TX_EN BIT(7)
#define ICE_SMA1_MASK_E810T (ICE_SMA1_DIR_EN_E810T | \
ICE_SMA1_TX_EN_E810T)
#define ICE_SMA2_MASK_E810T (ICE_SMA2_UFL2_RX_DIS_E810T | \
ICE_SMA2_DIR_EN_E810T | \
ICE_SMA2_TX_EN_E810T)
#define ICE_ALL_SMA_MASK_E810T (ICE_SMA1_MASK_E810T | \
ICE_SMA2_MASK_E810T)
#define ICE_SMA1_MASK (ICE_SMA1_DIR_EN | ICE_SMA1_TX_EN)
#define ICE_SMA2_MASK (ICE_SMA2_UFL2_RX_DIS | ICE_SMA2_DIR_EN | \
ICE_SMA2_TX_EN)
#define ICE_ALL_SMA_MASK (ICE_SMA1_MASK | ICE_SMA2_MASK)
#define ICE_SMA_MIN_BIT_E810T 3
#define ICE_SMA_MAX_BIT_E810T 7
#define ICE_SMA_MIN_BIT 3
#define ICE_SMA_MAX_BIT 7
#define ICE_PCA9575_P1_OFFSET 8
/* E810T PCA9575 IO controller registers */
/* PCA9575 IO controller registers */
#define ICE_PCA9575_P0_IN 0x0
/* E810T PCA9575 IO controller pin control */
#define ICE_E810T_P0_GNSS_PRSNT_N BIT(4)
/* PCA9575 IO controller pin control */
#define ICE_P0_GNSS_PRSNT_N BIT(4)
/* ETH56G PHY register addresses */
/* Timestamp PHY incval registers */