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arch/tile: Allow tilegx to build with either 16K or 64K page size
This change introduces new flags for the hv_install_context() API that passes a page table pointer to the hypervisor. Clients can explicitly request 4K, 16K, or 64K small pages when they install a new context. In practice, the page size is fixed at kernel compile time and the same size is always requested every time a new page table is installed. The <hv/hypervisor.h> header changes so that it provides more abstract macros for managing "page" things like PFNs and page tables. For example there is now a HV_DEFAULT_PAGE_SIZE_SMALL instead of the old HV_PAGE_SIZE_SMALL. The various PFN routines have been eliminated and only PA- or PTFN-based ones remain (since PTFNs are always expressed in fixed 2KB "page" size). The page-table management macros are renamed with a leading underscore and take page-size arguments with the presumption that clients will use those macros in some single place to provide the "real" macros they will use themselves. I happened to notice the old hv_set_caching() API was totally broken (it assumed 4KB pages) so I changed it so it would nominally work correctly with other page sizes. Tag modules with the page size so you can't load a module built with a conflicting page size. (And add a test for SMP while we're at it.) Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
This commit is contained in:
Chris Metcalf
@@ -21,7 +21,6 @@ generic-y += ipcbuf.h
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generic-y += irq_regs.h
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generic-y += kdebug.h
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generic-y += local.h
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generic-y += module.h
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generic-y += msgbuf.h
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generic-y += mutex.h
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generic-y += param.h
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@@ -21,7 +21,7 @@ struct mm_context {
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* Written under the mmap_sem semaphore; read without the
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* semaphore but atomically, but it is conservatively set.
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*/
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unsigned int priority_cached;
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unsigned long priority_cached;
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};
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typedef struct mm_context mm_context_t;
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@@ -30,11 +30,15 @@ init_new_context(struct task_struct *tsk, struct mm_struct *mm)
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return 0;
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}
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/* Note that arch/tile/kernel/head.S also calls hv_install_context() */
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/*
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* Note that arch/tile/kernel/head_NN.S and arch/tile/mm/migrate_NN.S
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* also call hv_install_context().
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*/
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static inline void __install_page_table(pgd_t *pgdir, int asid, pgprot_t prot)
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{
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/* FIXME: DIRECTIO should not always be set. FIXME. */
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int rc = hv_install_context(__pa(pgdir), prot, asid, HV_CTX_DIRECTIO);
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int rc = hv_install_context(__pa(pgdir), prot, asid,
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HV_CTX_DIRECTIO | CTX_PAGE_FLAG);
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if (rc < 0)
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panic("hv_install_context failed: %d", rc);
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}
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@@ -0,0 +1,40 @@
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/*
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* Copyright 2011 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ASM_TILE_MODULE_H
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#define _ASM_TILE_MODULE_H
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#include <arch/chip.h>
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#include <asm-generic/module.h>
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/* We can't use modules built with different page sizes. */
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#if defined(CONFIG_PAGE_SIZE_16KB)
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# define MODULE_PGSZ " 16KB"
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#elif defined(CONFIG_PAGE_SIZE_64KB)
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# define MODULE_PGSZ " 64KB"
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#else
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# define MODULE_PGSZ ""
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#endif
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/* We don't really support no-SMP so tag if someone tries. */
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#ifdef CONFIG_SMP
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#define MODULE_NOSMP ""
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#else
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#define MODULE_NOSMP " nosmp"
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#endif
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#define MODULE_ARCH_VERMAGIC CHIP_ARCH_NAME MODULE_PGSZ MODULE_NOSMP
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#endif /* _ASM_TILE_MODULE_H */
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@@ -20,8 +20,17 @@
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#include <arch/chip.h>
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/* PAGE_SHIFT and HPAGE_SHIFT determine the page sizes. */
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#define PAGE_SHIFT HV_LOG2_PAGE_SIZE_SMALL
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#define HPAGE_SHIFT HV_LOG2_PAGE_SIZE_LARGE
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#if defined(CONFIG_PAGE_SIZE_16KB)
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#define PAGE_SHIFT 14
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#define CTX_PAGE_FLAG HV_CTX_PG_SM_16K
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#elif defined(CONFIG_PAGE_SIZE_64KB)
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#define PAGE_SHIFT 16
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#define CTX_PAGE_FLAG HV_CTX_PG_SM_64K
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#else
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#define PAGE_SHIFT HV_LOG2_DEFAULT_PAGE_SIZE_SMALL
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#define CTX_PAGE_FLAG 0
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#endif
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#define HPAGE_SHIFT HV_LOG2_DEFAULT_PAGE_SIZE_LARGE
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#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
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#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
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@@ -19,24 +19,24 @@
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#include <linux/mm.h>
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#include <linux/mmzone.h>
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#include <asm/fixmap.h>
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#include <asm/page.h>
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#include <hv/hypervisor.h>
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/* Bits for the size of the second-level page table. */
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#define L2_KERNEL_PGTABLE_SHIFT \
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(HV_LOG2_PAGE_SIZE_LARGE - HV_LOG2_PAGE_SIZE_SMALL + HV_LOG2_PTE_SIZE)
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#define L2_KERNEL_PGTABLE_SHIFT _HV_LOG2_L2_SIZE(HPAGE_SHIFT, PAGE_SHIFT)
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/* How big is a kernel L2 page table? */
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#define L2_KERNEL_PGTABLE_SIZE (1UL << L2_KERNEL_PGTABLE_SHIFT)
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/* We currently allocate user L2 page tables by page (unlike kernel L2s). */
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#if L2_KERNEL_PGTABLE_SHIFT < HV_LOG2_PAGE_SIZE_SMALL
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#define L2_USER_PGTABLE_SHIFT HV_LOG2_PAGE_SIZE_SMALL
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#if L2_KERNEL_PGTABLE_SHIFT < PAGE_SHIFT
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#define L2_USER_PGTABLE_SHIFT PAGE_SHIFT
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#else
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#define L2_USER_PGTABLE_SHIFT L2_KERNEL_PGTABLE_SHIFT
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#endif
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/* How many pages do we need, as an "order", for a user L2 page table? */
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#define L2_USER_PGTABLE_ORDER (L2_USER_PGTABLE_SHIFT - HV_LOG2_PAGE_SIZE_SMALL)
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/* How big is a kernel L2 page table? */
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#define L2_KERNEL_PGTABLE_SIZE (1 << L2_KERNEL_PGTABLE_SHIFT)
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#define L2_USER_PGTABLE_ORDER (L2_USER_PGTABLE_SHIFT - PAGE_SHIFT)
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static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
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{
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@@ -50,14 +50,14 @@ static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
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static inline void pmd_populate_kernel(struct mm_struct *mm,
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pmd_t *pmd, pte_t *ptep)
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{
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set_pmd(pmd, ptfn_pmd(__pa(ptep) >> HV_LOG2_PAGE_TABLE_ALIGN,
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set_pmd(pmd, ptfn_pmd(HV_CPA_TO_PTFN(__pa(ptep)),
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__pgprot(_PAGE_PRESENT)));
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}
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static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
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pgtable_t page)
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{
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set_pmd(pmd, ptfn_pmd(HV_PFN_TO_PTFN(page_to_pfn(page)),
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set_pmd(pmd, ptfn_pmd(HV_CPA_TO_PTFN(PFN_PHYS(page_to_pfn(page))),
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__pgprot(_PAGE_PRESENT)));
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}
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@@ -68,8 +68,20 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
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extern pgd_t *pgd_alloc(struct mm_struct *mm);
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extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
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extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address);
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extern void pte_free(struct mm_struct *mm, struct page *pte);
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extern pgtable_t pgtable_alloc_one(struct mm_struct *mm, unsigned long address,
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int order);
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extern void pgtable_free(struct mm_struct *mm, struct page *pte, int order);
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static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
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unsigned long address)
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{
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return pgtable_alloc_one(mm, address, L2_USER_PGTABLE_ORDER);
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}
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static inline void pte_free(struct mm_struct *mm, struct page *pte)
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{
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pgtable_free(mm, pte, L2_USER_PGTABLE_ORDER);
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}
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#define pmd_pgtable(pmd) pmd_page(pmd)
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@@ -85,8 +97,13 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
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pte_free(mm, virt_to_page(pte));
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}
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extern void __pte_free_tlb(struct mmu_gather *tlb, struct page *pte,
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unsigned long address);
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extern void __pgtable_free_tlb(struct mmu_gather *tlb, struct page *pte,
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unsigned long address, int order);
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static inline void __pte_free_tlb(struct mmu_gather *tlb, struct page *pte,
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unsigned long address)
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{
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__pgtable_free_tlb(tlb, pte, address, L2_USER_PGTABLE_ORDER);
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}
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#define check_pgt_cache() do { } while (0)
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@@ -104,19 +121,44 @@ void shatter_pmd(pmd_t *pmd);
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void shatter_huge_page(unsigned long addr);
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#ifdef __tilegx__
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/* We share a single page allocator for both L1 and L2 page tables. */
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#if HV_L1_SIZE != HV_L2_SIZE
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# error Rework assumption that L1 and L2 page tables are same size.
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#endif
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#define L1_USER_PGTABLE_ORDER L2_USER_PGTABLE_ORDER
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#define pud_populate(mm, pud, pmd) \
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pmd_populate_kernel((mm), (pmd_t *)(pud), (pte_t *)(pmd))
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#define pmd_alloc_one(mm, addr) \
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((pmd_t *)page_to_virt(pte_alloc_one((mm), (addr))))
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#define pmd_free(mm, pmdp) \
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pte_free((mm), virt_to_page(pmdp))
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#define __pmd_free_tlb(tlb, pmdp, address) \
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__pte_free_tlb((tlb), virt_to_page(pmdp), (address))
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/* Bits for the size of the L1 (intermediate) page table. */
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#define L1_KERNEL_PGTABLE_SHIFT _HV_LOG2_L1_SIZE(HPAGE_SHIFT)
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/* How big is a kernel L2 page table? */
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#define L1_KERNEL_PGTABLE_SIZE (1UL << L1_KERNEL_PGTABLE_SHIFT)
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/* We currently allocate L1 page tables by page. */
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#if L1_KERNEL_PGTABLE_SHIFT < PAGE_SHIFT
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#define L1_USER_PGTABLE_SHIFT PAGE_SHIFT
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#else
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#define L1_USER_PGTABLE_SHIFT L1_KERNEL_PGTABLE_SHIFT
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#endif
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/* How many pages do we need, as an "order", for an L1 page table? */
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#define L1_USER_PGTABLE_ORDER (L1_USER_PGTABLE_SHIFT - PAGE_SHIFT)
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static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
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{
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struct page *p = pgtable_alloc_one(mm, address, L1_USER_PGTABLE_ORDER);
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return (pmd_t *)page_to_virt(p);
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}
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static inline void pmd_free(struct mm_struct *mm, pmd_t *pmdp)
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{
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pgtable_free(mm, virt_to_page(pmdp), L1_USER_PGTABLE_ORDER);
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}
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static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
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unsigned long address)
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{
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__pgtable_free_tlb(tlb, virt_to_page(pmdp), address,
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L1_USER_PGTABLE_ORDER);
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}
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#endif /* __tilegx__ */
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#endif /* _ASM_TILE_PGALLOC_H */
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@@ -27,8 +27,10 @@
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#include <linux/slab.h>
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#include <linux/list.h>
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#include <linux/spinlock.h>
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#include <linux/pfn.h>
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#include <asm/processor.h>
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#include <asm/fixmap.h>
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#include <asm/page.h>
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struct mm_struct;
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struct vm_area_struct;
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@@ -162,7 +164,7 @@ extern void set_page_homes(void);
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(pgprot_t) { ((oldprot).val & ~_PAGE_ALL) | (newprot).val }
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/* Just setting the PFN to zero suffices. */
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#define pte_pgprot(x) hv_pte_set_pfn((x), 0)
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#define pte_pgprot(x) hv_pte_set_pa((x), 0)
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/*
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* For PTEs and PDEs, we must clear the Present bit first when
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@@ -262,7 +264,7 @@ static inline int pte_none(pte_t pte)
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static inline unsigned long pte_pfn(pte_t pte)
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{
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return hv_pte_get_pfn(pte);
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return PFN_DOWN(hv_pte_get_pa(pte));
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}
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/* Set or get the remote cache cpu in a pgprot with remote caching. */
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@@ -271,7 +273,7 @@ extern int get_remote_cache_cpu(pgprot_t prot);
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static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
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{
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return hv_pte_set_pfn(prot, pfn);
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return hv_pte_set_pa(prot, PFN_PHYS(pfn));
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}
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/* Support for priority mappings. */
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@@ -471,7 +473,7 @@ static inline unsigned long pmd_page_vaddr(pmd_t pmd)
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* OK for pte_lockptr(), since we just end up with potentially one
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* lock being used for several pte_t arrays.
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*/
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#define pmd_page(pmd) pfn_to_page(HV_PTFN_TO_PFN(pmd_ptfn(pmd)))
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#define pmd_page(pmd) pfn_to_page(PFN_DOWN(HV_PTFN_TO_CPA(pmd_ptfn(pmd))))
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static inline void pmd_clear(pmd_t *pmdp)
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{
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@@ -20,11 +20,12 @@
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* The level-1 index is defined by the huge page size. A PGD is composed
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* of PTRS_PER_PGD pgd_t's and is the top level of the page table.
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*/
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#define PGDIR_SHIFT HV_LOG2_PAGE_SIZE_LARGE
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#define PGDIR_SIZE HV_PAGE_SIZE_LARGE
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#define PGDIR_SHIFT HPAGE_SHIFT
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#define PGDIR_SIZE HPAGE_SIZE
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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#define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
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#define SIZEOF_PGD (PTRS_PER_PGD * sizeof(pgd_t))
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#define PTRS_PER_PGD _HV_L1_ENTRIES(HPAGE_SHIFT)
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#define PGD_INDEX(va) _HV_L1_INDEX(va, HPAGE_SHIFT)
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#define SIZEOF_PGD _HV_L1_SIZE(HPAGE_SHIFT)
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/*
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* The level-2 index is defined by the difference between the huge
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@@ -33,8 +34,9 @@
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* Note that the hypervisor docs use PTE for what we call pte_t, so
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* this nomenclature is somewhat confusing.
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*/
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#define PTRS_PER_PTE (1 << (HV_LOG2_PAGE_SIZE_LARGE - HV_LOG2_PAGE_SIZE_SMALL))
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#define SIZEOF_PTE (PTRS_PER_PTE * sizeof(pte_t))
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#define PTRS_PER_PTE _HV_L2_ENTRIES(HPAGE_SHIFT, PAGE_SHIFT)
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#define PTE_INDEX(va) _HV_L2_INDEX(va, HPAGE_SHIFT, PAGE_SHIFT)
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#define SIZEOF_PTE _HV_L2_SIZE(HPAGE_SHIFT, PAGE_SHIFT)
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#ifndef __ASSEMBLY__
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@@ -21,17 +21,19 @@
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#define PGDIR_SIZE HV_L1_SPAN
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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#define PTRS_PER_PGD HV_L0_ENTRIES
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#define SIZEOF_PGD (PTRS_PER_PGD * sizeof(pgd_t))
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#define PGD_INDEX(va) HV_L0_INDEX(va)
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#define SIZEOF_PGD HV_L0_SIZE
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/*
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* The level-1 index is defined by the huge page size. A PMD is composed
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* of PTRS_PER_PMD pgd_t's and is the middle level of the page table.
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*/
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#define PMD_SHIFT HV_LOG2_PAGE_SIZE_LARGE
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#define PMD_SIZE HV_PAGE_SIZE_LARGE
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#define PMD_SHIFT HPAGE_SHIFT
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#define PMD_SIZE HPAGE_SIZE
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#define PMD_MASK (~(PMD_SIZE-1))
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#define PTRS_PER_PMD (1 << (PGDIR_SHIFT - PMD_SHIFT))
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#define SIZEOF_PMD (PTRS_PER_PMD * sizeof(pmd_t))
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#define PTRS_PER_PMD _HV_L1_ENTRIES(HPAGE_SHIFT)
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#define PMD_INDEX(va) _HV_L1_INDEX(va, HPAGE_SHIFT)
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#define SIZEOF_PMD _HV_L1_SIZE(HPAGE_SHIFT)
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/*
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* The level-2 index is defined by the difference between the huge
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@@ -40,17 +42,19 @@
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* Note that the hypervisor docs use PTE for what we call pte_t, so
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* this nomenclature is somewhat confusing.
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*/
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#define PTRS_PER_PTE (1 << (HV_LOG2_PAGE_SIZE_LARGE - HV_LOG2_PAGE_SIZE_SMALL))
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#define SIZEOF_PTE (PTRS_PER_PTE * sizeof(pte_t))
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#define PTRS_PER_PTE _HV_L2_ENTRIES(HPAGE_SHIFT, PAGE_SHIFT)
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#define PTE_INDEX(va) _HV_L2_INDEX(va, HPAGE_SHIFT, PAGE_SHIFT)
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#define SIZEOF_PTE _HV_L2_SIZE(HPAGE_SHIFT, PAGE_SHIFT)
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/*
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* Align the vmalloc area to an L2 page table, and leave a guard page
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* at the beginning and end. The vmalloc code also puts in an internal
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* Align the vmalloc area to an L2 page table. Omit guard pages at
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* the beginning and end for simplicity (particularly in the per-cpu
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* memory allocation code). The vmalloc code puts in an internal
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* guard page between each allocation.
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*/
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#define _VMALLOC_END HUGE_VMAP_BASE
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#define VMALLOC_END (_VMALLOC_END - PAGE_SIZE)
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#define VMALLOC_START (_VMALLOC_START + PAGE_SIZE)
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#define VMALLOC_END _VMALLOC_END
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#define VMALLOC_START _VMALLOC_START
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#define HUGE_VMAP_END (HUGE_VMAP_BASE + PGDIR_SIZE)
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@@ -98,7 +102,7 @@ static inline int pud_bad(pud_t pud)
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* A pud_t points to a pmd_t array. Since we can have multiple per
|
||||
* page, we don't have a one-to-one mapping of pud_t's to pages.
|
||||
*/
|
||||
#define pud_page(pud) pfn_to_page(HV_PTFN_TO_PFN(pud_ptfn(pud)))
|
||||
#define pud_page(pud) pfn_to_page(PFN_DOWN(HV_PTFN_TO_CPA(pud_ptfn(pud))))
|
||||
|
||||
static inline unsigned long pud_index(unsigned long address)
|
||||
{
|
||||
|
||||
Reference in New Issue
Block a user