mirror of
https://github.com/Dasharo/linux.git
synced 2026-03-06 15:25:10 -08:00
Merge tag 'drivers-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC driver updates from Arnd Bergmann:
"These are all the driver updates for SoC specific drivers. There are a
couple of subsystems with individual maintainers picking up their
patches here:
- The reset controller subsystem add support for a few new SoC
variants to existing drivers, along with other minor improvements
- The OP-TEE subsystem gets a driver for the ARM FF-A transport
- The memory controller subsystem has improvements for Tegra,
Mediatek, Renesas, Freescale and Broadcom specific drivers.
- The tegra cpuidle driver changes get merged through this tree this
time. There are only minor changes, but they depend on other tegra
driver updates here.
- The ep93xx platform finally moves to using the drivers/clk/
subsystem, moving the code out of arch/arm in the process. This
depends on a small sound driver change that is included here as
well.
- There are some minor updates for Qualcomm and Tegra specific
firmware drivers.
The other driver updates are mainly for drivers/soc, which contains a
mixture of vendor specific drivers that don't really fit elsewhere:
- Mediatek drivers gain more support for MT8192, with new support for
hw-mutex and mmsys routing, plus support for reset lines in the
mmsys driver.
- Qualcomm gains a new "sleep stats" driver, and support for the
"Generic Packet Router" in the APR driver.
- There is a new user interface for routing the UARTS on ASpeed BMCs,
something that apparently nobody else has needed so far.
- More drivers can now be built as loadable modules, in particular
for Broadcom and Samsung platforms.
- Lots of improvements to the TI sysc driver for better
suspend/resume support"
Finally, there are lots of minor cleanups and new device IDs for
amlogic, renesas, tegra, qualcomm, mediateka, samsung, imx,
layerscape, allwinner, broadcom, and omap"
* tag 'drivers-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (179 commits)
optee: Fix spelling mistake "reclain" -> "reclaim"
Revert "firmware: qcom: scm: Add support for MC boot address API"
qcom: spm: allow compile-testing
firmware: arm_ffa: Remove unused 'compat_version' variable
soc: samsung: exynos-chipid: add exynosautov9 SoC support
firmware: qcom: scm: Don't break compile test on non-ARM platforms
soc: qcom: smp2p: Add of_node_put() before goto
soc: qcom: apr: Add of_node_put() before return
soc: qcom: qcom_stats: Fix client votes offset
soc: qcom: rpmhpd: fix sm8350_mxc's peer domain
dt-bindings: arm: cpus: Document qcom,msm8916-smp enable-method
ARM: qcom: Add qcom,msm8916-smp enable-method identical to MSM8226
firmware: qcom: scm: Add support for MC boot address API
soc: qcom: spm: Add 8916 SPM register data
dt-bindings: soc: qcom: spm: Document qcom,msm8916-saw2-v3.0-cpu
soc: qcom: socinfo: Add PM8150C and SMB2351 models
firmware: qcom_scm: Fix error retval in __qcom_scm_is_call_available()
soc: aspeed: Add UART routing support
soc: fsl: dpio: rename the enqueue descriptor variable
soc: fsl: dpio: use an explicit NULL instead of 0
...
This commit is contained in:
Linus Torvalds
@@ -99,7 +99,7 @@ config ARM_MVEBU_V7_CPUIDLE
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config ARM_TEGRA_CPUIDLE
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bool "CPU Idle Driver for NVIDIA Tegra SoCs"
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depends on ARCH_TEGRA && !ARM64
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depends on (ARCH_TEGRA || COMPILE_TEST) && !ARM64 && MMU
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select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
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select ARM_CPU_SUSPEND
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help
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@@ -112,6 +112,7 @@ config ARM_QCOM_SPM_CPUIDLE
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select CPU_IDLE_MULTIPLE_DRIVERS
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select DT_IDLE_STATES
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select QCOM_SCM
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select QCOM_SPM
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help
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Select this to enable cpuidle for Qualcomm processors.
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The Subsystem Power Manager (SPM) controls low power modes for the
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@@ -18,158 +18,18 @@
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#include <linux/cpuidle.h>
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#include <linux/cpu_pm.h>
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#include <linux/qcom_scm.h>
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#include <soc/qcom/spm.h>
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#include <asm/proc-fns.h>
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#include <asm/suspend.h>
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#include "dt_idle_states.h"
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#define MAX_PMIC_DATA 2
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#define MAX_SEQ_DATA 64
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#define SPM_CTL_INDEX 0x7f
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#define SPM_CTL_INDEX_SHIFT 4
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#define SPM_CTL_EN BIT(0)
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enum pm_sleep_mode {
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PM_SLEEP_MODE_STBY,
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PM_SLEEP_MODE_RET,
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PM_SLEEP_MODE_SPC,
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PM_SLEEP_MODE_PC,
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PM_SLEEP_MODE_NR,
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};
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enum spm_reg {
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SPM_REG_CFG,
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SPM_REG_SPM_CTL,
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SPM_REG_DLY,
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SPM_REG_PMIC_DLY,
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SPM_REG_PMIC_DATA_0,
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SPM_REG_PMIC_DATA_1,
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SPM_REG_VCTL,
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SPM_REG_SEQ_ENTRY,
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SPM_REG_SPM_STS,
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SPM_REG_PMIC_STS,
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SPM_REG_NR,
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};
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struct spm_reg_data {
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const u8 *reg_offset;
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u32 spm_cfg;
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u32 spm_dly;
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u32 pmic_dly;
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u32 pmic_data[MAX_PMIC_DATA];
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u8 seq[MAX_SEQ_DATA];
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u8 start_index[PM_SLEEP_MODE_NR];
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};
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struct spm_driver_data {
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struct cpuidle_qcom_spm_data {
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struct cpuidle_driver cpuidle_driver;
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void __iomem *reg_base;
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const struct spm_reg_data *reg_data;
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struct spm_driver_data *spm;
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};
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static const u8 spm_reg_offset_v2_1[SPM_REG_NR] = {
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[SPM_REG_CFG] = 0x08,
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[SPM_REG_SPM_CTL] = 0x30,
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[SPM_REG_DLY] = 0x34,
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[SPM_REG_SEQ_ENTRY] = 0x80,
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};
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/* SPM register data for 8974, 8084 */
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static const struct spm_reg_data spm_reg_8974_8084_cpu = {
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.reg_offset = spm_reg_offset_v2_1,
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.spm_cfg = 0x1,
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.spm_dly = 0x3C102800,
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.seq = { 0x03, 0x0B, 0x0F, 0x00, 0x20, 0x80, 0x10, 0xE8, 0x5B, 0x03,
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0x3B, 0xE8, 0x5B, 0x82, 0x10, 0x0B, 0x30, 0x06, 0x26, 0x30,
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0x0F },
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 3,
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};
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/* SPM register data for 8226 */
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static const struct spm_reg_data spm_reg_8226_cpu = {
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.reg_offset = spm_reg_offset_v2_1,
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.spm_cfg = 0x0,
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.spm_dly = 0x3C102800,
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.seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90,
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0x5B, 0x60, 0x03, 0x60, 0x3B, 0x76, 0x76, 0x0B, 0x94, 0x5B,
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0x80, 0x10, 0x26, 0x30, 0x0F },
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 5,
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};
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static const u8 spm_reg_offset_v1_1[SPM_REG_NR] = {
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[SPM_REG_CFG] = 0x08,
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[SPM_REG_SPM_CTL] = 0x20,
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[SPM_REG_PMIC_DLY] = 0x24,
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[SPM_REG_PMIC_DATA_0] = 0x28,
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[SPM_REG_PMIC_DATA_1] = 0x2C,
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[SPM_REG_SEQ_ENTRY] = 0x80,
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};
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/* SPM register data for 8064 */
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static const struct spm_reg_data spm_reg_8064_cpu = {
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.reg_offset = spm_reg_offset_v1_1,
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.spm_cfg = 0x1F,
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.pmic_dly = 0x02020004,
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.pmic_data[0] = 0x0084009C,
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.pmic_data[1] = 0x00A4001C,
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.seq = { 0x03, 0x0F, 0x00, 0x24, 0x54, 0x10, 0x09, 0x03, 0x01,
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0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F },
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 2,
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};
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static inline void spm_register_write(struct spm_driver_data *drv,
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enum spm_reg reg, u32 val)
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{
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if (drv->reg_data->reg_offset[reg])
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writel_relaxed(val, drv->reg_base +
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drv->reg_data->reg_offset[reg]);
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}
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/* Ensure a guaranteed write, before return */
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static inline void spm_register_write_sync(struct spm_driver_data *drv,
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enum spm_reg reg, u32 val)
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{
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u32 ret;
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if (!drv->reg_data->reg_offset[reg])
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return;
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do {
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writel_relaxed(val, drv->reg_base +
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drv->reg_data->reg_offset[reg]);
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ret = readl_relaxed(drv->reg_base +
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drv->reg_data->reg_offset[reg]);
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if (ret == val)
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break;
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cpu_relax();
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} while (1);
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}
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static inline u32 spm_register_read(struct spm_driver_data *drv,
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enum spm_reg reg)
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{
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return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]);
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}
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static void spm_set_low_power_mode(struct spm_driver_data *drv,
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enum pm_sleep_mode mode)
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{
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u32 start_index;
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u32 ctl_val;
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start_index = drv->reg_data->start_index[mode];
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ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL);
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ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT);
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ctl_val |= start_index << SPM_CTL_INDEX_SHIFT;
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ctl_val |= SPM_CTL_EN;
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spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val);
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}
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static int qcom_pm_collapse(unsigned long int unused)
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{
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qcom_scm_cpu_power_down(QCOM_SCM_CPU_PWR_DOWN_L2_ON);
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@@ -201,10 +61,10 @@ static int qcom_cpu_spc(struct spm_driver_data *drv)
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static int spm_enter_idle_state(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int idx)
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{
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struct spm_driver_data *data = container_of(drv, struct spm_driver_data,
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cpuidle_driver);
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struct cpuidle_qcom_spm_data *data = container_of(drv, struct cpuidle_qcom_spm_data,
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cpuidle_driver);
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return CPU_PM_CPU_IDLE_ENTER_PARAM(qcom_cpu_spc, idx, data);
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return CPU_PM_CPU_IDLE_ENTER_PARAM(qcom_cpu_spc, idx, data->spm);
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}
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static struct cpuidle_driver qcom_spm_idle_driver = {
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@@ -225,134 +85,92 @@ static const struct of_device_id qcom_idle_state_match[] = {
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{ },
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};
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static int spm_cpuidle_init(struct cpuidle_driver *drv, int cpu)
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static int spm_cpuidle_register(struct device *cpuidle_dev, int cpu)
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{
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struct platform_device *pdev = NULL;
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struct device_node *cpu_node, *saw_node;
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struct cpuidle_qcom_spm_data *data = NULL;
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int ret;
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memcpy(drv, &qcom_spm_idle_driver, sizeof(*drv));
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drv->cpumask = (struct cpumask *)cpumask_of(cpu);
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cpu_node = of_cpu_device_node_get(cpu);
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if (!cpu_node)
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return -ENODEV;
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/* Parse idle states from device tree */
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ret = dt_init_idle_driver(drv, qcom_idle_state_match, 1);
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saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
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if (!saw_node)
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return -ENODEV;
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pdev = of_find_device_by_node(saw_node);
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of_node_put(saw_node);
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of_node_put(cpu_node);
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if (!pdev)
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return -ENODEV;
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data = devm_kzalloc(cpuidle_dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->spm = dev_get_drvdata(&pdev->dev);
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if (!data->spm)
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return -EINVAL;
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data->cpuidle_driver = qcom_spm_idle_driver;
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data->cpuidle_driver.cpumask = (struct cpumask *)cpumask_of(cpu);
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ret = dt_init_idle_driver(&data->cpuidle_driver,
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qcom_idle_state_match, 1);
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if (ret <= 0)
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return ret ? : -ENODEV;
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/* We have atleast one power down mode */
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return qcom_scm_set_warm_boot_addr(cpu_resume_arm, drv->cpumask);
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ret = qcom_scm_set_warm_boot_addr(cpu_resume_arm, cpumask_of(cpu));
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if (ret)
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return ret;
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return cpuidle_register(&data->cpuidle_driver, NULL);
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}
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static struct spm_driver_data *spm_get_drv(struct platform_device *pdev,
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int *spm_cpu)
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static int spm_cpuidle_drv_probe(struct platform_device *pdev)
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{
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struct spm_driver_data *drv = NULL;
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struct device_node *cpu_node, *saw_node;
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int cpu;
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bool found = 0;
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for_each_possible_cpu(cpu) {
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cpu_node = of_cpu_device_node_get(cpu);
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if (!cpu_node)
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continue;
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saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
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found = (saw_node == pdev->dev.of_node);
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of_node_put(saw_node);
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of_node_put(cpu_node);
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if (found)
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break;
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}
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if (found) {
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drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
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if (drv)
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*spm_cpu = cpu;
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}
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return drv;
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}
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static const struct of_device_id spm_match_table[] = {
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{ .compatible = "qcom,msm8226-saw2-v2.1-cpu",
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.data = &spm_reg_8226_cpu },
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{ .compatible = "qcom,msm8974-saw2-v2.1-cpu",
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.data = &spm_reg_8974_8084_cpu },
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{ .compatible = "qcom,apq8084-saw2-v2.1-cpu",
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.data = &spm_reg_8974_8084_cpu },
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{ .compatible = "qcom,apq8064-saw2-v1.1-cpu",
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.data = &spm_reg_8064_cpu },
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{ },
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};
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static int spm_dev_probe(struct platform_device *pdev)
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{
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struct spm_driver_data *drv;
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struct resource *res;
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const struct of_device_id *match_id;
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void __iomem *addr;
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int cpu, ret;
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if (!qcom_scm_is_available())
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return -EPROBE_DEFER;
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drv = spm_get_drv(pdev, &cpu);
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if (!drv)
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return -EINVAL;
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platform_set_drvdata(pdev, drv);
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for_each_possible_cpu(cpu) {
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ret = spm_cpuidle_register(&pdev->dev, cpu);
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if (ret && ret != -ENODEV) {
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dev_err(&pdev->dev,
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"Cannot register for CPU%d: %d\n", cpu, ret);
|
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}
|
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}
|
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
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drv->reg_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(drv->reg_base))
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return PTR_ERR(drv->reg_base);
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|
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match_id = of_match_node(spm_match_table, pdev->dev.of_node);
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if (!match_id)
|
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return -ENODEV;
|
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|
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drv->reg_data = match_id->data;
|
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|
||||
ret = spm_cpuidle_init(&drv->cpuidle_driver, cpu);
|
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if (ret)
|
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return ret;
|
||||
|
||||
/* Write the SPM sequences first.. */
|
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addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY];
|
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__iowrite32_copy(addr, drv->reg_data->seq,
|
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ARRAY_SIZE(drv->reg_data->seq) / 4);
|
||||
|
||||
/*
|
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* ..and then the control registers.
|
||||
* On some SoC if the control registers are written first and if the
|
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* CPU was held in reset, the reset signal could trigger the SPM state
|
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* machine, before the sequences are completely written.
|
||||
*/
|
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spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg);
|
||||
spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly);
|
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spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly);
|
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spm_register_write(drv, SPM_REG_PMIC_DATA_0,
|
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drv->reg_data->pmic_data[0]);
|
||||
spm_register_write(drv, SPM_REG_PMIC_DATA_1,
|
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drv->reg_data->pmic_data[1]);
|
||||
|
||||
/* Set up Standby as the default low power mode */
|
||||
spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
|
||||
|
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return cpuidle_register(&drv->cpuidle_driver, NULL);
|
||||
}
|
||||
|
||||
static int spm_dev_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct spm_driver_data *drv = platform_get_drvdata(pdev);
|
||||
|
||||
cpuidle_unregister(&drv->cpuidle_driver);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver spm_driver = {
|
||||
.probe = spm_dev_probe,
|
||||
.remove = spm_dev_remove,
|
||||
static struct platform_driver spm_cpuidle_driver = {
|
||||
.probe = spm_cpuidle_drv_probe,
|
||||
.driver = {
|
||||
.name = "saw",
|
||||
.of_match_table = spm_match_table,
|
||||
.name = "qcom-spm-cpuidle",
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(spm_driver);
|
||||
static int __init qcom_spm_cpuidle_init(void)
|
||||
{
|
||||
struct platform_device *pdev;
|
||||
int ret;
|
||||
|
||||
ret = platform_driver_register(&spm_cpuidle_driver);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pdev = platform_device_register_simple("qcom-spm-cpuidle",
|
||||
-1, NULL, 0);
|
||||
if (IS_ERR(pdev)) {
|
||||
platform_driver_unregister(&spm_cpuidle_driver);
|
||||
return PTR_ERR(pdev);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
device_initcall(qcom_spm_cpuidle_init);
|
||||
|
||||
@@ -337,6 +337,9 @@ static void tegra_cpuidle_setup_tegra114_c7_state(void)
|
||||
|
||||
static int tegra_cpuidle_probe(struct platform_device *pdev)
|
||||
{
|
||||
if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NOT_READY)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
/* LP2 could be disabled in device-tree */
|
||||
if (tegra_pmc_get_suspend_mode() < TEGRA_SUSPEND_LP2)
|
||||
tegra_cpuidle_disable_state(TEGRA_CC6);
|
||||
|
||||
Reference in New Issue
Block a user