mirror of
https://github.com/Dasharo/linux.git
synced 2026-03-06 15:25:10 -08:00
Merge branches 'clk-microchip', 'clk-xilinx', 'clk-allwinner', 'clk-imx' and 'clk-qcom' into clk-next
* clk-microchip:
clk: at91: sama7d65: add sama7d65 pmc driver
dt-bindings: clock: Add SAMA7D65 PMC compatible string
dt-bindings: clocks: atmel,at91sam9x5-sckc: add sama7d65
clk: at91: sckc: Use SCKC_{TD, MD}_SLCK IDs for clk32k clocks
dt-bindings: clk: at91: Add clock IDs for the slow clock controller
* clk-xilinx:
clk: clocking-wizard: calculate dividers fractional parts
dt-bindings: clock: xilinx: Add reset GPIO for VCU
dt-bindings: clock: xilinx: Convert VCU bindings to dtschema
* clk-allwinner:
clk: sunxi-ng: h616: Reparent CPU clock during frequency changes
clk: sunxi-ng: a64: stop force-selecting PLL-MIPI as TCON0 parent
clk: sunxi-ng: a64: drop redundant CLK_PLL_VIDEO0_2X and CLK_PLL_MIPI
dt-bindings: clock: sunxi: Export PLL_VIDEO_2X and PLL_MIPI
* clk-imx:
clk: imx: Apply some clks only for i.MX93
arm64: dts: imx93: Use IMX93_CLK_SPDIF_IPG as SPDIF IPG clock
clk: imx93: Add IMX93_CLK_SPDIF_IPG clock
dt-bindings: clock: imx93: Add SPDIF IPG clk
clk: imx: pll14xx: Add 208 MHz and 416 MHz entries for PLL1416x
clk: imx8mp: Fix clkout1/2 support
* clk-qcom: (63 commits)
clk: qcom: Select CLK_X1E80100_GCC in config CLK_X1P42100_GPUCC
dt-bindings: clock: move qcom,x1e80100-camcc to its own file
clk: qcom: smd-rpm: Add clocks for MSM8940
dt-bindings: clock: qcom,rpmcc: Add MSM8940 compatible
clk: qcom: smd-rpm: Add clocks for MSM8937
dt-bindings: clock: qcom,rpmcc: Add MSM8937 compatible
clk: qcom: ipq5424: Use icc-clk for enabling NoC related clocks
dt-bindings: interconnect: Add Qualcomm IPQ5424 support
clk: qcom: Add SM6115 LPASSCC
dt-bindings: clock: Add Qualcomm SM6115 LPASS clock controller
clk: qcom: gcc-sdm845: Do not use shared clk_ops for QUPs
clk: qcom: gcc-sdm845: Add general purpose clock ops
clk: qcom: clk-rcg2: split __clk_rcg2_configure function
clk: qcom: clk-rcg2: document calc_rate function
clk: qcom: gcc-x1e80100: Do not turn off usb_2 controller GDSC
clk: qcom: ipq5424: add gcc_xo_clk
dt-bindings: clock: qcom: gcc-ipq5424: add gcc_xo_clk macro
dt-bindings: clock: qcom: gcc-ipq5424: remove apss_dbg clock macro
clk: qcom: ipq5424: remove apss_dbg clock
dt-bindings: clock: qcom,sdm845-camcc: add sdm670 compatible
...
This commit is contained in:
Stephen Boyd
@@ -42,6 +42,10 @@
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#define PMC_PLLADIV2 (PMC_MAIN + 11)
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#define PMC_LVDSPLL (PMC_MAIN + 12)
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/* SAMA7D65 */
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#define PMC_MCK3 (PMC_MAIN + 13)
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#define PMC_MCK5 (PMC_MAIN + 14)
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#ifndef AT91_PMC_MOSCS
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#define AT91_PMC_MOSCS 0 /* MOSCS Flag */
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#define AT91_PMC_LOCKA 1 /* PLLA Lock */
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@@ -55,4 +59,8 @@
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#define AT91_PMC_GCKRDY 24 /* Generated Clocks */
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#endif
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/* Slow clock. */
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#define SCKC_MD_SLCK 0
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#define SCKC_TD_SLCK 1
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#endif
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@@ -209,5 +209,6 @@
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#define IMX91_CLK_ENET2_REGULAR 204
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#define IMX91_CLK_ENET2_REGULAR_GATE 205
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#define IMX91_CLK_ENET1_QOS_TSN_GATE 206
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#define IMX93_CLK_SPDIF_IPG 207
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#endif
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@@ -0,0 +1,22 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
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#define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
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/* CMN PLL core clock. */
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#define CMN_PLL_CLK 0
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/* The output clocks from CMN PLL of IPQ9574. */
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#define XO_24MHZ_CLK 1
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#define SLEEP_32KHZ_CLK 2
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#define PCS_31P25MHZ_CLK 3
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#define NSS_1200MHZ_CLK 4
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#define PPE_353MHZ_CLK 5
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#define ETH0_50MHZ_CLK 6
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#define ETH1_50MHZ_CLK 7
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#define ETH2_50MHZ_CLK 8
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#define ETH_25MHZ_CLK 9
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#endif
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@@ -12,7 +12,6 @@
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#define GPLL2 2
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#define GPLL2_OUT_MAIN 3
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#define GCC_SLEEP_CLK_SRC 4
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#define GCC_APSS_DBG_CLK 5
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#define GCC_USB0_EUD_AT_CLK 6
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#define GCC_PCIE0_AXI_M_CLK_SRC 7
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#define GCC_PCIE0_AXI_M_CLK 8
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@@ -152,5 +151,6 @@
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#define GCC_PCIE3_RCHNG_CLK_SRC 142
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#define GCC_PCIE3_RCHNG_CLK 143
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#define GCC_IM_SLEEP_CLK 144
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#define GCC_XO_CLK 145
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#endif
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@@ -133,5 +133,7 @@
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#define VCAP_CLK 124
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#define VCAP_NPL_CLK 125
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#define PLL15 126
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#define DSI2_PIXEL_LVDS_SRC 127
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#define LVDS_CLK 128
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#endif
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@@ -0,0 +1,211 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS615_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_QCS615_H
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/* GCC clocks */
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#define GPLL0_OUT_AUX2_DIV 0
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#define GPLL3_OUT_AUX2_DIV 1
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#define GPLL0 2
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#define GPLL3 3
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#define GPLL4 4
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#define GPLL6 5
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#define GPLL6_OUT_MAIN 6
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#define GPLL7 7
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#define GPLL8 8
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#define GPLL8_OUT_MAIN 9
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#define GCC_AGGRE_UFS_PHY_AXI_CLK 10
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#define GCC_AGGRE_USB2_SEC_AXI_CLK 11
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#define GCC_AGGRE_USB3_PRIM_AXI_CLK 12
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#define GCC_AHB2PHY_EAST_CLK 13
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#define GCC_AHB2PHY_WEST_CLK 14
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#define GCC_BOOT_ROM_AHB_CLK 15
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#define GCC_CAMERA_AHB_CLK 16
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#define GCC_CAMERA_HF_AXI_CLK 17
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#define GCC_CAMERA_XO_CLK 18
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#define GCC_CE1_AHB_CLK 19
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#define GCC_CE1_AXI_CLK 20
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#define GCC_CE1_CLK 21
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#define GCC_CFG_NOC_USB2_SEC_AXI_CLK 22
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 23
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#define GCC_CPUSS_AHB_CLK 24
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#define GCC_CPUSS_AHB_CLK_SRC 25
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#define GCC_CPUSS_GNOC_CLK 26
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#define GCC_DDRSS_GPU_AXI_CLK 27
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#define GCC_DISP_AHB_CLK 28
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#define GCC_DISP_GPLL0_DIV_CLK_SRC 29
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#define GCC_DISP_HF_AXI_CLK 30
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#define GCC_DISP_XO_CLK 31
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#define GCC_EMAC_AXI_CLK 32
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#define GCC_EMAC_PTP_CLK 33
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#define GCC_EMAC_PTP_CLK_SRC 34
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#define GCC_EMAC_RGMII_CLK 35
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#define GCC_EMAC_RGMII_CLK_SRC 36
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#define GCC_EMAC_SLV_AHB_CLK 37
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#define GCC_GP1_CLK 38
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#define GCC_GP1_CLK_SRC 39
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#define GCC_GP2_CLK 40
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#define GCC_GP2_CLK_SRC 41
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#define GCC_GP3_CLK 42
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#define GCC_GP3_CLK_SRC 43
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#define GCC_GPU_CFG_AHB_CLK 44
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#define GCC_GPU_GPLL0_CLK_SRC 45
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 46
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#define GCC_GPU_IREF_CLK 47
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#define GCC_GPU_MEMNOC_GFX_CLK 48
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#define GCC_GPU_SNOC_DVM_GFX_CLK 49
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#define GCC_PCIE0_PHY_REFGEN_CLK 50
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#define GCC_PCIE_0_AUX_CLK 51
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#define GCC_PCIE_0_AUX_CLK_SRC 52
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#define GCC_PCIE_0_CFG_AHB_CLK 53
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#define GCC_PCIE_0_CLKREF_CLK 54
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#define GCC_PCIE_0_MSTR_AXI_CLK 55
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#define GCC_PCIE_0_PIPE_CLK 56
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#define GCC_PCIE_0_SLV_AXI_CLK 57
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#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 58
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#define GCC_PCIE_PHY_AUX_CLK 59
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#define GCC_PCIE_PHY_REFGEN_CLK_SRC 60
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#define GCC_PDM2_CLK 61
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#define GCC_PDM2_CLK_SRC 62
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#define GCC_PDM_AHB_CLK 63
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#define GCC_PDM_XO4_CLK 64
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#define GCC_PRNG_AHB_CLK 65
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#define GCC_QMIP_CAMERA_NRT_AHB_CLK 66
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#define GCC_QMIP_DISP_AHB_CLK 67
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#define GCC_QMIP_PCIE_AHB_CLK 68
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#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 69
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#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 70
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#define GCC_QSPI_CORE_CLK 71
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#define GCC_QSPI_CORE_CLK_SRC 72
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 73
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#define GCC_QUPV3_WRAP0_CORE_CLK 74
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#define GCC_QUPV3_WRAP0_S0_CLK 75
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 76
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#define GCC_QUPV3_WRAP0_S1_CLK 77
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 78
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#define GCC_QUPV3_WRAP0_S2_CLK 79
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 80
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#define GCC_QUPV3_WRAP0_S3_CLK 81
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 82
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#define GCC_QUPV3_WRAP0_S4_CLK 83
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 84
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#define GCC_QUPV3_WRAP0_S5_CLK 85
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 86
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#define GCC_QUPV3_WRAP1_CORE_2X_CLK 87
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#define GCC_QUPV3_WRAP1_CORE_CLK 88
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#define GCC_QUPV3_WRAP1_S0_CLK 89
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 90
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#define GCC_QUPV3_WRAP1_S1_CLK 91
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 92
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#define GCC_QUPV3_WRAP1_S2_CLK 93
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 94
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#define GCC_QUPV3_WRAP1_S3_CLK 95
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 96
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#define GCC_QUPV3_WRAP1_S4_CLK 97
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 98
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#define GCC_QUPV3_WRAP1_S5_CLK 99
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 100
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 101
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 102
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#define GCC_QUPV3_WRAP_1_M_AHB_CLK 103
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#define GCC_QUPV3_WRAP_1_S_AHB_CLK 104
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#define GCC_RX1_USB2_CLKREF_CLK 105
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#define GCC_RX3_USB2_CLKREF_CLK 106
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#define GCC_SDCC1_AHB_CLK 107
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#define GCC_SDCC1_APPS_CLK 108
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#define GCC_SDCC1_APPS_CLK_SRC 109
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#define GCC_SDCC1_ICE_CORE_CLK 110
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#define GCC_SDCC1_ICE_CORE_CLK_SRC 111
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#define GCC_SDCC2_AHB_CLK 112
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#define GCC_SDCC2_APPS_CLK 113
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#define GCC_SDCC2_APPS_CLK_SRC 114
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#define GCC_SDR_CORE_CLK 115
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#define GCC_SDR_CSR_HCLK 116
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#define GCC_SDR_PRI_MI2S_CLK 117
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#define GCC_SDR_SEC_MI2S_CLK 118
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#define GCC_SDR_WR0_MEM_CLK 119
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#define GCC_SDR_WR1_MEM_CLK 120
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#define GCC_SDR_WR2_MEM_CLK 121
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#define GCC_SYS_NOC_CPUSS_AHB_CLK 122
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#define GCC_UFS_CARD_CLKREF_CLK 123
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#define GCC_UFS_MEM_CLKREF_CLK 124
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#define GCC_UFS_PHY_AHB_CLK 125
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#define GCC_UFS_PHY_AXI_CLK 126
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#define GCC_UFS_PHY_AXI_CLK_SRC 127
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#define GCC_UFS_PHY_ICE_CORE_CLK 128
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#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 129
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#define GCC_UFS_PHY_PHY_AUX_CLK 130
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#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 131
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 132
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 133
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK 134
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 135
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#define GCC_USB20_SEC_MASTER_CLK 136
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#define GCC_USB20_SEC_MASTER_CLK_SRC 137
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#define GCC_USB20_SEC_MOCK_UTMI_CLK 138
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#define GCC_USB20_SEC_MOCK_UTMI_CLK_SRC 139
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#define GCC_USB20_SEC_SLEEP_CLK 140
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#define GCC_USB2_PRIM_CLKREF_CLK 141
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#define GCC_USB2_SEC_CLKREF_CLK 142
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#define GCC_USB2_SEC_PHY_AUX_CLK 143
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#define GCC_USB2_SEC_PHY_AUX_CLK_SRC 144
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#define GCC_USB2_SEC_PHY_COM_AUX_CLK 145
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#define GCC_USB2_SEC_PHY_PIPE_CLK 146
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#define GCC_USB30_PRIM_MASTER_CLK 147
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 148
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 149
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 150
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#define GCC_USB30_PRIM_SLEEP_CLK 151
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#define GCC_USB3_PRIM_CLKREF_CLK 152
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#define GCC_USB3_PRIM_PHY_AUX_CLK 153
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 154
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 155
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 156
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#define GCC_USB3_SEC_CLKREF_CLK 157
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#define GCC_VIDEO_AHB_CLK 158
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#define GCC_VIDEO_AXI0_CLK 159
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#define GCC_VIDEO_XO_CLK 160
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#define GCC_VSENSOR_CLK_SRC 161
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#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 162
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#define GCC_UFS_PHY_AXI_HW_CTL_CLK 163
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#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 164
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#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 165
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#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 166
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/* GCC Resets */
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#define GCC_EMAC_BCR 0
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#define GCC_QUSB2PHY_PRIM_BCR 1
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#define GCC_QUSB2PHY_SEC_BCR 2
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#define GCC_USB30_PRIM_BCR 3
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#define GCC_USB2_PHY_SEC_BCR 4
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#define GCC_USB3_DP_PHY_SEC_BCR 5
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#define GCC_USB3PHY_PHY_SEC_BCR 6
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#define GCC_PCIE_0_BCR 7
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#define GCC_PCIE_0_PHY_BCR 8
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#define GCC_PCIE_PHY_BCR 9
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#define GCC_PCIE_PHY_COM_BCR 10
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#define GCC_UFS_PHY_BCR 11
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#define GCC_USB20_SEC_BCR 12
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#define GCC_USB3_PHY_PRIM_SP0_BCR 13
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#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 14
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#define GCC_SDCC1_BCR 15
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#define GCC_SDCC2_BCR 16
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/* GCC power domains */
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#define EMAC_GDSC 0
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#define PCIE_0_GDSC 1
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#define UFS_PHY_GDSC 2
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#define USB20_SEC_GDSC 3
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#define USB30_PRIM_GDSC 4
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#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 5
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#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 6
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#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 7
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#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 8
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#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 9
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#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 10
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#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11
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#endif
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@@ -0,0 +1,15 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023, Linaro Ltd.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SM6115_H
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#define _DT_BINDINGS_CLK_QCOM_LPASSCC_SM6115_H
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/* LPASS CC */
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#define LPASS_SWR_TX_CONFIG_CGCR 0
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/* LPASS_AUDIO CC */
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#define LPASS_AUDIO_SWR_RX_CGCR 0
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#endif
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@@ -0,0 +1,112 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
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/*
|
||||
* Copyright (c) 2022, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
* Copyright (c) 2024, Linaro Ltd.
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||||
*/
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#ifndef _DT_BINDINGS_CLK_QCOM_SM8750_DISP_CC_H
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#define _DT_BINDINGS_CLK_QCOM_SM8750_DISP_CC_H
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/* DISP_CC clocks */
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#define DISP_CC_ESYNC0_CLK 0
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||||
#define DISP_CC_ESYNC0_CLK_SRC 1
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#define DISP_CC_ESYNC1_CLK 2
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#define DISP_CC_ESYNC1_CLK_SRC 3
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#define DISP_CC_MDSS_ACCU_SHIFT_CLK 4
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#define DISP_CC_MDSS_AHB1_CLK 5
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#define DISP_CC_MDSS_AHB_CLK 6
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#define DISP_CC_MDSS_AHB_CLK_SRC 7
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#define DISP_CC_MDSS_BYTE0_CLK 8
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||||
#define DISP_CC_MDSS_BYTE0_CLK_SRC 9
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||||
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 10
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 11
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||||
#define DISP_CC_MDSS_BYTE1_CLK 12
|
||||
#define DISP_CC_MDSS_BYTE1_CLK_SRC 13
|
||||
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 14
|
||||
#define DISP_CC_MDSS_BYTE1_INTF_CLK 15
|
||||
#define DISP_CC_MDSS_DPTX0_AUX_CLK 16
|
||||
#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 17
|
||||
#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 18
|
||||
#define DISP_CC_MDSS_DPTX0_LINK_CLK 19
|
||||
#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 20
|
||||
#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 21
|
||||
#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 22
|
||||
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 23
|
||||
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 24
|
||||
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 25
|
||||
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 26
|
||||
#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 27
|
||||
#define DISP_CC_MDSS_DPTX1_AUX_CLK 28
|
||||
#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 29
|
||||
#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 30
|
||||
#define DISP_CC_MDSS_DPTX1_LINK_CLK 31
|
||||
#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 32
|
||||
#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 33
|
||||
#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 34
|
||||
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 35
|
||||
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 36
|
||||
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 37
|
||||
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 38
|
||||
#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 39
|
||||
#define DISP_CC_MDSS_DPTX2_AUX_CLK 40
|
||||
#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 41
|
||||
#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 42
|
||||
#define DISP_CC_MDSS_DPTX2_LINK_CLK 43
|
||||
#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 44
|
||||
#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 45
|
||||
#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 46
|
||||
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 47
|
||||
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 48
|
||||
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 49
|
||||
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 50
|
||||
#define DISP_CC_MDSS_DPTX3_AUX_CLK 51
|
||||
#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 52
|
||||
#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 53
|
||||
#define DISP_CC_MDSS_DPTX3_LINK_CLK 54
|
||||
#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 55
|
||||
#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 56
|
||||
#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 57
|
||||
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 58
|
||||
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 59
|
||||
#define DISP_CC_MDSS_ESC0_CLK 60
|
||||
#define DISP_CC_MDSS_ESC0_CLK_SRC 61
|
||||
#define DISP_CC_MDSS_ESC1_CLK 62
|
||||
#define DISP_CC_MDSS_ESC1_CLK_SRC 63
|
||||
#define DISP_CC_MDSS_MDP1_CLK 64
|
||||
#define DISP_CC_MDSS_MDP_CLK 65
|
||||
#define DISP_CC_MDSS_MDP_CLK_SRC 66
|
||||
#define DISP_CC_MDSS_MDP_LUT1_CLK 67
|
||||
#define DISP_CC_MDSS_MDP_LUT_CLK 68
|
||||
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 69
|
||||
#define DISP_CC_MDSS_PCLK0_CLK 70
|
||||
#define DISP_CC_MDSS_PCLK0_CLK_SRC 71
|
||||
#define DISP_CC_MDSS_PCLK1_CLK 72
|
||||
#define DISP_CC_MDSS_PCLK1_CLK_SRC 73
|
||||
#define DISP_CC_MDSS_PCLK2_CLK 74
|
||||
#define DISP_CC_MDSS_PCLK2_CLK_SRC 75
|
||||
#define DISP_CC_MDSS_RSCC_AHB_CLK 76
|
||||
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 77
|
||||
#define DISP_CC_MDSS_VSYNC1_CLK 78
|
||||
#define DISP_CC_MDSS_VSYNC_CLK 79
|
||||
#define DISP_CC_MDSS_VSYNC_CLK_SRC 80
|
||||
#define DISP_CC_OSC_CLK 81
|
||||
#define DISP_CC_OSC_CLK_SRC 82
|
||||
#define DISP_CC_PLL0 83
|
||||
#define DISP_CC_PLL1 84
|
||||
#define DISP_CC_PLL2 85
|
||||
#define DISP_CC_SLEEP_CLK 86
|
||||
#define DISP_CC_SLEEP_CLK_SRC 87
|
||||
#define DISP_CC_XO_CLK 88
|
||||
#define DISP_CC_XO_CLK_SRC 89
|
||||
|
||||
/* DISP_CC resets */
|
||||
#define DISP_CC_MDSS_CORE_BCR 0
|
||||
#define DISP_CC_MDSS_CORE_INT2_BCR 1
|
||||
#define DISP_CC_MDSS_RSCC_BCR 2
|
||||
|
||||
/* DISP_CC GDSCR */
|
||||
#define MDSS_GDSC 0
|
||||
#define MDSS_INT2_GDSC 1
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,226 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8750_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_GCC_SM8750_H
|
||||
|
||||
/* GCC clocks */
|
||||
#define GCC_AGGRE_NOC_PCIE_AXI_CLK 0
|
||||
#define GCC_AGGRE_UFS_PHY_AXI_CLK 1
|
||||
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 2
|
||||
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3
|
||||
#define GCC_BOOT_ROM_AHB_CLK 4
|
||||
#define GCC_CAM_BIST_MCLK_AHB_CLK 5
|
||||
#define GCC_CAMERA_AHB_CLK 6
|
||||
#define GCC_CAMERA_HF_AXI_CLK 7
|
||||
#define GCC_CAMERA_SF_AXI_CLK 8
|
||||
#define GCC_CAMERA_XO_CLK 9
|
||||
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 10
|
||||
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 11
|
||||
#define GCC_CNOC_PCIE_SF_AXI_CLK 12
|
||||
#define GCC_DDRSS_GPU_AXI_CLK 13
|
||||
#define GCC_DDRSS_PCIE_SF_QTB_CLK 14
|
||||
#define GCC_DISP_AHB_CLK 15
|
||||
#define GCC_DISP_HF_AXI_CLK 16
|
||||
#define GCC_EVA_AHB_CLK 17
|
||||
#define GCC_EVA_AXI0_CLK 18
|
||||
#define GCC_EVA_AXI0C_CLK 19
|
||||
#define GCC_EVA_XO_CLK 20
|
||||
#define GCC_GP1_CLK 21
|
||||
#define GCC_GP1_CLK_SRC 22
|
||||
#define GCC_GP2_CLK 23
|
||||
#define GCC_GP2_CLK_SRC 24
|
||||
#define GCC_GP3_CLK 25
|
||||
#define GCC_GP3_CLK_SRC 26
|
||||
#define GCC_GPLL0 27
|
||||
#define GCC_GPLL0_OUT_EVEN 28
|
||||
#define GCC_GPLL1 29
|
||||
#define GCC_GPLL4 30
|
||||
#define GCC_GPLL7 31
|
||||
#define GCC_GPLL9 32
|
||||
#define GCC_GPU_CFG_AHB_CLK 33
|
||||
#define GCC_GPU_GEMNOC_GFX_CLK 34
|
||||
#define GCC_GPU_GPLL0_CLK_SRC 35
|
||||
#define GCC_GPU_GPLL0_DIV_CLK_SRC 36
|
||||
#define GCC_PCIE_0_AUX_CLK 37
|
||||
#define GCC_PCIE_0_AUX_CLK_SRC 38
|
||||
#define GCC_PCIE_0_CFG_AHB_CLK 39
|
||||
#define GCC_PCIE_0_MSTR_AXI_CLK 40
|
||||
#define GCC_PCIE_0_PHY_RCHNG_CLK 41
|
||||
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 42
|
||||
#define GCC_PCIE_0_PIPE_CLK 43
|
||||
#define GCC_PCIE_0_PIPE_CLK_SRC 44
|
||||
#define GCC_PCIE_0_SLV_AXI_CLK 45
|
||||
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 46
|
||||
#define GCC_PCIE_RSCC_CFG_AHB_CLK 47
|
||||
#define GCC_PCIE_RSCC_XO_CLK 48
|
||||
#define GCC_PDM2_CLK 49
|
||||
#define GCC_PDM2_CLK_SRC 50
|
||||
#define GCC_PDM_AHB_CLK 51
|
||||
#define GCC_PDM_XO4_CLK 52
|
||||
#define GCC_QMIP_CAMERA_CMD_AHB_CLK 53
|
||||
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 54
|
||||
#define GCC_QMIP_CAMERA_RT_AHB_CLK 55
|
||||
#define GCC_QMIP_GPU_AHB_CLK 56
|
||||
#define GCC_QMIP_PCIE_AHB_CLK 57
|
||||
#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 58
|
||||
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 59
|
||||
#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 60
|
||||
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 61
|
||||
#define GCC_QUPV3_I2C_CORE_CLK 62
|
||||
#define GCC_QUPV3_I2C_S0_CLK 63
|
||||
#define GCC_QUPV3_I2C_S0_CLK_SRC 64
|
||||
#define GCC_QUPV3_I2C_S1_CLK 65
|
||||
#define GCC_QUPV3_I2C_S1_CLK_SRC 66
|
||||
#define GCC_QUPV3_I2C_S2_CLK 67
|
||||
#define GCC_QUPV3_I2C_S2_CLK_SRC 68
|
||||
#define GCC_QUPV3_I2C_S3_CLK 69
|
||||
#define GCC_QUPV3_I2C_S3_CLK_SRC 70
|
||||
#define GCC_QUPV3_I2C_S4_CLK 71
|
||||
#define GCC_QUPV3_I2C_S4_CLK_SRC 72
|
||||
#define GCC_QUPV3_I2C_S5_CLK 73
|
||||
#define GCC_QUPV3_I2C_S5_CLK_SRC 74
|
||||
#define GCC_QUPV3_I2C_S6_CLK 75
|
||||
#define GCC_QUPV3_I2C_S6_CLK_SRC 76
|
||||
#define GCC_QUPV3_I2C_S7_CLK 77
|
||||
#define GCC_QUPV3_I2C_S7_CLK_SRC 78
|
||||
#define GCC_QUPV3_I2C_S8_CLK 79
|
||||
#define GCC_QUPV3_I2C_S8_CLK_SRC 80
|
||||
#define GCC_QUPV3_I2C_S9_CLK 81
|
||||
#define GCC_QUPV3_I2C_S9_CLK_SRC 82
|
||||
#define GCC_QUPV3_I2C_S_AHB_CLK 83
|
||||
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 84
|
||||
#define GCC_QUPV3_WRAP1_CORE_CLK 85
|
||||
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 86
|
||||
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 87
|
||||
#define GCC_QUPV3_WRAP1_S0_CLK 88
|
||||
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 89
|
||||
#define GCC_QUPV3_WRAP1_S1_CLK 90
|
||||
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 91
|
||||
#define GCC_QUPV3_WRAP1_S2_CLK 92
|
||||
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 93
|
||||
#define GCC_QUPV3_WRAP1_S3_CLK 94
|
||||
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 95
|
||||
#define GCC_QUPV3_WRAP1_S4_CLK 96
|
||||
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 97
|
||||
#define GCC_QUPV3_WRAP1_S5_CLK 98
|
||||
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 99
|
||||
#define GCC_QUPV3_WRAP1_S6_CLK 100
|
||||
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 101
|
||||
#define GCC_QUPV3_WRAP1_S7_CLK 102
|
||||
#define GCC_QUPV3_WRAP1_S7_CLK_SRC 103
|
||||
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 104
|
||||
#define GCC_QUPV3_WRAP2_CORE_CLK 105
|
||||
#define GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC 106
|
||||
#define GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK 107
|
||||
#define GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK 108
|
||||
#define GCC_QUPV3_WRAP2_S0_CLK 109
|
||||
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 110
|
||||
#define GCC_QUPV3_WRAP2_S1_CLK 111
|
||||
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 112
|
||||
#define GCC_QUPV3_WRAP2_S2_CLK 113
|
||||
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 114
|
||||
#define GCC_QUPV3_WRAP2_S3_CLK 115
|
||||
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 116
|
||||
#define GCC_QUPV3_WRAP2_S4_CLK 117
|
||||
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 118
|
||||
#define GCC_QUPV3_WRAP2_S5_CLK 119
|
||||
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 120
|
||||
#define GCC_QUPV3_WRAP2_S6_CLK 121
|
||||
#define GCC_QUPV3_WRAP2_S6_CLK_SRC 122
|
||||
#define GCC_QUPV3_WRAP2_S7_CLK 123
|
||||
#define GCC_QUPV3_WRAP2_S7_CLK_SRC 124
|
||||
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 125
|
||||
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 126
|
||||
#define GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK 127
|
||||
#define GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK 128
|
||||
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 129
|
||||
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 130
|
||||
#define GCC_SDCC2_AHB_CLK 131
|
||||
#define GCC_SDCC2_APPS_CLK 132
|
||||
#define GCC_SDCC2_APPS_CLK_SRC 133
|
||||
#define GCC_SDCC4_AHB_CLK 134
|
||||
#define GCC_SDCC4_APPS_CLK 135
|
||||
#define GCC_SDCC4_APPS_CLK_SRC 136
|
||||
#define GCC_UFS_PHY_AHB_CLK 137
|
||||
#define GCC_UFS_PHY_AXI_CLK 138
|
||||
#define GCC_UFS_PHY_AXI_CLK_SRC 139
|
||||
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 140
|
||||
#define GCC_UFS_PHY_ICE_CORE_CLK 141
|
||||
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 142
|
||||
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 143
|
||||
#define GCC_UFS_PHY_PHY_AUX_CLK 144
|
||||
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 145
|
||||
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 146
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 147
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 148
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 149
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 150
|
||||
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 151
|
||||
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 152
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 153
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 154
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 155
|
||||
#define GCC_USB30_PRIM_MASTER_CLK 156
|
||||
#define GCC_USB30_PRIM_MASTER_CLK_SRC 157
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 158
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 159
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 160
|
||||
#define GCC_USB30_PRIM_SLEEP_CLK 161
|
||||
#define GCC_USB3_PRIM_PHY_AUX_CLK 162
|
||||
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 163
|
||||
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 164
|
||||
#define GCC_USB3_PRIM_PHY_PIPE_CLK 165
|
||||
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 166
|
||||
#define GCC_VIDEO_AHB_CLK 167
|
||||
#define GCC_VIDEO_AXI0_CLK 168
|
||||
#define GCC_VIDEO_AXI1_CLK 169
|
||||
#define GCC_VIDEO_XO_CLK 170
|
||||
|
||||
/* GCC power domains */
|
||||
#define GCC_PCIE_0_GDSC 0
|
||||
#define GCC_PCIE_0_PHY_GDSC 1
|
||||
#define GCC_UFS_MEM_PHY_GDSC 2
|
||||
#define GCC_UFS_PHY_GDSC 3
|
||||
#define GCC_USB30_PRIM_GDSC 4
|
||||
#define GCC_USB3_PHY_GDSC 5
|
||||
|
||||
/* GCC resets */
|
||||
#define GCC_CAMERA_BCR 0
|
||||
#define GCC_DISPLAY_BCR 1
|
||||
#define GCC_EVA_BCR 2
|
||||
#define GCC_GPU_BCR 3
|
||||
#define GCC_PCIE_0_BCR 4
|
||||
#define GCC_PCIE_0_LINK_DOWN_BCR 5
|
||||
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6
|
||||
#define GCC_PCIE_0_PHY_BCR 7
|
||||
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8
|
||||
#define GCC_PCIE_PHY_BCR 9
|
||||
#define GCC_PCIE_PHY_CFG_AHB_BCR 10
|
||||
#define GCC_PCIE_PHY_COM_BCR 11
|
||||
#define GCC_PCIE_RSCC_BCR 12
|
||||
#define GCC_PDM_BCR 13
|
||||
#define GCC_QUPV3_WRAPPER_1_BCR 14
|
||||
#define GCC_QUPV3_WRAPPER_2_BCR 15
|
||||
#define GCC_QUPV3_WRAPPER_I2C_BCR 16
|
||||
#define GCC_QUSB2PHY_PRIM_BCR 17
|
||||
#define GCC_QUSB2PHY_SEC_BCR 18
|
||||
#define GCC_SDCC2_BCR 19
|
||||
#define GCC_SDCC4_BCR 20
|
||||
#define GCC_UFS_PHY_BCR 21
|
||||
#define GCC_USB30_PRIM_BCR 22
|
||||
#define GCC_USB3_DP_PHY_PRIM_BCR 23
|
||||
#define GCC_USB3_DP_PHY_SEC_BCR 24
|
||||
#define GCC_USB3_PHY_PRIM_BCR 25
|
||||
#define GCC_USB3_PHY_SEC_BCR 26
|
||||
#define GCC_USB3PHY_PHY_PRIM_BCR 27
|
||||
#define GCC_USB3PHY_PHY_SEC_BCR 28
|
||||
#define GCC_VIDEO_AXI0_CLK_ARES 29
|
||||
#define GCC_VIDEO_AXI1_CLK_ARES 30
|
||||
#define GCC_VIDEO_BCR 31
|
||||
#define GCC_EVA_AXI0_CLK_ARES 32
|
||||
#define GCC_EVA_AXI0C_CLK_ARES 33
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,15 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8750_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8750_H
|
||||
|
||||
/* TCSR_CC clocks */
|
||||
#define TCSR_PCIE_0_CLKREF_EN 0
|
||||
#define TCSR_UFS_CLKREF_EN 1
|
||||
#define TCSR_USB2_CLKREF_EN 2
|
||||
#define TCSR_USB3_CLKREF_EN 3
|
||||
|
||||
#endif
|
||||
@@ -33,9 +33,22 @@
|
||||
#define GPU_CC_SLEEP_CLK 23
|
||||
#define GPU_CC_XO_CLK_SRC 24
|
||||
#define GPU_CC_XO_DIV_CLK_SRC 25
|
||||
#define GPU_CC_CX_ACCU_SHIFT_CLK 26
|
||||
#define GPU_CC_GX_ACCU_SHIFT_CLK 27
|
||||
|
||||
/* GDSCs */
|
||||
#define GPU_CX_GDSC 0
|
||||
#define GPU_GX_GDSC 1
|
||||
|
||||
/* GPU_CC resets */
|
||||
#define GPU_CC_ACD_BCR 0
|
||||
#define GPU_CC_CB_BCR 1
|
||||
#define GPU_CC_CX_BCR 2
|
||||
#define GPU_CC_FAST_HUB_BCR 3
|
||||
#define GPU_CC_FF_BCR 4
|
||||
#define GPU_CC_GFX3D_AON_BCR 5
|
||||
#define GPU_CC_GMU_BCR 6
|
||||
#define GPU_CC_GX_BCR 7
|
||||
#define GPU_CC_XO_BCR 8
|
||||
|
||||
#endif
|
||||
|
||||
@@ -44,7 +44,9 @@
|
||||
#define _DT_BINDINGS_CLK_SUN50I_A64_H_
|
||||
|
||||
#define CLK_PLL_VIDEO0 7
|
||||
#define CLK_PLL_VIDEO0_2X 8
|
||||
#define CLK_PLL_PERIPH0 11
|
||||
#define CLK_PLL_MIPI 17
|
||||
|
||||
#define CLK_CPUX 21
|
||||
#define CLK_BUS_MIPI_DSI 28
|
||||
|
||||
@@ -0,0 +1,24 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
#ifndef INTERCONNECT_QCOM_IPQ5424_H
|
||||
#define INTERCONNECT_QCOM_IPQ5424_H
|
||||
|
||||
#define MASTER_ANOC_PCIE0 0
|
||||
#define SLAVE_ANOC_PCIE0 1
|
||||
#define MASTER_CNOC_PCIE0 2
|
||||
#define SLAVE_CNOC_PCIE0 3
|
||||
#define MASTER_ANOC_PCIE1 4
|
||||
#define SLAVE_ANOC_PCIE1 5
|
||||
#define MASTER_CNOC_PCIE1 6
|
||||
#define SLAVE_CNOC_PCIE1 7
|
||||
#define MASTER_ANOC_PCIE2 8
|
||||
#define SLAVE_ANOC_PCIE2 9
|
||||
#define MASTER_CNOC_PCIE2 10
|
||||
#define SLAVE_CNOC_PCIE2 11
|
||||
#define MASTER_ANOC_PCIE3 12
|
||||
#define SLAVE_ANOC_PCIE3 13
|
||||
#define MASTER_CNOC_PCIE3 14
|
||||
#define SLAVE_CNOC_PCIE3 15
|
||||
#define MASTER_CNOC_USB 16
|
||||
#define SLAVE_CNOC_USB 17
|
||||
|
||||
#endif /* INTERCONNECT_QCOM_IPQ5424_H */
|
||||
Reference in New Issue
Block a user