lib/raid6/altivec: Add vpermxor implementation for raid6 Q syndrome

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This patch uses the vpermxor instruction to optimise the raid6 Q
syndrome. This instruction was made available with POWER8, ISA version
2.07. It allows for both vperm and vxor instructions to be done in a
single instruction. This has been tested for correctness on a ppc64le
vm with a basic RAID6 setup containing 5 drives.

The performance benchmarks are from the raid6test in the
/lib/raid6/test directory. These results are from an IBM Firestone
machine with ppc64le architecture. The benchmark results show a 35%
speed increase over the best existing algorithm for powerpc (altivec).
The raid6test has also been run on a big-endian ppc64 vm to ensure it
also works for big-endian architectures.

Performance benchmarks:
  raid6: altivecx4 gen() 18773 MB/s
  raid6: altivecx8 gen() 19438 MB/s

  raid6: vpermxor4 gen() 25112 MB/s
  raid6: vpermxor8 gen() 26279 MB/s

Signed-off-by: Matt Brown <matthew.brown.dev@gmail.com>
Reviewed-by: Daniel Axtens <dja@axtens.net>
[mpe: Add VPERMXOR macro so we can build with old binutils]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

This commit is contained in:

Matt Brown

2017-08-04 13:42:32 +10:00

committed by

Michael Ellerman

parent 7004263bd4

commit 751ba79cc5

7 changed files with 161 additions and 3 deletions

									
										lib/raid6/algos.c
									
		+4
		
												View File
												
				@@ -74,6 +74,10 @@ const struct raid6_calls * const raid6_algos[] = {

					&raid6_altivec2,

					&raid6_altivec4,

					&raid6_altivec8,

					&raid6_vpermxor1,

					&raid6_vpermxor2,

					&raid6_vpermxor4,

					&raid6_vpermxor8,

				#endif

				#if defined(CONFIG_TILEGX)

					&raid6_tilegx8,