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pinctrl: intel: Add Intel Merrifield pin controller support

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This driver adds pinctrl support for Intel Merrifield. The IP block which is
called Family-Level Interface Shim is a separate entity in SoC. The GPIO driver
(gpio-intel-mid.c) will be updated accordingly to support pinctrl interface.

Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Andy Shevchenko
2016-06-23 13:49:36 +03:00
committed by Linus Walleij
parent 11884b18ef
commit 4e80c8f505
3 changed files with 923 additions and 0 deletions
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11
drivers/pinctrl/intel/Kconfig
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@@ -29,6 +29,17 @@ config PINCTRL_CHERRYVIEW
Cherryview/Braswell pinctrl driver provides an interface that
allows configuring of SoC pins and using them as GPIOs.
config PINCTRL_MERRIFIELD
tristate "Intel Merrifield pinctrl driver"
depends on X86_INTEL_MID
select PINMUX
select PINCONF
select GENERIC_PINCONF
help
Merrifield Family-Level Interface Shim (FLIS) driver provides an
interface that allows configuring of SoC pins and using them as
GPIOs.
config PINCTRL_INTEL
tristate
select PINMUX

1
drivers/pinctrl/intel/Makefile
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@@ -2,6 +2,7 @@
obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o
obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o
obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o
obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o
obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o

911
drivers/pinctrl/intel/pinctrl-merrifield.c Normal file
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