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clk: sophgo: Add SG2042 clock driver
Add a driver for the SOPHGO SG2042 clocks. Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
This commit is contained in:
Chen Wang
@@ -9,3 +9,31 @@ config CLK_SOPHGO_CV1800
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The driver require a 25MHz Oscillator to function generate clock.
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It includes PLLs, common clock function and some vendor clock for
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IPs of CV18XX series SoC
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config CLK_SOPHGO_SG2042_PLL
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tristate "Sophgo SG2042 PLL clock support"
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depends on ARCH_SOPHGO || COMPILE_TEST
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help
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This driver supports the PLL clock controller on the
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Sophgo SG2042 SoC. This clock IP uses three oscillators with
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frequency of 25 MHz as input, which are used for Main/Fixed
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PLL, DDR PLL 0 and DDR PLL 1 respectively.
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config CLK_SOPHGO_SG2042_CLKGEN
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tristate "Sophgo SG2042 Clock Generator support"
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depends on CLK_SOPHGO_SG2042_PLL
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help
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This driver supports the Clock Generator on the
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Sophgo SG2042 SoC. This clock IP depends on SG2042 PLL clock
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because it uses PLL clocks as input.
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This driver provides clock function such as DIV/Mux/Gate.
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config CLK_SOPHGO_SG2042_RPGATE
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tristate "Sophgo SG2042 RP subsystem clock controller support"
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depends on CLK_SOPHGO_SG2042_CLKGEN
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help
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This driver supports the RP((Riscv Processors)) subsystem clock
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controller on the Sophgo SG2042 SoC.
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This clock IP depends on SG2042 Clock Generator because it uses
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clock from Clock Generator IP as input.
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This driver provides Gate function for RP.
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@@ -5,3 +5,7 @@ clk-sophgo-cv1800-y += clk-cv1800.o
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clk-sophgo-cv1800-y += clk-cv18xx-common.o
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clk-sophgo-cv1800-y += clk-cv18xx-ip.o
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clk-sophgo-cv1800-y += clk-cv18xx-pll.o
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obj-$(CONFIG_CLK_SOPHGO_SG2042_CLKGEN) += clk-sg2042-clkgen.o
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obj-$(CONFIG_CLK_SOPHGO_SG2042_PLL) += clk-sg2042-pll.o
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obj-$(CONFIG_CLK_SOPHGO_SG2042_RPGATE) += clk-sg2042-rpgate.o
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1152
drivers/clk/sophgo/clk-sg2042-clkgen.c
Normal file
1152
drivers/clk/sophgo/clk-sg2042-clkgen.c
Normal file
File diff suppressed because it is too large
Load Diff
570
drivers/clk/sophgo/clk-sg2042-pll.c
Normal file
570
drivers/clk/sophgo/clk-sg2042-pll.c
Normal file
File diff suppressed because it is too large
Load Diff
291
drivers/clk/sophgo/clk-sg2042-rpgate.c
Normal file
291
drivers/clk/sophgo/clk-sg2042-rpgate.c
Normal file
@@ -0,0 +1,291 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Sophgo SG2042 RP clock Driver
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*
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* Copyright (C) 2024 Sophgo Technology Inc.
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* Copyright (C) 2024 Chen Wang <unicorn_wang@outlook.com>
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*/
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#include <linux/array_size.h>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
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#include "clk-sg2042.h"
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#define R_SYSGATE_BEGIN 0x0368
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#define R_RP_RXU_CLK_ENABLE (0x0368 - R_SYSGATE_BEGIN)
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#define R_MP0_STATUS_REG (0x0380 - R_SYSGATE_BEGIN)
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#define R_MP0_CONTROL_REG (0x0384 - R_SYSGATE_BEGIN)
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#define R_MP1_STATUS_REG (0x0388 - R_SYSGATE_BEGIN)
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#define R_MP1_CONTROL_REG (0x038C - R_SYSGATE_BEGIN)
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#define R_MP2_STATUS_REG (0x0390 - R_SYSGATE_BEGIN)
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#define R_MP2_CONTROL_REG (0x0394 - R_SYSGATE_BEGIN)
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#define R_MP3_STATUS_REG (0x0398 - R_SYSGATE_BEGIN)
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#define R_MP3_CONTROL_REG (0x039C - R_SYSGATE_BEGIN)
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#define R_MP4_STATUS_REG (0x03A0 - R_SYSGATE_BEGIN)
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#define R_MP4_CONTROL_REG (0x03A4 - R_SYSGATE_BEGIN)
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#define R_MP5_STATUS_REG (0x03A8 - R_SYSGATE_BEGIN)
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#define R_MP5_CONTROL_REG (0x03AC - R_SYSGATE_BEGIN)
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#define R_MP6_STATUS_REG (0x03B0 - R_SYSGATE_BEGIN)
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#define R_MP6_CONTROL_REG (0x03B4 - R_SYSGATE_BEGIN)
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#define R_MP7_STATUS_REG (0x03B8 - R_SYSGATE_BEGIN)
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#define R_MP7_CONTROL_REG (0x03BC - R_SYSGATE_BEGIN)
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#define R_MP8_STATUS_REG (0x03C0 - R_SYSGATE_BEGIN)
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#define R_MP8_CONTROL_REG (0x03C4 - R_SYSGATE_BEGIN)
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#define R_MP9_STATUS_REG (0x03C8 - R_SYSGATE_BEGIN)
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#define R_MP9_CONTROL_REG (0x03CC - R_SYSGATE_BEGIN)
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#define R_MP10_STATUS_REG (0x03D0 - R_SYSGATE_BEGIN)
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#define R_MP10_CONTROL_REG (0x03D4 - R_SYSGATE_BEGIN)
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#define R_MP11_STATUS_REG (0x03D8 - R_SYSGATE_BEGIN)
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#define R_MP11_CONTROL_REG (0x03DC - R_SYSGATE_BEGIN)
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#define R_MP12_STATUS_REG (0x03E0 - R_SYSGATE_BEGIN)
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#define R_MP12_CONTROL_REG (0x03E4 - R_SYSGATE_BEGIN)
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#define R_MP13_STATUS_REG (0x03E8 - R_SYSGATE_BEGIN)
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#define R_MP13_CONTROL_REG (0x03EC - R_SYSGATE_BEGIN)
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#define R_MP14_STATUS_REG (0x03F0 - R_SYSGATE_BEGIN)
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#define R_MP14_CONTROL_REG (0x03F4 - R_SYSGATE_BEGIN)
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#define R_MP15_STATUS_REG (0x03F8 - R_SYSGATE_BEGIN)
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#define R_MP15_CONTROL_REG (0x03FC - R_SYSGATE_BEGIN)
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/**
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* struct sg2042_rpgate_clock - Gate clock for RP(riscv processors) subsystem
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* @hw: clk_hw for initialization
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* @id: used to map clk_onecell_data
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* @offset_enable: offset of gate enable registers
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* @bit_idx: which bit in the register controls gating of this clock
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*/
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struct sg2042_rpgate_clock {
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struct clk_hw hw;
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unsigned int id;
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u32 offset_enable;
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u8 bit_idx;
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};
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/*
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* Clock initialization macro naming rules:
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* FW: use CLK_HW_INIT_FW_NAME
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*/
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#define SG2042_GATE_FW(_id, _name, _parent, _flags, \
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_r_enable, _bit_idx) { \
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.hw.init = CLK_HW_INIT_FW_NAME( \
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_name, \
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_parent, \
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NULL, \
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_flags), \
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.id = _id, \
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.offset_enable = _r_enable, \
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.bit_idx = _bit_idx, \
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}
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/*
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* Gate clocks for RP subsystem (including the MP subsystem), which control
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* registers are defined in SYS_CTRL.
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*/
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static const struct sg2042_rpgate_clock sg2042_gate_rp[] = {
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/* downstream of clk_gate_rp_cpu_normal about rxu */
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SG2042_GATE_FW(GATE_CLK_RXU0, "clk_gate_rxu0", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 0),
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SG2042_GATE_FW(GATE_CLK_RXU1, "clk_gate_rxu1", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 1),
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SG2042_GATE_FW(GATE_CLK_RXU2, "clk_gate_rxu2", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 2),
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SG2042_GATE_FW(GATE_CLK_RXU3, "clk_gate_rxu3", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 3),
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SG2042_GATE_FW(GATE_CLK_RXU4, "clk_gate_rxu4", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 4),
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SG2042_GATE_FW(GATE_CLK_RXU5, "clk_gate_rxu5", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 5),
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SG2042_GATE_FW(GATE_CLK_RXU6, "clk_gate_rxu6", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 6),
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SG2042_GATE_FW(GATE_CLK_RXU7, "clk_gate_rxu7", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 7),
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SG2042_GATE_FW(GATE_CLK_RXU8, "clk_gate_rxu8", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 8),
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SG2042_GATE_FW(GATE_CLK_RXU9, "clk_gate_rxu9", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 9),
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SG2042_GATE_FW(GATE_CLK_RXU10, "clk_gate_rxu10", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 10),
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SG2042_GATE_FW(GATE_CLK_RXU11, "clk_gate_rxu11", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 11),
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SG2042_GATE_FW(GATE_CLK_RXU12, "clk_gate_rxu12", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 12),
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SG2042_GATE_FW(GATE_CLK_RXU13, "clk_gate_rxu13", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 13),
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SG2042_GATE_FW(GATE_CLK_RXU14, "clk_gate_rxu14", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 14),
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SG2042_GATE_FW(GATE_CLK_RXU15, "clk_gate_rxu15", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 15),
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SG2042_GATE_FW(GATE_CLK_RXU16, "clk_gate_rxu16", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 16),
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SG2042_GATE_FW(GATE_CLK_RXU17, "clk_gate_rxu17", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 17),
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SG2042_GATE_FW(GATE_CLK_RXU18, "clk_gate_rxu18", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 18),
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SG2042_GATE_FW(GATE_CLK_RXU19, "clk_gate_rxu19", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 19),
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SG2042_GATE_FW(GATE_CLK_RXU20, "clk_gate_rxu20", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 20),
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SG2042_GATE_FW(GATE_CLK_RXU21, "clk_gate_rxu21", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 21),
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SG2042_GATE_FW(GATE_CLK_RXU22, "clk_gate_rxu22", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 22),
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SG2042_GATE_FW(GATE_CLK_RXU23, "clk_gate_rxu23", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 23),
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SG2042_GATE_FW(GATE_CLK_RXU24, "clk_gate_rxu24", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 24),
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SG2042_GATE_FW(GATE_CLK_RXU25, "clk_gate_rxu25", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 25),
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SG2042_GATE_FW(GATE_CLK_RXU26, "clk_gate_rxu26", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 26),
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SG2042_GATE_FW(GATE_CLK_RXU27, "clk_gate_rxu27", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 27),
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SG2042_GATE_FW(GATE_CLK_RXU28, "clk_gate_rxu28", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 28),
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SG2042_GATE_FW(GATE_CLK_RXU29, "clk_gate_rxu29", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 29),
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SG2042_GATE_FW(GATE_CLK_RXU30, "clk_gate_rxu30", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 30),
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SG2042_GATE_FW(GATE_CLK_RXU31, "clk_gate_rxu31", "rpgate",
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0, R_RP_RXU_CLK_ENABLE, 31),
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/* downstream of clk_gate_rp_cpu_normal about mp */
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SG2042_GATE_FW(GATE_CLK_MP0, "clk_gate_mp0", "rpgate",
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CLK_IS_CRITICAL, R_MP0_CONTROL_REG, 0),
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SG2042_GATE_FW(GATE_CLK_MP1, "clk_gate_mp1", "rpgate",
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CLK_IS_CRITICAL, R_MP1_CONTROL_REG, 0),
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SG2042_GATE_FW(GATE_CLK_MP2, "clk_gate_mp2", "rpgate",
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CLK_IS_CRITICAL, R_MP2_CONTROL_REG, 0),
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SG2042_GATE_FW(GATE_CLK_MP3, "clk_gate_mp3", "rpgate",
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CLK_IS_CRITICAL, R_MP3_CONTROL_REG, 0),
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SG2042_GATE_FW(GATE_CLK_MP4, "clk_gate_mp4", "rpgate",
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CLK_IS_CRITICAL, R_MP4_CONTROL_REG, 0),
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SG2042_GATE_FW(GATE_CLK_MP5, "clk_gate_mp5", "rpgate",
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CLK_IS_CRITICAL, R_MP5_CONTROL_REG, 0),
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SG2042_GATE_FW(GATE_CLK_MP6, "clk_gate_mp6", "rpgate",
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CLK_IS_CRITICAL, R_MP6_CONTROL_REG, 0),
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SG2042_GATE_FW(GATE_CLK_MP7, "clk_gate_mp7", "rpgate",
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CLK_IS_CRITICAL, R_MP7_CONTROL_REG, 0),
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SG2042_GATE_FW(GATE_CLK_MP8, "clk_gate_mp8", "rpgate",
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CLK_IS_CRITICAL, R_MP8_CONTROL_REG, 0),
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SG2042_GATE_FW(GATE_CLK_MP9, "clk_gate_mp9", "rpgate",
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CLK_IS_CRITICAL, R_MP9_CONTROL_REG, 0),
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SG2042_GATE_FW(GATE_CLK_MP10, "clk_gate_mp10", "rpgate",
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CLK_IS_CRITICAL, R_MP10_CONTROL_REG, 0),
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SG2042_GATE_FW(GATE_CLK_MP11, "clk_gate_mp11", "rpgate",
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CLK_IS_CRITICAL, R_MP11_CONTROL_REG, 0),
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SG2042_GATE_FW(GATE_CLK_MP12, "clk_gate_mp12", "rpgate",
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CLK_IS_CRITICAL, R_MP12_CONTROL_REG, 0),
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SG2042_GATE_FW(GATE_CLK_MP13, "clk_gate_mp13", "rpgate",
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CLK_IS_CRITICAL, R_MP13_CONTROL_REG, 0),
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SG2042_GATE_FW(GATE_CLK_MP14, "clk_gate_mp14", "rpgate",
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CLK_IS_CRITICAL, R_MP14_CONTROL_REG, 0),
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SG2042_GATE_FW(GATE_CLK_MP15, "clk_gate_mp15", "rpgate",
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CLK_IS_CRITICAL, R_MP15_CONTROL_REG, 0),
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};
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static DEFINE_SPINLOCK(sg2042_clk_lock);
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static int sg2042_clk_register_rpgates(struct device *dev,
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struct sg2042_clk_data *clk_data,
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const struct sg2042_rpgate_clock gate_clks[],
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int num_gate_clks)
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{
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const struct sg2042_rpgate_clock *gate;
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struct clk_hw *hw;
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int i, ret = 0;
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for (i = 0; i < num_gate_clks; i++) {
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gate = &gate_clks[i];
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hw = devm_clk_hw_register_gate_parent_data
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(dev,
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gate->hw.init->name,
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gate->hw.init->parent_data,
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gate->hw.init->flags,
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clk_data->iobase + gate->offset_enable,
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gate->bit_idx,
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0,
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&sg2042_clk_lock);
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if (IS_ERR(hw)) {
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pr_err("failed to register clock %s\n", gate->hw.init->name);
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ret = PTR_ERR(hw);
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break;
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}
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clk_data->onecell_data.hws[gate->id] = hw;
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}
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return ret;
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}
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static int sg2042_init_clkdata(struct platform_device *pdev,
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int num_clks,
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struct sg2042_clk_data **pp_clk_data)
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{
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struct sg2042_clk_data *clk_data;
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clk_data = devm_kzalloc(&pdev->dev,
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struct_size(clk_data, onecell_data.hws, num_clks),
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GFP_KERNEL);
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if (!clk_data)
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return -ENOMEM;
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clk_data->iobase = devm_platform_ioremap_resource(pdev, 0);
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if (WARN_ON(IS_ERR(clk_data->iobase)))
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return PTR_ERR(clk_data->iobase);
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clk_data->onecell_data.num = num_clks;
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*pp_clk_data = clk_data;
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return 0;
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}
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static int sg2042_rpgate_probe(struct platform_device *pdev)
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{
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struct sg2042_clk_data *clk_data = NULL;
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int num_clks;
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int ret;
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num_clks = ARRAY_SIZE(sg2042_gate_rp);
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ret = sg2042_init_clkdata(pdev, num_clks, &clk_data);
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if (ret)
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goto error_out;
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ret = sg2042_clk_register_rpgates(&pdev->dev, clk_data, sg2042_gate_rp,
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num_clks);
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if (ret)
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goto error_out;
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return devm_of_clk_add_hw_provider(&pdev->dev,
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of_clk_hw_onecell_get,
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&clk_data->onecell_data);
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error_out:
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pr_err("%s failed error number %d\n", __func__, ret);
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return ret;
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}
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static const struct of_device_id sg2042_rpgate_match[] = {
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{ .compatible = "sophgo,sg2042-rpgate" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, sg2042_rpgate_match);
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static struct platform_driver sg2042_rpgate_driver = {
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.probe = sg2042_rpgate_probe,
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.driver = {
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.name = "clk-sophgo-sg2042-rpgate",
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.of_match_table = sg2042_rpgate_match,
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.suppress_bind_attrs = true,
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},
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};
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module_platform_driver(sg2042_rpgate_driver);
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MODULE_AUTHOR("Chen Wang");
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MODULE_DESCRIPTION("Sophgo SG2042 rp subsystem clock driver");
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MODULE_LICENSE("GPL");
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||||
18
drivers/clk/sophgo/clk-sg2042.h
Normal file
18
drivers/clk/sophgo/clk-sg2042.h
Normal file
@@ -0,0 +1,18 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _CLK_SOPHGO_SG2042_H_
|
||||
#define _CLK_SOPHGO_SG2042_H_
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
/**
|
||||
* struct sg2042_clk_data - Common data of clock-controller
|
||||
* @iobase: base address of clock-controller
|
||||
* @onecell_data: used for adding providers.
|
||||
*/
|
||||
struct sg2042_clk_data {
|
||||
void __iomem *iobase;
|
||||
struct clk_hw_onecell_data onecell_data;
|
||||
};
|
||||
|
||||
#endif /* _CLK_SOPHGO_SG2042_H_ */
|
||||
Reference in New Issue
Block a user