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dt-bindings: Remove leading zeros from bindings notation
Improve the binding example by removing all the leading zeros to fix the following dtc warnings: Warning (unit_address_format): Node /XXX unit name should not have leading 0s Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find ./Documentation/devicetree/bindings "*.txt"` Some unnecessary changes were manually fixed. Signed-off-by: Marco Franchi <marco.franchi@nxp.com> Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Marco Franchi
committed by
Rob Herring
Rob Herring
parent
efb5b43a54
commit
48c926cd34
@@ -62,7 +62,7 @@ pmu_system_controller: system-controller@10040000 {
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Example of clock consumer :
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usb3503: usb3503@08 {
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usb3503: usb3503@8 {
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/* ... */
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clock-names = "refclk";
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clocks = <&pmu_system_controller 0>;
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@@ -71,7 +71,7 @@ Optional nodes:
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- compatible: only "samsung,secure-firmware" is currently supported
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- reg: address of non-secure SYSRAM used for communication with firmware
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firmware@0203F000 {
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firmware@203F000 {
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compatible = "samsung,secure-firmware";
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reg = <0x0203F000 0x1000>;
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};
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@@ -33,7 +33,7 @@ Required properties:
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property with the highest frequency
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Example:
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v2m_sysctl: sysctl@020000 {
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v2m_sysctl: sysctl@20000 {
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compatible = "arm,sp810", "arm,primecell";
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reg = <0x020000 0x1000>;
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clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
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@@ -37,7 +37,7 @@ Example:
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compatible = "arm,vexpress-sysreg";
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reg = <0x10000000 0x1000>;
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v2m_led_gpios: sys_led@08 {
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v2m_led_gpios: sys_led@8 {
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compatible = "arm,vexpress-sysreg,sys_led";
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gpio-controller;
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#gpio-cells = <2>;
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@@ -56,7 +56,7 @@ Examples:
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interrupts = <115>;
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};
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ahci: sata@01c18000 {
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ahci: sata@1c18000 {
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compatible = "allwinner,sun4i-a10-ahci";
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reg = <0x01c18000 0x1000>;
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interrupts = <56>;
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@@ -25,7 +25,7 @@ Optional properties:
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Examples:
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sata@02200000 {
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sata@2200000 {
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compatible = "fsl,imx6q-ahci";
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reg = <0x02200000 0x4000>;
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interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
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@@ -61,7 +61,7 @@ Timing property for child nodes. It is mandatory, not optional.
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Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
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weim: weim@021b8000 {
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weim: weim@21b8000 {
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compatible = "fsl,imx6q-weim";
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reg = <0x021b8000 0x4000>;
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clocks = <&clks 196>;
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@@ -28,7 +28,7 @@ which can normally be found in the datasheet.
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Example:
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rsb@01f03400 {
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rsb@1f03400 {
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compatible = "allwinner,sun8i-a23-rsb";
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reg = <0x01f03400 0x400>;
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interrupts = <0 39 4>;
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@@ -59,7 +59,7 @@ syscon: syscon@10000000 {
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compatible = "syscon";
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reg = <0x10000000 0x1000>;
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oscclk0: osc0@0c {
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oscclk0: osc0@c {
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compatible = "arm,syscon-icst307";
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#clock-cells = <0>;
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lock-offset = <0x20>;
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@@ -80,7 +80,7 @@ Example 3: I2S controller node that consumes the clock generated by the clock
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controller. Refer to the standard clock bindings for information
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about 'clocks' and 'clock-names' property.
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i2s0: i2s@03830000 {
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i2s0: i2s@3830000 {
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compatible = "samsung,i2s-v5";
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reg = <0x03830000 0x100>;
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dmas = <&pdma0 10
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@@ -43,7 +43,7 @@ Example: I2S controller node that consumes the clock generated by the clock
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controller. Refer to the standard clock bindings for information
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about 'clocks' and 'clock-names' property.
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i2s0: i2s@03830000 {
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i2s0: i2s@3830000 {
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/* ... */
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clock-names = "iis", "i2s_opclk0",
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"i2s_opclk1";
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@@ -21,7 +21,7 @@ Required properties:
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a size of 8.
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- #clock-cells : from common clock binding; shall be set to 1
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divider_clk: core-clock@0064 {
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divider_clk: core-clock@64 {
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compatible = "marvell,dove-divider-clock";
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reg = <0x0064 0x8>;
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#clock-cells = <1>;
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@@ -10,13 +10,13 @@ ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h
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for the full list of i.MX1 clock IDs.
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Examples:
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clks: ccm@0021b000 {
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clks: ccm@21b000 {
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#clock-cells = <1>;
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compatible = "fsl,imx1-ccm";
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reg = <0x0021b000 0x1000>;
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};
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pwm: pwm@00208000 {
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pwm: pwm@208000 {
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#pwm-cells = <2>;
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compatible = "fsl,imx1-pwm";
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reg = <0x00208000 0x1000>;
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@@ -14,14 +14,14 @@ Examples:
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#include <dt-bindings/clock/imx6qdl-clock.h>
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clks: ccm@020c4000 {
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clks: ccm@20c4000 {
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compatible = "fsl,imx6q-ccm";
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reg = <0x020c4000 0x4000>;
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interrupts = <0 87 0x04 0 88 0x04>;
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#clock-cells = <1>;
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};
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uart1: serial@02020000 {
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uart1: serial@2020000 {
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compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
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reg = <0x02020000 0x4000>;
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interrupts = <0 26 0x04>;
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@@ -46,7 +46,7 @@ Example:
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/* ... */
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Node of the MFD chip
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max77686: max77686@09 {
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max77686: max77686@9 {
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compatible = "maxim,max77686";
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interrupt-parent = <&wakeup_eint>;
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interrupts = <26 0>;
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@@ -71,7 +71,7 @@ Example:
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/* ... */
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Node of the MFD chip
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max77802: max77802@09 {
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max77802: max77802@9 {
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compatible = "maxim,max77802";
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interrupt-parent = <&wakeup_eint>;
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interrupts = <26 0>;
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@@ -42,7 +42,7 @@ Required properties:
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Example:
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clockgen-a@090ff000 {
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clockgen-a@90ff000 {
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compatible = "st,clkgen-c32";
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reg = <0x90ff000 0x1000>;
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@@ -36,7 +36,7 @@ For the PRCM CCUs on A83T/H3/A64, two more clocks are needed:
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- "iosc": the SoC's internal frequency oscillator
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Example for generic CCU:
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ccu: clock@01c20000 {
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ccu: clock@1c20000 {
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compatible = "allwinner,sun8i-h3-ccu";
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reg = <0x01c20000 0x400>;
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clocks = <&osc24M>, <&osc32k>;
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@@ -46,7 +46,7 @@ ccu: clock@01c20000 {
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};
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Example for PRCM CCU:
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r_ccu: clock@01f01400 {
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r_ccu: clock@1f01400 {
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compatible = "allwinner,sun50i-a64-r-ccu";
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reg = <0x01f01400 0x100>;
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clocks = <&osc24M>, <&osc32k>, <&iosc>, <&ccu CLK_PLL_PERIPH0>;
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@@ -137,7 +137,7 @@ the address block, which is related to the overall mmc block.
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For example:
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osc24M: clk@01c20050 {
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osc24M: clk@1c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-osc-clk";
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reg = <0x01c20050 0x4>;
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@@ -145,7 +145,7 @@ osc24M: clk@01c20050 {
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clock-output-names = "osc24M";
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};
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pll1: clk@01c20000 {
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pll1: clk@1c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-pll1-clk";
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reg = <0x01c20000 0x4>;
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@@ -153,7 +153,7 @@ pll1: clk@01c20000 {
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clock-output-names = "pll1";
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};
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pll5: clk@01c20020 {
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pll5: clk@1c20020 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-pll5-clk";
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reg = <0x01c20020 0x4>;
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@@ -161,7 +161,7 @@ pll5: clk@01c20020 {
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clock-output-names = "pll5_ddr", "pll5_other";
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};
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pll6: clk@01c20028 {
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pll6: clk@1c20028 {
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#clock-cells = <1>;
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compatible = "allwinner,sun6i-a31-pll6-clk";
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reg = <0x01c20028 0x4>;
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@@ -169,7 +169,7 @@ pll6: clk@01c20028 {
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clock-output-names = "pll6", "pll6x2";
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};
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cpu: cpu@01c20054 {
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cpu: cpu@1c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-cpu-clk";
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reg = <0x01c20054 0x4>;
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@@ -177,7 +177,7 @@ cpu: cpu@01c20054 {
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clock-output-names = "cpu";
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};
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mmc0_clk: clk@01c20088 {
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mmc0_clk: clk@1c20088 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20088 0x4>;
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@@ -199,7 +199,7 @@ gmac_int_tx_clk: clk@3 {
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clock-output-names = "gmac_int_tx";
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};
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gmac_clk: clk@01c20164 {
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gmac_clk: clk@1c20164 {
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#clock-cells = <0>;
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compatible = "allwinner,sun7i-a20-gmac-clk";
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reg = <0x01c20164 0x4>;
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@@ -211,7 +211,7 @@ gmac_clk: clk@01c20164 {
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clock-output-names = "gmac";
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};
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mmc_config_clk: clk@01c13000 {
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mmc_config_clk: clk@1c13000 {
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compatible = "allwinner,sun9i-a80-mmc-config-clk";
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reg = <0x01c13000 0x10>;
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clocks = <&ahb0_gates 8>;
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@@ -25,7 +25,7 @@ Example:
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};
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};
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...
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i2c0: i2c-master@0d090000 {
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i2c0: i2c-master@d090000 {
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...
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cdce706: clock-synth@69 {
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compatible = "ti,cdce706";
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@@ -14,7 +14,7 @@ Optional properties:
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- reset-names : must contain "ahb"
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Example:
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crypto: crypto-engine@01c15000 {
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crypto: crypto-engine@1c15000 {
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compatible = "allwinner,sun4i-a10-crypto";
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reg = <0x01c15000 0x1000>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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