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iio: dac: ad3552r: add high-speed platform driver
Add High Speed ad3552r platform driver. The ad3552r DAC is controlled by a custom (fpga-based) DAC IP through the current AXI backend, or similar alternative IIO backend. Compared to the existing driver (ad3552r.c), that is a simple SPI driver, this driver is coupled with a DAC IIO backend that finally controls the ad3552r by a fpga-based "QSPI+DDR" interface, to reach maximum transfer rate of 33MUPS using dma stream capabilities. All commands involving QSPI bus read/write are delegated to the backend through the provided APIs for bus read/write. Reviewed-by: Nuno Sa <nuno.sa@analog.com> Signed-off-by: Angelo Dureghello <adureghello@baylibre.com> Reviewed-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20241028-wip-bl-ad3552r-axi-v0-iio-testing-v9-7-f6960b4f9719@kernel-space.org Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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committed by
Jonathan Cameron
parent
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commit
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@@ -6,9 +6,28 @@
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menu "Digital to analog converters"
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config AD3552R_HS
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tristate "Analog Devices AD3552R DAC High Speed driver"
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select AD3552R_LIB
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select IIO_BACKEND
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help
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Say yes here to build support for Analog Devices AD3552R
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Digital to Analog Converter High Speed driver.
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The driver requires the assistance of an IP core to operate,
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since data is streamed into target device via DMA, sent over a
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QSPI + DDR (Double Data Rate) bus.
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To compile this driver as a module, choose M here: the
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module will be called ad3552r-hs.
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config AD3552R_LIB
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tristate
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config AD3552R
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tristate "Analog Devices AD3552R DAC driver"
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depends on SPI_MASTER
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select AD3552R_LIB
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select IIO_BUFFER
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select IIO_TRIGGERED_BUFFER
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help
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@@ -4,7 +4,9 @@
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#
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# When adding new entries keep the list in alphabetical order
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obj-$(CONFIG_AD3552R) += ad3552r.o ad3552r-common.o
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obj-$(CONFIG_AD3552R_HS) += ad3552r-hs.o
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obj-$(CONFIG_AD3552R_LIB) += ad3552r-common.o
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obj-$(CONFIG_AD3552R) += ad3552r.o
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obj-$(CONFIG_AD5360) += ad5360.o
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obj-$(CONFIG_AD5380) += ad5380.o
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obj-$(CONFIG_AD5421) += ad5421.o
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529
drivers/iio/dac/ad3552r-hs.c
Normal file
529
drivers/iio/dac/ad3552r-hs.c
Normal file
File diff suppressed because it is too large
Load Diff
19
drivers/iio/dac/ad3552r-hs.h
Normal file
19
drivers/iio/dac/ad3552r-hs.h
Normal file
@@ -0,0 +1,19 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2024 Analog Devices Inc.
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* Copyright (c) 2024 Baylibre, SAS
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*/
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#ifndef __LINUX_PLATFORM_DATA_AD3552R_HS_H__
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#define __LINUX_PLATFORM_DATA_AD3552R_HS_H__
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struct iio_backend;
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struct ad3552r_hs_platform_data {
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int (*bus_reg_read)(struct iio_backend *back, u32 reg, u32 *val,
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size_t data_size);
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int (*bus_reg_write)(struct iio_backend *back, u32 reg, u32 val,
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size_t data_size);
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u32 bus_sample_data_clock_hz;
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};
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#endif /* __LINUX_PLATFORM_DATA_AD3552R_HS_H__ */
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@@ -127,8 +127,12 @@
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#define AD3552R_GAIN_SCALE 1000
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#define AD3552R_LDAC_PULSE_US 100
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#define AD3552R_CH0_ACTIVE BIT(0)
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#define AD3552R_CH1_ACTIVE BIT(1)
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#define AD3552R_MAX_RANGES 5
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#define AD3542R_MAX_RANGES 6
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#define AD3552R_QUAD_SPI 2
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extern const s32 ad3552r_ch_ranges[AD3552R_MAX_RANGES][2];
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extern const s32 ad3542r_ch_ranges[AD3542R_MAX_RANGES][2];
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