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Karol Gugala 9c049e21ac Merge pull request #662 from antmicro/svplugin-instead-of-uhdm

Replace deprecated Yosys UHDM plugin with SV plugin

2023-09-13 13:14:14 +02:00

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ci/Action: fix artifacts

2022-10-03 05:16:46 +02:00

action

add F4PGA Action

2022-09-29 00:18:54 +01:00

docs

docs/conf: update extlinks syntax

2023-04-12 12:13:37 +02:00

f4pga

Change deprecated Yosys UHDM plugin to SV plugin

2023-09-10 21:05:18 +02:00

scripts

docs/changes: add 8 (#636 )

2022-09-08 13:30:31 +02:00

test

add HDL tests

2022-09-30 00:46:02 +01:00

third_party

build(deps): bump third_party/make-env from 33b80bd to bc9ec7f (#656 )

2023-02-13 03:35:27 +00:00

.gitattributes

add .gitattributes and .gitcommit

2022-08-02 02:21:30 +02:00

.gitcommit

add .gitattributes and .gitcommit

2022-08-02 02:21:30 +02:00

.gitignore

f4pga: cleanup and style

2022-04-26 12:16:38 +02:00

.gitmodules

use intersphinx instead of adding submodules

2022-02-10 04:14:26 +01:00

LICENSE

docs: s/http:/https:/

2022-04-05 13:34:02 +02:00

README.md

readme: update shield syntax (badges/shields#8671 )

2023-02-07 23:07:08 +01:00

readthedocs.yml

add missing headers

2022-06-02 00:35:06 +02:00

README.md

FOSS Flows For FPGA (F4PGA) project

This is the top-level repository for the F4PGA project, which is a Workgroup under the CHIPS Alliance; consisting of members from different backgrounds, including FPGA vendors, industrial users and academia (see Documentation > Community); who collaborate to build a more open source and software-driven FPGA ecosystem (IP, tools and workflows) to drive the adoption of FPGAs in existing and new use cases, and eliminate barriers of entry.

Documentation > Getting started (for everyone)
F4PGA Examples (for users)
F4PGA Architecture Definitions (for developers)

Languages

Python 94.1%

Shell 2.9%

Tcl 2.4%

XSLT 0.3%

VHDL 0.1%

Other 0.2%