Some reserved memory (e.g. CSE reserved memory) might be in the
middle of usable physical memory. The current memory map caculation
could not handle this case. This patch fixed this issue.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: gdong1 <guo.dong@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Update CbSupportPei to consume the new library, so platform could provide
platform specific library instance to parse platform specif info.
And add a NULL library instance to pass build.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: gdong1 <guo.dong@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Add the following definition in the [BuildOptions] section in package DSC
files to disable APIs that are deprecated. As a result replaced PcdSet32
with PcdSet32S accordingly to make the build pass.
[BuildOptions]
*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
Cc: Prince Agyeman <prince.agyeman@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=163
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Ported MASM/GAS assembly files into NASM files and updated the inf
file to refer to NASM files.
This change has been tested with GCC 4.8 and VS2013 build.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Cc: Lee Leahy <leroy.p.leahy@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
CorebootPayloadPkg has switched to use the generic PciBus and
PciHostBridge driver form MdeModulePkg. As a result, the
non-enumeration drivers including PciBusNoEnumerationDxe and
PciRootBridgenoEnumerationDxe need to be removed.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Not all platforms have or support graphics. The ASSERT that the
frame buffer HOB is not NULL is fatal for these platforms. Convert
this into an if statement and make the related PcdSet* calls c
onditional on locating the frame buffer HOB.
Change-Id: Ibdc4bf5359571f3ce1555efcaf4657b8e363b2cd
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
The video console resolution related PCDs are required to be
initialized after switching to use the generic BdsDxe driver
in MdeModulePkg.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
CorebootModulePkg currently uses a hardcoded table for memory type
initialization. It might need to be adjusted by platform to reduce
the memory fragmentation. So changing to use PCDs rather than
constant values to facilitate the customization.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
CorebootPayloadPkg has been changed to use generic SerialDxe driver
from MdeModulePkg. As part of the clean-up, the overridden SerialDxe
and PciSioSerialDxe drivers in CorebootModulePkg need to be removed.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Pass the serial port baudrate, register stride, input clock rate and
ID from coreboot to CorebootPayloadPkg.
Change-Id: I37111d23216e4effa2909337af7e8a6de36b61f7
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Skip non-bridge devices which are not enabled either for memory or I/O
access.
Change-Id: I1a39c69a8556b6b9cefd1a2bb191f7e0744ddfb0
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Remove trailing white space from PciEnumeratorSupport.c.
Change-Id: Ia2f354151d46c09b140e2b42609d76fbbf8333f9
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Ensure communication between the host and the UEFI system running
CorebootPayloadPkg. In cases where the host has flow control enabled
and the serial connection is providing the flow control signals, the
host will not be able to send data to the UEFI system because DTR and
RTS are not present. The host may also discard all output data from
the UEFI system because DTR is not present. By setting DTR and RTS
in the UART initialization code this case works properly.
Change-Id: I393f57104d111472cafcae01d4e43d4ea837be3b
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Copy the driver from MdeModulePkg/Universal/SerialDxe. Add
PlatformHookLib to the Library section of the .inf file to adjust the
PCDs for the UART.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Copy the driver from MdeModulePkg/Bus/Pci/PciSioSerialDxe. Add
PlatformHookLib to the Library section of the .inf file to adjust the
PCDs for the UART.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Remove the references to DuetPkg. Copy the files from revision
ffea0a2ce2 of DuetPkg into
CorebootModulePkg. The components include:
* PciBusNoEnumerationDxe
* PciRootBridgeNoEnumerationDxe
* SataControllerDxe
TEST=Build and run on Galileo Gen2
Change-Id: Id07185f7e226749e5f7c6b6cb427bcef7eac8496
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Dereferencing pMemTableSize in debug statement displays bad values when
it is set to NULL. Display the actual table size value instead.
TEST=Build and run on Galileo Gen2
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Verify the register address in the FADT.
TEST=Build and run on Galileo Gen2 when the FADT was not present.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Remove EFI_RESOURCE_ATTRIBUTE_TESTED when reporting lower 640KB memory
so that the coreboot header is not erased before being processed
by CbParseMemoryInfo. This change is needed for compatibility
with SVN revision 18146.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18234 6f19259b-4bc3-4df7-8a09-765794883524
This patch will get power management event register address and power management GPE enable register address.
Add missing code in CbParseLib.c.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17791 6f19259b-4bc3-4df7-8a09-765794883524
gdong1
Maurice Ma
Leahy, Leroy P
Scott Duplichan