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Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
98 lines
4.2 KiB
C
98 lines
4.2 KiB
C
/** @file
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Definition of Processor Specific Data HOB.
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Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef RISC_V_PROCESSOR_SPECIFIC_HOB_DATA_H_
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#define RISC_V_PROCESSOR_SPECIFIC_HOB_DATA_H_
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#include <Uefi.h>
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#include <IndustryStandard/SmBios.h>
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#include <SmbiosProcessorSpecificData.h>
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#define TO_BE_FILLED 0
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#define TO_BE_FILLED_BY_VENDOR 0
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#define TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER 0
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#define TO_BE_FILLED_BY_CODE 0
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#pragma pack(1)
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///
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/// RISC-V processor specific data HOB
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///
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typedef struct {
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EFI_GUID ParentProcessorGuid;
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UINTN ParentProcessorUid;
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EFI_GUID CoreGuid;
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VOID *Context; // The additional information of this core which
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// built in PEI phase and carried to DXE phase.
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// The content is processor or platform specific.
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SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData;
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} RISC_V_PROCESSOR_SPECIFIC_HOB_DATA;
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///
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/// RISC-V SMBIOS type 4 (Processor) GUID data HOB
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///
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typedef struct {
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EFI_GUID ProcessorGuid;
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UINTN ProcessorUid;
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SMBIOS_TABLE_TYPE4 SmbiosType4Processor;
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UINT16 EndingZero;
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} RISC_V_PROCESSOR_TYPE4_HOB_DATA;
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#define RISC_V_CACHE_INFO_NOT_PROVIDED 0xFFFF
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#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK 0x7
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#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 0x01
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#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 0x02
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#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3 0x03
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#define RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION 3
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#define RISC_V_CACHE_CONFIGURATION_SOCKET_MASK (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
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#define RISC_V_CACHE_CONFIGURATION_SOCKET_SOCKETED (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
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#define RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION 5
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#define RISC_V_CACHE_CONFIGURATION_LOCATION_MASK (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
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#define RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL (0x0 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
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#define RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL (0x1 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
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#define RISC_V_CACHE_CONFIGURATION_LOCATION_RESERVED (0x2 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
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#define RISC_V_CACHE_CONFIGURATION_LOCATION_UNKNOWN (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
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#define RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION 7
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#define RISC_V_CACHE_CONFIGURATION_ENABLE_MASK (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
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#define RISC_V_CACHE_CONFIGURATION_ENABLED (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
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#define RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION 8
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#define RISC_V_CACHE_CONFIGURATION_MODE_MASK (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
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#define RISC_V_CACHE_CONFIGURATION_MODE_WT (0x0 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
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#define RISC_V_CACHE_CONFIGURATION_MODE_WB (0x1 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
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#define RISC_V_CACHE_CONFIGURATION_MODE_VARIES (0x2 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
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#define RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
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///
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/// RISC-V SMBIOS type 7 (Cache) GUID data HOB
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///
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typedef struct {
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EFI_GUID ProcessorGuid;
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UINTN ProcessorUid;
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SMBIOS_TABLE_TYPE7 SmbiosType7Cache;
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UINT16 EndingZero;
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} RISC_V_PROCESSOR_TYPE7_HOB_DATA;
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///
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/// RISC-V SMBIOS type 7 (Cache) GUID data HOB
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///
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typedef struct {
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RISC_V_PROCESSOR_TYPE4_HOB_DATA *Processor;
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RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1Cache;
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RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2Cache;
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RISC_V_PROCESSOR_TYPE7_HOB_DATA *L3Cache;
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} RISC_V_PROCESSOR_SMBIOS_HOB_DATA;
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#pragma pack()
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#endif
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