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d2339f3c5f
The VPU clock divisor has changed in this commit: https://github.com/raspberrypi/firmware/commit/1e5456a, thus breaking the mini UART clock divisor calculation on the Pi 4. Fix this by reading the core clock from the mailbox instead. Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com> Reviewed-by: Pete Batard <pete@akeo.ie> Tested-by: Pete Batard <pete@akeo.ie>
177 lines
4.6 KiB
ArmAsm
177 lines
4.6 KiB
ArmAsm
/** @file
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*
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* Copyright (c) 2020, Andrei Warkentin <andrey.warkentin@gmail.com>
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* Copyright (c) 2019-2020, Pete Batard <pete@akeo.ie>
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* Copyright (c) 2016, Linaro Limited. All rights reserved.
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* Copyright (c) 2011-2020, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include <AsmMacroIoLibV8.h>
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#include <Library/ArmLib.h>
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#include <IndustryStandard/Bcm2836.h>
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#include <IndustryStandard/RpiMbox.h>
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.macro drain
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mov x5, #RPI_MBOX_MAX_TRIES
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0: ldr w6, [x4, #BCM2836_MBOX_STATUS_OFFSET]
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tbnz w6, #BCM2836_MBOX_STATUS_EMPTY, 1f
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dmb ld
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ldr wzr, [x4, #BCM2836_MBOX_READ_OFFSET]
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subs x5, x5, #1
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b.ne 0b
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1:
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.endm
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.macro poll, status
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mov x5, #RPI_MBOX_MAX_TRIES
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0: ldr w6, [x4, #BCM2836_MBOX_STATUS_OFFSET]
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tbz w6, #\status, 1f
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dmb ld
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subs x5, x5, #1
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b.ne 0b
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1:
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.endm
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.macro run, command_buffer
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adr x0, \command_buffer
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orr x0, x0, #RPI_MBOX_VC_CHANNEL
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add x0, x0, x1
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poll BCM2836_MBOX_STATUS_FULL
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str w0, [x4, #BCM2836_MBOX_WRITE_OFFSET]
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dmb sy
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poll BCM2836_MBOX_STATUS_EMPTY
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dmb sy
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ldr wzr, [x4, #BCM2836_MBOX_READ_OFFSET]
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dmb ld
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.endm
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ASM_FUNC (ArmPlatformPeiBootAction)
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mov x1, #FixedPcdGet64 (PcdDmaDeviceOffset)
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orr x0, x0, #RPI_MBOX_VC_CHANNEL
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// x1 holds the value of PcdDmaDeviceOffset throughout this function
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MOV32 (x4, BCM2836_MBOX_BASE_ADDRESS)
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drain
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run .Lmeminfo_buffer
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ldr w0, .Lmembase
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adr x2, mSystemMemoryBase
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str x0, [x2]
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ldr w0, .Lmemsize
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sub x0, x0, #1
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adr x2, mSystemMemoryEnd
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str x0, [x2]
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run .Lvcinfo_buffer
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ldr w0, .Lvcbase
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adr x2, mVideoCoreBase
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str x0, [x2]
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ldr w0, .Lvcsize
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adr x2, mVideoCoreSize
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str x0, [x2]
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run .Lrevinfo_buffer
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ldr w0, .Lrevision
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adr x2, mBoardRevision
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str w0, [x2]
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run .Lclkinfo_buffer
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ldr w0, .Lfrequency
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adr x2, _gPcd_BinaryPatch_PcdSerialClockRate
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str w0, [x2]
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ret
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.align 4
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.Lmeminfo_buffer:
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.long .Lmeminfo_size
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.long 0x0
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.long RPI_MBOX_GET_ARM_MEMSIZE
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.long 8 // buf size
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.long 0 // input len
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.Lmembase:
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.long 0 // mem base
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.Lmemsize:
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.long 0 // mem size
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.long 0 // end tag
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.set .Lmeminfo_size, . - .Lmeminfo_buffer
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.align 4
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.Lvcinfo_buffer:
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.long .Lvcinfo_size
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.long 0x0
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.long RPI_MBOX_GET_VC_MEMSIZE
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.long 8 // buf size
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.long 0 // input len
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.Lvcbase:
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.long 0 // videocore base
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.Lvcsize:
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.long 0 // videocore size
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.long 0 // end tag
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.set .Lvcinfo_size, . - .Lvcinfo_buffer
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.align 4
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.Lrevinfo_buffer:
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.long .Lrevinfo_size
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.long 0x0
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.long RPI_MBOX_GET_BOARD_REVISION
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.long 4 // buf size
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.long 0 // input len
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.Lrevision:
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.long 0 // revision
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.long 0 // end tag
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.set .Lrevinfo_size, . - .Lrevinfo_buffer
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.align 4
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.Lclkinfo_buffer:
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.long .Lclkinfo_size
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.long 0x0
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.long RPI_MBOX_GET_CLOCK_RATE
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.long 8 // buf size
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.long 4 // input len
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.long 4 // clock id: 0x04 = Core/VPU
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.Lfrequency:
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.long 0 // frequency
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.long 0 // end tag
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.set .Lclkinfo_size, . - .Lclkinfo_buffer
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//UINTN
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//ArmPlatformGetPrimaryCoreMpId (
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// VOID
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// );
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ASM_FUNC (ArmPlatformGetPrimaryCoreMpId)
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MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore))
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ret
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//UINTN
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//ArmPlatformIsPrimaryCore (
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// IN UINTN MpId
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// );
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ASM_FUNC (ArmPlatformIsPrimaryCore)
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mov x0, #1
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ret
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//UINTN
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//ArmPlatformGetCorePosition (
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// IN UINTN MpId
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// );
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// With this function: CorePos = (ClusterId * 4) + CoreId
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ASM_FUNC (ArmPlatformGetCorePosition)
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and x1, x0, #ARM_CORE_MASK
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and x0, x0, #ARM_CLUSTER_MASK
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add x0, x1, x0, LSR #6
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ret
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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