Benjamin Doron 69e6a5e160 MinPlatformPkg/PciHostBridgeLibSimple: Fix Mem.Limit assignment ...

In the case where the root bridge's Mem.Limit is the base address of
PCIe MMIO, subtract one to make a valid end address.

This fixes an issue where CpuDxe returns "Length(0x50000001) is not
aligned!" when PciHostBridgeDxe attempts to make this range uncacheable.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

2021-07-29 08:31:26 +08:00

..

PciHostBridgeLibSimple

MinPlatformPkg/PciHostBridgeLibSimple: Fix Mem.Limit assignment

2021-07-29 08:31:26 +08:00

PciSegmentInfoLibSimple

MinPlatformPkg PciSegmentInfoLibSimple: Update GetPciSegmentInfo() API

2020-06-26 11:26:23 +08:00