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https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html NOTE: The following files with a missing license are not modified by this patch series. These files will be address in a future patch. Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
47 lines
939 B
ArmAsm
47 lines
939 B
ArmAsm
#
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# Copyright (c) 2018, Linaro Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#
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#include <AsmMacroIoLibV8.h>
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#include <Library/ArmLib.h>
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.text
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.align 3
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ASM_FUNC(ArmPlatformPeiBootAction)
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ret
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//UINTN
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//ArmPlatformIsPrimaryCore (
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// IN UINTN MpId
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// );
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ASM_FUNC(ArmPlatformIsPrimaryCore)
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MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask))
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and x0, x0, x1
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MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore))
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cmp w0, w1
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cset x0, eq
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ret
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//UINTN
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//ArmPlatformGetPrimaryCoreMpId (
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// VOID
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// );
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ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
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MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore))
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ret
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//UINTN
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//ArmPlatformGetCorePosition (
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// IN UINTN MpId
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// );
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// With this function: CorePos = (ClusterId * 4) + CoreId
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ASM_FUNC(ArmPlatformGetCorePosition)
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and x1, x0, #ARM_CORE_MASK
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and x0, x0, #ARM_CLUSTER_MASK
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add x0, x1, x0, LSR #6
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ret
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