diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
index d8413d28..a9b7e446 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
@@ -1,7 +1,7 @@
 /** @file
   Implementation of Fsp Misc UPD Initialization.
 
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -11,7 +11,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <Library/DebugLib.h>
 #include <Library/PciLib.h>
 #include <Library/PeiLib.h>
-
 #include <FspEas.h>
 #include <FspmUpd.h>
 #include <FspsUpd.h>
@@ -34,24 +33,21 @@ PeiFspMiscUpdUpdatePreMem (
 {
   EFI_STATUS                        Status;
   UINTN                             VariableSize;
-  VOID                              *MemorySavedData;
+  VOID                              *FspNvsBufferPtr;
   UINT8                             MorControl;
   VOID                              *MorControlPtr;
 
   //
   // Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths.
   //
-  VariableSize = 0;
-  MemorySavedData = NULL;
-  Status = PeiGetVariable (
-             L"MemoryConfig",
-             &gFspNonVolatileStorageHobGuid,
-             &MemorySavedData,
-             &VariableSize
-             );
-  DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" gFspNonVolatileStorageHobGuid - %r\n", Status));
-  DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize));
-  FspmUpd->FspmArchUpd.NvsBufferPtr = MemorySavedData;
+  FspNvsBufferPtr   = NULL;
+  VariableSize  = 0;
+  Status = PeiGetLargeVariable (L"FspNvsBuffer", &gFspNvsBufferVariableGuid, &FspNvsBufferPtr, &VariableSize);
+  if (Status == EFI_SUCCESS) {
+    DEBUG ((DEBUG_INFO, "Get L\"FspNvsBuffer\" gFspNvsBufferVariableGuid - %r\n", Status));
+    DEBUG ((DEBUG_INFO, "FspNvsBuffer Size - 0x%x\n", VariableSize));
+    FspmUpd->FspmArchUpd.NvsBufferPtr = FspNvsBufferPtr;
+  }
 
   if (FspmUpd->FspmArchUpd.NvsBufferPtr != NULL) {
     //
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
index e4a657c5..eac9344b 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
@@ -1,7 +1,7 @@
 ## @file
 #  Provide FSP wrapper platform related function.
 #
-# Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2021 Intel Corporation. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -74,7 +74,6 @@
   PchInfoLib
   PchHsioLib
   PchPcieRpLib
-  MemoryAllocationLib
   SiPolicyLib
   PeiLib
 
@@ -134,9 +133,11 @@
   gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAudioConnector
 
   gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress
+  gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort4ClkInfo
 
 [Guids]
-  gFspNonVolatileStorageHobGuid                 ## CONSUMES
+  gFspNvsBufferVariableGuid                     ## CONSUMES
   gTianoLogoGuid                                ## CONSUMES
   gEfiMemoryOverwriteControlDataGuid
 
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
index c9dfb17e..3764f7c3 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
@@ -431,8 +431,8 @@ SiliconPolicyUpdatePreMem (
   SA_MISC_PEI_PREMEM_CONFIG     *MiscPeiPreMemConfig;
   MEMORY_CONFIG_NO_CRC          *MemConfigNoCrc;
   VOID                          *Buffer;
-  UINTN                         VariableSize;
-  VOID                          *MemorySavedData;
+  UINTN                         FspNvsBufferSize;
+  VOID                          *FspNvsBufferPtr;
   UINT8                         SpdAddressTable[4];
 
   DEBUG((DEBUG_INFO, "\nUpdating Policy in Pre-Mem\n"));
@@ -463,18 +463,13 @@ SiliconPolicyUpdatePreMem (
       // Note: AmberLake FSP does not implement the FSPM_ARCH_CONFIG_PPI added in FSP 2.1, hence
       // the platform specific S3DataPtr must be used instead.
       //
-      VariableSize = 0;
-      MemorySavedData = NULL;
-      Status = PeiGetVariable (
-                L"MemoryConfig",
-                &gFspNonVolatileStorageHobGuid,
-                &MemorySavedData,
-                &VariableSize
-                );
-      DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" gFspNonVolatileStorageHobGuid - %r\n", Status));
-      DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize));
-      if (!EFI_ERROR (Status)) {
-        MiscPeiPreMemConfig->S3DataPtr = MemorySavedData;
+      FspNvsBufferPtr   = NULL;
+      FspNvsBufferSize  = 0;
+      Status = PeiGetLargeVariable (L"FspNvsBuffer", &gFspNvsBufferVariableGuid, &FspNvsBufferPtr, &FspNvsBufferSize);
+      if (Status == EFI_SUCCESS) {
+        DEBUG ((DEBUG_INFO, "Get L\"FspNvsBuffer\" gFspNvsBufferVariableGuid - %r\n", Status));
+        DEBUG ((DEBUG_INFO, "FspNvsBuffer Size - 0x%x\n", FspNvsBufferSize));
+        MiscPeiPreMemConfig->S3DataPtr = FspNvsBufferPtr;
       }
 
       //
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
index 0a8cf91b..4dcc0001 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
@@ -52,7 +52,7 @@
   gHsioPciePreMemConfigGuid                     ## CONSUMES
   gHsioSataPreMemConfigGuid                     ## CONSUMES
   gSaMiscPeiPreMemConfigGuid                    ## CONSUMES
-  gFspNonVolatileStorageHobGuid                 ## CONSUMES
+  gFspNvsBufferVariableGuid                     ## CONSUMES
   gIoApicConfigGuid                             ## CONSUMES
   gHpetPreMemConfigGuid                         ## CONSUMES
   gLockDownConfigGuid