45 Commits

Author SHA1 Message Date
spkamat
a6c549e4b5 Update shell related documentation (#212)
Added information related to platform specific shell commands and
enabling shell in release build.

Signed-off-by: Sachin Kamat <sachin.kamat@intel.com>
2025-06-24 07:56:22 -07:00
Sabryna
2d67e89703 Update basic info, tool version & amend parts of tutorials (#211)
Visual Studio Supported version: 2015-2022
Ubuntu latest stable version: 22.04
Intel UDK link deceprated, replaced with updated direct links
Other minor updates to the documentations

Signed-off-by: Syahirah Sabryna <nur.syahirah.sabryna.mohmad@intel.com>
2025-06-16 11:05:45 +08:00
Atharva Lele
2dd1feb4db Update formatting for GPIO configuration doc (#180)
Make minor formatting changes

Signed-off-by: Atharva Lele <atharva.lele@intel.com>
2023-05-23 12:01:05 -07:00
Atharva Lele
3cd403e1a0 Enhance GPIO configuration documentation (#179)
- Move some documentation to Developer's Guide
- Add documentation on how CfgDataTool processes GPIO configs
  and creates the final configuration binary

Signed-off-by: Atharva Lele <atharva.lele@intel.com>
2023-05-23 09:57:16 -07:00
tsaikevin
ac61f154ec Add Up Xtreme i12 capsule update information (#176)
Add instructions to create capsulte and trigger firmware update.

Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
2023-05-09 17:38:27 -07:00
Atharva Lele
3d16dd6432 Add SBL performance table (SBLT) details to docs (#177)
Adds relevant info for SBL performance table that will be
added to the Firmware Performance Data Table with the PR
noted below.

https://github.com/slimbootloader/slimbootloader/pull/1890

Also adds a section on how to obtain performance measurements
from the OsLoader shell.

Signed-off-by: Atharva Lele <atharva.lele@intel.com>
2023-05-02 19:02:22 -07:00
Atharva Lele
dbde6f11c2 Enhance docs and clean up warnings in several docs (#169)
- Make footer copyright year update automatically
- Add clarification about EPLD region
- Add heading to build tool doc
- Clean up warnings about section links, length of underlines, etc.
- Adjust whitespace in Build System doc
- Fix reference to key management section

Signed-off-by: Atharva Lele <atharva.lele@intel.com>
2023-04-04 14:30:28 -07:00
Atharva Lele
d7b1930cf4 Enhance build system documentation (#167)
* Move build process to build system doc

Place it in a more appropriate section

Signed-off-by: Atharva Lele <atharva.lele@intel.com>

* Enhance build system documentation

- Add details on OsLoader and FW update packaging
- Add section on post build image construction
- Add section on patching of stages
- Add section on including SBL containers in final SBL image

Signed-off-by: Atharva Lele <atharva.lele@intel.com>

---------

Signed-off-by: Atharva Lele <atharva.lele@intel.com>
2023-03-08 16:31:46 -08:00
Atharva Lele
e017ecd527 Enhance memory map documentation (#165)
- Add details on types of memory and memory allocation
- Add details on memory allocation libraries used

Signed-off-by: Atharva Lele <atharva.lele@intel.com>
2023-02-28 09:47:49 -08:00
Atharva Lele
c44a9a9039 Update boot flow doc (#166)
Add detail on what data is passed from Stage 2 to payload
and add payload function signature

Signed-off-by: Atharva Lele <atharva.lele@intel.com>
2023-02-27 19:20:39 -08:00
Atharva Lele
8d40a31500 Enhance Boot Flow documentation (#162)
- Add details about each stage and what each stage does
- Add details about what data is passed and how it is passed
  between stages
- Add information about Loader Global Data and how it is used
  by the bootloader

Signed-off-by: Atharva Lele <atharva.lele@intel.com>
2023-02-17 17:04:56 -08:00
Atharva Lele
bcea38bb10 Add build details for each stage (#163)
Add details about how each stage is packaged and what each stage
contains to the build system documentation.

Signed-off-by: Atharva Lele <atharva.lele@intel.com>
2023-02-17 17:04:42 -08:00
bejeanmo
1287869e62 Added Stage 1 Temp Ram memory map. (#161)
* Added Stage 1 Temp Ram memory map.

Added a table showing the temporary memory map during Stage 1 execution.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>

* Correct Top of Low Mem to Top of 4GB.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>

---------

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
2023-02-14 11:30:30 -08:00
sean-m-mcginn
39319deba6 Add documentation for firmware resiliency (#151)
* Add documentation for firmware resiliency

This change adds a section for firmware resiliency
as well as updates existing sections that are related
to firmware resiliency

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>

* Fix grammatical errors in resiliency and recovery section

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>

* Add in test tool tutorials for SBL resiliency

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>

* Add in block diagrams for SBL resiliency

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>

* Make minor improvements to resiliency and update sections

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>

* Mention non-overlapping region requirement for FW update capsule tool

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>

* Give example for building FW update capsule with TMAC:IPFW

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>

* Add note that corruptcomp tool should be disabled in prod builds

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-01-13 13:40:04 -08:00
Atharva Lele
8fc7c9a09c Fix OsLoader flow image file name (#156)
Fix filename case for (PNG --> png)

Signed-off-by: Atharva Lele <atharva.lele@intel.com>

Signed-off-by: Atharva Lele <atharva.lele@intel.com>
2022-12-14 17:16:33 -08:00
Atharva Lele
f3f8dd4fc1 Enhance Payload page and add OsLoader page (#155)
* Elaborate on payload types

- Add a few details to the payload types section
- Remove Android and hypervisor from OsLoader intro

Signed-off-by: Atharva Lele <atharva.lele@intel.com>

* Add OsLoader section to Developer's Guide

Add details about OsLoader and OsLoader code flow

Signed-off-by: Atharva Lele <atharva.lele@intel.com>
Signed-off-by: Sachin Kamat <sachin.kamat@intel.com>

Signed-off-by: Atharva Lele <atharva.lele@intel.com>
Signed-off-by: Sachin Kamat <sachin.kamat@intel.com>
2022-12-14 17:01:47 -08:00
Atharva Lele
9170797fab IAS and other cleanup (#153)
* GenContainer: bold the default container type

Signed-off-by: Atharva Lele <atharva.lele@intel.com>

* Add container type to VxWorks create container command

Signed-off-by: Atharva Lele <atharva.lele@intel.com>

* Remove ACRN page from the How-Tos index

Signed-off-by: Atharva Lele <atharva.lele@intel.com>

* Remove fastboot page from the How-Tos index

Signed-off-by: Atharva Lele <atharva.lele@intel.com>

* Update image on Container tool to remove spell check lines

Signed-off-by: Atharva Lele <atharva.lele@intel.com>

* Change IAS reference to container in build system doc

Signed-off-by: Atharva Lele <atharva.lele@intel.com>

* Replace IAS references with container in Change Boot Options doc

Signed-off-by: Atharva Lele <atharva.lele@intel.com>

Signed-off-by: Atharva Lele <atharva.lele@intel.com>
2022-12-09 17:04:58 -08:00
spkamat
fc217eed39 Update shell interface section (#144)
Shell interface section updated with the latest supported commands.

Signed-off-by: Sachin Kamat <sachin.kamat@intel.com>

Signed-off-by: Sachin Kamat <sachin.kamat@intel.com>
2022-08-23 07:33:32 -07:00
jinjhuli
e00bdaf589 Add FSP, VBT and microcode upgrade guide (#117)
Add ingredients upgrade guide in developer's guide section.

Signed-off-by: jinjhuli <jin.jhu.lim@intel.com>
2021-06-14 08:13:29 -07:00
James Gutbub
77457660fa Resolve some stale example outputs (#104)
There are a few places in the documentation where
some older output is being displayed which is
causing some confusion for readers. Update it to
reflect current code.

Signed-off-by: James Gutbub <james.gutbub@intel.com>
2020-12-10 10:49:00 -08:00
Sindhura Grandhi
11764cc3bf Making some Configuration Edits. (#99)
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
2020-10-21 15:56:25 -07:00
Ravi Rangarajan
559fb1c96c Added size attribute to value field in config spec (#98)
Signed-off-by: Ravi Rangarajan <ravi.p.rangarajan@intel.com>
2020-09-24 14:59:50 -07:00
Ravi Rangarajan
f6b54e73c8 Updated FSP github links (#97) 2020-09-23 15:58:08 -07:00
Ravi Rangarajan
c899492b68 Doc updates (#96)
* Added Debugging with Intel System Studio

* Changed IAS to Boot Image with Container info
2020-09-23 14:58:58 -07:00
Ravi Rangarajan
dfd5838732 Cleaned up config sections and added x-ref links (#92) 2020-09-15 09:39:54 -07:00