coreboot

mirror of https://github.com/Dasharo/coreboot.git synced 2026-03-06 14:43:26 -08:00

Files

Arthur Heymans 6a8c93416a soc/intel/xeon-sp/spr: Hook up public FSP bin and headers

vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/ is still needed due to
Intel FSP repo does not ship all header files.

TEST=Build and boot on intel/archercity CRB

Upstream-Status: Backport [CB:80360]
Change-Id: I778d3535c273dff653330518653bdefcb45e66f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80360
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>

2025-09-11 12:38:04 +02:00

config.asrock.spc741d8

mb/asrock: Add SPR 1S server board ASRock Rack SPC741D8-2L2T/BCM

2025-09-11 12:38:03 +02:00

config.intel.cpx.crb

configs: Add builder config to create a working Cedar Island CRB

2020-03-26 18:15:04 +00:00

config.intel.crb.ac

soc/intel/xeon-sp/spr: Hook up public FSP bin and headers

2025-09-11 12:38:04 +02:00

config.intel.crb.avc

configs/builder: Update PBP path for Gen6 Xeon-SP boards