Roger Wang
9992a98c67
spd/lp5: Add Hynix memory part
...
Add Micron memory part H58G56CK8BX146 to LP5 global list.
And Regenerate the SPD files for the SoC. The specification
is attached in issue tracker.
BUG=b:367841051
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I2a003aad32bca9ae5438973ecf0d7872481fee20
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2024-11-30 05:03:59 +00:00
Amanda Huang
2626bcf5f8
spd/lp5: Add SPD for MT62F2G32D4DS-020 WT:F
...
Add MT62F2G32D4DS-020 WT:F in the memory_parts.json and re-generate
the SPD
BUG=b:373394046
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I592cebf972df1e54555561b243eed42af83342e3
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com >
Reviewed-by: Subrata Banik <subratabanik@google.com >
Reviewed-by: Pranava Y N <pranavayn@google.com >
2024-10-17 10:05:13 +00:00
Subrata Banik
d0d41f28d3
util/spd_tools: Add Intel Panther Lake (PTL) platform
...
This patch add support for PTL platform to the `spd_tools`.
This would be useful to create dynamic SPD for fatcat variants.
BUG=b:347669091
TEST=Able to generate SPD for LP5 DRAM part.
Change-Id: I55c3f49439fb1ad961c6866f03594431e54279b9
Signed-off-by: Subrata Banik <subratabanik@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83822
Reviewed-by: Eric Lai <ericllai@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com >
2024-08-09 09:24:18 +00:00
Leo Chou
c96f3c24fd
spd/lp4x: Add SPD for Zilia SDVB8D8A34XGCL3N3T
...
This adds support for Zilia SDVB8D8A34XGCL3N3T LP4x chips.
Generatd SPD data with:
util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x
BRANCH=None
BUG=344482259
Change-Id: I4408e62ab2a15002960c1d9659ab6af45bd7f7bb
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
Reviewed-by: Eric Lai <ericllai@google.com >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2024-06-07 18:36:42 +00:00
Kun Liu
aa65c8ed95
spd/lp5: Add SPDs for MT62F1G32D2DS-023 WT:C and K3KL8L80DM-MGCU
...
Add MT62F1G32D2DS-023 WT:C and K3KL8L80DM-MGCU
in the memory_parts.json and re-generate the SPD
Micron:MT62F1G32D2DS-023 WT:C
Samsung:K3KL8L80DM-MGCU
BUG=b:337730271
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: Ic5c3ed46829330f83e144cf8d18be6fa808431aa
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com >
Reviewed-by: Eric Lai <ericllai@google.com >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2024-06-07 15:59:38 +00:00
Daniel Peng
9a01263952
spd/lp4x: Add SPD for CXDB4CBAM-ML-A in parts_spd_manifest.generated.txt
...
Generate initial SPD matched for CXMT CXDB4CBAM-ML-A.
BUG=b:304932936
TEST=make -C util/spd_tools
util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x
Change-Id: Ia33a94a1784f865b4776ad9107e25e87420f944f
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78891
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com >
Reviewed-by: Eric Lai <ericllai@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-11-13 06:16:55 +00:00
Stanley Wu
2a37ba6029
spd/lp4x: Generate initial SPD for CXDB4ABAM-ML
...
Generate initial SPD for CXMT CXDB4ABAM-ML
BUG=b:290154780
TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x
Change-Id: I0de6b128f05abf2fbd4b785818268b69338ed45a
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@gmail.com >
Reviewed-by: Derek Huang <derekhuang@google.com >
2023-08-09 13:43:59 +00:00
Wisley Chen
3ffda28c8b
spd/lp4x: Generate initial SPD for K4UCE3Q4AB-MGCL
...
Generate initial SPD for Samsung K4UCE3Q4AB-MGCL
BUG=b:281943392
BRANCH=firmware-brya-14505.B
TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x
Change-Id: I0a860f3f9c307e70f63a53435cc26e6f278d0a17
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@gmail.com >
2023-06-03 20:37:05 +00:00
Karthikeyan Ramasubramanian
9e45e32420
util/spd_tools: Add support for Phoenix platform
...
Update spd_gen and part_id_gen utilities to accommodate Phoenix platform
so that SPD can be generated for the memory parts used in that platform.
SPD requirements for Phoenix and Mendocino platforms are identical.
BUG=b:273383819
TEST=Run spd_gen and ensure that both Mendocino and Phoenix platforms
share the platform manifest for LP5 memory parts.
Change-Id: I7a12f73065864f08db8922c1a69eb503865a25b1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Jon Murphy <jpmurphy@google.com >
2023-04-05 10:01:15 +00:00
John Su
06a4cb437c
spd/lp5: Add 2 Micron memory parts
...
Add Micron memory part MT62F1G32D2DS-023 and MT62F2G32D4DS-023 to LP5
global list. Attributes are derived from CCM005-1974498342-145. Also,
regenerate the SPD files for the SoC.
BUG=b:271188237
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I6675a68b7a515bd6d21db3ea2da762b06dee017a
Signed-off-by: John Su <john_su@compal.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2023-03-10 13:46:26 +00:00
John Su
79375d09e0
spd/lp5: Modify Hynix LPDDR5X memory Speed
...
Because SPD tool now supports 8533Mbps, so modify speed to regenerate
the SPD file for Hynix H58G66BK8BX067 and H58G56BK8BX068.
BUG=b:263189532, b:270629852
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I813fc1495836dbe33de426cf41a1f58c8e8a046e
Signed-off-by: John Su <john_su@compal.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73251
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com >
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com >
Reviewed-by: Chao Gui <chaogui@google.com >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
2023-03-04 04:35:50 +00:00
Subrata Banik
c467995bc2
spd/lp5: Add SPD for Samsung K3KL6L60GM-MGCT
...
This adds support for Samsung K3KL6L60GM-MGCT chips.
BUG=b:270708359
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: I64b2623bc8da94c1fd3a935ec5368cdc6e76505b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com >
Reviewed-by: Kapil Porwal <kapilporwal@google.com >
2023-03-02 11:43:31 +00:00
Jamie Chen
47f84d3a24
spd/lp5: Add new part H58G56BK8BX068
...
HYNIX H58G56BK8BX068 will be used for omnigul.
Add it to the parts list and regenerate the SPDs using spd_gen.
BUG=b:264340545
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: Id4adbaf7611e34107522df988482d9efd229d514
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72967
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2023-02-15 13:10:55 +00:00
Jamie Chen
7bbe138848
spd/lp5: Add new part H58G66BK8BX067
...
Micron H58G66BK8BX067 will be used for omnigul.
Add it to the parts list and regenerate the SPDs using spd_gen.
BUG=b:264340545
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: Ida422b17d7abfd130a80a28e49a1fa1b70043adf
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72885
Reviewed-by: Subrata Banik <subratabanik@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-02-09 14:52:45 +00:00
Johnny Li
7866193eee
spd/ddr4: Correct Hynix ddr4 part number from H5AG36EXNDX019 to H5AG36EXNDX017
...
Correct Hynix ddr4 part number H5AG36EXNDX019 to H5AG36EXNDX017 by Hynix Memory spec.
BUG=b:236739240
BRANCH=Volteer
TEST="util/spd_tools/bin/spd_gen memory_parts.json ddr4" and verify it builds successfully.
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com >
Change-Id: I6195fa1402691afc303f5223de48f552660cd97f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71159
Reviewed-by: Tarun Tuli <taruntuli@google.com >
Reviewed-by: Zhuohao Lee <zhuohao@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-12-24 23:35:31 +00:00
Frank Wu
3a4e201a21
spd/lp5: Update memory configuration of H9JCNNNFA5MLYR-N6E
...
Update bitWidthPerChannel in memory_parts.json and re-generate the SPD.
Then the device boots successfully with DDR H9JCNNNFA5MLYR-N6E.
BUG=b:261530632
BRANCH=None
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: Ib78c2e28394206b59c41b6b28cf24d8a756f7ae9
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com >
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2022-12-15 14:28:02 +00:00
EricKY Cheng
3a15fd1621
spd/lp5: Re-generate the SPD data
...
Re-generate Hynix H58G66BK7BX067 and H58G56BK7BX068 data
with current spd_tools.
BUG=b:243337816
BRANCH=None
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com >
Change-Id: I19ae0477dea64f2cdd37b6aa51eadd6957c54059
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com >
2022-10-28 12:06:29 +00:00
Frank Wu
afd2f6ed62
spd/lp5: Add new memory configuration of H9JCNNNFA5MLYR-N6E
...
Add Hynix H9JCNNNFA5MLYR-N6E in the memory_parts.json and re-generate
the SPD.
BUG=b:250470704
BRANCH=None
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com >
Change-Id: I9926a5859cf060e0bfa903f47d8a98c8d6115579
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Jon Murphy <jpmurphy@google.com >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Chao Gui <chaogui@google.com >
2022-10-20 16:24:06 +00:00
EricKY Cheng
a261502de5
spd/lp5: Add new memory configuration of H58G66BK7BX067 and H58G56BK7BX068
...
Add Hynix H58G66BK7BX067 and H58G56BK7BX068 in the
memory_parts.json and re-generate the SPD.
BUG=b:243337816
BRANCH=None
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com >
Change-Id: I8d6aac3ecec36b126e7e41d6c9475695aa7a26b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Jon Murphy <jpmurphy@google.com >
2022-10-13 17:06:20 +00:00
Robert Zieba
de6ecd0101
util/spd_tools: Change Mendocino to use 0x13 for LP5x memory type
...
Mendocino supports LP5x but currently doesn't support SPDs that use the
LP5x memory type, 0x15. This commit updates set 1 SPDs, which are
currently only used for mendocino, to use 0x13 for their memory type.
BUG=b:245509394
TEST=Generated SPDs, verified that only set 1 have changed to 0x13
Change-Id: I46606cb5ff871296d0214e1f781c3b22e93d24ea
Signed-off-by: Robert Zieba <robertzieba@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67747
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
2022-09-29 17:12:00 +00:00
Caveh Jalali
c762e231da
util/spd_tools: Update LP5X support for ADL/RPL/MTL
...
This updates the SPD utility and generated SPDs for LP5X to use memory
type code 0x15 (LPDDR5X) instead of 0x13 (LPDDR5). This is done based on
Intel Tech Advisory Doc ID #616599 dated May 2022, page 15.
SPDs were regenerated with:
"util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5"
This only affects the SPDs for 2 memory parts for Intel SoCs and the
only board referencing these is rex.
BUG=b:242765117
TEST=inspected SPD hex dump
Change-Id: Iadb4688f1cb4265dab1dc7c242f0c301d5498b83
Signed-off-by: Caveh Jalali <caveh@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
Reviewed-by: Reka Norman <rekanorman@chromium.org >
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com >
2022-09-07 22:19:21 +00:00
EricKY Cheng
df23c33a54
mb/google/skyrim/var/winterhold: Update Lp5x and Lp5 memory support
...
Update K3KL8L80CM-MGCT, K3KL9L90CM-MGCT,H58G66AK6BX070 support
BRANCH=None
BUG=b:243337816
TEST= SPD add
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com >
Change-Id: I2c370fbd007c22b1f94074d9f16e5bc7c4e04848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Jon Murphy <jpmurphy@google.com >
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com >
2022-08-30 14:52:37 +00:00
Robert Zieba
c4d77128c5
util/spd_tools: Add support for LP5X SPDs
...
This commit adds support for LP5X SPDs. The SPD format is identical to
LP5 except that the memory type is set to 0x15 instead of 0x13. Since
they are essentially the same, LP5/5X parts share the same parts JSON
file and SPD directory. LP5X parts are distinguished by the optional
`lp5x` attribute. This commit also updates two existing LP5X memory
parts with the correct attribute.
BUG=b:242765117
TEST=Generated SPDs, verified that SPDs generated from LP5X parts match
their LP5 counterparts except for memory type byte.
Signed-off-by: Robert Zieba <robertzieba@google.com >
Change-Id: I67df22bc3fd8ea45fe4dad16b8579351eb4d0d8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Caveh Jalali <caveh@chromium.org >
2022-08-25 00:48:46 +00:00
Karthikeyan Ramasubramanian
0b4f49c792
util/spd_tools/spd_gen/lp5: Remove maxSpeed for Sabrina
...
Firmware component that does memory training already limits the memory
controller to train at 5500 Mbps for all memory parts in Sabrina. Hence
removing this interim SPD change to limit the speed.
BUG=b:238074863
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com >
Change-Id: I2bc82c7407a97aac282708c3e0bd56ae99a8fc31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66290
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-08-01 20:30:39 +00:00
Tarun Tuli
59b9d96d62
spd/lp5: Add SPD for Micron MT62F2G32D4DS-026
...
This adds support for Micron MT62F2G32D4DS-026 chips.
BUG=b:240289148
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Signed-off-by: Tarun Tuli <taruntuli@google.com >
Change-Id: I1212506d742178803a7e7bf7e0236d1095f7af9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2022-07-29 15:00:33 +00:00
Roger Wang
Amanda Huang
Subrata Banik
Leo Chou
Kun Liu
Daniel Peng
Stanley Wu
Wisley Chen
Karthikeyan Ramasubramanian
John Su
Jamie Chen
Johnny Li
Frank Wu
EricKY Cheng
Robert Zieba
Caveh Jalali
Tarun Tuli