The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.
This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2a6a4d1eb7e0d0cd32c8690caf3eff340cdb0d8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80124
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Update the new variant templates to refer to the new unified version
of spd_tools:
- Update the comments in mem_parts_used.txt
- Change the placeholder SPD in Makefile.inc to 'placeholder'
BUG=b:191776301
TEST=None
Change-Id: I03265de0d1182da81dd25a2fe6f940a0b82e5fa4
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The chipset devicetree only has the essential PCIe devices enabled that
are needed for the SoC code to work. It also defines aliases for all
PCIe devices that can be used to reference the devices in the mainboard-
specific devicetrees and devicetree overrides. To make the change easier
to review that part will be done in a follow-up patch.
Despite missing in the PPR, device pci 18.7 exists on Picasso.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b7c3fd32579a23539594672593a243172c161c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
* Add comments to mem_parts_used.txt to point out that the order of
the entries matters when assigning IDs, so always add a new part
to the end of the file.
* Update existing mem_parts_used.txt to add the same comment.
* No updates to Zork variants, because they use an optional ID, so
the order actually doesn't matter there.
BUG=b:175898902
TEST=create a new variant of dalboz, trembyle, volteer, waddledee,
or waddledoo, and observe that mem_parts_used.txt has the new
verbiage.
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Iffbd8e69a89b1b7c810c5d25c7a6148d459d8b02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
New util directories have been added with no description.md file.
The description file for supermicro was added at a secondary level,
which doesn't help a user find the util since no path was added. Move
it up to the top level.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I40b4c25dd7706513e96c6b8078a34160f8bb901e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tom Hiller <thrilleratplay@gmail.com>
The template for overridetree.cb includes HeciEnabled, which has
been removed from the CNL config struct, so remove it from the
overridetree.
BUG=b:174360951
TEST=`new_variant_fulltest.sh puff` succeeds
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I87f67c53cc75d9ddd40b4960739180a95de6ecd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Add an empty SPD in SPD_SOURCES when creating a new variant of
hatch, volteer, waddledee, or waddledoo, so that coreboot can build
successfully.
For variants that use spd_tools, add an empty mem_parts_used.txt so
that the developer can add the supported memory parts and regenerate
the Makefile.inc with the correct SPD references.
Add an empty SPD for LPDDR4x for waddledee and waddledoo to use.
BUG=b:169422833
TEST=create a new variant of hatch, volteer, waddledee, and waddledoo.
Observe that each one succeeds.
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I06dfb6103701bf8949180595f1e98fac48bcc585
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
We need at least one SPD in SPD_SOURCES when creating a new variant
of trembyle or dalboz, or else coreboot won't build. Add the empty
DDR4 SPD so that we can build the new variant.
Add an empty mem_parts_used.txt so that the developer can add the
supported memory parts and regenerate spd/Makefile.inc using
spd_tools.
BUG=b:169199396
TEST=create a new variant of dalboz or trembyle and observe that
the build succeeds.
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I764690c76529780186d0a1d156a623821f9d6972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
ACPI tables are generated at runtime for camera components. Remove
the static ASL file.
BUG=b:168755528
TEST=create a new variant of Waddledoo and observe that the build
succeeds.
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: Ie9e3d5856d5e95562df03814ab31e4e79a40a968
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45629
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tyler Wang
Martin Roth
YH Lin
Subrata Banik
Shou-Chieh Hsu
Zhuohao Lee
Reka Norman
Bhanu Prakash Maiya
Felix Held
Paul Fagerburg
Martin Roth
Zheng Bao
Rob Barnes
Sam McNally
Angel Pons
Tim Wawrzynczak