diff --git a/.gitmodules b/.gitmodules index 4fa82999dc..28195b3e5b 100644 --- a/.gitmodules +++ b/.gitmodules @@ -70,3 +70,7 @@ [submodule "3rdparty/open-power-signing-utils"] path = 3rdparty/open-power-signing-utils url = https://review.coreboot.org/open-power-signing-utils.git +[submodule "3rdparty/amd_firmwares"] + path = 3rdparty/amd_firmwares + url = https://github.com/openSIL/amd_firmwares.git + branch = turin_poc diff --git a/3rdparty/amd_firmwares b/3rdparty/amd_firmwares new file mode 160000 index 0000000000..619e402fdc --- /dev/null +++ b/3rdparty/amd_firmwares @@ -0,0 +1 @@ +Subproject commit 619e402fdcac91da293de28386f4508da6140326 diff --git a/src/soc/amd/turin_poc/Kconfig b/src/soc/amd/turin_poc/Kconfig index 8eadb04933..5d63553ddb 100644 --- a/src/soc/amd/turin_poc/Kconfig +++ b/src/soc/amd/turin_poc/Kconfig @@ -169,8 +169,11 @@ config CPU_PT_ROM_MAP_GB menu "PSP Configuration Options" config AMDFW_CONFIG_FILE - string + string "AMD FW configuration file" default "src/soc/amd/turin_poc/fw.cfg" + help + Specify the path the fw.cfg file describing the PSP blobs to be + integrated in the build. config PSP_DISABLE_POSTCODES bool "Disable PSP post codes" @@ -218,6 +221,13 @@ config PSPV2_MBOX_CMD_OFFSET hex default 0x10970 +config PSP_EARLY_VGA_IMAGE + string "PSP Early VGA image file path" + default "" + help + Path to the optional early VGA image to be displayed by PSP before + x86 reset vector. + endmenu config CONSOLE_UART_BASE_ADDRESS diff --git a/src/soc/amd/turin_poc/Makefile.mk b/src/soc/amd/turin_poc/Makefile.mk index 68144574c2..ea28844b86 100644 --- a/src/soc/amd/turin_poc/Makefile.mk +++ b/src/soc/amd/turin_poc/Makefile.mk @@ -29,7 +29,7 @@ CPPFLAGS_common += -I$(src)/soc/amd/turin_poc/acpi CPPFLAGS_common += -I$(src)/soc/amd/turin_poc/include ifeq ($(call int-gt, $(CONFIG_ROM_SIZE) 0x1000000), 1) -CBFSTOOL_ADD_CMD_OPTIONS+= --mmap 0:0xff000000:0x1000000 +CBFSTOOL_ADD_CMD_OPTIONS+= --mmap 0x1000000:0xff000000:0x1000000 endif ifneq ($(call strip_quotes, $(CONFIG_AMDFW_CONFIG_FILE)),) @@ -94,6 +94,10 @@ set-bit=$(call int-shift-left, 1 $(call _toint,$1)) PSP_SOFTFUSE=$(shell A=$(call int-add, \ $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) +ifeq ($(CONFIG_PSP_INIT_ESPI),y) +PSP_SOFTFUSE_BITS += 15 +endif + # # Build the arguments to amdfwtool (order is unimportant). Missing file names # result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. @@ -116,6 +120,11 @@ OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-s OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE), --apob-nv-base) +OPT_EFS_ESPI_CONFIG=$(call add_opt_prefix, $(CONFIG_EFS_ESPI0_CONFIG), --espi0-config) +OPT_EFS_ESPI_CONFIG+=$(call add_opt_prefix, $(CONFIG_EFS_ESPI1_CONFIG), --espi1-config) +OPT_EFS_ESPI_CONFIG+=$(call add_opt_prefix, $(CONFIG_EFS_ESPI0_CONFIG1), --espi0-config1) +OPT_EFS_ESPI_CONFIG+=$(call add_opt_prefix, $(CONFIG_EFS_ESPI1_CONFIG1), --espi1-config1) + OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) @@ -124,10 +133,15 @@ OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) -OPT_UCODE_FILES=$(foreach i, $(shell seq $(words $(amd_microcode_bins))), \ - $(call add_opt_prefix, $(word $(i), $(amd_microcode_bins)), \ +microcode_bins=$(wildcard ${FIRMWARE_LOCATION}/*U?odePatch_BRH_*.bin) +microcode_bins+=$(wildcard ${FIRMWARE_LOCATION}/*U?odePatch_BRHD_*.bin) + +OPT_UCODE_FILES=$(foreach i, $(shell seq $(words $(microcode_bins))), \ + $(call add_opt_prefix, $(word $(i), $(microcode_bins)), \ --instance $(shell printf "%x" $$(($(i)-1))) --ucode)) +OPT_VGA_IMAGE=$(call add_opt_prefix, $(CONFIG_PSP_EARLY_VGA_IMAGE), --early-vga-image) + AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_APOB_ADDR) \ $(OPT_APOB_NV_SIZE) \ @@ -146,6 +160,8 @@ AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_EFS_SPI_READ_MODE) \ $(OPT_EFS_SPI_SPEED) \ $(OPT_EFS_SPI_MICRON_FLAG) \ + $(OPT_EFS_ESPI_CONFIG) \ + $(OPT_VGA_IMAGE) \ --config $(CONFIG_AMDFW_CONFIG_FILE) \ --flashsize $(call strip_quotes, $(CONFIG_ROM_SIZE)) diff --git a/src/soc/amd/turin_poc/fw.cfg b/src/soc/amd/turin_poc/fw.cfg index 11b1ee638e..e22e0d8de2 100644 --- a/src/soc/amd/turin_poc/fw.cfg +++ b/src/soc/amd/turin_poc/fw.cfg @@ -1,54 +1,66 @@ # PSP fw config file -FIRMWARE_LOCATION 3rdparty/amd_blobs/turin/PSP -SOC_NAME Turin +FIRMWARE_LOCATION 3rdparty/amd_firmwares/Firmwares/Turin +SOC_NAME Turin -# type file +# type file # PSP -AMD_PUBKEY_FILE Typex0_0_0_0_AmdPubKey.bin -PSPBTLDR_FILE Typex1_0_0_0_PspBootLoader.bin Lbb -PSPRCVR_FILE Typex3_0_0_0_PspRecBL.bin -PSP_SMUFW1_SUB0_FILE Typex8_0_0_0_Smu.bin -PSP_SMUFW1_SUB1_FILE Typex8_0_0_1_Smu.bin -PSP_SMUFW1_SUB2_FILE Typex8_0_0_2_Smu.bin -PSPSECUREDEBUG_FILE Typex9_0_0_0_DbgKey.bin -PSP_OEM_ABL_KEY_FILE Typexa_0_0_0_OemAblKey.bin -PSP_SMUFW2_SUB0_FILE Typex12_0_0_0_Smu2.bin -PSP_SMUFW2_SUB1_FILE Typex12_0_0_1_Smu2.bin -PSP_SMUFW2_SUB2_FILE Typex12_0_0_2_Smu2.bin Lbb -PSP_SEC_DEBUG_FILE Typex13_0_0_0_PspEarlyUnlock.bin Lbb -PSP_IKEK_FILE Typex21_0_0_0_ikek.bin -PSP_TOKEN_UNLOCK_FILE Typex22_0_0_0_PspTokenUnlockData.bin -PSP_SECG0_FILE Typex24_0_0_0_SecureGasket.bin -PSP_SECG1_FILE Typex24_0_0_1_SecureGasket.bin -PSP_SECG2_FILE Typex24_0_0_2_SecureGasket.bin -PSP_MP5FW_SUB0_FILE Typex2a_0_0_0_Mp5Fw.bin -PSP_MP5FW_SUB1_FILE Typex2a_0_0_1_Mp5Fw.bin -PSP_MP5FW_SUB2_FILE Typex2a_0_0_2_Mp5Fw.bin -PSP_ABL0_FILE Typex30_0_0_0_PspAgesaBL0.bin -SEV_CODE_FILE Typex39_0_0_0_SevCode.bin -SEV_DATA_FILE Typex38_0_0_0_SevData.bin -PSP_DXIOFW_FILE Typex42_0_0_0_DxioFw.bin -UNIFIEDUSB_FILE Typex44_0_0_0_UsbPhyFw.bin -DRTMTA_FILE Typex47_0_0_0_DrtmTa.bin -KEYDBBL_FILE Typex50_0_0_0_PspBlPubKey.bin -SPL_TABLE_FILE Typex55_0_0_0_BLAntiRB.bin Lbb -PSP_MPIOFW_FILE Typex5d_0_0_0_MPIOOffchipFW.bin -PSP_RIB_FILE_SUB0 Typex76_0_0_0_RIB.bin -PSP_MPDMATFFW_FILE Typex8c_0_0_0_MpdmaTfFw.bin -PSP_GMI3PHYFW_FILE Typex91_0_0_0_Gmi3PhyFw.bin -PSP_MPDMAPMFW_FILE Typex92_0_0_0_MpdmaPmFw.bin -AMD_FUSE_CHAIN Dummy Lbb +AMD_PUBKEY_FILE TypeId0x00_AmdPubKey_BRH.tkn +PSPBTLDR_FILE TypeId0x01_PspBl_BRH.sbin +PSPSECUREOS_FILE TypeId0x02_PspOS_BRH.csbin +PSPRCVR_FILE TypeId0x03_PspRecBl_BRH.sbin +PSP_SMUFW1_SUB0_FILE TypeId0x08_SmuFirmware_breithorn.csbin +PSPSECUREDEBUG_FILE TypeId0x09_PspDebugUnlockToken_BRH.stkn +PSP_OEM_ABL_KEY_FILE TypeId0x0A_PspAblPubKey_BRH.stkn +PSP_SEC_DEBUG_FILE TypeId0x13_SduFw_BRH.csbin +PSP_TEEIPKEY_FILE TypeId0x15_IpKeyManagerDriver_BRH.csbin +PSP_SEV_DRIVER_FILE TypeId0x1A_SevDriver_BRH.csbin +PSP_BOOT_DRIVER_FILE TypeId0x1B_BootDriver_BRH.csbin +PSP_SOC_DRIVER_FILE TypeId0x1C_SocDriver_BRH.csbin +PSP_DEBUG_DRIVER_FILE TypeId0x1D_HadDriver_BRH.csbin +PSP_INTERFACE_DRIVER_FILE TypeId0x1F_InterfaceDriver_BRH.csbin +PSP_IKEK_FILE TypeId0x21_PspAmdIkek_BRH.bin +PSP_TOKEN_UNLOCK_FILE TypeId0x22_SecureEmptyToken.bin +PSP_SECG0_FILE TypeId0x24_RegisterAccessPolicy_BRH.csbin +PSP_DRIVERS_FILE TypeId0x28_PspSystemDriver_BRH.csbin +PSP_MP5FW_SUB0_FILE TypeId0x2A_SmuFirmware_breithorn.csbin +PSP_S0I3_FILE TypeId0x2D_AblRt.csbin +PSP_ABL0_FILE TypeId0x30_AgesaBootLoaderU_BRH.csbin +SEV_DATA_FILE TypeId0x38_PspSevEmptyData.bin +PSP_DXIOFW_FILE TypeId0x42_PhyFw_BRH.ecsbin +UNIFIEDUSB_FILE TypeId0x44_USB_PHY_BRH.esbin +SECURE_POLICY_L1_FILE TypeId0x45_RegisterAccessPolicy_BRH.csbin +DRTMTA_FILE TypeId0x47_DRTMDriver_BRH.sbin +KEYDBBL_FILE TypeId0x50_PspKeyDataBase_BRH.sbin +KEYDB_TOS_FILE TypeId0x51_PspTosKeyDataBase_BRH.sbin +SPL_TABLE_FILE TypeId0x55_SPLTable_BRH.sbin +PSP_MPIOFW_FILE TypeId0x5DMpioFw_BRH.csbin +PSP_RAS_DRIVER_FILE TypeId0x64_RasDriver_BRH.csbin +PSP_RAS_TA_FILE TypeId0x65_ta_ras_prod_amdTEE.sbin +PSP_FHP_DRIVER_FILE TypeId0x67_FHPDriver_BRH.csbin +PSP_SPDM_DRIVER_FILE TypeId0x68_SPDMDriver_BRH.csbin +PSP_DPE_DRIVER_FILE TypeId0x69_DPEDriver_BRH.csbin +PSPBTLDR_AB_FILE TypeId0x73_PspBl_BRH.sbin +PSP_RIB_FILE_SUB0 TypeId0x76_DfRib_BRH.csbin +PSP_MPDMATFFW_FILE TypeId0x8C_MPDMATF_BRH.sbin +PSP_GMI3PHYFW_FILE TypeId0x91_GmiPhyFw_BRH.esbin +PSP_MPDMAPMFW_FILE TypeId0x92_Page_BRH.sbin +SRAM_FW_EXT_FILE TypeId0x9D_AspSramFwExt_BRH.sbin +PSP_TOS_WHITELIST TypeId0x9F_psp_tos_wl_bin_brh.sbin +CPU_S3_IMAGE_INS3 TypeId0xA0_S3Image_BRH.sbin +AMD_FUSE_CHAIN Dummy Lbb # BDT -PSP_PMUI_FILE_SUB0_INS3 Typex64_0_3_0_PmuCode.bin -PSP_PMUI_FILE_SUB0_INS4 Typex64_0_4_0_PmuCode.bin -PSP_PMUI_FILE_SUB0_INS9 Typex64_0_9_0_PmuCode.bin -PSP_PMUI_FILE_SUB0_INSA Typex64_0_a_0_PmuCode.bin -PSP_PMUI_FILE_SUB0_INSB Typex64_0_b_0_PmuCode.bin -PSP_PMUD_FILE_SUB0_INS3 Typex65_0_3_0_PmuData.bin -PSP_PMUD_FILE_SUB0_INS4 Typex65_0_4_0_PmuData.bin -PSP_PMUD_FILE_SUB0_INS9 Typex65_0_9_0_PmuData.bin -PSP_PMUD_FILE_SUB0_INSA Typex65_0_a_0_PmuData.bin -PSP_PMUD_FILE_SUB0_INSB Typex65_0_b_0_PmuData.bin -PSP_PMUD_FILE_SUB0_INSC Typex65_0_c_0_PmuData.bin -# TODO: Typex69_0_0_0_EarlyVgaImage.bin +PSP_PMUI_FILE_SUB0_INS3 Type0x64_AppbDdr5RdimmImem3_BRH.ecsbin +PSP_PMUI_FILE_SUB4_INS3 Type0x64_AppbDdr5RdimmImem3_BRH_C0.ecsbin +PSP_PMUI_FILE_SUB0_INS4 Type0x64_AppbDdr5RdimmImem4_BRH.ecsbin +PSP_PMUI_FILE_SUB4_INS4 Type0x64_AppbDdr5RdimmImem4_BRH_C0.ecsbin +PSP_PMUI_FILE_SUB0_INS9 Type0x64_AppbDdr5RdimmPosttrainImem9_BRH.ecsbin +PSP_PMUI_FILE_SUB0_INSA Type0x64_AppbDdr5RdimmPosttrainImem10_BRH.ecsbin +PSP_PMUD_FILE_SUB0_INS3 Type0x65_AppbDdr5RdimmDmem3_BRH.ecsbin +PSP_PMUD_FILE_SUB4_INS3 Type0x65_AppbDdr5RdimmDmem3_BRH_C0.ecsbin +PSP_PMUD_FILE_SUB0_INS4 Type0x65_AppbDdr5RdimmDmem4_BRH.ecsbin +PSP_PMUD_FILE_SUB0_INS9 Type0x65_AppbDdr5RdimmPosttrainDmem9_BRH.ecsbin +PSP_PMUD_FILE_SUB4_INS9 Type0x65_AppbDdr5RdimmPosttrainDmem9_BRH_C0.ecsbin +PSP_PMUD_FILE_SUB0_INSA Type0x65_AppbDdr5RdimmPosttrainDmem10_BRH.ecsbin +PSP_PMUD_FILE_SUB0_INSB Type0x65_AppbDdr5RdimmQuickbootDmem11_BRH.csbin +PSP_PMUD_FILE_SUB0_INSC Type0x65_AppbDdr5RdimmQuickbootDmem12_BRH.csbin