From f6ed696bbc55ba2a8702070e1fc49b2d67bc2a6f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 3 Jun 2026 11:07:38 +0200 Subject: [PATCH] mb/msi/ms7e56/devicetree.cb: Set proper polarity for SIO UART IRQ4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SIO is configured for low level interrupts. Reflect that in eSPI controller configuratio nso that the interrupts in OS work correctly. TEST=Enable serial console in Linux and get login prompt. Upstream-Status: Pending Change-Id: I4de833f3a73157c03d35f1bcdf3b476f3da6721e Signed-off-by: Michał Żygowski --- src/mainboard/msi/ms7e56/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/msi/ms7e56/devicetree.cb b/src/mainboard/msi/ms7e56/devicetree.cb index a59b8d948f..bbb95610d7 100644 --- a/src/mainboard/msi/ms7e56/devicetree.cb +++ b/src/mainboard/msi/ms7e56/devicetree.cb @@ -41,6 +41,7 @@ chip soc/amd/phoenix .oob_ch_en = 1, .flash_ch_en = 1, .irq_mask = 0xffe107, + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(4), }" register "s0ix_enable" = "false"