From f4e4a695fec07fa4392e13da5586fa752a1474e0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 27 Apr 2021 17:47:55 +0200 Subject: [PATCH] TGL RVP modifications MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski Change-Id: I28ba5a05317af39483a188dc40d91f9a235ef9f3 --- src/drivers/intel/fsp2_0/debug.c | 8 +++---- src/drivers/intel/fsp2_0/silicon_init.c | 1 + src/drivers/intel/gma/Kconfig | 6 ++--- src/mainboard/intel/tglrvp/Kconfig | 2 ++ src/mainboard/intel/tglrvp/Makefile.inc | 2 ++ src/mainboard/intel/tglrvp/chromeos.fmd | 9 +++---- src/mainboard/intel/tglrvp/data.vbt | Bin 0 -> 6144 bytes src/mainboard/intel/tglrvp/data2.vbt | Bin 0 -> 6144 bytes src/mainboard/intel/tglrvp/gma-mainboard.ads | 22 ++++++++++++++++++ src/mainboard/intel/tglrvp/mainboard.c | 3 +++ .../intel/tglrvp/romstage_fsp_params.c | 9 +++++-- .../baseboard/include/baseboard/variants.h | 2 +- .../tglrvp/variants/tglrvp_up3/devicetree.cb | 13 ++++++----- .../intel/tglrvp/variants/tglrvp_up3/memory.c | 21 ++++++++--------- .../variants/tglrvp_up3_ddr4/devicetree.cb | 2 +- .../tglrvp/variants/tglrvp_up3_ddr4/memory.c | 20 ++++++++-------- src/soc/intel/common/block/cpu/mp_init.c | 2 +- src/soc/intel/tigerlake/bootblock/bootblock.c | 3 +++ src/soc/intel/tigerlake/fsp_params.c | 15 ++++++++---- src/soc/intel/tigerlake/me.c | 1 + util/autoport/main.go | 2 +- 21 files changed, 95 insertions(+), 48 deletions(-) create mode 100644 src/mainboard/intel/tglrvp/data.vbt create mode 100644 src/mainboard/intel/tglrvp/data2.vbt create mode 100644 src/mainboard/intel/tglrvp/gma-mainboard.ads diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c index 3d66587eb9..6ae56dfe68 100644 --- a/src/drivers/intel/fsp2_0/debug.c +++ b/src/drivers/intel/fsp2_0/debug.c @@ -80,11 +80,11 @@ void fsp_debug_after_silicon_init(uint32_t status) if (CONFIG(DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status); - /* Display the HOBs */ - if (CONFIG(DISPLAY_HOBS)) - fsp_display_hobs(); + // /* Display the HOBs */ + // if (CONFIG(DISPLAY_HOBS)) + // fsp_display_hobs(); - display_mtrrs(); + // display_mtrrs(); } /*----------- diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index a4ffbda4cc..4ab405c367 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -160,6 +160,7 @@ static void do_silicon_init(struct fsp_header *hdr) multi_phase_params.multi_phase_action = GET_NUMBER_OF_PHASES; multi_phase_params.phase_index = 0; multi_phase_params.multi_phase_param_ptr = &multi_phase_get_number; + printk(BIOS_SPEW, "FspMultiPhaseSiInit get phase number\n"); status = multi_phase_si_init(&multi_phase_params); fsps_return_value_handler(FSP_MULTI_PHASE_SI_INIT_GET_NUMBER_OF_PHASES_API, status); diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index b001fd3e4d..6e2e4b317f 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -87,7 +87,7 @@ config GFX_GMA || NORTHBRIDGE_INTEL_HASWELL \ || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE \ || SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE \ - || SOC_INTEL_WHISKEYLAKE || SOC_INTEL_COMETLAKE + || SOC_INTEL_WHISKEYLAKE || SOC_INTEL_COMETLAKE || SOC_INTEL_TIGERLAKE depends on MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID select RAMSTAGE_LIBHWBASE @@ -115,7 +115,7 @@ config GFX_GMA_GENERATION default "Broxton" if SOC_INTEL_APOLLOLAKE default "Skylake" if SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE || \ SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE || \ - SOC_INTEL_COMETLAKE + SOC_INTEL_COMETLAKE || SOC_INTEL_TIGERLAKE default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL default "Ironlake" if NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X @@ -126,7 +126,7 @@ config GFX_GMA_PCH default "Cougar_Point" if NORTHBRIDGE_INTEL_SANDYBRIDGE default "Lynx_Point" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL default "Sunrise_Point" if SOC_INTEL_COMMON_SKYLAKE_BASE - default "Cannon_Point" if SOC_INTEL_CANNONLAKE_BASE + default "Cannon_Point" if SOC_INTEL_CANNONLAKE_BASE || SOC_INTEL_TIGERLAKE default "No_PCH" config GFX_GMA_PANEL_1_PORT diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 208e1d4110..eba959e7e0 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -23,6 +23,8 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_CSE_LITE_SKU select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_SPI_TPM_CR50 + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT select SPI_TPM select INTEL_CAR_NEM diff --git a/src/mainboard/intel/tglrvp/Makefile.inc b/src/mainboard/intel/tglrvp/Makefile.inc index 2ca32f3760..8a25724e72 100644 --- a/src/mainboard/intel/tglrvp/Makefile.inc +++ b/src/mainboard/intel/tglrvp/Makefile.inc @@ -18,6 +18,8 @@ ramstage-y += ec.c ramstage-y += mainboard.c ramstage-y += board_id.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/tglrvp/chromeos.fmd b/src/mainboard/intel/tglrvp/chromeos.fmd index 6433ef745d..7ae11c54b3 100644 --- a/src/mainboard/intel/tglrvp/chromeos.fmd +++ b/src/mainboard/intel/tglrvp/chromeos.fmd @@ -11,16 +11,17 @@ FLASH@0xfe000000 0x2000000 { RW_FWID_A@0x69ffc0 0x40 } RW_MISC@0x6a0000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x20000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 } - RW_ELOG@0x20000 0x4000 - RW_SHARED@0x24000 0x4000 { + RW_ELOG@0x21000 0x4000 + RW_SHARED@0x25000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } - RW_VPD@0x28000 0x2000 + RW_VPD@0x29000 0x1000 RW_NVRAM@0x2a000 0x6000 } SMMSTORE@0x6d0000 0x40000 diff --git a/src/mainboard/intel/tglrvp/data.vbt b/src/mainboard/intel/tglrvp/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..4e50f1db5c28e91e68f1cd4f13da3e3ab98d2e54 GIT binary patch literal 6144 zcmY!ha|%%i@pN|$@^SQbRRDt&1_K5kvAYZg44A;l(?2-g#WBP&-pR+`*<0Z$gBXLf z*uPf{3@MC^l01e628Nz_C8;?YL7ED_`AL~MsroLd#n~nK1quPqo(hi1$*DQ1MTsS; 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+with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + LVDS, + eDP); + +end GMA.Mainboard; diff --git a/src/mainboard/intel/tglrvp/mainboard.c b/src/mainboard/intel/tglrvp/mainboard.c index 82877ed28e..d96e7daa94 100644 --- a/src/mainboard/intel/tglrvp/mainboard.c +++ b/src/mainboard/intel/tglrvp/mainboard.c @@ -8,6 +8,7 @@ #include #include #include +//#include const char *smbios_system_sku(void) { @@ -27,6 +28,8 @@ static void mainboard_init(void *chip_info) gpio_configure_pads(pads, num); mainboard_ec_init(); + + //do_global_reset(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c index 70e4567af8..6df1788a8d 100644 --- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -11,10 +11,15 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + mem_cfg->DciUsb3TypecUfpDbg = 0; + mem_cfg->VtdItbtEnable = 0; + mem_cfg->UsbTcPortEnPreMem = 0; + + const struct ddr_memory_cfg *mem_config = variant_memory_params(); - const struct spd_info *spd_info = variant_spd_info(); + const struct spd_info spd_info = variant_spd_info(); bool half_populated = false; - meminit_ddr(mem_cfg, mem_config, spd_info, half_populated); + meminit_ddr(mem_cfg, mem_config, &spd_info, half_populated); } diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h index ee8e7aa7cc..6be56154e9 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h @@ -16,6 +16,6 @@ const struct cros_gpio *variant_cros_gpios(size_t *num); size_t variant_memory_sku(void); const struct ddr_memory_cfg *variant_memory_params(void); -const struct spd_info *variant_spd_info(void); +const struct spd_info variant_spd_info(void); #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index c39d063edc..12b17fd3c5 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -116,6 +116,7 @@ chip soc/intel/tigerlake register "TcssAuxOri" = "0" register "TcssD3HotDisable" = "1" register "TcssD3ColdDisable" = "1" + register "UsbTcPortEn" = "0" # Enable S0ix register "s0ix_enable" = "1" @@ -201,17 +202,17 @@ chip soc/intel/tigerlake device pci 05.0 on end # IPU 0x9A19 device pci 06.0 on end # PEG60 0x9A09 - device pci 07.0 on end # TBT_PCIe0 0x9A23 - device pci 07.1 on end # TBT_PCIe1 0x9A25 - device pci 07.2 on end # TBT_PCIe2 0x9A27 - device pci 07.3 on end # TBT_PCIe3 0x9A29 + device pci 07.0 off end # TBT_PCIe0 0x9A23 + device pci 07.1 off end # TBT_PCIe1 0x9A25 + device pci 07.2 off end # TBT_PCIe2 0x9A27 + device pci 07.3 off end # TBT_PCIe3 0x9A29 device pci 08.0 off end # GNA 0x9A11 device pci 09.0 off end # NPK 0x9A33 device pci 0a.0 off end # Crash-log SRAM 0x9A0D device pci 0d.0 on end # USB xHCI 0x9A13 device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 - device pci 0d.2 on end # TBT DMA0 0x9A1B - device pci 0d.3 on end # TBT DMA1 0x9A1D + device pci 0d.2 off end # TBT DMA0 0x9A1B + device pci 0d.3 off end # TBT DMA1 0x9A1D device pci 0e.0 off end # VMD 0x9A0B # From PCH EDS(576591) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c index bc36de19c0..3b6fa8744d 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c @@ -6,7 +6,7 @@ #include #include -#include "spd/spd.h" +#include "../../spd/spd.h" size_t __weak variant_memory_sku(void) @@ -96,7 +96,7 @@ static uintptr_t mainboard_get_spd_index(void) } static const struct ddr_memory_cfg board_mem_config = { - .mem_type = MEMTYPE_LPDDR4, + .mem_type = MEMTYPE_LPDDR4X, .lpddr4_cfg = &mem_config, }; @@ -106,14 +106,13 @@ const struct ddr_memory_cfg *__weak variant_memory_params(void) return &board_mem_config; } -static struct spd_info spd_info = { - .topology = MEMORY_DOWN, - .md_spd_loc = SPD_CBFS, -}; - - -const struct spd_info *__weak variant_spd_info(void) +const struct spd_info __weak variant_spd_info(void) { - spd_info.cbfs_index = mainboard_get_spd_index(); - return (const struct spd_info *)&spd_info; + const struct spd_info spd_info = { + .topology = MEMORY_DOWN, + .md_spd_loc = SPD_CBFS, + .cbfs_index = mainboard_get_spd_index(), + }; + + return spd_info; } \ No newline at end of file diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3_ddr4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3_ddr4/devicetree.cb index c39d063edc..aa4f0315ff 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3_ddr4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3_ddr4/devicetree.cb @@ -16,7 +16,7 @@ chip soc/intel/tigerlake register "HeciEnabled" = "1" # FSP configuration - register "SaGv" = "SaGv_Enabled" + register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3_ddr4/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3_ddr4/memory.c index 8ad719dbf9..69f6734a20 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3_ddr4/memory.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3_ddr4/memory.c @@ -25,15 +25,15 @@ const struct ddr_memory_cfg *__weak variant_memory_params(void) return &board_mem_config; } -static const struct spd_info spd_info = { - .topology = SODIMM, - .smbus_info[0] = {.addr_dimm0 = 0x50, - .addr_dimm1 = 0 }, - .smbus_info[1] = {.addr_dimm0 = 0x52, - .addr_dimm1 = 0 }, -}; - -const struct spd_info *__weak variant_spd_info(void) +const struct spd_info __weak variant_spd_info(void) { - return &spd_info; + const struct spd_info spd_info = { + .topology = SODIMM, + .smbus_info[0] = {.addr_dimm0 = 0x50, + .addr_dimm1 = 0 }, + .smbus_info[1] = {.addr_dimm0 = 0x52, + .addr_dimm1 = 0 }, + }; + + return spd_info; } \ No newline at end of file diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index c3fe40bc18..cfc854f0b3 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -30,8 +30,8 @@ __weak void soc_init_cpus(struct bus *cpu_bus) static void init_one_cpu(struct device *dev) { + intel_microcode_load_unlocked(intel_microcode_find()); soc_core_init(dev); - intel_microcode_load_unlocked(microcode_patch); } static struct device_operations cpu_dev_ops = { diff --git a/src/soc/intel/tigerlake/bootblock/bootblock.c b/src/soc/intel/tigerlake/bootblock/bootblock.c index 96e6268f74..acae51fbdf 100644 --- a/src/soc/intel/tigerlake/bootblock/bootblock.c +++ b/src/soc/intel/tigerlake/bootblock/bootblock.c @@ -5,6 +5,8 @@ #include #include #include +#include +#include asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { @@ -29,4 +31,5 @@ void bootblock_soc_init(void) /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); + intel_update_microcode_from_cbfs(); } diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 8032865789..b557ee32d1 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -89,6 +89,11 @@ __weak void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config * /* Override settings per board. */ } +int soc_fsp_multi_phase_init_is_enable(void) +{ + return 0; +} + /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { @@ -164,8 +169,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) else params->Usb2OverCurrentPin[i] = 0xff; - if (config->usb2_ports[i].type_c) - params->PortResetMessageEnable[i] = 1; + //if (config->usb2_ports[i].type_c) + // params->PortResetMessageEnable[i] = 1; } for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { @@ -351,7 +356,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchFivrExtVnnRailSxVoltage = (config->ext_fivr_settings.vnn_sx_voltage_mv * 10) / 25; - params->PchFivrExtV1p05RailIccMaximum = + params->PchFivrExtV1p05RailIccMax = config->ext_fivr_settings.v1p05_icc_max_ma; } @@ -373,11 +378,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) config->PchPmPwrCycDur); /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ - params->EnableMultiPhaseSiliconInit = 1; + // params->EnableMultiPhaseSiliconInit = 1; /* Disable C1 C-state Demotion */ params->C1StateAutoDemotion = 0; + params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER); + mainboard_silicon_init_params(params); } diff --git a/src/soc/intel/tigerlake/me.c b/src/soc/intel/tigerlake/me.c index da1a2992e6..9de1c539d9 100644 --- a/src/soc/intel/tigerlake/me.c +++ b/src/soc/intel/tigerlake/me.c @@ -165,3 +165,4 @@ static void dump_me_status(void *unused) BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, dump_me_status, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, dump_me_status, NULL); diff --git a/util/autoport/main.go b/util/autoport/main.go index 35e21ab6c1..1d50b7f350 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -880,7 +880,7 @@ use HW.GFX.GMA.Display_Probing; private package GMA.Mainboard is -- FIXME: check this - ports : constant Port_List := + (DP1, DP2, DP3,