mirror of
https://github.com/Dasharo/coreboot.git
synced 2026-06-13 10:16:48 -07:00
broadcom: Remove SoC and board support
The reason for this code cleanup is the legacy Google Purin board which isn't available anymore and AFAIK never made it into the stores. * Remove broadcom cygnus SoC support * Remove /util/broadcom tool * Remove Google Purin mainboard * Remove MAINTAINERS entries Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/29905 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Philipp Deppenwiese
@@ -18,7 +18,6 @@ Technologies, for example the Pistachio SoC. `C`
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`Yacc`
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* __board_status__ - Tools to collect logs and upload them to the board
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status repository `Bash` `Go`
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* __broadcom__ - Generate Broadcom secure boot image. `C`
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* __cavium__ - Devicetree_convert Tool to convert a DTB to a static C
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file `Python`
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* __cbfstool__
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@@ -404,12 +404,10 @@ S: Orphaned
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F: src/cpu/allwinner/
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F: src/cpu/armltd/
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F: src/cpu/ti/
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F: src/soc/broadcom/
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F: src/soc/marvell/
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F: src/soc/qualcomm/
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F: src/soc/samsung/
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F: util/arm_boot_tools/
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F: util/broadcom/
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F: util/exynos/
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F: util/ipqheader/
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+1
-1
@@ -93,7 +93,7 @@ subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
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subdirs-y += src/superio
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subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*)
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subdirs-y += src/cpu src/vendorcode
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subdirs-y += util/cbfstool util/sconfig util/nvramtool util/broadcom
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subdirs-y += util/cbfstool util/sconfig util/nvramtool
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subdirs-y += util/futility util/marvell util/bincfg
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subdirs-y += $(wildcard src/arch/*)
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subdirs-y += src/mainboard/$(MAINBOARDDIR)
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@@ -1,53 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright 2015 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
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||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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if BOARD_GOOGLE_PURIN
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_2048
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select COMMON_CBFS_SPI_WRAPPER
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select MAINBOARD_HAS_CHROMEOS
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select SOC_BROADCOM_CYGNUS
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select SPI_FLASH
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select SPI_FLASH_SPANSION
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select SPI_FLASH_STMICRO # required for the reference board BCM958305K
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select MAINBOARD_HAS_I2C_TPM_GENERIC
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select MAINBOARD_HAS_TPM1
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config VBOOT
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select VBOOT_VBNV_FLASH
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config MAINBOARD_DIR
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string
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default google/purin
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config MAINBOARD_PART_NUMBER
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string
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default "Purin"
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config MAINBOARD_VENDOR
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string
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default "Google"
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config DRAM_SIZE_MB
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int
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default 256
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config GBB_HWID
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string
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depends on CHROMEOS
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default "Purin TEST 1"
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endif # BOARD_GOOGLE_PURIN
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@@ -1,2 +0,0 @@
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config BOARD_GOOGLE_PURIN
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bool "Purin"
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@@ -1,36 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright 2015 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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||||
##
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||||
## This program is distributed in the hope that it will be useful,
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||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||
## GNU General Public License for more details.
|
||||
##
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bootblock-y += bootblock.c
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bootblock-y += boardid.c
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bootblock-y += chromeos.c
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bootblock-y += reset.c
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verstage-y += boardid.c
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verstage-y += chromeos.c
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verstage-y += reset.c
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romstage-y += boardid.c
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romstage-y += chromeos.c
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romstage-y += reset.c
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ramstage-y += boardid.c
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ramstage-y += chromeos.c
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ramstage-y += mainboard.c
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ramstage-y += reset.c
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bootblock-y += memlayout.ld
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verstage-y += memlayout.ld
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romstage-y += memlayout.ld
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ramstage-y += memlayout.ld
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@@ -1,6 +0,0 @@
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Vendor name: Google
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Board name: Purin Broadcom Cygnus reference board
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Category: eval
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@@ -1,21 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
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||||
*
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||||
* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||
* GNU General Public License for more details.
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||||
*/
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#include <boardid.h>
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uint32_t board_id(void)
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{
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return -1;
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}
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@@ -1,20 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 20145Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
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||||
*
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||||
* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||
* GNU General Public License for more details.
|
||||
*/
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||||
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#include <bootblock_common.h>
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void bootblock_mainboard_init(void)
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{
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}
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@@ -1,31 +0,0 @@
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/*
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||||
* This file is part of the coreboot project.
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||||
*
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||||
* Copyright 2015 Google Inc.
|
||||
*
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||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
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||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
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#include <boot/coreboot_tables.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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}
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int get_recovery_mode_switch(void)
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||||
{
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return 0;
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}
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int get_write_protect_state(void)
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{
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return 0;
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}
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@@ -1,32 +0,0 @@
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FLASH@0x0 0x200000 {
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WP_RO@0x0 0x100000 {
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RO_SECTION@0x0 0xf0000 {
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BOOTBLOCK@0 128K
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COREBOOT(CBFS)@0x20000 0x60000
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FMAP@0x80000 0x1000
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GBB@0x81000 0x6ef00
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RO_FRID@0xeff00 0x100
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}
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RO_VPD@0xf0000 0x10000
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}
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RW_SECTION_A@0x100000 0x58000 {
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VBLOCK_A@0x0 0x2000
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FW_MAIN_A(CBFS)@0x2000 0x55f00
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RW_FWID_A@0x57f00 0x100
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}
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RW_SHARED@0x158000 0x4000 {
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SHARED_DATA@0x0 0x4000
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}
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RW_ELOG@0x15c000 0x4000
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RW_GPT@0x160000 0x20000 {
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RW_GPT_PRIMARY@0x0 0x10000
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RW_GPT_SECONDARY@0x10000 0x10000
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}
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RW_SECTION_B@0x180000 0x58000 {
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VBLOCK_B@0x0 0x2000
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FW_MAIN_B(CBFS)@0x2000 0x55f00
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RW_FWID_B@0x57f00 0x100
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}
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RW_VPD@0x1d8000 0x8000
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RW_NVRAM@0x1e0000 0x10000
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}
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@@ -1,19 +0,0 @@
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##
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||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright 2015 Google Inc.
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##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
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# TODO fill with Versatile Express board data in QEMU.
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chip soc/broadcom/cygnus
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device cpu_cluster 0 on end
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end
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@@ -1,42 +0,0 @@
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/*
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* This file is part of the coreboot project.
|
||||
*
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||||
* Copyright 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/device.h>
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||||
#include <boot/coreboot_tables.h>
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#include <symbols.h>
|
||||
|
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static void mainboard_init(struct device *dev)
|
||||
{
|
||||
}
|
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|
||||
static void mainboard_enable(struct device *dev)
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{
|
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dev->ops->init = &mainboard_init;
|
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}
|
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|
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
|
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};
|
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|
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void lb_board(struct lb_header *header)
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{
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struct lb_range *dma;
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|
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dma = (struct lb_range *)lb_new_record(header);
|
||||
dma->tag = LB_TAB_DMA;
|
||||
dma->size = sizeof(*dma);
|
||||
dma->range_start = (uintptr_t)_dma_coherent;
|
||||
dma->range_size = _dma_coherent_size;
|
||||
}
|
||||
@@ -1,14 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <soc/memlayout.ld>
|
||||
@@ -1,20 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <reset.h>
|
||||
|
||||
void do_board_reset(void)
|
||||
{
|
||||
}
|
||||
@@ -1,2 +0,0 @@
|
||||
# Load all chipsets
|
||||
source "src/soc/broadcom/*/Kconfig"
|
||||
@@ -1,81 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright 2014 Google Inc.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
config SOC_BROADCOM_CYGNUS
|
||||
bool
|
||||
default n
|
||||
select ARCH_BOOTBLOCK_ARMV7
|
||||
select ARCH_RAMSTAGE_ARMV7
|
||||
select ARCH_ROMSTAGE_ARMV7
|
||||
select ARCH_VERSTAGE_ARMV7
|
||||
select BOOTBLOCK_CONSOLE
|
||||
select GENERIC_UDELAY
|
||||
select HAVE_MONOTONIC_TIMER
|
||||
select HAVE_UART_SPECIAL
|
||||
select GENERIC_GPIO_LIB
|
||||
|
||||
if SOC_BROADCOM_CYGNUS
|
||||
|
||||
config VBOOT
|
||||
select VBOOT_STARTS_IN_BOOTBLOCK
|
||||
select VBOOT_SEPARATE_VERSTAGE
|
||||
select VBOOT_RETURN_FROM_VERSTAGE
|
||||
|
||||
config CONSOLE_SERIAL_UART_ADDRESS
|
||||
hex
|
||||
depends on DRIVERS_UART
|
||||
default 0x18023000
|
||||
|
||||
config CYGNUS_DDR333
|
||||
def_bool n
|
||||
|
||||
config CYGNUS_DDR400
|
||||
def_bool n
|
||||
|
||||
config CYGNUS_DDR533
|
||||
def_bool n
|
||||
|
||||
config CYGNUS_DDR667
|
||||
def_bool n
|
||||
|
||||
config CYGNUS_DDR800
|
||||
bool "DDR Speed at 800MHz"
|
||||
default y
|
||||
|
||||
config CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE
|
||||
bool "Enable DDR auto self-refresh"
|
||||
default y
|
||||
help
|
||||
Warning: M0 expects that auto self-refresh is enabled. Modify
|
||||
with caution.
|
||||
|
||||
|
||||
config CYGNUS_SHMOO_REUSE_DDR_32BIT
|
||||
bool "Indicate if DDR width is 32-bit"
|
||||
default n
|
||||
|
||||
config CYGNUS_SDRAM_TEST_DDR
|
||||
bool "Run a write-read test on DDR after initialization"
|
||||
default n
|
||||
|
||||
config CYGNUS_PRINT_SHMOO_DEBUG
|
||||
bool "Print debug info for shmoo"
|
||||
default n
|
||||
|
||||
config CYGNUS_GPIO_TEST
|
||||
bool "Run a test on gpio"
|
||||
default n
|
||||
|
||||
endif
|
||||
@@ -1,100 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright 2015 Google Inc.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
ifeq ($(CONFIG_SOC_BROADCOM_CYGNUS),y)
|
||||
|
||||
bootblock-y += bootblock.c
|
||||
bootblock-y += cbmem.c
|
||||
bootblock-y += i2c.c
|
||||
bootblock-y += timer.c
|
||||
bootblock-y += tz.c
|
||||
bootblock-y += hw_init.c
|
||||
bootblock-$(CONFIG_SPI_FLASH) += spi.c
|
||||
ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
|
||||
bootblock-y += ns16550.c
|
||||
endif
|
||||
|
||||
verstage-y += i2c.c
|
||||
verstage-y += timer.c
|
||||
verstage-$(CONFIG_SPI_FLASH) += spi.c
|
||||
verstage-y += ns16550.c
|
||||
|
||||
romstage-y += cbmem.c
|
||||
romstage-y += i2c.c
|
||||
romstage-y += timer.c
|
||||
romstage-y += romstage.c
|
||||
romstage-y += sdram.c
|
||||
romstage-$(CONFIG_SPI_FLASH) += spi.c
|
||||
romstage-y += ns16550.c
|
||||
romstage-y += ddr_init.c
|
||||
romstage-y += ddr_init_table.c
|
||||
romstage-y += shmoo_and28.c
|
||||
romstage-y += phy_reg_access.c
|
||||
romstage-y += ydc_ddr_bist.c
|
||||
romstage-y += timer.c
|
||||
romstage-y += gpio.c
|
||||
romstage-y += iomux.c
|
||||
|
||||
ramstage-y += cbmem.c
|
||||
ramstage-y += i2c.c
|
||||
ramstage-y += sdram.c
|
||||
ramstage-y += soc.c
|
||||
ramstage-y += timer.c
|
||||
ramstage-$(CONFIG_SPI_FLASH) += spi.c
|
||||
ramstage-y += ns16550.c
|
||||
ramstage-y += usb.c
|
||||
|
||||
CPPFLAGS_common += -Isrc/soc/broadcom/cygnus/include/
|
||||
|
||||
ifneq ($(V),1)
|
||||
redirect := > /dev/null
|
||||
endif
|
||||
|
||||
# Options used in the command line:
|
||||
# -out: path of the output file
|
||||
# -config: path to the file containing unauth header
|
||||
# -hmac: path to the file containing hmac for sha256
|
||||
# -bl: boot image file, ie. input file
|
||||
#
|
||||
# Authenticated header parameters:
|
||||
#
|
||||
# SBIConfiguration /* Indicates SBI config */
|
||||
# SYMMETRIC 0x0040
|
||||
#
|
||||
# CustomerID; /* Customer ID */
|
||||
# TYPE bits [31-28]
|
||||
# PRODUCTION 0x6
|
||||
# DEVELOPMENT 0x9
|
||||
# CUSTOMER_ID bits [27-0]
|
||||
#
|
||||
# ProductID; /* Product ID */
|
||||
#
|
||||
# CustomerRevisionID; /* Customer Revision ID */
|
||||
#
|
||||
# SBIUsage /* Boot Image Usage */
|
||||
# NONE 0 /* All purposes */
|
||||
# SLEEP 1
|
||||
# DEEP_SLEEP 2
|
||||
# EXCEPTION 4
|
||||
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin \
|
||||
$(objutil)/broadcom/secimage/secimage \
|
||||
util/broadcom/unauth.cfg \
|
||||
util/broadcom/khmacsha256
|
||||
@printf " SIGN $(subst $(obj)/,,$(@))\n"
|
||||
$(objutil)/broadcom/secimage/secimage -out $@ \
|
||||
-config util/broadcom/unauth.cfg \
|
||||
-hmac util/broadcom/khmacsha256 -bl $<
|
||||
|
||||
endif
|
||||
@@ -1,35 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/cache.h>
|
||||
#include <bootblock_common.h>
|
||||
#include <stddef.h>
|
||||
#include <symbols.h>
|
||||
#include <soc/hw_init.h>
|
||||
|
||||
void bootblock_soc_init(void)
|
||||
{
|
||||
/*
|
||||
* not only for speed but for preventing the CPU from crashing.
|
||||
* the CPU is not happy when cache is cleaned without mmu turned on.
|
||||
*/
|
||||
mmu_init();
|
||||
mmu_config_range(0, 4096, DCACHE_OFF);
|
||||
mmu_config_range_kb((uintptr_t)_sram/KiB, _sram_size/KiB,
|
||||
DCACHE_WRITETHROUGH);
|
||||
dcache_mmu_enable();
|
||||
|
||||
hw_init();
|
||||
}
|
||||
@@ -1,24 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <cbmem.h>
|
||||
#include <stddef.h>
|
||||
#include <symbols.h>
|
||||
#include <soc/sdram.h>
|
||||
|
||||
void *cbmem_top(void)
|
||||
{
|
||||
return _dram + sdram_size_mb()*MiB;
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user